CDCBT1001DPWR [TI]
1.2V 至 1.8V 时钟缓冲器和电平转换器 | DPW | 5 | -40 to 85;
| 型号： | CDCBT1001DPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.2V 至 1.8V 时钟缓冲器和电平转换器 | DPW | 5 | -40 to 85 时钟 转换器 电平转换器 |
| 文件： | 总18页 (文件大小：1201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCBT1001
ZHCSP11 –MAY 2022
CDCBT1001 1.2V 至1.8V 时钟缓冲器和电平转换器
1 特性
3 说明
• 时钟频率范围：DC 到24 MHz
• 1.2V 至1.8V LVCMOS 时钟电平转换：
– VDD_IN = 1.2V ± 10%
– VDD_OUT = 1.8V ± 10%
• 低附加抖动和低相位噪声：
CDCBT1001 是 1.2V 至 1.8V 时钟缓冲器和电平转换
器。VDD_IN 引脚电源电压定义了输入 LVCMOS 时钟
的电平。VDD_OUT 引脚电源电压定义了输出
LVCMOS 时钟的电平。VDD_IN = 1.2V ± 10%。
VDD_OUT = 1.8V ± 10%
– 最大0.8ps 的12kHz 至5MHz 附加RMS 抖动
(fout = 24MHz)
– 发生1kHz 偏移时的最大相位噪声为–
120dBc/Hz (fout = 24MHz)
24MHz 下的 12kHz 至 5MHz 附加 RMS 抖动小于
0.8ps。
器件信息
封装(1)
封装尺寸（标称值）
器件型号
CDCBT1001
– 最大相位本底噪声为–148dBc/Hz（fout
24MHz，foffset ≥1MHz）
=
X2SON (5)
0.80mm × 0.80mm
• 在20% 至80% 条件下具有5ns 的上升/下降时间
• 10ns 传播延迟
• 低电流消耗
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
• 工作温度范围：-40°C 至85°C
2 应用
• 个人电子产品中的FPGA/处理器时钟缓冲/电平转换
• 服务器和附加卡中的1.2V 时钟缓冲器和电平转换器
.
VDD_IN
VDD_OUT
CLK_IN
1
5
4
VDD_IN
CLK_IN
CLK_OUT
3
GND
VDD_OUT
2
CLK_OUT
方框图
Not to scale
引脚配置
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCES945
CDCBT1001
ZHCSP11 –MAY 2022
www.ti.com.cn
Table of Contents
8 Application and Implementation....................................9
8.1 Application Information............................................... 9
8.2 Typical Applications.................................................... 9
9 Power Supply Recommendations................................11
10 Layout...........................................................................11
10.1 Layout Guidelines................................................... 11
10.2 Layout Example...................................................... 11
11 Device and Documentation Support..........................12
11.1 Documentation Support.......................................... 12
11.2 接收文档更新通知................................................... 12
11.3 支持资源..................................................................12
11.4 Trademarks............................................................. 12
11.5 Electrostatic Discharge Caution..............................12
11.6 术语表..................................................................... 12
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description........................................................8
7.1 Overview.....................................................................8
7.2 Functional Block Diagram...........................................8
7.3 Feature Description.....................................................8
7.4 Device Functional Modes............................................8
Information.................................................................... 12
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
May 2022
*
Initial Release
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5 Pin Configuration and Functions
CLK_IN
1
5
4
VDD_IN
3
GND
VDD_OUT
2
CLK_OUT
Not to scale
图5-1. DPW Package 5-Pin X2SON Transparent Top View
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Clock input. LVCMOS input clock is injected into this pin. The acceptable LVCMOS voltage
level is defined by VDD_IN.
CLK_IN
1
I
Clock output. This pin outputs LVCMOS clock. The output LVCMOS voltage level is
defined by VDD_OUT
CLK_OUT
4
O
VDD_IN
VDD_OUT
GND
5
2
3
P
P
G
Input supply voltage. 1.08 V ≤VDD_IN ≤1.32 V.
Output supply voltage. 1.62 V ≤VDD_OUT ≤1.98 V.
Ground
(1) I = Input, O = Output, P = Power, G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
MAX
1.5
UNIT
VDD_IN
VDD_OUT
VI
VDD_IN supply voltage
VDD_OUT supply voltage
Input voltage(2)
V
V
V
2.25
1.5
Voltage applied to the output in the high-impedance or power-off
state(2)
2.25
V
V
–0.5
–0.5
VO
VDD_OUT +
0.2
Voltage applied to the output in the high or low state(2) (3)
IIK
Input clamp current, VI < 0
mA
mA
mA
mA
mA
°C
–50
–50
50
IOK
Output clamp current, VO < 0
Continuous output current
–50
–50
–10
–40
–65
IO
Continuous current through VDD_OUT or GND
Continuous current through VDD_IN
Junction temperature
50
IO
10
TJ
150
150
Tstg
Storage temperature
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 2.25 V maximum if the output current ratings are observed.
6.2 ESD Ratings
VALUE
UNIT
OWNER
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V
V(ESD)
Electrostatic discharge
Charged device model (CDM), per JEDEC
specification JS-002, all pins(2)
±1000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.08
1.62
–40
NOM
MAX
UNIT
V
VDD_IN
VDD_OUT Output supply voltage
TA Ambient temperature
Input supply voltage
1.32
1.98
85
V
°C
6.4 Thermal Information
CDCBT1001
THERMAL METRIC(1)
DPW (X2SON)
5 PINS
462.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
℃/W
℃/W
℃/W
RθJC(top)
RθJB
227.7
326.5
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CDCBT1001
DPW (X2SON)
5 PINS
THERMAL METRIC(1)
UNIT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
33.8
ΨJT
ΨJB
℃/W
℃/W
325.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY CHARACTERISTICS
Both input and output clocks are toggling. 2
pF load termination. f0 = 12 MHz.
35
60
µA
µA
µA
µA
Current consumption on
VDD_IN
IDD_IN
Both input and output clocks are toggling. 2
pF load termination. f0 = 24 MHz.
Both input and output clocks are toggling. 2
pF load termination. f0 = 12 MHz.
500
1000
Current consumption on
IDD_OUT
VDD_OUT
Both input and output clocks are toggling. 2
pF load termination. f0 = 24 MHz.
CLOCK INPUT CHARACTERISTICS
f0
Operating frequency
Input leakage current
DC
24
8
MHz
µA
IIN_LEAK
–8
VDD_IN x
0.8
VIH
VIL
Input voltage high
Input voltage low
V
V
VDD_IN x
0.2
Input edge rate
0.01
V/ns
pF
∆v/∆t
CI
Input capacitance
2
Time after power supply
exceeds 0.5 V before applying
input clock, to ensure glitchless
output
tstartup
225
us
CLOCK OUTPUT CHARACTERISTICS
VDD_OUT
VI = VIH, IOH = -100 µA, VDD_OUT =
1.62-1.98 V
VOH
VOH
VOL
VOL
Output voltage high
Output voltage high
Output voltage low
Output voltage low
V
V
V
V
–0.1
VI = VIH, IOH = -8 mA, VDD_OUT = 1.62 V
1.2
VI = VIL, IOL = 100 µA, VDD_OUT =
1.62-1.98 V
0.1
VI = VIL, IOL = 8 mA, VDD_OUT = 1.62 V
0.45
Input duty cycle = 45% - 55%, input slew
rate ≥0.2 V/ns, VIL ≤0.15 * VDD_IN, VIH
≥0.85 * VDD_IN, VIH - VIL ≥850 mVpp
40
37
60
%
ODC
Output duty cycle
Input duty cycle = 45% - 55%, input slew
rate ≥0.2 V/ns, VIL ≤0.2 * VDD_IN, VIH
≥0.8 * VDD_IN, VIH - VIL ≥850 mVpp
63
3
%
ns
ns
tR, tF
tPD
Clock output rise/fall time
20% to 80%, 2 pF load capacitance
Input slew rate ≥0.2 V/ns, VIL ≤0.2 *
Input-to-output propagation
delay
10
VDD_IN, VIH ≥0.8 * VDD_IN, VIH
VIL ≥850 mVpp
-
Rout
Output impedance
34
Ω
CLOCK OUTPUT PERFORMANCE
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RJRMS-
12 kHz to 5 MHz additive RMS f0 =24 MHz, input slew rate ≥0.2 V/ns, VIH
0.8
ps
random jitter
- VIL ≥850 mVpp
ADD
f0 =24 MHz, input phase noise = -104
dBc/Hz, input slew rate ≥0.2 V/ns, VIH
VIL ≥850 mVpp
PN10
Output phase noise @10 Hz
-
-
-
-
-
-
-
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–100
f0 =24 MHz, input phase noise = -127
dBc/Hz, input slew rate ≥0.2 V/ns, VIH
VIL ≥850 mVpp
PN100
PN1k
Output phase noise @100 Hz
Output phase noise @1 kHz
Output phase noise @10 kHz
–110
–120
–130
–140
–148
–148
f0 =24 MHz, input phase noise = -137
dBc/Hz, input slew rate ≥0.2 V/ns, VIH
VIL ≥850 mVpp
f0 =24 MHz, input phase noise = -159
dBc/Hz, input slew rate ≥0.2 V/ns, VIH
VIL ≥850 mVpp
PN10k
PN100k
PN1M
PN5M
f0 =24 MHz, input phase noise = -164
Output phase noise @100 kHz dBc/Hz, input slew rate ≥0.2 V/ns, VIH
VIL ≥850 mVpp
f0 =24 MHz, input phase noise = -166
dBc/Hz, input slew rate ≥0.2 V/ns, VIH
VIL ≥850 mVpp
Output phase noise @1 MHz
Output phase noise @5 MHz
f0 =24 MHz, input phase noise = -165
dBc/Hz, input slew rate ≥0.2 V/ns, VIH
VIL ≥850 mVpp
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6.6 Typical Characteristics
VDD_IN = 1.2 V, VDD_OUT = 1.8 V, TA = 25 °C,
Input phase noise as specified in Electrical Characteristics table
图6-1. 24-MHz Phase Noise
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7 Detailed Description
7.1 Overview
The CDCBT1001 is a single-channel, 1.2-V to 1.8-V clock buffer and level translator. VDD_IN defines input
LVCMOS clock level and VDD_OUT defines output LVCMOS clock level.
7.2 Functional Block Diagram
VDD_IN
VDD_OUT
CLK_IN
CLK_OUT
7.3 Feature Description
7.3.1 Power Down Tolerant Input
The device can have a clock signal on the input pin when the chip is powered down.
7.3.2 Up Conversion
The device supports 1.2-V to 1.8-V up conversion.
7.4 Device Functional Modes
The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The CDCBT1001 device can be used in level-translation applications for interfacing between devices or systems
that are operating at different interface voltages.
8.2 Typical Applications
8.2.1 Processor Clock Up Translation
图8-1 shows an example of CDCBT1001 being used in a clock level shifting application.
1.2 V
1.8 V
VDD_IN
VDD_OUT
System
Controller
Processor
1.2 V
LVCMOS
Input
1.8 V
LVCMOS
Output
Clock
Clock
图8-1. Processor Clock Up Translation Application
8.2.1.1 Design Requirements
For this design example, use the parameters shown in 表8-1.
表8-1. Design Parameters
DESIGN PARAMETER
Input voltage supply
Output voltage supply
EXAMPLE VALUE
1.2 V
1.8 V
8.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input clock
– The supply voltage on VDD_IN will determine the input clock voltage range.
– For a valid logic-high, the high level clock input must exceed VIH spec. For a valid logic-low, the low level
clock input must be below VIL.
– Some specifications such as duty cycle and phase noise have additional requirements for VIH, VIL, input
swing and input slew rate. Refer to the test conditions column in the Electrical Characteristics table.
• Output clock
– The supply voltage on VDD_OUT will determine the output clock voltage range.
8.2.1.3 Application Curve
图 6-1 listed in the Typical Characteristics section can also be used as an application curve for the Processor
Clock Up Translation application example.
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表8-2. Table of Graphs
TITLE
FIGURE
24-MHz Phase Noise
图6-1
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9 Power Supply Recommendations
TI recommends to place a 0.1-µF bypass capacitor on each VDD pin.
10 Layout
10.1 Layout Guidelines
To ensure reliability of the device, follow the common printed-circuit board layout guidelines listed below:
• Use bypass capacitors on power supplies.
• Use short trace lengths to avoid excessive loading.
图 10-1 shows an example layout for the DPW (X2SON-5) package. This example layout includes two 0402
(metric) capacitors, and uses the measurements listed in the package outline drawing appended to the end of
this data sheet. A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be
used to trace out the center pin connection through another board layer, or the via can be left out of the layout.
10.2 Layout Example
0402
0.1 μF
Bypass
Capacitor
5
4
8 mil
8 mil
1
8 mil
8 mil
3
2
SOLDER MASK
0402
OPENING, TYP
0.1 μF
Bypass
Capacitor
METAL UNDER
SOLDER MASK,
TYP
图10-1. Example Layout for the DPW (X2SON-5) Package
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
• Texas Instruments, Designing and Manufacturing with TI's X2SON Packages application report
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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26-May-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CDCBT1001DPWR
ACTIVE
X2SON
DPW
5
3000 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BT
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
0.85
0.75
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.324)
4X (0.05)
0.25 0.1
2
1
4
5
NOTE 3
2X
3
2X (0.26)
0.48
0.27
0.17
4X
0.239
0.139
0.1
C A B
C
0.288
0.188
3X
0.05
4223102/D 03/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
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EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
(
0.1)
SYMM
4X (0.42)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
SOLDER MASK
OPENING, TYP
4X (0.06)
(
0.25)
(0.21) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/D 03/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.06)
5
1
4X (0.22)
SYMM
(
0.24)
4X (0.26)
(0.21)
(0.48)
TYP
SOLDER MASK
EDGE
3
2
4
(R0.05) TYP
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 3
92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:100X
4223102/D 03/2022
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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