CD74HCT257M [TI]
High Speed CMOS Logic Quad 2-Input Multiplexer with Three-State Non-Inverting Outputs; 高速CMOS逻辑四路2输入多路复用器与三态非反相输出
| 型号： | CD74HCT257M |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Quad 2-Input Multiplexer with Three-State Non-Inverting Outputs |
| 文件： | 总7页 (文件大小：54K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC257,
CD74HCT257
Data sheet acquired from Harris Semiconductor
SCHS171
High Speed CMOS Logic Quad 2-Input
November 1997
Multiplexer with Three-State Non-Inverting Outputs
Features
Description
• Buffered Inputs
The Harris CD74HC257 and CD74HCT257 are quad 2-input
multiplexers which select four bits of data from two sources
under the control of a common Select Input (S). The Output
Enable input (OE) is active LOW. When OE is HIGH, all of
the outputs (1Y-4Y) are in the high impedance state regard-
less of all other input conditions.
• Typical Propagation Delay ( In to Output ) = 12ns at
[ /Title
(CD74
HC257
,
CD74
HCT25
7)
o
V
= 5V, C = 15pF, T = 25 C
CC
L A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Moving data from two groups of registers to four common
output busses is a common use of the 257. The state of the
Select input determines the particular register from which
the data comes. It can also be used as a function generator.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
/Sub-
ject
• Significant Power Reduction Compared to LSTTL
Logic ICs
Ordering Information
• HC Types
- 2V to 6V Operation
(High
Speed
CMOS
Logic
Quad
2-Input
Multi-
plexer
TEMP. RANGE
PKG.
NO.
o
PART NUMBER
CD74HC257E
CD74HCT257E
CD74HC257M
CD74HCT257M
NOTES:
( C)
PACKAGE
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
E16.3
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
E16.3
M16.15
M16.15
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
Pinout
CD74HC257, CD74HC257
(PDIP, SOIC)
TOP VIEW
S
1
2
3
4
5
6
7
8
16 V
CC
1I
15 OE
0
1
1I
14 4I
13 4I
0
1
1Y
2I
2I
12 4Y
0
1
11 3I
10 3I
0
1
2Y
9
3Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1650.1
Copyright © Harris Corporation 1997
1
CD74HC257, CD74HCT257
Functional Diagram
15
OE
1
S
13
4I
1
P
N
12
4Y
14
4I
0
10
11
6
9
7
4
3I
3I
2I
2I
1I
1I
3Y
2Y
1
0
1
0
1
0
3 CIRCUITS IDENTICAL TO CIRCUIT
IN ABOVE DASHED ENCLOSURE
5
3
2
1Y
TRUTH TABLE
OUTPUT
ENABLE
SELECT
INPUT
DATA INPUTS
OUTPUT
OE
H
L
S
X
L
I
I
Y
Z
L
0
1
X
L
X
X
X
L
L
L
H
X
X
H
L
L
H
H
L
H
H
NOTE:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance, OFF State
2
CD74HC257, CD74HCT257
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
160
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±70mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-6
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-7.8
Low Level Output
Voltage
CMOS Loads
V
V
V
or
0.02
0.02
0.02
6
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
7.8
Input Leakage
Current
I
V
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
GND
3
CD74HC257, CD74HCT257
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
Three-State Leakage
Current
I
V
V
or
-
6
-
-
±0.5
-
±5
-
±10
µA
OZ
IL
IH
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
V
IL
High Level Output
Voltage
TTL Loads
-6
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
0.02
6
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆I
V
4.5 to
5.5
100
360
450
CC
CC
-2.1
Three-State Leakage
Current
I
V
V
or
-
5.5
-
-
±0.5
-
±5
-
±10
µA
OZ
IL
IH
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
Data
0.95
3
S
OE
0.6
NOTE: Unit Load is ∆I
Specifications table, e.g., 360µA max at 25 C.
limit specified in DC Electrical
o
CC
4
CD74HC257, CD74HCT257
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
PARAMETER
HC TYPES
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
Propagation Delay
In to Y
t
, t
PLH PHL
C = 50pF
2
-
-
150
30
-
190
38
-
225
45
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
L
4.5
C = 15pF
L
5
6
2
12
-
CL = 50pF
26
175
35
-
33
220
44
-
38
265
53
-
Propagation Delay
S to Y
t , t
PLH PHL
C = 50pF
-
L
4.5
5
-
C = 15pF
L
14
-
CL = 50pF
CL = 50pF
6
30
150
30
-
37
190
38
-
45
225
45
-
Propagation Delay
OE to Y
t
, t
,
2
-
PLZ PHZ
t
, t
PZL PZH
C = 50pF
4.5
5
-
L
C = 15pF
L
12
-
CL = 50pF
6
26
60
12
10
10
20
33
75
15
13
10
20
38
90
18
15
10
20
Output Transition Times
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
-
4.5
6
-
-
C
-
-
-
-
I
Three-State Output
Capacitance
C
-
-
O
Power Dissipation
Capacitance
C
-
5
45
-
-
-
pF
PD
(Notes 5, 6)
HCT TYPES
Propagation Delay
In to Y
t
, t
C = 50pF
4.5
5
-
13
-
33
-
41
-
50
-
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH PHL
L
C = 15pF
L
Propagation Delay
S to Y
t
t
C = 50pF
4.5
5
38
-
48
-
57
-
PZL, PZH
L
C = 15pF
12
-
L
Propagation Delay
OE to Y
t
, t
C = 50pF
4.5
5
30
-
38
-
45
-
PLZ PHZ
L
C = 15pF
16
-
L
Output Transition Times
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
12
10
20
15
10
20
18
10
20
C
-
-
-
I
Three-State Output
Capacitance
C
-
-
O
Power Dissipation
Capacitance
C
-
5
45
-
-
-
pF
PD
(Notes 5, 6)
NOTES:
5. C
is used to determine the dynamic power consumption, per multiplexer.
2
PD
6. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
i
L
5
CD74HC257, CD74HCT257
Test Circuits and Waveforms
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
6
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Copyright 1998, Texas Instruments Incorporated
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