CD74HCT166E [TI]
High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register; 高速CMOS逻辑8位并行输入/串行输出移位寄存器
| 型号： | CD74HCT166E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register |
| 文件： | 总8页 (文件大小：58K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC166,
CD74HCT166
Data sheet acquired from Harris Semiconductor
SCHS157
High Speed CMOS Logic
February 1998
8-Bit Parallel-In/Serial-Out Shift Register
at V
= 5V
Features
CC
• HCT Types
- 4.5V to 5.5V Operation
• Buffered Inputs
o
• Typical f
MAX
= 50MHz at V = 5V, C = 15pF, T = 25 C
CC L A
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
[ /Title
(CD74
HC166
,
CD74
HCT16
6)
• Fanout (Over Temperature Range)
IL
IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
l
OL OH
Ordering Information
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
TEMP. RANGE
PKG.
NO.
o
PART NUMBER
CD74HC166E
CD74HCT166E
CD74HC166M
CD74HCT166M
CD54HC166W
NOTES:
( C)
PACKAGE
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
Wafer
• Significant Power Reduction Compared to LSTTL
Logic ICs
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
E16.3
E16.3
/Sub-
ject
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
M16.15
M16.15
(High
Speed
CMOS
Logic
8-Bit
Paral-
lel-
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
In/Seri
Pinout
CD74HC166, CD74HCT166 (PDIP, SOIC)
TOP VIEW
DS
D0
1
2
3
4
5
6
7
8
16 V
CC
15 PE
14 D7
13 Q7
12 D6
11 D5
10 D4
D1
D2
D3
CE
CP
9
MR
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1501.1
Copyright © Harris Corporation 1998
1
CD74HC166, CD74HCT166
Functional Diagram
D0 D1 D2 D3 D4 D5 D6 D7
PE
PARALLEL ENABLE CIRCUIT
D0
D7
D
8 - REGISTERS
S
Q7
CP
CE
MR
TRUTH TABLE
INPUTS
INTERNAL
Q STATES
PARALLEL
MASTER
RESET
PARALLEL
ENABLE
CLOCK
ENABLE
OUTPUT
Q7
CLOCK
SERIAL
D0 D7
Q0
L
Q1
L
L
X
X
L
X
L
L
L
L
H
X
L
↑
↑
↑
↑
X
X
X
H
L
X
X
L
H
H
H
H
H
Q00
a
Q10
b
Q0
h
a...h
X
H
H
X
H
Q0n
Q0n
Q10
Q6n
Q6n
Q70
X
L
X
X
Q00
NOTES:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
↑ = Transition from Low to High Level
a...h = The level of steady-state input at inputs D0 thru D7, respectively.
Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established.
Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent ↑ transition of the clock.
2
CD74HC166, CD74HCT166
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
160
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-4
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-5.2
Low Level Output
Voltage
CMOS Loads
V
V
V
or
0.02
0.02
0.02
4
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
5.2
Input Leakage
Current
I
V
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
GND
3
CD74HC166, CD74HCT166
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
or
IH
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
V
or
IH
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆I
CC
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
DS, D0-D7
0.2
0.35
0.5
PE
CP, CE
MR
0.2
NOTE: Unit Load is ∆I
Specifications table, e.g., 360µA max at 25 C.
limit specified in DC Electrical
o
CC
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Clock Frequency
(Figure 1)
f
2
6
-
-
-
5
-
-
-
4
-
-
-
MHz
MHz
MHz
MAX
4.5
30
35
25
29
20
23
6
4
CD74HC166, CD74HCT166
Prerequisite For Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
MR Pulse Width
SYMBOL
V
(V)
MIN
100
20
17
80
16
14
80
16
14
1
MAX
MIN
125
25
21
100
20
17
100
20
17
1
MAX
MIN
150
30
26
120
24
20
120
24
20
1
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CC
t
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
w
(Figure 1)
4.5
6
2
Clock Pulse Width
(Figure 1)
t
W
4.5
6
Set-up Time
Data and CE to Clock
(Figure 5)
t
2
SU
4.5
6
Hold Time
Data to Clock
(Figure 5)
t
2
H
4.5
6
1
1
1
1
1
1
Removal Time
MR to Clock
(Figure 5)
t
REM
2
0
0
0
4.5
6
0
0
0
0
0
0
Set-up Time
PE to CP
(Figure 5)
t
2
145
29
25
0
180
36
31
0
220
44
38
0
SU
4.5
6
Hold Time
PE to CP or CE
(Figure 5)
t
2
H
4.5
6
0
0
0
0
0
0
HCT TYPES
Clock Frequency (Figure 2)
f
MAX
4.5
4.5
4.5
4.5
25
35
20
16
-
-
-
-
20
44
25
20
-
-
-
-
16
53
30
24
-
-
-
-
MHz
ns
MR Pulse Width (Figure 2)
Clock Pulse Width (Figure 2)
t
w
w
t
ns
Set-up Time Data and CE to
Clock (Figure 6)
t
ns
SU
Hold Time Data to Clock
(Figure 6)
t
4.5
4.5
0
0
-
-
0
0
-
-
0
0
-
-
ns
ns
H
Removal Time MR to Clock
(Figure 6)
t
REM
Set-up Time PE to CP (Figure 6)
t
4.5
4.5
30
0
-
-
38
0
-
-
45
0
-
-
ns
ns
SU
Hold Time PE to CP or CE
(Figure 6)
t
H
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
PARAMETER
HC TYPES
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
Propagation Delay,
Clock to Output (Figure 3)
t
, t
C = 50pF
2
-
-
160
32
-
200
40
-
240
48
-
ns
ns
ns
ns
PLH PHL
L
4.5
C = 15pF
L
5
6
13
-
CL = 50pF
27
34
41
5
CD74HC166, CD74HCT166
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
PARAMETER
SYMBOL
CONDITIONS
C = 50pF
V
(V)
TYP
MAX
75
15
13
160
32
27
10
-
MAX
95
19
16
200
40
34
10
-
MAX
110
22
UNITS
ns
CC
Output Transition Time
(Figure 3)
t
, t
TLH THL
2
-
-
L
4.5
ns
6
2
-
19
ns
Propagation Delay
MR to Output
(Figure 3)
t
C = 50pF
L
-
240
48
ns
PHL
4.5
6
-
ns
-
41
ns
Input Capacitance
C
-
-
-
-
10
pF
I
Power Dissipation
Capacitance
C
5
41
-
pF
PD
(Notes 5, 6)
HCT TYPES
Propagation Delay,
Clock to Output
(Figure 4)
t
, t
C = 50pF
4.5
-
40
50
60
ns
PLH PHL
L
Output Transition Time
(Figure 4)
t
, t
TLH THL
C = 50pF
4.5
4.5
-
-
-
-
15
40
10
19
50
10
22
60
10
ns
ns
pF
L
Propagation Delay
MR to Output (Figure 4)
t
C = 50pF
L
PHL
Input Capacitance
NOTES:
C
-
I
5. C
6. P
is used to determine the dynamic power consumption, per gate.
PD
2
2
C
V
f + ∑ (C V
+ f ) where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V
= Supply
D = PD CC
i
L
CC
O
i
O
L
CC
Voltage.
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
f
t C
f
L
CL
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
6
CD74HC166, CD74HCT166
Test Circuits and Waveforms (Continued)
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
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