CD74HC221MT [TI]
High-Speed CMOS Logic Dual Monostable Multivibrator with Reset; 高速CMOS逻辑双路单稳多谐振荡器与重置型号: | CD74HC221MT |
厂家: | TEXAS INSTRUMENTS |
描述: | High-Speed CMOS Logic Dual Monostable Multivibrator with Reset |
文件: | 总18页 (文件大小:378K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CD54HC221, CD74HC221,
CD74HCT221
Data sheet acquired from Harris Semiconductor
SCHS166F
High-Speed CMOS Logic
Dual Monostable Multivibrator with Reset
November 1997 - Revised October 2003
Features
Description
• Overriding RESET Terminates Output Pulse
• Triggering from the Leading or Trailing Edge
• Q and Q Buffered Outputs
The ’HC221 and CD74HCT221 are dual monostable
multivibrators with reset. An external resistor (R ) and an
X
[ /Title
(CD74
HC221
,
CD74
HCT22
1)
external capacitor (C ) control the timing and the accuracy
X
for the circuit. Adjustment of R and C provides a wide
X
X
range of output pulse widths from the Q and Q terminals.
Pulse triggering on the B input occurs at a particular voltage
level and is not related to the rise and fall time of the trigger
pulse.
• Separate Resets
• Wide Range of Output-Pulse Widths
• Schmitt Trigger on B Inputs
• Fanout (Over Temperature Range)
Once triggered, the outputs are independent of further trigger
inputs on A and B. The output pulse can be terminated by a
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads LOW level on the Reset (R) pin. Trailing Edge triggering (A)
/Sub-
ject
and leading-edge-triggering (B) inputs are provided for
triggering from either edge of the input pulse. On power up,
the IC is reset. If either Mono is not used each input (on the
unused device) must be terminated either high or low.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
(High
Speed
CMOS
Logic
Dual
Monos
table
Multi-
• Significant Power Reduction Compared to LSTTL
Logic ICs
The minimum value of external resistance, R , is typically 500Ω.
X
• HC Types
The minimum value of external capacitance, C , is 0pF. The
X
calculation for the pulse width is t = 0.7 R C at V = 4.5V.
- 2V to 6V Operation
W
X X
CC
- High Noise Immunity: N = 30%, N = 30% of V
CC
IL
IH
Ordering Information
at V
= 5V
CC
o
PART NUMBER
CD54HC221F3A
CD74HC221E
TEMP. RANGE ( C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
CD74HC221M
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
CD74HC221MT
CD74HC221M96
CD74HC221NSR
CD74HC221PW
CD74HC221PWR
CD74HC221PWT
CD74HCT221E
CD74HCT221M
CD74HCT221MT
CD74HCT221M96
Pinout
CD54HC221
(CERDIP)
CD74HC221
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
(PDIP, SOIC, SOP, TSSOP)
CD74HCT221
(PDIP, SOIC)
TOP VIEW
1A
1B
1R
1Q
2Q
1
2
3
4
5
6
7
8
16 V
CC
15 1C R
X
X
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
14 1C
X
13 1Q
12 2Q
11 2R
10 2B
2C
X
X
2C R
X
9
2A
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC221, CD74HC221, CD74HCT221
Functional Diagram
1C
1R
X
X
V
CC
14
15
1C R
1C
X
X
X
13
4
1A
1Q
1Q
1
2
MONO 1
1B
1R
3
11
2R
2A
5
9
2Q
2Q
MONO 2
12
10
2B
2C
2C R
X
X
X
6
7
V
CC
2C
2R
X
X
TRUTH TABLE
INPUTS
OUTPUTS
A
H
X
L
B
X
L
↑
R
H
H
H
Q
Q
H
H
L
L
↓
H
H
X
L
X
H
L
L
H
↑
(Note 3)
(Note 3)
H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, ↑ = Transition from
↓
Low to High Level, = Transition from High to Low Level,
= One High Level
Pulse,
NOTE:
= One Low Level Pulse
1. For this combination the reset input must be low and the following sequence
must be used: pin 1 (or 9) must be set high or pin 2 (or 10) set low; then pin 1
(or 9) must be low and pin 2 (or 10) set high. Now the reset input goes from low-
to-high and the device will be triggered.
2
CD54HC221, CD74HC221, CD74HCT221
Logic Diagram
V
CC
16
C
P
R
N
X
A
B
R
1 (9)
2 (10)
3 (11)
P
V
CC
P
OP
AMP
R2
R3
R
D
C
RESET
FF
15 (7)
R C
-
+
X
X
Q
C
S
R
V
CC
MIRROR VOLTAGE
QM
QM
P P
C
X
R
Q
MASK
FF
R1
S
MAIN
FF
R4
Q
PULLDOWN
FF
14 (6)
N
V
CC
C
8
X
D
C
C
Q
N
GND
Q
4 (12)
(13) 5
R
Q
Q
+
-
OP AMP
3
CD54HC221, CD74HC221, CD74HCT221
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Package Thermal Impedance, θ (see Note 2):
JA
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
CC
DC Input Diode Current, I
For V < -0.5V or V > V
o
IK
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
o
o
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
(SOIC - Lead Tips Only)
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time, t , t on Inputs A and R
r
f
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Input Rise and Fall Time, t , t on Input B
r
f
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
3.15
-
3.15
-
3.15
4.2
-
0.5
1.35
1.8
-
4.2
-
0.5
1.35
1.8
-
4.2
-
Low Level Input
Voltage
V
-
2
-
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
1.9
4.4
5.9
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
-
5.9
-
5.9
-
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
5.2
-
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
0.1
0.1
0.1
-
0.1
0.1
0.1
-
OL
4.5
6
-
-
Low Level Output
Voltage
TTL Loads
-
-
4
4.5
6
0.26
0.26
0.33
0.33
-
0.4
0.4
5.2
-
4
CD54HC221, CD74HC221, CD74HCT221
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
Input Leakage
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
I
V
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
Current
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 3)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
3. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
All Inputs
UNIT LOADS
0.3
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Prerequisite For Switching Function
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Input Pulse Width
A
t
2
70
14
12
70
14
12
-
-
-
-
-
-
-
-
-
-
-
-
90
18
15
90
18
15
-
-
-
-
-
-
105
21
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
WL
4.5
6
2
18
Input Pulse Width
B
t
105
21
WH
4.5
6
18
5
CD54HC221, CD74HC221, CD74HCT221
Prerequisite For Switching Function (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Input Pulse Width
SYMBOL
V
(V)
MIN
70
14
12
0
TYP
MAX
MIN
90
18
15
0
MAX
MIN
105
21
18
0
MAX
UNITS
ns
CC
t
2
-
-
-
-
-
-
-
-
-
-
WL
Reset
4.5
-
-
-
ns
6
2
-
-
-
ns
Recovery Time
R to A or B
t
-
-
-
ns
SU
4.5
6
0
-
-
0
-
-
0
-
-
ns
0
0
0
ns
Output Pulse Width Q or Q
t
5
630
770
602
798
595
805
µs
W
C
= 0.1µF R = 10kΩ
X
X
Output Pulse Width Q or Q
t
4.5
-
140
-
-
-
-
-
ns
W
C
C
C
= 28pF, R = 2kΩ
X
X
X
X
= 1000pF, R = 2kΩ
t
t
4.5
4.5
-
-
1.5
7
-
-
-
-
-
-
-
-
-
-
µs
µs
X
W
= 1000pF, R = 10kΩ
X
W
HCT TYPES
Input Pulse Width
A
t
4.5
4.5
4.5
4.5
5
14
14
18
0
-
-
18
18
23
0
-
21
21
27
0
-
ns
ns
ns
ns
µs
ns
WL
Input Pulse Width
B
t
-
-
-
-
WH
Input Pulse Width
Reset
t
-
-
-
-
WL
Recovery Time
R to A or B
t
-
-
-
770
-
-
798
-
-
805
-
SU
Output Pulse Width Q or Q
t
630
-
602
-
595
-
W
W
C
= 0.1µF R = 10kΩ
X
X
Output Pulse Width Q or Q
t
4.5
140
C
C
C
= 28pF, R = 2kΩ
X
X
X
X
= 1000pF, R = 2kΩ
t
t
4.5
4.5
-
-
1.5
7
-
-
-
-
-
-
-
-
-
-
µs
µs
X
W
= 1000pF, R = 10kΩ
X
W
Switching Specifications Input t , t = 6ns
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
HC TYPES
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay,
Trigger A, B, R to Q
t
C = 50pF
2
-
-
-
210
42
36
-
-
-
-
-
-
-
-
-
265
53
45
-
-
-
-
-
-
-
-
-
315
63
54
-
ns
ns
ns
ns
ns
ns
ns
ns
PLH
PHL
L
C = 50pF
4.5
6
-
-
-
-
-
-
-
L
C = 50pF
-
L
C = 15pF
5
18
-
L
Propagation Delay,
Trigger A, B, R to Q
t
C = 50pF
2
170
34
29
-
215
43
37
-
255
51
43
-
L
C = 50pF
4.5
6
-
L
C = 50pF
-
L
C = 15pF
5
14
L
6
CD54HC221, CD74HC221, CD74HCT221
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
Propagation Delay,
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
t
C = 50pF
2
-
-
-
160
32
27
180
36
31
75
15
13
10
-
-
-
-
-
-
-
-
-
-
-
-
200
40
34
225
45
38
95
19
16
10
-
-
-
-
-
-
-
-
-
-
-
-
240
48
41
270
54
46
110
22
19
10
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
%
PLH
L
R to Q
4.5
6
-
-
-
-
-
-
-
-
-
-
-
Propagation Delay,
R to Q
t
C = 50pF
2
-
PHL
L
4.5
6
-
-
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
-
4.5
6
-
-
C
-
-
-
-
IN
Pulse Width Match Between
Circuits in the Same Package
4.5 to
5.5
±2
C
= 1000pF, R = 10kΩ
X
X
Power Dissipation Capacitance
(Notes 4, 5)
CPD
-
5
-
166
-
-
-
-
-
pF
HCT TYPES
Propagation Delay,
Trigger A, B, R to Q
t
t
C = 50pF
4.5
5
-
-
-
-
-
-
18
-
42
-
-
-
-
-
-
-
-
-
-
-
-
-
63
-
ns
ns
ns
ns
ns
PLH
L
C = 15pF
L
Propagation Delay,
Trigger A, B, R to Q
C = 50pF
4.5
5
34
-
43
-
51
-
PHL
L
C = 15pF
14
-
L
Propagation Delay,
R to Q
t
t
C = 50pF
4.5
38
-
57
PLH
L
Propagation Delay,
R to Q
C = 50pF
4.5
-
-
37
-
-
-
56
ns
PHL
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
4.5
6
-
-
-
-
-
-
-
75
15
13
10
-
-
-
-
-
-
95
19
16
10
-
-
-
-
-
-
110
22
19
10
-
ns
ns
ns
pF
%
-
C
-
-
-
-
IN
Pulse Width Match Between
Circuits in the Same Package
4.5 to
5.5
±2
C
= 1000pF, R = 10kΩ
X
X
Power Dissipation Capacitance
(Notes 4, 5)
CPD
-
5
-
166
-
-
-
-
-
pF
NOTES:
4. C
is used to determine the dynamic power consumption, per multivibrator.
2
PD
5. P = (C
+ C ) V
CC
f + Σ where f = input frequency, f = output frequency, C = output load capacitance, V
= supply voltage.
CC
D
PD
L
i
i
o
L
7
CD54HC221, CD74HC221, CD74HCT221
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
8
CD54HC221, CD74HC221, CD74HCT221
Typical Performance Curves
685
680
675
R
V
= 10K
= 5V
R
= 10K
o
X
X
T
= 25 C
CC
A
0.9
0.8
HCT
C
= 1µF
X
670
665
0.7
0.6
-75 -50 -25
0
25
50
75 100 125 150 175
o
0
2
4
6
8
10
T , AMBIENT TEMPERATURE ( C)
V
, SUPPLY VOLTAGE (V)
CC
A
FIGURE 5. HC/HCT221 OUTPUT PULSE WIDTH vs
TEMPERATURE
FIGURE 6. HC/HCT221 K FACTOR vs SUPPLY VOLTAGE
6
6
10
10
V
= 4.5V
CC
V
= 2V
CC
5
4
3
2
5
10
10
10
10
10
10
10
10
4
3
2
R
= 100K
R
= 100K
X
X
R
R
= 50K
= 10K
X
R
R
= 50K
= 10K
X
X
10
1
X
10
1
R
= 2K
X
R
= 2K
X
0.1
0.1
2
3
4
5
6
7
8
10
2
3
4
5
6
7
8
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
C , TIMING CAPACITANCE (pF)
C , TIMING CAPACITANCE (pF)
X
X
FIGURE 7. HC221 OUTPUT PULSE WIDTH vs C
FIGURE 8. HC/HCT221 OUTPUT PULSE WIDTH vs C
X
X
9
CD54HC221, CD74HC221, CD74HCT221
10
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
PDIP
Drawing
5962-8780501EA
CD54HC221F
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
16
1
1
None
None
None
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
CD54HC221F3A
CD74HC221E
J
1
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC221M
CD74HC221M96
CD74HC221MT
CD74HC221NSR
CD74HC221PW
CD74HC221PWR
CD74HC221PWT
CD74HCT221E
CD74HCT221M
CD74HCT221M96
CD74HCT221MT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SO
D
D
16
16
16
16
16
16
16
16
16
16
16
40
2500
250
2000
90
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
D
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
NS
PW
PW
PW
N
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
TSSOP
TSSOP
TSSOP
PDIP
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-NC-NC-NC
2000
250
25
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Pb-Free
(RoHS)
SOIC
SOIC
SOIC
D
40
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
D
2500
250
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
D
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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