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CD74HC147NSRG4 [TI]

High-Speed CMOS Logic 10- to 4-Line Priority Encoder; 高速CMOS逻辑10至4线优先编码器
CD74HC147NSRG4
型号： CD74HC147NSRG4
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

High-Speed CMOS Logic 10- to 4-Line Priority Encoder
高速CMOS逻辑10至4线优先编码器

运算电路 逻辑集成电路 光电二极管 编码器
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中文：  中文翻译
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CD54HC147, CD74HC147,  
CD74HCT147  
Data sheet acquired from Harris Semiconductor  
SCHS149F  
High-Speed CMOS Logic  
September 1997 - Revised November 2003  
10- to 4-Line Priority Encoder  
provide binary representation on the four active LOW inputs  
(Y0 to Y3). A priority is assigned to each input so that when  
two or more inputs are simultaneously active, the input with  
the highest priority is represented on the output, with input  
Features  
[ /Title  
(CD74  
HC147  
,
CD74  
HCT14  
7)  
• Buffered Inputs and Outputs  
• Typical Propagation Delay: 13ns at V  
o
= 5V,  
CC  
line l having the highest priority.  
9
C = 15pF, T = 25 C  
L
A
These devices provide the 10-line to 4-line priority encoding  
function by use of the implied decimal “zero”. The “zero” is  
encoded when all nine data inputs are HIGH, forcing all four  
outputs HIGH.  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
/Sub-  
ject  
Ordering Information  
(High  
Speed  
CMOS  
Logic  
10-to-4  
Line  
Prior-  
ity  
Encode  
r)  
TEMP. RANGE  
o
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
PART NUMBER  
CD54HC147F3A  
CD74HC147E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC147M  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
at V  
= 5V  
CC  
CD74HC147MT  
CD74HC147M96  
CD74HC147NSR  
CD74HC147PW  
CD74HC147PWR  
CD74HC147PWT  
CD74HCT147E  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
l
/Autho  
r ()  
Description  
/Key-  
words  
(High  
Speed  
CMOS  
Logic  
10-to-4  
Line  
The ’HC147 and CD74HCT147 are high speed silicon-gate  
CMOS devices and are pin-compatible with low power  
Schottky TTL (LSTTL).  
NOTE: When ordering, use the entire part number. The suffixes  
96 and R denote tape and reel. The suffix T denotes a  
small-quantity reel of 250.  
The ’HC147 and CD74HCT147 9-input priority encoders  
accept data from nine active LOW inputs (l to l ) and  
1
9
Pinout  
Prior-  
ity  
CD54HC147 (CERDIP)  
CD74HC147 (PDIP, SOIC, SOP, TSSOP)  
CD74HCT147 (PDIP, TSSOP)  
TOP VIEW  
Encode  
r, High  
Speed  
CMOS  
Logic  
10-to-4  
Line  
I4  
I5  
1
2
3
4
5
6
7
8
16 V  
CC  
15 NC  
14 Y3  
13 I3  
12 I2  
11 I1  
10 I9  
I6  
I7  
I8  
Y2  
Y1  
GND  
Prior-  
ity  
9
Y0  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD54HC147, CD74HC147, CD74HCT147  
Functional Diagram  
11  
I1  
9
12  
Y0  
I2  
I3  
I4  
I5  
I6  
13  
1
7
Y1  
Y2  
Y3  
2
6
3
4
5
I7  
I8  
I9  
14  
10  
GND = 8  
= 16  
V
CC  
TRUTH TABLE  
INPUTS  
OUTPUTS  
Y2 Y1  
I1  
H
X
X
X
X
X
X
X
X
L
I2  
H
X
X
X
X
X
X
X
L
I3  
H
X
X
X
X
X
X
L
I4  
H
X
X
X
X
X
L
I5  
H
X
X
X
X
L
I6  
H
X
X
X
L
I7  
H
X
X
L
I8  
I9  
H
L
Y3  
H
L
Y0  
H
L
H
X
L
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
L
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
L
H
L
H
H
H = High Logic Level, L = Low Logic Level, X = Don’t Care  
2
CD54HC147, CD74HC147, CD74HCT147  
Absolute Maximum Ratings  
Thermal Information  
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Package Thermal Impedance, θ (see Note 1):  
JA  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W  
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 C/W  
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
CC  
DC Input Diode Current, I  
For V < -0.5V or V > V  
o
IK  
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
OK  
For V < -0.5V or V > V  
I
I
CC  
o
DC Output Diode Current, I  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
o
DC Output Source or Sink Current per Output Pin, I  
O
o
o
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
o
DC V  
or Ground Current, I  
I
. . . . . . . . . . . . . . . . . .±50mA  
CC  
CC or GND  
(SOIC - Lead Tips Only)  
Operating Conditions  
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL  
V (V)  
I
I
(mA)  
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
O
High Level Input  
Voltage  
V
-
-
-
2
4.5  
6
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
3.15  
-
-
3.15  
-
-
3.15  
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
2
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IH IL  
-0.02  
2
1.9  
1.9  
1.9  
OH  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IH IL  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
8
-
80  
-
160  
µA  
CC  
CC  
3
CD54HC147, CD74HC147, CD74HCT147  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
HCT TYPES  
SYMBOL  
V (V)  
I
I
(mA)  
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
O
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
CMOS Loads  
V
V
V
or V  
-0.02  
4.5  
4.5  
4.5  
4.5  
4.4  
4.4  
4.4  
OH  
IH  
IH  
IL  
High Level Output  
Voltage  
TTL Loads  
-4  
3.98  
-
-
-
-
3.84  
-
3.7  
-
V
V
V
Low Level Output  
Voltage  
CMOS Loads  
V
or V  
0.02  
4
-
-
0.1  
0.26  
-
-
0.1  
0.33  
-
-
0.1  
0.4  
OL  
IL  
Low Level Output  
Voltage  
TTL Loads  
Input Leakage  
Current  
I
V
and  
0
0
-
5.5  
5.5  
-
-
-
±0.1  
8
-
-
-
±1  
80  
-
-
-
±1  
µA  
µA  
µA  
I
CC  
GND  
Quiescent Device  
Current  
I
V
or  
-
160  
490  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
∆I  
CC  
(Note 2)  
V
4.5 to  
5.5  
100  
360  
450  
CC  
-2.1  
NOTE:  
2. For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
INPUT  
I , I , I , I , I  
UNIT LOADS  
1.1  
1.5  
1
2
3
6
7
I , I , I , I  
5 8 9  
4
NOTE: Unit Load is ∆I  
360µA max at 25 C.  
limit specified in DC Electrical Table, e.g.,  
CC  
o
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
SYMBOL CONDITIONS  
PARAMETER  
HC TYPES  
V
(V) MIN  
TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
CC  
Propagation Delay,  
Input to Output (Figure 1)  
t
t
C = 50pF  
2
-
-
-
160  
32  
-
-
-
-
-
-
-
-
-
200  
40  
-
-
-
-
-
-
-
-
-
240  
48  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
pF  
PLH, PHL  
L
4.5  
5
-
-
-
-
-
-
-
13  
-
6
27  
75  
15  
13  
10  
34  
95  
19  
16  
10  
41  
110  
22  
19  
10  
Transition Times  
(Figure 1)  
t
, t  
TLH THL  
C = 50pF  
L
2
-
4.5  
6
-
-
Input Capacitance  
C
-
-
-
IN  
4
CD54HC147, CD74HC147, CD74HCT147  
Switching Specifications Input t , t = 6ns (Continued)  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
PARAMETER  
SYMBOL CONDITIONS  
V
(V) MIN  
TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
CC  
Power Dissipation Capaci-  
tance  
C
-
5
-
32  
-
-
-
-
-
pF  
PD  
(Notes 3, 4)  
HCT TYPES  
Propagation Delay,  
Input to Output (Figure 2)  
t
, t  
C = 50pF  
4.5  
5
-
-
-
-
-
-
14  
-
35  
-
-
-
-
-
-
44  
-
-
-
-
-
-
53  
-
ns  
ns  
ns  
pF  
pF  
PLH PHL  
L
Transition Times (Figure 2)  
Input Capacitance  
t
, t  
TLH THL  
C = 50pF  
L
4.5  
-
15  
10  
-
19  
10  
-
22  
10  
-
C
-
-
-
IN  
Power Dissipation Capaci-  
tance  
C
5
42  
PD  
(Notes 3, 4)  
NOTES:  
3. C  
is used to determine the dynamic power consumption, per gate.  
2
PD  
4. P = V  
f (C  
PD  
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.  
CC  
D
CC  
i
L
i
L
Test Circuits and Waveforms  
t = 6ns  
t = 6ns  
f
r
t = 6ns  
f
t = 6ns  
r
V
CC  
3V  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
TLH  
THL  
t
t
THL  
TLH  
90%  
1.3V  
90%  
50%  
10%  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
t
t
PLH  
PLH  
PHL  
PHL  
FIGURE 6. HC AND HCU TRANSITION TIMES AND PROPAGA-  
TION DELAY TIMES, COMBINATION LOGIC  
FIGURE 7. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
5
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-Jun-2007  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CDIP  
PDIP  
Drawing  
8406401EA  
CD54HC147F3A  
CD74HC147E  
ACTIVE  
ACTIVE  
ACTIVE  
J
J
16  
16  
16  
1
1
TBD  
TBD  
A42 SNPB  
A42 SNPB  
N / A for Pkg Type  
N / A for Pkg Type  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD74HC147EE4  
CD74HC147M  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
SOIC  
N
D
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC147M96  
CD74HC147M96E4  
CD74HC147M96G4  
CD74HC147ME4  
CD74HC147MG4  
CD74HC147MT  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC147MTE4  
CD74HC147MTG4  
CD74HC147NSR  
CD74HC147NSRE4  
CD74HC147NSRG4  
CD74HC147PW  
SOIC  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
NS  
NS  
NS  
PW  
PW  
PW  
PW  
PW  
PW  
PW  
PW  
PW  
N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
PDIP  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC147PWE4  
CD74HC147PWG4  
CD74HC147PWR  
CD74HC147PWRE4  
CD74HC147PWRG4  
CD74HC147PWT  
CD74HC147PWTE4  
CD74HC147PWTG4  
CD74HCT147E  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25  
Pb-Free  
CU NIPDAU N / A for Pkg Type  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-Jun-2007  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
(RoHS)  
CD74HCT147EE4  
ACTIVE  
PDIP  
N
16  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Jun-2007  
TAPE AND REEL INFORMATION  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Jun-2007  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
330  
(mm)  
16  
CD74HC147M96  
CD74HC147NSR  
CD74HC147PWR  
D
16  
16  
16  
FMX  
MLA  
MLA  
6.5  
8.2  
7.0  
10.3  
10.5  
5.6  
2.1  
2.5  
1.6  
8
12  
8
16  
16  
12  
Q1  
Q1  
Q1  
NS  
PW  
330  
16  
330  
12  
TAPE AND REEL BOX INFORMATION  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
CD74HC147M96  
CD74HC147NSR  
CD74HC147PWR  
D
16  
16  
16  
FMX  
MLA  
MLA  
342.9  
342.9  
338.1  
336.6  
336.6  
340.5  
28.58  
28.58  
20.64  
NS  
PW  
Pack Materials-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Jun-2007  
Pack Materials-Page 3  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°–8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,  
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.  
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and  
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s  
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this  
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily  
performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
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provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask  
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:  
Products  
Amplifiers  
Data Converters  
DSP  
Applications  
Audio  
amplifier.ti.com  
dataconverter.ti.com  
dsp.ti.com  
www.ti.com/audio  
Automotive  
Broadband  
Digital Control  
Military  
www.ti.com/automotive  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
interface.ti.com  
logic.ti.com  
Logic  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
www.ti-rfid.com  
www.ti.com/lpw  
Telephony  
Low Power  
Wireless  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2007, Texas Instruments Incorporated  

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