CD54HC367F3A [TI]
High-Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting; 高速CMOS逻辑六角缓冲器/线路驱动器，三态非反相和反相
| 型号： | CD54HC367F3A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting |
| 文件： | 总11页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54/74HC367, CD54/74HCT367,
CD54/74HC368, CD74HCT368
Data sheet acquired from Harris Semiconductor
SCHS181D
High-Speed CMOS Logic Hex Buffer/Line Driver,
Three-State Non-Inverting and Inverting
November 1997 - Revised October 2003
Features
Ordering Information
TEMP. RANGE
o
• Buffered Inputs
PART NUMBER
CD54HC367F3A
CD54HC368F3A
CD54HCT367F3A
CD74HC367E
( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
• High Current Bus Driver Outputs
• Two Independent Three-State Enable Controls
[ /Title
(CD74
HC367
,
CD74
HCT36
7,
CD74
HC368
,
CD74
HCT36
8)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• Typical Propagation Delay t
, t
= 8ns at V = 5V,
CC
PLH PHL
o
C = 15pF, T = 25 C
L
A
CD74HC367M
• Fanout (Over Temperature Range)
CD74HC367MT
CD74HC367M96
CD74HC368E
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
CD74HC368M
CD74HC368MT
CD74HC368M96
CD74HCT367E
CD74HCT367M
CD74HCT367MT
CD74HCT367M96
CD74HCT368E
CD74HCT368M
CD74HCT368MT
CD74HCT368M96
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
/Sub-
ject
(High
Speed
- High Noise Immunity: N = 30%, N = 30% of V
CC
IL
IH
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Description
The ’HC367, ’HCT367, ’HC368, and CD74HCT368 silicon gate
CMOS three-state buffers are general purpose high-speed
non-inverting and inverting buffers. They have high drive cur-
rent outputs which enable high speed operation even when
driving large bus capacitances. These circuits possess the low
power dissipation of CMOS circuitry, yet have speeds compara-
ble to low power Schottky TTL circuits. Both circuits are capable
of driving up to 15 low power Schottky inputs.
The ’HC367 and ’HCT367 are non-inverting buffers, whereas
the ’HC368 and CD74HCT368 are inverting buffers. These
devices have two output enables, one enable (OE1) controls 4
gates and the other (OE2) controls the remaining 2 gates.
The ’HCT367 and CD74HCT368 logic families are speed, func-
tion and pin compatible with the standard LS logic family.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
Pinouts
CD54HC367, CD54HCT367
(CERDIP)
CD54HC368
(CERDIP)
CD74HC367, CD74HCT367
(PDIP, SOIC)
CD74HC368, CD74HCT368
(PDIP, SOIC)
TOP VIEW
TOP VIEW
OE1
1A
1
2
3
4
5
6
7
8
16 V
OE1
1A
1
2
3
4
5
6
7
8
16 V
CC
CC
15 OE2
14 6A
13 6Y
12 5A
11 5Y
10 4A
15 OE2
14 6A
13 6Y
12 5A
11 5Y
10 4A
1Y
1Y
2A
2A
2Y
2Y
3A
3A
3Y
3Y
9
4Y
9 4Y
GND
GND
Functional Diagrams
HC367, HCT367
HC368, CD74HCT368
1
1
16
16
V
V
CC
OE1
OE1
CC
15
14
15
14
2
3
2
3
OE2
6A
OE2
6A
1A
1Y
1A
1Y
13
12
13
12
4
4
6Y
5A
6Y
2A
2Y
2A
2Y
3A
5
6
5
6
5A
5Y
4A
11
10
11
10
3A
3Y
5Y
4A
7
8
7
8
3Y
9
9
GND
4Y
GND
4Y
TRUTH TABLE
OUTPUTS
(Y)
INPUTS
OE
L
A
HC/HCT367
HC/HCT368
L
H
X
L
H
H
L
L
H
(Z)
(Z)
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance (OFF) State
2
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
Logic Diagram
V
CC
16
ONE OF SIX IDENTICAL CIRCUITS
2
1A
3
(NOTE 1)
1Y
GND
8
1
OE1
OE2
4
5
2A
3A
4A
5A
6A
15
2Y
3Y
4Y
5Y
6Y
6
7
9
10
12
14
11
13
NOTE:
1. Inverter not included in HC/HCT367
FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT367 AND HC/HCT368 (OUTPUTS FOR HC/HCT367 ARE COMPLEMENTS OF
THOSE SHOWN, i.e., 1Y, 2Y, ETC.)
3
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 2)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
67
73
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
O
CC
(SOIC - Lead Tips Only)
DC V
CC
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-6
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-7.8
Low Level Output
Voltage
CMOS Loads
V
or
0.02
0.02
0.02
6
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
V
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
7.8
Input Leakage
Current
I
V
or
-
6
6
6
-
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
0
160
±10
CC
CC
GND
Three-State Leakage
Current
I
V
or
V =
O
±0.5
±5.0
OZ
IL
V
V
or
IH
CC
GND
4
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HCT TYPES
SYMBOL V (V)
I
(mA)
V (V) MIN TYP MAX
CC
MIN
MAX
MIN
MAX
UNITS
I
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 3)
V
4.5 to
5.5
100
360
450
CC
-2.1
Three-State Leakage
Current
I
V
V
or
V =
O
5.5
-
-
±0.5
-
±5.0
-
±10
µA
OZ
IL
V
or
IH
CC
GND
NOTE:
3. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
OE1
UNIT LOADS
0.6
All Others
0.55
NOTE: Unit Load is ∆I
Specifications table, e.g., 360µA max at 25 C.
limit specified in DC Electrical
o
CC
Switching Specifications Input t , t = 6ns
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
MAX
TEST
PARAMETER
HC TYPES
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
MAX
UNITS
CC
Propagation Delay,
Data to Outputs
HC/HCT367
t
, t
C = 50pF
2
-
-
105
21
18
-
130
26
24
-
160
32
27
-
ns
ns
ns
ns
PLH PHL
L
4.5
6
5
-
C = 15pF
8
L
5
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
PARAMETER
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
105
21
18
-
MAX
130
26
24
-
MAX
160
32
27
-
UNITS
ns
CC
Propagation Delay,
Data to Outputs
HC/HCT368
t , t
PLH PHL
C = 50pF
2
-
-
L
4.5
ns
6
5
2
-
ns
C = 15pF
9
-
ns
L
Propagation Delay,
Output Enable and Disable
to Outputs
t , t
PLH PHL
C = 50pF
150
30
26
-
190
38
33
-
225
45
38
-
ns
L
4.5
6
-
ns
-
ns
C = 15pF
5
12
-
ns
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
60
12
10
10
20
75
15
13
10
20
90
18
15
10
20
ns
4.5
6
-
ns
-
ns
C
-
-
-
-
pF
pF
I
Three-State Output
Capacitance
C
-
-
O
Power Dissipation
Capacitance
C
-
5
40
-
-
-
pF
PD
(Notes 4, 5)
HCT TYPES
Propagation Delay,
Data to Outputs
HC/HCT367
t
t
t
, t
C = 50pF
4.5
5
-
25
-
31
-
38
-
ns
ns
PLH PHL
L
C = 15pF
9
L
Propagation Delay,
Data to Outputs
HC/HCT368
, t
PLH PHL
C = 50pF
4.5
5
-
30
-
38
-
45
-
ns
ns
L
C = 15pF
11
L
Propagation Delay,
Output Enable and Disable
to Outputs
, t
PLH PHL
C = 50pF
4.5
5
-
35
-
44
-
53
-
ns
ns
L
C = 15pF
14
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
-
12
10
20
-
15
10
20
-
18
10
20
-
ns
pF
pF
pF
C
-
-
-
-
-
IN
Three-State Capacitance
C
-
O
Power Dissipation
Capacitance
C
5
42
PD
(Notes 4, 5)
NOTES:
4. C
is used to determine the dynamic power consumption, per buffer.
2
PD
5. P = V
f (C
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
PD
L
i
L
6
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
Test Circuits and Waveforms
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 3. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 4. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 5. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 6. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
7
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