CD54FCT240ATM
更新时间：2024-09-18 06:42:11
品牌：TI
描述：FCT Interface Logic Octal Buffers/Line Drivers, Three-State
概述
规格参数
数据手册CD54FCT240ATM 概述
FCT Interface Logic Octal Buffers/Line Drivers, Three-State FCT接口逻辑八路缓冲器/线路驱动器，三态 总线驱动器/收发器
CD54FCT240ATM 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 包装说明： | SOP, SOP20,.4 | Reach Compliance Code： | not_compliant |
| ECCN代码： | 3A001.A.2.C | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.25 | Is Samacsys： | N |
| 控制类型： | ENABLE LOW | 系列： | FCT |
| JESD-30 代码： | R-PDSO-G20 | 长度： | 12.8 mm |
| 负载电容（CL）： | 50 pF | 逻辑集成电路类型： | BUS DRIVER |
| 位数： | 4 | 功能数量： | 2 |
| 端口数量： | 2 | 端子数量： | 20 |
| 最高工作温度： | 125 °C | 最低工作温度： | -55 °C |
| 输出特性： | 3-STATE | 输出极性： | INVERTED |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装等效代码： | SOP20,.4 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 电源： | 5 V | Prop。Delay @ Nom-Sup： | 6.7 ns |
| 传播延迟（tpd）： | 6.7 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 2.65 mm | 子类别： | Bus Driver/Transceivers |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 4.5 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | YES |
| 技术： | BICMOS | 温度等级： | MILITARY |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 7.5 mm | Base Number Matches： | 1 |
CD54FCT240ATM 数据手册
通过下载CD54FCT240ATM数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载CD74FCT240AT and CD74FCT244AT were not acquired from Harris Semiconductor.
CD54/74FCT240, CD54/74FCT240AT,
CD54/74FCT241, CD54/74FCT244,
Data sheet acquired from Harris Semiconductor
SCHS270A
CD54/74FCT244AT
FCT Interface Logic
Octal Buffers/Line Drivers, Three-State
February 1996
Features
Description
• CD54/74FCT240, CD54/74FCT240AT - Inverting
The CD54/74FCT240, 240AT, 241, 244 and 244AT three-
state octal buffers/line drivers use
a small-geometry
• CD54/74FCT241, CD54/74FCT244, CD54/74FCT244AT -
Non-Inverting
BiCMOS technology. The output stage is a combination of
bipolar and CMOS transistors that limits the output-HIGH
level to two diode drops below VCC. This resultant lowering
of output swing (0V to 3.7V) reduces power bus ringing (a
source of EMI) and minimizes VCC bounce and ground
bounce and their effects during simultaneous output
switching. The output configuration also enhances switching
speed and is capable of sinking 48mA to 64mA.
• Buffered Inputs
• Typical Propagation Delay:
o
4.1ns at VCC = 5V, TA = 25 C (FCT240AT, FCT244AT)
• SCR-Latchup-Resistant BiCMOS Process and Circuit
Design
The CD54/74FCT240, 240AT, 244 and 244AT have active-
LOW output enables (1OE, 2OE). The CD54/74FCT241 and
CD54/74FCT241AT have one active-LOW (1OE) and one
active-HIGH (2OE) output enable.
• FCTXXX Types - Speed of Bipolar FAST®/AS/S;
FCTXXXAT Types - 30% Faster Than FAST/AS/S with
Significantly Reduced Power Consumption
• 48mA to 64mA Output Sink Current (Commer-
cial/Extended Industrial)
Functional Diagram
241, 244 240
• Output Voltage Swing Limited to 3.7V at VCC = 5V
• Controlled Output-Edge Rates
2
4
18
16
14
12
9
1A0
1A1
1A2
1A3
2A0
2A1
2A2
2A3
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
6
8
• Input/Output Isolation to VCC
11
13
15
17
• BiCMOS Technology with Low Quiescent Power
7
5
3
240, 244 241
Ordering Information
1
19
VCC = 20
GND = 10
1OE
1OE
o
PART NUMBER
CD54/74FCT240E
CD54/74FCT240ATE
CD54/74FCT241E
CD54/74FCT244E
CD54/74FCT244ATE
CD54/74FCT240M
CD54/74FCT240ATM
CD54/74FCT241M
CD54/74FCT244M
CD54/74FCT244ATM
CD54/74FCT240SM
CD54/74FCT241SM
CD54/74FCT244SM
CD54FCT240H
TEMP. RANGE ( C)
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125
PACKAGE
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
20 Ld SOIC
20 Ld SOIC
20 Ld SOIC
20 Ld SSOP
20 Ld SSOP
20 Ld SSOP
2OE
2OE
CD54/74FCT240, CD54/74FCT240AT TRUTH TABLE
INPUT
INPUT
OUTPUT
1OE, 20E
A
L
Y
H
L
L
L
H
X
H
Z
CD54/74FCT244, CD54/74FCT244AT TRUTH TABLE
INPUT
INPUT
OUTPUT
1OE, 2OE
A
L
Y
H
L
L
L
H
X
H
Z
CD54/74FCT241 TRUTH TABLE
INPUT
OUTPUT
INPUT
OUTPUT
1OE
1A
L
1Y
L
2OE
L
2A
X
2Y
Z
CD54FCT241H
-55 to 125
L
L
H
H
Z
H
L
L
CD54FCT244H
-55 to 125
H
X
H
H
H
NOTE: H = High Voltage Level, L = LOW Voltage Level
X = Immaterial, Z = HIGH Impedance
FAST® is a registered trademark of Fairchild Semiconductor Corporation.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 2227.3
Copyright © Harris Corporation 1996
1
CD54/74FCT540, CD54/74FCT540AT, CD54/74FCT241, CD54/74FCT244, CD54/74FCT244AT
Switching Specifications FCT Series tr, tf = 2.5ns, C = 50pF, R - See Figure 2
L
L
o
o
o
o
o
o
+25
C
0 C to
-55 C to
+25
C
0 C to
-55 C to
o
o
o
o
+70 C
+125 C
+70 C
+125 C
V
CC
PARAMETER
Propagation Delays
SYMBOL
(V)
TYP MIN MAX MIN MAX TYP MIN MAX MIN MAX UNITS
Data to Outputs
FCT240/AT
t
t
t
t
t
t
t
t
t
,
5†
5
5
4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
8
6.5
6.5
10
8
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
9
7
4.4
-
1.5
-
5.6
-
1.5
-
6.7
-
ns
ns
µs
µs
ns
ns
µs
ns
µs
PLH
t
PHL
FCT241
,
PLH
t
PHL
FCT244/AT
FCT240/AT
FCT241
,
5
4.5
7
7
3.8
4.7
-
1.5
1.5
-
5.3
6.2
-
1.5
1.5
-
6.2
7.7
-
PLH
t
PHL
Output Enable
Times
,
5
10.5
8.5
8.5
10
7.5
7.5
PZL
t
PZH
,
5
5.5
6
PZL
t
PZH
FCT244/AT
FCT240/AT
FCT241
,
5
8
4.8
4
1.5
1.5
-
6.5
5.6
-
1.5
1.5
-
7.8
6.5
-
PZL
t
PZH
Output Disable
Times
,
5
6
9.5
7
PLZ
t
PHZ
,
5
4.5
5
-
PLZ
t
PHZ
FCT244/AT
,
5
7
4.5
1.5
5.8
1.5
6.8
PLZ
t
PHZ
Power Dissipation
Capacitance
FCT240/AT
FCT241
C
§
-
-
38 Typical
33 Typical
35 Typical
38 Typical
-
pF
pF
pF
V
PD
C
§
§
PD
PD
FCT244/AT
During Switch-
C
35 Typical
o
Min. (Valley) V
OHV
ing of Other Outputs (Output Under
Test Not Switching)
V
5
5
0.5 Typical at +25 C
OHV
See
Figure 1
o
Max. (Peak) V
OLP
During Switch-
V
1 Typical at +25 C
V
OLP
ing of Other Outputs (Output Under
Test Not Switching)
See
Figure 1
Input Capacitance
C
-
-
-
-
-
-
10
15
-
-
10
15
-
-
-
-
10
15
-
-
10
15
pF
pF
I
3-State Output Capacitance
† 5V: min. is at 5.5V, max. is at 4.5V.
C
O
o
o
o
o
5V: min. is at 5.25V for 0 C to +70 C, max. is at 4.75V for 0 C to +70 C, typ. is at 5V
2
2
§ C , measured per function, is used to determine the dynamic power consumption. P (per package) = V
I
+ ∑ (V
fi C
+ V
PD CC CC
D
CC
PD O
fo C + V
∆I D) where:
CC CC
L
V
= supply voltage
= flow through current x unit load
CC
∆I
CC
C
= output load capacitance
L
D = duty cycle of input high
fo = output frequency
fi = input frequency
2
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
CD54FCT240ATM 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CD54FCT240ATM96 | RENESAS | FCT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20 | 获取价格 |
|
| CD54FCT240E | TI | FCT Interface Logic Octal Buffers/Line Drivers, Three-State | 获取价格 |
|
| CD54FCT240E | RENESAS | IC,BUFFER/DRIVER,DUAL,4-BIT,FCT/PCT-CMOS,DIP,20PIN,PLASTIC | 获取价格 |
|
| CD54FCT240EN | ETC | Logic IC | 获取价格 |
|
| CD54FCT240F | ETC | Logic IC | 获取价格 |
|
| CD54FCT240H | TI | FCT Interface Logic Octal Buffers/Line Drivers, Three-State | 获取价格 |
|
| CD54FCT240H | RENESAS | IC,BUFFER/DRIVER,DUAL,4-BIT,FCT/PCT-CMOS,DIE | 获取价格 |
|
| CD54FCT240M | TI | FCT Interface Logic Octal Buffers/Line Drivers, Three-State | 获取价格 |
|
| CD54FCT240M96 | RENESAS | IC,BUFFER/DRIVER,DUAL,4-BIT,FCT/PCT-CMOS,SOP,20PIN,PLASTIC | 获取价格 |
|
| CD54FCT240SM | TI | FCT Interface Logic Octal Buffers/Line Drivers, Three-State | 获取价格 |
|
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