CD4053BQM96Q1_技术文档

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ꢀꢌ ꢍ ꢎ ꢏꢐꢏ ꢑꢍ ꢒ ꢌ ꢓꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗꢙꢎ ꢚꢁꢗ ꢌꢓ ꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗ ꢙ ꢎ

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SCHS354 − AUGUST 2004

D

Matched Switching Characteristics,

= 5 Ω (Typ) for V − V = 15 V

Features

r

on

DD

EE

D

Qualification in Accordance With

AEC-Q100

Very Low Quiescent Power Dissipation

Under All Digital-Control Input and Supply

Conditions, 0.2 µW (Typ)

†

D

Qualified for Automotive Applications

D

Customer-Specific Configuration Control

Can Be Supported Along With

Major-Change Approval

at V

− V = V

− V = 10 V

DD

SS

DD EE

D

Binary Address Decoding on Chip

5-V, 10-V, and 15-V Parametric Ratings

100% Tested for Quiescent Current at 20 V

D

Wide Range of Digital and Analog Signal

Levels

− Digital: 3 V to 20 V

Maximum Input Current of 1µA at 18 V Over

Full Package Temperature Range, 100 nA at

18 V and 25°C

Break-Before-Make Switching Eliminates

Channel Overlap

− Analog: 3 20 V

P-P

Low ON Resistance, 125 Ω (Typ) Over

15 V Signal Input Range

D

P-P

for V

− V = 18 V

DD

EE

D

High OFF Resistance, Channel Leakage of

+ 100 pA (Typ) at V − V = 18 V

Applications

DD

EE

Logic-Level Conversion for Digital

Addressing Signals of 3 V to 20 V

D

Analog and Digital Multiplexing and

Demultiplexing

(V

− V = 3 V to 20 V) to Switch Analog

DD

SS

D

Analog-to-Digital (A/D) and

Digital-to-Analog (D/A) Conversion

Signals to 20 V

(V

− V = 20 V)

P-P DD EE

†

Contact factory for details. Q100 qualification data available on

request.

Signal Gating

description/ordering information

The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches that have

low ON impedance and very low OFF leakage current. Control of analog signals up to 20 V can be achieved

P-P

by digital signal amplitudes of 4.5 V to 20 V (If V

− V = 3 V, a V

− V of up to 13 V can be controlled;

DD

SS

DD EE

for V

− V

level differences above 13 V, a V

− V

of at least 4.5 V is required). For example, if

= 4.5 V, V = 0 V, and V = −13.5 V, analog signals from −13.5 V to 4.5 V can be controlled by digital

inputs of 0 V to 5 V. These multiplexer circuits dissipate extremely low quiescent power over the full V

DD

EE

DD

SS

V

DD

SS EE

− V

SS

DD

and V

− V supply-voltage ranges, independent of the logic state of the control signals. When a logic high

DD

EE

(H) is present at the inhibit (INH) input, all channels are off.

ORDERING INFORMATION

ORDERABLE

TOP-SIDE

MARKING

‡

PACKAGE

T

A

PART NUMBER

CD4051BQM96Q1

CD4051BQPWRQ1

SOIC − M

Reel of 2500

Reel of 2000

Reel of 2500

Reel of 2000

Reel of 2500

Reel of 2000

CD4051Q

TSSOP − PW

SOIC − M

CM051BQ

CD4052Q

CD4053Q

§

CD4052BQM96Q1

−40°C to 125°C

§

TSSOP − PW

SOIC − M

CD4052BQPWRQ1

CD4053BQM96Q1

CD4053BQPWRQ1

§

TSSOP − PW

‡

§

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Product Preview

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  2004, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢅ ꢆ ꢇꢈ ꢅꢉ ꢀꢁ ꢂ ꢃꢄ ꢊ ꢆ ꢇꢈꢅ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢋ ꢆ ꢇꢈꢅ

ꢀ ꢌ ꢍꢎ ꢏ ꢐꢏ ꢑ ꢍꢒ ꢌꢓ ꢑꢔꢕ ꢖ ꢑ ꢗꢘ ꢗꢙ ꢎꢚ ꢁ ꢗ ꢌꢓ ꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗꢙꢎ

ꢛꢕ ꢔ ꢜ ꢑ ꢍꢒꢕ ꢀ ꢝꢑ ꢗꢞ ꢗꢑ ꢀꢍ ꢐꢞ ꢗ ꢙꢎ ꢕ ꢍꢐ

SCHS354 − AUGUST 2004

description/ordering information (continued)

The CD4051B is a single eight-channel multiplexer that has three binary control inputs (A, B, and C) and an

inhibit input. The three binary signals select one of eight channels to be turned on and connect one of the eight

inputs to the output.

The CD4052B is a differential four-channel multiplexer that has two binary control inputs (A and B) and an inhibit

input. The two binary input signals select one of four pairs of channels to be turned on and connect the analog

inputs to the outputs.

The CD4053B is a triple two-channel multiplexer with three separate digital control inputs (A, B, and C) and an

inhibit input. Each control input selects one of a pair of channels, which are connected in a single-pole,

double-throw configuration.

When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs, and the

common (COM OUT/IN) terminals are the inputs.

CD4051

M OR PW PACKAGE

(TOP VIEW)

CD4052

M OR PW PACKAGE

(TOP VIEW)

CHANNEL I/O 4

CHANNEL I/O 6

COM OUT/IN

CHANNEL I/O 7

CHANNEL I/O 5

INH

V

Y CHANNEL I/O 0

Y CHANNEL I/O 2

COM Y OUT/IN

Y CHANNEL I/O 3

Y CHANNEL I/O 1

INH

V

DD

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DD

CHANNEL I/O 2

X CHANNEL I/O 2

X CHANNEL I/O 1

COM X OUT/IN

X CHANNEL I/O 0

X CHANNEL I/O 3

A

CHANNEL I/O 1

CHANNEL I/O 0

CHANNEL I/O 3

A

B

C

V

EE

SS

EE

SS

B

CD4053

M OR PW PACKAGE

(TOP VIEW)

IN/OUT by

IN/OUT bx

V

DD

OUT/IN bx or by

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

IN/OUT cy

OUT/IN ax or ay

OUT/IN CX OR CY

IN/OUT CX

INH

IN/OUT ay

IN/OUT ax

A

B

C

V

EE

SS

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀꢌ ꢍ ꢎ ꢏꢐꢏ ꢑꢍ ꢒ ꢌ ꢓꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗꢙꢎ ꢚꢁꢗ ꢌꢓ ꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗ ꢙ ꢎ

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ꢕ

ꢔ

ꢜ

ꢑ

ꢍ

ꢒ

ꢕ

ꢀ

ꢝ

ꢑ

ꢗ

ꢞ

ꢗ

ꢑ

ꢀ

ꢍ

ꢐ

ꢞ

ꢗ

ꢙ

ꢎ

ꢕ

ꢍ

ꢐ

SCHS354 − AUGUST 2004

Function Tables

CD4051

INPUTS

ON

CHANNEL

INH

L

B

L

C

L

A

L

0

L

H

L

1

L

H

L

2

L

H

L

3

L

H

X

4

L

H

L

5

6

L

H

X

L

H

X

7

H

None

X = don’t care

CD4052

INPUTS

ON

CHANNEL

INH

L

B

L

A

L

0x, 0y

1x, 2y

2x, 2y

3x, 3y

None

L

H

L

H

X

L

H

X

H

X = don’t care

CD4053

INPUTS

ON

CHANNEL

INH

L

A OR B OR C

L

H

X

ax or bx or cx

ay or by or cy

None

L

H

X = don’t care

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCHS354 − AUGUST 2004

logic diagram (positive logic)

CD4051B

CHANNEL I/O

7

4

6

2

5

4

1

3

2

1

0

16

12 15 14 13

V

DD

TG

†

11

10

9

A

†

Binary

to

1-of-8

Decoder

With

Inhibit

B

COM

OUT/IN

3

Logic-Level

Conversion

C

6

INH

8

7

V

SS

EE

†

All inputs are protected by CMOS protection network.

CD4052B

X CHANNEL I/O

3

2

1

0

11

15

14

12

TG

16

V

DD

TG

COM X

13

3

OUT/IN

†

10

9

A

Binary

COM Y

OUT/IN

to

Logic-Level

Conversion

†

1-of-4

Decoder

With

B

†

6

INH

Inhibit

1

0

5

1

2

4

3

8

7

V

SS

V

EE

Y CHANNEL I/O

†

All inputs are protected by CMOS protection network.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀꢌ ꢍ ꢎ ꢏꢐꢏ ꢑꢍ ꢒ ꢌ ꢓꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗꢙꢎ ꢚꢁꢗ ꢌꢓ ꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗ ꢙ ꢎ

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SCHS354 − AUGUST 2004

logic diagrams (positive logic) (continued)

CD4053B

IN/OUT

cy cx by bx ay ax

V

DD

16

3

5

1

2

13 12

COM OUT/IN

ac or ay

Binary to

TG

Logic-Level

Conversion

†

1-of-2

Decoders

With

A

11

10

14

Inhibit

COM OUT/IN

bc or by

B

15

COM OUT/IN

xc or xy

†

C

9

6

4

†

INH

V

DD

8

V

SS

V

EE

7

†

All inputs are protected by standard CMOS protection network.

‡

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V+ to V− (voltages referenced to V terminal) . . . . . . . . . . . . . . . . . . . . . −0.5 to 20 V

SS

DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

DD

DC input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA

Package thermal impedance, θ (see Note 1): M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W

JA

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W

Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Lead temperature (during soldering):

J

At distance 1/16 1/32 inch (1,59 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 265°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

ĕ

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢅ ꢆ ꢇꢈ ꢅꢉ ꢀꢁ ꢂ ꢃꢄ ꢊ ꢆ ꢇꢈꢅ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢋ ꢆ ꢇꢈꢅ

ꢀ ꢌ ꢍꢎ ꢏ ꢐꢏ ꢑ ꢍꢒ ꢌꢓ ꢑꢔꢕ ꢖ ꢑ ꢗꢘ ꢗꢙ ꢎꢚ ꢁ ꢗ ꢌꢓ ꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗꢙꢎ

ꢛꢕ ꢔ ꢜ ꢑ ꢍꢒꢕ ꢀ ꢝꢑ ꢗꢞ ꢗꢑ ꢀꢍ ꢐꢞ ꢗ ꢙꢎ ꢕ ꢍꢐ

SCHS354 − AUGUST 2004

recommended operating conditions

MIN

5

MAX

20

UNIT

V

DD

Supply voltage

T

A

Operating free-air temperature

−40

125

°C

electrical characteristics, V

(see Note 2)

= 5 V, A = 1 V, R = 100 Ω, unless otherwise noted

V L

SUPPLY

LIMITS AT INDICATED

TEMPERATURES

V

(V)

DD

PARAMETER

TEST CONDITIONS

UNIT

25°C

125°C

−40°C

MIN

TYP

0.04

0.08

MAX

5

10

150

300

10

15

20

10

Quiescent device

current

I

µA

DD

20

600

20

100

3000

100

Signal Input (V ) and Output (V

)

os

is

5

850

330

210

1300

550

470 1050

Drain-to-source

ON-state resistance

V

= 0 V, V

= 0 to V

= 0 V,

= 0 V

EE

IS

SS

DD

10

15

5

180

125

15

10

5

400

240

r

Ω

on

320

ON-state resistance

difference between

any two switches

10

15

∆r

V

= 0 V, V

SS

on

EE

Any channel OFF (MAX) or all channels

OFF (COM OUT/IN) (Max),

Input/output leakage

current (switch off)

−5

18

5

0.1

1

10

0.1

µA

V

= 0 V, V = 0 V, See Note 3

EE

SS

C

Input capacitance

Output capacitance

V

= −5 V, V

= −5 V

5

30

18

9

pF

is

SS

CD4051

CD4052

CD4053

V

EE

= −5 V, V

5

pF

os

SS

Feedthrough

capacitance

C

V

= −5 V, V

SS

= −5 V

5

0.2

ios

EE

5

30

15

10

60

30

20

Propagation delay

(signal input to

output)

= V , R = 200 kΩ,

DD

IS(p-p)

L

10

15

t

pd

ns

C

= 50 pF, t , t = 20 ns

r f

L

NOTES: 2. Peak-to-peak voltage symmetrical about

V

DD

− V

EE

2

3. Determined by minimum feasible leakage measurement for automatic testing

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀꢌ ꢍ ꢎ ꢏꢐꢏ ꢑꢍ ꢒ ꢌ ꢓꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗꢙꢎ ꢚꢁꢗ ꢌꢓ ꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗ ꢙ ꢎ

ꢛ ꢕꢔ ꢜ ꢑ ꢍꢒ ꢕ ꢀꢝꢑ ꢗꢞꢗ ꢑ ꢀꢍ ꢐꢞ ꢗꢙ ꢎ ꢕꢍ ꢐ

SCHS354 − AUGUST 2004

electrical characteristics, V

(see Note 2) (continued)

= 5 V, A = 1 V, R = 100 Ω, unless otherwise noted

V L

SUPPLY

LIMITS AT INDICATED

TEMPERATURES

V

EE

(V)

V

DD

(V)

PARAMETER

TEST CONDITIONS

UNIT

25°C

125°C

−40°C

MIN

TYP

MAX

Control (Address or Inhibit), V

C

V

5

10

15

5

1.5

3

1.5

3

1.5

3

V

= V

DD

= 1kΩ to V ,

< 2 µA on all OFF channels

through 1kΩ,

SS

IL

IH

L

DD

V

IL

Input low voltage

V

R

I

SS

4

is

3.5

7

3.5

7

3.5

7

V

= V

DD

through 1kΩ,

IL

IH

DD

10

15

18

5

V

Input high voltage

Input current

V

IH

IN

R

I

= 1kΩ to V ,

< 2 µA on all OFF channels

L

SS

11

0.1

11

1

11

is

−5

10

I

V

IN

= 0 V, 18 V

0.1

720

320

240

450

720

320

240

400

450

210

160

300

µA

0

450

160

120

225

400

160

120

200

90

Address-to-signal

OUT (channels ON

t , t = 20 ns, C = 50 pF,

r f

= 10 kΩ, V

L

SS

10

15

5

R

= 0 V,

L

t

ns

pd1

pd2

pd3

or OFF) propagation See Figure 10, Figure 11, and

delay

Figure 14

−5

0

5

Inhibit-to-signal

OUT (channel

turning ON)

t , t = 20 ns, C = 50 pF,

r f

= 1 kΩ, V

L

SS

0

10

15

5

R

= 0 V,

L

0

See Figure 11

propagation delay

−10

0

5

Inhibit-to-signal

OUT (channel

turning OFF)

t , t = 20 ns, C = 50 pF,

r f

L

SS

0

10

15

5

R

= 10 kΩ, V

= 0 V,

ns

L

0

70

See Figure 15

propagation delay

−10

130

Input capacitance,

any address or

inhibit input

C

5

7.5

pF

IN

NOTES: 2: Peak-to-peak voltage symmetrical about

V

DD

− V

EE

2

3: Determined by minimum feasible leakage measurement for automatic testing

7

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SCHS354 − AUGUST 2004

electrical specifications

LIMITS AT

INDICATED

V

(V)

V

DD

(V)

TEMPERATURES

IS

PARAMETER

TEST CONDITIONS

UNIT

25°C

MIN

TYP

30

MAX

CD4053

CD4052

CD4051

5

10

R

= 1 kΩ,

at COM OUT/IN,

L

V

OS

−3-dB cutoff

frequency,

channel ON

(sine-wave input)

10

25

See Note 2,

MHz

20

V

OS

at COM OUT/IN

V

EE

V

OS

= V , 20log V /V = −3 dB,

SS OS IS

at any channel

60

2

3

5

0.3

0.2

0.12

8

R

= 10 kΩ,

L

10

15

Total harmonic

distortion

See Note 2

THD

%

V

EE

= V , f = 1-kHz sine wave

SS is

CD4053

CD4052

CD4051

5

10

R

= 1 kΩ,

at COM OUT/IN,

L

−40-dB

feedthrough

frequency

10

V

OS

See Note 2

MHz

12

V

= V , 20log V /V = −40 dB,

SS OS IS

(all channels OFF)

EE

OS

8

3

6

at any channel

R

= 1 kΩ, between any two channels, See Note 2

5

10

L

V

EE

= V , 20log V /V = −40 dB,

SS OS IS

Between sections, Measured on common

CD4052

V

= V , 20log V /V = −40 dB,

SS OS IS

EE

Between sections,

10

2.5

6

Measured on any channel

−40-dB signal

crosstalk frequency

MHz

V

= V , 20log V /V = −40 dB,

SS OS IS

EE

Between any two sections,

In pin 2, Out pin 14

CD4053

V

= V , 20log V /V = −40 dB,

SS OS IS

EE

Between any two sections,

In pin 15, Out pin 14

R

= 10 kΩ, See Note 4

10

65

L

Address or inhibit

to signal crosstalk

mV

PEAK

V

EE

CC

= 0 V, V

SS

= 0 V, t , t = 20 ns,

r f

V

= V

− V

(square wave)

DD

SS

NOTES: 2. Peak-to-peak voltage symmetrical about

4. Both ends of channel

V

DD

− V

EE

2

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SCHS354 − AUGUST 2004

TYPICAL CHARACTERISTICS

CHANNEL ON-STATE RESISTANCE

vs

INPUT SIGNAL VOLTAGE

Supply Voltage (V

DD

− V ) = 5 V

EE

600

500

400

300

200

300

250

Supply Voltage (V

DD

− V ) = 10 V

EE

T

= 125°C

A

T

= 125°C

A

200

150

25°C

−55°C

25°C

100

−55°C

100

0

50

0

−4

−3

−2

−1

0

1

2

3

4

−10 −7.5 −5 −2.5

0

2.5

5

7.5

10

V

is

− Input Signal Voltage − V

V

is

− Input Signal Voltage − V

92CS-27326RI

92CS-27327RI

Figure 1

Figure 2

CHANNEL ON-STATE RESISTANCE

vs

INPUT SIGNAL VOLTAGE

T

A

= 25°C

Supply Voltage (V

DD

− V ) = 15 V

EE

300

250

300

250

200

150

100

Supply Voltage (V

DD

− V ) = 5 V

EE

200

150

100

T

A

= 125°C

25°C

10 V

15 V

−55°C

50

0

50

0

−10 −7.5 −5 −2.5

0

2.5

5

7.5

10

−10 −7.5 −5 −2.5

0

2.5

5

7.5

10

V

is

− Input Signal Voltage − V

V

is

− Input Signal Voltage − V

92CS-27330RI

92CS-27329RI

Figure 3

Figure 4

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SCHS354 − AUGUST 2004

TYPICAL CHARACTERISTICS

DYNAMIC POWER DISSIPATION

vs

SWITCHING FREQUENCY (CD4051B)

ON CHARACTERISTICS FOR

1-OF-8 CHANNELS (CD4051B)

5

4

6

10

T

= 255 C

Test Circuit

V

DD

A

V

T

= 5 V

= 0 V

= −5 V

DD

SS

EE

R

= 100 kW, R = 10 kW

L

Alternating O

and I Pattern

1 kW

B/D

CD4029

4

2

500 W

100 W

f

C

= 50 pF

L

= 255 C

A

B

C

A

V

DD

100 Ω

V

= 15 V

DD

11 10

9

13

14

15

12

1

5

2

4

3

2

10

0

CD4051

V

= 10 V

DD

−2

3

6

8

7

4

V

= 5 V

C

DD

L

−4

−6

100 Ω

Ι

C

= 15 pF

L

10

2

3

5

10

−6

−4

−2

0

2

4

6

10

1

10

f − Switching Frequency − kHz

V

is

− Input Signal Voltage − V

Figure 5

Figure 6

DYNAMIC POWER DISSIPATION

vs

DYNAMIC POWER DISSIPATION

vs

SWITCHING FREQUENCY (CD4052B)

SWITCHING FREQUENCY (CD4053B)

5

4

5

4

3

10

V = 15 V

DD

T

= 255 C

T = 255 C

A

Alternating ÒOÓ

and ÒIÓ Pattern

Alternating O

and I Pattern

V

= 10 V

DD

Test Circuit

C

= 50 pF

f

C = 50 pF

L

CD4029

B/D

Test Circuit

V

DD

V

= 15 V

DD

f

A

B

100 Ω

9

3

4

C

L

10

9

100 W

1

3

C

L

3

2

12

10

5

2

4

13

12

14

15

11

5

13

2

1

15

14

100 W

CD4053

V

= 10 V

CD4052

DD

10

11

6

7

V

= 5 V

DD

2

V

= 5 V

DD

10

7

8

C

= 15 pF

C

= 15 pF

L

Ι

10

2

10

3

4

5

10

2

3

4

5

10

1

10

1

10

f − Switching Frequency − kHz

Figure 7

Figure 8

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ꢀꢌ ꢍ ꢎ ꢏꢐꢏ ꢑꢍ ꢒ ꢌ ꢓꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗꢙꢎ ꢚꢁꢗ ꢌꢓ ꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗ ꢙ ꢎ

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SCHS354 − AUGUST 2004

PARAMETER MEASUREMENT INFORMATION

V

DD

= 15 V

V

DD

= 7.5 V

V

DD

= 5 V

V

= 5 V

DD

5 V

7.5 V

16

V

SS

= 0 V

V

SS

= 0 V

V

SS

= 0 V

V

= 0 V

EE

7

8

7

8

7

8

7

8

V

EE

= –10 V

V

EE

= –7.5 V

V

EE

= –5 V

V

SS

(D)

(C)

(B)

(A)

NOTE: The A, B, C, and INH input logic levels are L = V

and H = V . The analog signal (through the TG) may swing from V

DD EE

to V .

DD

SS

Figure 9. Typical Bias-Voltage Test Circuits

t = 20 ns

r

t = 20 ns

r

t = 20 ns

f

t = 20 ns

f

90%

50%

90%

50%

90%

50%

90%

50%

10%

Turn-On Time

90%

50%

90%

10%

Turn-Off Time

Turn-On Time

t

PHZ

Figure 10. Channel Turned ON Waveforms

(R = 1 kΩ)

Figure 11. Channel Turned OFF Waveforms

(R = 1 kΩ)

L

11

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SCHS354 − AUGUST 2004

PARAMETER MEASUREMENT INFORMATION

V

DD

V

DD

V

DD

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

1

2

3

4

5

6

7

16

15

14

13

12

11

10

15

14

13

12

11

10

9

I

DD

I

DD

I

DD

₈CD4052

9

CD4053

CD4051

CD4052

Figure 12. OFF Channel Leakage Current, Any Channel OFF

V

DD

V

DD

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

I

DD

I

DD

CD4052

CD4051

CD4053

Figure 13. OFF Channel Leakage Current, All Channels OFF

V

DD

V

DD

Output

1

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

DD

R

2

3

4

5

6

7

8

L

C

L

R

C

L

C

R

L

V

DD

V

DD

V

EE

V

EE

V

DD

SS

V

EE

V

EE

Clock

In

EE

V

SS

DD

Clock

In

V

SS

Clock

In

V

SS

V

SS

V

CD4053

V

SS

V

SS

CD4052

CD4051

Figure 14. Propagation Delay, Address Input to Signal Output

V

DD

Output

V

DD

Output

V

1

16

15

14

13

12

11

10

9

DD

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

2

3

4

5

6

7

8

50 pF

V

R

L

R

50 pF

L

R

L

V

EE

V

EE

V

DD

V

DD

V

DD

V

DD

V

DD

SS

V

EE

V

SS

V

SS

V

Clock

In

SS Clock

In

V

EE

V

SS

V

EE

Clock

In

V

SS

V

t

and t

PLH

SS

PHL

V

SS

V

SS

t

and t

t

and t

PHL

PLH

PHL PLH

CD4053

CD4052

CD4051

Figure 15. Propagation Delay, Inhibit Input to Signal Output

12

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ꢛ

ꢕ

ꢔ

ꢜ

ꢑ

ꢍꢒ

ꢕ

ꢀ

ꢝ

ꢑ

ꢗ

ꢞ

ꢗ

ꢑ

ꢀ

ꢍ

ꢐ

ꢞ

ꢗ

ꢙ

ꢎ

ꢕ

ꢍ

ꢐ

SCHS354 − AUGUST 2004

PARAMETER MEASUREMENT INFORMATION

V

DD

V

DD

V

DD

µA

1 K

V

IH

1

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1K

2

3

4

5

6

7

8

mA

µA

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1K

V

IH

1K

1 K

V

IH

V

IL

V

IH

V

IL

V

IL

V

IH

IL

CD4053B

CD4052B

V

IL

CD4051B

V

IL

Measure <2 mA on All OFF Channels (e.g., Channel 2x)

Measure <2 mA on All OFF Channels (e.g., Channel 6)

Measure <2 mA on All OFF Channels (e.g., Channel by)

Figure 16. Input-Voltage Test Circuit (Noise Immunity)

V

DD

V

DD

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CD4052

Ι

CD4051

CD4053

Ι

Figure 17. Quiescent Device Current

Keithley

610 Digital

Multimeter

V

DD

TG

On

10 kW

1-kW

Range

Y

X

X−Y

Plotter

V

SS

H.P.

Moseley

7030A

Figure 18. Channel ON-Resistance Test Circuit

13

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ꢀ ꢌ ꢍꢎ ꢏ ꢐꢏ ꢑ ꢍꢒ ꢌꢓ ꢑꢔꢕ ꢖ ꢑ ꢗꢘ ꢗꢙ ꢎꢚ ꢁ ꢗ ꢌꢓ ꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗꢙꢎ

ꢛ

ꢕ

ꢔ

ꢜ

ꢑ

ꢍ

ꢒ

ꢕ

ꢀ

ꢝ

ꢑ

ꢗ

ꢞ

ꢗ

ꢑ

ꢀ

ꢍ

ꢐ

ꢞ

ꢗ

ꢙ

ꢎ

ꢕ

ꢍꢐ

SCHS354 − AUGUST 2004

PARAMETER MEASUREMENT INFORMATION

V

DD

V

DD

1

2

3

4

5

6

7

8

16

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

15

14

13

12

11

10

9

V

DD

Ι

V

SS

V

SS

CD4051

CD4053

CD4051

CD4053

V

SS

V

SS

NOTE: Measure inputs sequentially to both V

and V

SS.

.

NOTE: Measure inputs sequentially to both V

DD

and V

SS.

DD

SS

Connect all unused inputs to either V

DD

or V

Connect all unused inputs to either V

or V .

DD

SS

Figure 19. Input Current

5 V

P−P

Channel

OFF

Channel

ON

RF

VM

Common

RF

VM

R

L

OFF

Channel

5 V

P−P

1K

R

L

V

DD

Channel

ON

RF

VM

Channel

OFF

6

7

8

R

L

R

L

Figure 20. Feedthrough

Figure 21. Crosstalk Between Any Two Channels

5 V

P−P

Channel In Y

ON or OFF

Channel In X

ON or OFF

RF

VM

R

L

Figure 22. Crosstalk Between Duals or Triplets (CD4052B, CD4053B)

Differential

Signals

CD4052

Communications

Link

.

Differential

Amplifier/Line

Driver

Differential

Receiver

Differential

Multiplexing

Demultiplexing

Figure 23. Typical Time-Division Application of the CD4052B

14

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ꢀꢌ ꢍ ꢎ ꢏꢐꢏ ꢑꢍ ꢒ ꢌ ꢓꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗꢙꢎ ꢚꢁꢗ ꢌꢓ ꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗ ꢙ ꢎ

ꢛ

ꢕ

ꢔ

ꢜ

ꢑ

ꢍꢒ

ꢕ

ꢀ

ꢝ

ꢑ

ꢗ

ꢞ

ꢗ

ꢑ

ꢀ

ꢍ

ꢐ

ꢞ

ꢗ

ꢙ

ꢎ

ꢕ

ꢍ

ꢐ

SCHS354 − AUGUST 2004

APPLICATION INFORMATION

In applications where separate power sources drive V

and the signal inputs, the V

current capability should

DD

exceed V /R (R = effective external load). This provision avoids permanent current flow or clamp action on the

DD

L

V

supply when power is applied or removed from the CD4051B, CD4052B, or CD4053B.

DD

A

B

C

A

B

C

INH

CD4051B

Q

0

A

B

C

INH

A

B

E

D

E

Q

1

1/2

CD4556

Common

Output

Q

2

A

B

C

INH

Figure 24. 24-to-1 Multiplexer Addressing

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

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型号：	CD4053BQM96Q1
厂家：	TEXAS INSTRUMENTS
描述：	CMOS ALALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION CMOS ALALOG多路复用器/多路解复用器采用逻辑电平转换解复用器开关复用器或开关信号电路光电二极管输出元件
文件：	总18页 (文件大小：394K)
中文：	中文翻译
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