CCB3Q3306AMPWEP [TI]
双路 FET 总线开关、2.5V/3.3V、低压高带宽总线开关 | PW | 8 | -55 to 125;
| 型号： | CCB3Q3306AMPWEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路 FET 总线开关、2.5V/3.3V、低压高带宽总线开关 | PW | 8 | -55 to 125 开关 |
| 文件： | 总13页 (文件大小：629K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CB3Q3306A-EP
www.ti.com.cn
ZHCSBY1 –DECEMBER 2013
双 FET 总线开关 2.5V/3.3V 低压高带宽总线开关
查询样片: SN74CB3Q3306A-EP
1
特性
•
•
•
高带宽数据路径（高达 500MHz(1)）
•
•
锁断性能超过 100mA
符合 JESD 78，II 类规范的要求
支持器件加电与断电的 5V 容限 I/O
静电放电 (ESD) 性能测试符合 JESD 22 标准
工作范围内低且平的导通状态电阻 (ron)
特性
–
2000V 人体模型
（ron = 4Ω 典型值）
（A114-B，II 类）
•
数据 I/O 端口上的轨到轨切换
–
1000V 充电器件模型 (C101)
–
–
3.3V VCC 时的 0 至 5V 切换
2.5V VCC 时的 0 至 3.3V 切换
•
支持数字和模拟应用：USB 接口，差分信号接口，
总线隔离，低失真信号选通
•
•
支持近零传播延迟的双向数据流
支持国防、航空航天、和医疗应用
低输入/输出电容最大限度地减少
加载和信号失真
（Cio(OFF) = 3.5pF 典型值）
•
•
•
•
•
•
•
受控基线
同一组装和测试场所
同一制造场所
•
•
•
•
•
快速开关频率（fOE = 20MHz 最大值）
数据与控制输入提供下冲钳位二极管
低功耗（ICC = 0.25mA 典型值）
2.3V 至 3.6V 的 VCC 工作电压范围
支持军用（-55°C 至 125°C）温度范围
延长的产品生命周期
延长的产品变更通知
产品可追溯性
数据 I/O 支持 0 至 5 V 信号传输级
(0.8V，1.2V，1.5V，1.8V，2.5V，3.3V，5V）
PW PACKAGE
(TOP VIEW)
•
控制输入可由 TTL 或
5V/3.3V CMOS 输出驱动
1
2
3
4
8
7
6
5
1OE
1A
VCC
2OE
2B
•
(1)
Ioff 支持部分断电模式工作
要获得与 CB3Q 系列性能特点相关的额外信息，请参考 TI 应
用报告，《CBT-C，CB3T 和 CB3Q 信号开关系列》，文献编
号 SCDA008。
1B
GND
2A
订购信息
TJ
封装(1)
管
可订购器件型号
正面标记
VID 号
薄型小外形尺
寸封装
(TSSOP)-PW
CCB3Q3306AMPWEP
V62/14606-01XE-T
V62/14606-01XE
-55°C 至 125°C
U306AM
卷带
CCB3Q3306AMPWREP
(1) 封装图示、标准包装数量、散热数据、符号以及印刷电路板 (PCB) 设计指南可从以下网址内获得 www.ti.com/sc/package。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
版权 © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
English Data Sheet: SCDS352
SN74CB3Q3306A-EP
ZHCSBY1 –DECEMBER 2013
www.ti.com.cn
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
说明
SN74CB3Q3306A 是一款高带宽 FET 总线开关，此开关利用一个电荷泵来提升导通晶体管的栅极电压，从而提供
一个低平的导通状态电阻 (ron)。 低平导通状态电阻可实现最小传播延迟，并且支持数据输入/输出 (I/O) 端口上的轨
到轨切换。 此器件还特有低数据 I/O 电容，以最大限度地减少数据总线上的电容负载和信号失真。 专门设计用于
支持高带宽应用，SN74CB3Q3306A 提供非常适合于宽带通信、网络互联、以及数据密集型计算系统的经优化的
接口解决方案。
SN74CB3Q3306A 可组成两个 1 位开关，此开关具有分离输出使能 (1OE，2OE) 输入。 它即可用作 2 个 1 位总
线开关，也可用作 1 个 2 位总线开关。 当 OE 为低电平时，相关 1 位总线开关打开，并且 A 端口被连接至 B 端
口，从而实现两个端口之间的双向数据流。 当 OE 为高电平时，相关 1 位总线开关关闭，并且在 A 与 B 端口之间
存在高阻抗状态。
该器件完全符合使用 Ioff 的部分断电应用的规范要求。 Ioff 电路可防止在器件断电时电流回流对器件造成损坏。 该
器件可在关闭时提供隔离。
为了确保加电或断电期间的高阻抗状态，OE 应通过一个上拉电阻器被连接至 VCC；该电阻器的最小值由驱动器的
电流吸入能力来决定。
Table 1. FUNCTION TABLE
(EACH BUS SWITCH)
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
Z
A port = B port
Disconnect
H
LOGIC DIAGRAM (POSITIVE LOGIC)
2
3
1A
1B
2B
SW
1
1OE
5
7
6
2A
SW
2OE
2
Copyright © 2013, Texas Instruments Incorporated
SN74CB3Q3306A-EP
www.ti.com.cn
ZHCSBY1 –DECEMBER 2013
Figure 1. SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
A
B
V
CC
Charge
Pump
(1)
EN
(1) EN is the internal enable signal applied to the switch.
ABSOLUTE MAXIMUM RATINGS(1)
over operating junction temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
4.6
7
UNIT
V
VCC Supply voltage range
VIN
VI/O Switch I/O voltage range(2) (3) (4)
IIK Control input clamp current
II/OK I/O port clamp current
Control input voltage range(2) (3)
V
7
V
VIN < 0
VI/O < 0
–50
–50
±64
±100
mA
mA
mA
mA
II/O
ON-state switch current(5)
Continuous current through each VCC or
GND
TJ
Maximum junction temperature
Storage temperature range
150
150
°C
°C
Tstg
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VI and VO are used to denote specific conditions for VI/O
.
(5) II and IO are used to denote specific conditions for II/O
.
Copyright © 2013, Texas Instruments Incorporated
3
SN74CB3Q3306A-EP
ZHCSBY1 –DECEMBER 2013
www.ti.com.cn
THERMAL INFORMATION
SN74CB3Q3306A-EP
THERMAL METRIC(1)
PW
8 PINS
190.6
74
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
119.4
12
°C/W
ψJT
ψJB
117.7
N/A
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS(1)
MIN MAX UNIT
VCC
VIH
Supply voltage
2.3
1.7
2
3.6
5.5
5.5
0.7
0.8
5.5
125
V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
High-level control input
voltage
V
0
Low-level control input
voltage
VIL
V
0
VI/O
TJ
Data input/output voltage
0
V
Operating junction temperature
–55
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
Copyright © 2013, Texas Instruments Incorporated
SN74CB3Q3306A-EP
www.ti.com.cn
ZHCSBY1 –DECEMBER 2013
ELECTRICAL CHARACTERISTICS(1)
over recommended operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(2) MAX UNIT
VIK
IIN
VCC = 3.6 V,
VCC = 3.6 V,
II = –18 mA
–1.8
±1
V
Control
inputs
VIN = 0 to 5.5 V
μA
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC
(3)
IOZ
Ioff
VCC = 3.6 V,
VCC = 0,
±1
1
μA
μA
VO = 0 to 5.5 V,
VI = 0
II/O = 0,
ICC
VCC = 3.6 V,
VIN = VCC or GND
0.25
0.03
0.7 mA
Switch ON or OFF,
One input at 3 V,
A and B ports open,
TJ = -55°C to 85°C
TJ = 125°C
25
μA
36
Control
inputs
(4)
ΔICC
VCC = 3.6 V,
VCC = 3.6 V,
Other inputs at VCC or GND
Per control
input
mA/
MHz
(5)
ICCD
Control input switching at 50% duty cycle
Control
inputs
Cin
Cio(OFF)
Cio(ON)
VCC = 3.3 V,
VCC = 3.3 V,
VCC = 3.3 V,
VIN = 5.5 V, 3.3 V, or 0
2.5
3.5
pF
pF
pF
Switch OFF,
VIN = VCC,
VI/O = 5.5 V, 3.3 V, or 0
VI/O = 5.5 V, 3.3 V, or 0
Switch ON,
VIN = GND,
8
4
TJ = -55°C to 85°C
TJ = 125°C
8
10
9
VI = 0,
IO = 30 mA
IO = –15 mA
IO = 30 mA
IO = –15 mA
VCC = 2.3 V,
TYP at VCC = 2.5 V
TJ = -55°C to 85°C
TJ = 125°C
5
4
5
VI = 1.7 V,
VI = 0,
58
Ω
6
(6)
ron
TJ = -55°C to 85°C
TJ = 125°C
8
8
VCC = 3 V
TJ = -55°C to 85°C
TJ = 125°C
VI = 2.4 V,
66
(1) VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
(2) All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
(5) This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see
Figure 4).
(6) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
100,000,000
10,000,000
WB Failure Mode
1,000,000
100,000
EM Failure Mode
10,000
1,000
80
90
100
110
120
130
140
150
Continuous Junction Temperature, TJ (°C)
(1) See datasheet for absolute maximum and minimum recommended operating conditions.
(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3) Enhanced plastic product disclaimer applies.
Figure 2. SN74CB3Q3306A-EP Operating Life Derating Chart
Copyright © 2013, Texas Instruments Incorporated
5
SN74CB3Q3306A-EP
ZHCSBY1 –DECEMBER 2013
www.ti.com.cn
SWITCHING CHARACTERISTICS
over recommended operating junction temperature range (unless otherwise noted) (see Figure 5)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MAX
MIN
MAX
10
MIN
(1)
f OE
OE
A or B
B or A
20
0.3
2.3
10
9
MHz
TJ = -55° to 85°C
TJ = 125°C
0.2
1.2
12
(2)
tpd
A or B
ns
ten
OE
OE
A or B
A or B
1.5
1
1.5
1
ns
ns
tdis
14
(1) Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0)
(2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
TYPICAL ron vs VI
16
V
CC
= 3.3 V
14
12
10
8
T
= 25°C
= −15 mA
A
I
O
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
V − V
3.0
3.5
4.0
4.5
5.0
I
Figure 3. Typical ron vs VI
12
V
CC
= 3.3 V
T = 25°C
A
A and B Ports Open
10
8
6
4
2
One OE Switching
16
0
0
2
4
6
8
10
12
14
18
20
OE Switching Frequency − MHz
Figure 4. Typical ICC vs OE Switching Frequency
6
Copyright © 2013, Texas Instruments Incorporated
SN74CB3Q3306A-EP
www.ti.com.cn
ZHCSBY1 –DECEMBER 2013
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
V
G1
TEST CIRCUIT
DUT
2 × V
CC
Input Generator
S1
R
L
Open
GND
V
V
O
I
50 Ω
50 Ω
C
L
R
G2
L
(see Note A)
S1
V
I
C
L
V
∆
R
L
V
CC
TEST
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
V
V
or GND
or GND
30 pF
50 pF
CC
t
pd(s)
CC
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × V
2 × V
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
CC
t
/t
PLZ PZL
CC
2.5 V ± 0.2 V
3.3 V ± 0.3 V
GND
GND
500 Ω
500 Ω
V
V
30 pF
50 pF
0.15 V
0.3 V
CC
t
/t
PHZ PZH
CC
Output
Control
(V
V
CC
V /2
CC
V /2
CC
)
IN
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
Output
Control
V
CC
V /2
CC
S1 at 2 × V
V + V
∆
OL
V /2
CC
V /2
CC
CC
(V
IN
)
(see Note B)
OL
0 V
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− V
∆
V /2
CC
Output
V /2
CC
V /2
CC
0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
)
pd(s)
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
en
are the same as t
. The t propagation delay is the calculated RC time constant of the typical ON-state resistance
pd(s) pd
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Test Circuit and Voltage Waveforms
Copyright © 2013, Texas Instruments Incorporated
7
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CCB3Q3306AMPWEP
CCB3Q3306AMPWREP
V62/14606-01XE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
8
8
8
8
150
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
U306AM
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
U306AM
U306AM
U306AM
V62/14606-01XE-T
150
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
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EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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