CC430F513X [TI]
MSP430 SoC with RF Core; MSP430 SoC的射频核心型号: | CC430F513X |
厂家: | TEXAS INSTRUMENTS |
描述: | MSP430 SoC with RF Core |
文件: | 总118页 (文件大小:1320K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
www.ti.com
SLAS554D –MAY 2009–REVISED JULY 2010
MSP430 SoC with RF Core
1
FEATURES
•
True System-on-Chip (SoC) for Low-Power
Wireless Communication Applications
•
High-Performance Sub-1-GHz RF Transceiver
Core
•
•
Wide Supply Voltage Range: 1.8 V to 3.6 V
Ultralow Power Consumption:
–
–
–
Same as in CC1101
Wide Supply Voltage Range: 2.0 V to 3.6 V
–
–
–
–
CPU Active Mode (AM): 160 µA/MHz
Standby Mode (LPM3 RTC Mode):2.0 µA
Off Mode (LPM4 RAM Retention): 1.0 µA
Radio in RX: 15 mA, 250 kbps, 915 MHz
Frequency Bands: 300 MHz to 348 MHz,
389 MHz to 464 MHz, and 779 MHz to
928 MHz
–
–
Programmable Data Rate From 0.6 kBaud
to 500 kBaud
•
MSP430™ System and Peripherals
High Sensitivity (–117 dBm at 0.6 kBaud,
-111 dBm at 1.2 kBaud, 315 MHz, 1% Packet
Error Rate)
–
–
–
16-Bit RISC Architecture, Extended
Memory, up to 20-MHz System Clock
Wake-Up From Standby Mode in Less
Than 6 µs
–
–
–
–
Excellent Receiver Selectivity and Blocking
Performance
Flexible Power Management System with
SVS and Brownout
Programmable Output Power Up to +12
dBm for All Supported Frequencies
–
–
Unified Clock System with FLL
2-FSK, 2-GFSK, and MSK Supported as well
as OOK and Flexible ASK Shaping
16-Bit Timer TA0, Timer_A with Five
Capture/Compare Registers
Flexible Support for Packet-Oriented
Systems: On-Chip Support for Sync Word
Detection, Address Check, Flexible Packet
Length, and Automatic CRC Handling
–
16-Bit Timer TA1, Timer_A with Three
Capture/Compare Registers
–
–
Hardware Real-Time Clock
Two Universal Serial Communication
Interfaces
–
Support for Automatic Clear Channel
Assessment (CCA) Before Transmitting (for
Listen-Before-Talk Systems)
–
–
USCI_A0 supporting UART, IrDA, SPI
USCI_B0 supporting I2C, SPI
–
–
Digital RSSI Output
Suited for Systems Targeting Compliance
With EN 300 220 (Europe) and
FCC CFR Part 15 (US)
–
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold, and Autoscan
Features (Only CC430F613x and
CC430F513x)
–
–
Suited for Systems Targeting Compliance
With Wireless M-Bus Standard EN
13757-4:2005
–
–
Comparator
Integrated LCD Driver With Contrast
Control for up to 96 Segments (Only
CC430F61xx)
Support for Asynchronous and
Synchronous Serial Receive/Transmit Mode
for Backward Compatibility With Existing
Radio Communication Protocols
–
128-bit AES Security Encryption/Decryption
Coprocessor
•
•
Family Members are Summarized in Table 1.
–
–
–
32-Bit Hardware Multiplier
Three-Channel Internal DMA
For Complete Module Descriptions, See the
CC430 Family User's Guide (SLAU259).
Serial Onboard Programming, No External
Programming Voltage Needed
–
Embedded Emulation Module (EEM)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554D –MAY 2009–REVISED JULY 2010
www.ti.com
DESCRIPTION
The Texas Instruments CC430 family of ultralow-power microcontroller system-on-chip with integrated RF
transceiver cores consists of several devices featuring different sets of peripherals targeted for a wide range of
applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life
in portable measurement applications. The device features the powerful MSP430™ 16-bit RISC CPU, 16-bit
registers, and constant generators that contribute to maximum code efficiency.
The CC430 family provides a tight integration between the microcontroller core, its peripherals, software, and the
RF transceiver, making these true system-on-chip solutions easy to use as well as improving performance.
The CC430F61xx series are microcontroller system-on-chip configurations combining the excellent performance
of the state-of-the-art CC1101 sub-1-GHz RF transceiver with the MSP430 CPUXV2, up to 32 kB of in-system
programmable flash memory, up to 4 kB of RAM, two 16-bit timers, a high-performance 12-bit A/D converter with
eight external inputs plus internal temperature and battery sensors on CC430F613x devices, comparator,
universal serial communication interfaces (USCI), 128-bit AES security accelerator, hardware multiplier, DMA,
real-time clock module with alarm capabilities, LCD driver, and up to 44 I/O pins.
The CC430F513x series are microcontroller system-on-chip configurations combining the excellent performance
of the state-of-the-art CC1101 sub-1-GHz RF transceiver with the MSP430 CPUXV2, up to 32 kB of in-system
programmable flash memory, up to 4 kB of RAM, two 16-bit timers, a high performance 12-bit A/D converter with
six external inputs plus internal temperature and battery sensors, comparator, universal serial communication
interfaces (USCI), 128-bit AES security accelerator, hardware multiplier, DMA, real-time clock module with alarm
capabilities, and up to 30 I/O pins.
Typical applications for these devices include wireless analog and digital sensor systems, heat cost allocators,
thermostats, metering (AMR/AMI), smart grid wireless networks etc.
Family members available are summarized in Table 1.
For complete module descriptions, see the CC430 Family User's Guide, literature number SLAU259.
Table 1. Family Members
USCI
Channel
A:
Channel
B:
Program
(KB)
SRAM
(KB)
Timer_A
ADC12_A
Package
Type
(2)
Device
LCD_B
Comp_B
I/O
(1)
(2)
UART/LIN SPI/ I2C
/IrDA/SPI
8 ext/
4 int ch.
CC430F6137
CC430F6135
32
16
4
2
5, 3
5, 3
96 seg
96 seg
1
1
1
1
8 ch.
8 ch.
44
44
64 RGC
64 RGC
8 ext/
4 int ch.
CC430F6127
CC430F6126
CC430F6125
32
32
16
4
2
2
5, 3
5, 3
5, 3
96 seg
96 seg
96 seg
1
1
1
1
1
1
n/a
n/a
n/a
8 ch.
8 ch.
8 ch.
44
44
44
64 RGC
64 RGC
64 RGC
6 ext/
4 int ch.
CC430F5137
CC430F5135
CC430F5133
32
16
8
4
2
2
5, 3
5, 3
5, 3
n/a
n/a
n/a
1
1
1
1
1
1
6 ch.
6 ch.
6 ch.
30
30
30
48 RGZ
48 RGZ
48 RGZ
6 ext/
4 int ch.
6 ext/
4 int ch.
(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 5, 3 would represent two instantiations of Timer_A, the first
instantiation having 5 and the second instantiation having 3 capture compare registers and PWM output generators, respectively.
(2) n/a: not available.
2
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Copyright © 2009–2010, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
www.ti.com
SLAS554D –MAY 2009–REVISED JULY 2010
ORDERING INFORMATION(1)
PACKAGED DEVICES(2)
TA
PLASTIC 64-PIN QFN (RGC)
CC430F6137IRGC
CC430F6135IRGC
CC430F6127IRGC
CC430F6126IRGC
CC430F6125IRGC
PLASTIC 48-PIN QFN (RGZ)
CC430F5137IRGZ
CC430F5135IRGZ
CC430F5133IRGZ
–40°C to 85°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Copyright © 2009–2010, Texas Instruments Incorporated
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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554D –MAY 2009–REVISED JULY 2010
www.ti.com
CC430F613x Functional Block Diagram
XIN XOUT
(32kHz)
P1.x/P2.x
2x8
P3.x/P4.x
2x8
P5.x
RF_XIN RF_XOUT
(26MHz)
1x8
I/O Ports
P1/P2
2x8 I/Os
I/O Ports
P3/P4
2x8 I/Os
I/O Ports
P5
1x8 I/Os
REF
MCLK
ACLK
Unified
Clock
System
Packet
Handler
Comp_B
ADC12
Voltage
Reference
SMCLK
PA
1x16 I/Os
PB
1x16 I/Os
Digital RSSI
Carrier Sense
PQI / LQI
CCA
DMA
Controller
3 Channel
MAB
MDB
Bus
Cntrl
Logic
Sub-1GHz
Radio
CPUXV2
incl. 16
Registers
(CC1101)
SYS
Flash
RAM
Watch-
dog
CPU Interface
MODEM
32kB
16kB
4kB
2kB
CRC16
MPY32
Port
Mapping
Controller
EEM
(S: 3+1)
MDB
MAB
JTAG
Interface
Frequency
Synthesizer
Spy-Bi-
Wire
Power
Mgmt
USCI_A0
(UART,
IrDA, SPI)
LCD_B
AES128
TA0
TA1
96
Segments
1,2,3,4
Mux
RF/ANALOG
TX & RX
RTC_A
Security
En-/De-
cryption
LDO
SVM/SVS
Brownout
5 CC
Registers
3 CC
Registers
USCI_B0
(SPI, I2C)
RF_P RF_N
4
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Copyright © 2009–2010, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
www.ti.com
SLAS554D –MAY 2009–REVISED JULY 2010
RGC PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P1.7/PM_UCA0CLK/PM_UCB0STE/R03
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
GUARD
2
3
P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23
LCDCAP/R33
4
5
COM0
R_BIAS
6
AVCC_RF
AVCC_RF
RF_N
P5.7/COM1/S26
7
P5.6/COM2/S25
8
P5.5/COM3/S24
CC430F613x
9
RF_P
P5.4/S23
10
11
12
13
14
15
16
VCORE
AVCC_RF
AVCC_RF
RF_XOUT
RF_XIN
DVCC
P1.4/PM_UCB0CLK/PM_UCA0STE/S22
P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21
P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20
P1.1/PM_RFGDO2/S19
P1.0/PM_RFGDO0/S18
P5.2/S0
P5.3/S1
P4.0/S2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS
Exposed die
attached pad
The secondary digital functions on ports P1, P2, and P3 are fully mappable. Pinout above shows only the default
mapping. See Table 7 for details.
CAUTION: the LCDCAP/R33 must be connected to VSS if not used.
Copyright © 2009–2010, Texas Instruments Incorporated
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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554D –MAY 2009–REVISED JULY 2010
www.ti.com
CC430F612x Functional Block Diagram
XIN XOUT
(32kHz)
P1.x/P2.x
2x8
P3.x/P4.x
2x8
P5.x
RF_XIN RF_XOUT
(26MHz)
1x8
I/O Ports
P1/P2
2x8 I/Os
I/O Ports
P3/P4
2x8 I/Os
I/O Ports
P5
1x8 I/Os
REF
MCLK
ACLK
Unified
Clock
System
Packet
Handler
Comp_B
Voltage
Reference
SMCLK
PA
1x16 I/Os
PB
1x16 I/Os
Digital RSSI
Carrier Sense
PQI / LQI
CCA
DMA
Controller
3 Channel
MAB
MDB
Bus
Cntrl
Logic
Sub-1GHz
Radio
CPUXV2
incl. 16
Registers
(CC1101)
SYS
Flash
RAM
Watch-
dog
CPU Interface
MODEM
32kB
32kB
16kB
4kB
2kB
2kB
CRC16
MPY32
Port
Mapping
Controller
EEM
(S: 3+1)
MDB
MAB
JTAG
Interface
Frequency
Synthesizer
Spy-Bi-
Wire
Power
Mgmt
USCI_A0
(UART,
IrDA, SPI)
LCD_B
AES128
TA0
TA1
96
Segments
1,2,3,4
Mux
RF/ANALOG
TX & RX
RTC_A
Security
En-/De-
cryption
LDO
SVM/SVS
Brownout
5 CC
Registers
3 CC
Registers
USCI_B0
(SPI, I2C)
RF_P RF_N
6
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Copyright © 2009–2010, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
www.ti.com
SLAS554D –MAY 2009–REVISED JULY 2010
RGC PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P1.7/PM_UCA0CLK/PM_UCB0STE/R03
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
GUARD
2
3
P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23
LCDCAP/R33
4
5
COM0
R_BIAS
6
AVCC_RF
AVCC_RF
RF_N
P5.7/COM1/S26
7
P5.6/COM2/S25
8
P5.5/COM3/S24
CC430F612x
9
RF_P
P5.4/S23
10
11
12
13
14
15
16
VCORE
AVCC_RF
AVCC_RF
RF_XOUT
RF_XIN
DVCC
P1.4/PM_UCB0CLK/PM_UCA0STE/S22
P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21
P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20
P1.1/PM_RFGDO2/S19
P1.0/PM_RFGDO0/S18
P5.2/S0
P5.3/S1
P4.0/S2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS
Exposed die
attached pad
The secondary digital functions on ports P1, P2, and P3 are fully mappable. Pin out above shows only the default
mapping. Refer to Table 7 for details.
CAUTION: the LCDCAP/R33 must be connected to VSS if not used.
Copyright © 2009–2010, Texas Instruments Incorporated
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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554D –MAY 2009–REVISED JULY 2010
www.ti.com
CC430F513x Functional Block Diagram
XIN XOUT
(32kHz)
P1.x/P2.x
2x8
P5.x
RF_XIN RF_XOUT
(26MHz)
P3.x
1x8
1x2
I/O Ports
P1/P2
2x8 I/Os
I/O Ports
P3
1x8 I/Os
I/O Ports
P5
1x2 I/Os
REF
MCLK
ACLK
Unified
Clock
System
Packet
Handler
Comp_B
ADC12
Voltage
Reference
SMCLK
PA
1x16 I/Os
Digital RSSI
Carrier Sense
PQI / LQI
CCA
DMA
Controller
3 Channel
MAB
MDB
Bus
Cntrl
Logic
Sub-1GHz
Radio
CPUXV2
incl. 16
Registers
(CC1101)
SYS
Flash
RAM
Watch-
dog
CPU Interface
MODEM
32
kB
16kB
8kB
4kB
2kB
CRC16
MPY32
Port
Mapping
Controller
EEM
(S: 3+1)
MDB
MAB
JTAG
Interface
Frequency
Synthesizer
Spy-Bi-
Wire
Power
Mgmt
USCI_A0
(UART,
IrDA, SPI)
AES128
TA0
TA1
RF/ANALOG
TX & RX
RTC_A
Security
En-/De-
cryption
5 CC
Registers
3 CC
Registers
LDO
SVM/SVS
Brownout
USCI_B0
(SPI, I2C)
RF_P RF_N
8
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Copyright © 2009–2010, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
www.ti.com
SLAS554D –MAY 2009–REVISED JULY 2010
RGZ PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
36
1
PJ.1/TDI/TCLK
PJ.0/TDO
GUARD
P2.2/PM_TA1CCR1A/CB2/A2
P2.1/PM_TA1CCR0A/CB1/A1
2
35
34
33
32
31
30
29
28
27
26
25
3
4
P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0
P1.7/PM_UCA0CLK/PM_UCB0STE
P1.6/PM_UCA0TXD/PM_UCA0SIMO
P1.5/PM_UCA0RXD/PM_UCA0SOMI
VCORE
R_BIAS
5
AVCC_RF
AVCC_RF
RF_N
6
CC430F513x
7
8
DVCC
RF_P
9
P1.4/PM_UCB0CLK/PM_UCA0STE
P1.3/PM_UCB0SIMO/PM_UCB0SDA
P1.2/PM_UCB0SOMI/PM_UCB0SCL
P1.1/PM_RFGDO2
AVCC_RF
AVCC_RF
RF_XOUT
RF_XIN
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
VSS
Exposed die
attached pad
The secondary digital functions on ports P1, P2, and P3 are fully mappable. Pin out above shows only the default
mapping. Refer to Table 7 for details.
Copyright © 2009–2010, Texas Instruments Incorporated
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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554D –MAY 2009–REVISED JULY 2010
www.ti.com
CC430F613x and CC430F612x Terminal Functions
TERMINAL
NAME
I/O(1)
DESCRIPTION
NO.
General-purpose digital I/O with port interrupt and map-able secondary function
I/O Default mapping: USCI_A0 clock input/output / USCI_B0 SPI slave transmit enable
Input/output port of lowest analog LCD voltage (V5)
P1.7/ PM_UCA0CLK/
PM_UCB0STE/ R03
1
General-purpose digital I/O with port interrupt and map-able secondary function
P1.6/ PM_UCA0TXD/
PM_UCB0SIMO/ R13/ LCDREF
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out
Input/output port of third most positive analog LCD voltage (V3 or V4)
External reference voltage input for regulated LCD voltage
2
3
I/O
General-purpose digital I/O with port interrupt and map-able secondary function
I/O Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in
Input/output port of second most positive analog LCD voltage (V2)
P1.5/ PM_UCA0RXD/
PM_UCB0SOMI/ R23
LCD capacitor connection
LCDCAP/ R33
COM0
4
5
6
I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: must be connected to VSS if not used.
O
LCD common output COM0 for LCD backplane
General-purpose digital I/O
P5.7/ COM1/ S26
I/O LCD common output COM1 for LCD backplane
LCD segment output S26
General-purpose digital I/O
P5.6/ COM2/ S25
7
I/O LCD common output COM2 for LCD backplane
LCD segment output S25
General-purpose digital I/O
P5.5/ COM3/ S24
P5.4/ S23
8
9
I/O LCD common output COM3 for LCD backplane
LCD segment output S24
General-purpose digital I/O
I/O
LCD segment output S23
VCORE
DVCC
10
11
Regulated core power supply
Digital power supply
General-purpose digital I/O with port interrupt and map-able secondary function
I/O Default mapping: USCI_B0 clock input/output / USCI_A0 SPI slave transmit enable
LCD segment output S22
P1.4/ PM_UCB0CLK/
PM_UCA0STE/ S22
12
13
14
15
16
17
18
19
20
21
General-purpose digital I/O with port interrupt and map-able secondary function
I/O Default mapping: USCI_B0 SPI slave in master out/USCI_B0 I2C data
LCD segment output S21
P1.3/ PM_UCB0SIMO/
PM_UCB0SDA/ S21
General-purpose digital I/O with port interrupt and map-able secondary function
I/O Default mapping: USCI_B0 SPI slave out master in/UCSI_B0 I2C clock
LCD segment output S20
P1.2/ PM_UCB0SOMI/
PM_UCB0SCL/ S20
General-purpose digital I/O with port interrupt and map-able secondary function
I/O Default mapping: Radio GDO2 output
P1.1/ PM_RFGDO2/ S19
P1.0/ PM_RFGDO0/ S18
P3.7/ PM_SMCLK/ S17
LCD segment output S19
General-purpose digital I/O with port interrupt and map-able secondary function
I/O Default mapping: Radio GDO0 output
LCD segment output S18
General-purpose digital I/O with map-able secondary function
I/O Default mapping: SMCLK output
LCD segment output S17
General-purpose digital I/O with map-able secondary function
I/O Default mapping: Radio GDO1 output
LCD segment output S16
P3.6/ PM_RFGDO1/ S16
P3.5/ PM_TA0CCR4A/ S15
P3.4/ PM_TA0CCR3A/ S14
P3.3/ PM_TA0CCR2A/ S13
(1) I = input, O = output
General-purpose digital I/O with map-able secondary function
I/O Default mapping: TA0 CCR4 compare output/capture input
LCD segment output S15
General-purpose digital I/O with map-able secondary function
I/O Default mapping: TA0 CCR3 compare output/capture input
LCD segment output S14
General-purpose digital I/O with map-able secondary function
I/O Default mapping: TA0 CCR2 compare output/capture input
LCD segment output S13
10
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Copyright © 2009–2010, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
www.ti.com
SLAS554D –MAY 2009–REVISED JULY 2010
CC430F613x and CC430F612x Terminal Functions (continued)
TERMINAL
NAME
I/O(1)
DESCRIPTION
NO.
General-purpose digital I/O with map-able secondary function
P3.2/ PM_TA0CCR1A/ S12
P3.1/ PM_TA0CCR0A/ S11
22
I/O Default mapping: TA0 CCR1 compare output/capture input
LCD segment output S12
General-purpose digital I/O with map-able secondary function
I/O Default mapping: TA0 CCR0 compare output/capture input
LCD segment output S11
23
24
General-purpose digital I/O with map-able secondary function
I/O Default mapping: Comparator_B output; TA0 clock input
LCD segment output S10
P3.0/ PM_CBOUT0/ PM_TA0CLK/
S10
DVCC
25
26
Digital power supply
General-purpose digital I/O
I/O
P4.7/ S9
LCD segment output S9
General-purpose digital I/O
I/O
P4.6/ S8
P4.5/ S7
P4.4/ S6
P4.3/ S5
P4.2/ S4
P4.1/ S3
P4.0/ S2
P5.3/ S1
P5.2/ S0
27
28
29
30
31
32
33
34
35
LCD segment output S8
General-purpose digital I/O
I/O
LCD segment output S7
General-purpose digital I/O
I/O
LCD segment output S6
General-purpose digital I/O
I/O
LCD segment output S5
General-purpose digital I/O
I/O
LCD segment output S4
General-purpose digital I/O
I/O
LCD segment output S3
General-purpose digital I/O
I/O
LCD segment output S2
General-purpose digital I/O
I/O
LCD segment output S1
General-purpose digital I/O
I/O
LCD segment output S0
RF_XIN
36
37
38
39
I
Input terminal for RF crystal oscillator, or external clock input
Output terminal for RF crystal oscillator
Radio analog power supply
RF_XOUT
AVCC_RF
AVCC_RF
O
Radio analog power supply
RF Positive RF input to LNA in receive mode
I/O Positive RF output from PA in transmit mode
RF_P
RF_N
40
41
RF Negative RF input to LNA in receive mode
I/O Negative RF output from PA in transmit mode
AVCC_RF
AVCC_RF
RBIAS
42
43
44
45
Radio analog power supply
Radio analog power supply
External bias resistor for radio reference current
Power supply connection for digital noise isolation
GUARD
General-purpose digital I/O
I/O
PJ.0/ TDO
46
47
48
49
50
Test data output port
General-purpose digital I/O
I/O
PJ.1/ TDI/ TCLK
PJ.2/ TMS
Test data input or test clock input
General-purpose digital I/O
Test mode select
I/O
General-purpose digital I/O
Test clock
PJ.3/ TCK
I/O
Test mode pin – select digital I/O on JTAG pins
Spy-bi-wire input clock
TEST/ SBWTCK
I
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CC430F613x and CC430F612x Terminal Functions (continued)
TERMINAL
NAME
I/O(1)
DESCRIPTION
NO.
Reset input active low
RST/NMI/ SBWTDIO
51
I/O Non-maskable interrupt input
Spy-bi-wire data input/output
DVCC
AVSS
52
53
Digital power supply
Analog ground supply for ADC12
General-purpose digital I/O
I/O
P5.1/ XOUT
54
Output terminal of crystal oscillator XT1
General-purpose digital I/O
Input terminal for crystal oscillator XT1
P5.0/ XIN
AVCC
55
56
I/O
Analog power supply
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: ADC12CLK output; DMA external trigger input
Comparator_B input CB7
P2.7/ PM_ADC12CLK/
PM_DMAE0/ CB7 (/A7)
57
58
I/O
I/O
Analog input A7 – 12-bit ADC (only CC430F613x)
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: ACLK output
Comparator_B input CB6
P2.6/ PM_ACLK/ CB6 (/A6)
Analog input A6 – 12-bit ADC (only CC430F613x)
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: SVM output
P2.5/ PM_SVMOUT/ CB5
(/A5/ VREF+/ VeREF+)
Comparator_B input CB5
59
60
I/O
I/O
Analog input A5 – 12-bit ADC (only CC430F613x)
Output of reference voltage to the ADC (only CC430F613x)
Input for an external reference voltage to the ADC (only CC430F613x)
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: RTCCLK output
Comparator_B input CB4
P2.4/ PM_RTCCLK/ CB4
(/A4/ VREF-/ VeREF-)
Analog input A4 – 12-bit ADC (only CC430F613x)
Negative terminal for the ADC's reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage (only CC430F613x)
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: TA1 CCR2 compare output/capture input
Comparator_B input CB3
P2.3/ PM_TA1CCR2A/ CB3 (/A3)
P2.2/ PM_TA1CCR1A/ CB2 (/A2)
P2.1/PM_TA1CCR0A/CB1(/A1)
61
62
63
64
I/O
I/O
I/O
I/O
Analog input A3 – 12-bit ADC (only CC430F613x)
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: TA1 CCR1 compare output/capture input
Comparator_B input CB2
Analog input A2 – 12-bit ADC (only CC430F613x)
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: TA1 CCR0 compare output/capture input
Comparator_B input CB1
Analog input A1 – 12-bit ADC (only CC430F613x)
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: Comparator_B output; TA1 clock input
Comparator_B input CB0
P2.0/ PM_CBOUT1/ PM_TA1CLK/
CB0 (/A0)
Analog input A0 – 12-bit ADC (only CC430F613x)
Ground supply
VSS - Exposed die attach pad
The exposed die attach pad must be connected to a solid ground plane as this is
the ground connection for the chip!
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CC430F513x Terminal Functions
TERMINAL
NAME
I/O(1)
DESCRIPTION
NO.
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: TA1 CCR1 compare output/capture input
Comparator_B input CB2
P2.2/ PM_TA1CCR1A/ CB2/ A2
P2.1/ PM_TA1CCR0A/ CB1/ A1
1
I/O
Analog input A2 – 12-bit ADC
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: TA1 CCR0 compare output/capture input
Comparator_B input CB1
2
3
I/O
I/O
Analog input A1 – 12-bit ADC
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: Comparator_B output; TA1 clock input
Comparator_B input CB0
P2.0/ PM_CBOUT1/ PM_TA1CLK/
CB0/ A0
Analog input A0 – 12-bit ADC
P1.7/ PM_UCA0CLK/
PM_UCB0STE
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: USCI_A0 clock input/output / USCI_B0 SPI slave transmit enable
4
5
6
I/O
I/O
I/O
P1.6/ PM_UCA0TXD/
PM_UCB0SIMO
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out
P1.5/ PM_UCA0RXD/
PM_UCB0SOMI
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in
VCORE
DVCC
7
8
Regulated core power supply
Digital power supply
P1.4/ PM_UCB0CLK/
PM_UCA0STE
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: USCI_B0 clock input/output / USCI_A0 SPI slave transmit enable
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P1.3/ PM_UCB0SIMO/
PM_UCB0SDA
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: USCI_B0 SPI slave in master out/USCI_B0 I2C data
10
11
12
13
14
15
16
17
18
19
20
P1.2/ PM_UCB0SOMI/
PM_UCB0SCL
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: USCI_B0 SPI slave out master in/UCSI_B0 I2C clock
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: Radio GDO2 output
P1.1/ PM_RFGDO2
P1.0/ PM_RFGDO0
P3.7/ PM_SMCLK
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: Radio GDO0 output
General-purpose digital I/O with map-able secondary function
Default mapping: SMCLK output
General-purpose digital I/O with map-able secondary function
Default mapping: Radio GDO1 output
P3.6/ PM_RFGDO1
P3.5/ PM_TA0CCR4A
P3.4/ PM_TA0CCR3A
P3.3/ PM_TA0CCR2A
P3.2/ PM_TA0CCR1A
P3.1/ PM_TA0CCR0A
General-purpose digital I/O with map-able secondary function
Default mapping: TA0 CCR4 compare output/capture input
General-purpose digital I/O with map-able secondary function
Default mapping: TA0 CCR3 compare output/capture input
General-purpose digital I/O with map-able secondary function
Default mapping: TA0 CCR2 compare output/capture input
General-purpose digital I/O with map-able secondary function
Default mapping: TA0 CCR1 compare output/capture input
General-purpose digital I/O with map-able secondary function
Default mapping: TA0 CCR0 compare output/capture input
General-purpose digital I/O with map-able secondary function
Default mapping: Comparator_B output; TA0 clock input
P3.0/ PM_CBOUT0/ PM_TA0CLK
DVCC
21
22
23
Digital power supply
P2.7/ PM_ADC12CLK/
PM_DMAE0
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: ADC12CLK output; DMA external trigger input
I/O
I/O
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: ACLK output
P2.6/ PM_ACLK
24
RF_XIN
25
26
27
I
Input terminal for RF crystal oscillator, or external clock input
Output terminal for RF crystal oscillator
Radio analog power supply
RF_XOUT
AVCC_RF
O
(1) I = input, O = output
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CC430F513x Terminal Functions (continued)
TERMINAL
I/O(1)
DESCRIPTION
NAME
NO.
AVCC_RF
RF_P
28
Radio analog power supply
RF Positive RF input to LNA in receive mode
I/O Positive RF output from PA in transmit mode
29
RF Negative RF input to LNA in receive mode
I/O Negative RF output from PA in transmit mode
RF_N
30
AVCC_RF
AVCC_RF
RBIAS
31
32
33
34
Radio analog power supply
Radio analog power supply
External bias resistor for radio reference current
Power supply connection for digital noise isolation
GUARD
General-purpose digital I/O
I/O
PJ.0/ TDO
35
36
37
38
39
Test data output port
General-purpose digital I/O
I/O
PJ.1/ TDI/ TCLK
PJ.2/ TMS
Test data input or test clock input
General-purpose digital I/O
Test mode select
I/O
General-purpose digital I/O
Test clock
PJ.3/ TCK
I/O
Test mode pin – select digital I/O on JTAG pins
Spy-bi-wire input clock
TEST/ SBWTCK
I
Reset input active low
I/O Non-maskable interrupt input
Spy-bi-wire data input/output
RST/NMI/ SBWTDIO
40
DVCC
AVSS
41
42
Digital power supply
Analog ground supply for ADC12
General-purpose digital I/O
I/O
P5.1/ XOUT
43
Output terminal of crystal oscillator XT1
General-purpose digital I/O
I/O
P5.0/ XIN
AVCC
44
45
Input terminal for crystal oscillator XT1
Analog power supply
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: SVM output
P2.5/ PM_SVMOUT/ CB5/
A5/ VREF+/ VeREF+
Comparator_B input CB5
Analog input A5 – 12-bit ADC
46
I/O
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: RTCCLK output
P2.4/ PM_RTCCLK/ CB4/
A4/ VREF-/ VeREF-
Comparator_B input CB4
Analog input A4 – 12-bit ADC
Negative terminal for the ADC's reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
47
48
I/O
I/O
General-purpose digital I/O with port interrupt and map-able secondary function
Default mapping: TA1 CCR2 compare output/capture input
Comparator_B input CB3
P2.3/ PM_TA1CCR2A/ CB3/ A3
VSS - Exposed die attach pad
Analog input A3 – 12-bit ADC
Ground supply
The exposed die attach pad must be connected to a solid ground plane as this is
the ground connection for the chip!
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SHORT-FORM DESCRIPTION
Sub-1 GHz Radio
The implemented sub-1-GHz radio module is based on the industry-leading CC1101, requiring very few external
components. Figure 1 shows a high-level block diagram of the implemented radio.
RADIO CONTROL
ADC
LNA
ADC
RF_P
0
FREQ
SYNTH
RF_N
90
PA
RC OSC
BIAS
XOSC
RBIAS
RF_XIN RF_XOUT
Figure 1. Sub-1 GHz Radio Block Diagram
The radio features a low-IF receiver. The received RF signal is amplified by a low-noise amplifier (LNA) and
down-converted in quadrature to the intermediate frequency (IF). At IF, the I/Q signals are digitized. Automatic
gain control (AGC), fine channel filtering, demodulation bit/packet synchronization are performed digitally.
The transmitter part is based on direct synthesis of the RF frequency. The frequency synthesizer includes a
completely on-chip LC VCO and a 90 degrees phase shifter for generating the I and Q LO signals to the
down-conversion mixers in receive mode.
The 26-MHz crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the
ADC and the digital part.
A memory mapped register interface is used for data access, configuration and status request by the CPU.
The digital baseband includes support for channel configuration, packet handling and data buffering.
For complete module descriptions, see the CC430 Family User's Guide, literature number SLAU259.
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CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant
generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Operating Modes
The CC430 has one active mode and five software selectable low-power modes of operation. An interrupt event
can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
•
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
–
•
–
–
–
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
FLL loop control remains active
•
•
Low-power mode 1 (LPM1)
–
–
–
CPU is disabled
FLL loop control is disabled
ACLK and SMCLK remain active, MCLK is disabled
Low-power mode 2 (LPM2)
–
–
–
–
CPU is disabled
MCLK and FLL loop control and DCOCLK are disabled
DCO's dc-generator remains enabled
ACLK remains active
•
•
Low-power mode 3 (LPM3)
–
–
–
–
CPU is disabled
MCLK, FLL loop control, and DCOCLK are disabled
DCO's dc-generator is disabled
ACLK remains active
Low-power mode 4 (LPM4)
–
–
–
–
–
–
CPU is disabled
ACLK is disabled
MCLK, FLL loop control, and DCOCLK are disabled
DCO's dc-generator is disabled
Crystal oscillator is stopped
Complete data retention
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 2. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power-Up
External Reset
Watchdog Timeout, Password
Violation
WDTIFG, KEYV (SYSRSTIV)(1) (2)
Reset
0FFFEh
63, highest
Flash Memory Password Violation
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV)(1) (3)
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
62
61
User NMI
NMI
Oscillator Fault
NMIIFG, OFIFG, ACCVIFG (SYSUNIV)(1) (3)
Flash Memory Access Violation
Comparator_B
Comparator_B Interrupt Flags (CBIV)(1)
WDTIFG
UCA0RXIFG, UCA0TXIFG (UCA0IV)(1)
Maskable
Maskable
Maskable
0FFF8h
0FFF6h
0FFF4h
60
59
58
Watchdog Interval Timer Mode
USCI_A0 Receive/Transmit
UCB0RXIFG, UCB0TXIFG, I2C Status Interrupt
Flags (UCB0IV)(1)
USCI_B0 Receive/Transmit
Maskable
0FFF2h
57
ADC12_A
(Reserved on CC430F612x)
ADC12IFG0 ... ADC12IFG15 (ADC12IV)(1)
Maskable
Maskable
Maskable
0FFF0h
0FFEEh
0FFECh
56
55
54
TA0
TA0CCR0 CCIFG0
TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1)
TA0
Radio Interface Interrupt Flags (RF1AIFIV)
Radio Core Interrupt Flags (RF1AIV)
RF1A CC1101-based Radio
Maskable
0FFEAh
53
DMA
TA1
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1)
Maskable
Maskable
0FFE8h
0FFE6h
52
51
TA1CCR0 CCIFG0
TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1)
TA1
Maskable
0FFE4h
50
I/O Port P1
I/O Port P2
P1IFG.0 to P1IFG.7 (P1IV)(1)
P2IFG.0 to P2IFG.7 (P2IV)(1)
Maskable
Maskable
0FFE2h
0FFE0h
49
48
LCD_B
(Reserved on CC430F513x)
LCD_B Interrupt Flags (LCDBIV)(1)
Maskable
0FFDEh
0FFDCh
47
46
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV)(1)
RTC_A
AES
Maskable
Maskable
AESRDYIFG
0FFDAh
0FFD8h
⋮
45
44
Reserved
Reserved(4)
⋮
0FF80h
0, lowest
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space.
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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Memory Organization
Table 3. Memory Organization
CC430F6137/F6127
CC430F5137(1)
CC430F6135/F6125
CC430F6126(1)
CC430F5133(1)
CC430F5135(1)
Main Memory
(flash)
Total
Size
32kB
32kB
16kB
8kB
Main: Interrupt
vector
00FFFFh–00FF80h
00FFFFh–00FF80h
00FFFFh–00FF80h
00FFFFh–00FF80h
Main: code
memory
Bank 0
32kB
00FFFFh–008000h
32kB
00FFFFh–008000h
16kB
00FFFFh–00C000h
8kB
00FFFFh–00E000h
Total
Size
4kB
2kB
2kB
2kB
RAM
Sect 1
2kB
not available
not available
not available
002BFFh–002400h
Sect 0
2kB
2kB
2kB
2kB
0023FFh–001C00h
0023FFh–001C00h
0023FFh–001C00h
0023FFh–001C00h
128 B
128 B
128 B
128 B
001AFFh to 001A80h
001AFFh to 001A80h
001AFFh to 001A80h
001AFFh to 001A80h
Device
Descriptor
128 B
128 B
128 B
128 B
001A7Fh to 001A00h
001A7Fh to 001A00h
001A7Fh to 001A00h
001A7Fh to 001A00h
Info A
Info B
Info C
Info D
BSL 3
BSL 2
BSL 1
BSL 0
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Information
memory (flash)
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
Bootstrap loader
(BSL) memory
(flash)
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
512 B
512 B
512 B
0011FFh to 001000h
0011FFh to 001000h
0011FFh to 001000h
0011FFh to 001000h
4 KB
000FFFh to 0h
4 KB
000FFFh to 0h
4 KB
000FFFh to 0h
4 KB
000FFFh to 0h
Peripherals
(1) All not mentioned memory regions are vacant memory and any access to them will cause a Vacant Memory Interrupt.
Bootstrap Loader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the
device memory via the BSL is protected by an user-defined password. BSL entry requires a specific entry
sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the features of the
BSL and its implementation, see the MSP430 Memory Programming User's Guide, literature number SLAU265.
Table 4. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.6
P1.5
VCC
VSS
Data receive
Power supply
Ground supply
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JTAG Operation
JTAG Standard Interface
The CC430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 5. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide, literature number SLAU278.
Table 5. JTAG Pin Requirements and Functions
DEVICE SIGNAL
PJ.3/TCK
Direction
FUNCTION
JTAG clock input
JTAG state control
JTAG data input/TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
IN
OUT
IN
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
IN
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the CC430 family supports the two wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 6. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide, literature number SLAU278.
Table 6. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
Direction
IN
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input/output
Power supply
IN, OUT
VSS
Ground supply
Flash Memory
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), or in-system by the CPU. The
CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash
memory include:
•
Flash memory has n segments of main memory and four segments of information memory (Info A to Info D)
of 128 bytes each. Each segment in main memory is 512 bytes in size.
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments Info A to Info D can be erased individually, or as a group with the main memory segments.
Segments Info A to Info D are also called information memory.
•
Segment A can be locked separately.
RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
•
•
•
RAM memory has n sectors of 2k bytes each.
Each sector 0 to n can be complete disabled, however data retention is lost.
Each sector 0 to n automatically enters low power retention mode when possible.
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Peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using all
instructions. For complete module descriptions, see the CC430 Family User's Guide, literature number SLAU259.
Oscillator and System Clock
The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an internal
very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an
integrated internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The UCS module
is designed to meet the requirements of both low system cost and low-power consumption. The UCS module
features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the
DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast
turn-on clock source and stabilizes in less than 5 µs. The UCS module provides the following clock signals:
•
•
•
•
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, the internal
low-frequency oscillator (VLO), or the trimmed low-frequency oscillator (REFO).
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
Digital I/O
There are up to five 8-bit I/O ports implemented: ports P1 through P5.
•
•
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Programmable drive strength on all ports.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P5) or word-wise in pairs (PA and PB).
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Port Mapping Controller
The port mapping controller allows the flexible and re-configurable mapping of digital functions to port pins of
ports P1 through P3.
Table 7. Port Mapping, Mnemonics, and Functions
Value
PxMAPy Mnemonic
Input Pin Function (PxDIR.y=0)
Output Pin Function (PxDIR.y=1)
0
PM_NONE
None
DVSS
Comparator_B output (on TA0 clock
input)
PM_CBOUT0
PM_TA0CLK
PM_CBOUT1
1(1)
TA0 clock input
-
-
Comparator_B output (on TA1 clock
input)
2(1)
PM_TA1CLK
PM_ACLK
TA1 clock input
None
-
3
4
5
6
ACLK output
PM_MCLK
None
MCLK output
PM_SMCLK
None
SMCLK output
PM_RTCCLK
PM_ADC12CLK
PM_DMAE0
None
RTCCLK output
-
ADC12CLK output
7(1)
DMA external trigger input
None
-
8
PM_SVMOUT
PM_TA0CCR0A
PM_TA0CCR1A
PM_TA0CCR2A
PM_TA0CCR3A
PM_TA0CCR4A
PM_TA1CCR0A
PM_TA1CCR1A
PM_TA1CCR2A
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCA0CLK
PM_UCB0STE
PM_UCB0SOMI
PM_UCB0SCL
PM_UCB0SIMO
PM_UCB0SDA
PM_UCB0CLK
PM_UCA0STE
PM_RFGDO0
PM_RFGDO1
PM_RFGDO2
Reserved
SVM output
9
TA0 CCR0 capture input CCI0A
TA0 CCR1 capture input CCI1A
TA0 CCR2 capture input CCI2A
TA0 CCR3 capture input CCI3A
TA0 CCR4 capture input CCI4A
TA1 CCR0 capture input CCI0A
TA1 CCR1 capture input CCI1A
TA1 CCR2 capture input CCI2A
TA0 CCR0 compare output Out0
TA0 CCR1 compare output Out1
TA0 CCR2 compare output Out2
TA0 CCR3 compare output Out3
TA0 CCR4 compare output Out4
TA1 CCR0 compare output Out0
TA1 CCR1 compare output Out1
TA1 CCR2 compare output Out2
10
11
12
13
14
15
16
USCI_A0 UART RXD (Direction controlled by USCI - input)
USCI_A0 SPI slave out master in (direction controlled by USCI)
USCI_A0 UART TXD (Direction controlled by USCI - output)
USCI_A0 SPI slave in master out (direction controlled by USCI)
USCI_A0 clock input/output (direction controlled by USCI)
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
USCI_B0 SPI slave out master in (direction controlled by USCI)
USCI_B0 I2C clock (open drain and direction controlled by USCI)
USCI_B0 SPI slave in master out (direction controlled by USCI)
USCI_B0 I2C data (open drain and direction controlled by USCI)
USCI_B0 clock input/output (direction controlled by USCI)
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
Radio GDO0 (direction controlled by Radio)
17(2)
18(2)
19(3)
20(4)
21(4)
22(5)
23
24
25
26
Radio GDO1 (direction controlled by Radio)
Radio GDO2 (direction controlled by Radio)
None
DVSS
(1) Input or output function is selected by the corresponding setting in the port direction register PxDIR.
(2) UART or SPI functionality is determined by the selected USCI mode.
(3) UCA0CLK function takes precedence over UCB0STE function. If the mapped pin is required as UCA0CLK input or output USCI_B0 will
be forced to 3-wire SPI mode even if 4-wire mode is selected.
(4) SPI or I2C functionality is determined by the selected USCI mode. In case the I2C functionality is selected the output of the mapped pin
drives only the logical 0 to VSS level.
(5) UCB0CLK function takes precedence over UCA0STE function. If the mapped pin is required as UCB0CLK input or output USCI_A0 will
be forced to 3-wire SPI mode even if 4-wire mode is selected.
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Table 7. Port Mapping, Mnemonics, and Functions (continued)
Value
27
PxMAPy Mnemonic
Reserved
Input Pin Function (PxDIR.y=0)
Output Pin Function (PxDIR.y=1)
None
None
None
None
DVSS
DVSS
DVSS
DVSS
28
Reserved
29
Reserved
30
Reserved
Disables the output driver as well as the input Schmitt-trigger to prevent
parasitic cross currents when applying analog signals.
31 (0FFh)(6)
PM_ANALOG
(6) The value of the PMPAP_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are
ignored resulting in a read out value of 31.
Table 8. Default Mapping
Pin
PxMAPy Mnemonic
PM_RFGDO0
Input Pin Function (PxDIR.y=0)
Output Pin Function (PxDIR.y=1)
Radio GDO0
P1.0/P1MAP0
P1.1/P1MAP1
None
None
PM_RFGDO2
Radio GDO2
USCI_B0 SPI slave out master in (direction controlled by USCI)/USCI_B0
I2C clock (open drain and direction controlled by USCI)
P1.2/P1MAP2
P1.3/P1MAP3
P1.4/P1MAP4
P1.5/P1MAP5
P1.6/P1MAP6
P1.7/P1MAP7
PM_UCB0SOMI/PM_UCB0SCL
PM_UCB0SIMO/PM_UCB0SDA
PM_UCB0CLK/PM_UCA0STE
PM_UCA0RXD/PM_UCA0SOMI
PM_UCA0TXD/PM_UCA0SIMO
PM_UCA0CLK/PM_UCB0STE
USCI_B0 SPI slave in master out (direction controlled by USCI)/USCI_B0
I2C data (open drain and direction controlled by USCI)
USCI_B0 clock input/output (direction controlled by USCI)/USCI_A0 SPI
slave transmit enable (direction controlled by USCI - input)
USCI_A0 UART RXD (Direction controlled by USCI - input)/USCI_A0 SPI
slave out master in (direction controlled by USCI)
USCI_A0 UART TXD (Direction controlled by USCI - output)/USCI_A0
SPI slave in master out (direction controlled by USCI)
USCI_A0 clock input/output (direction controlled by USCI)/USCI_B0 SPI
slave transmit enable (direction controlled by USCI - input)
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7
P3.0/P3MAP0
P3.1/P3MAP1
P3.2/P3MAP2
P3.3/P3MAP3
P3.4/P3MAP4
P3.5/P3MAP5
P3.6/P3MAP6
P3.7/P3MAP7
PM_CBOUT1/PM_TA1CLK
PM_TA1CCR0A
PM_TA1CCR1A
PM_TA1CCR2A
PM_RTCCLK
TA1 clock input
TA1 CCR0 capture input CCI0A
TA1 CCR1 capture input CCI1A
TA1 CCR2 capture input CCI2A
None
Comparator_B output
TA1 CCR0 compare output Out0
TA1 CCR1 compare output Out1
TA1 CCR2 compare output Out2
RTCCLK output
PM_SVMOUT
None
SVM output
PM_ACLK
None
ACLK output
PM_ADC12CLK/PM_DMAE0
PM_CBOUT0/PM_TA0CLK
PM_TA0CCR0A
PM_TA0CCR1A
PM_TA0CCR2A
PM_TA0CCR3A
PM_TA0CCR4A
PM_RFGDO1
DMA external trigger input
TA0 clock input
ADC12CLK output
Comparator_B output
TA0 CCR0 capture input CCI0A
TA0 CCR1 capture input CCI1A
TA0 CCR2 capture input CCI2A
TA0 CCR3 capture input CCI3A
TA0 CCR4 capture input CCI4A
None
TA0 CCR0 compare output Out0
TA0 CCR1 compare output Out1
TA0 CCR2 compare output Out2
TA0 CCR3 compare output Out3
TA0 CCR4 compare output Out4
Radio GDO1
PM_SMCLK
None
SMCLK output
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System Module (SYS)
The SYS module handles many of the system functions within the device. These include power on reset and
power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap
loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data
exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.
Table 9. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
SYSRSTIV , System Reset
ADDRESS
INTERRUPT EVENT
No interrupt pending
Brownout (BOR)
RST/NMI (POR)
DoBOR (BOR)
Reserved
VALUE
00h
PRIORITY
019Eh
02h
Highest
04h
06h
08h
Security violation (BOR)
SVSL (POR)
0Ah
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SVMH_OVP (POR)
DoPOR (POR)
WDT timeout (PUC)
WDT password violation (PUC)
KEYV flash password violation (PUC)
FLL unlock (PUC)
Peripheral area fetch (PUC)
PMM password violation (PUC)
Reserved
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h to 3Eh
00h
Lowest
Highest
SYSSNIV , System NMI
019Ch
No interrupt pending
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
DLYHIFG
08h
VMAIFG
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
VLRLIFG
10h
VLRHIFG
12h
Reserved
14h to 1Eh
00h
Lowest
Highest
SYSUNIV, User NMI
019Ah
No interrupt pending
NMIFG
02h
OFIFG
04h
ACCVIFG
06h
Reserved
08h to 1Eh
Lowest
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DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces
system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move
data to or from a peripheral.
Table 10. DMA Trigger Assignments(1)
Channel
Trigger
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
Reserved
2
3
4
5
6
Reserved
Reserved
Reserved
7
Reserved
Reserved
Reserved
8
Reserved
Reserved
Reserved
9
Reserved
Reserved
Reserved
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RFRXIFG
RFRXIFG
RFRXIFG
RFTXIFG
RFTXIFG
RFTXIFG
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
Reserved
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
Reserved
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ADC12IFGx(2)
Reserved
ADC12IFGx(2)
Reserved
ADC12IFGx(2)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPY ready
DMA2IFG
MPY ready
DMA0IFG
MPY ready
DMA1IFG
DMAE0
DMAE0
DMAE0
(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not
cause any DMA trigger event when selected.
(2) Only on CC430F613x and CC430F513x. Reserved on CC430F612x.
Watchdog Timer (WDT_A)
The primary function of the watchdog timer is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the timer can be configured as an interval timer and can generate interrupts at selected time
intervals.
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CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations.
AES128 Accelerator
The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys according to
the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.
Universal Serial Communication Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA.
The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
The USCI_Bn module provides support for SPI (3 or 4 pin) and I2C.
A USCI_A0 and USCI_B0 module are implemented.
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TA0
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple
capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 11. TA0 Signal Connections
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
PM_TA0CLK
ACLK (internal)
SMCLK (internal)
RFCLK/192(1)
PM_TA0CCR0A
DVSS
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
NA
PM_TA0CCR0A
PM_TA0CCR1A
CCR0
CCR1
CCR2
CCR3
TA0
DVSS
DVCC
VCC
PM_TA0CCR1A
CCI1A
ADC12 (internal)(2)
ADC12SHSx = {1}
CBOUT (internal)
CCI1B
TA1
TA2
TA3
DVSS
DVCC
GND
VCC
PM_TA0CCR2A
ACLK (internal)
DVSS
CCI2A
CCI2B
GND
PM_TA0CCR2A
PM_TA0CCR3A
DVCC
VCC
PM_TA0CCR3A
CCI3A
GDO1 from Radio
(internal)
CCI3B
DVSS
DVCC
GND
VCC
PM_TA0CCR4A
CCI4A
PM_TA0CCR4A
GDO2 from Radio
(internal)
CCI4B
CCR4
TA4
DVSS
DVCC
GND
VCC
(1) If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK.
(2) Only on CC430F613x and CC430F513x
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TA1
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support multiple
capture/compares, PWM outputs, and interval timing. TA1 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 12. TA1 Signal Connections
DEVICE OUTPUT
MODULE OUTPUT
SIGNAL
PZ
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
SIGNAL
PM_TA1CLK
ACLK (internal)
SMCLK (internal)
RFCLK/192(1)
TACLK
ACLK
Timer
NA
SMCLK
INCLK
CCI0A
PM_TA1CCR0A
PM_TA1CCR0A
RF Async. Output
(internal)
CCI0B
RF Async. Input (internal)
CCR0
TA0
DVSS
DVCC
GND
VCC
PM_TA1CCR1A
CBOUT (internal)
DVSS
CCI1A
CCI1B
GND
VCC
PM_TA1CCR1A
PM_TA1CCR2A
CCR1
CCR2
TA1
TA2
DVCC
PM_TA1CCR2A
ACLK (internal)
DVSS
CCI2A
CCI2B
GND
VCC
DVCC
(1) If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK.
Real-Time Clock (RTC_A)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated
real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers
that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar
mode integrates an internal calendar which compensates for months with less than 31 days and includes leap
year correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.
REF Voltage Reference
The reference module (REF) is responsible for generation of all critical reference voltages that can be used by
the various analog peripherals in the device. These include the ADC12_A, LCD_B, and COMP_B modules.
LCD_B (Only CC430F613x and CC430F612x)
The LCD_B driver generates the segment and common signals required to drive a Liquid Crystal Display (LCD).
The LCD_B controller has dedicated data memories to hold segment drive information. Common and segment
signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux LCDs are supported. The
module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is
possible to control the level of the LCD voltage and thus contrast by software. The module also provides an
automatic blinking capability for individual segments.
Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
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ADC12_A (Only CC430F613x and CC430F513x)
The ADC12_A module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any
CPU intervention.
Embedded Emulation Module (EEM, S Version)
The Embedded Emulation Module (EEM) supports real-time in-system debugging. The S version of the EEM
implemented on all devices has the following features:
•
•
•
•
•
Three hardware triggers/breakpoints on memory access
One hardware trigger/breakpoint on CPU register write access
Up to four hardware triggers can be combined to form complex triggers/breakpoints
One cycle counter
Clock control on module level
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Peripheral File Map
Table 13. Peripherals
OFFSET ADDRESS
RANGE
MODULE NAME
BASE ADDRESS
Special Functions (refer to Table 14)
PMM (refer to Table 15)
0100h
0120h
0140h
0150h
0158h
015Ch
0160h
0180h
01B0h
01C0h
01C8h
01D0h
01D8h
0200h
000h - 01Fh
000h - 00Fh
000h - 00Fh
000h - 007h
000h - 001h
000h - 001h
000h - 01Fh
000h - 01Fh
000h - 001h
000h - 007h
000h - 007h
000h - 007h
000h - 007h
000h - 01Fh
Flash Control (refer to Table 16)
CRC16 (refer to Table 17)
RAM Control (refer to Table 18)
Watchdog (refer to Table 19)
UCS (refer to Table 20)
SYS (refer to Table 21)
Shared Reference (refer to Table 22)
Port Mapping Control (refer to Table 23)
Port Mapping Port P1 (refer to Table 24)
Port Mapping Port P2 (refer to Table 25)
Port Mapping Port P3 (refer to Table 26)
Port P1/P2 (refer to Table 27)
Port P3/P4 (P4 not available on CC430F513x)
(refer to Table 28)
0220h
000h - 01Fh
Port P5 (refer to Table 29)
Port PJ (refer to Table 30)
0240h
0320h
0340h
0380h
04A0h
04C0h
0500h
0510h
0520h
0530h
05C0h
05E0h
000h - 01Fh
000h - 01Fh
000h - 03Fh
000h - 03Fh
000h - 01Fh
000h - 02Fh
000h - 00Fh
000h - 00Fh
000h - 00Fh
000h - 00Fh
000h - 01Fh
000h - 01Fh
TA0 (refer to Table 31)
TA1 (refer to Table 32)
RTC_A (refer to Table 33)
32-bit Hardware Multiplier (refer to Table 34)
DMA Module Control (refer to Table 35)
DMA Channel 0 (refer to Table 36)
DMA Channel 1 (refer to Table 37)
DMA Channel 2 (refer to Table 38)
USCI_A0 (refer to Table 39)
USCI_B0 (refer to Table 40)
ADC12 (refer to Table 41, only CC430F613x and
CC430F513x)
0700h
000h - 03Fh
Comparator_B (refer to Table 42)
AES Accelerator (refer to Table 43)
08C0h
09C0h
000h - 00Fh
000h - 00Fh
LCD_B (refer to Table 44, only CC430F613x and
CC430F612x)
0A00h
0F00h
000h - 05Fh
000h - 03Fh
Radio Interface (refer to Table 45)
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Table 14. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
SFRIE1
OFFSET
SFR interrupt enable
SFR interrupt flag
00h
02h
04h
SFRIFG1
SFR reset pin control
SFRRPCR
Table 15. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
PMMCTL0
OFFSET
PMM Control 0
00h
02h
04h
06h
0Ch
0Eh
10h
PMM control 1
PMMCTL1
SVSMHCTL
SVSMLCTL
PMMIFG
SVS high side control
SVS low side control
PMM interrupt flags
PMM interrupt enable
PMM power mode 5 control
PMMIE
PM5CTL0
Table 16. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
Flash control 3
Flash control 4
FCTL1
FCTL3
FCTL4
00h
04h
06h
Table 17. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
CRC16DI
OFFSET
CRC data input
00h
02h
04h
06h
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
Table 18. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
REGISTER
RCCTL0
OFFSET
OFFSET
OFFSET
RAM control 0
00h
00h
Table 19. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
WDTCTL
Watchdog timer control
Table 20. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
UCSCTL0
UCS control 0
UCS control 1
UCS control 2
UCS control 3
UCS control 4
UCS control 5
UCS control 6
UCS control 7
UCS control 8
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
UCSCTL1
UCSCTL2
UCSCTL3
UCSCTL4
UCSCTL5
UCSCTL6
UCSCTL7
UCSCTL8
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Table 21. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
SYSCTL
OFFSET
System control
00h
02h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
Bootstrap loader configuration area
JTAG mailbox control
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus Error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
SYSSNIV
SYSRSTIV
Table 22. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
REFCTL
OFFSET
OFFSET
Shared reference control
00h
Table 23. Port Mapping Control Registers (Base Address: 01C0h)
REGISTER DESCRIPTION
REGISTER
PMAPKEYID
PMAPCTL
Port mapping key register
00h
02h
Port mapping control register
Table 24. Port Mapping Port P1 Registers (Base Address: 01C8h)
REGISTER DESCRIPTION
REGISTER
P1MAP0
OFFSET
OFFSET
OFFSET
Port P1.0 mapping register
Port P1.1 mapping register
Port P1.2 mapping register
Port P1.3 mapping register
Port P1.4 mapping register
Port P1.5 mapping register
Port P1.6 mapping register
Port P1.7 mapping register
00h
01h
02h
03h
04h
05h
06h
07h
P1MAP1
P1MAP2
P1MAP3
P1MAP4
P1MAP5
P1MAP6
P1MAP7
Table 25. Port Mapping Port P2 Registers (Base Address: 01D0h)
REGISTER DESCRIPTION
REGISTER
P2MAP0
Port P2.0 mapping register
Port P2.1 mapping register
Port P2.2 mapping register
Port P2.3 mapping register
Port P2.4 mapping register
Port P2.5 mapping register
Port P2.6 mapping register
Port P2.7 mapping register
00h
01h
02h
03h
04h
05h
06h
07h
P2MAP2
P2MAP2
P2MAP3
P2MAP4
P2MAP5
P2MAP6
P2MAP7
Table 26. Port Mapping Port P3 Registers (Base Address: 01D8h)
REGISTER DESCRIPTION
REGISTER
P3MAP0
P3MAP3
Port P3.0 mapping register
Port P3.1 mapping register
00h
01h
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Table 26. Port Mapping Port P3 Registers (Base Address: 01D8h) (continued)
REGISTER DESCRIPTION
REGISTER
P3MAP2
OFFSET
Port P3.2 mapping register
Port P3.3 mapping register
Port P3.4 mapping register
Port P3.5 mapping register
Port P3.6 mapping register
Port P3.7 mapping register
02h
03h
04h
05h
06h
07h
P3MAP3
P3MAP4
P3MAP5
P3MAP6
P3MAP7
Table 27. Port P1/P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
02h
04h
06h
08h
0Ah
0Eh
18h
1Ah
1Ch
01h
03h
05h
07h
09h
0Bh
1Eh
19h
1Bh
1Dh
Port P1 output
Port P1 direction
P1OUT
P1DIR
P1REN
P1DS
P1SEL
P1IV
Port P1 pullup/pulldown enable
Port P1 drive strength
Port P1 selection
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
P1IES
P1IE
P1IFG
P2IN
Port P2 input
Port P2 output
P2OUT
P2DIR
P2REN
P2DS
P2SEL
P2IV
Port P2 direction
Port P2 pullup/pulldown enable
Port P2 drive strength
Port P2 selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IES
P2IE
P2IFG
Table 28. Port P3/P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P3 output
P3OUT
P3DIR
P3REN
P3DS
Port P3 direction
Port P3 pullup/pulldown enable
Port P3 drive strength
Port P3 selection
P3SEL
P4IN
Port P4 input
Port P4 output
P4OUT
P4DIR
P4REN
P4DS
Port P4 direction
Port P4 pullup/pulldown enable
Port P4 drive strength
Port P4 selection
P4SEL
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Table 29. Port P5 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
02h
04h
06h
08h
0Ah
Port P5 output
Port P5 direction
P5OUT
P5DIR
P5REN
P5DS
Port P5 pullup/pulldown enable
Port P5 drive strength
Port P5 selection
P5SEL
Table 30. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
02h
04h
06h
08h
Port PJ output
PJOUT
PJDIR
PJREN
PJDS
Port PJ direction
Port PJ pullup/pulldown enable
Port PJ drive strength
Table 31. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
TA0CTL
OFFSET
TA0 control
00h
02h
04h
06h
08h
0Ah
10h
12h
14h
16h
18h
1Ah
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
TA0 counter register
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0CCTL3
TA0CCTL4
TA0R
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
Capture/compare register 3
Capture/compare register 4
TA0 expansion register 0
TA0 interrupt vector
TA0CCR0
TA0CCR1
TA0CCR2
TA0CCR3
TA0CCR4
TA0EX0
TA0IV
Table 32. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
TA1CTL
OFFSET
TA1 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter register
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TA1 expansion register 0
TA1 interrupt vector
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
TA1IV
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Table 33. Real Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
RTCCTL0
OFFSET
RTC control 0
00h
01h
02h
03h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
RTC control 1
RTCCTL1
RTC control 2
RTCCTL2
RTC control 3
RTCCTL3
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTCPS0CTL
RTCPS1CTL
RTCPS0
RTC prescaler 1
RTCPS1
RTC interrupt vector word
RTC seconds/counter register 1
RTC minutes/counter register 2
RTC hours/counter register 3
RTC day of week/counter register 4
RTC days
RTCIV
RTCSEC/RTCNT1
RTCMIN/RTCNT2
RTCHOUR/RTCNT3
RTCDOW/RTCNT4
RTCDAY
RTC month
RTCMON
RTC year low
RTCYEARL
RTCYEARH
RTCAMIN
RTC year high
RTC alarm minutes
RTC alarm hours
RTCAHOUR
RTCADOW
RTCADAY
RTC alarm day of week
RTC alarm days
Table 34. 32-bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension register
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control register 0
RES3
MPY32CTL0
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Table 35. DMA Module Control Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
DMACTL0
OFFSET
OFFSET
OFFSET
OFFSET
DMA module control 0
DMA module control 1
DMA module control 2
DMA module control 3
DMA module control 4
DMA interrupt vector
00h
02h
04h
06h
08h
0Ah
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
Table 36. DMA Channel 0 Registers (Base Address: 0510h)
REGISTER DESCRIPTION
REGISTER
DMA0CTL
DMA channel 0 control
00h
02h
04h
06h
08h
0Ah
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
Table 37. DMA Channel 1 Registers (Base Address: 0520h)
REGISTER DESCRIPTION
REGISTER
DMA1CTL
DMA channel 1 control
00h
02h
04h
06h
08h
0Ah
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
Table 38. DMA Channel 2 Registers (Base Address: 0530h)
REGISTER DESCRIPTION
REGISTER
DMA2CTL
DMA channel 2 control
00h
02h
04h
06h
08h
0Ah
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
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Table 39. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
UCA0CTL0
OFFSET
USCI control 0
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 1
UCA0CTL1
UCA0BR0
USCI baud rate 0
USCI baud rate 1
UCA0BR1
USCI modulation control
USCI status
UCA0MCTL
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA0IFG
UCA0IV
Table 40. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
UCB0CTL0
OFFSET
USCI synchronous control 0
USCI synchronous control 1
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
UCB0CTL1
UCB0BR0
UCB0BR1
UCB0STAT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA
UCB0I2CSA
UCB0IE
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB0IFG
USCI interrupt vector word
UCB0IV
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Table 41. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
ADC12CTL0
OFFSET
Control register 0
00h
02h
04h
0Ah
0Ch
0Eh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
Control register 1
ADC12CTL1
Control register 2
ADC12CTL2
Interrupt-flag register
Interrupt-enable register
Interrupt-vector-word register
ADC12IFG
ADC12IE
ADC12IV
ADC memory-control register 0
ADC memory-control register 1
ADC memory-control register 2
ADC memory-control register 3
ADC memory-control register 4
ADC memory-control register 5
ADC memory-control register 6
ADC memory-control register 7
ADC memory-control register 8
ADC memory-control register 9
ADC memory-control register 10
ADC memory-control register 11
ADC memory-control register 12
ADC memory-control register 13
ADC memory-control register 14
ADC memory-control register 15
Conversion memory 0
ADC12MCTL0
ADC12MCTL1
ADC12MCTL2
ADC12MCTL3
ADC12MCTL4
ADC12MCTL5
ADC12MCTL6
ADC12MCTL7
ADC12MCTL8
ADC12MCTL9
ADC12MCTL10
ADC12MCTL11
ADC12MCTL12
ADC12MCTL13
ADC12MCTL14
ADC12MCTL15
ADC12MEM0
ADC12MEM1
ADC12MEM2
ADC12MEM3
ADC12MEM4
ADC12MEM5
ADC12MEM6
ADC12MEM7
ADC12MEM8
ADC12MEM9
ADC12MEM10
ADC12MEM11
ADC12MEM12
ADC12MEM13
ADC12MEM14
ADC12MEM15
Conversion memory 1
Conversion memory 2
Conversion memory 3
Conversion memory 4
Conversion memory 5
Conversion memory 6
Conversion memory 7
Conversion memory 8
Conversion memory 9
Conversion memory 10
Conversion memory 11
Conversion memory 12
Conversion memory 13
Conversion memory 14
Conversion memory 15
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Table 42. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
CBCTL0
OFFSET
Comp_B control register 0
Comp_B control register 1
Comp_B control register 2
Comp_B control register 3
Comp_B interrupt register
Comp_B interrupt vector word
00h
02h
04h
06h
0Ch
0Eh
CBCTL1
CBCTL2
CBCTL3
CBINT
CBIV
Table 43. AES Accelerator Registers (Base Address: 09C0h)
REGISTER DESCRIPTION
REGISTER
AESACTL0
OFFSET
AES accelerator control register 0
Reserved
00h
02h
AES accelerator status register
AES accelerator key register
AES accelerator data in register
AES accelerator data out register
AESASTAT
AESAKEY
AESADIN
04h
06h
008h
00Ah
AESADOUT
Table 44. LCD_B Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
LCDBCTL0
OFFSET
LCD_B control register 0
LCD_B control register 1
LCD_B blinking control register
LCD_B memory control register
LCD_B voltage control register
LCD_B port control register 0
LCD_B port control register 1
LCD_B charge pump control register
LCD_B interrupt vector word
LCD_B memory 1
000h
002h
004h
006h
008h
00Ah
00Ch
012h
01Eh
020h
021h
LCDBCTL1
LCDBBLKCTL
LCDBMEMCTL
LCDBVCTL
LCDBPCTL0
LCDBPCTL1
LCDBCTL0
LCDBIV
LCDM1
LCD_B memory 2
LCDM2
...
LCD_B memory 14
LCDM14
LCDBM1
LCDBM2
02Dh
040h
041h
LCD_B blinking memory 1
LCD_B blinking memory 2
...
LCD_B blinking memory 14
LCDBM14
04Dh
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Table 45. Radio Interface Registers (Base Address: 0F00h)
REGISTER DESCRIPTION
REGISTER
RF1AIFCTL0
OFFSET
Radio interface control register 0
Radio interface control register 1
Radio interface error flag register
Radio interface error vector word
Radio interface interrupt vector word
Radio instruction word register
00h
02h
06h
0Ch
0Eh
10h
12h
14h
16h
20h
22h
24h
28h
2Ah
2Ch
30h
32h
34h
36h
38h
RF1AIFCTL1
RF1AIFERR
RF1AIFERRV
RF1AIFIV
RF1AINSTRW
RF1AINSTR1W
RF1AINSTR2W
RF1ADINW
RF1ASTATW
RF1ASTAT1W
RF1AISTAT2W
RF1ADOUTW
RF1ADOUT1W
RF1ADOUT2W
RF1AIN
Radio instruction word register, 1-byte auto-read
Radio instruction word register, 2-byte auto-read
Radio data in register
Radio status word register
Radio status word register, 1-byte auto-read
Radio status word register, 2-byte auto-read
Radio data out register
Radio data out register, 1-byte auto-read
Radio data out register, 2-byte auto-read
Radio core signal input register
Radio core interrupt flag register
Radio core interrupt edge select register
Radio core interrupt enable register
Radio core interrupt vector word
RF1AIFG
RF1AIES
RF1AIE
RF1AIV
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Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to VSS
–0.3 V to 4.1 V
–0.3 V to (VCC + 0.3 V),
4.1 V Max
Voltage applied to any pin (excluding VCORE, RF_P, RF_N, and R_BIAS)(2)
Voltage applied to VCORE, RF_P, RF_N, and R_BIAS(2)
Input RF level at pins RF_P and RF_N
Diode current at any device terminal
–0.3 V to 2.0 V
10 dBm
±2 mA
Storage temperature range(3), Tstg
–55°C to 105°C
95°C
Maximum junction temperature, TJ
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS
.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics CC430F51xx
Low-K board
High-K board
48 QFN (RGZ)
48 QFN (RGZ)
98°C/W
28°C/W
qJA
Junction to ambient thermal resistance, still air
Thermal Packaging Characteristics CC430F61xx
Low-K board
High-K board
64 QFN (RGC)
64 QFN (RGC)
83°C/W
26°C/W
qJA
Junction to ambient thermal resistance, still air
Recommended Operating Conditions
MIN NOM
MAX UNIT
Supply voltage range applied at all DVCC and AVCC
PMMCOREVx = 0 (default
after POR)
1.8
3.6
V
pins(1) during program execution and flash programming
with PMM default settings. Radio is not operational with
PMMCOREVx = 0, 1.(2)
VCC
PMMCOREVx = 1
PMMCOREVx = 2
PMMCOREVx = 3
2.0
2.2
2.4
3.6
3.6
3.6
V
V
V
Supply voltage range applied at all DVCC and AVCC
pins(1) during program execution, flash programming and
radio operation with PMM default settings.(2)
VCC
Supply voltage range applied at all DVCC and AVCC
pins(1) during program execution, flash programming and PMMCOREVx = 2,
VCC
radio operation with PMMCOREVx = 2, high-side SVS
level lowered (SVSHRVLx=SVSHRRRLx=1) or high-side
SVS disabled (SVSHE=0).(3) (2)
SVSHRVLx=SVSHRRRLx=1
or SVSHE=0
2.0
3.6
V
Supply voltage applied at the exposed die attach VSS and
AVSS pin
VSS
0
V
TA
Operating free-air temperature
Operating junction temperature
Recommended capacitor at VCORE
–40
–40
470
85
85
°C
°C
nF
TJ
CVCORE
CDVCC
CVCORE
/
Capacitor ratio of capacitor at DVCC to capacitor at
VCORE
10
0
PMMCOREVx = 0
(default condition)
8
MHz
Processor (MCLK) frequency(4) (see Figure 2)
PMMCOREVx = 1
PMMCOREVx = 2
PMMCOREVx = 3
0
0
0
12 MHz
16 MHz
20 MHz
fSYSTEM
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3) Lowering the high-side SVS level or disabling the high-side SVS might cause the LDO to operate out of regulation but the core voltage
will still stay within it's limits and is still supervised by the low-side SVS ensuring reliable operation.
(4) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
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Recommended Operating Conditions (continued)
MIN NOM
MAX UNIT
PINT
PIO
Internal power dissipation
VCC x I(DVCC)
W
(VCC - VIOH) x IIOH
VIOL x IIOL
+
I/O power dissipation of I/O pins powered by DVCC
Maximum allowed power dissipation, PMAX > PIO + PINT
W
W
PMAX
(TJ - TA)/qJA
20
16
12
3
2, 3
2
1, 2
1, 2, 3
1
8
0
0, 1
0, 1, 2
0, 1, 2, 3
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 2. Maximum System Frequency
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
(2) (3)
over recommended operating free-air temperature (unless otherwise noted)(1)
FREQUENCY (fDCO = fMCLK = fSMCLK
)
EXECUTION
MEMORY
PARAMETER
VCC
PMMCOREVx
1 MHz
8 MHz 12 MHz 16 MHz
20 MHz
UNIT
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
0
1
2
3
0
1
2
3
0.23 0.26 1.35 1.60
0.25 0.28 1.55
0.27 0.30 1.75
0.28 0.32 1.85
0.18 0.20 0.95 1.10
0.20 0.22 1.10
0.21 0.24 1.20
0.22 0.25 1.30
2.30 2.65
2.60
(4)
IAM, Flash
Flash
RAM
3.0 V
mA
3.45 3.90
3.65
2.75
4.55 5.10
3.10 3.60
1.60 1.85
1.80
(5)
IAM, RAM
3.0 V
mA
2.40 2.70
2.50
1.90
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
(4) Active mode supply current when program executes in flash at a nominal supply voltage of 3.0 V.
(5) Active mode supply current when program executes in RAM at a nominal supply voltage of 3.0 V.
Typical Characteristics - Active Mode Supply Currents
Active Mode Supply Current
vs
MCLK Frequency
5
VCC = 3.0 V
PMMVCOREx=3
4
3
PMMVCOREx=2
2
PMMVCOREx=1
1
PMMVCOREx=0
0
0
5
10
15
20
MCLK Frequency - MHz
Figure 3.
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(2)
Temperature (TA)
PARAMETER
VCC
PMMCOREVx
-40°C
TYP MAX
25°C
MAX
100
60°C
MAX
100
85°C
MAX
80 100
UNIT
TYP
80
TYP
80
TYP
2.2 V
3.0 V
2.2 V
3.0 V
0
3
0
3
0
1
2
3
0
1
2
3
0
1
2
3
80
90
100
110
11
(4)
(4)
ILPM0,1MHz
Low-power mode 0(3)
Low-power mode 2(5)
µA
µA
90
6.5
7.5
2.0
2.1
2.2
2.2
1.1
1.2
1.3
1.3
1.0
1.1
1.2
1.2
110
11
90
6.5
7.5
3.0
3.2
3.4
3.5
2.1
2.3
2.5
2.6
2.0
2.2
2.4
2.5
110
11
90
6.5
7.5
4.4
4.8
5.1
5.3
3.5
3.9
4.2
4.4
3.4
3.8
4.1
4.3
110
11
6.5
7.5
1.8
1.9
2.0
2.0
0.9
1.0
1.1
1.1
0.8
0.9
1.0
1.0
ILPM2
12
12
12
12
2.6
4.0
5.9
Low-power mode 3, crystal
ILPM3,XT1LF
ILPM3,VLO
ILPM4
3.0 V
3.0 V
3.0 V
µA
µA
µA
(4)
mode(6)
2.9
2.3
4.8
3.7
7.4
5.6
Low-power mode 3,
(4)
VLO mode(7)
2.6
2.2
4.5
3.6
7.1
5.5
Low-power mode 4(8)
(4)
2.5
4.4
7.0
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
(4) Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML).
High side monitor disabled (SVMH). RAM retention enabled.
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1
MHz operation, DCO bias generator enabled.
(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
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Typical Characteristics - Low-Power Mode Supply Currents
LPM3 Supply Current
vs
LPM4 Supply Current
vs
Temperature
Temperature
5
4
3
2
1
0
5
4
3
2
1
0
VCC = 3.0 V
VDD = 3.0 V
PMMCOREVx = 3
PMMCOREVx = 0
PMMCOREVx = 3
PMMCOREVx = 0
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
Figure 4.
Figure 5.
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Low-Power Mode with LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(2)
Temperature (TA)
PARAMETER
VCC
PMMCOREVx
-40°C
TYP MAX
2.2
25°C
TYP MAX
2.4
60°C
TYP MAX
3.5
85°C
TYP MAX
UNIT
0
1
2
3
0
1
2
3
0
1
2
0
1
2
3
4.9
5.3
5.6
5.8
5.8
6.2
6.5
6.7
Low-power mode 3
(LPM3) current, LCD
4-mux mode, external
biasing(3) (4)
ILPM3
LCD,
ext. bias
2.3
2.4
2.4
3.1
3.2
3.3
3.3
2.5
2.6
2.6
3.3
3.4
3.5
3.5
4.0
4.1
4.2
4.2
4.3
4.5
4.5
3.7
3.9
4.0
4.3
4.5
4.7
4.8
3.0 V
µA
4.0
7.4
Low-power mode 3
(LPM3) current, LCD
4-mux mode, internal
biasing, charge pump
disabled(3) (5)
ILPM3
LCD,
int. bias
3.0 V
2.2 V
3.0 V
µA
µA
4.3
8.9
Low-power mode 3
(LPM3) current, LCD
4-mux mode, internal
biasing, charge pump
enabled(3) (6)
ILPM3
LCD,CP
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML).
High side monitor disabled (SVMH). RAM retention enabled.
(4) LCDMx = 11 (4-mux mode), LCDREXT=1, LCDEXTBIAS=1 (external biasing), LCD2B=0 (1/3 bias), LCDCPEN=0 (charge pump
disabled), LCDSSEL=0, LCDPREx=101, LCDDIVx=00011 (fLCD = 32768 Hz/32/4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2,...=0, odd segments S1, S3,...=1. No LCD panel load.
(5) LCDMx = 11 (4-mux mode), LCDREXT=0, LCDEXTBIAS=0 (internal biasing), LCD2B=0 (1/3 bias), LCDCPEN=0 (charge pump
disabled), LCDSSEL=0, LCDPREx=101, LCDDIVx=00011 (fLCD = 32768 Hz/32/4 = 256 Hz)
Even segments S0, S2,...=0, odd segments S1, S3,...=1. No LCD panel load.
(6) LCDMx = 11 (4-mux mode), LCDREXT=0, LCDEXTBIAS=0 (internal biasing), LCD2B=0 (1/3 bias), LCDCPEN=1 (charge pump
enabled), VLCDx=1000 (VLCD= 3 V typ.), LCDSSEL=0, LCDPREx=101, LCDDIVx=00011 (fLCD = 32768 Hz/32/4 = 256 Hz)
Even segments S0, S2,...=0, odd segments S1, S3,...=1. No LCD panel load.
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MAX UNIT
Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.8 V
3 V
MIN
0.80
1.50
0.45
0.75
0.3
TYP
1.40
V
VIT+
Positive-going input threshold voltage
2.10
1.8 V
3 V
1.00
V
VIT–
Negative-going input threshold voltage
1.65
1.8 V
3 V
0.8
V
Vhys
RPull
Input voltage hysteresis (VIT+ – VIT–
Pullup/pulldown resistor
)
0.4
1.0
For pullup: VIN = VSS
For pulldown: VIN = VCC
20
35
5
50
kΩ
CI
Input capacitance
VIN = VSS or VCC
(1) (2)
pF
nA
Ilkg(Px.x)
High-impedance leakage current
1.8 V/3 V
1.8 V/3 V
±50
Ports with interrupt capability
External interrupt timing (External trigger pulse (see block diagram and
t(int)
20
ns
width to set interrupt flag)(3)
terminal function
descriptions).
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
(3) An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals shorter
than t(int)
.
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Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA, PxDS.y = 0(2)
I(OHmax) = –3 mA, PxDS.y = 0(3)
I(OHmax) = –2 mA, PxDS.y = 0(2)
I(OHmax) = –6 mA, PxDS.y = 0(3)
I(OLmax) = 1 mA, PxDS.y = 0(2)
I(OLmax) = 3 mA, PxDS.y = 0(3)
I(OLmax) = 2 mA, PxDS.y = 0(2)
I(OLmax) = 6 mA, PxDS.y = 0(3)
I(OHmax) = –3 mA, PxDS.y = 1(2)
I(OHmax) = –10 mA, PxDS.y = 1(3)
I(OHmax) = –5 mA, PxDS.y = 1(2)
I(OHmax) = –15 mA, PxDS.y = 1(3)
I(OLmax) = 3 mA, PxDS.y = 1(2)
I(OLmax) = 10 mA, PxDS.y = 1(3)
I(OLmax) = 5 mA, PxDS.y = 1(2)
I(OLmax) = 15 mA, PxDS.y = 1(3)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
VCC
High-level output voltage,
Reduced Drive Strength(1)
VOH
VOL
VOH
VOL
V
VCC
3.0 V
1.8 V
3.0 V
1.8 V
3 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
Low-level output voltage,
Reduced Drive Strength(1)
V
V
V
VCC – 0.25
VCC
VCC
VCC
VCC
VCC – 0.60
VCC – 0.25
VCC – 0.60
High-level output voltage,
Full Drive Strength
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
1.8 V
3 V
Low-level output voltage,
Full Drive Strength
VCC = 1.8 V
PMMCOREVx = 0
16
25
16
25
Port output frequency
(with load)
(4) (5)
fPx.y
CL = 20 pF, RL
MHz
MHz
VCC = 3 V
PMMCOREVx = 2
VCC = 1.8 V
PMMCOREVx = 0
fPort_CLK
Clock output frequency
CL = 20 pF(5)
VCC = 3 V
PMMCOREVx = 2
(1) Selecting reduced drive strength may reduce EMI.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(3) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
(4) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS
.
(5) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
25
20
15
10
5
8
7
6
5
4
3
2
1
0
VCC = 3.0 V
P4.3
VCC = 1.8 V
TA = 25°C
P4.3
TA = 25°C
TA = 85°C
TA = 85°C
0
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
VOL - Low-Level Output Voltage - V
VOL - Low-Level Output Voltage - V
Figure 6.
Figure 7.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0
0
VCC = 3.0 V
P4.3
VCC = 1.8 V
P4.3
-1
-2
-3
-4
-5
-6
-7
-8
-5
-10
-15
-20
-25
TA = 85°C
TA = 25°C
TA = 85°C
TA = 25°C
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
VOH - High-Level Output Voltage - V
VOH - High-Level Output Voltage - V
Figure 8.
Figure 9.
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Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
60
50
40
30
20
10
0
25
20
15
10
5
VCC = 3.0 V
P4.3
TA = 25°C
TA = 85°C
VCC = 1.8 V
P4.3
TA = 25°C
TA = 85°C
0
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
VOL - Low-Level Output Voltage - V
VOL - Low-Level Output Voltage - V
Figure 10.
Figure 11.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0
0
VCC = 3.0 V
P4.3
VCC = 1.8 V
P4.3
-10
-20
-30
-40
-50
-60
-5
-10
-15
-20
-25
TA = 85°C
TA = 25°C
TA = 85°C
TA = 25°C
1.5
0
0.5
1
2
2.5
3
3.5
0
0.5
1
1.5
2
VOH - High-Level Output Voltage - V
VOH - High-Level Output Voltage - V
Figure 12.
Figure 13.
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MAX UNIT
Crystal Oscillator, XT1, Low-Frequency Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
0.075
Differential XT1 oscillator crystal
fOSC = 32768 Hz, XTS = 0,
ΔIDVCC.LF
current consumption from lowest XT1BYPASS = 0, XT1DRIVEx = 2,
3.0 V
0.170
µA
drive setting, LF mode
TA = 25°C
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
0.290
XT1 oscillator crystal frequency,
LF mode
fXT1,LF0
XTS = 0, XT1BYPASS = 0
32768
Hz
XT1 oscillator logic-level
square-wave input frequency,
LF mode
fXT1,LF,SW
XTS = 0, XT1BYPASS = 1(2) (3)
10 32.768
210
50 kHz
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
LF crystals(4)
OALF
kΩ
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
XTS = 0, XCAPx = 0(6)
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
2
5.5
Integrated effective load
capacitance, LF mode(5)
CL,eff
pF
8.5
12.0
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Duty cycle LF mode
30
10
70
%
Oscillator fault frequency,
fFault,LF
XTS = 0(8)
10000
Hz
LF mode(7)
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C,
1000
500
CL,eff = 6 pF
tSTART,LF
Startup time, LF mode
3.0 V
ms
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C,
CL,eff = 12 pF
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this datasheet.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
(a) For XT1DRIVEx = 0, CL,eff ≤ 6 pF
(b) For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF
(c) For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF
(d) For XT1DRIVEx = 3, CL,eff ≥ 6 pF
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
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Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
VCC
MIN
TYP
9.4
0.5
4
MAX UNIT
14 kHz
%/°C
fVLO
Measured at ACLK
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
6
dfVLO/dT
Measured at ACLK(1)
Measured at ACLK(2)
Measured at ACLK
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
%/V
40
50
60
%
(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
3
MAX UNIT
IREFO
fREFO
REFO oscillator current consumption TA = 25°C
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
3 V
µA
Hz
REFO frequency calibrated
Measured at ACLK
32768
Full temperature range
±3.5
±1.5
%
%
REFO absolute tolerance calibrated
REFO frequency temperature drift
REFO frequency supply voltage drift Measured at ACLK(2)
TA = 25°C
Measured at ACLK(1)
dfREFO/dT
dfREFO/dVCC
Duty cycle
tSTART
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
0.01
1.0
50
%/°C
%/V
%
Measured at ACLK
40
60
REFO startup time
40%/60% duty cycle
25
µs
(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
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DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DCORSELx = 0, DCOx = 0, MODx = 0
DCORSELx = 0, DCOx = 31, MODx = 0
DCORSELx = 1, DCOx = 0, MODx = 0
DCORSELx = 1, DCOx = 31, MODx = 0
DCORSELx = 2, DCOx = 0, MODx = 0
DCORSELx = 2, DCOx = 31, MODx = 0
DCORSELx = 3, DCOx = 0, MODx = 0
DCORSELx = 3, DCOx = 31, MODx = 0
DCORSELx = 4, DCOx = 0, MODx = 0
DCORSELx = 4, DCOx = 31, MODx = 0
DCORSELx = 5, DCOx = 0, MODx = 0
DCORSELx = 5, DCOx = 31, MODx = 0
DCORSELx = 6, DCOx = 0, MODx = 0
DCORSELx = 6, DCOx = 31, MODx = 0
DCORSELx = 7, DCOx = 0, MODx = 0
DCORSELx = 7, DCOx = 31, MODx = 0
MIN
0.07
0.70
0.15
1.47
0.32
3.17
0.64
6.07
1.3
TYP
MAX UNIT
0.20 MHz
1.70 MHz
0.36 MHz
3.45 MHz
0.75 MHz
7.38 MHz
1.51 MHz
14.0 MHz
3.2 MHz
fDCO(0,0)
fDCO(0,31)
fDCO(1,0)
fDCO(1,31)
fDCO(2,0)
fDCO(2,31)
fDCO(3,0)
fDCO(3,31)
fDCO(4,0)
fDCO(4,31)
fDCO(5,0)
fDCO(5,31)
fDCO(6,0)
fDCO(6,31)
fDCO(7,0)
fDCO(7,31)
DCO frequency (0, 0)
DCO frequency (0, 31)
DCO frequency (1, 0)
DCO frequency (1, 31)
DCO frequency (2, 0)
DCO frequency (2, 31)
DCO frequency (3, 0)
DCO frequency (3, 31)
DCO frequency (4, 0)
DCO frequency (4, 31)
DCO frequency (5, 0)
DCO frequency (5, 31)
DCO frequency (6, 0)
DCO frequency (6, 31)
DCO frequency (7, 0)
DCO frequency (7, 31)
12.3
2.5
28.2 MHz
6.0 MHz
23.7
4.6
54.1 MHz
10.7 MHz
88.0 MHz
19.6 MHz
135 MHz
39.0
8.5
60
Frequency step between range
DCORSEL and DCORSEL + 1
SDCORSEL
SDCO
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3 ratio
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
40
1.12 ratio
Duty cycle
dfDCO/dT
Measured at SMCLK
DCO frequency temperature drift fDCO = 1 MHz
50
0.1
1.9
60
%
%/°C
%/V
dfDCO/dVCC
DCO frequency voltage drift
fDCO = 1 MHz
Typical DCO Frequency, VCC = 3.0 V,TA = 25°C
100
10
DCOx = 31
1
DCOx = 0
0.1
0
1
2
3
4
5
6
7
DCORSEL
Figure 14. Typical DCO frequency
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PMM, Brown-Out Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| dDVCC/dt | < 3 V/s
| dDVCC/dt | < 3 V/s
MIN
TYP
MAX UNIT
BORH on voltage,
DVCC falling level
V(DVCC_BOR_IT–)
V(DVCC_BOR_IT+)
1.45
V
BORH off voltage,
DVCC rising level
0.80
60
1.30
1.50
250
V
V(DVCC_BOR_hys) BORH hysteresis
Pulse length required at
mV
tRESET
RST/NMI pin to accept a
reset
2
µs
PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Core voltage, active
mode, PMMCOREV = 3
VCORE3(AM)
VCORE2(AM)
VCORE1(AM)
VCORE0(AM)
VCORE3(LPM)
VCORE2(LPM)
VCORE1(LPM)
VCORE0(LPM)
2.4 V ≤ DVCC ≤ 3.6 V
1.90
V
Core voltage, active
mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
2.0 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V
2.4 V ≤ DVCC ≤ 3.6 V
2.2 V ≤ DVCC ≤ 3.6 V
2.0 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V
1.80
1.60
1.40
1.94
1.84
1.64
1.44
V
V
V
V
V
V
V
Core voltage, active
mode, PMMCOREV = 1
Core voltage, active
mode, PMMCOREV = 0
Core voltage, low-current
mode, PMMCOREV = 3
Core voltage, low-current
mode, PMMCOREV = 2
Core voltage, low-current
mode, PMMCOREV = 1
Core voltage, low-current
mode, PMMCOREV = 0
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PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVSHE = 0, DVCC = 3.6 V
MIN
TYP
0
MAX UNIT
nA
nA
I(SVSH)
SVS current consumption
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
SVSHE = 1, SVSHRVL = 0
200
1.5
µA
1.53
1.73
1.93
2.03
1.60
1.80
2.00
2.10
2.25
2.52
2.85
2.85
1.60
1.80
2.00
2.10
1.70
1.90
2.10
2.20
2.35
2.65
3.00
3.00
1.67
SVSHE = 1, SVSHRVL = 1
1.87
V
V(SVSH_IT–)
SVSH on voltage level(1)
SVSHE = 1, SVSHRVL = 2
2.07
SVSHE = 1, SVSHRVL = 3
2.17
1.80
2.00
2.20
SVSHE = 1, SVSMHRRL = 0
SVSHE = 1, SVSMHRRL = 1
SVSHE = 1, SVSMHRRL = 2
SVSHE = 1, SVSMHRRL = 3
SVSHE = 1, SVSMHRRL = 4
SVSHE = 1, SVSMHRRL = 5
SVSHE = 1, SVSMHRRL = 6
SVSHE = 1, SVSMHRRL = 7
2.30
V
V(SVSH_IT+)
SVSH off voltage level(1)
2.50
2.78
3.15
3.15
SVSHE = 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
2.5
20
tpd(SVSH)
SVSH propagation delay
µs
µs
SVSHE = 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
12.5
100
t(SVSH)
SVSH on/off delay time
DVCC rise time
SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
dVDVCC/dt
0
1000
V/s
(1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the CC430 Family User's Guide (SLAU259) on recommended settings and usage.
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PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVMHE = 0, DVCC = 3.6 V
MIN
TYP
0
MAX UNIT
nA
I(SVMH)
SVMH current consumption
SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
SVMHE = 1, SVSMHRRL = 0
SVMHE = 1, SVSMHRRL = 1
SVMHE = 1, SVSMHRRL = 2
SVMHE = 1, SVSMHRRL = 3
SVMHE = 1, SVSMHRRL = 4
SVMHE = 1, SVSMHRRL = 5
SVMHE = 1, SVSMHRRL = 6
SVMHE = 1, SVSMHRRL = 7
SVMHE = 1, SVMHOVPE = 1
200
1.5
nA
µA
1.60
1.80
2.00
2.10
2.25
2.52
2.85
2.85
1.70
1.90
2.10
2.20
2.35
2.65
3.00
3.00
3.75
1.80
2.00
2.20
2.30
V(SVMH)
SVMH on/off voltage level(1)
2.50
2.78
3.15
3.15
V
SVMHE = 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
2.5
20
tpd(SVMH)
SVMH propagation delay
SVMH on/off delay time
µs
µs
SVMHE = 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
12.5
100
t(SVMH)
SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the CC430 Family User's Guide (SLAU259) on recommended settings and usage.
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PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVSLE = 0, PMMCOREV = 2
MIN
TYP
0
MAX UNIT
nA
nA
µA
I(SVSL)
SVSL current consumption
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
200
1.5
SVSLE = 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
2.5
20
tpd(SVSL)
SVSL propagation delay
SVSL on/off delay time
µs
µs
SVSLE = 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
12.5
100
t(SVSL)
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SVMLE = 0, PMMCOREV = 2
MIN
TYP
0
MAX UNIT
nA
nA
µA
I(SVML)
SVML current consumption
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1
200
1.5
SVMLE = 1, dVCORE/dt = 10 mV/µs,
SVMLFP = 1
2.5
20
tpd(SVML)
SVML propagation delay
SVML on/off delay time
µs
µs
SVMLE = 1, dVCORE/dt = 1 mV/µs,
SVMLFP = 0
SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs,
SVMLFP = 1
12.5
100
t(SVML)
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs,
SVMLFP = 0
Wake-up from Low Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Wake-up time from
LPM2, LPM3, or LPM4
to active mode(1)
PMMCOREV = SVSMLRRL = n, where n = 0,
1, 2, or 3
SVSLFP = 1
f
MCLK ≥ 4.0 MHz
5
tWAKE-UP-
FAST
µs
fMCLK < 4.0 MHz
6
Wake-up time from
LPM2, LPM3 or LPM4 to
active mode(2)
tWAKE-UP-
SLOW
PMMCOREV = SVSMLRRL = n, where n = 0, 1, 2, or 3
SVSLFP = 0
150 165 µs
Wake-up time from RST
or BOR event to active
mode(3)
tWAKE-UP-
RESET
2
3
ms
(1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the CC430 Family
User's Guide (SLAU259).
(2) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the CC430 Family User's Guide (SLAU259).
(3) This value represents the time from the wakeup event to the reset vector execution.
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Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ± 10%
1.8 V/
3.0 V
fTA
Timer_A input clock frequency
25 MHz
All capture inputs.
Minimum pulse width required for
capture.
1.8 V/
3.0 V
tTA,cap
Timer_A capture timing
20
ns
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USCI (UART Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
(equals baud rate in MBaud)
fBITCLK
1
MHz
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2.2 V
3 V
MIN
50
TYP
MAX UNIT
600
ns
tt
UART receive deglitch time(1)
50
600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
fUSCI
USCI input clock frequency
fSYSTEM MHz
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note (1), Figure 15 and Figure 16)
PMMCOR
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
EVx
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
55
38
30
25
0
0
ns
tSU,MI
SOMI input data setup time
3
0
3
0
3
0
3
ns
ns
ns
0
tHD,MI
SOMI input data hold time
SIMO output data valid time(2)
SIMO output data hold time(3)
0
0
20
ns
18
UCLK edge to SIMO valid,
CL = 20 pF
tVALID,MO
16
ns
15
-10
-8
ns
ns
tHD,MO
CL = 20 pF
-10
-8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 15 and Figure 16.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 15 and Figure 16.
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1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 15. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 16. SPI Master Mode, CKPH = 1
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USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note (1), Figure 17 and Figure 18)
PMMCOR
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
EVx
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
11
8
0
ns
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE low to clock
7
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
6
3
ns
3
STE lag time, Last clock to STE
high
3
3
66
ns
50
STE access time, STE low to
SOMI data out
36
30
30
ns
23
STE disable time, STE high to
SOMI high impedance
16
13
5
5
2
2
5
5
5
5
ns
ns
ns
ns
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time(2)
SOMI output data hold time(3)
tHD,SI
76
ns
60
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO
44
ns
40
18
12
10
8
ns
ns
tHD,SO
CL = 20 pF
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 15 and Figure 16.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 15
and Figure 16.
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tSU,SI
tLO/HI
tLO/HI
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 17. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tHD,MO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 18. SPI Slave Mode, CKPH = 1
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USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 19)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ± 10%
fSCL
SCL clock frequency
2.2 V/3 V
2.2 V/3 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
f
SCL ≤ 100 kHz
fSCL > 100 kHz
SCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
f
tSU,STA
Setup time for a repeated START
2.2 V/3 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2.2 V/3 V
2.2 V/3 V
ns
ns
250
4.0
0.6
50
fSCL ≤ 100 kHz
tSU,STO
Setup time for STOP
2.2 V/3 V
µs
fSCL > 100 kHz
2.2 V
3 V
600
ns
tSP
Pulse width of spikes suppressed by input filter
50
600
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
SCL
tLOW
tHIGH
tSP
tSU,DAT
tSU,STO
tHD,DAT
Figure 19. I2C Mode Timing
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LCD_B Recommended Operating Conditions
PARAMETER
Supply voltage range,
charge pump enabled,
LCD≤3.6V
CONDITIONS
MIN
NOM
MAX
UNIT
LCDCPEN=1, 0000 < VLCDx ≤ 1111 (charge
pump enabled, VLCD≤3.6V)
VCC,LCD_B,CP en,3.6
VCC,LCD_B,CP en,3.3
VCC,LCD_B,int. bias
VCC,LCD_B,ext. bias
2.2
3.6
V
V
Supply voltage range,
charge pump enabled,
LCDCPEN=1, 0000 < VLCDx ≤ 1100 (charge
pump enabled, VLCD≤3.3V)
2.0
2.4
2.4
3.6
3.6
3.6
V
V
V
VLCD≤3.3V
Supply voltage range,
internal biasing,
charge pump disabled
LCDCPEN=0, VLCDEXT=0
LCDCPEN=0, VLCDEXT=0
Supply voltage range,
external biasing,
charge pump disabled
Supply voltage range,
external LCD voltage,
internal or external
biasing, charge pump
disabled
VCC,LCD_B,VLCDEXT
LCDCPEN=0, VLCDEXT=1
LCDCPEN=0, VLCDEXT=1
2.0
3.6
3.6
V
V
External LCD voltage
at LCDCAP/R33,
internal or external
biasing, charge pump
disabled
VLCDCAP/R33
2.4
4.7
Capacitor on LCDCAP
when charge pump
enabled
LCDCPEN=1, VLCDx > 0000 (charge pump
enabled)
CLCDCAP
4.7
32
10
µF
Hz
LCD frame frequency fLCD = 2 × mux × fFRAME with mux= 1 (static),
range
fFrame
0
100
2, 3, 4.
ACLK input frequency
range
fACLK,in
CPanel
VR33
30
40
10000
kHz
pF
V
Panel capacitance
100Hz frame frequency
Analog input voltage
at R33
LCDCPEN=0, VLCDEXT=1
2.4
VCC+0.2
VR03
VR13 2/3*(VR33
-VR03
+
Analog input voltage
at R23
VR23,1/3bias
LCDREXT=1, LCDEXTBIAS=1, LCD2B=0
LCDREXT=1, LCDEXTBIAS=1, LCD2B=0
VR33
VR23
VR33
V
V
)
Analog input voltage
at R13 with 1/3
biasing
VR03
VR03 1/3*(VR33
-VR03
+
VR13,1/3bias
)
Analog input voltage
at R13 with 1/2
biasing
VR03
VR03 1/2*(VR33
-VR03
+
VR13,1/2bias
LCDREXT=1, LCDEXTBIAS=1, LCD2B=1
R0EXT=1
V
V
V
)
Analog input voltage
at R03
VR03
VSS
Voltage difference
between VLCD and
R03
VLCD-VR03
LCDCPEN=0, R0EXT=1
2.4
VCC+0.2
1.5
External LCD
reference voltage
applied at
VLCDREF/R13
VLCDREFx = 01
0.8
1.2
V
LCDREF/R13
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LCD_B Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VLCD
LCD voltage
VLCDx=0000, VLCDEXT=0
2.4 V to
3.6 V
VCC
V
LCDCPEN=1, VLCDx=0001
LCDCPEN=1, VLCDx=0010
LCDCPEN=1, VLCDx=0011
LCDCPEN=1, VLCDx=0100
LCDCPEN=1, VLCDx=0101
LCDCPEN=1, VLCDx=0110
LCDCPEN=1, VLCDx=0111
LCDCPEN=1, VLCDx=1000
LCDCPEN=1, VLCDx=1001
LCDCPEN=1, VLCDx=1010
LCDCPEN=1, VLCDx=1011
LCDCPEN=1, VLCDx=1100
LCDCPEN=1, VLCDx=1101
LCDCPEN=1, VLCDx=1110
LCDCPEN=1, VLCDx=1111
LCDCPEN=1, VLCDx=1111
2.0 V to
3.6 V
2.54
2.60
2.66
2.72
2.78
2.84
2.90
2.96
3.02
3.08
3.14
3.20
3.26
3.32
3.38
200
V
V
2.0 V to
3.6 V
2.0 V to
3.6 V
V
2.0 V to
3.6 V
V
2.0 V to
3.6 V
V
2.0 V to
3.6 V
V
2.0 V to
3.6 V
V
2.0 V to
3.6 V
V
2.0 V to
3.6 V
V
2.0 V to
3.6 V
V
2.0 V to
3.6 V
V
2.0 V to
3.6 V
V
2.2 V to
3.6 V
V
2.2 V to
3.6 V
V
2.2 V to
3.6 V
3.6
V
ICC,Peak,CP Peak supply currents due to
charge pump activities
2.2V
µA
ms
tLCD,CP,on
Time to charge CLCD when
discharge
CLCDCAP=4.7µF, LCDCPEN=0→1,
VLCDx=1111
2.2V
100
500
ICP,Load
Max. charge pump load current
LCDCPEN=1, VLCDx=1111
2.2V
2.2V
50
µA
RLCD,Seg
LCD driver output impedance,
segment lines
LCDCPEN=1, VLCDx=1000,
ILOAD=±10µA
10
10
kΩ
RLCD,COM
LCD driver output impedance,
common lines
LCDCPEN=1, VLCDx=1000,
ILOAD=±10µA
2.2V
kΩ
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12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2
0
TYP
MAX UNIT
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
Analog supply voltage
Full performance
AVCC
3.6
V
V
V(Ax)
Analog input voltage range(2) All ADC12 analog input pins Ax
AVCC
155
fADC12CLK = 5.0 MHz, ADC12ON = 1,
Operating supply current into
2.2 V
3 V
125
150
IADC12_A
REFON = 0, SHT0 = 0, SHT1 = 0,
AVCC terminal(3)
µA
220
ADC12DIV = 0
Only one terminal Ax can be selected at one
CI
RI
Input capacitance
time
2.2 V
20
25
pF
Input MUX ON resistance
0 V ≤ VAx ≤ AVCC
10
200
1900
Ω
(1) The leakage current is specified by the digital I/O input leakage.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See REF, External Reference and REF, Built-In Reference.
(3) The internal reference supply current is not included in current consumption parameter IADC12_A
.
12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC12 linearity
parameters
fADC12CLK
fADC12OSC
2.2 V/3 V
0.45
4.8
5.4 MHz
Internal ADC12
oscillator(1)
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V/3 V
2.2 V/3 V
4.2
2.4
4.8
5.4 MHz
REFON = 0, Internal oscillator,
fADC12OSC = 4.2 MHz to 5.4 MHz
3.1
µs
tCONVERT
Conversion time
External fADC12CLK from ACLK, MCLK or SMCLK,
(2)
ADC12SSEL ≠ 0
RS = 400 Ω, RI = 1000 Ω, CI = 30 pF,
t = [RS + RI] × CI
tSample
Sampling time
2.2 V/3 V
1000
ns
(3)
(1) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(2) 13 × ADC12DIV × 1/fADC12CLK
(3) Approximately ten Tau (t) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
12-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
±2
LSB
±1.7
Integral
linearity error (INL)
EI
2.2 V/3 V
Differential
ED
EO
EG
ET
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
±1.0 LSB
±2.0 LSB
±2.0 LSB
±3.5 LSB
linearity error (DNL) CVREF+ = 20 pF
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
Internal impedance of source RS < 100 Ω, CVREF+ = 20 pF
Offset error
Gain error
±1.0
±1.0
±1.4
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
Total unadjusted
error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
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(1)
12-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2.2 V
3 V
MIN
TYP
680
680
2.25
2.25
MAX UNIT
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
(2) (3)
VSENSOR
See
mV
2.2 V
3 V
(3)
TCSENSOR
See
ADC12ON = 1, INCH = 0Ah
mV/°C
2.2 V
3 V
30
30
Sample time required if
channel 10 is selected(4)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
tSENSOR(sample)
µs
AVCC divider at channel 11,
VAVCC factor
ADC12ON = 1, INCH = 0Bh
ADC12ON = 1, INCH = 0Bh
0.48
0.5
0.52 VAVCC
VMID
2.2 V
3 V
1.06
1.44
1.1
1.5
1.14
V
AVCC divider at channel 11
1.56
Sample time required if
channel 11 is selected(5)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
tVMID(sample)
2.2 V/3 V
1000
ns
(1) The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of
the temperature sensor.
(2) The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset error
of the built-in temperature sensor.
(3) The device descriptor structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of the available reference voltage
levels. The sensor voltage can be computed as VSENSE = TCSENSOR * (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can
be computed from the calibration values for higher accuracy.
(4) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
.
(5) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
1000
950
900
850
800
750
700
650
600
550
500
-40 -30 -20 -10
0 10 20 30 40 50 60 70 80
Ambient Temperature - ˚C
Figure 20. Typical Temperature Sensor Voltage
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REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
1.4
0
TYP
MAX UNIT
(2)
VeREF+
Positive external reference voltage input
VeREF+ > VREF–/VeREF–
AVCC
1.2
V
V
(3)
VREF–/VeREF–
Negative external reference voltage input VeREF+ > VREF–/VeREF–
(VeREF+
VREF–/VeREF–
–
Differential external reference voltage
VeREF+ > VREF–/VeREF–
input
(4)
1.4
AVCC
V
)
1.4 V ≤ VeREF+ ≤ VAVCC
VeREF– = 0 V
,
fADC12CLK = 5
MHz,ADC12SHTx = 1h,
Conversion rate 200ksps
2.2 V/3 V
2.2 V/3 V
±8.5
±26
µA
IVeREF+
IVREF–/VeREF–
Static input current
1.4 V ≤ VeREF+ ≤ VAVCC
VeREF– = 0 V
fADC12CLK = 5
MHz,ADC12SHTx = 8h,
Conversion rate 20ksps
,
±1
µA
µF
CVREF+/-
Capacitance at VREF+/- terminal
(5)10
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10µF and 100nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the CC430 Family User's Guide (SLAU259).
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MAX UNIT
REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
REFVSEL = 2 for 2.5 V
REFON = REFOUT = 1
IVREF+= 0 A
3 V
2.41 ±1.5%
1.93 ±1.5%
1.45 ±1.5%
REFVSEL = 1 for 2.0 V
REFON = REFOUT = 1
IVREF+= 0 A
Positive built-in reference
voltage output
VREF+
3 V
V
V
REFVSEL = 0 for 1.5 V
REFON = REFOUT = 1
IVREF+= 0 A
2.2 V/ 3 V
REFVSEL = 0 for 1.5 V, reduced performance
REFVSEL = 0 for 1.5 V
1.8
2.2
2.3
2.8
AVCC minimum voltage,
Positive built-in reference
active
AVCC(min)
REFVSEL = 1 for 2.0 V
REFVSEL = 2 for 2.5 V
REFON = 1, REFOUT = 0, REFBURST = 0
REFON = 1, REFOUT = 1, REFBURST = 0
3 V
3 V
100
0.9
140
1.5
µA
Operating supply current into
AVCC terminal(2) (3)
IREF+
mA
REFVSEL = 0, 1, 2
Load-current regulation,
VREF+ terminal(4)
IVREF+ = +10 µA/–1000 µA
AVCC = AVCC (min) for each reference level.
REFVSEL = 0, 1, 2; REFON = REFOUT = 1
IL(VREF+)
2500 µV/mA
Capacitance at VREF+/-
terminals
CVREF+/-
REFON = REFOUT = 1(5)
20
100
50
pF
IVREF+ = 0 A
REFVSEL = 0, 1, 2;
REFON = 1, REFOUT = 0 or 1
Temperature coefficient of
built-in reference(6)
ppm/
°C
TCREF+
30
AVCC = AVCC (min) - AVCC(max)
TA = 25 °C
REFVSEL = 0, 1, 2;
Power supply rejection ratio
(DC)
PSRR_DC
PSRR_AC
120
300 µV/V
mV/V
REFON = 1, REFOUT = 0 or 1
AVCC = AVCC (min) - AVCC(max)
TA = 25 °C
f = 1 kHz, ΔVpp = 100 mV
REFVSEL = 0, 1, 2;
Power supply rejection ratio
(AC)
6.4
REFON = 1, REFOUT = 0 or 1
AVCC = AVCC (min) - AVCC(max)
REFVSEL = 0, 1, 2;
REFOUT = 0, REFON = 0 → 1
75
75
Settling time of reference
voltage(7)
tSETTLE
µs
AVCC = AVCC (min) - AVCC(max)
CVREF = CVREF(max)
REFVSEL = 0, 1, 2;
REFOUT = 1, REFON = 0 → 1
(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one
smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as,
used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the reference
for the conversion and utilizes the smaller buffer.
(2) The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion. REFOUT = 0 represents
the current contribution of the smaller buffer. REFOUT = 1 represents the current contribution of the larger buffer without external load.
(3) The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to IREF+ with REFON
=1 and REFOUT = 0.
(4) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace, etc.
(5) Two decoupling capacitors, 10µF and 100nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A.
(6) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)).
(7) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.
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Comparator B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
VCC
Supply voltage
1.8
3.6
40
50
65
30
0.5
V
1.8 V
2.2 V
CBPWRMD = 00
30
40
Comparator operating supply
current into AVCC, Excludes
reference resistor ladder
IAVCC_COMP
3.0 V
µA
CBPWRMD = 01
CBPWRMD = 10
2.2/3.0 V
2.2/3.0 V
10
0.1
Quiescent current of local
reference voltage amplifier into
AVCC
IAVCC_REF
CBREFACC = 1, CBREFLx = 01
22
µA
VIC
Common mode input range
0
VCC-1
±20
V
CBPWRMD = 00
mV
mV
pF
kΩ
MΩ
ns
VOFFSET
CIN
Input offset voltage
CBPWRMD = 01, 10
±10
Input capacitance
5
3
ON - switch closed
4
RSIN
Series input resistance
OFF - switch opened
CBPWRMD = 00, CBF = 0
30
450
600
50
tPD
Propagation delay, response time CBPWRMD = 01, CBF = 0
CBPWRMD = 10, CBF = 0
ns
µs
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 00
0.35
0.6
1.0
1.8
0.6
1.0
1.8
3.4
1.0
1.8
3.4
6.5
µs
µs
µs
µs
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 01
Propagation delay with filter
active
tPD,filter
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 10
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 11
Comparator enable time, settling CBON = 0 to CBON = 1,
tEN_CMP
tEN_REF
VCB_REF
1
2
µs
µs
V
time
CBPWRMD = 00, 01, 10
Resistor reference enable time
CBON = 0 to CBON = 1
0.3
1.5
VIN = reference into resistor ladder,
n = 0 to 31
Reference voltage for a given tap
VIN × (n+1) / 32
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MAX UNIT
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
DVCC(PGM/ERASE) Program and erase supply voltage
1.8
3.6
5
V
mA
IPGM
Average supply current from DVCC during program
3
IERASE
Average supply current from DVCC during erase
Average supply current from DVCC during mass erase or bank erase
Cumulative program time(1)
2
mA
IMERASE, IBANK
tCPT
2
mA
16
ms
Program/erase endurance
104
100
64
105
cycles
years
µs
tRetention
tWord
Data retention duration
Word or byte program time(2)
Block program time for first byte or word(2)
TJ = 25°C
85
65
tBlock, 0
49
µs
Block program time for each additional byte or word, except for last
byte or word(2)
Block program time for last byte or word(2)
tBlock, 1–(N–1)
tBlock, N
37
55
23
49
73
32
µs
µs
Erase time for segment erase, mass erase, and bank erase when
available(2)
tErase
ms
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
fMCLK,MGR
0
1
MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V/3 V
0
20 MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V/3 V
0.025
15
µs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge)(1)
tSBW, En
tSBW,Rst
2.2 V/3 V
1
µs
Spy-Bi-Wire return to normal operation time
TCK input frequency - 4-wire JTAG(2)
Internal pull-down resistance on TEST
15
0
100
5
µs
2.2 V
3 V
MHz
fTCK
0
10 MHz
80 kΩ
Rinternal
2.2 V/3 V
45
60
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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RF1A CC1101-Based Radio Parameters
Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
MIN
2.0
TYP
MAX UNIT
VCC
Supply voltage range during radio operation
3.6
3
V
PMMCOREVx
Core voltage range, PMMCOREVx setting during radio operation
2
300
389(1)
779
0.6
348
RF frequency range
Data rate
464 MHz
928
2-FSK
500
2-GFSK, OOK, and ASK
(Shaped) MSK (also known as differential offset QPSK)(2)
0.6
250 kBaud
500
26
RF crystal frequency
RF crystal tolerance
26
26
27 MHz
ppm
Total tolerance including initial tolerance, crystal loading, aging and
temperature dependency.(3)
±40
RF crystal load capacitance
10
13
20
pF
RF crystal effective series
resistance
100
Ω
(1) If using a 27-MHz crystal, the lower frequency limit for this band is 392 MHz.
(2) If using optional Manchester encoding, the data rate in kbps is half the baud rate.
(3) The acceptable crystal tolerance depends on frequency band, channel bandwidth, and spacing. Also see Design Note DN005 -- CC11xx
Sensitivity versus Frequency Offset and Crystal Accuracy, literature number SWRA122.
RF Crystal Oscillator, XT2
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
PARAMETER
Start-up time(2)
Duty cycle
TEST CONDITIONS
MIN
TYP
150
50
MAX
810
55
UNIT
µs
45
%
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
(2) The start-up time depends to a very large degree on the used crystal.
Current Consumption, Reduced-Power Modes
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
RF crystal oscillator only (e.g. SLEEP state with MCSM0.OSC_FORCE_ON = 1)
IDLE state (incl. RF crystal oscillator)
MIN
TYP
100
1.7
MAX
UNIT
µA
Current
consumption
mA
mA
FSTXON state (Only the frequency synthesizer is running)(2)
9.5
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
(2) This current consumption is also representative of other intermediate states when going from IDLE to RX or TX, including the calibration
state.
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Current Consumption, Receive Mode
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
(2)
DATA
RATE
(kBaud)
FREQ
(MHz)
PARAMETER
TEST CONDITIONS
Input at -100 dBm (close to
MIN
TYP
MAX UNIT
17
16
sensitivity limit)
1.2
38.4
250
1.2
Input at -40 dBm (well above
sensitivity limit)
Input at -100 dBm (close to
sensitivity limit)
17
Register settings
optimized for reduced
current
315
Input at -40 dBm (well above
sensitivity limit)
16
Input at -100 dBm (close to
sensitivity limit)
18
Input at -40 dBm (well above
sensitivity limit)
16.5
18
Input at -100 dBm (close to
sensitivity limit)
Input at -40 dBm (well above
sensitivity limit)
17
Input at -100 dBm (close to
sensitivity limit)
18
Current
consumption,
RX
Register settings
optimized for reduced
current
433
38.4
250
1.2
mA
Input at -40 dBm (well above
sensitivity limit)
17
Input at -100 dBm (close to
sensitivity limit)
18.5
17
Input at -40 dBm (well above
sensitivity limit)
Input at -100 dBm (close to
sensitivity limit)
16
Input at -40 dBm (well above
sensitivity limit)
15
Input at -100 dBm (close to
sensitivity limit)
16
Register settings
optimized for reduced
current(3)
868, 915
38.4
250
Input at -40 dBm (well above
sensitivity limit)
15
Input at -100 dBm (close to
sensitivity limit)
16
Input at -40 dBm (well above
sensitivity limit)
15
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
(2) Reduced current setting (MDMCFG2.DEM_DCFILT_OFF = 1) gives a slightly lower current consumption at the cost of a reduction in
sensitivity. See tables "RF Receive" for additional details on current consumption and sensitivity.
(3) For 868/915 MHz, see Figure 21 for current consumption with register settings optimized for sensitivity.
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19
19
18
17
16
TA = 85°C
TA = 25°C
TA = -40°C
TA = 85°C
TA = 25°C
TA = -40°C
18
17
16
-100
-80
-60
-40
-20
-100
-80
-60
-40
-20
Input Power [dBm]
Input Power [dBm]
1.2 kBaud GFSK
38.4 kBaud GFSK
19
18
17
16
19
18
17
TA = 85°C
TA = 85°C
TA = 25°C
TA = -40°C
TA = 25°C
TA = -40°C
16
-100
-80
-60
-40
-20
-100
-80
-60
-40
-20
Input Power [dBm]
Input Power [dBm]
250 kBaud GFSK
500 kBaud MSK
Figure 21. Typical RX Current Consumption Over Temperature and Input Power Level, 868 MHz,
Sensitivity-Optimized Setting
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MAX UNIT
Current Consumption, Transmit Mode
(2)
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
FREQUENCY
[MHz}
PATABLE
Setting
OUTPUT
POWER [dBm]
PARAMETER
MIN
TYP
0xC0
0xC4
0x51
0x29
0xC0
0xC6
0x50
0x2D
0xC0
0xC3
0x8D
0x2D
0xC0
0xC3
0x8D
0x2D
max.
+10
0
26
25
15
15
33
29
17
17
36
33
18
18
35
32
18
18
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
315
433
868
915
-6
max.
+10
0
-6
Current consumption, TX
max.
+10
0
-6
max.
+10
0
-6
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
(2) Reduced current setting (MDMCFG2.DEM_DCFILT_OFF = 1) gives a slightly lower current consumption at the cost of a reduction in
sensitivity. See tables "RF Receive" for additional details on current consumption and sensitivity.
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Typical TX Current Consumption, 315 MHz
Output VCC
Power
[dBm]
2.0 V
3.0 V
25°C
3.6 V
PATABLE
Setting
PARAMETER
UNIT
TA
25°C
25°C
0xC0
0xC4
0x51
0x29
max.
+10
0
27.5
25.1
14.4
14.2
26.4
25.2
14.6
14.7
28.1
Current
consumption,
TX
25.3
mA
14.7
-6
15.0
Typical TX Current Consumption, 433 MHz
Output VCC
Power
[dBm]
2.0 V
3.0 V
25°C
3.6 V
PATABLE
Setting
PARAMETER
UNIT
TA
25°C
25°C
0xC0
0xC6
0x50
0x2D
max.
+10
0
33.1
28.6
16.6
16.8
33.4
28.8
16.8
17.5
33.8
Current
consumption,
TX
28.8
mA
16.9
-6
17.8
Typical TX Current Consumption, 868 MHz
Output VCC
Power
[dBm]
2.0 V
3.0 V
25°C
3.6 V
UNIT
PATABLE
Setting
PARAMETER
TA
-40°C
25°C
85°C
-40°C
85°C
-40°C
25°C
85°C
0xC0
0xC3
0x8D
0x2D
max.
+10
0
36.7
34.0
18.0
17.1
35.2
32.8
17.6
17.0
34.2
32.0
17.5
17.2
38.5
34.2
18.3
17.8
35.5
33.0
17.8
17.8
34.9
32.5
18.1
18.3
37.1
34.3
18.4
18.2
35.7
33.1
18.0
18.1
34.7
32.2
17.7
18.1
Current
consumption,
TX
mA
-6
Typical TX Current Consumption, 915 MHz
Output VCC
Power
[dBm]
2.0 V
3.0 V
25°C
3.6 V
25°C
PATABLE
Setting
PARAMETER
UNIT
TA
-40°C
25°C
85°C
-40°C
85°C
-40°C
85°C
0xC0
0xC3
0x8D
0x2D
max.
+10
0
35.5
33.2
17.8
17.0
33.8
32.0
17.4
16.9
33.2
31.0
17.1
16.9
36.2
33.4
18.1
17.7
34.8
32.1
17.6
17.6
33.6
31.2
17.3
17.6
36.3
33.5
18.2
18.1
35.0
32.3
17.8
18.0
33.8
31.3
17.5
18.0
Current
consumption,
TX
mA
-6
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RF Receive, Overall
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Digital channel filter bandwidth(2)
58
812 kHz
25 MHz to 1 GHz
Spurious emissions(3) (4)
-68
-66
9
-57
dBm
-47
Above 1 GHz
RX latency
Serial operation(5)
bit
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
(2) User programmable. The bandwidth limits are proportional to crystal frequency (given values assume a 26.0 MHz crystal)
(3) Typical radiated spurious emission is -49 dBm measured at the VCO frequency
(4) Maximum figure is the ETSI EN 300 220 limit
(5) Time from start of reception until data is available on the receiver data output pin is equal to 9 bit.
RF Receive, 315 MHz
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
2-FSK, 1% packet error rate, 20-byte packet length, Sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF = 0 (unless
otherwise noted)
DATA RATE
(kBaud)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
0.6
14.3kHz deviation, 58kHz digital channel filter bandwidth
5.2kHz deviation, 58kHz digital channel filter bandwidth(2)
20kHz deviation, 100kHz digital channel filter bandwidth(3)
-117
-111
-103
-95
1.2
Receiver sensitivity
38.4
250
dBm
(4)
127kHz deviation, 540kHz digital channel filter bandwidth
MSK, 812kHz digital channel filter bandwidth(4)
500
-86
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
(2) Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then
reduced by about 2mA close to the sensitivity limit. The sensitivity is typically reduced to -109dBm.
(3) Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then
reduced by about 2mA close to the sensitivity limit. The sensitivity is typically reduced to -102dBm.
(4) MDMCFG2.DEM_DCFILT_OFF=1 can not be used for data rates ≥ 250kBaud.
RF Receive, 433 MHz
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
2-FSK, 1% packet error rate, 20-byte packet length, Sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF = 0 (unless
otherwise noted)
DATA RATE
(kBaud)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
0.6
14.3kHz deviation, 58kHz digital channel filter bandwidth
5.2-kHz deviation, 58-kHz digital channel filter bandwidth(2)
20-kHz deviation, 100-kHz digital channel filter bandwidth(3)
-114
-111
-104
1.2
38.4
Receiver sensitivity
dBm
127-kHz deviation, 540-kHz digital channel filter bandwidth
250
500
-93
-85
(4)
MSK, 812kHz digital channel filter bandwidth(4)
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
(2) Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then
reduced by about 2mA close to the sensitivity limit. The sensitivity is typically reduced to -109dBm.
(3) Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then
reduced by about 2mA close to the sensitivity limit. The sensitivity is typically reduced to -101dBm.
(4) MDMCFG2.DEM_DCFILT_OFF=1 can not be used for data rates ≥ 250kBaud.
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RF Receive, 868/915 MHz
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
1% packet error rate, 20-byte packet length, Sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF = 0 (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
0.6-kBaud data rate, 2-FSK, 14.3-kHz deviation, 58-kHz digital channel filter bandwidth (unless otherwise noted)
Receiver sensitivity
-115
dBm
1.2-kBaud data rate, 2-FSK, 5.2-kHz deviation, 58-kHz digital channel filter bandwidth (unless otherwise noted)
-109
-109
Receiver sensitivity(2)
dBm
2-GFSK modulation by setting MDMCFG2.MOD_FORMAT=2,
Gaussian filter with BT = 0.5
Saturation
FIFOTHR.CLOSE_IN_RX=0(3)
-28
39
39
dBm
dB
-100-kHz offset
+100-kHz offset
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit,
100 kHz channel spacing(4)
IF frequency 152 kHz, desired channel 3 dB above
the sensitivity limit
Image channel rejection
Blocking
29
dB
±2 MHz offset
±10 MHz offset
-48
-40
dBm
dBm
Desired channel 3 dB above the sensitivity limit(5)
38.4-kBaud data rate, 2-FSK, 20-kHz deviation, 100-kHz digital channel filter bandwidth (unless otherwise noted)
Receiver sensitivity(6)
-102
dBm
2-GFSK modulation by setting MDMCFG2.MOD_FORMAT = 2,
Gaussian filter with BT = 0.5
-101
Saturation
FIFOTHR.CLOSE_IN_RX=0(3)
-19
20
dBm
dB
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit,
200 kHz channel spacing(5)
-200-kHz offset
+200-kHz offset
25
Image channel rejection IF frequency 152 kHz, Desired channel 3 dB above the sensitivity limit
23
dB
Blocking
Desired channel 3 dB above the sensitivity limit(5)
±2-MHz offset
±10-MHz offset
-48
-40
dBm
dBm
250-kBaud data rate, 2-FSK, 127-kHz deviation, 540-kHz digital channel filter bandwidth (unless otherwise noted)
(7)
Receiver sensitivity
-90
dBm
2-GFSK modulation by setting MDMCFG2.MOD_FORMAT = 2,
Gaussian filter with BT = 0.5
-90
Saturation
FIFOTHR.CLOSE_IN_RX=0(3)
-19
24
dBm
dB
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit,
750-kHz channel spacing(8)
-750-kHz offset
+750-kHz offset
30
Image channel rejection IF frequency 304 kHz, Desired channel 3 dB above the sensitivity limit
18
dB
Blocking
Desired channel 3 dB above the sensitivity limit(8)
±2-MHz offset
±10-MHz offset
-53
-39
dBm
dBm
500-kBaud data rate, MSK, 812-kHz digital channel filter bandwidth (unless otherwise noted)
Receiver sensitivity(7)
-84
-2
dBm
dB
Image channel rejection IF frequency 355 kHz, Desired channel 3 dB above the sensitivity limit
Blocking
Desired channel 3 dB above the sensitivity limit(9)
±2-MHz offset
±10-MHz offset
-53
-38
dBm
dBm
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
(2) Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then
reduced by about 2mA close to the sensitivity limit. The sensitivity is typically reduced to -107dBm
(3) See Design Note DN010 Close-in Reception with CC1101, literature number SWRA147.
(4) See Figure 22 for blocking performance at other offset frequencies.
(5) See Figure 23 for blocking performance at other offset frequencies.
(6) Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then
reduced by about 2mA close to the sensitivity limit. The sensitivity is typically reduced to -100dBm.
(7) MDMCFG2.DEM_DCFILT_OFF = 1 cannot be used for data rates ≥ 250kBaud.
(8) See Figure 24 for blocking performance at other offset frequencies.
(9) See Figure 25 for blocking performance at other offset frequencies.
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80
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
-10
-20
-10
-40 -30
-20 -10
0
10
20
30
40
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
Offset [MHz]
Offset [MHz]
NOTE: 868.3 MHz, 2-FSK, 5.2-kHz deviation, IF frequency is 152.3 kHz, digital channel filter bandwidth is 58 kHz
Figure 22. Typical Selectivity at 1.2-kBaud Data Rate
80
70
60
50
40
30
20
10
0
50
40
30
20
10
0
-10
-20
-10
-20
-40 -30
-20 -10
0
10
20
30
40
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
Offset [MHz]
Offset [MHz]
NOTE: 868 MHz, 2-FSK, 20 kHz deviation, IF frequency is 152.3 kHz, digital channel filter bandwidth is 100 kHz
Figure 23. Typical Selectivity at 38.4-kBaud Data Rate
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80
70
60
50
40
30
20
10
0
50
40
30
20
10
0
-10
-20
-10
-20
-40 -30
-20 -10
Offset [MHz]
NOTE: 868 MHz, 2-FSK, IF frequency is 304 kHz, digital channel filter bandwidth is 540 kHz
0
10
20
30
40
-3
-2
-1
0
1
2
3
Offset [MHz]
Figure 24. Typical Selectivity at 250-kBaud Data Rate
80
70
60
50
40
30
20
10
0
50
40
30
20
10
0
-10
-20
-10
-20
-40 -30
-20 -10
Offset [MHz]
NOTE: 868 MHz, 2-FSK, IF frequency is 355 kHz, digital channel filter bandwidth is 812 kHz
0
10
20
30
40
-3
-2
-1
0
1
2
3
Offset [MHz]
Figure 25. Typical Selectivity at 500-kBaud Data Rate
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UNIT
Typical Sensitivity, 315 MHz, Sensitivity Optimized Setting
VCC
2.0 V
3.0 V
3.6 V
PARAMETER
DATA RATE (kBaud)
TA
-40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C
1.2
38.4
250
-112
-105
-95
-112
-105
-95
-110
-104
-92
-112
-105
-94
-111
-103
-95
-109
-102
-92
-112
-105
-95
-111
-104
-94
-108
-102
-91
Sensitivity,
315MHz
dBm
Typical Sensitivity, 433 MHz, Sensitivity Optimized Setting
VCC
TA
2.0 V
3.0 V
3.6 V
PARAMETER
DATA RATE (kBaud)
UNIT
-40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C
1.2
38.4
250
-111
-104
-93
-110
-104
-94
-108
-101
-91
-111
-104
-93
-111
-104
-93
-108
-101
-90
-111
-104
-93
-110
-103
-93
-107
-101
-90
Sensitivity,
433MHz
dBm
Typical Sensitivity, 868 MHz, Sensitivity Optimized Setting
VCC
2.0 V
3.0 V
3.6 V
PARAMETER
DATA RATE (kBaud)
UNIT
TA
-40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C
1.2
38.4
250
500
-109
-102
-90
-109
-102
-90
-107
-100
-88
-109
-102
-89
-109
-102
-90
-106
-99
-87
-80
-109
-102
-89
-108
-101
-90
-106
-99
-87
-80
Sensitivity,
868MHz
dBm
-84
-84
-81
-84
-84
-84
-84
Typical Sensitivity, 915 MHz, Sensitivity Optimized Setting
VCC
2.0 V
3.0 V
3.6 V
PARAMETER
DATA RATE (kBaud)
UNIT
TA
-40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C
1.2
38.4
250
500
-109
-102
-92
-109
-102
-92
-107
-100
-89
-109
-102
-92
-109
-102
-92
-106
-99
-88
-81
-109
-103
-92
-108
-102
-92
-105
-99
-88
-80
Sensitivity,
915MHz
dBm
-87
-86
-81
-86
-86
-86
-85
80
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RF Transmit
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
PTX = +10 dBm (unless otherwise noted)
FREQUENCY
PARAMETER
(MHz)
TEST CONDITIONS
MIN
TYP
MAX UNIT
315
122 + j31
116 + j41
86.5 + j43
+12
Differential load
433
Ω
impedance(2)
868/915
315
433
868
915
+13
Output power, highest
setting(3)
Delivered to a 50Ω single-ended load via CC430
reference design's RF matching network
dBm
dBm
+11
+11
Output power, lowest
setting(3)
Delivered to a 50Ω single-ended load via CC430
reference design's RF matching network
-30
Second harmonic
Third harmonic
-56
-57
433
868
915
315
433
868
915
315
Second harmonic
Third harmonic
-50
Harmonics,
dBm
radiated(4)(5)(6)
-52
Second harmonic
Third harmonic
-50
-54
Frequencies below 960 MHz
< -38
< -48
-45
+10 dBm CW
Frequencies above 960 MHz
Frequencies below 1 GHz
Frequencies above 1 GHz
Second harmonic
+10 dBm CW
+10 dBm CW
+11 dBm CW(7)
+10 dBm CW
< -48
-59
Harmonics, conducted
dBm
Other harmonics
< -71
-53
Second harmonic
Other harmonics
< -47
< -58
< -53
< -54
< -54
Frequencies below 960 MHz
Frequencies above 960 MHz
Frequencies below 1 GHz
Frequencies above 1 GHz
433
+10 dBm CW
Frequencies within 47 to 74, 87.5 to
118, 174 to 230, 470 to 862 MHz
< -63
Spurious emissions,
conducted, harmonics
not included(8)
dBm
Frequencies below 1 GHz
Frequencies above 1 GHz
< -46
< -59
868
915
+10 dBm CW
+11 dBm CW
Frequencies within 47 to 74, 87.5 to
118, 174 to 230, 470 to 862 MHz
< -56
Frequencies below 960 MHz
Frequencies above 960 MHz
< -49
< -63
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
(2) Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. Follow the CC430 reference designs available
from the TI website.
(3) Output power is programmable, and full range is available in all frequency bands. Output power may be restricted by regulatory limits.
See also Application Note AN050 Using the CC1101 in the European 868MHz SRD Band, literature number SWRA146 and Design
Note DN013 Programming Output Power on CC1101, literature number SWRA168, which gives the output power and harmonics when
using multi-layer inductors. The output power is then typically +10 dBm when operating at 868/915 MHz.
(4) The antennas used during the radiated measurements (SMAFF-433 from R.W.Badland and Nearson S331 868/915) play a part in
attenuating the harmonics.
(5) Measured on EM430F6137RF900 with CW, maximum output power
(6) All harmonics are below -41.2 dBm when operating in the 902 – 928 MHz band.
(7) Requirement is -20 dBc under FCC 15.247
(8) All radiated spurious emissions are within the limits of ETSI. Also see Design Note DN017 CC11xx 868/915 MHz RF Matching, literature
number SWRA168.
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RF Transmit (continued)
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
PTX = +10 dBm (unless otherwise noted)
FREQUENCY
PARAMETER
(MHz)
TEST CONDITIONS
MIN
TYP
MAX UNIT
TX latency(9)
Serial operation
8
bits
(9) Time from sampling the data on the transmitter data input pin until it is observed on the RF output ports
Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
PATABLE Setting
Output Power [dBm]
315 MHz
0x12
433 MHz
0x05
868 MHz
0x03
915 MHz
-30
-12
-6
0x03
0x25
0x2D
0x8D
0xC3
0xC0
0x33
0x26
0x25
0x29
0x2D
0x50
0x2D
0x8D
0xC3
0xC0
0
0x51
10
0xC4
0xC0
0xC4
0xC0
max.
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
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Typical Output Power, 315 MHz(1)
VCC
TA
2.0 V
3.0 V
3.6 V
UNIT
PARAMETER
PATABLE Setting
-40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C
0xC0 (max)
11.9
10.3
11.8
10.3
9.3
11.8
10.3
0xC4 (10dBm)
0xC6 (default)
0x51 (0dBm)
0x29 (-6dBm)
Output power,
315MHz
dBm
0.7
0.6
0.7
-6.8
-5.6
-5.3
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
Typical Output Power, 433 MHz(1)
VCC
TA
2.0 V
3.0 V
3.6 V
PARAMETER
PATABLE Setting
UNIT
-40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C
0xC0 (max)
12.6
10.3
12.6
10.2
10.0
0.3
12.6
10.2
0xC4 (10dBm)
0xC6 (default)
0x50 (0dBm)
0x2D (-6dBm)
Output power,
433MHz
dBm
0.3
0.3
-6.4
-5.4
-5.1
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
Typical Output Power, 868 MHz(1)
VCC
TA
2.0 V
3.0 V
3.6 V
PARAMETER
PATABLE Setting
UNIT
-40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C
0xC0 (max)
11.9
10.8
11.2
10.1
10.5
9.4
11.9
10.8
11.2
10.1
8.8
10.5
9.4
11.9
10.7
11.2
10.1
10.5
9.4
0xC3 (10dBm)
0xC6 (default)
0x8D (0dBm)
0x2D (-6dBm)
Output power,
868MHz
dBm
1.0
0.3
-0.3
-7.3
1.1
0.3
-0.3
-6.3
1.1
0.3
-0.3
-6.0
-6.5
-6.8
-5.3
-5.8
-4.9
-5.4
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
Typical Output Power, 915 MHz(1)
VCC
TA
2.0 V
3.0 V
3.6 V
PARAMETER
PATABLE Setting
UNIT
-40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C
0xC0 (max)
12.2
11.0
11.4
10.3
10.6
9.5
12.1
11.0
11.4
10.3
8.8
10.7
9.5
12.1
11.0
11.4
10.3
10.7
9.6
0xC3 (10dBm)
0xC6 (default)
0x8D (0dBm)
0x2D (-6dBm)
Output power,
915MHz
dBm
1.9
1.0
0.3
1.9
1.0
0.3
1.9
1.1
0.3
-5.5
-6.0
-6.5
-4.3
-4.8
-5.5
-3.9
-4.4
-5.1
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
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Frequency Synthesizer Characteristics
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
MIN figures are given using a 27MHz crystal. TYP and MAX figures are given using a 26MHz crystal.
PARAMETER
Programmed frequency resolution(2)
Synthesizer frequency tolerance(3)
TEST CONDITIONS
26 to 27 MHz crystal
MIN
TYP
fXOSC/216
±40
MAX
UNIT
Hz
397
412
ppm
50 kHz offset from carrier
100 kHz offset from carrier
200 kHz offset from carrier
500 kHz offset from carrier
1 MHz offset from carrier
2 MHz offset from carrier
5 MHz offset from carrier
10 MHz offset from carrier
Crystal oscillator running
–95
–94
–94
–98
RF carrier phase noise
dBc/Hz
–107
–112
–118
–129
88.4
PLL turn-on / hop time(4)
PLL RX/TX settling time(5)
PLL TX/RX settling time(6)
PLL calibration time(7)
85.1
9.3
88.4
9.6
µs
µs
µs
µs
9.6
20.7
694
21.5
21.5
721
721
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
(2) The resolution (in Hz) is equal for all frequency bands.
(3) Depends on crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth /
spacing.
(4) Time from leaving the IDLE state until arriving in the RX, FSTXON or TX state, when not performing calibration.
(5) Settling time for the 1-IF frequency step from RX to TX
(6) Settling time for the 1-IF frequency step from TX to RX
(7) Calibration can be initiated manually or automatically before entering or after leaving RX/TX
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Typical RSSI_offset Values
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)
RSSI_OFFSET (dB)
DATA RATE (kBaud)
433 MHz
868 MHz
1.2
38.4
250
500
74
74
74
74
74
74
74
74
(1) All measurement results are obtained using the EM430F6137RF900 with BOM according to tested frequency range (see Table 46).
0
-20
0
-20
250kBaud
500kBaud
1.2kBaud
38.4kBaud
-40
-40
-60
-60
-80
-80
-100
-100
-120
-120
-120
-100
-80
-60
-40
-20
0
-120
-100
-80
-60
-40
-20
0
Input Power [dBm]
Input Power [dBm]
Figure 26. Typical RSSI Value vs Input Power Level for Different Data Rates at 868 MHz
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APPLICATION CIRCUIT
T C K
T E S T / S B W T C K
n R S T / N M I / S B W T D I O
D V C C
V A S S
D V C C
V A C C
For a complete reference design including layout see the CC430 Wireless Development Tools and related
documentation.
Figure 27. Typical Application Circuit CC430F61xx
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T M S
T C K
D V C C
T E S T / S B W T C K
n R S T / N M I / S B W T D I O
D V C C
V A S S
V A C C
For a complete reference design including layout see the CC430 Wireless Development Tools and related
documentation.
Figure 28. Typical Application Circuit CC430F51xx
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Table 46. Bill of Materials
Component(s)
C1,3,4,5,7,9,11,13,15
C8,10,12,14
for 315 MHz
for 433 MHz
100 nF
10 µF
for 868/915 MHz
Comment
Decoupling capacitors
Decoupling capacitors
Decoupling capacitors
VCORE capacitor
C2,6,16,17,18
C19
2 pF
470 nF
RST decoupling cap
(optimized for SBW)
C20
2.2 nF
27 pF
Load capacitors for
26 MHz crystal(1)
C21,22
R1
R2
56 kΩ
47kΩ
R_BIAS (±1% required)
RST pullup
L1,2
L3,4
L5
Capacitors: 220 pF
0.033 µH
0.033 µH
dnp(2)
0.016 µH
0.027 µH
0.047 µH
dnp(2)
0.012 µH
0.018 µH
0.015 µH
0.0022 µH
0.015 µH
1 pF
L6
L7
0.033 µH
dnp(2)
0.051 µH
2.7 pF
C23
C24
C25
C26
C27
C28
C29
220 pF
220 pF
3.9 pF
100 pF
1.5 pF
6.8 pF
6.8 pF
3.9 pF
1.5 pF
220 pF
220 pF
4.7 pF
1.5 pF
10 pF
8.2 pF
220 pF
220 pF
1.5 pF
(1) The load capacitance CL seen by the crystal is CL = 1/((1/C21)+(1/C22)) + Cparasitic. The parasitic capacitance Cparasitic includes pin
capacitance and PCB stray capacitance. It can be typically estimated to be around 2.5 pF.
(2) dnp: do not populate.
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INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 to P1.4, Input/Output With Schmitt Trigger
S18...S22
(n/a CC430F513x)
LCDS18...LCDS22
Pad Logic
P1REN.x
P1MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P1OUT.x
0
1
from Port Mapping
P1.0/P1MAP0(/S18)
P1.1/P1MAP1(/S19)
P1.2/P1MAP2(/S20)
P1.3/P1MAP3(/S21)
P1.4/P1MAP4(/S22)
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
D
to Port Mapping
P1IRQ.x
P1IE.x
EN
Set
Q
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge
Select
CC430F513x devices don't provide LCD functionality on port P1 pins.
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Table 47. Port P1 (P1.0 to P1.4) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x)
x
FUNCTION
LCDS19...
22(1)
P1DIR.x
P1SEL.x
P1MAPx
P1.0/P1MAP/S18
0
P1.0 (I/O)
I: 0; O: 1
0; 1(2)
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
X
≤ 30(2)
= 31
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
Mapped secondary digital function - see Table 7
Output driver and input Schmitt trigger disabled
S18 (not available on CC430F513x)
P1.1 (I/O)
X
X
P1.1/P1MAP1/S19
P1.2/P1MAP2/S20
P1.3/P1MAP3/S21
P1.4/P1MAP4/S22
1
2
3
4
I: 0; O: 1
0; 1(2)
X
Mapped secondary digital function - see Table 7
Output driver and input Schmitt trigger disabled
S19 (not available on CC430F513x)
P1.2 (I/O)
≤ 30(2)
= 31
X
X
X
I: 0; O: 1
0; 1(2)
X
Mapped secondary digital function - see Table 7
Output driver and input Schmitt trigger disabled
S22 (not available on CC430F513x)
P1.3 (I/O)
≤ 30(2)
= 31
X
X
X
I: 0; O: 1
0; 1(2)
X
X
Mapped secondary digital function - see Table 7
Output driver and input Schmitt trigger disabled
S21 (not available on CC430F513x)
P1.4 (I/O)
≤ 30(2)
= 31
X
X
I: 0; O: 1
0; 1(2)
X
X
Mapped secondary digital function - see Table 7
Output driver and input Schmitt trigger disabled
S22 (not available on CC430F513x)
≤ 30(2)
= 31
X
X
(1) LCDSx not available in CC430F513x.
(2) According to mapped function - see Table 7.
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CC430F612x
CC430F513x
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SLAS554D –MAY 2009–REVISED JULY 2010
Port P1, P1.5 to P1.7, Input/Output With Schmitt Trigger
to LCD_B
(n/a CC430F513x)
Pad Logic
P1REN.x
P1MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P1OUT.x
0
1
from Port Mapping
P1.5/P1MAP5(/R23)
P1.6/P1MAP6(/R13)
P1.7/P1MAP7(/R03)
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
D
to Port Mapping
P1IRQ.x
P1IE.x
EN
Set
Q
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge
Select
CC430F513x devices don't provide LCD functionality on port P1 pins.
Table 48. Port P1 (P1.5 to P1.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
I: 0; O: 1
P1SEL.x
P1MAPx
P1.5/P1MAP5/R23
5
P1.5 (I/O)
0
1
1
0
1
1
0
1
1
X
≤ 30(1)
= 31
X
Mapped secondary digital function - see Table 7
R23(2) (not available on CC430F513x)
P1.6 (I/O)
0; 1(1)
X
P1.6/P1MAP6/R13/
LCDREF
6
7
I: 0; O: 1
0; 1(1)
X
Mapped secondary digital function - see Table 7
R13/LCDREF(2) (not available on CC430F513x)
P1.7 (I/O)
≤ 30(1)
= 31
X
P1.7/P1MAP7/R03
I: 0; O: 1
0; 1(1)
X
Mapped secondary digital function - see Table 7
R03(2) (not available on CC430F513x)
≤ 30(1)
= 31
(1) According to mapped function - see Table 7.
(2) Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver as well as the input Schmitt trigger.
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CC430F612x
CC430F513x
SLAS554D –MAY 2009–REVISED JULY 2010
www.ti.com
Port P2, P2.0 to P2.3, Input/Output With Schmitt Trigger
Pad Logic
To ADC12
(n/a CC430F612x)
INCHx = x
To Comparator_B
from Comparator_B
CBPD.x
P2REN.x
P2MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P2OUT.x
0
1
from Port Mapping
P2.0/P2MAP0/CB0(/A0)
P2.1/P2MAP2/CB1(/A1)
P2.2/P2MAP2/CB2(/A2)
P2.3/P2MAP3/CB3(/A3)
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
Bus
Keeper
EN
D
to Port Mapping
P2IRQ.x
P2IE.x
EN
Set
Q
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge
Select
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CC430F612x
CC430F513x
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SLAS554D –MAY 2009–REVISED JULY 2010
Port P2, P2.4 to P2.5, Input/Output With Schmitt Trigger
Pad Logic
to/from Reference
(n/a CC430F612x)
To ADC12
(n/a CC430F612x)
INCHx = x
To Comparator_B
from Comparator_B
CBPD.x
P2REN.x
P2MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P2OUT.x
0
1
from Port Mapping
P2.4/P2MAP4/CB4(/A4/VREF-/VeREF-)
P2.5/P2MAP5/CB5(/A5/VREF+/VeRF+)
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
Bus
Keeper
EN
D
to Port Mapping
P2IRQ.x
P2IE.x
EN
Set
Q
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge
Select
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CC430F613x
CC430F612x
CC430F513x
SLAS554D –MAY 2009–REVISED JULY 2010
www.ti.com
Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
Pad Logic
To ADC12
(n/a CC430F513x)
INCHx = x
To Comparator_B
(n/a CC430F513x)
from Comparator_B
CBPD.x
(n/a CC430F513x)
P2REN.x
P2MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P2OUT.x
0
1
from Port Mapping
P2.6/P2MAP6(/CB6/A6)
P2.7/P2MAP7(/CB7/A7)
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
Bus
Keeper
EN
D
to Port Mapping
P2IRQ.x
P2IE.x
EN
Set
Q
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge
Select
CC430F513x devices don't provide analog functionality on port P2.6 and P2.7 pins.
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CC430F612x
CC430F513x
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SLAS554D –MAY 2009–REVISED JULY 2010
Table 49. Port P2 (P2.0 to P2.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
P2MAPx
X
CBPD.x
P2.0/P2MAP0/CB0
(/A0)
0
P2.0 (I/O)
Mapped secondary digital function - see Table 7
I: 0; O: 1
0; 1(1)
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
0
0
X
1
0
0
X
1
0
0
X
1
0
0
X
1
0
0
X
1
0
0
X
1
0
0
≤ 30(1)
= 31
X
A0 (not available on CC430F612x)(2)
X
CB0(3)
X
I: 0; O: 1
0; 1(1)
X
P2.1/P2MAP1/CB1
(/A1)
1
2
3
4
5
6
P2.1 (I/O)
X
Mapped secondary digital function - see Table 7
A1 (not available on CC430F612x)(2)
≤ 30(1)
= 31
X
CB1(3)
X
P2.2/P2MAP2/CB2
(/A2)
P2.2 (I/O)
I: 0; O: 1
0; 1(1)
X
X
Mapped secondary digital function - see Table 7
A2 (not available on CC430F612x)(2)
≤ 30(1)
= 31
X
CB2(3)
X
P2.3/P2MAP3/CB3
(/A3)
P2.3 (I/O)
I: 0; O: 1
0; 1(1)
X
X
Mapped secondary digital function - see Table 7
A3 (not available on CC430F612x)(2)
≤ 30(1)
= 31
X
CB3(3)
X
P2.4/P2MAP4/CB4
(/A4/VREF-/VeREF-)
P2.4 (I/O)
I: 0; O: 1
0; 1(1)
X
X
Mapped secondary digital function - see Table 7
A4/VREF-/VeREF- (not available on CC430F612x)(2)
≤ 30(1)
= 31
X
CB4(3)
X
P2.5/P2MAP5/CB5
(/A5/VREF+/VeREF+)
P2.5 (I/O)
I: 0; O: 1
0; 1(1)
X
X
Mapped secondary digital function - see Table 7
A5/VREF+/VeREF+ (not available on CC430F612x)(2)
CB5(3)
≤ 30(1)
= 31
X
X
P2.6/P2MAP6(/CB6)
(/A6)
P2.6 (I/O)
I: 0; O: 1
0; 1(1)
X
Mapped secondary digital function - see Table 7
≤ 30(1)
A6 (not available on CC430F612x and
CC430F513x)(2)
X
1
= 31
X
CB6 (not available on CC430F513x)(3)
X
X
0
1
X
X
1
0
0
P2.7/P2MAP7(/CB7)
(/A7)
7
P2.7 (I/O)
I: 0; O: 1
0; 1(1)
Mapped secondary digital function - see Table 7
≤ 30(1)
A7 (not available on CC430F612x and
CC430F513x)(2)
CB7 (not available on CC430F513x)(3)
X
X
1
= 31
X
X
1
X
(1) According to mapped function - see Table 7.
(2) Setting P2SEL.x bit together with P2MAPx = PM_ANALOG disables the output driver as well as the input Schmitt trigger.
(3) Setting the CBPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input
buffer for that pin, regardless of the state of the associated CBPD.x bit.
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CC430F612x
CC430F513x
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Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
S10...S17
(n/a CC430F513x)
LCDS10...LCDS17
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
DVSS
DVCC
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
from Port Mapping
P3OUT.x
0
1
from Port Mapping
P3.0/P3MAP0(/S10)
P3.1/P3MAP1(/S11)
P3.2/P3MAP2(/S12)
P3.3/P3MAP3(/S13)
P3.4/P3MAP4(/S14)
P3.5/P3MAP5(/S15)
P3.6/P3MAP6(/S16)
P3.7/P3MAP7(/S17)
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Keeper
EN
D
to Port Mapping
CC430F513x devices don't provide LCD functionality on port P3 pins.
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CC430F612x
CC430F513x
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SLAS554D –MAY 2009–REVISED JULY 2010
Table 50. Port P3 (P3.0 to P3.7) Pin Functions
CONTROL BITS/SIGNALS
LCDS10...
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL.x
P3MAPx
17(1)
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
P3.0/P3MAP0/S10
P3.1/P3MAP1/S11
P3.2/P3MAP7/S12
P3.3/P3MAP3/S13
P3.4/P3MAP4/S14
P3.5/P3MAP5/S15
P3.6/P3MAP6/S16
P3.7/P3MAP7/S17
0
P3.0 (I/O)
Mapped secondary digital function - see Table 7
I: 0; O: 1
0; 1(2)
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
X
≤ 30(2)
= 31
X
Output driver and input Schmitt trigger disabled
S10 (not available on CC430F513x)
P3.1 (I/O)
X
X
1
2
3
4
5
6
7
I: 0; O: 1
0; 1(2)
X
Mapped secondary digital function - see Table 7
Output driver and input Schmitt trigger disabled
S11 (not available on CC430F513x)
P3.2 (I/O)
≤ 30(2)
= 31
X
X
X
I: 0; O: 1
0; 1(2)
X
Mapped secondary digital function - see Table 7
Output driver and input Schmitt trigger disabled
S12 (not available on CC430F513x)
P3.3 (I/O)
≤ 30(2)
= 31
X
X
X
I: 0; O: 1
0; 1(2)
X
Mapped secondary digital function - see Table 7
Output driver and input Schmitt trigger disabled
S13 (not available on CC430F513x)
P3.4 (I/O)
≤ 30(2)
= 31
X
X
X
I: 0; O: 1
0; 1(2)
X
Mapped secondary digital function - see Table 7
Output driver and input Schmitt trigger disabled
S14 (not available on CC430F513x)
P3.5 (I/O)
≤ 30(2)
= 31
X
X
X
I: 0; O: 1
0; 1(2)
X
Mapped secondary digital function - see Table 7
Output driver and input Schmitt trigger disabled
S15 (not available on CC430F513x)
P3.6 (I/O)
≤ 30(2)
= 31
X
X
X
I: 0; O: 1
0; 1(2)
X
X
Mapped secondary digital function - see Table 7
Output driver and input Schmitt trigger disabled
S16 (not available on CC430F513x)
P3.7 (I/O)
≤ 30(2)
= 31
X
X
I: 0; O: 1
0; 1(2)
X
X
Mapped secondary digital function - see Table 7
Output driver and input Schmitt trigger disabled
S17 (not available on CC430F513x)
≤ 30(2)
= 31
X
X
(1) LCDSx not available in CC430F513x.
(2) According to mapped function - see Table 7.
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CC430F612x
CC430F513x
SLAS554D –MAY 2009–REVISED JULY 2010
www.ti.com
Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger (CC430F613x and CC430F612x only)
S2...S9
LCDS2...LCDS9
Pad Logic
P4REN.x
DVSS
DVCC
0
1
1
P4DIR.x
0
1
Direction
0: Input
1: Output
P4OUT.x
DVSS
0
1
P4.0/S2
P4.1/S3
P4.2/S4
P4.3/S5
P4.4/S6
P4.5/S7
P4.6/S8
P4.7/S9
P4DS.x
P4SEL.x
P4IN.x
0: Low drive
1: High drive
Bus
EN
D
Keeper
Not Used
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CC430F612x
CC430F513x
www.ti.com
SLAS554D –MAY 2009–REVISED JULY 2010
Table 51. Port P4 (P4.0 to P4.7) Pin Functions (CC430F613x and CC430F612x only)
CONTROL BITS/SIGNALS
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL.x
LCDS2...7
P4.0/P4MAP0/S2
P4.1/P4MAP1/S3
P4.2/P4MAP7/S4
P4.3/P4MAP3/S5
P4.4/P4MAP4/S6
P4.5/P4MAP5/S7
P4.6/P4MAP6/S8
P4.7/P4MAP7/S9
0
P4.0 (I/O)
N/A
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
DVSS
S2
1
X
1
2
3
4
5
6
7
P4.1 (I/O)
N/A
I: 0; O: 1
0
DVSS
S3
1
X
P4.2 (I/O)
N/A
I: 0; O: 1
0
DVSS
S4
1
X
P4.3 (I/O)
N/A
I: 0; O: 1
0
DVSS
S5
1
X
P4.4 (I/O)
N/A
I: 0; O: 1
0
DVSS
S6
1
X
P4.5 (I/O)
N/A
I: 0; O: 1
0
DVSS
S7
1
X
P4.6 (I/O)
N/A
I: 0; O: 1
0
DVSS
S8
1
X
P4.7 (I/O)
N/A
I: 0; O: 1
0
1
X
DVSS
S9
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CC430F612x
CC430F513x
SLAS554D –MAY 2009–REVISED JULY 2010
www.ti.com
Port P5, P5.0, Input/Output With Schmitt Trigger
Pad Logic
to XT1
P5REN.0
DVSS
DVCC
0
1
1
P5DIR.0
0
1
P5OUT.0
0
1
Module X OUT
P5.0/XIN
P5DS.x
P5SEL.0
P5IN.0
0: Low drive
1: High drive
Bus
EN
D
Keeper
Module X IN
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CC430F613x
CC430F612x
CC430F513x
www.ti.com
SLAS554D –MAY 2009–REVISED JULY 2010
Port P5, P5.1, Input/Output With Schmitt Trigger
Pad Logic
to XT1
P5REN.1
DVSS
DVCC
0
1
1
P5DIR.1
0
1
P5OUT.1
0
1
Module X OUT
P5.1/XOUT
P5DS.x
P5SEL.0
0: Low drive
1: High drive
XT1BYPASS
P5IN.1
Bus
EN
D
Keeper
Module X IN
Table 52. Port P5 (P5.0 and P5.1) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.0
P5SEL.1
XT1BYPASS
P5.0/XIN
0
P5.0 (I/O)
I: 0; O: 1
0
1
1
0
1
1
X
X
X
X
X
X
X
0
1
X
0
1
XIN crystal mode(2)
XIN bypass mode(2)
P5.1 (I/O)
XOUT crystal mode(3)
P5.1 (I/O)(3)
X
X
P5.1/XOUT
1
I: 0; O: 1
X
X
(1) X = Don't care
(2) Setting P5SEL.0 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.0 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.0 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.1 can be used as
general-purpose I/O.
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CC430F612x
CC430F513x
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www.ti.com
Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger (CC430F613x and CC430F612x only)
S0(P5.2)/S1(P5.3)/S23(P5.4)
LCDS0(P5.2)/LCDS1(P5.3)/LCDS23(P5.4)
Pad Logic
P5REN.x
DVSS
DVCC
0
1
1
P5DIR.x
0
1
P5OUT.x
DVSS
0
1
P5.2/S0
P5.3/S1
P5.4/S23
P5DS.x
P5SEL.x
P5IN.x
0: Low drive
1: High drive
Bus
EN
D
Keeper
Not Used
Table 53. Port P5 (P5.2 to P5.3) Pin Functions (CC430F613x and CC430F612x only)
CONTROL BITS/SIGNALS
PIN NAME (P5.x)
P5.2/S0
x
FUNCTION
P5DIR.x
P5SEL.x
LCDS0...1
2
P5.2 (I/O)
N/A
I: 0; O: 1
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
DVSS
S0
1
X
P5.3/S1
3
P5.3 (I/O)
N/A
I: 0; O: 1
0
1
X
DVSS
S1
Table 54. Port P5 (P5.4) Pin Functions (CC430F613x and CC430F612x only)
CONTROL BITS/SIGNALS
PIN NAME (P5.x)
P5.4/S23
x
FUNCTION
P5DIR.x
P5SEL.x
LCDS23
4
P5.4 (I/O)
N/A
I: 0; O: 1
0
1
1
X
0
0
0
1
0
1
X
DVSS
S23
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CC430F513x
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SLAS554D –MAY 2009–REVISED JULY 2010
Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger (CC430F613x and CC430F612x only)
S24(P5.5)/S25(P5.6)/S26(P5.7)
LCDS24(P5.5)/LCDS25(P5.6)/LCDS26(P5.7)
COM3(P5.5)/COM2(P5.6)/COM1(P5.7)
Pad Logic
P5REN.x
DVSS
DVCC
0
1
1
P5DIR.x
P5OUT.x
P5.5/COM3/S24
P5.6/COM2/S25
P5.7/COM1/S26
P5DS.x
P5SEL.x
P5IN.x
0: Low drive
1: High drive
Bus
Keeper
Table 55. Port P5 (P5.5 to P5.7) Pin Functions (CC430F613x and CC430F612x only)
CONTROL BITS/SIGNALS
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.x
LCDS24...26
P5.5/COM3/S24
5
P5.5 (I/O)
COM3(1)
S24(1)
I: 0; O: 1
0
1
0
0
1
0
0
1
0
0
X
1
0
X
1
0
X
1
X
X
P5.6/COM2/S25
P5.7/COM1/S26
6
7
P5.6 (I/O)
COM2(1)
S25(1)
I: 0; O: 1
X
X
P5.7 (I/O)
COM1(1)
S26(1)
I: 0; O: 1
X
X
(1) Setting P5SEL.x bit disables the output driver as well as the input Schmitt trigger.
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www.ti.com
Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.0
0
1
DVSS
DVCC
1
PJDIR.0
DVCC
0
1
PJOUT.0
0
1
From JTAG
PJ.0/TDO
PJDS.0
From JTAG
PJIN.0
0: Low drive
1: High drive
Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.x
0
1
DVSS
DVCC
1
PJDIR.x
DVSS
0
1
PJOUT.x
0
1
From JTAG
PJ.1/TDI/TCLK
PJ.2/TMS
PJDS.x
From JTAG
PJIN.x
0: Low drive
1: High drive
PJ.3/TCK
EN
D
To JTAG
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CC430F513x
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SLAS554D –MAY 2009–REVISED JULY 2010
Table 56. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS/
SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
PJ.0/TDO
0
PJ.0 (I/O)(2)
I: 0; O: 1
TDO(3)
X
PJ.1/TDI/TCLK
PJ.2/TMS
1
2
3
PJ.1 (I/O)(2)
TDI/TCLK(3) (4)
PJ.2 (I/O)(2)
TMS(3) (4)
PJ.3 (I/O)(2)
TCK(3) (4)
I: 0; O: 1
X
I: 0; O: 1
X
PJ.3/TCK
I: 0; O: 1
X
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
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CC430F612x
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Device Descriptor Structures
Table 57 lists the content of the device descriptor tag-length-value (TLV) structure for CC430F613x and
CC430F613x device types.
Table 58 lists the content of the device descriptor tag-length-value (TLV) structure for CC430F612x device types.
Table 57. Device Descriptor Table
'F6137
Value
06h
'F6135
Value
06h
'F5137
Value
06h
'F5135
Value
06h
'F5133
Value
06h
Size
bytes
Description
Address
Info Block
Info length
CRC length
CRC value
Device ID
Device ID
01A00h
01A01h
01A02h
01A04h
01A05h
1
1
2
1
1
1
1
1
1
4
2
2
2
06h
06h
06h
06h
06h
per unit
61h
per unit
61h
per unit
51h
per unit
51h
per unit
51h
37h
35h
37h
35h
33h
Hardware revision 01A06h
Firmware revision 01A07h
10h
10h
10h
10h
10h
10h
10h
10h
10h
10h
Die Record
Die Record Tag
01A08h
08h
08h
08h
08h
08h
Die Record length 01A09h
0Ah
0Ah
0Ah
0Ah
0Ah
Lot/Wafer ID
Die X position
Die Y position
Test results
01A0Ah
01A0Eh
01A10h
01A12h
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC12
Calibration
ADC12 Calibration
Tag
01A14h
01A15h
1
1
11h
10h
11h
10h
11h
10h
11h
10h
11h
10h
ADC12 Calibration
length
ADC Gain Factor
ADC Offset
01A16h
01A18h
2
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5V
Reference
Temp. Sensor
30°C
01A1Ah
01A1Ch
01A1Eh
01A20h
01A22h
01A24h
2
2
2
2
2
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5V
Reference
Temp. Sensor
85°C
ADC 2.0V
Reference
Temp. Sensor
30°C
ADC 2.0V
Reference
Temp. Sensor
85°C
ADC 2.5V
Reference
Temp. Sensor
30°C
ADC 2.5V
Reference
Temp. Sensor
85°C
REF
Calibration
REF Calibration
Tag
01A26h
01A27h
1
1
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
REF Calibration
length
106
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CC430F612x
CC430F513x
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SLAS554D –MAY 2009–REVISED JULY 2010
Table 57. Device Descriptor Table (continued)
'F6137
Value
'F6135
Value
'F5137
Value
'F5135
Value
'F5133
Value
Size
bytes
Description
Address
1.5V Reference
Factor
01A28h
01A2Ah
01A2Ch
01A2Eh
01A2Fh
01A30h
2
2
2
1
1
per unit
per unit
per unit
02h
per unit
per unit
per unit
02h
per unit
per unit
per unit
02h
per unit
per unit
per unit
02h
per unit
per unit
per unit
02h
2.0V Reference
Factor
2.5V Reference
Factor
Peripheral
Descriptor
(PD)
Peripheral
Descriptor Tag
Peripheral
Descriptor Length
57h
57h
55h
55h
55h
Peripheral
Descriptors
PD
Length
...
...
...
...
...
Table 58. Device Descriptor Table CC430F612x
'F6127
Value
06h
'F6126
'F6125
Size
bytes
Description
Address
Value
06h
Value
06h
Info Block
Info length
CRC length
01A00h
01A01h
01A02h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Eh
01A10h
01A12h
01A14h
01A15h
01A16h
01A26h
01A27h
01A28h
01A2Ah
01A2Ch
01A2Eh
1
1
2
1
1
1
1
1
1
4
2
2
2
1
1
16
1
1
2
2
2
1
06h
06h
06h
CRC value
per unit
61h
per unit
61h
per unit
61h
Device ID
Device ID
27h
26h
25h
Hardware revision
Firmware revision
Die Record Tag
Die Record length
Lot/Wafer ID
Die X position
Die Y position
Test results
10h
10h
10h
10h
10h
10h
Die Record
08h
08h
08h
0Ah
0Ah
0Ah
per unit
per unit
per unit
per unit
05h
per unit
per unit
per unit
per unit
05h
per unit
per unit
per unit
per unit
05h
Empty Descriptor
REF Calibration
Empty Tag
Empty Tag Length
10h
10h
10h
undefined
12h
undefined
12h
undefined
12h
REF Calibration Tag
REF Calibration length
1.5V Reference Factor
2.0V Reference Factor
2.5V Reference Factor
Peripheral Descriptor Tag
06h
06h
06h
per unit
per unit
per unit
02h
per unit
per unit
per unit
02h
per unit
per unit
per unit
02h
Peripheral
Descriptor (PD)
Peripheral Descriptor
Length
01A2Fh
01A30h
1
55h
...
55h
...
55h
...
Peripheral Descriptors
PD Length
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REVISION HISTORY
REVISION
SLAS554
DESCRIPTION
Product Preview data sheet release
SLAS554A
SLAS554B
SLAS554C
Product Preview data sheet updated with electrical parameters
Production Data release data sheet for CC430F51xx devices. CC430F61xx devices are Product Preview.
Production Data release data sheet for CC430F61xx devices.
Added correct termination of LCDCAP/R33 if not used.
Corrected unit in Frequency Synthesizer Characteristics from "ms" to "µs".
SLAS554D
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Jul-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CC430F5133IRGZ
CC430F5133IRGZR
CC430F5133IRGZT
CC430F5135IRGZ
CC430F5135IRGZR
CC430F5135IRGZT
CC430F5137IRGZ
CC430F5137IRGZR
CC430F5137IRGZT
CC430F6125IRGC
CC430F6125IRGCR
CC430F6125IRGCT
CC430F6126IRGC
CC430F6126IRGCR
CC430F6126IRGCT
CC430F6127IRGC
CC430F6127IRGCR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
48
48
48
48
48
48
48
48
48
64
64
64
64
64
64
64
64
1000
2500
250
1000
2500
250
52
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
Purchase Samples
Purchase Samples
Purchase Samples
Purchase Samples
Purchase Samples
Purchase Samples
Purchase Samples
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Purchase Samples
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Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2500
250
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
250
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
250
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
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Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CC430F6127IRGCT
CC430F6135IRGC
CC430F6135IRGCR
CC430F6135IRGCT
CC430F6137IRGC
CC430F6137IRGCR
CC430F6137IRGCT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
RGC
RGC
RGC
64
64
64
64
64
64
64
250
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
Request Free Samples
Purchase Samples
2000
250
52
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Request Free Samples
Purchase Samples
2000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
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