CC1352P7_技术文档

CC1352P7

ZHCSO54A –MAY 2021 –REVISED NOVEMBER 2021

CC1352P7 具有集成功率放大器的

SimpleLink™ 高性能多频带无线MCU

• SimpleLink™ TI 15.4-stack

• 6LoWPAN

• 专有系统

1 特性

无线微处理器

• 功能强大的48MHz Arm® Cortex®-M4F 处理器

• 704KB 闪存程序存储器

• 256KB ROM，用于协议和库函数

• 8KB 高速缓存SRAM

• 具有奇偶校验功能的144KB 超低泄漏SRAM，可

实现高度可靠运行

高性能无线电

• -121dBm（在2.5kbps 远距离模式下）

• -110dBm（在50kbps、802.15.4、868MHz 时）

• -104dBm（在低功耗Bluetooth® 为125kbps 时）

• 高达+20dBm 的输出功率，具有温度补偿

法规遵从性

• 双频带Sub-1GHz 和2.4GHz 运行

• 动态多协议管理器(DMM) 驱动程序

• 可编程无线电包括对2-(G)FSK、4-(G)FSK、

MSK、OOK、低功耗Bluetooth® 5.2、IEEE

802.15.4 PHY 和MAC 的支持

• 适用于符合以下标准的系统：

– ETSI EN 300 220 接收器类别1.5 和2、EN 300

328、EN 303 131、EN 303 204、EN 300 440

类别2 和3

• 支持无线升级(OTA)

– FCC CFR47 第15 部分

超低功耗传感器控制器

– ARIB STD-T108 和STD-T66

• 具有4KB SRAM 的自主MCU

• 采样、存储和处理传感器数据

• 快速唤醒进入低功耗运行

MCU 外设

• 数字外设可连接至任何GPIO

• 四个32 位或八个16 位通用计时器

• 12 位ADC、200ksps、8 通道

• 8 位DAC

• 软件定义外设；电容式触控、流量计、LCD

低功耗

• 两个比较器

• 可编程电流源

• 两个UART、两个SSI、I²C、I²S

• 实时时钟(RTC)

• 集成温度和电池监控器

• MCU 功耗：

– 2.63mA 有源模式，CoreMark

– 55μA/MHz（运行CoreMark 时）

– 0.8μA 待机模式，RTC，144KB RAM

– 0.1μA 关断模式，引脚唤醒

信息安全机制

• 超低功耗传感器控制器功耗：

– 2MHz 模式下为25.2μA

– 24MHz 模式下为701μA

• 无线电功耗：

• AES 128 位和256 位加密加速计

• ECC 和RSA 公钥硬件加速器

• SHA2 加速器（包括至SHA-512 的全套装）

• 真随机数发生器(TRNG)

– RX：5.4mA（在868MHz 条件下）

– RX：6.4mA（在2.4GHz 条件下）

– TX：21mA（在+10dBm 和2.4GHz 条件下）

– TX：24.9mA（在+14dBm 和868MHz 条件

下）

– TX：64mA（在+20dBm 和915MHz 条件下）

– TX：101mA（在+20dBm 和2.4GHz 条件下）

开发工具和软件

• LP-CC1352P7 开发套件

• SimpleLink™ CC13xx 和CC26xx 软件开发套件

(SDK)

• 用于简单无线电配置的SmartRF™ Studio

• 用于构建低功耗检测应用的Sensor Controller

Studio

无线协议支持

• SysConfig 系统配置工具

• Thread、Zigbee®、Matter

• 低功耗Bluetooth® 5.2

• Wi-SUN®

工作温度范围

• 片上降压直流/直流转换器

• 1.8V 至3.8V 单电源电压

• -40°C 至+105°C

• mioty®

• Amazon Sidewalk

• 无线M-Bus

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SWRS251

CC1352P7

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ZHCSO54A –MAY 2021 –REVISED NOVEMBER 2021

封装

– 防火安全–烟雾和热量探测器、气体检测仪以

及火警控制面板

• 零售自动化

• 7mm × 7mm RGZ VQFN48 (26 GPIO)

• 符合RoHS 标准的封装

– 零售自动化和支付应用–电子货架标签和便携

式POS 终端

• 个人电子产品

2 应用

• 电网基础设施

– 射频远程控制

– 智能仪表–电表、水表、燃气表和热量分配表

– 电网通信–无线通信

– 智能扬声器、智能显示器和机顶盒

– 游戏、电子玩具和机器人玩具

– 可穿戴设备（非医用）、智能追踪器、智能服装

和智能手表

– 电动汽车充电基础设施–交流充电（桩）站

– 其他替代能源–能量收集

• 楼宇自动化

• 无线模块

– 楼宇安全系统–运动检测器、门窗传感器、玻

璃破裂探测器、紧急按钮、电子智能锁和IP 网

络摄像头

– HVAC 系统–恒温器、环境传感器和HVAC 控

制器

– 无线第三方模块包括低功耗蓝牙、Thread、

Zigbee、Matter、Wi-SUN^®、Amazon

Sidewalk、mioty^®和多协议

– 无线通信模块

3 说明

SimpleLink^™CC1352P7 器件是一款多协议、多频带 Sub-1GHz 和 2.4GHz 无线微控制器 (MCU)，支持以下协

议：Thread、Zigbee^®、低功耗 Bluetooth^®5.2、IEEE 802.15.4g、支持 IPv6 的智能对象 (6LoWPAN)、mioty^®、

Wi-SUN^®、专有系统（包括 TI 15.4-Stack（Sub-1GHz 和2.4GHz））和通过动态多协议管理器(DMM) 驱动程序

实现的并发多协议。CC1352P7 基于 Arm^®Cortex^®M4F 主处理器，针对电网基础设施、楼宇自动化、零售自动

化、个人电子产品和医疗应用中的低功耗无线通信和高级传感功能进行了优化。

CC1352P7 具有由 Arm^®Cortex^®-M0 驱动的软件定义无线电，支持多个物理层和射频标准。 CC1352P7 支持在

287MHz 至 351MHz、359MHz 至 527MHz、861MHz 至 1054MHz、1076MHz 至 1315MHz 以及 2360MHz 至

2500MHz 频带内运行。通过动态多协议管理器(DMM) 驱动程序，可在运行时完成 PHY 和频带切换。CC1352P7

具有高效的内置 PA，在 2.4GHz 频带中 TX 支持 +10dBm (21mA) 和 +20dBm (101mA) 的输出功率，在

Sub-1GHz 频带中TX 支持+20dBm (64mA) 的输出功率。

在保持 144KB RAM 时，CC1352P7 具有 0.9μA 的低待机电流。除了 Cortex® M4F 主处理器，该器件还具有能

够实现快速唤醒功能的自主式超低功耗传感器控制器 CPU。例如，传感器控制器能够在系统电流为 1µA 时进行

1Hz ADC 采样。

CC1352P7 具有低 SER（软错误率）FIT（时基故障），可延长运行寿命。SRAM 奇偶校验功能始终开启，可更

大程度地降低因潜在辐射事件导致的损坏风险。许多客户对产品生命周期的要求为 10 至 15 年或者更久，为了达

到这一目标，TI 制定了产品生命周期政策，对产品的寿命和供货连续性作出承诺。

CC1352P7 器件是 SimpleLink™ MCU 平台的一部分，包括 Wi-Fi®、低功耗 Bluetooth®、Thread、Zigbee、Wi-

SUN®、Amazon Sidewalk、mioty®、Sub-1GHz MCU 和主机 MCU。 CC1352P7 是可扩展产品系列（闪存为

32KB 至 704KB）的一部分，具有引脚对引脚兼容的封装选项。通用 SimpleLink™ CC13xx 和 CC26xx 软件开发

套件(SDK) 及SysConfig 系统配置工具支持产品系列中各器件之间的迁移。SDK 随附了丰富的软件栈、应用示例

和SimpleLink^™Academy 培训课程。有关更多信息，请查看无线连接。

器件信息

器件型号⁽¹⁾

CC1352P74T0RGZR

封装尺寸（标称值）

封装

VQFN (48)

7.00mm × 7.00mm

(1) 如需所有可用器件的最新器件、封装和订购信息，请参阅节11 中的“封装选项附录”或访问TI 网站。

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3.1 功能方框图

RF Core

cJTAG

Main CPU

256KB

ROM

ADC

Arm^®Cortex^®-M4F

Processor

704KB

Flash

Digital PLL

with 8KB

Cache

DSP Modem

16KB

SRAM

48 MHz

Arm^®Cortex^®-M0

Processor

144KB

SRAM

with Parity

ROM

General Hardware Peripherals and Modules

Sensor Interface

I²C and I²S

4× 32-bit Timers

2× SSI (SPI)

Watchdog Timer

TRNG

ULP Sensor Controller

8-bit DAC

2× UART

12-bit ADC, 200 ks/s

32 ch. µDMA

31 GPIOs

Low-Power Comparator

2x Low-Power Comparator

SPI-I²C Digital Sensor IF

Temperature and

Battery Monitor

AES-256, SHA2-512

ECC, RSA

Constant Current Source

RTC

Time-to-Digital Converter

LDO, Clocks, and References

Optional DC/DC Converter

4KB SRAM

图3-1. CC1352P7 方框图

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Table of Contents

7.18 Timing and Switching Characteristics..................... 24

7.19 Peripheral Characteristics.......................................28

7.20 Typical Characteristics............................................34

8 Detailed Description......................................................47

8.1 Overview...................................................................47

8.2 System CPU............................................................. 47

8.3 Radio (RF Core)........................................................48

8.4 Memory.....................................................................50

8.5 Sensor Controller......................................................50

8.6 Cryptography............................................................ 52

8.7 Timers....................................................................... 53

8.8 Serial Peripherals and I/O.........................................54

8.9 Battery and Temperature Monitor............................. 54

8.10 µDMA......................................................................54

8.11 Debug......................................................................54

8.12 Power Management................................................55

8.13 Clock Systems........................................................ 56

8.14 Network Processor..................................................56

9 Application, Implementation, and Layout................... 57

9.1 Reference Designs................................................... 57

9.2 Junction Temperature Calculation.............................58

10 Device and Documentation Support..........................59

10.1 Device Nomenclature..............................................59

10.2 Tools and Software................................................. 59

10.3 Documentation Support.......................................... 62

10.4 支持资源..................................................................62

10.5 Trademarks.............................................................62

10.6 Electrostatic Discharge Caution..............................63

10.7 术语表..................................................................... 63

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 2

3 说明................................................................................... 2

3.1 功能方框图..................................................................3

4 Revision History.............................................................. 4

5 Device Comparison.........................................................5

6 Terminal Configuration and Functions..........................6

6.1 Pin Diagram –RGZ Package (Top View)..................6

6.2 Signal Descriptions –RGZ Package.........................7

6.3 Connections for Unused Pins and Modules................8

7 Specifications.................................................................. 9

7.1 Absolute Maximum Ratings........................................ 9

7.2 ESD Ratings............................................................... 9

7.3 Recommended Operating Conditions.........................9

7.4 Power Supply and Modules...................................... 10

7.5 Power Consumption - Power Modes........................ 10

7.6 Power Consumption - Radio Modes......................... 11

7.7 Nonvolatile (Flash) Memory Characteristics............. 11

7.8 Thermal Resistance Characteristics......................... 12

7.9 RF Frequency Bands................................................12

7.10 861 MHz to 1054 MHz - Receive (RX)....................13

7.11 861 MHz to 1054 MHz - Transmit (TX) .................. 16

7.12 861 MHz to 1054 MHz - PLL Phase Noise

Wideband Mode.......................................................... 17

7.13 861 MHz to 1054 MHz - PLL Phase Noise

Narrowband Mode.......................................................18

7.14 Bluetooth Low Energy - Receive (RX).................... 18

7.15 Bluetooth Low Energy - Transmit (TX)....................21

7.16 Zigbee and Thread - IEEE 802.15.4-2006 2.4

GHz (OQPSK DSSS1:8, 250 kbps) - RX.................... 22

7.17 Zigbee and Thread - IEEE 802.15.4-2006 2.4

Information.................................................................... 64

GHz (OQPSK DSSS1:8, 250 kbps) - TX.....................23

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

November 2021

*

Initial Release

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5 Device Comparison

表5-1. Device Family Overview

FLASH

(KB)

RAM

(KB)

DEVICE

RADIO SUPPORT

GPIO

PACKAGE SIZE

RGZ (7-mm × 7-mm VQFN48)

RHB (5 mm × 5 mm VQFN32)

RSM (4 mm × 4 mm VQFN32)

Sub-1 GHz

Wireless M-Bus

CC1310

32-128

16-20

10-30

Sub-1 GHz

Wi-SUN^®

Amazon Sidewalk

Wireless M-Bus

CC1312R

CC1352P

352-704

80-144

30

26

RGZ (7-mm × 7-mm VQFN48)

Multiprotocol

Sub-1 GHz

Wi-SUN^®

Amazon Sidewalk

Wireless M-Bus

Bluetooth 5.2 Low Energy

Zigbee

352-704

80-144

Thread

2.4 GHz proprietary FSK-based formats

+20-dBm high-power amplifier

Multiprotocol

Sub-1 GHz

Wi-SUN^®

Wireless M-Bus

Bluetooth 5.2 Low Energy

Zigbee

CC1352R

352

80

28

RGZ (7-mm × 7-mm VQFN48)

Thread

2.4 GHz proprietary FSK-based formats

Bluetooth 5.2 Low Energy

2.4 GHz proprietary FSK-based formats

CC2642R

352

80

31

RGZ (7-mm × 7-mm VQFN48)

RTC (7-mm × 7-mm VQFN48)

CC2642R-Q1

Bluetooth 5.2 Low Energy

Multiprotocol

Bluetooth 5.2 Low Energy

Zigbee

CC2652R

352-704

352

80-144

80

31

RGZ (7-mm × 7-mm VQFN48)

Thread

2.4 GHz proprietary FSK-based formats

Multiprotocol

Bluetooth 5.2 Low Energy

Zigbee

CC2652RB

Thread

Multiprotocol

Bluetooth 5.2 Low Energy

Zigbee

CC2652P

352-704

80-144

26

RGZ (7-mm × 7-mm VQFN48)

Thread

2.4 GHz proprietary FSK-based formats

+19.5-dBm high-power amplifier

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6 Terminal Configuration and Functions

6.1 Pin Diagram –RGZ Package (Top View)

RF_P_2_4GHZ

RF_N_2_4GHZ

RF_P_SUB_1GHZ

RF_N_SUB_1GHZ

TX_20DBM_P

1

2

3

4

5

6

7

8

9

36 DIO_23

35 RESET_N

34 VDDS_DCDC

33 DCDC_SW

32 DIO_22

TX_20DBM_N

31 DIO_21

RX_TX

X32K_Q1

X32K_Q2

30 DIO_20

29 DIO_19

28 DIO_18

DIO_5 10

DIO_6 11

DIO_7 12

27 DIO_17

26 DIO_16

25 JTAG_TCKC

图6-1. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)

The following I/O pins marked in 图6-1 in bold have high-drive capabilities:

• Pin 10, DIO_5

• Pin 11, DIO_6

• Pin 12, DIO_7

• Pin 24, JTAG_TMSC

• Pin 26, DIO_16

• Pin 27, DIO_17

The following I/O pins marked in 图6-1 in italics have analog capabilities:

• Pin 36, DIO_23

• Pin 37, DIO_24

• Pin 38, DIO_25

• Pin 39, DIO_26

• Pin 40, DIO_27

• Pin 41, DIO_28

• Pin 42, DIO_29

• Pin 43, DIO_30

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6.2 Signal Descriptions –RGZ Package

表6-1. Signal Descriptions –RGZ Package

I/O

TYPE

DESCRIPTION

NAME

NO.

33

23

10

11

12

14

15

16

17

18

19

20

21

26

27

28

29

30

31

32

36

37

38

39

40

41

42

43

DCDC_SW

DCOUPL

DIO_5

Power

Output from internal DC/DC converter⁽¹⁾

—

For decoupling of internal 1.27 V regulated digital-supply ⁽²⁾

—

I/O

Digital

GPIO, high-drive capability

DIO_6

Digital

GPIO, high-drive capability

DIO_7

Digital

GPIO, high-drive capability

DIO_8

Digital

GPIO

DIO_9

Digital

GPIO

DIO_10

DIO_11

DIO_12

DIO_13

DIO_14

DIO_15

DIO_16

DIO_17

DIO_18

DIO_19

DIO_20

DIO_21

DIO_22

DIO_23

DIO_24

DIO_25

DIO_26

DIO_27

DIO_28

DIO_29

DIO_30

EGP

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO, JTAG_TDO, high-drive capability

GPIO, JTAG_TDI, high-drive capability

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital or Analog

GND

GPIO, analog capability

Ground –exposed ground pad⁽³⁾

JTAG TMSC, high-drive capability

JTAG TCKC

—

24

25

35

—

I/O

I

JTAG_TMSC

JTAG_TCKC

RESET_N

Digital

I

Digital

Reset, active low. No internal pullup resistor

Positive 2.4-GHz RF input signal to LNA during RX

Positive 2.4-GHz RF output signal from PA during TX

RF_P_2_4GHZ

1

2

3

4

RF

—

Negative 2.4-GHz RF input signal to LNA during RX

Negative 2.4-GHz RF output signal from PA during TX

RF_N_2_4GHZ

Positive Sub-1 GHz RF input signal to LNA during RX

Positive Sub-1 GHz RF output signal from PA during TX

RF_P_SUB_1GHZ

RF_N_SUB_1GHZ

Negative Sub-1 GHz RF input signal to LNA during RX

Negative Sub-1 GHz RF output signal from PA during TX

RX_TX

7

5

6

RF

Optional bias pin for the RF LNA

—

TX_20DBM_P

TX_20DBM_N

Positive Sub-1 GHz or 2.4-GHz high-power TX signal

Negative Sub-1 GHz or 2.4-GHz high-power TX signal

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表6-1. Signal Descriptions –RGZ Package (continued)

I/O

TYPE

DESCRIPTION

NAME

NO.

Internal supply, must be powered from the internal DC/DC

converter or the internal LDO^{(2) (4) (6)}

VDDR

45

Power

—

Internal supply, must be powered from the internal DC/DC

converter or the internal LDO^{(2) (5) (6)}

VDDR_RF

48

VDDS

44

13

22

34

46

47

8

Power

Analog

1.8-V to 3.8-V main chip supply⁽¹⁾

1.8-V to 3.8-V DIO supply⁽¹⁾

—

VDDS2

VDDS3

1.8-V to 3.8-V DIO supply⁽¹⁾

VDDS_DCDC

X48M_N

X48M_P

X32K_Q1

X32K_Q2

1.8-V to 3.8-V DC/DC converter supply

48-MHz crystal oscillator pin 1

48-MHz crystal oscillator pin 2

32-kHz crystal oscillator pin 1

32-kHz crystal oscillator pin 2

9

(1) For more details, see technical reference manual listed in 节10.3.

(2) Do not supply external circuitry from this pin.

(3) EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is

imperative for proper device operation.

(4) If internal DC/DC converter is not used, this pin is supplied internally from the main LDO.

(5) If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO.

(6) Output from internal DC/DC and LDO is trimmed to 1.68 V.

6.3 Connections for Unused Pins and Modules

表6-2. Connections for Unused Pins

PREFERRED

FUNCTION

SIGNAL NAME

PIN NUMBER

ACCEPTABLE PRACTICE⁽¹⁾

PRACTICE⁽¹⁾

10–12

14–21

26–32

36–43

GPIO

DIO_n

NC or GND

NC

X32K_Q1

8

9

32.768-kHz crystal

NC or GND

NC

X32K_Q2

DCDC_SW

VDDS_DCDC

33

34

NC

DC/DC converter⁽²⁾

VDDS

(1) NC = No connect

(2) When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still

be connected and the 22 uF DCDC capacitor must be kept on the VDDR net.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

–0.3

MAX UNIT

VDDS⁽³⁾

Supply voltage

4.1

V

Voltage on any digital pin⁽⁴⁾

VDDS + 0.3, max 4.1

Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P

Voltage scaling enabled

VDDR + 0.3, max 2.25

VDDS

V_in

Voltage on ADC input

Voltage scaling disabled, internal reference

Voltage scaling disabled, VDDS as reference

1.49

V

VDDS / 2.9

Input level, Sub-1 GHz RF pins (RF_P_SUB_1GHZ and RF_N_SUB_1GHZ)

Input level, 2.4 GHz RF pins (RF_P_2_4GHZ and RF_N_2_4GHZ)

Storage temperature

10

5

dBm

°C

T_stg

150

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to ground, unless otherwise noted.

(3) VDDS_DCDC, VDDS2 and VDDS3 must be at the same potential as VDDS.

(4) Including analog capable DIOs.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

V

Human body model (HBM), per ANSI/ESDA/JEDEC JS001⁽¹⁾

Charged device model (CDM), per JESD22-C101⁽²⁾

All pins

V_ESD

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

105

115

3.8

UNIT

°C

Operating ambient temperature^{(1) (3)}

–40

Operating junction temperature^{(1) (3)}

°C

–40

Operating supply voltage (VDDS)

1.8

2.1

V

Operating supply voltage (VDDS), boost mode

VDDR = 1.95 V

3.8

V

+14 dBm RF output sub-1 GHz power amplifier

Rising supply voltage slew rate

Falling supply voltage slew rate⁽²⁾

0

100

20

mV/µs

(1) Operation at or near maximum operating temperature for extended durations will result in a reduction in lifetime.

(2) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used

to ensure compliance with this slew rate.

(3) For thermal resistance characteristics refer to 节7.8.

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7.4 Power Supply and Modules

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

TYP

1.1 - 1.55

1.77

MAX

UNIT

VDDS Power-on-Reset (POR) threshold

V

VDDS Brown-out Detector (BOD) ⁽¹⁾

Rising threshold

Falling threshold

VDDS Brown-out Detector (BOD), before initial boot ⁽²⁾

VDDS Brown-out Detector (BOD) ⁽¹⁾

1.70

1.75

(1) For boost mode (VDDR =1.95 V), TI drivers software initialization will trim VDDS BOD limits to maximum (approximately 2.0 V)

(2) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin

7.5 Power Consumption - Power Modes

When measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with T_c= 25 °C, V_DDS= 3.6 V with DC/DC

enabled unless otherwise noted.

PARAMETER

TEST CONDITIONS

TYP

UNIT

Core Current Consumption

Reset. RESET_N pin asserted or VDDS below power-on-reset threshold

Shutdown. No clocks running, no retention

110

Reset and Shutdown

nA

RTC running, CPU, 144KB RAM and (partial) register retention.

RCOSC_LF

0.8

0.7

µA

mA

Standby

RTC running, CPU, 64KB RAM and (partial) register retention.

without cache retention RCOSC_LF

RTC running, CPU, 144KB RAM and (partial) register retention

XOSC_LF

0.9

I_core

RTC running, CPU, 144KB RAM and (partial) register retention.

RCOSC_LF

1.9

Standby

with cache retention

RTC running, CPU, 144KB RAM and (partial) register retention.

XOSC_LF

2.0

Supply Systems and RAM powered

RCOSC_HF

Idle

590

2.63

MCU running CoreMark at 48 MHz

RCOSC_HF

Active

Peripheral Current Consumption

Peripheral power

domain

Delta current with domain enabled

39

2.6

89

Serial power domain

RF Core

Delta current with power domain enabled,

clock enabled, RF core idle

µDMA

Timers

Delta current with clock enabled, module is idle

Delta current with clock enabled, module is idle⁽³⁾

Delta current with clock enabled, module is idle

Delta current with clock enabled, module is idle⁽²⁾

Delta current with clock enabled, module is idle⁽¹⁾

Delta current with clock enabled, module is idle

57

97

I_peri

µA

I2C

9.2

22

I2S

SSI

50

UART

110

16

CRYPTO (AES)

PKA

TRNG

59

20

Sensor Controller Engine Consumption

Active mode

I_SCE

24 MHz, infinite loop

2 MHz, infinite loop

701

µA

Low-power mode

25.2

(1) Only one UART running

(2) Only one SSI running

(3) Only one GPTimer running

10

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7.6 Power Consumption - Radio Modes

When measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with T_c= 25 °C, V_DDS= 3.6 V with DC/DC

enabled unless otherwise noted.

High power PA connected to V_DDSunless otherwise noted.

Using boost mode (increasing VDDR up to 1.95 V), will increase system current by 15% (does not apply to TX +14 dBm

setting where this current is already included).

Relevant I_coreand I_pericurrents are included in below numbers.

PARAMETER

TEST CONDITIONS

TYP UNIT

Radio receive current, 868 MHz

5.4

7.1

mA

Radio receive current, 2.44 GHz

(Bluetooth Low Energy)

V_DDS= 3.0 V

0 dBm output power setting

868 MHz

8.0

14.3

24.9

7.5

mA

Radio transmit current

Sub-1 GHz PA

+10 dBm output power setting

868 MHz

Radio transmit current

Boost mode, Sub-1 GHz PA

+14 dBm output power setting

868 MHz

Radio transmit current

2.4 GHz PA (Bluetooth Low Energy)

0 dBm output power setting, V_DDS= 3.0 V

+5 dBm output power setting

Radio transmit current

9.8

2.4 GHz PA (Bluetooth Low Energy) 2440 MHz, V_DDS= 3.0 V

Radio transmit current

High-power PA

Transmit (TX), +20 dBm output power setting

915 MHz, VDDS = 3.3 V

64

Radio transmit current

High-power PA⁽¹⁾

Transmit (TX), +20 dBm output power setting

2440 MHz (Bluetooth Low Energy), VDDS = 3.0 V

101

Radio transmit current

High-power PA, 10 dBm

configuration⁽²⁾

Transmit (TX), +10 dBm output power setting

2440 MHz (Bluetooth Low Energy), VDDS = 3.0 V

21

mA

(1) Measured on the CC1352-P7EM-XD7793-XD24-PA24 reference design.

(2) Measured on the CC1352-P7EM-XD7793-XD24-PA24_10dBm reference design.

7.7 Nonvolatile (Flash) Memory Characteristics

Over operating free-air temperature range and V_DDS= 3.0 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Flash sector size

8

KB

Supported flash erase cycles before failure, single-bank^{(1) (5)}

Supported flash erase cycles before failure, single sector⁽²⁾

30

60

k Cycles

Maximum number of write operations per row before sector

erase⁽³⁾

Write

Operations

83

Years at 105

°C

Flash retention

105 °C

11.4

Flash sector erase current

Average delta current

Zero cycles

9.5

10

mA

ms

mA

µs

Flash sector erase time⁽⁴⁾

30k cycles

4000

Flash write current

Flash write time⁽⁴⁾

Average delta current, 4 bytes at a time

4 bytes at a time

5.2

21.6

(1) A full bank erase is counted as a single erase cycle on each sector. If both flash banks are always cycled simultaneously they can be

cycled 30K times each. Alternatively, the banks can be cycled a total of 30K times, e.g. the main bank X times and the second bank Y

times (X+Y=30K)

(2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k

cycles

(3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per

write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum

number of write operations per row is reached.

(4) This number is dependent on Flash aging and increases over time and erase cycles

(5) Aborting flash during erase or program modes is not a safe operation.

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7.8 Thermal Resistance Characteristics

PACKAGE

RGZ

(VQFN)

THERMAL METRIC⁽¹⁾

UNIT

48 PINS

23.7

13.0

7.7

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W⁽²⁾

R_θJC(top)

R_θJB

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JT

7.6

ψ_JB

R_θJC(bot)

1.9

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) °C/W = degrees Celsius per watt.

7.9 RF Frequency Bands

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

MIN

2360

1076

861

TYP

MAX

UNIT

2500

1315

1054

527

Frequency bands

MHz

431

359

439

287

351

12

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7.10 861 MHz to 1054 MHz - Receive (RX)

Measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with T_c= 25 °C, V_DDS= 3.6 V with

DC/DC enabled and high power PA connected to V_DDSunless otherwise noted.

All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is

measured at a dedicated antenna connection. All measurements are performed conducted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

General Parameters

Digital channel filter programmable receive

bandwidth

4

4000

kHz

Data rate step size

1.5

< -57

< -47

bps

dBm

Spurious emissions 25 MHz to 1 GHz

Spurious emissions 1 GHz to 13 GHz

868 MHz

Conducted emissions measured according to ETSI EN 300 220

802.15.4, 50 kbps, ±25 kHz deviation, 2-GFSK, 100 kHz RX Bandwidth

Sensitivity

BER = 10^–2, 868 MHz

BER = 10^–2, 868 MHz⁽¹⁾

dBm

dB

–110

10

Saturation limit

Selectivity, ±200 kHz

Selectivity, ±400 kHz

Blocking, ±1 MHz

Blocking, ±2 MHz

Blocking, ±5 MHz

Blocking, ±10 MHz

44

49

dB

58

dB

62

dB

70

dB

78

dB

Image rejection (image compensation

enabled)

BER = 10^–2, 868 MHz⁽¹⁾

39

dB

RSSI dynamic range

RSSI accuracy

Starting from the sensitivity limit

95

±3

dB

Starting from the sensitivity limit across the given dynamic range

802.15.4, 100 kbps, ±25 kHz deviation, 2-GFSK, 137 kHz RX Bandwidth

Sensitivity 100 kbps

Selectivity, ±200 kHz

Selectivity, ±400 kHz

Co-channel rejection

868 MHz, 1% PER, 127 byte payload

-103

38

dBm

dB

868 MHz, 1% PER, 127 byte payload. Wanted signal at -96 dBm

868 MHz, 1% PER, 127 byte payload. Wanted signal at -79 dBm

45

dB

-9

dB

802.15.4, 200 kbps, ±50 kHz deviation, 2-GFSK, 311 kHz RX Bandwidth

Sensitivity

BER = 10^–2, 868 MHz

BER = 10^–2, 915 MHz

dBm

–103

BER = 10^–2, 915 MHz. Wanted signal 3 dB above sensitivity

limit.

Selectivity, ±400 kHz

Selectivity, ±800 kHz

Blocking, ±2 MHz

44

49

57

69

dB

BER = 10^–2, 915 MHz. Wanted signal 3 dB above sensitivity

limit.

BER = 10^–2, 915 MHz. Wanted signal 3 dB above sensitivity

limit.

BER = 10^–2, 915 MHz. Wanted signal 3 dB above sensitivity

limit.

Blocking, ±10 MHz

802.15.4, 500 kbps, ±190 kHz deviation, 2-GFSK, 655 kHz RX Bandwidth

Sensitivity 500 kbps

Selectivity, ±1 MHz

Selectivity, ±2 MHz

Co-channel rejection

916 MHz, 1% PER, 127 byte payload

-95

35

47

-9

dBm

dB

916 MHz, 1% PER, 127 byte payload. Wanted signal at -88 dBm

916 MHz, 1% PER, 127 byte payload. Wanted signal at -71 dBm

dB

SimpleLink™ Long Range 2.5 kbps or 5 kbps (20 ksym/s, 2-GFSK, ±5 kHz Deviation, FEC (Half Rate), DSSS = 1:2 or 1:4, 34 kHz RX Bandwidth

Sensitivity

2.5 kbps, BER = 10^–2, 868 MHz

5 kbps, BER = 10^–2, 868 MHz

2.5 kbps, BER = 10^–2, 868 MHz

2.5 kbps, BER = 10^–2, 868 MHz⁽¹⁾

-121

-119

10

dBm

dB

Sensitivity

Saturation limit

Selectivity, ±100 kHz

Selectivity, ±200 kHz

Selectivity, ±300 kHz

Blocking, ±1 MHz

49

50

dB

51

dB

63

dB

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7.10 861 MHz to 1054 MHz - Receive (RX) (continued)

Measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with T_c= 25 °C, V_DDS= 3.6 V with

DC/DC enabled and high power PA connected to V_DDSunless otherwise noted.

All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is

measured at a dedicated antenna connection. All measurements are performed conducted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Blocking, ±2 MHz

2.5 kbps, BER = 10^–2, 868 MHz⁽¹⁾

69

dB

Blocking, ±5 MHz

Blocking, ±10 MHz

2.5 kbps, BER = 10^–2, 868 MHz⁽¹⁾

79

88

Image rejection (image compensation

enabled)

2.5 kbps, BER = 10^–2, 868 MHz⁽¹⁾

47

dB

RSSI dynamic range

RSSI accuracy

Starting from the sensitivity limit

108

±3

dB

Starting from the sensitivity limit across the given dynamic range

OOK, 4.8 kbps, 39 kHz RX Bandwidth

Sensitivity

BER = 10^–2, 868 MHz

BER = 10^–2, 915 MHz

-114

dBm

Sensitivity

Narrowband, 9.6 kbps ±2.4 kHz deviation, 2-GFSK, 868 MHz, 17.1 kHz RX Bandwidth

Sensitivity

1% BER

-117

41

dBm

dB

1% BER. Wanted signal 3 dB above the ETSI reference

sensitivity limit (-104.6 dBm). Interferer ±20 kHz

Adjacent Channel Rejection

1% BER. Wanted signal 3 dB above the ETSI reference

sensitivity limit (-104.6 dBm). Interferer ±40 kHz

Alternate Channel Rejection

Blocking, ±1 MHz

42

65

69

85

dB

1% BER. Wanted signal 3 dB above the ETSI reference

sensitivity limit (-104.6 dBm).

1% BER. Wanted signal 3 dB above the ETSI reference

sensitivity limit (-104.6 dBm).

Blocking, ±2 MHz

1% BER. Wanted signal 3 dB above the ETSI reference

sensitivity limit (-104.6 dBm).

Blocking, ±10 MHz

1 Mbps, ±350 kHz deviation, 2-GFSK, 2.2 MHz RX Bandwidth

Sensitivity

BER = 10^–2, 868 MHz

BER = 10^–2, 915 MHz

-97

dBm

BER = 10^–2, 915 MHz. Wanted signal 3 dB above sensitivity

limit.

Blocking, +2 MHz

Blocking, -2 MHz

Blocking, +10 MHz

44

27

59

54

dB

BER = 10^–2, 915 MHz. Wanted signal 3 dB above sensitivity

limit.

BER = 10^–2, 915 MHz. Wanted signal 3 dB above sensitivity

limit.

BER = 10^–2, 915 MHz. Wanted signal 3 dB above sensitivity

limit.

Blocking, -10 MHz

Wi-SUN, 2-GFSK

Sensitivity

50 kbps, ±12.5 kHz deviation, 2-GFSK, 866.6 MHz, 68 kHz RX

BW, 10% PER, 250 byte payload

-107

30

dBm

dB

50 kbps, ±12.5 kHz deviation, 2-GFSK, 68 kHz RX Bandwidth,

866.6 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB

above sensitivity level

Selectivity, ±100 kHz, 50 kbps, ±12.5 kHz

deviation, 2-GFSK, 866.6 MHz

50 kbps, ±12.5 kHz deviation, 2-GFSK, 68 kHz RX Bandwidth,

866.6 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB

above sensitivity level

Selectivity, ±200 kHz, 50 kbps, ±12.5 kHz

deviation, 2-GFSK, 866.6 MHz

36

-107

34

dB

dBm

dB

50 kbps, ±25 kHz deviation, 2-GFSK, 98 kHz RX Bandwidth,

918.2 MHz, 10% PER, 250 byte payload

Sensitivity

50 kbps, ±25 kHz deviation, 2-GFSK, 98 kHz RX Bandwidth,

918.2 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB

above sensitivity level

Selectivity, ±200 kHz, 50 kbps, ±25 kHz

deviation, 2-GFSK, 918.2 MHz

50 kbps, ±25 kHz deviation, 2-GFSK, 98 kHz RX Bandwidth,

918.2 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB

above sensitivity level

Selectivity, ±400 kHz, 50 kbps, ±25 kHz

deviation, 2-GFSK, 918.2 MHz

41

dB

100 kbps, ±25 kHz deviation, 2-GFSK, 866.6 MHz, 135 kHz RX

BW, 10% PER, 250 byte payload

Sensitivity

-104

dBm

14

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7.10 861 MHz to 1054 MHz - Receive (RX) (continued)

Measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with T_c= 25 °C, V_DDS= 3.6 V with

DC/DC enabled and high power PA connected to V_DDSunless otherwise noted.

All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is

measured at a dedicated antenna connection. All measurements are performed conducted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

100 kbps, ±25 kHz deviation, 2-GFSK, 135 kHz RX Bandwidth,

866.6 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB

above sensitivity level

Selectivity, ±200 kHz, 100 kbps, ±25 kHz

deviation, 2-GFSK, 866.6 MHz

37

dB

100 kbps, ±25 kHz deviation, 2-GFSK, 135 kHz RX Bandwidth,

866.6 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB

above sensitivity level

Selectivity, ±400 kHz, 100 kbps, ±25 kHz

deviation, 2-GFSK, 866.6 MHz

45

-102

40

dB

dBm

dB

100 kbps, ±50 kHz deviation, 2-GFSK, 920.9 MHz, 196 kHz RX

BW, 10% PER, 250 byte payload

Sensitivity

100 kbps, ±50 kHz deviation, 2-GFSK, 196 kHz RX Bandwidth,

920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB

above sensitivity level

Selectivity, ±400 kHz, 100 kbps, ±50 kHz

deviation, 2-GFSK, 920.9 MHz

100 kbps, ±50 kHz deviation, 2-GFSK, 196 kHz RX Bandwidth,

920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB

above sensitivity level

Selectivity, ±800 kHz, 100 kbps, ±50 kHz

deviation, 2-GFSK, 920.9 MHz

49

-99

41

dB

dBm

dB

150 kbps, ±37.5 kHz deviation, 2-GFSK, 920.9 MHz, 273 kHz RX

BW, 10% PER, 250 byte payload

Sensitivity

150 kbps, ±37.5 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth,

920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB

above sensitivity level

Selectivity, ±400 kHz, 150 kbps, ±37.5 kHz

deviation, 2-GFSK, 920.9 MHz

150 kbps, ±37.5 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth,

920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB

above sensitivity level

Selectivity, ±800 kHz, 150 kbps, ±37.5 kHz

deviation, 2-GFSK, 920.9 MHz

47

-99

42

dB

dBm

dB

200 kbps, ±50 kHz deviation, 2-GFSK, 918.4 MHz, 273 kHz RX

BW, 10% PER, 250 byte payload

Sensitivity

200 kbps, ±50 kHz deviation, 2-GFSK, 273 kHz RX

Bandwidth, 918.4 MHz, 10% PER, 250 byte payload. Wanted

signal 3 dB above sensitivity level

Selectivity, ±400 kHz, 200 kbps, ±50 kHz

deviation, 2-GFSK, 918.4 MHz

200 kbps, ±50 kHz deviation, 2-GFSK, 273 kHz RX

Bandwidth, 918.4 MHz, 10% PER, 250 byte payload. Wanted

signal 3 dB above sensitivity level

Selectivity, ±800 kHz, 200 kbps, ±50 kHz

deviation, 2-GFSK, 918.4 MHz

49

-99

45

dB

dBm

dB

200 kbps, ±100 kHz deviation, 2-GFSK, 920.8 MHz, 273 kHz RX

BW, 10% PER, 250 byte payload

Sensitivity

200 kbps, ±100 kHz deviation, 2-GFSK, 273 kHz RX

Bandwidth, 920.8 MHz,, 10% PER, 250 byte payload. Wanted

signal 3 dB above sensitivity level

Selectivity, ±600 kHz, 200 kbps, ±100 kHz

deviation, 2-GFSK, 920.8 MHz

200 kbps, ±100 kHz deviation, 2-GFSK, 273 kHz RX

Bandwidth, 920.8 MHz,, 10% PER, 250 byte payload. Wanted

signal 3 dB above sensitivity level

Selectivity, ±1200 kHz, 200 kbps, ±100 kHz

deviation, 2-GFSK, 920.8 MHz

52

-97

42

dB

dBm

dB

300 kbps, ±75 kHz deviation, 2-GFSK, 917.6 MHz, 498 kHz RX

BW, 10% PER, 250 byte payload

Sensitivity

300 kbps, ±75 kHz deviation, 2-GFSK, 498 kHz RX Bandwidth,

917.6 MHz,, 10% PER, 250 byte payload. Wanted signal 3 dB

above sensitivity level

Selectivity, ±600 kHz, 300 kbps, ±75 kHz

deviation, 2-GFSK, 917.6 MHz

300 kbps, ±75 kHz deviation, 2-GFSK, 498 kHz RX Bandwidth,

917.6 MHz,, 10% PER, 250 byte payload. Wanted signal 3 dB

above sensitivity level

Selectivity, ±1200 kHz, 300 kbps, ±75 kHz

deviation, 2-GFSK, 917.6 MHz

47

dB

(1) Wanted signal 3 dB above the reference sensitivity limit according to ETSI EN 300 220 v. 3.1.1

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7.11 861 MHz to 1054 MHz - Transmit (TX)

Measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with T_c= 25°C, V_DDS= 3.6 V with

DC/DC enabled and high power PA connected to V_DDSunless otherwise noted.

All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is

measured at a dedicated antenna connection. All measurements are performed conducted. ⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

General parameters

VDDR = 1.95 V

Minimum supply voltage (VDDS ) for boost

mode is 2.1 V

Max output power, boost mode Sub-1 GHz PA⁽²⁾

14

dBm

868 MHz and 915 MHz

Max output power, Sub-1 GHz PA⁽²⁾

868 MHz and 915 MHz

13

20

34

6

dBm

dB

915 MHz

VDDS = 3.3V

Max output power, High power PA

Output power programmable range Sub-1 GHz PA

868 MHz and 915 MHz

Output power programmable range

High power PA

868 MHz and 915 MHz

VDDS = 3.3V

dB

+10 dBm setting

Output power variation over temperature Sub-1 GHz PA

Over recommended temperature operating

range

±2

dB

+14 dBm setting

Over recommended temperature operating

range

Output power variation over temperature Boost mode, Sub-1 GHz

PA

±1.5

Spurious emissions and harmonics

+14 dBm setting

ETSI restricted bands

< -54

< -36

< -30

< -56

< -52

< -50

dBm

Spurious emissions

30 MHz to 1 GHz

(excluding harmonics)

+14 dBm setting

ETSI outside restricted bands

Sub-1 GHz PA, 868 MHz

(3)

1 GHz to 12.75 GHz

(outside ETSI restricted bands)

+14 dBm setting

measured in 1 MHz bandwidth (ETSI)

30 MHz to 88 MHz

(within FCC restricted bands)

+14 dBm setting

88 MHz to 216 MHz

(within FCC restricted bands)

Spurious emissions out-

216 MHz to 960 MHz

of-band

(within FCC restricted bands)

Sub-1 GHz PA, 915 MHz

(3)

960 MHz to 2390 MHz and above

2483.5 MHz (within FCC restricted

band)

+14 dBm setting

<-42

dBm

1 GHz to 12.75 GHz

(outside FCC restricted bands)

+14 dBm setting

< -40

< -55

< -52

< -49

dBm

30 MHz to 88 MHz

(within FCC restricted bands)

+20 dBm setting, VDDS = 3.3 V

88 MHz to 216 MHz

(within FCC restricted bands)

Spurious emissions out-

216 MHz to 960 MHz

of-band

(within FCC restricted bands)

High power PA, 915

MHz^{(3) (4)}

960 MHz to 2390 MHz and above

2483.5 MHz (within FCC restricted

band)

+20 dBm setting, VDDS = 3.3 V

< -41

< -20

dBm

1 GHz to 12.75 GHz

(outside FCC restricted bands)

16

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7.11 861 MHz to 1054 MHz - Transmit (TX) (continued)

Measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with T_c= 25°C, V_DDS= 3.6 V with

DC/DC enabled and high power PA connected to V_DDSunless otherwise noted.

All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is

measured at a dedicated antenna connection. All measurements are performed conducted. ⁽¹⁾

PARAMETER

TEST CONDITIONS

+14 dBm setting

MIN

TYP

MAX UNIT

Below 710 MHz

(ARIB T-108)

< -36

dBm

710 MHz to 900 MHz

(ARIB T-108)

+14 dBm setting

< -55

< -45

< -30

dBm

900 MHz to 915 MHz

(ARIB T-108)

Spurious emissions out-

of-band

Sub-1 GHz PA, 920.6/928

930 MHz to 1000 MHz

(ARIB T-108)

MHz ⁽³⁾

1000 MHz to 1215 MHz

(ARIB T-108)

Above 1215 MHz

(ARIB T-108)

+14 dBm setting, 868 MHz

< -30

< -42

< -30

< -42

< -30

< -42

< -30

< -42

Second harmonic

Third harmonic

Fourth harmonic

Fifth harmonic

dBm

+14 dBm setting, 915 MHz

+14 dBm setting, 868 MHz

+14 dBm setting, 915 MHz

Harmonics

Sub-1 GHz PA

+14 dBm setting, 868 MHz

+14 dBm setting, 915 MHz

+14 dBm setting, 868 MHz

+14 dBm setting, 915 MHz

Second harmonic

Third harmonic

Fourth harmonic

Fifth harmonic

+20 dBm setting, VDDS = 3.3 V, 915 MHz

dBm

Harmonics

High power PA

Adjacent Channel Power

Adjacent channel power, Adjacent channel, 20 kHz offset. 9.6

regular 14 dBm PA kbps, h=0.5

12.5 dBm setting. 868.3 MHz. 14 kHz channel

BW

-23

-29

dBm

Alternate channel power, Alternate channel, 40 kHz offset. 9.6

regular 14 dBm PA kbps, h=0.5

12.5 dBm setting. 868.3 MHz. 14 kHz channel

BW

(1) Some combinations of frequency, data rate and modulation format requires use of external crystal load capacitors for regulatory

compliance. More details can be found in the device errata.

(2) Output power is dependent on RF match. For dual-band devices in the CC13X2 platform, output power might be slightly reduced

depending on RF layout trade-offs.

(3) Suitable for systems targeting compliance with EN 300 220, EN 303 131, EN 303 204, FCC CFR47 Part 15, ARIB STD-T108.

(4) Spurious emissions increase for supply voltages below 2.2 V. As such, care must be taken to ensure regulatory requirements are met

when operating at low supply voltage levels. An alternative is to use the Sub-1 GHz PA below 2.2 V.

7.12 861 MHz to 1054 MHz - PLL Phase Noise Wideband Mode

When measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with T_c= 25 °C, V_DDS= 3.0 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

±10 kHz offset

dBc/Hz

–75

±100 kHz offset

±200 kHz offset

±400 kHz offset

±1000 kHz offset

±2000 kHz offset

±10000 kHz offset

–98

–106

–113

–122

–129

–140

Phase noise in the 868- and 915-MHz bands

20 kHz PLL loop bandwidth

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7.13 861 MHz to 1054 MHz - PLL Phase Noise Narrowband Mode

When measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with T_c= 25 °C, V_DDS= 3.0 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

±10 kHz offset

dBc/Hz

–95

±100 kHz offset

±200 kHz offset

±400 kHz offset

±1000 kHz offset

±2000 kHz offset

±10000 kHz offset

–94

–95

Phase noise in the 868- and 915-MHz bands

150 kHz PLL loop bandwith

–104

–119

–129

–140

7.14 Bluetooth Low Energy - Receive (RX)

Measured on the CC1352-P7EM-XD7793-XD24-PA24 reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with

DC/DC enabled and high power PA connected to V_DDSunless otherwise noted.

All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is

measured at a dedicated antenna connection. All measurements are performed conducted.

PARAMETER

125 kbps (LE Coded)

Receiver sensitivity

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Differential mode. BER = 10^–3

dBm

–104

Receiver saturation

Differential mode. BER = 10^–3

>5

Difference between the incoming carrier frequency and

the internally generated carrier frequency

Frequency error tolerance

Data rate error tolerance

Co-channel rejection⁽¹⁾

Selectivity, ±1 MHz⁽¹⁾

Selectivity, ±2 MHz⁽¹⁾

Selectivity, ±3 MHz⁽¹⁾

Selectivity, ±4 MHz⁽¹⁾

Selectivity, ±6 MHz⁽¹⁾

Selectivity, ±7 MHz

kHz

ppm

dB

> (–300 / 300)

> (–320 / 240)

> (–125 / 100)

–1.5

Difference between incoming data rate and the internally

generated data rate (37-byte packets)

Difference between incoming data rate and the internally

generated data rate (255-byte packets)

Wanted signal at –79 dBm, modulated interferer in

channel, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at ±1

8 / 4.5⁽²⁾

dB

MHz, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at ±2

44 / 37⁽²⁾

46 / 44⁽²⁾

44 / 46⁽²⁾

48 / 44⁽²⁾

51 / 45⁽²⁾

37

dB

MHz, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at ±3

dB

MHz, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at ±4

dB

MHz, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at ≥±6

dB

MHz, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at ≥±7

dB

MHz, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at

Selectivity, Image frequency⁽¹⁾

dB

image frequency, BER = 10^–3

Note that Image frequency + 1 MHz is the Co- channel –

1 MHz. Wanted signal at –79 dBm, modulated interferer

at ±1 MHz from image frequency, BER = 10^–3

Selectivity, Image frequency ±1

MHz⁽¹⁾

4.5 / 44 ⁽²⁾

dB

RSSI Range

89

±4

dB

RSSI Accuracy (+/-)

500 kbps (LE Coded)

Receiver sensitivity

Receiver saturation

Differential mode. BER = 10^–3

dBm

–100

> 5

Difference between the incoming carrier frequency and

the internally generated carrier frequency

Frequency error tolerance

Data rate error tolerance

kHz

> (–300 / 300)

> (–450 / 450)

Difference between incoming data rate and the internally

generated data rate (37-byte packets)

ppm

18

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7.14 Bluetooth Low Energy - Receive (RX) (continued)

Measured on the CC1352-P7EM-XD7793-XD24-PA24 reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with

DC/DC enabled and high power PA connected to V_DDSunless otherwise noted.

All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is

measured at a dedicated antenna connection. All measurements are performed conducted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Difference between incoming data rate and the internally

generated data rate (255-byte packets)

Data rate error tolerance

ppm

> (–150 / 175)

Wanted signal at –72 dBm, modulated interferer in

Co-channel rejection⁽¹⁾

Selectivity, ±1 MHz⁽¹⁾

Selectivity, ±2 MHz⁽¹⁾

Selectivity, ±3 MHz⁽¹⁾

Selectivity, ±4 MHz⁽¹⁾

Selectivity, ±6 MHz⁽¹⁾

Selectivity, ±7 MHz

dB

–3.5

8 / 4⁽²⁾

channel, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at ±1

MHz, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at ±2

43 / 35⁽²⁾

46 / 46⁽²⁾

45 / 47⁽²⁾

46 / 45⁽²⁾

49 / 45⁽²⁾

35

MHz, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at ±3

MHz, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at ±4

MHz, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at ≥±6

MHz, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at ≥±7

MHz, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at

Selectivity, Image frequency⁽¹⁾

image frequency, BER = 10^–3

Note that Image frequency + 1 MHz is the Co- channel –

1 MHz. Wanted signal at –72 dBm, modulated interferer

at ±1 MHz from image frequency, BER = 10^–3

Selectivity, Image frequency ±1

MHz⁽¹⁾

4 / 46⁽²⁾

dB

RSSI Range

90

±4

dB

RSSI Accuracy (+/-)

1 Mbps (LE 1M)

Receiver sensitivity

Receiver saturation

Differential mode. BER = 10^–3

dBm

–97

> 5

Difference between the incoming carrier frequency and

the internally generated carrier frequency

Frequency error tolerance

Data rate error tolerance

Co-channel rejection⁽¹⁾

Selectivity, ±1 MHz⁽¹⁾

kHz

ppm

dB

> (–350 / 350)

> (–650 / 750)

–6

Difference between incoming data rate and the internally

generated data rate (37-byte packets)

Wanted signal at –67 dBm, modulated interferer in

channel, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ±1

7 / 4⁽²⁾

dB

MHz, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ±2

Selectivity, ±2 MHz⁽¹⁾

39 / 33⁽²⁾

36 / 40⁽²⁾

36 / 45⁽²⁾

40

dB

MHz,BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ±3

Selectivity, ±3 MHz⁽¹⁾

dB

MHz, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ±4

Selectivity, ±4 MHz⁽¹⁾

dB

MHz, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ≥±5

Selectivity, ±5 MHz or more⁽¹⁾

Selectivity, image frequency⁽¹⁾

dB

MHz, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at

33

dB

image frequency, BER = 10^–3

Note that Image frequency + 1 MHz is the Co- channel –

1 MHz. Wanted signal at –67 dBm, modulated interferer

at ±1 MHz from image frequency, BER = 10^–3

Selectivity, image frequency

±1 MHz⁽¹⁾

4 / 41⁽²⁾

dB

Out-of-band blocking⁽³⁾

Out-of-band blocking

30 MHz to 2000 MHz

2003 MHz to 2399 MHz

2484 MHz to 2997 MHz

3000 MHz to 12.75 GHz

dBm

–10

–18

–12

–2

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7.14 Bluetooth Low Energy - Receive (RX) (continued)

Measured on the CC1352-P7EM-XD7793-XD24-PA24 reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with

DC/DC enabled and high power PA connected to V_DDSunless otherwise noted.

All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is

measured at a dedicated antenna connection. All measurements are performed conducted.

PARAMETER

Intermodulation

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Wanted signal at 2402 MHz, –64 dBm. Two interferers

at 2405 and 2408 MHz respectively, at the given power

level

dBm

–42

Spurious emissions,

30 to 1000 MHz

dBm

Measurement in a 50-Ωsingle-ended load.

< –59

< –47

Spurious emissions,

1 to 12.75 GHz

RSSI dynamic range

RSSI accuracy

70

±4

dB

2 Mbps (LE 2M)

Differential mode. Measured at SMA connector, BER =

10^–3

Receiver sensitivity

dBm

kHz

ppm

dB

–91

> 5

Differential mode. Measured at SMA connector, BER =

10^–3

Receiver saturation

Difference between the incoming carrier frequency and

the internally generated carrier frequency

Frequency error tolerance

Data rate error tolerance

Co-channel rejection⁽¹⁾

> (–500 / 500)

> (–700 / 750)

–7

Difference between incoming data rate and the internally

generated data rate (37-byte packets)

Wanted signal at –67 dBm, modulated interferer in

channel,BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ±2

MHz, Image frequency is at –2 MHz, BER = 10^–3

Selectivity, ±2 MHz⁽¹⁾

8 / 4⁽²⁾

36 / 34⁽²⁾

37 / 36⁽²⁾

4

dB

Wanted signal at –67 dBm, modulated interferer at ±4

Selectivity, ±4 MHz⁽¹⁾

MHz, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ±6

Selectivity, ±6 MHz⁽¹⁾

MHz, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at

Selectivity, image frequency⁽¹⁾

image frequency, BER = 10^–3

Note that Image frequency + 2 MHz is the Co-channel.

Wanted signal at –67 dBm, modulated interferer at ±2

MHz from image frequency, BER = 10^–3

Selectivity, image frequency

±2 MHz⁽¹⁾

–7 / 36⁽²⁾

dB

Out-of-band blocking⁽³⁾

Out-of-band blocking

30 MHz to 2000 MHz

2003 MHz to 2399 MHz

2484 MHz to 2997 MHz

3000 MHz to 12.75 GHz

dBm

–16

–21

–15

–12

Wanted signal at 2402 MHz, –64 dBm. Two interferers

at 2408 and 2414 MHz respectively, at the given power

level

Intermodulation

dBm

–38

RSSI Range

60

±4

dB

RSSI Accuracy (+/-)

(1) Numbers given as I/C dB

(2) X / Y, where X is +N MHz and Y is –N MHz

(3) Excluding one exception at F_wanted/ 2, per Bluetooth Specification

20

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7.15 Bluetooth Low Energy - Transmit (TX)

Measured on the CC1352-P7EM-XD7793-XD24-PA24 reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with

DC/DC enabled and high power PA connected to V_DDSunless otherwise noted.

All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is

measured at a dedicated antenna connection. All measurements are performed conducted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

General Parameters

Max output power,

high power PA

20

6

dBm

dB

Differential mode, delivered to a single-ended 50 Ωload through a balun

Output power

programmable range

high power PA

Max output power,

high power PA, 10

dBm configuration⁽³⁾

10.5

5

dBm

dB

Differential mode, delivered to a single-ended 50 Ωload through a balun

Output power

programmable range

high power PA, 10

dBm configuration⁽³⁾

Max output power, 2.4

GHz PA

5

dBm

dB

Differential mode, delivered to a single-ended 50 Ωload through a balun

Output power

programmable range,

2.4 GHz PA

26

Spurious emissions and harmonics

f < 1 GHz, outside restricted bands

< -36

< -55

-37

dBm

Spurious emissions,

f < 1 GHz, restricted bands FCC

f > 1 GHz, including harmonics

Second harmonic

high-power PA⁽¹⁾

+20 dBm setting

-35

Harmonics,

high-power PA⁽²⁾

Third harmonic

-42

f < 1 GHz, outside restricted bands

f < 1 GHz, restricted bands ETSI

f < 1 GHz, restricted bands FCC,

f > 1 GHz, including harmonics

Second harmonic

< -36

< -54

< -55

-41

Spurious emissions,

high-power PA, 10

dBm configuration⁽¹⁾

(3)

+10 dBm setting⁽³⁾

Harmonics,

< -42

high-power PA, 10

dBm configuration⁽³⁾

Third harmonic

< -42

dBm

f < 1 GHz, outside restricted bands

f < 1 GHz, restricted bands ETSI

f < 1 GHz, restricted bands FCC

f > 1 GHz, including harmonics

Second harmonic

dBm

< –36

< –54

< –55

< –42

Spurious emissions,

2.4 GHz PA

+5 dBm setting

Harmonics,

2.4 GHz PA

Third harmonic

(1) To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting may be

required when operating at the upper Bluetooth Low Energy channel(s).

(2) To ensure margins for passing FCC requirements for harmonic emission, a reduction of maximum output-power may be required.

(3) Measured on the CC1352-P7EM-XD7793-XD24-PA24_10dbm reference design.

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7.16 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX

Measured on the CC1352-P7EM-XD7793-XD24-PA24 reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with

DC/DC enabled and high power PA connected to V_DDSunless otherwise noted.

All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is

measured at a dedicated antenna connection. All measurements are performed conducted.

PARAMETER

General Parameters

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Receiver sensitivity

Receiver saturation

PER = 1%

dBm

–99

> 5

Wanted signal at –82 dBm, modulated interferer at ±5 MHz,

PER = 1%

Adjacent channel rejection

Alternate channel rejection

36

57

dB

Wanted signal at –82 dBm, modulated interferer at ±10

MHz, PER = 1%

Wanted signal at –82 dBm, undesired signal is IEEE

802.15.4 modulated channel, stepped through all channels

2405 to 2480 MHz, PER = 1%

Channel rejection, ±15 MHz or more

59

dB

Blocking and desensitization,

5 MHz from upper band edge

Wanted signal at –97 dBm (3 dB above the sensitivity

level), CW jammer, PER = 1%

57

62

65

59

63

65

dB

Blocking and desensitization,

10 MHz from upper band edge

Wanted signal at –97 dBm (3 dB above the sensitivity

level), CW jammer, PER = 1%

Blocking and desensitization,

20 MHz from upper band edge

Wanted signal at –97 dBm (3 dB above the sensitivity

level), CW jammer, PER = 1%

dB

Blocking and desensitization,

50 MHz from upper band edge

Wanted signal at –97 dBm (3 dB above the sensitivity

level), CW jammer, PER = 1%

dB

Blocking and desensitization,

–5 MHz from lower band edge

Wanted signal at –97 dBm (3 dB above the sensitivity

level), CW jammer, PER = 1%

dB

Blocking and desensitization,

–10 MHz from lower band edge

Wanted signal at –97 dBm (3 dB above the sensitivity

level), CW jammer, PER = 1%

dB

Blocking and desensitization,

–20 MHz from lower band edge

Wanted signal at –97 dBm (3 dB above the sensitivity

level), CW jammer, PER = 1%

dB

Blocking and desensitization,

–50 MHz from lower band edge

Wanted signal at –97 dBm (3 dB above the sensitivity

level), CW jammer, PER = 1%

dB

Spurious emissions, 30 MHz to 1000

MHz

dBm

ppm

Measurement in a 50-Ω single-ended load

–66

–53

Spurious emissions, 1 GHz to 12.75

GHz

Difference between the incoming carrier frequency and the

internally generated carrier frequency

Frequency error tolerance

Symbol rate error tolerance

> 350

> 1000

Difference between incoming symbol rate and the internally

generated symbol rate

RSSI dynamic range

RSSI accuracy

95

±4

dB

22

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7.17 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX

Measured on the CC1352-P7EM-XD7793-XD24-PA24 reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with

DC/DC enabled and high power PA connected to V_DDSunless otherwise noted.

All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is

measured at a dedicated antenna connection. All measurements are performed conducted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

General Parameters

Max output power, high

power PA

20

6

dBm

dB

Differential mode, delivered to a single-ended 50-Ωload through a balun

Output power

programmable range,

high power PA

Max output power, high

power PA, 10 dBm

configuration⁽⁴⁾

10.5

5

dBm

dB

Differential mode, delivered to a single-ended 50-Ωload through a balun

Output power

programmable range,

high power PA, 10 dBm

configuration⁽⁴⁾

Max output power, 2.4

GHz PA

5

dBm

dB

Differential mode, delivered to a single-ended 50-Ωload through a balun

Output power

programmable range,

2.4 GHz PA

26

Spurious emissions and harmonics

f < 1 GHz, outside restricted

< -39

dBm

bands

Spurious emissions,

high-power PA⁽²⁾

f < 1 GHz, restricted bands FCC

f > 1 GHz, including harmonics

Second harmonic

< -49

-40

dBm

+20 dBm setting

-35

Harmonics,

high-power PA⁽³⁾

Third harmonic

-42

f < 1 GHz, outside restricted

bands

< -36

dBm

Spurious emissions,

high-power PA, 10 dBm

configuration^{(2) (4)}

f < 1 GHz, restricted bands ETSI

f < 1 GHz, restricted bands FCC

f > 1 GHz, including harmonics

Second harmonic

< -47

< -55

-42

dBm

+10 dBm setting⁽⁴⁾

Harmonics,

< -42

high-power PA, 10 dBm

configuration⁽⁴⁾

Third harmonic

< -42

< -36

dBm

f < 1 GHz, outside restricted

bands

Spurious emissions,

2.4 GHz PA ⁽¹⁾

f < 1 GHz, restricted bands ETSI

f < 1 GHz, restricted bands FCC

f > 1 GHz, including harmonics

Second harmonic

< -47

< -55

dBm

+5 dBm setting

< –42

< -42

Harmonics,

2.4 GHz PA

Third harmonic

< -42

IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps)

Error vector magnitude,

+20 dBm setting

2

%

high power PA

Error vector magnitude,

high power PA, 10 dBm

+10 dBm setting

+5 dBm setting

configuration⁽⁴⁾

Error vector magnitude,

2.4-GHz PA

(1) To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than

100% duty cycle may be used when operating at 2480 MHz.

(2) To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than

100% duty cycle may be used when operating at the upper 802.15.4 channel(s).

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(3) To ensure margins for passing FCC requirements for harmonic emission, duty cycling may be required.

(4) Measured on the CC1352-P7EM-XD7793-XD24-PA24_10dbm reference design.

7.18 Timing and Switching Characteristics

7.18.1 Reset Timing

PARAMETER

MIN

TYP

MAX

UNIT

RESET_N low duration

1

µs

7.18.2 Wakeup Timing

Measured over operating free-air temperature with V_DDS= 3.0 V (unless otherwise noted). The times listed here do not

include software overhead.

PARAMETER

TEST CONDITIONS

MIN

TYP

850 - 4000

165

MAX

UNIT

MCU, Reset to Active⁽¹⁾

µs

MCU, Shutdown to Active⁽¹⁾

MCU, Standby to Active

MCU, Active to Standby

MCU, Idle to Active

39

15

(1) The wakeup time is dependent on remaining charge on VDDR capacitor when starting the device, and thus how long the device has

been in Reset or Shutdown before starting up again. The wake up time increases with a higher capacitor value.

24

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7.18.3 Clock Specifications

7.18.3.1 48 MHz Crystal Oscillator (XOSC_HF)

Measured on a Texas Instruments reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.⁽¹⁾

PARAMETER

MIN

TYP

MAX

UNIT

Crystal frequency

48

MHz

Equivalent series resistance

6 pF < C_L≤9 pF

ESR

20

60

80

Ω

Equivalent series resistance

5 pF < C_L≤ 6 pF

Ω

Motional inductance, relates to the load capacitance that is used for the crystal (C_L

in Farads)⁽⁵⁾

2

L_M

C_L

< 3 × 10^–25/ C_L

H

Crystal load capacitance⁽⁴⁾

Start-up time⁽²⁾

5

7⁽³⁾

9

pF

µs

200

(1) Probing or otherwise stopping the crystal while the DC/DC converter is enabled may cause permanent damage to the device.

(2) Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.

(3) On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed

through software in the Customer Configuration section (CCFG).

(4) Adjustable load capacitance is integrated into the device. External load capacitors are required for systems targeting compliance with

certain regulations. See the device errata for further details.

(5) The crystal manufacturer's specification must satisfy this requirement for proper operation.

7.18.3.2 48 MHz RC Oscillator (RCOSC_HF)

Measured on a Texas Instruments reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

MIN

TYP

MAX

UNIT

MHz

%

Frequency

48

Uncalibrated frequency accuracy

Calibrated frequency accuracy⁽¹⁾

Start-up time

±1

±0.25

5

%

µs

(1) Accuracy relative to the calibration source (XOSC_HF)

7.18.3.3 2 MHz RC Oscillator (RCOSC_MF)

Measured on a Texas Instruments reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

MIN

TYP

MAX

UNIT

MHz

µs

Calibrated frequency

Start-up time

2

5

7.18.3.4 32.768 kHz Crystal Oscillator (XOSC_LF)

Measured on a Texas Instruments reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

MIN

TYP

32.768

30

MAX

UNIT

kHz

kΩ

Crystal frequency

ESR

C_L

Equivalent series resistance

Crystal load capacitance

100

12

6

7⁽¹⁾

pF

(1) Default load capacitance using TI reference designs including parasitic capacitance. Crystals with different load capacitance may be

used.

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7.18.3.5 32 kHz RC Oscillator (RCOSC_LF)

Measured on a Texas Instruments reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

MIN

TYP

MAX

UNIT

Frequency

32.8

kHz

Calibrated

RTC

Calibrated periodically against XOSC_HF⁽²⁾

±600⁽³⁾

50

ppm

variation⁽¹⁾

Temperature coefficient

ppm/°C

(1) When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time

Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This

functionality is available through the TI-provided Power driver.

(2) TI driver software calibrates the RTC every time XOSC_HF is enabled.

(3) Some device's variation can exceed 1000 ppm. Further calibration will not improve variation.

7.18.4 Synchronous Serial Interface (SSI) Characteristics

7.18.4.1 Synchronous Serial Interface (SSI) Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

SSIClk cycle time

MIN

TYP

MAX

UNIT

NO.

S1

t_{clk_per}

t_{clk_high}

t_{clk_low}

12

65024

System Clocks ⁽²⁾

t_{clk_per}

S2⁽¹⁾

S3⁽¹⁾

SSIClk high time

SSIClk low time

0.5

t_{clk_per}

(1) Refer to SSI timing diagrams 图7-1, 图7-2 and 图7-3.

(2) When using the TI-provided Power driver, the SSI system clock is always 48 MHz.

S1

S2

SSIClk

S3

SSIFss

SSITx

MSB

LSB

SSIRx

4 to 16 bits

图7-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement

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S2

S1

SSIClk

SSIFss

SSITx

SSIRx

S3

MSB

LSB

8-bit control

0

MSB

LSB

4 to 16 bits output data

图7-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer

S1

S2

SSIClk

(SPO = 0)

S3

SSIClk

(SPO = 1)

SSITx

(Master)

MSB

LSB

SSIRx

(Slave)

MSB

LSB

SSIFss

图7-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1

7.18.5 UART

7.18.5.1 UART Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

UART rate

2.89

MBaud

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7.19 Peripheral Characteristics

7.19.1 ADC

7.19.1.1 Analog-to-Digital Converter (ADC) Characteristics

T_c= 25 °C, V_DDS= 3.0 V and voltage scaling enabled, unless otherwise noted.⁽¹⁾

Performance numbers require use of offset and gain adjustments in software by TI-provided ADC drivers.

PARAMETER

Input voltage range

Resolution

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

0

VDDS

12

Bits

ksps

LSB

Sample Rate

200

Offset

Internal 4.3 V equivalent reference⁽²⁾

±2

±7

Gain error

Internal 4.3 V equivalent reference⁽²⁾

DNL⁽⁴⁾

INL

Differential nonlinearity

Integral nonlinearity

>–1

±4

Internal 4.3 V equivalent reference⁽²⁾, 200 kSamples/s,

9.6 kHz input tone

9.8

Internal 4.3 V equivalent reference⁽²⁾, 200 kSamples/s,

9.6 kHz input tone, DC/DC enabled

9.8

10.1

11.1

VDDS as reference, 200 kSamples/s, 9.6 kHz input tone

ENOB

Effective number of bits

Bits

Internal reference, voltage scaling disabled,

32 samples average, 200 kSamples/s, 300 Hz input tone

Internal reference, voltage scaling disabled,

11.3

11.6

14-bit mode, 200 kSamples/s, 600 Hz input tone ⁽⁵⁾

Internal reference, voltage scaling disabled,

15-bit mode, 200 kSamples/s, 150 Hz input tone ⁽⁵⁾

Internal 4.3 V equivalent reference⁽²⁾, 200 kSamples/s,

9.6 kHz input tone

–65

–70

–72

THD

Total harmonic distortion

VDDS as reference, 200 kSamples/s, 9.6 kHz input tone

dB

Internal reference, voltage scaling disabled,

32 samples average, 200 kSamples/s, 300 Hz input tone

Internal 4.3 V equivalent reference⁽²⁾, 200 kSamples/s,

9.6 kHz input tone

60

63

68

Signal-to-noise

and

distortion ratio

SINAD,

SNDR

VDDS as reference, 200 kSamples/s, 9.6 kHz input tone

Internal reference, voltage scaling disabled,

32 samples average, 200 kSamples/s, 300 Hz input tone

Internal 4.3 V equivalent reference⁽²⁾, 200 kSamples/s,

9.6 kHz input tone

70

73

75

SFDR

Spurious-free dynamic range VDDS as reference, 200 kSamples/s, 9.6 kHz input tone

Internal reference, voltage scaling disabled,

32 samples average, 200 kSamples/s, 300 Hz input tone

Conversion time

Serial conversion, time-to-output, 24 MHz clock

Internal 4.3 V equivalent reference⁽²⁾

VDDS as reference

50

0.40

0.57

Clock Cycles

Current consumption

mA

Equivalent fixed internal reference (input voltage scaling

enabled). For best accuracy, the ADC conversion should be

initiated through the TI-RTOS API in order to include the gain/

offset compensation factors stored in FCFG1

Reference voltage

4.3^{(2) (3)}

V

Fixed internal reference (input voltage scaling disabled). For

best accuracy, the ADC conversion should be initiated through

the TI-RTOS API in order to include the gain/offset

compensation factors stored in FCFG1. This value is derived

from the scaled value (4.3 V) as follows:

Reference voltage

1.48

V

V_ref= 4.3 V × 1408 / 4095

Reference voltage

VDDS as reference, input voltage scaling enabled

VDDS as reference, input voltage scaling disabled

VDDS

V

VDDS /

2.82⁽³⁾

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7.19.1.1 Analog-to-Digital Converter (ADC) Characteristics (continued)

T_c= 25 °C, V_DDS= 3.0 V and voltage scaling enabled, unless otherwise noted.⁽¹⁾

Performance numbers require use of offset and gain adjustments in software by TI-provided ADC drivers.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

200 kSamples/s, voltage scaling enabled. Capacitive input,

Input impedance depends on sampling frequency and sampling

time

Input impedance

>1

MΩ

(1) Using IEEE Std 1241-2010 for terminology and test methods

(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V

(3) Applied voltage must be within Absolute Maximum Ratings at all times

(4) No missing codes

(5) ADC_output = Σ(4ⁿsamples ) >> n, n = desired extra bits

7.19.2 DAC

7.19.2.1 Digital-to-Analog Converter (DAC) Characteristics

T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

General Parameters

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

8

Bits

Any load, any V_REF, pre-charge OFF, DAC charge-pump ON

1.8

2.0

3.8

External Load⁽⁴⁾, any V_REF, pre-charge OFF, DAC charge-pump

OFF

V_DDS

Supply voltage

V

Any load, V_REF= DCOUPL, pre-charge ON

Buffer ON (recommended for external load)

Buffer OFF (internal load)

2.6

16

3.8

250

F_DAC

Clock frequency

kHz

1000

V_REF= VDDS, buffer OFF, internal load

V_REF= VDDS, buffer ON, external capacitive load = 20 pF⁽³⁾

13

13.8

20

Voltage output settling time

1 / F_DAC

External capacitive load

External resistive load

Short circuit current

200

400

pF

MΩ

µA

10

VDDS = 3.8 V, DAC charge-pump OFF

VDDS = 3.0 V, DAC charge-pump ON

VDDS = 3.0 V, DAC charge-pump OFF

VDDS = 2.0 V, DAC charge-pump ON

VDDS = 2.0 V, DAC charge-pump OFF

VDDS = 1.8 V, DAC charge-pump ON

VDDS = 1.8 V, DAC charge-pump OFF

50.8

51.7

53.2

48.7

70.2

46.3

88.9

Max output impedance Vref =

VDDS, buffer ON, CLK 250

kHz

Z_MAX

kΩ

Internal Load - Continuous Time Comparator / Low Power Clocked Comparator

V_REF= VDDS,

load = Continuous Time Comparator or Low Power Clocked

Comparator

F_DAC= 250 kHz

Differential nonlinearity

±1

DNL

LSB⁽¹⁾

V_REF= VDDS,

load = Continuous Time Comparator or Low Power Clocked

Comparator

±1.2

F_DAC= 16 kHz

V_REF= VDDS = 3.8 V

±0.64

±0.81

±1.27

±3.43

±2.88

±2.37

V_REF= VDDS= 3.0 V

Offset error⁽²⁾

Load = Continuous Time

Comparator

V_REF= VDDS = 1.8 V

LSB⁽¹⁾

V_REF= DCOUPL, pre-charge ON

V_REF= DCOUPL, pre-charge OFF

V_REF= ADCREF

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7.19.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued)

T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

±0.78

±0.77

±3.46

±3.44

±4.70

±4.11

±1.53

±1.71

±2.10

±6.00

±3.85

±5.84

±2.92

±3.06

±3.91

±7.84

±4.06

±6.94

0.03

MAX

UNIT

V_REF= VDDS= 3.8 V

V_REF= VDDS = 3.0 V

V_REF= VDDS= 1.8 V

Offset error⁽²⁾

Load = Low Power Clocked

Comparator

LSB⁽¹⁾

V_REF= DCOUPL, pre-charge ON

V_REF= DCOUPL, pre-charge OFF

V_REF= ADCREF

V_REF= VDDS = 3.8 V

V_REF= VDDS = 3.0 V

Max code output voltage

variation⁽²⁾

Load = Continuous Time

Comparator

V_REF= VDDS= 1.8 V

LSB⁽¹⁾

V_REF= DCOUPL, pre-charge ON

V_REF= DCOUPL, pre-charge OFF

V_REF= ADCREF

V_REF= VDDS= 3.8 V

V_REF=VDDS= 3.0 V

Max code output voltage

variation⁽²⁾

Load = Low Power Clocked

Comparator

V_REF= VDDS= 1.8 V

LSB⁽¹⁾

V_REF= DCOUPL, pre-charge ON

V_REF= DCOUPL, pre-charge OFF

V_REF= ADCREF

V_REF= VDDS = 3.8 V, code 1

V_REF= VDDS = 3.8 V, code 255

V_REF= VDDS= 3.0 V, code 1

V_REF= VDDS= 3.0 V, code 255

V_REF= VDDS= 1.8 V, code 1

V_REF= VDDS = 1.8 V, code 255

V_REF= DCOUPL, pre-charge OFF, code 1

V_REF= DCOUPL, pre-charge OFF, code 255

V_REF= DCOUPL, pre-charge ON, code 1

V_REF= DCOUPL, pre-charge ON, code 255

V_REF= ADCREF, code 1

3.62

0.02

2.86

0.01

Output voltage range⁽²⁾

Load = Continuous Time

Comparator

1.71

V

0.01

1.21

1.27

2.46

0.01

V_REF= ADCREF, code 255

1.41

V_REF= VDDS = 3.8 V, code 1

V_REF= VDDS= 3.8 V, code 255

V_REF= VDDS= 3.0 V, code 1

V_REF= VDDS= 3.0 V, code 255

V_REF= VDDS = 1.8 V, code 1

V_REF= VDDS = 1.8 V, code 255

V_REF= DCOUPL, pre-charge OFF, code 1

V_REF= DCOUPL, pre-charge OFF, code 255

V_REF= DCOUPL, pre-charge ON, code 1

V_REF= DCOUPL, pre-charge ON, code 255

V_REF= ADCREF, code 1

0.03

3.61

0.02

2.85

0.01

Output voltage range⁽²⁾

Load = Low Power Clocked

Comparator

1.71

V

0.01

1.21

1.27

2.46

0.01

V_REF= ADCREF, code 255

1.41

External Load

V_REF= VDDS, F_DAC= 250 kHz

V_REF= DCOUPL, F_DAC= 250 kHz

V_REF= ADCREF, F_DAC= 250 kHz

V_REF= VDDS, F_DAC= 250 kHz

±1

±2

±1

INL

Integral nonlinearity

LSB⁽¹⁾

DNL

Differential nonlinearity

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7.19.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued)

T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

±0.40

±0.50

±0.75

±1.55

±1.30

±1.10

±1.00

±3.45

±2.10

±1.90

0.03

MAX

UNIT

V_REF= VDDS= 3.8 V

V_REF= VDDS= 3.0 V

V_REF= VDDS = 1.8 V

Offset error

LSB⁽¹⁾

V_REF= DCOUPL, pre-charge ON

V_REF= DCOUPL, pre-charge OFF

V_REF= ADCREF

V_REF= VDDS= 3.8 V

V_REF= VDDS= 3.0 V

V_REF= VDDS= 1.8 V

Max code output voltage

variation

LSB⁽¹⁾

V_REF= DCOUPL, pre-charge ON

V_REF= DCOUPL, pre-charge OFF

V_REF= ADCREF

V_REF= VDDS = 3.8 V, code 1

V_REF= VDDS = 3.8 V, code 255

V_REF= VDDS = 3.0 V, code 1

V_REF= VDDS= 3.0 V, code 255

V_REF= VDDS= 1.8 V, code 1

V_REF= VDDS = 1.8 V, code 255

V_REF= DCOUPL, pre-charge OFF, code 1

V_REF= DCOUPL, pre-charge OFF, code 255

V_REF= DCOUPL, pre-charge ON, code 1

V_REF= DCOUPL, pre-charge ON, code 255

V_REF= ADCREF, code 1

3.61

0.02

2.85

0.02

Output voltage range

Load = Low Power Clocked

Comparator

1.71

V

0.02

1.20

1.27

2.46

0.02

V_REF= ADCREF, code 255

1.42

(1) 1 LSB (V_REF3.8 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 14.10 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV

(2) Includes comparator offset

(3) A load > 20 pF will increases the settling time

(4) Keysight 34401A Multimeter

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7.19.3 Temperature and Battery Monitor

7.19.3.1 Temperature Sensor

Measured on a Texas Instruments reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

°C

Resolution

Accuracy

2

-40 °C to 0 °C

0 °C to 105 °C

±4.0

±2.5

3.6

°C

Supply voltage coefficient⁽¹⁾

°C/V

(1) The temperature sensor is automatically compensated for VDDS variation when using the TI-provided temperature driver.

7.19.3.2 Battery Monitor

Measured on a Texas Instruments reference design with T_c= 25 °C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

mV

V

Resolution

Range

25

1.8

3.8

Integral nonlinearity (max)

Accuracy

23

22.5

-32

-1

mV

%

VDDS = 3.0 V

Offset error

Gain error

7.19.4 Comparators

7.19.4.1 Low-Power Clocked Comparator

T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Input voltage range

Clock frequency

0

V_DDS

V

SCLK_LF

Using internal DAC with VDDS as reference voltage,

DAC code = 0 - 255

Internal reference voltage⁽¹⁾

Offset

0.024 - 2.865

V

Measured at V_DDS/ 2, includes error from internal DAC

±5

1

mV

Clock

Cycle

Decision time

Step from –50 mV to 50 mV

(1) The comparator can use an internal 8 bits DAC as its reference. The DAC output voltage range depends on the reference voltage

selected. See #none#

7.19.4.2 Continuous Time Comparator

T_c= 25°C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

Input voltage range⁽¹⁾

Offset

0

V_DDS

Measured at V_DDS/ 2

±5

0.70

8.0

mV

µs

Decision time

Step from –10 mV to 10 mV

Current consumption

Internal reference

µA

(1) The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using

the DAC

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7.19.5 Current Source

7.19.5.1 Programmable Current Source

T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

0.25 - 20

0.25

MAX UNIT

Current source programmable output range (logarithmic

range)

µA

Resolution

7.19.6 GPIO

7.19.6.1 GPIO DC Characteristics

Measurements CBSed to PG2.1:

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

T_A= 25 °C, V_DDS= 1.8 V

GPIO VOH at 8 mA load

IOCURR = 2, high-drive GPIOs only

IOCURR = 1

1.56

0.24

1.59

0.21

73

V

GPIO VOL at 8 mA load

GPIO VOH at 4 mA load

V

GPIO VOL at 4 mA load

IOCURR = 1

V

GPIO pullup current

Input mode, pullup enabled, Vpad = 0 V

Input mode, pulldown enabled, Vpad = VDDS

IH = 1, transition voltage for input read as 0 →1

IH = 1, transition voltage for input read as 1 →0

µA

V

GPIO pulldown current

19

GPIO low-to-high input transition, with hysteresis

GPIO high-to-low input transition, with hysteresis

1.08

0.73

V

IH = 1, difference between 0 →1

and 1 →0 points

GPIO input hysteresis

0.35

V

T_A= 25 °C, V_DDS= 3.0 V

GPIO VOH at 8 mA load

IOCURR = 2, high-drive GPIOs only

IOCURR = 1

2.59

0.42

2.63

0.40

V

GPIO VOL at 8 mA load

GPIO VOH at 4 mA load

GPIO VOL at 4 mA load

IOCURR = 1

T_A= 25 °C, V_DDS= 3.8 V

GPIO pullup current

Input mode, pullup enabled, Vpad = 0 V

282

110

µA

V

GPIO pulldown current

Input mode, pulldown enabled, Vpad = VDDS

IH = 1, transition voltage for input read as 0 →1

IH = 1, transition voltage for input read as 1 →0

GPIO low-to-high input transition, with hysteresis

GPIO high-to-low input transition, with hysteresis

1.97

1.55

V

IH = 1, difference between 0 →1

and 1 →0 points

GPIO input hysteresis

T_A= 25 °C

0.42

V

Lowest GPIO input voltage reliably interpreted as a

High

VIH

0.8*V_DDS

V

Highest GPIO input voltage reliably interpreted as a

Low

VIL

0.2*V_DDS

V

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7.20 Typical Characteristics

All measurements in this section are done with T_c= 25 °C and V_DDS= 3.0 V, unless otherwise noted. See 节 7.3

for device limits. Values exceeding these limits are for reference only.

7.20.1 MCU Current

Active Current vs. VDDS

Standby Current vs. Temperature

144 kB RAM retention, no Cache Retention, RTC On

SCLK_LF = 32 kHz XOSC

Running CoreMark, SCLK_HF = 48 MHz RCOSC

6

5.5

5

8

7

6

5

4

3

2

1

0

4.5

4

3.5

3

2.5

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

Temperature [^oC]

Voltage [V]

图7-4. Active Mode (MCU) Current vs. Supply Voltage (VDDS)

图7-5. Standby Mode (MCU) Current vs. Temperature

7.20.2 RX Current

RX Current vs. Temperature

50 kbps, 868.3 MHz, VDSS = 3.6 V

Bluetooth Low Energy 1 Mbps, 2.44 GHz

7

6.8

6.6

6.4

6.2

6

7.5

7.4

7.3

7.2

7.1

7

6.9

6.8

6.7

6.6

6.5

6.4

6.3

6.2

6.1

6

5.8

5.6

5.4

5.2

5

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

Temperature [^oC]

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

Temperature [C]

图7-7. RX Current vs. Temperature (Bluetooth Low Energy 1

图7-6. RX Current vs. Temperature (50 kbps, 868.3 MHz, VDDS

Mbps, 2.44 GHz)

= 3.6 V)

RX Current vs. VDSS

RX Current vs. VDDS

50 kbps, 868.3 MHz

Bluetooth Low Energy 1 Mbps, 2.44 GHz

11

10.5

10

9.5

9

11.5

11

10.5

10

9.5

9

8.5

8

8.5

8

7.5

7

7.5

7

6.5

6

6.5

6

5.5

5

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Voltage [V]

图7-8. RX Current vs. Supply Voltage (VDDS) (50 kbps, 868.3

图7-9. RX Current vs. Supply Voltage (VDDS) (Bluetooth Low

MHz)

Energy 1 Mbps, 2.44 GHz)

34

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ZHCSO54A –MAY 2021 –REVISED NOVEMBER 2021

7.20.3 TX Current

TX Current vs. Temperature

50 kbps, 868.3 MHz, +10 dBm, VDDS = 3.6 V

TX Current vs. Temperature

50 kbps, 915 MHz, +20 dBm PA, VDDS = 3.3 V

18

17.7

17.4

17.1

16.8

16.5

16.2

15.9

15.6

15.3

15

85

80

75

70

65

60

55

50

45

40

35

30

25

+20 dBm

+19 dBm

+18 dBm

+17 dBm

+16 dBm

+15 dBm

+14 dBm

14.7

14.4

14.1

13.8

13.5

13.2

12.9

12.6

12.3

12

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

Temperature [°C]

D015

D016

图7-10. TX Current vs. Temperature (50 kbps, 868.3 MHz, VDDS

图7-11. TX Current vs. Temperature (50 kbps, 915 MHz, VDDS =

= 3.6 V)

3.3 V)

TX Current vs. Temperature

Bluetooth Low Energy 1 Mbps, 2.44 GHz, 0 dBm

Bluetooth Low Energy 1 Mbps, 2.44 GHz, +20 dBm PA

8

7.8

7.6

7.4

7.2

7

150

+20 dBm

140

130

120

110

100

90

+19 dBm

+18 dBm

+17 dBm

+16 dBm

+15 dBm

+14 dBm

6.8

6.6

6.4

6.2

6

80

70

60

50

40

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

Temperature [^oC]

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

Temperature [°C]

图7-12. TX Current vs. Temperature (Bluetooth Low Energy 1

图7-13. TX Current vs. Temperature (Bluetooth Low Energy 1

Mbps, 2.44 GHz)

Mbps, 2.44 GHz, VDDS = 3.3 V)

TX Current vs. Temperature

TX Current vs. VDDS

50 kbps, 868.3 MHz, +10 dBm

Bluetooth Low Energy 1 Mbps, 2.44 GHz, + 10 dBm PA

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

+ 10 dBm

+ 9 dBm

+ 8 dBm

+ 7 dBm

+ 6 dBm

24

22

20

18

16

14

12

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

Temperature [C]

1.8 1.9

2

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9

3

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8

Voltage [V]

D022

图7-14. TX Current vs. Temperature (250 kbps, 2.44 GHz, +10

dBm PA)

图7-15. TX Current vs. Supply Voltage (VDDS) (50 kbps, 868.3

MHz)

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ZHCSO54A –MAY 2021 –REVISED NOVEMBER 2021

7.20.3 TX Current (continued)

TX Current vs. VDDS

50 kbps, 915 MHz, +20 dBm PA

Bluetooth Low Energy 1 Mbps, 2.44 GHz, 0 dBm

12

11.5

11

70

+20 dBm

+19 dBm

65

+18 dBm

+17 dBm

10.5

10

60

+16 dBm

+15 dBm

55

+14 dBm

9.5

9

50

45

40

35

30

25

8.5

8

7.5

7

6.5

6

5.5

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Voltage [V]

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Voltage [V]

图7-17. TX Current vs. Supply Voltage (VDDS) (Bluetooth Low

D023

Energy 1 Mbps, 2.44 GHz)

图7-16. TX Current vs. Supply Voltage (VDDS) (50 kbps, 915

MHz)

TX Current vs. VDDS

Bluetooth Low Energy 1 Mbps, 2.44 GHz, +20 dBm PA

Bluetooth Low Energy 1 Mbps 2.44GHz, + 10 dBm PA

130

45

+20 dBm

+19 dBm

+18 dBm

+17 dBm

+16 dBm

+15 dBm

+14 dBm

+ 10 dBm

+ 9 dBm

+ 8 dBm

+ 7 dBm

+ 6 dBm

125

120

115

110

105

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

1.8 1.9

2

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8

Voltage [V]

图7-19. TX Current vs. Supply Voltage (VDDS) (250 kbps, 2.44

图7-18. TX Current vs. Supply Voltage (VDDS) (Bluetooth Low

GHz, +10 dBm PA)

Energy 1 Mbps, 2.44 GHz, +20 dBm PA)

表7-1. Typical TX Current and Output Power

CC1352P7 at 868 MHz, VDDS = 3.6 V ⁽¹⁾(Measured on CC1352P-7EM-XD7793-XD24-PA9093)

txPower

0x013F¹

0xB224

0x895E

0x669A

0x3E92

0x3EDC

0x2CD8

0x26D4

0x20D1

0x1CCE

0x16CD

0x14CB

0x12CA

TX Power Setting (SmartRF Studio)

Typical Output Power [dBm]

Typical Current Consumption [mA]

14

12.5

12

11

10

9

13.6

11.9

11.5

10.6

9.7

24

17

16

15

14

13

12

11

10

9

8.9

8

8.3

7

7.4

6

6.3

5

4.8

4

4.2

3

2.8

8

2

1.9

8

1

Boost mode enabled. VDDR regulated to 1.95 V.

36

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ZHCSO54A –MAY 2021 –REVISED NOVEMBER 2021

7.20.3 TX Current (continued)

表7-1. Typical TX Current and Output Power (continued)

CC1352P7 at 868 MHz, VDDS = 3.6 V ⁽¹⁾(Measured on CC1352P-7EM-XD7793-XD24-PA9093)

txPower

0x12C9

0x10C8

0x0AC4

0x0AC2

0x06C1

0x04C0

TX Power Setting (SmartRF Studio)

Typical Output Power [dBm]

Typical Current Consumption [mA]

1

1.0

8

7

6

5

4

0

-0.1

-5

-6.8

-10

-15

-20

-13.3

-18.5

-22.0

(1) Internal regulated voltage powers the PA, therefore the output power is not affected by variation in VDDS voltage.

表7-2. Typical TX Current and Output Power

CC1352P7 at 915 MHz, VDDS = 3.3 V ⁽¹⁾(Measured on CC1352P-7EM-XD7793-XD24-PA9093)

txPower

0x1B8ED2

0x448CF

0x48022

0x2661C

0x5618

TX Power Setting (SmartRF Studio)

Typical Output Power [dBm]

Typical Current Consumption [mA]

20

19

18

17

16

15

14

20.4

19.3

17.8

16.8

15.9

14.9

13.7

65

55

45

41

37

33

30

0x4812

0x380D

(1) VDDS powers the PA, therefore the output power is affected by variation in VDDS voltage.

表7-3. Typical TX Current and Output Power

CC1352P7 at 2.4 GHz, VDDS = 3.3 V ⁽¹⁾(Measured on CC1352-7PEM-XD7793-XD24-PA24)

txPower

0x3F75F5

0x3F61E2

0x3047E0

0x1B4FE5

0x1B39DE

0x1B2FDA

0x1B27D6

TX Power Setting (SmartRF Studio)

Typical Output Power [dBm]

Typical Current Consumption [mA]

20

19

18

17

16

15

14

19.6

18.3

17.4

16.3

15.2

14.3

13.2

102

86

79

71

63

58

52

(1) VDDS powers the PA, therefore the output power is affected by variation in VDDS voltage.

表7-4. Typical TX Current and Output Power

CC1352P7 at 2.4 GHz, VDDS = 3.0 V ⁽¹⁾(Measured on CC1352-7PEM-XD7793-XD24-PA24_10dBm)

txPower

0x103F5F

0x10335A

0x143661

0x144F2A

0x144F26

0x144722

TX Power Setting (SmartRF Studio)

Typical Output Power [dBm]

Typical Current Consumption [mA]

10

9

10.7

9.6

8.5

7.6

6.6

5.4

21

19

17

16

15

8

7

6

5

(1) Internal regulated voltage powers the PA, therefore the output power is not affected by variation in VDDS voltage.

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ZHCSO54A –MAY 2021 –REVISED NOVEMBER 2021

7.20.3 TX Current (continued)

表7-5. Typical TX Current and Output Power

CC1352P7 at 2.4 GHz, VDDS = 3.0 V ⁽¹⁾(Measured on CC1352-7PEM-XD7793-XD24-PA24)

txPower

0x762E

0x8220

0x5617

0x3E66

0x3261

0x2C5D

0x1899

0x1695

0x1693

0x0CD4

0x0AD3

0x0AD0

0x06CD

0x04CA

0x04C8

TX Power Setting (SmartRF Studio)

Typical Output Power [dBm]

Typical Current Consumption [mA]

5

4

4.7

3.7

10

9

8

7

6

5

4

3

2.8

2

1.9

1

0.9

0

0.0

-3

-5

-6

-9

-10

-12

-15

-18

-20

-3.1

-4.9

-6.0

-9.1

-9.8

-11.9

-14.6

-17.8

-20.4

(1) Internal regulated voltage powers the PA, therefore the output power is not affected by variation in VDDS voltage.

38

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ZHCSO54A –MAY 2021 –REVISED NOVEMBER 2021

7.20.4 RX Performance

Sensitivity vs. Frequency

50 kbps

Sensitivity vs. Frequency

50 kbps

-105

-106

-107

-108

-109

-110

-111

-112

-113

-114

-115

-105

-106

-107

-108

-109

-110

-111

-112

-113

-114

-115

863

864

865

866

867

868

869

870

900

903

906

909

912

915

918

921

924

927

930

Frequency [MHz]

D026

D027

图7-20. Sensitivity vs. Frequency (50 kbps, 868 MHz)

图7-21. Sensitivity vs. Frequency (50 kbps, 915 MHz)

Sensitivity vs. Frequency

IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps)

Sensitivity vs. Frequency

Bluetooth Low Energy 1 Mbps, 2.44 GHz

-95

-96

-92

-93

-94

-95

-96

-97

-98

-99

-97

-98

-99

-100

-101

-102

-103

-104

-105

-100

-101

-102

2.4

2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48

2.4

2.408

2.416

2.424

2.432

2.44

2.448

2.456

2.464

2.472

2.48

Frequency [GHz]

D028

D029

图7-22. Sensitivity vs. Frequency (Bluetooth Low Energy 1

图7-23. Sensitivity vs. Frequency (250 kbps, 2.44 GHz)

Mbps, 2.44 GHz)

Sensitivity vs. Temperature

50 kbps, 868.3 MHz

Sensitivity vs. Temperature

Bluetooth Low Energy 1 Mbps, 2.44 GHz

-105

-106

-107

-108

-109

-110

-111

-112

-113

-114

-115

-92

-93

-94

-95

-96

-97

-98

-99

-100

-101

-102

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

Temperature [°C]

D030

Temperature [°C]

D031

图7-24. Sensitivity vs. Temperature (50 kbps, 868.3 MHz)

图7-25. Sensitivity vs. Temperature (Bluetooth Low Energy 1

Mbps, 2.44 GHz)

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ZHCSO54A –MAY 2021 –REVISED NOVEMBER 2021

7.20.4 RX Performance (continued)

Sensitivity vs. VDDS

50 kbps, 868.3 MHz

Sensitivity vs. Temperature

IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz

-105

-106

-107

-108

-109

-110

-111

-112

-113

-114

-115

-95

-96

-97

-98

-99

-100

-101

-102

-103

-104

-105

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Temperature [°C]

Voltage [V]

D032

D033

图7-26. Sensitivity vs. Temperature (250 kbps, 2.44 GHz)

图7-27. Sensitivity vs. Supply Voltage (VDDS) (50 kbps, 868.3

MHz)

Sensitivity vs. VDDS

Bluetooth Low Energy 1 Mbps, 2.44 Ghz

Sensitivity vs. VDDS

Bluetooth Low Energy 1 Mbps, 2.44 GHz, DCDC Off

-92

-93

-92

-93

-94

-95

-96

-97

-98

-99

-100

-101

-102

-100

-101

-102

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Voltage [V]

D034

D035

图7-28. Sensitivity vs. Supply Voltage (VDDS) (Bluetooth Low

图7-29. Sensitivity vs. Supply Voltage (VDDS) (Bluetooth Low

Energy 1 Mbps, 2.44 GHz)

Energy 1 Mbps, 2.44 GHz, DCDC Off)

Sensitivity vs. VDDS

IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz

Selectivity vs. Frequency Offset

50 kbps, 868.3 MHz

-95

-96

80

60

40

20

0

-97

-98

-99

-100

-101

-102

-103

-104

-105

-20

-10

-8

-6

-4

-2

0

2

4

6

8

10

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Frequency [MHz]

Voltage [V]

D038

D036

图7-31. Selectivity vs. Frequency Offset (50 kbps, 868.3 MHz)

图7-30. Sensitivity vs. Supply Voltage (VDDS) (250 kbps, 2.44

GHz)

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7.20.4 RX Performance (continued)

Packet error rate vs level and frequency offset for SLR 5 kbps.

100

90

80

70

60

50

40

30

20

10

0

-20

-40

-60

-80

-100

-120

-30

-20

-10

0

10

20

30

Offset frequency [ppm]

图7-33. PER vs. Level vs. Frequency (SimpleLink™ Long

图7-32. PER vs. Level vs. Frequency (SimpleLink™ Long

Range 5 kbps, 868 MHz)

图7-34. Narrowband, 9.6 kbps ±2.4 kHz deviation, 2-GFSK, 868 MHz, 17.1 kHz RX Bandwidth

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ZHCSO54A –MAY 2021 –REVISED NOVEMBER 2021

7.20.5 TX Performance

Output Power vs. Temperature

50 kbps, 915 MHz, +20 dBm PA, VDDS = 3.3 V

Output Power vs. Temperature

50 kbps, 868.3 MHz, +14 dBm

26

24

22

20

18

16

14

12

14

13.8

13.6

13.4

13.2

13

+20 dBm

+19 dBm

+18 dBm

+17 dBm

+16 dBm

+15 dBm

+14 dBm

12.8

12.6

12.4

12.2

12

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

-40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90 100

Temperature [°C]

D039

D040

图7-35. Output Power vs. Temperature (50 kbps, 868.3 MHz)

图7-36. Output Power vs. Temperature (50 kbps, 915 MHz)

Output Power vs. Temperature

Bluetooth Low Energy 1 Mbps, 2.44 GHz, 0 dBm

Output Power vs. Temperature

Bluetooth Low Energy 1 Mbps, 2.44 GHz, +5 dBm

2

1.8

1.6

1.4

1.2

1

7

6.8

6.6

6.4

6.2

6

5.8

5.6

5.4

5.2

5

0.8

0.6

0.4

0.2

0

4.8

4.6

4.4

4.2

4

-0.2

-0.4

-0.6

-0.8

-1

3.8

3.6

3.4

3.2

3

-1.2

-1.4

-1.6

-1.8

-2

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

Temperature [°C]

D042

D041

图7-38. Output Power vs. Temperature (Bluetooth Low Energy

图7-37. Output Power vs. Temperature (Bluetooth Low Energy

1 Mbps, 2.44 GHz, +5 dBm)

1 Mbps, 2.44 GHz)

Output Power vs. Temperature

Bluetooth Low Energy 1 Mbps, 2.44 GHz, +20 dBm PA, VDDS = 3.3 V

TX Output Power vs. Temperature

Bluetooth Low Energy 1 Mbps, 2.44 GHz, +10 dBm

15

26

+ 10 dBm

+ 9 dBm

+20 dBm

+19 dBm

14

+ 8 dBm

+ 7 dBm

+ 6 dBm

13

12

11

10

9

24

22

20

18

16

14

12

+18 dBm

+17 dBm

+16 dBm

+15 dBm

+14 dBm

8

7

6

5

4

3

2

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

Temperature [C]

-40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90 100

Temperature [°C]

图7-40. Output Power vs. Temperature (2.44 GHz, +10 dBm PA)

D043

图7-39. Output Power vs. Temperature (Bluetooth Low Energy

1 Mbps, 2.44 GHz, +20 dBm PA)

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7.20.5 TX Performance (continued)

Output Power vs. VDDS

50 kbps, 868.3 MHz, +14 dBm

Output Power vs. VDDS

50 kbps, 915 MHz, +20 dBm PA

14

13.9

13.8

13.7

13.6

13.5

13.4

13.3

13.2

13.1

13

22

20

18

16

14

12

10

+20 dBm

+19 dBm

+18 dBm

+17 dBm

+16 dBm

+15 dBm

+14 dBm

12.9

12.8

12.7

12.6

12.5

12.4

12.3

12.2

12.1

12

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9

3

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8

Voltage [V]

D045

D044

图7-42. Output Power vs. Supply Voltage (VDDS) (50 kbps, 915

图7-41. Output Power vs. Supply Voltage (VDDS) (50 kbps,

MHz)

868.3 MHz)

Output Power vs. VDDS

Bluetooth Low Energy 1 Mbps, 2.44 GHz, 0 dBm

Output Power vs. VDDS

Bluetooth Low Energy 1 Mbps, 2.44 GHz, +5 dBm

2

1.8

1.6

1.4

1.2

1

7

6.8

6.6

6.4

6.2

6

0.8

0.6

0.4

0.2

0

5.8

5.6

5.4

5.2

5

-0.2

-0.4

-0.6

-0.8

-1

4.8

4.6

4.4

4.2

4

-1.2

-1.4

-1.6

-1.8

-2

3.8

3.6

3.4

3.2

3

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Voltage [V]

D046

D048

图7-43. Output Power vs. Supply Voltage (VDDS) (Bluetooth

图7-44. Output Power vs. Supply Voltage (VDDS) (Bluetooth

Low Energy 1 Mbps, 2.44 GHz)

Low Energy 1 Mbps, 2.44 GHz, +5 dBm)

TX Output Power vs. VDDS

Output Power vs. VDDS

Bluetooth Low Energy 1 Mbps, 2.44 GHz, +20 dBm PA

Bluetooth Low Energy 1 Mbps, 2.44 GHz, +10 dBm PA

14

22

+ 10 dBm

+20 dBm

+19 dBm

13

12

11

10

9

+ 9 dBm

+ 8 dBm

+ 7 dBm

+ 6 dBm

+18 dBm

20

+17 dBm

+16 dBm

+15 dBm

18

+14 dBm

16

14

12

10

8

7

6

5

4

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Voltage [V]

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

图7-46. Output Power vs. Supply Voltage (VDDS) (2.44 GHz, +10

Voltage [V]

D050

dBm PA)

图7-45. Output Power vs. Supply Voltage (VDDS) (Bluetooth

Low Energy 1 Mbps, 2.44 GHz, +20 dBm PA)

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7.20.5 TX Performance (continued)

Output Power vs. Frequency

50 kbps, +14 dBm

Output Power vs. Frequency

50 kbps, +14 dBm

14

13.9

13.8

13.7

13.6

13.5

13.4

13.3

13.2

13.1

13

14

13.9

13.8

13.7

13.6

13.5

13.4

13.3

13.2

13.1

13

12.9

12.8

12.7

12.6

12.5

12.4

12.3

12.2

12.1

12

12.9

12.8

12.7

12.6

12.5

12.4

12.3

12.2

12.1

12

863

864

865

866

867

868

869

870

902 904 906 908 910 912 914 916 918 920 922 924 926 928

Frequency [MHz]

D052

D053

图7-47. Output Power vs. Frequency (50 kbps, 868 MHz)

图7-48. Output Power vs. Frequency (50 kbps, 915 MHz)

Output Power vs. Frequency

50 kbps, +20 dBm PA, VDDS = 3.3 V

Output Power vs. Frequency

Bluetooth Low Energy 1 Mbps, 2.44 Ghz, 0 dBm

22

2

1.8

1.6

1.4

1.2

1

+20 dBm

21.6

+17 dBm

21.2

20.8

20.4

20

0.8

0.6

0.4

0.2

0

19.6

19.2

18.8

18.4

18

-0.2

-0.4

-0.6

-0.8

-1

17.6

17.2

16.8

16.4

-1.2

-1.4

-1.6

-1.8

-2

16

902 904 906 908 910 912 914 916 918 920 922 924 926 928

2.4

2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48

Frequency [MHz]

D056

Frequency [GHz]

D058

图7-49. Output Power vs. Frequency (50 kbps, 915 MHz, VDDS

图7-50. Output Power vs. Frequency (Bluetooth Low Energy 1

= 3.3 V)

Mbps, 2.44 GHz)

Output Power vs. Frequency

Bluetooth Low Energy 1 Mbps, 2.44 Ghz, +5 dBm

Output Power vs. Frequency

Bluetooth Low Energy 1 Mbps, +20 dBm PA, VDDS = 3.3 V

7

6.8

6.6

6.4

6.2

6

25

+20 dBm

24

+19 dBm

+18 dBm

23

+17 dBm

+16 dBm

+15 dBm

+14 dBm

22

21

20

19

18

17

16

15

14

13

5.8

5.6

5.4

5.2

5

4.8

4.6

4.4

4.2

4

3.8

3.6

3.4

3.2

3

2.4

2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48

2.4

2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48

Frequency [GHz]

D059

D060

图7-51. Output Power vs. Frequency (Bluetooth Low Energy 1

图7-52. Output Power vs. Frequency (Bluetooth Low Energy 1

Mbps, 2.44 GHz, +5 dBm)

Mbps, 2.44 GHz, +20 dBm PA)

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7.20.5 TX Performance (continued)

Output Power vs. Frequency

IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), +10 dBm PA

14

13

12

11

10

9

+10 dBm

+9 dBm

+ 8dBm

+7 dBm

+6 dBm

8

7

6

5

2405

2415

2425

2435

2445

2455

2465

2475 2480

Frequency [MHz]

图7-53. Output Power vs. Frequency (250 kbps, +10 dBm PA)

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7.20.6 ADC Performance

ENOB vs. Input Frequency

ENOB vs. Sampling Frequency

Vin = 3.0 V Sine wave, Internal reference,

Fin = Fs / 10

11.4

Internal Reference, No Averaging

Internal Unscaled Reference, 14-bit Mode

10.2

10.15

10.1

10.05

10

11.1

10.8

10.5

10.2

9.9

9.95

9.9

9.85

9.8

9.6

1

2

3

4

5

6

7 8 10

20

30 40 50 70 100

200

0.2 0.3

0.5 0.7

1

2

3

4

5

6 7 8 10

20

30 40 50 70 100

Frequency [kHz]

D062

D061

图7-55. ENOB vs. Sampling Frequency

图7-54. ENOB vs. Input Frequency

INL vs. ADC Code

Vin = 3.0 V Sine wave, Internal reference,

200 kSamples/s

DNL vs. ADC Code

Vin = 3.0 V Sine wave, Internal reference,

200 kSamples/s

1.5

1

2.5

2

0.5

0

1.5

1

-0.5

-1

0.5

0

-1.5

-0.5

0

400

800

1200 1600 2000 2400 2800 3200 3600 4000

400

800

1200 1600 2000 2400 2800 3200 3600 4000

ADC Code

D064

D065

图7-56. INL vs. ADC Code

图7-57. DNL vs. ADC Code

ADC Accuracy vs. VDDS

Vin = 1 V, Internal reference,

200 kSamples/s

ADC Accuracy vs. Temperature

Vin = 1 V, Internal reference,

200 kSamples/s

1.01

1.009

1.008

1.007

1.006

1.005

1.004

1.003

1.002

1.001

1

1.01

1.009

1.008

1.007

1.006

1.005

1.004

1.003

1.002

1.001

1

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Temperature [°C]

Voltage [V]

D066

D067

图7-58. ADC Accuracy vs. Temperature

图7-59. ADC Accuracy vs. Supply Voltage (VDDS)

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8 Detailed Description

8.1 Overview

节3.1 shows the core modules of the CC1352P7 device.

8.2 System CPU

The CC1352P7 SimpleLink^™Wireless MCU contains an Arm^®Cortex^®-M4F system CPU, which runs the

application and the higher layers of radio protocol stacks.

The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements

of minimal memory implementation, and low-power consumption, while delivering outstanding computational

performance and exceptional system response to interrupts.

Its features include the following:

• ARMv7-M architecture optimized for small-footprint embedded applications

• Arm Thumb^®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm

core in a compact memory size

• Fast code execution permits increased sleep mode time

• Deterministic, high-performance interrupt handling for time-critical applications

• Single-cycle multiply instruction and hardware divide

• Hardware division and fast digital-signal-processing oriented multiply accumulate

• Saturating arithmetic for signal processing

• IEEE 754-compliant single-precision Floating Point Unit (FPU)

• Memory Protection Unit (MPU) for safety-critical applications

• Full debug with data matching for watchpoint generation

– Data Watchpoint and Trace Unit (DWT)

– JTAG Debug Access Port (DAP)

– Flash Patch and Breakpoint Unit (FPB)

• Trace support reduces the number of pins required for debugging and tracing

– Instrumentation Trace Macrocell Unit (ITM)

– Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO)

• Optimized for single-cycle flash memory access

• Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait

states

• Ultra-low-power consumption with integrated sleep modes

• 48 MHz operation

• 1.25 DMIPS per MHz

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8.3 Radio (RF Core)

The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor that

interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and

assembles the information bits in a given packet structure. The RF core offers a high level, command-based API

to the main CPU that configurations and data are passed through. The Arm Cortex-M0 processor is not

programmable by customers and is interfaced through the TI-provided RF driver that is included with the

SimpleLink Software Development Kit (SDK).

The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the main

CPU, which reduces power and leaves more resources for the user application. Several signals are also

available to control external circuitry such as RF switches or range extenders autonomously.

Dual-band and multiprotocol solutions are enabled through time-sliced access of the radio, handled

transparently for the application through the TI-provided RF driver and dual-mode manager.

The various physical layer radio formats are partly built as a software defined radio where the radio behavior is

either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with

the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards

even with over-the-air (OTA) updates while still using the same silicon.

备注

Not all combinations of features, frequencies, data rates, and modulation formats described in this

chapter are supported. Over time, TI can enable new physical radio formats (PHYs) for the device and

provides performance numbers for selected PHYs in the data sheet. Supported radio formats for a

specific device, including optimized settings to use with the TI RF driver, are included in the SmartRF

Studio tool with performance numbers of selected formats found in 节7.

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8.3.1 Proprietary Radio Formats

The CC1352P7 radio can support a wide range of physical radio formats through a set of hardware peripherals

combined with firmware available in the device ROM, covering various customer needs for optimizing towards

parameters such as speed or sensitivity. This allows great flexibility in tuning the radio both to work with legacy

protocols as well as customizing the behavior for specific application needs.

表 8-1 gives a simplified overview of features of the various radio formats available in ROM. Other radio formats

may be available in the form of radio firmware patches or programs through the Software Development Kit (SDK)

and may combine features in a different manner, as well as add other features.

表8-1. Feature Support

Feature

Main 2-(G)FSK Mode

High Data Rates

Low Data Rates

SimpleLink™ Long Range

Programmable preamble,

sync word and CRC

Yes

No

Programmable receive

bandwidth

Yes

Yes (down to 4 kHz)

Yes

Data / Symbol rate⁽³⁾

20 to 1000 kbps

2-(G)FSK

≤2 Msps

≤100 ksps

≤20 ksps

2-(G)FSK

4-(G)FSK

2-(G)FSK

4-(G)FSK

Modulation format

Dual Sync Word

Carrier Sense ^{(1) (2)}

Preamble Detection⁽²⁾

Data Whitening

Digital RSSI

Yes

No

Yes

No

Yes

CRC filtering

1:2

1:4

1:8

Direct-sequence spread

spectrum (DSSS)

No

Forward error correction

(FEC)

No

Yes

Link Quality Indicator (LQI)

Yes

(1) Carrier Sense can be used to implement HW-controlled listen-before-talk (LBT) and Clear Channel Assessment (CCA) for compliance

with such requirements in regulatory standards. This is available through the CMD_PROP_CS radio API.

(2) Carrier Sense and Preamble Detection can be used to implement sniff modes where the radio is duty cycled to save power.

(3) Data rates are only indicative. Data rates outside this range may also be supported. For some specific combinations of settings, a

smaller range might be supported.

8.3.2 Bluetooth 5.2 Low Energy

The RF Core offers full support for Bluetooth 5.2 Low Energy, including the high-speed 2-Mbps physical layer

and the 500-kbps and 125-kbps long range PHYs (Coded PHY) through the TI provided Bluetooth 5.2 stack or

through a high-level Bluetooth API. The Bluetooth 5.2 PHY and part of the controller are in radio and system

ROM, providing significant savings in memory usage and more space available for applications.

The new high-speed mode allows data transfers up to 2 Mbps, twice the speed of Bluetooth 4.2 and five times

the speed of Bluetooth 4.0, without increasing power consumption. In addition to faster speeds, this mode offers

significant improvements for energy efficiency and wireless coexistence with reduced radio communication time.

Bluetooth 5.2 also enables unparalleled flexibility for adjustment of speed and range based on application needs,

which capitalizes on the high-speed or long-range modes respectively. Data transfers are now possible at 2

Mbps, enabling development of applications using voice, audio, imaging, and data logging that were not

previously an option using Bluetooth Low Energy. With high-speed mode, existing applications deliver faster

responses, richer engagement, and longer battery life. Bluetooth 5.2 enables fast, reliable firmware updates.

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8.3.3 802.15.4 (Thread, Zigbee, 6LoWPAN)

Through a dedicated IEEE radio API, the RF Core supports the 2.4-GHz IEEE 802.15.4-2011 physical layer (2

Mchips per second Offset-QPSK with DSSS 1:8), used in Thread, Zigbee, and 6LoWPAN protocols. The

802.15.4 PHY and MAC are in radio and system ROM. TI also provides royalty-free protocol stacks for Thread

and Zigbee as part of the SimpleLink SDK, enabling a robust end-to-end solution.

8.4 Memory

The up to 704KB nonvolatile (flash) memory provides storage for code and data. The flash memory is in-system

programmable and erasable. The last flash memory sector must contain a Customer Configuration section

(CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is done

through the ccfg.c source file that is included in all TI provided examples.

The ultra-low leakage system static RAM (SRAM) is split into four 32KB and one 16KB blocks and can be used

for both storage of data and execution of code. Retention of SRAM contents in Standby power mode is enabled

by default and included in Standby mode power consumption numbers. Parity checking for detection of bit errors

in memory is built-in, which reduces chip-level soft errors and thereby increases reliability. System SRAM is

always initialized to zeroes upon code execution from boot.

To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way

nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the system CPU.

The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area

(CCFG).

There is a 4KB ultra-low leakage SRAM available for use with the Sensor Controller Engine which is typically

used for storing Sensor Controller programs, data and configuration parameters. This RAM is also accessible by

the system CPU. The Sensor Controller RAM is not cleared to zeroes between system resets.

The ROM includes a TI-RTOS kernel and low-level drivers, as well as significant parts of selected radio stacks,

which frees up flash memory for the application. The ROM also contains a serial (SPI and UART) bootloader that

can be used for initial programming of the device.

8.5 Sensor Controller

The Sensor Controller contains circuitry that can be selectively enabled in both Standby and Active power

modes. The peripherals in this domain can be controlled by the Sensor Controller Engine, which is a proprietary

power-optimized CPU. This CPU can read and monitor sensors or perform other tasks autonomously; thereby

significantly reducing power consumption and offloading the system CPU.

The Sensor Controller Engine is user programmable with a simple programming language that has syntax

similar to C. This programmability allows for sensor polling and other tasks to be specified as sequential

algorithms rather than static configuration of complex peripheral modules, timers, DMA, register programmable

state machines, or event routing.

The main advantages are:

• Flexibility - data can be read and processed in unlimited manners while still ensuring ultra-low power

• 2 MHz low-power mode enables lowest possible handling of digital sensors

• Dynamic reuse of hardware resources

• 40-bit accumulator supporting multiplication, addition and shift

• Observability and debugging options

Sensor Controller Studio is used to write, test, and debug code for the Sensor Controller. The tool produces C

driver source code, which the System CPU application uses to control and exchange data with the Sensor

Controller. Typical use cases may be (but are not limited to) the following:

• Read analog sensors using integrated ADC or comparators

• Interface digital sensors using GPIOs, SPI, UART, or I²C (UART and I²C are bit-banged)

• Capacitive sensing

• Waveform generation

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• Very low-power pulse counting (flow metering)

• Key scan

The peripherals in the Sensor Controller include the following:

• The low-power clocked comparator can be used to wake the system CPU from any state in which the

comparator is active. A configurable internal reference DAC can be used in conjunction with the comparator.

The output of the comparator can also be used to trigger an interrupt or the ADC.

• Capacitive sensing functionality is implemented through the use of a constant current source, a time-to-digital

converter, and a comparator. The continuous time comparator in this block can also be used as a higher-

accuracy alternative to the low-power clocked comparator. The Sensor Controller takes care of baseline

tracking, hysteresis, filtering, and other related functions when these modules are used for capacitive

sensing.

• The ADC is a 12-bit, 200-ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC can be

triggered by many different sources including timers, I/O pins, software, and comparators.

• The analog modules can connect to up to eight different GPIOs

• Dedicated SPI master with up to 6 MHz clock speed

The peripherals in the Sensor Controller can also be controlled from the main application processor.

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8.6 Cryptography

The CC1352P7 device comes with a wide set of modern cryptography-related hardware accelerators, drastically

reducing code footprint and execution time for cryptographic operations. It also has the benefit of being lower

power and improves availability and responsiveness of the system because the cryptography operations runs in

a background hardware thread.

Together with a large selection of open-source cryptography libraries provided with the Software Development

Kit (SDK), this allows for secure and future proof IoT applications to be easily built on top of the platform. The

hardware accelerator modules are:

• True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for the

purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is

built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit.

• Secure Hash Algorithm 2 (SHA-2) with support for SHA224, SHA256, SHA384, and SHA512

• Advanced Encryption Standard (AES) with 128 and 256 bit key lengths

• Public Key Accelerator - Hardware accelerator supporting mathematical operations needed for elliptic

curves up to 512 bits and RSA key pair generation up to 1024 bits.

Through use of these modules and the TI provided cryptography drivers, the following capabilities are available

for an application or stack:

• Key Agreement Schemes

– Elliptic curve Diffie–Hellman with static or ephemeral keys (ECDH and ECDHE)

– Elliptic curve Password Authenticated Key Exchange by Juggling (ECJ-PAKE)

• Signature Generation

– Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA)

• Curve Support

– Short Weierstrass form (full hardware support), such as:

• NIST-P224, NIST-P256, NIST-P384, NIST-P521

• Brainpool-256R1, Brainpool-384R1, Brainpool-512R1

• secp256r1

– Montgomery form (hardware support for multiplication), such as:

• Curve25519

• SHA2 based MACs

– HMAC with SHA224, SHA256, SHA384, or SHA512

• Block cipher mode of operation

– AESCCM

– AESGCM

– AESECB

– AESCBC

– AESCBC-MAC

• True random number generation

Other capabilities, such as RSA encryption and signatures as well as Edwards type of elliptic curves such as

Curve1174 or Ed25519, can also be implemented using the provided hardware accelerators but are not part of

the TI SimpleLink SDK for the CC1352P7 device.

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8.7 Timers

A large selection of timers are available as part of the CC1352P7 device. These timers are:

• Real-Time Clock (RTC)

A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF). This timer is

available in all power modes except Shutdown. The timer can be calibrated to compensate for frequency drift

when using the RCOSC_LF as the low frequency system clock. If an external LF clock with frequency

different from 32.768 kHz is used, the RTC tick speed can be adjusted to compensate for this. When using

TI-RTOS, the RTC is used as the base timer in the operating system and should thus only be accessed

through the kernel APIs such as the Clock module. The real time clock can also be read by the Sensor

Controller Engine to timestamp sensor data and also has dedicated capture channels. By default, the RTC

halts when a debugger halts the device.

• General Purpose Timers (GPTIMER)

The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on up to 48

MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or periodic counting,

pulse width modulation (PWM), time counting between edges and edge counting. The inputs and outputs of

the timer are connected to the device event fabric, which allows the timers to interact with signals such as

GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available in Active and Idle power modes.

• Sensor Controller Timers

The Sensor Controller contains 3 timers:

AUX Timer 0 and 1 are 16-bit timers with a 2^Nprescaler. Timers can either increment on a clock or on each

edge of a selected tick source. Both one-shot and periodical timer modes are available.

AUX Timer 2 is a 16-bit timer that can operate at 24 MHz, 2 MHz or 32 kHz independent of the Sensor

Controller functionality. There are 4 capture or compare channels, which can be operated in one-shot or

periodical modes. The timer can be used to generate events for the Sensor Controller Engine or the ADC, as

well as for PWM output or waveform generation.

• Radio Timer

A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is

typically used as the timing base in wireless network communication using the 32-bit timing word as the

network time. The radio timer is synchronized with the RTC by using a dedicated radio API when the device

radio is turned on or off. This ensures that for a network stack, the radio timer seems to always be running

when the radio is enabled. The radio timer is in most cases used indirectly through the trigger time fields in

the radio APIs and should only be used when the accurate 48 MHz high frequency crystal is the source of

SCLK_HF.

• Watchdog timer

The watchdog timer is used to regain control if the system operates incorrectly due to software errors. It is

typically used to generate an interrupt to and reset of the device for the case where periodic monitoring of the

system components and tasks fails to verify proper functionality. The watchdog timer runs on a 1.5 MHz clock

rate and cannot be stopped once enabled. The watchdog timer pauses to run in Standby power mode and

when a debugger halts the device.

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8.8 Serial Peripherals and I/O

The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's synchronous

serial interfaces. The SSIs support both SPI master and slave up to 4 MHz. The SSI modules support

configurable phase and polarity.

The UARTs implement universal asynchronous receiver and transmitter functions. They support flexible baud-

rate generation up to a maximum of 3 Mbps.

The I²S interface is used to handle digital audio and can also be used to interface pulse-density modulation

microphones (PDM).

The I²C interface is used to communicate with devices compatible with the I²C standard. The I²C interface can

handle 100 kHz and 400 kHz operation, and can serve as both master and slave.

The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals

to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a

programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge

(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs

have high-drive capabilities, which are marked in bold in 节 6. All digital peripherals can be connected to any

digital pin on the device.

For more information, see the CC13x2x7, CC26x2x7 SimpleLink™ Wireless MCU Technical Reference Manual.

8.9 Battery and Temperature Monitor

A combined temperature and battery voltage monitor is available in the CC1352P7 device. The battery and

temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage and

respond to changes in environmental conditions as needed. The module contains window comparators to

interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can

also be used to wake up the device from Standby mode through the Always-On (AON) event fabric.

8.10 µDMA

The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload

data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available

bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA

controller has dedicated channels for each supported on-chip module and can be programmed to automatically

perform transfers between peripherals and memory when the peripheral is ready to transfer more data.

Some features of the µDMA controller include the following (this is not an exhaustive list):

• Highly flexible and configurable channel operation of up to 32 channels

• Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral

• Data sizes of 8, 16, and 32 bits

• Ping-pong mode for continuous streaming of data

8.11 Debug

The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface.

The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.

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8.12 Power Management

To minimize power consumption, the CC1352P7 supports a number of power modes and power management

features (see 表8-2).

表8-2. Power Modes

SOFTWARE CONFIGURABLE POWER MODES

RESET PIN

HELD

MODE

ACTIVE

Active

On

IDLE

Off

STANDBY

Off

SHUTDOWN

CPU

Off

No

Off

No

Flash

Available

On

Off

SRAM

On

Retention

Duty Cycled

Partial

Full

Supply System

Register and CPU retention

SRAM retention

On

Full

48 MHz high-speed clock

(SCLK_HF)

XOSC_HF or

RCOSC_HF

XOSC_HF or

RCOSC_HF

Off

2 MHz medium-speed clock

(SCLK_MF)

RCOSC_MF

Available

32 kHz low-speed clock

(SCLK_LF)

XOSC_LF or

RCOSC_LF

XOSC_LF or

RCOSC_LF

XOSC_LF or

RCOSC_LF

Peripherals

Available

On

Available

On

Off

Available

On

Off

On

Off

Sensor Controller

Wake-up on RTC

Off

Wake-up on pin edge

Wake-up on reset pin

Brownout detector (BOD)

Power-on reset (POR)

Watchdog timer (WDT)

Available

On

Duty Cycled

On

Off

On

Off

Available

Paused

Off

In Active mode, the application system CPU is actively executing code. Active mode provides normal operation

of the processor and all of the peripherals that are currently enabled. The system clock can be any available

clock source (see 表8-2).

In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked

and no code is executed. Any interrupt event brings the processor back into active mode.

In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or Sensor

Controller event is required to bring the device back to active mode. MCU peripherals with retention do not need

to be reconfigured when waking up again, and the CPU continues execution from where it went into standby

mode. All GPIOs are latched in standby mode.

In Shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller), and the

I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin

defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can

differentiate between reset in this way and reset-by-reset pin or power-on reset by reading the reset status

register. The only state retained in this mode is the latched I/O state and the flash memory contents.

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The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor Controller

independently of the system CPU. This means that the system CPU does not have to wake up, for example to

perform an ADC sampling or poll a digital sensor over SPI, thus saving both current and wake-up time that would

otherwise be wasted. The Sensor Controller Studio tool enables the user to program the Sensor Controller,

control its peripherals, and wake up the system CPU as needed. All Sensor Controller peripherals can also be

controlled by the system CPU.

备注

The power, RF and clock management for the CC1352P7 device require specific configuration and

handling by software for optimized performance. This configuration and handling is implemented in the

TI-provided drivers that are part of the SimpleLink™ CC13xx and CC26xx software development kit

(SDK). Therefore, TI highly recommends using this software framework for all application

development on the device. The complete SDK with TI-RTOS (optional), device drivers, and examples

are offered free of charge in source code.

8.13 Clock Systems

The CC1352P7 device has several internal system clocks.

The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by the

internal 48 MHz RC Oscillator (RCOSC_HF) or an external 48 MHz crystal (XOSC_HF). Radio operation

requires an external 48 MHz crystal.

SCLK_MF is an internal 2 MHz clock that is used by the Sensor Controller in low-power mode and also for

internal power management circuitry. The SCLK_MF clock is always driven by the internal 2 MHz RC Oscillator

(RCOSC_MF).

SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used by the Sensor Controller for

ultra-low-power operation and is also used for the RTC and to synchronize the radio timer before or after

Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC Oscillator (RCOSC_LF), a 32.768

kHz watch-type crystal, or a clock input on any digital IO.

When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to other

devices, thereby reducing the overall system cost.

8.14 Network Processor

Depending on the product configuration, the CC1352P7 device can function as a wireless network processor

(WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as

a system-on-chip (SoC) with the application and protocol stack running on the device's system CPU inside the

device.

In the first case, the external host MCU communicates with the device using SPI or UART. In the second case,

the application must be written according to the application framework supplied with the wireless protocol stack.

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9 Application, Implementation, and Layout

备注

Information in the following Applications section is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI's customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

For general design guidelines and hardware configuration guidelines, refer to CC13xx/CC26xx Hardware

Configuration and PCB Design Considerations Application Report.

For optimum RF performance, especially when using the high-power PA, it is important to accurately follow the

reference design with respect to component values and layout. Failure to do so may lead to reduced RF

performance due to balun mismatch. For the high-power PA, the amplitude- and phase balance through the

balun must be <1 dB and <6 degrees, respectively.

PCB stack-up is also critical for proper operation. The CC1352P7 EVMs and characterization boards are using a

finished thickness between the top layer (RF signals) and layer 2 (ground plane) of 175 µm. It is very important

to use the same substrate thickness, or slightly thicker, in an end product implementing the CC1352P7 device.

9.1 Reference Designs

The following reference designs should be followed closely when implementing designs using the CC1352P7

device.

Special attention must be paid to RF component placement, decoupling capacitors and DCDC regulator

components, as well as ground connections for all of these.

CC1352-P7EM-XD7793- The differential CC1352-P7EM-XD7793-XD24-PA9093 reference design provides

XD24-PA9093 Design

Files

schematic, layout and production files for the characterization board used for deriving

the performance number found in this document. This board includes tuning for

915 MHz on the high-power PA output.

CC1352-P7EM-XD7793- The differential CC1352-P7EM-XD7793-XD24-PA24 reference design provides

XD24-PA24 Design Files schematic, layout and production files for the characterization board used for deriving

the performance number found in this document. This board includes tuning for 20

dBm operation at 2.4 GHz on the high-power PA output.

CC1352-P7EM-XD7793- The differential CC1352-P7EM-XD7793-XD24-PA24_10dBm reference design

XD24-PA24_10dBm

Design Files

provides schematic, layout and production files for the characterization board used for

deriving the performance number found in this document. This board includes tuning

for 10 dBm operation at 2.4 GHz on the high-power PA output.

LP-CC1352P7-1 Design Detailed schematics and layouts for the multi-band CC1352P7 LaunchPad evaluation

Files

board featuring 868/915 MHz RF matching on the 20 dBm PA output and up to 5 dBm

TX power at 2.4 GHz.

LP-CC1352P7-4 Design Detailed schematics and layouts for the multi-band CC1352P7 LaunchPad evaluation

Files

board featuring 2.4 GHz RF matching optimized for 10 dBm operation on the 20 dBm

PA output and up to 13 dBm TX power at 433 MHz. For evaluation of 20 dBm

operation at 2.4 GHz the BOM can be modified as described in the schematics

available in the Design Files.

Sub-1 GHz

The antenna kit allows real-life testing to identify the optimal antenna for your

and 2.4 GHz Antenna Kit application. The antenna kit includes 16 antennas for frequencies from 169 MHz to

for LaunchPad™

Development

Kit and SensorTag

2.4 GHz, including:

• PCB antennas

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• Helical antennas

• Chip antennas

• Dual-band antennas for 868 MHz and 915 MHz combined with 2.4 GHz

The antenna kit includes a JSC cable to connect to the Wireless MCU LaunchPad

Development Kits and SensorTags.

9.2 Junction Temperature Calculation

This section shows the different techniques for calculating the junction temperature under various operating

conditions. For more details, see Semiconductor and IC Package Thermal Metrics.

There are three recommended ways to derive the junction temperature from other measured temperatures:

1. From package temperature:

T = ψ × P + T

case

(1)

(2)

(3)

J

JT

2. From board temperature:

T = ψ × P + T

board

J

JB

3. From ambient temperature:

T = R

× P + T

A

J

θJA

P is the power dissipated from the device and can be calculated by multiplying current consumption with supply

voltage. Thermal resistance coefficients are found in 节7.8.

Example:

Using 方程式 3, the temperature difference between ambient temperature and junction temperature is

calculated. In this example, we assume a simple use case where the radio is transmitting continuously at 20dBm

output power. Let us assume the ambient temperature is 105 °C and the supply voltage is 3.3 V. To calculate P,

we need to look up the current consumption for Tx at 105 °C in 图 7-11. From the plot, we see that the current

consumption is 68 mA. This means that P is 3.3 V × 68 mA = 224.4 mW.

The junction temperature is then calculated as:

°C

T = 23.4

× 224.4mW + T = 5.3°C + T

A

(4)

W

J

A

As can be seen from the example, the junction temperature is 5.3 °C higher than the ambient temperature when

running continuous Tx at 105 °C and, thus, well within the recommended operating conditions of 115 °C.

For various application use cases current consumption for other modules may have to be added to calculate the

appropriate power dissipation. For example, the MCU may be running simultaneously as the radio, peripheral

modules may be enabled, etc. Typically, the easiest way to find the peak current consumption, and thus the peak

power dissipation in the device, is to measure as described in Measuring CC13xx and CC26xx Current

Consumption.

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10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed as follows.

10.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and/or date-

code. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example, XCC1352P7 is

in preview; therefore, an X prefix/identification is assigned).

Device development evolutionary flow:

X

P

Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

null Production version of the silicon die that is fully qualified.

Production devices have been characterized fully, and the quality and reliability of the device have been

demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, RGZ).

For orderable part numbers of CC1352P7 devices in the RGZ (7-mm x 7-mm) package type, see the Package

Option Addendum of this document, the Device Information in 节 3, the TI website (www.ti.com), or contact your

TI sales representative.

CC1352

P

7

4

T

0

RGZ

R

R = Large Reel

PREFIX

X = Experimental device

Blank = Qualified device

PACKAGE

RGZ = 48-pin VQFN (Very Thin Quad Flatpack No-Lead)

PRODUCT REVISION

DEVICE

SimpleLink™ Ultra-Low-Power

Wireless MCU

TEMPERATURE

T = 105 C Ambient

CONFIGURATION

R = Regular

P = +20 dBm PA included

SRAM SIZE

4 = 144kB

FLASH SIZE

7 = 704 kB

图10-1. Device Nomenclature

10.2 Tools and Software

The CC1352P7 device is supported by a variety of software and hardware development tools.

Development Kit

CC1352P7-1

LaunchPad™

Development Kit

The CC1352P7-1 LaunchPad^™Development Kit enables development of high-performance

wireless applications in the 863 - 930 MHz and 2.4 GHz frequency bands that benefit from

low-power operation. The kit features the CC1352P7 multi-band and multiprotocol SimpleLink

Wireless MCU with an integrated High-Power Amplifier. The kit works with the LaunchPad

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ecosystem, easily enabling additional functionality like sensors, display, and more. The built-

in EnergyTrace^™software is an energy-based code analysis tool that measures and displays

the application’s energy profile and helps to optimize it for ultra-low power consumption.

The RF configuration of the LaunchPad enables up to +20 dBm output power for 863 to

930 MHz and +5 dBm output power for 2.4 GHz.

CC1352P7-4

LaunchPad™

Development Kit

The CC1352P7-4 LaunchPad^™Development Kit enables development of high-performance

wireless applications in the 433 MHz and 2.4 GHz frequency bands that benefit from low-

power operation. The kit features the CC1352P7 dual-band and multiprotocol SimpleLink

Wireless MCU with an integrated High Power Amplifier. The kit works with the LaunchPad

ecosystem, easily enabling additional functionality like sensors, display, and more. The built-

in EnergyTrace^™software is an energy-based code analysis tool that measures and displays

the application’s energy profile and helps to optimize it for ultra-low-power consumption.

The RF configuration of the LaunchPad enables up to +13 dBm output power for 433 MHz

and +10 dBm output power for 2.4 GHz. The LaunchPad can also be used as a development

kit when evaluating other device family devices such as CC1312R7 for use with 433 MHz

frequency bands or CC2652P7 for +10 dBm in the 2.4 GHz band.

For evaluation of +20 dBm operation at 2.4 GHz the BOM can be modified as described in

the schematics available in the Design Files.

Software

SimpleLink™

CC13XX-

CC26XX SDK

The SimpleLink CC13xx and CC26xx Software Development Kit (SDK) provides a complete

package for the development of wireless applications on the CC13XX / CC26XX family of

devices. The SDK includes a comprehensive software package for the CC1352P7 device,

including the following protocol stacks:

• Bluetooth Low Energy 4 and 5.2

• Thread (based on OpenThread)

• Zigbee 3.0

• Wi-SUN^®

• TI 15.4-Stack - an IEEE 802.15.4-based star networking solution for Sub-1 GHz and

2.4 GHz

• Proprietary RF - a large set of building blocks for building proprietary RF software

• Multiprotocol support - concurrent operation between stacks using the Dynamic Multiprotocol

Manager (DMM)

The SimpleLink CC13XX-CC26XX SDK is part of TI’s SimpleLink MCU platform, offering a

single development environment that delivers flexible hardware, software and tool options for

customers developing wired and wireless applications. For more information about the

SimpleLink MCU Platform, visit http://www.ti.com/simplelink.

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Development Tools

Code Composer

Studio^™

Integrated

Development

Environment (IDE)

Code Composer Studio is an integrated development environment (IDE) that supports TI's

Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a

suite of tools used to develop and debug embedded applications. It includes an optimizing

C/C++ compiler, source code editor, project build environment, debugger, profiler, and many

other features. The intuitive IDE provides a single user interface taking you through each

step of the application development flow. Familiar tools and interfaces allow users to get

started faster than ever before. Code Composer Studio combines the advantages of the

Eclipse^®software framework with advanced embedded debug capabilities from TI resulting

in a compelling feature-rich development environment for embedded developers.

CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace^™

software (application energy usage profiling). A real-time object viewer plugin is available for

TI-RTOS, part of the SimpleLink SDK.

Code Composer Studio is provided free of charge when used in conjunction with the XDS

debuggers included on a LaunchPad Development Kit.

Code Composer

Studio™ Cloud

IDE

Code Composer Studio (CCS) Cloud is a web-based IDE that allows you to create, edit and

build CCS and Energia™ projects. After you have successfully built your project, you can

download and run on your connected LaunchPad. Basic debugging, including features like

setting breakpoints and viewing variable values is now supported with CCS Cloud.

IAR Embedded

Workbench^®for

Arm^®

IAR Embedded Workbench^®is a set of development tools for building and debugging

embedded system applications using assembler, C and C++. It provides a completely

integrated development environment that includes a project manager, editor, and build tools.

IAR has support for all SimpleLink Wireless MCUs. It offers broad debugger support,

including XDS110, IAR I-jet^™and Segger J-Link^™. A real-time object viewer plugin is

available for TI-RTOS, part of the SimpleLink SDK. IAR is also supported out-of-the-box on

most software examples provided as part of the SimpleLink SDK.

A 30-day evaluation or a 32 KB size-limited version is available through iar.com.

SmartRF™ Studio

SmartRF™ Studio is a Windows^®application that can be used to evaluate and configure

SimpleLink Wireless MCUs from Texas Instruments. The application will help designers of

RF systems to easily evaluate the radio at an early stage in the design process. It is

especially useful for generation of configuration register values and for practical testing and

debugging of the RF system. SmartRF Studio can be used either as a standalone

application or together with applicable evaluation boards or debug probes for the RF device.

Features of the SmartRF Studio include:

• Link tests - transmit and receive packets between nodes

• Antenna and radiation tests - set the radio in continuous wave TX and RX states

• Export radio configuration code for use with the TI SimpleLink SDK RF driver

• Custom GPIO configuration for signaling and control of external switches

Sensor Controller

Studio

Sensor Controller Studio is used to write, test and debug code for the Sensor Controller

peripheral. The tool generates a Sensor Controller Interface driver, which is a set of C

source files that are compiled into the System CPU application. These source files also

contain the Sensor Controller binary image and allow the System CPU application to control

and exchange data with the Sensor Controller. Features of the Sensor Controller Studio

include:

• Ready-to-use examples for several common use cases

• Full toolchain with built-in compiler and assembler for programming in a C-like

programming language

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• Provides rapid development by using the integrated sensor controller task testing and

debugging functionality, including visualization of sensor data and verification of

algorithms

CCS UniFlash

CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs.

UniFlash has a GUI, command line, and scripting interface. CCS UniFlash is available free

of charge.

10.2.1 SimpleLink™ Microcontroller Platform

The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of wired

and wireless Arm^®MCUs (System-on-Chip) in a single software development environment. Delivering flexible

hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software

development kit and use throughout your entire portfolio. Learn more on ti.com/simplelink.

10.3 Documentation Support

To receive notification of documentation updates on data sheets, errata, application notes and similar, navigate

to the device product folder on ti.com/product/CC1352P7. In the upper right corner, click on Alert me to register

and receive a weekly digest of any product information that has changed. For change details, review the revision

history included in any revised document.

The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as

follows.

TI Resource Explorer

Software examples, libraries, executables, and documentation are available for your

device and development board.

Errata

CC1352P7 Silicon

Errata

The silicon errata describes the known exceptions to the functional specifications for

each silicon revision of the device and description on how to recognize a device

revision.

Application Reports

All application reports for the CC1352P7 device are found on the device product folder at: ti.com/product/

CC1352P7/#tech-docs.

Technical Reference Manual (TRM)

CC13x2x7, CC26x2x7 SimpleLink™

Wireless MCU TRM

The TRM provides a detailed description of all modules and

peripherals available in the device family.

10.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.5 Trademarks

SimpleLink^™, LaunchPad^™, EnergyTrace^™, Code Composer Studio^™, and TI E2E^™are trademarks of Texas

Instruments.

I-jet^™is a trademark of IAR Systems AB.

J-Link^™is a trademark of SEGGER Microcontroller Systeme GmbH.

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Wi-SUN^®and mioty^®are registered trademarks of Wi-SUN Alliance Inc.

Zigbee^®is a registered trademark of Zigbee Alliance Inc.

Bluetooth^®is a registered trademark of Bluetooth SIG Inc.

Arm Thumb^®is a registered trademark of Arm Limited (or its subsidiaries).

Eclipse^®is a registered trademark of Eclipse Foundation.

IAR Embedded Workbench^®is a registered trademark of IAR Systems AB.

Windows^®is a registered trademark of Microsoft Corporation.

所有商标均为其各自所有者的财产。

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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11 Mechanical, Packaging, and Orderable Information

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GENERIC PACKAGE VIEW

RGZ 48

7 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224671/A

www.ti.com

PACKAGE OUTLINE

VQFN - 1 mm max height

RGZ0048A

PLASTIC QUADFLAT PACK- NO LEAD

A

7.1

6.9

B

(0.1) TYP

7.1

6.9

SIDE WALL DETAIL

OPTIONAL METAL THICKNESS

PIN 1 INDEX AREA

(0.45) TYP

CHAMFERED LEAD

CORNER LEAD OPTION

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

2X 5.5

5.15±0.1

(0.2) TYP

13

24

44X 0.5

12

25

SEE SIDE WALL

DETAIL

SYMM

2X

5.5

1

36

0.30

0.18

PIN1 ID

(OPTIONAL)

48X

48

37

SYMM

0.1

C A B

C

0.5

0.3

48X

0.05

SEE LEAD OPTION

4219044/D 02/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGZ0048A

PLASTIC QUADFLAT PACK- NO LEAD

2X (6.8)

5.15)

SYMM

(

48X (0.6)

37

48

48X (0.24)

44X (0.5)

1

36

SYMM

2X

(5.5)

(6.8)

2X

(1.26)

2X

(1.065)

(R0.05)

TYP

25

12

21X (Ø0.2) VIA

TYP

24

13

2X (1.065)

2X (1.26)

2X (5.5)

LAND PATTERN EXAMPLE

SCALE: 15X

SOLDER MASK

OPENING

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4219044/D 02/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGZ0048A

PLASTIC QUADFLAT PACK- NO LEAD

2X (6.8)

SYMM

(

1.06)

37

48X (0.6)

48

48X (0.24)

44X (0.5)

1

36

SYMM

2X

(5.5)

(6.8)

2X

(0.63)

2X

(1.26)

(R0.05)

TYP

25

12

24

13

2X

(1.26)

2X (0.63)

2X (5.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

67% PRINTED COVERAGE BY AREA

SCALE: 15X

4219044/D 02/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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重要声明和免责声明

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型号：	CC1352P7
厂家：	TEXAS INSTRUMENTS
描述：	具有集成式功率放大器的 SimpleLink™ Arm® Cortex®-M4F 多协议低于 1GHz 和 2.4GHz 无线 MCU 放大器无线功率放大器
文件：	总72页 (文件大小：3343K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CC1352P7 [TI]

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