CC1311P3 [TI]
具有 352KB 闪存和集成 +20dBm PA 的 SimpleLink™ Arm® Cortex®-M4 Sub-1GHz 无线 MCU;型号: | CC1311P3 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 352KB 闪存和集成 +20dBm PA 的 SimpleLink™ Arm® Cortex®-M4 Sub-1GHz 无线 MCU 无线 闪存 |
文件: | 总61页 (文件大小:3137K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CC1311P3
ZHCSQ71 –MARCH 2022
CC1311P3 具有集成式功率放大器的
SimpleLink™ 高性能Sub-1GHz 无线MCU
MCU 外设
1 特性
• 数字外设可连接至任何GPIO
无线微控制器
• 四个32 位或八个16 位通用计时器
• 12 位ADC、200ksps、8 通道
• 8 位DAC
• 功能强大的48MHz Arm® Cortex®-M4 处理器
• 352KB 闪存程序存储器
• 32KB 超低泄漏SRAM
• 模拟比较器
• UART、SSI、I2C、I2S
• 实时时钟(RTC)
• 集成温度和电池监控器
• 8KB 缓存SRAM(也可作为通用RAM 提供)
• 可编程无线电包括对2-(G)FSK、4-(G)FSK、
MSK、OOK、IEEE 802.15.4 PHY 和MAC 的支持
• 支持无线升级(OTA)
安全驱动工具
低功耗
• AES 128 位加密加速计
• 真随机数发生器(TRNG)
• MCU 功耗:
– 2.63mA 有源模式,CoreMark®
– 55μA/MHz(运行CoreMark 时)
– 0.7μA 待机模式,RTC,32KB RAM
– 0.1μA 关断模式,引脚唤醒
• 无线电功耗:
• 软件开发套件(SDK) 中提供了其他加密驱动器
开发工具和软件
• LP-CC1311P3 开发套件
• SimpleLink™ CC13xx 和CC26xx 软件开发套件
(SDK)
• 用于简单无线电配置的SmartRF™ Studio
• SysConfig 系统配置工具
– RX:5.4mA(在868MHz 条件下)
– TX:24.9mA(在+14dBm 和868MHz 条件
下)
工作温度范围
– TX:65mA(在+20dBm 和915MHz 条件下)
• 片上降压直流/直流转换器
• 1.8V 至3.8V 单电源电压
• -40°C 至+105°C
无线协议支持
• mioty
• 无线M-Bus
• SimpleLink™ TI 15.4-stack
• 6LoWPAN
封装
• 7mm × 7mm RGZ VQFN48(26 个GPIO)
• 符合RoHS 标准的封装
• 专有系统
高性能无线电
• -121dBm(在2.5kbps 远距离模式下)
• -120dBm(在4.8kbps 窄带模式、433MHz 下)
• -118dBm(在9.6kbps 窄带模式、868MHz 下)
• -110dBm(在50kbps、802.15.4、868MHz 时)
• 高达+20dBm 的输出功率,具有温度补偿
• 低至4kHz 的接收器滤波器带宽
法规遵从性
• 适用于符合以下标准的系统:
– ETSI EN 300 220 接收器类别1.5 和2、EN 303
131、EN 303 204
– FCC CFR47 第15 部分
– ARIB STD-T108
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SWRS255
CC1311P3
ZHCSQ71 –MARCH 2022
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– 防火安全–烟雾和热量探测器、气体检测仪以
及火警控制面板
• 零售自动化
2 应用
• 电网基础设施
– 零售自动化和支付应用–电子货架标签和便携
式POS 终端
• 个人电子产品
– 智能仪表–电表、水表、燃气表和热量分配表
– 电网通信–无线通信
– 电动汽车充电基础设施–交流充电(桩)站
– 其他替代能源–能量收集
• 楼宇自动化
– 射频远程控制
– 智能扬声器和智能显示器
– 游戏、电子玩具和机器人玩具
– 可穿戴设备(非医用)和智能追踪器
• 无线模块
– 楼宇安全系统–运动检测器、门窗传感器、玻
璃破裂探测器、紧急按钮、电子智能锁和IP 网
络摄像头
– 无线第三方模块
– 无线通信模块
– HVAC 系统–恒温器、环境传感器和HVAC 控
制器
3 说明
SimpleLink™ CC1311P3 器件是一款多协议 Sub-1GHz 无线微控制器 (MCU),支持以下协议:IEEE 802.15.4g、
支持 IPv6 的智能对象 (6LoWPAN)、mioty、专有系统(包括 TI 15.4-Stack (Sub-1GHz))。CC1311P3 基于
Arm® Cortex® M4 主处理器,针对电网基础设施、楼宇自动化、零售自动化、个人电子产品和医疗应用中的低功
耗无线通信和高级传感功能进行了优化。
CC1311P3 具有由 Arm® Cortex® M0 驱动的软件定义无线电,支持多个物理层和射频标准。该器件支持在
143MHz 至 176MHz、287MHz 至 351MHz、359MHz 至 527MHz、861MHz 至 1054MHz、1076MHz 至
1315MHz 频带内运行。CC1311P3 具有高效的内置PA,支持 +14dBm TX (24.9mA) 和+20dBm TX (65mA)。在
RX 中且在数据速率为 2.5kbps 的SimpleLink™ 远距离模式下,该器件具有 -121dBm 的灵敏度和 88dB 的屏蔽性
能(±10MHz)。
在保持32KB RAM 时,CC1311P3 具有0.7μA 的低待机电流。
许多客户对产品生命周期的要求为10 至15 年或者更久,为了达到这一目标,TI 制定了产品生命周期政策,对产
品的寿命和供货连续性作出承诺。
CC1311P3 器件是 SimpleLink™ MCU 平台的一部分,包括 Wi-Fi®、低功耗 Bluetooth®、Thread、Zigbee、Wi-
SUN®、Amazon Sidewalk、mioty、Sub-1GHz MCU 和主机 MCU。 CC1311P3 是可扩展产品系列(闪存为
32KB 至 704KB)的一部分,具有引脚对引脚兼容的封装选项。通用 SimpleLink™ CC13xx 和 CC26xx 软件开发
套件(SDK) 及SysConfig 系统配置工具支持产品系列中各器件之间的迁移。SDK 随附了丰富的软件栈、应用示例
和SimpleLink™ Academy 培训课程。如需了解更多相关信息,请查看无线连接。
器件信息
器件型号(1)
CC1311P31T0RGZR
封装尺寸(标称值)
封装
VQFN (48)
7.00mm × 7.00mm
(1) 如需所有可用器件的最新器件、封装和订购信息,请参阅节12 中的“封装选项附录”或访问TI 网站。
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4 功能方框图
RF Core
cJTAG
Main CPU
40KB
ROM
ADC
ADC
Arm® Cortex®-M4
Processor
352KB
Flash
Digital PLL
with 8KB
Cache
DSP Modem
48 MHz
SRAM
ROM
Arm® Cortex®-M0
Processor
32KB
SRAM
General Hardware Peripherals and Modules
I2C
4× 32-bit Timers
8-bit DAC
UART
SSI (SPI)
Watchdog Timer
32 ch. µDMA
RTC
12-bit ADC, 200 ks/s
Low-Power Comparator
Time-to-Digital Converter
I2S
26 GPIOs
AES & TRNG
Temperature and
Battery Monitor
LDO, Clocks, and References
Optional DC/DC Converter
图4-1. CC1311P3 功能方框图
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Table of Contents
8.17 Timing and Switching Characteristics..................... 22
8.18 Peripheral Characteristics.......................................25
8.19 Typical Characteristics............................................31
9 Detailed Description......................................................40
9.1 Overview...................................................................40
9.2 System CPU............................................................. 40
9.3 Radio (RF Core)........................................................41
9.4 Memory.....................................................................43
9.5 Cryptography............................................................ 44
9.6 Timers....................................................................... 45
9.7 Serial Peripherals and I/O.........................................46
9.8 Battery and Temperature Monitor............................. 46
9.9 µDMA........................................................................46
9.10 Debug..................................................................... 46
9.11 Power Management................................................47
9.12 Clock Systems........................................................ 48
9.13 Network Processor..................................................48
10 Application, Implementation, and Layout................. 49
10.1 Reference Designs................................................. 49
11 Device and Documentation Support..........................50
11.1 Device Nomenclature..............................................50
11.2 Tools and Software..................................................51
11.3 Documentation Support.......................................... 53
11.4 支持资源..................................................................53
11.5 Trademarks............................................................. 53
11.6 Electrostatic Discharge Caution..............................54
11.7 术语表..................................................................... 54
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 2
3 说明................................................................................... 2
4 功能方框图.........................................................................3
5 Revision History.............................................................. 4
6 Device Comparison.........................................................5
7 Pin Configuration and Functions...................................6
7.1 Pin Diagram –RGZ Package (Top View)..................6
7.2 Signal Descriptions –RGZ Package.........................7
7.3 Connections for Unused Pins and Modules................8
8 Specifications.................................................................. 9
8.1 Absolute Maximum Ratings........................................ 9
8.2 ESD Ratings............................................................... 9
8.3 Recommended Operating Conditions.........................9
8.4 Power Supply and Modules........................................ 9
8.5 Power Consumption - Power Modes........................ 10
8.6 Power Consumption - Radio Modes......................... 11
8.7 Nonvolatile (Flash) Memory Characteristics............. 11
8.8 Thermal Resistance Characteristics......................... 11
8.9 RF Frequency Bands................................................12
8.10 861 MHz to 1054 MHz - Receive (RX)....................13
8.11 861 MHz to 1054 MHz - Transmit (TX) .................. 16
8.12 861 MHz to 1054 MHz - PLL Phase Noise
Wideband Mode.......................................................... 17
8.13 861 MHz to 1054 MHz - PLL Phase Noise
Narrowband Mode.......................................................18
8.14 359 MHz to 527 MHz - Receive (RX)......................19
8.15 359 MHz to 527 MHz - Transmit (TX) .................... 21
8.16 359 MHz to 527 MHz - PLL Phase Noise............... 21
Information.................................................................... 55
5 Revision History
注:以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
March 2022
*
Initial Release
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6 Device Comparison
RADIO SUPPORT
PACKAGE SIZE
FLASH
(KB)
RAM +
Cache (KB)
Device
GPIO
CC1310
CC1311R3
CC1311P3
CC1312R
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32-128
352
352
352
704
352
352
704
128
352
352
352
352
352
352
704
352
704
16-20 + 8 10-30
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32 + 8
32 + 8
80 + 8
144 + 8
80 + 8
80 + 8
144 + 8
20 + 8
80 + 8
80 + 8
32 + 8
32 + 8
80 + 8
80 + 8
144 + 8
80 + 8
144 + 8
22-30
26
X
X
X
30
CC1312R7
CC1352R
X
X
X
X
X
X
X
X
X
X
30
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
28
CC1352P
X
X
26
CC1352P7
CC2640R2F
CC2642R
26
10-31
31
X
X
CC2642R-Q1
CC2651R3
CC2651P3
CC2652R
31
X
X
X
X
X
X
X
X
X
X
X
X
X
X
23-31
22-26
31
X
X
X
X
X
X
X
X
X
X
X
X
X
CC2652RB
CC2652R7
CC2652P
31
31
X
X
26
CC2652P7
26
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7 Pin Configuration and Functions
7.1 Pin Diagram –RGZ Package (Top View)
NC
NC
1
2
3
4
5
6
7
8
9
36 DIO_23
35 RESET_N
34 VDDS_DCDC
33 DCDC_SW
32 DIO_22
RF_P
RF_N
TX_20DBM_P
TX_20DBM_N
RX_TX
31 DIO_21
30 DIO_20
X32K_Q1
X32K_Q2
29 DIO_19
28 DIO_18
DIO_5 10
DIO_6 11
DIO_7 12
27 DIO_17
26 DIO_16
25 JTAG_TCKC
图7-1. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)
The following I/O pins marked in 图7-1 in bold have high-drive capabilities:
• Pin 10, DIO_5
• Pin 11, DIO_6
• Pin 12, DIO_7
• Pin 24, JTAG_TMSC
• Pin 26, DIO_16
• Pin 27, DIO_17
The following I/O pins marked in 图7-1 in italics have analog capabilities:
• Pin 36, DIO_23
• Pin 37, DIO_24
• Pin 38, DIO_25
• Pin 39, DIO_26
• Pin 40, DIO_27
• Pin 41, DIO_28
• Pin 42, DIO_29
• Pin 43, DIO_30
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7.2 Signal Descriptions –RGZ Package
表7-1. Signal Descriptions –RGZ Package
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
33
23
10
11
12
14
15
16
17
18
19
20
21
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
DCDC_SW
DCOUPL
DIO_5
Power
Power
Output from internal DC/DC converter(1)
—
For decoupling of internal 1.27 V regulated digital-supply (2)
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Digital
GPIO, high-drive capability
DIO_6
Digital
GPIO, high-drive capability
DIO_7
Digital
GPIO, high-drive capability
DIO_8
Digital
GPIO
DIO_9
Digital
GPIO
DIO_10
DIO_11
DIO_12
DIO_13
DIO_14
DIO_15
DIO_16
DIO_17
DIO_18
DIO_19
DIO_20
DIO_21
DIO_22
DIO_23
DIO_24
DIO_25
DIO_26
DIO_27
DIO_28
DIO_29
DIO_30
EGP
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO, JTAG_TDO, high-drive capability
GPIO, JTAG_TDI, high-drive capability
GPIO
Digital
Digital
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
GND
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
Ground –exposed ground pad(3)
JTAG TMSC, high-drive capability
JTAG TCKC
—
24
25
35
—
I/O
I
JTAG_TMSC
JTAG_TCKC
RESET_N
Digital
Digital
I
Digital
Reset, active low. No internal pullup resistor
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RF_P
RF_N
3
4
RF
RF
—
—
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RX_TX
7
5
6
RF
RF
RF
Optional bias pin for the RF LNA
Positive high-power TX signal
Negative high-power TX signal
—
—
—
TX_20DBM_P
TX_20DBM_N
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO(2) (4) (6)
VDDR
45
Power
—
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO(2) (5) (6)
VDDR_RF
VDDS
48
44
Power
Power
—
—
1.8-V to 3.8-V main chip supply(1)
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表7-1. Signal Descriptions –RGZ Package (continued)
PIN
NAME
I/O
TYPE
DESCRIPTION
NO.
13
22
34
46
47
8
VDDS2
Power
Power
Power
Analog
Analog
Analog
Analog
1.8-V to 3.8-V DIO supply(1)
—
—
—
—
—
—
—
VDDS3
1.8-V to 3.8-V DIO supply(1)
VDDS_DCDC
X48M_N
1.8-V to 3.8-V DC/DC converter supply
48-MHz crystal oscillator pin 1
48-MHz crystal oscillator pin 2
32-kHz crystal oscillator pin 1
32-kHz crystal oscillator pin 2
X48M_P
X32K_Q1
X32K_Q2
9
(1) For more details, see the device technical reference manual listed in 节11.3.
(2) Do not supply external circuitry from this pin.
(3) EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is
imperative for proper device operation.
(4) If internal DC/DC converter is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO.
(6) Output from internal DC/DC and LDO is trimmed to 1.68 V.
7.3 Connections for Unused Pins and Modules
表7-2. Connections for Unused Pins –RGZ Package
PREFERRED
FUNCTION
SIGNAL NAME
PIN NUMBER
ACCEPTABLE PRACTICE(1)
PRACTICE(1)
10–12
14–21
26–32
36–43
GPIO
DIO_n
NC or GND
NC
X32K_Q1
X32K_Q2
NC
8
9
32.768-kHz crystal
No Connects
NC or GND
NC
NC
NC
NC
NC
1–2
33
DCDC_SW
VDDS_DCDC
DC/DC converter(2)
34
VDDS
VDDS
(1) NC = No connect
(2) When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still
be connected and the 22 uF DCDC capacitor must be kept on the VDDR net.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX UNIT
VDDS(3)
Supply voltage
4.1
V
V
V
Voltage on any digital pin(4) (5)
VDDS + 0.3, max 4.1
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P
Voltage scaling enabled
VDDR + 0.3, max 2.25
VDDS
1.49
Vin
Voltage on ADC input
Voltage scaling disabled, internal reference
Voltage scaling disabled, VDDS as reference
V
VDDS / 2.9
10
Input level, RF pins (RF_P and RF_N)
Storage temperature
dBm
°C
Tstg
150
–40
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
(2) All voltage values are with respect to ground, unless otherwise noted.
(3) VDDS_DCDC, VDDS2 and VDDS3 must be at the same potential as VDDS.
(4) Including analog capable DIOs.
(5) Injection current is not supported on any GPIO pin
8.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1)
Charged device model (CDM), per JESD22-C101(2)
All pins
All pins
VESD
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
105
115
3.8
UNIT
°C
Operating ambient temperature(1) (2)
–40
Operating junction temperature(1) (2)
°C
–40
Operating supply voltage (VDDS)
1.8
2.1
V
Operating supply voltage (VDDS), boost mode
VDDR = 1.95 V
3.8
V
+14 dBm RF output sub-1 GHz power amplifier
Operating supply voltage (VDDS), boost mode
Rising supply voltage slew rate
+20 dBm RF output high power amplifier
3.3
0
3.8
100
20
V
mV/µs
mV/µs
Falling supply voltage slew rate(3)
0
(1) Operation at or near maximum operating temperature for extended durations will result in lifetime reduction.
(2) For thermal resistance characteristics refer to 节8.8.
(3) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used
to ensure compliance with this slew rate.
8.4 Power Supply and Modules
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VDDS Power-on-Reset (POR) threshold
VDDS Brown-out Detector (BOD) (1)
MIN
TYP
1.1 - 1.55
1.77
MAX
UNIT
V
V
V
Rising threshold
Rising threshold
VDDS Brown-out Detector (BOD), before initial boot (2)
1.70
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
VDDS Brown-out Detector (BOD) (1)
Falling threshold
1.75
V
(1) For boost mode (VDDR =1.95 V), TI drivers software initialization will trim VDDS BOD limits to maximum (approximately 2.0 V)
(2) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin
8.5 Power Consumption - Power Modes
When measured on the CC1311-P3EM-7XD7793-PA915 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC
enabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
TYP
UNIT
Core Current Consumption
Reset. RESET_N pin asserted or VDDS below power-on-reset threshold
Shutdown. No clocks running, no retention
115
115
Reset and Shutdown
nA
RTC running, CPU, 32KB RAM and (partial) register retention.
RCOSC_LF
0.7
0.8
µA
µA
µA
µA
µA
mA
Standby
without cache retention
RTC running, CPU, 32KB RAM and (partial) register retention
XOSC_LF
RTC running, CPU, 32KB RAM and (partial) register retention.
RCOSC_LF
Icore
2.1
Standby
with cache retention
RTC running, CPU, 32KB RAM and (partial) register retention.
XOSC_LF
2.2
Supply Systems and RAM powered
RCOSC_HF
Idle
570
2.50
MCU running CoreMark at 48 MHz
RCOSC_HF
Active
Peripheral Current Consumption
Peripheral power
domain
Delta current with domain enabled
Delta current with domain enabled
47.0
3.3
Serial power domain
RF Core
Delta current with power domain enabled,
clock enabled, RF core idle
122
µDMA
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle(1)
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
58.1
87.0
11.6
25.8
61.3
125
Timers
Iperi
µA
I2C
I2S
SSI
UART
CRYPTO (AES)
TRNG
25.2
23.3
(1) Only one GPTimer running
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8.6 Power Consumption - Radio Modes
When measured on the CC1311-P3EM-7XD7793-PA915 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC
enabled unless otherwise noted.
High power PA connected to VDDS unless otherwise noted.
Using boost mode (increasing VDDR up to 1.95 V), will increase system current by 15% (does not apply to TX +14 dBm
setting where this current is already included).
Relevant Icore and Iperi currents are included in below numbers.
PARAMETER
TEST CONDITIONS
TYP UNIT
Radio receive current, 868 MHz
5.4
7.4
mA
mA
0 dBm output power setting
868 MHz
Radio transmit current
Regular PA
+10 dBm output power setting
868 MHz
13.9
24.9
65
mA
mA
mA
Radio transmit current
Boost mode, regular PA
+14 dBm output power setting
868 MHz
Radio transmit current
High-power PA
Transmit (TX), +20 dBm output power setting
915 MHz, VDDS = 3.3 V
8.7 Nonvolatile (Flash) Memory Characteristics
Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Flash sector size
8
KB
Supported flash erase cycles before failure, full bank(1) (5)
Supported flash erase cycles before failure, single sector(2)
30
60
k Cycles
k Cycles
Maximum number of write operations per row before sector
erase(3)
Write
Operations
83
Flash retention
105 °C
11.4
Years
mA
ms
Flash sector erase current
Average delta current
Zero cycles
9.7
10
Flash sector erase time(4)
30k cycles
4000
ms
Flash write current
Flash write time(4)
Average delta current, 4 bytes at a time
4 bytes at a time
5.3
mA
µs
21.6
(1) A full bank erase is counted as a single erase cycle on each sector.
(2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k
cycles
(3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per
write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum
number of write operations per row is reached.
(4) This number is dependent on Flash aging and increases over time and erase cycles
(5) Aborting flash during erase or program modes is not a safe operation.
8.8 Thermal Resistance Characteristics
PACKAGE
RGZ
THERMAL METRIC(1)
UNIT
(VQFN)
48 PINS
25.0
14.5
8.7
RθJA
Junction-to-ambient thermal resistance
°C/W(2)
°C/W(2)
°C/W(2)
°C/W(2)
°C/W(2)
°C/W(2)
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJT
8.6
ψJB
RθJC(bot)
2.1
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.
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8.9 RF Frequency Bands
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
MIN
1076
861
431
359
287
143
TYP
MAX
UNIT
1315
1054
527
Frequency bands
MHz
439
351
176
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8.10 861 MHz to 1054 MHz - Receive (RX)
When measured on CC1311-P3EM-7XD7793-PA915 with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
General Parameters
Digital channel filter programmable receive
bandwidth
4
4000
kHz
Data rate step size
1.5
< -57
< -47
bps
dBm
dBm
Spurious emissions 25 MHz to 1 GHz
Spurious emissions 1 GHz to 13 GHz
868 MHz
Conducted emissions measured according to ETSI EN 300 220
IEEE 802.15.4, 50 kbps, ±25 kHz Deviation, 2-GFSK, 100 kHz RX Bandwidth
Sensitivity
BER = 10–2, 868 MHz
BER = 10–2, 868 MHz
BER = 10–2, 868 MHz(1)
BER = 10–2, 868 MHz(1)
BER = 10–2, 868 MHz(1)
BER = 10–2, 868 MHz(1)
BER = 10–2, 868 MHz(1)
BER = 10–2, 868 MHz(1)
dBm
dBm
dB
–110
10
Saturation limit
Selectivity, ±200 kHz
Selectivity, ±400 kHz
Blocking, ±1 MHz
Blocking, ±2 MHz
Blocking, ±5 MHz
Blocking, ±10 MHz
44
48
dB
58
dB
62
dB
70
dB
77
dB
Image rejection (image compensation
enabled)
BER = 10–2, 868 MHz(1)
41
dB
RSSI dynamic range
RSSI accuracy
Starting from the sensitivity limit
95
±3
dB
dB
Starting from the sensitivity limit across the given dynamic range
100 kbps, ±25 kHz Deviation, 2-GFSK, 137 kHz RX Bandwidth
Sensitivity 100 kbps
Selectivity, ±200 kHz
Selectivity, ±400 kHz
Co-channel rejection
1% PER, 127 byte payload, 868 MHz
-104
31
dBm
dB
1% PER, 127 byte payload, 868 MHz. Wanted signal at -96 dBm
1% PER, 127 byte payload, 868 MHz. Wanted signal at -96 dBm
1% PER, 127 byte payload, 868 MHz. Wanted signal at -79 dBm
37
dB
-9
dB
200 kbps, ±50 kHz Deviation, 2-GFSK, 311 kHz RX Bandwidth
Sensitivity
Sensitivity
BER = 10–2, 868 MHz
BER = 10–2, 915 MHz
dBm
dBm
–103
–102
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity
limit.
Selectivity, ±400 kHz
Selectivity, ±800 kHz
Blocking, ±2 MHz
45
49
57
69
dB
dB
dB
dB
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity
limit.
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity
limit.
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity
limit.
Blocking, ±10 MHz
500 kbps, ±190 kHz Deviation, 2-GFSK, 1150 kHz RX Bandwidth
Sensitivity 500 kbps
Selectivity, ±1 MHz
Selectivity, ±2 MHz
Co-channel rejection
1% PER, 127 byte payload, 915 MHz
-94
14
42
-9
dBm
dB
1% PER, 127 byte payload, 915 MHz. Wanted signal at -88 dBm
1% PER, 127 byte payload, 915 MHz. Wanted signal at -88 dBm
1% PER, 127 byte payload, 915 MHz. Wanted signal at -71 dBm
dB
dB
1 Mbps, ±350 kHz Deviation, 2-GFSK, 1.3 MHz RX Bandwidth
Sensitivity
Sensitivity
BER = 10–2, 868 MHz
BER = 10–2, 915 MHz
-97
-96
dBm
dBm
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity
limit.
Blocking, +2 MHz
Blocking, -2 MHz
Blocking, +10 MHz
43
26
54
dB
dB
dB
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity
limit.
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity
limit.
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When measured on CC1311-P3EM-7XD7793-PA915 with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity
limit.
Blocking, -10 MHz
48
dB
SimpleLink™ Long Range, 2.5/5 kbps (20 ksps), ±5 kHz Deviation, 2-GFSK, 34 kHz RX Bandwidth, FEC = 1:2, DSSS = 1:4/1:2
Sensitivity
2.5 kbps, BER = 10–2, 868 MHz
5 kbps, BER = 10–2, 868 MHz
-121
-119
10
dBm
dBm
dBm
dB
Sensitivity
Saturation limit
2.5 kbps, BER = 10–2, 868 MHz
2.5 kbps, BER = 10–2, 868 MHz(1)
2.5 kbps, BER = 10–2, 868 MHz(1)
2.5 kbps, BER = 10–2, 868 MHz(1)
2.5 kbps, BER = 10–2, 868 MHz(1)
2.5 kbps, BER = 10–2, 868 MHz(1)
2.5 kbps, BER = 10–2, 868 MHz(1)
2.5 kbps, BER = 10–2, 868 MHz(1)
Selectivity, ±100 kHz
Selectivity, ±200 kHz
Selectivity, ±300 kHz
Blocking, ±1 MHz
Blocking, ±2 MHz
Blocking, ±5 MHz
Blocking, ±10 MHz
49
50
dB
51
dB
63
dB
69
dB
79
dB
88
dB
Image rejection (image compensation
enabled)
2.5 kbps, BER = 10–2, 868 MHz(1)
47
dB
RSSI dynamic range
RSSI accuracy
Starting from the sensitivity limit
97
±3
dB
dB
Starting from the sensitivity limit across the given dynamic range
Narrowband, 9.6 kbps, ±2.4 kHz Deviation, 2-GFSK, 17.1 kHz RX Bandwidth
Sensitivity
BER = 10–2, 868 MHz
-117
41
dBm
dB
BER = 10–2, 868 MHz. Wanted signal 3 dB above the ETSI
reference sensitivity limit (-104.6 dBm). Interferer ±20 kHz
Adjacent Channel Rejection
BER = 10–2, 868 MHz. Wanted signal 3 dB above the ETSI
reference sensitivity limit (-104.6 dBm). Interferer ±40 kHz
Alternate Channel Rejection
Blocking, ±1 MHz
42
65
70
85
dB
dB
dB
dB
BER = 10–2, 868 MHz. Wanted signal 3 dB above the ETSI
reference sensitivity limit (-104.6 dBm).
BER = 10–2, 868 MHz. Wanted signal 3 dB above the ETSI
reference sensitivity limit (-104.6 dBm).
Blocking, ±2 MHz
BER = 10–2, 868 MHz. Wanted signal 3 dB above the ETSI
reference sensitivity limit (-104.6 dBm).
Blocking, ±10 MHz
Wi-SUN, 2-GFSK
Sensitivity
50 kbps, ±12.5 kHz deviation, 2-GFSK, 68 kHz RX Bandwidth,
868 MHz, 10% PER, 250 byte payload
-107
30
dBm
dB
50 kbps, ±12.5 kHz deviation, 2-GFSK, 68 kHz RX Bandwidth,
868.3 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
Selectivity, ±100 kHz, 50 kbps, ±12.5 kHz
deviation, 2-GFSK, 868.3 MHz
50 kbps, ±12.5 kHz deviation, 2-GFSK, 68 kHz RX Bandwidth,
868.3 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
Selectivity, ±200 kHz, 50 kbps, ±12.5 kHz
deviation, 2-GFSK, 868.3 MHz
36
-106
34
dB
dBm
dB
50 kbps, ±25 kHz deviation, 2-GFSK, 98 kHz RX Bandwidth,
918.2 MHz, 10% PER, 250 byte payload
Sensitivity
50 kbps, ±25 kHz deviation, 2-GFSK, 98 kHz RX Bandwidth,
918.2 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
Selectivity, ±200 kHz, 50 kbps, ±25 kHz
deviation, 2-GFSK, 918.2 MHz
50 kbps, ±25 kHz deviation, 2-GFSK, 98 kHz RX Bandwidth,
918.2 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
Selectivity, ±400 kHz, 50 kbps, ±25 kHz
deviation, 2-GFSK, 918.2 MHz
41
-104
37
dB
dBm
dB
100 kbps, ±25 kHz deviation, 2-GFSK, 135 kHz RX Bandwidth,
868 MHz, 10% PER, 250 byte payload
Sensitivity
100 kbps, ±25 kHz deviation, 2-GFSK, 135 kHz RX Bandwidth,
868.3 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
Selectivity, ±200 kHz, 100 kbps, ±25 kHz
deviation, 2-GFSK, 868.3 MHz
100 kbps, ±25 kHz deviation, 2-GFSK, 135 kHz RX Bandwidth,
868.3 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
Selectivity, ±400 kHz, 100 kbps, ±25 kHz
deviation, 2-GFSK, 868.3 MHz
45
dB
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When measured on CC1311-P3EM-7XD7793-PA915 with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
100 kbps, ±50 kHz deviation, 2-GFSK, 196 kHz RX Bandwidth,
920.9 MHz, 10% PER, 250 byte payload
Sensitivity
-102
dBm
100 kbps, ±50 kHz deviation, 2-GFSK, 196 kHz RX Bandwidth,
920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
Selectivity, ±400 kHz, 100 kbps, ±50 kHz
deviation, 2-GFSK, 920.9 MHz
40
dB
100 kbps, ±50 kHz deviation, 2-GFSK, 196 kHz RX Bandwidth,
920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
Selectivity, ±800 kHz, 100 kbps, ±50 kHz
deviation, 2-GFSK, 920.9 MHz
49
-99
41
dB
dBm
dB
150 kbps, ±37.5 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth,
920.9 MHz, 10% PER, 250 byte payload
Sensitivity
150 kbps, ±37.5 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth,
920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
Selectivity, ±400 kHz, 150 kbps, ±37.5 kHz
deviation, 2-GFSK, 920.9 MHz
150 kbps, ±37.5 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth,
920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
Selectivity, ±800 kHz, 150 kbps, ±37.5 kHz
deviation, 2-GFSK, 920.9 MHz
47
-99
42
dB
dBm
dB
200 kbps, ±50 kHz deviation, 2-GFSK, 918.4 MHz, 273 kHz RX
BW, 10% PER, 250 byte payload
Sensitivity
200 kbps, ±50 kHz deviation, 2-GFSK, 273 kHz RX
Bandwidth, 918.4 MHz, 10% PER, 250 byte payload. Wanted
signal 3 dB above sensitivity level
Selectivity, ±400 kHz, 200 kbps, ±50 kHz
deviation, 2-GFSK, 918.4 MHz
200 kbps, ±50 kHz deviation, 2-GFSK, 273 kHz RX
Bandwidth, 918.4 MHz, 10% PER, 250 byte payload. Wanted
signal 3 dB above sensitivity level
Selectivity, ±800 kHz, 200 kbps, ±50 kHz
deviation, 2-GFSK, 918.4 MHz
49
-99
45
dB
dBm
dB
200 kbps, ±100 kHz deviation, 2-GFSK, 273 kHz RX
Bandwidth, 920.8 MHz, 10% PER, 250 byte payload
Sensitivity
200 kbps, ±100 kHz deviation, 2-GFSK, 273 kHz RX
Bandwidth, 920.8 MHz, 10% PER, 250 byte payload. Wanted
signal 3 dB above sensitivity level
Selectivity, ±600 kHz, 200 kbps, ±100 kHz
deviation, 2-GFSK, 920.8 MHz
200 kbps, ±100 kHz deviation, 2-GFSK, 273 kHz RX
Bandwidth, 920.8 MHz, 10% PER, 250 byte payload. Wanted
signal 3 dB above sensitivity level
Selectivity, ±1200 kHz, 200 kbps, ±100 kHz
deviation, 2-GFSK, 920.8 MHz
52
-97
42
dB
dBm
dB
300 kbps, ±75 kHz deviation, 2-GFSK, 917.6 MHz, 498 kHz RX
BW, 10% PER, 250 byte payload
Sensitivity
300 kbps, ±75 kHz deviation, 2-GFSK, 498 kHz RX Bandwidth,
917.6 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
Selectivity, ±600 kHz, 300 kbps, ±75 kHz
deviation, 2-GFSK, 917.6 MHz
300 kbps, ±75 kHz deviation, 2-GFSK, 498 kHz RX Bandwidth,
917.6 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
Selectivity, ±1200 kHz, 300 kbps, ±75 kHz
deviation, 2-GFSK, 917.6 MHz
47
dB
(1) Wanted signal 3 dB above the reference sensitivity limit according to ETSI EN 300 220 v. 3.1.1
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8.11 861 MHz to 1054 MHz - Transmit (TX)
Measured on the CC1311-P3EM-7XD7793-PA915 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled and high power PA connected to VDDS using 2-GFSK, 50 kbps, ±25 kHz deviation unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
General parameters
VDDR = 1.95 V
Max output power, boost mode
Regular PA
Minimum supply voltage (VDDS ) for boost
mode is 2.1 V
14
dBm
868 MHz and 915 MHz
Max output power,
Regular PA
868 MHz and 915 MHz
13
20
24
6
dBm
dBm
dB
Max output power,
High power PA
915 MHz
VDDS = 3.3V
Output power programmable range
Regular PA
868 MHz and 915 MHz
Output power programmable range
High power PA
868 MHz and 915 MHz
VDDS = 3.3V
dB
+10 dBm setting
Over recommended temperature operating
range
Output power variation over temperature
Regular PA
±2
dB
dB
+14 dBm setting
Over recommended temperature operating
range
Output power variation over temperature
Boost mode, regular PA
±1.5
Spurious emissions and harmonics
+14 dBm setting
ETSI restricted bands
< -54
< -36
< -30
< -56
< -52
< -50
dBm
dBm
dBm
dBm
dBm
dBm
30 MHz to 1 GHz
Spurious emissions
(excluding harmonics)
Regular PA (2)
+14 dBm setting
ETSI outside restricted bands
1 GHz to 12.75 GHz
(outside ETSI restricted bands)
+14 dBm setting
measured in 1 MHz bandwidth (ETSI)
30 MHz to 88 MHz
(within FCC restricted bands)
+14 dBm setting
+14 dBm setting
+14 dBm setting
88 MHz to 216 MHz
(within FCC restricted bands)
Spurious emissions out-
of-band
216 MHz to 960 MHz
(within FCC restricted bands)
Regular PA, 915 MHz (2)
960 MHz to 2390 MHz and above
2483.5 MHz (within FCC restricted
band)
+14 dBm setting
<-42
dBm
1 GHz to 12.75 GHz
(outside FCC restricted bands)
+14 dBm setting
< -40
< -55
< -52
< -49
dBm
dBm
dBm
dBm
30 MHz to 88 MHz
(within FCC restricted bands)
+20 dBm setting, VDDS = 3.3 V
+20 dBm setting, VDDS = 3.3 V
+20 dBm setting, VDDS = 3.3 V
88 MHz to 216 MHz
(within FCC restricted bands)
Spurious emissions out-
of-band
High power PA, 915
216 MHz to 960 MHz
(within FCC restricted bands)
MHz(2) (3)
960 MHz to 2390 MHz and above
2483.5 MHz (within FCC restricted
band)
+20 dBm setting, VDDS = 3.3 V
+20 dBm setting, VDDS = 3.3 V
< -41
< -20
dBm
dBm
1 GHz to 12.75 GHz
(outside FCC restricted bands)
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Measured on the CC1311-P3EM-7XD7793-PA915 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled and high power PA connected to VDDS using 2-GFSK, 50 kbps, ±25 kHz deviation unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted. (1)
PARAMETER
TEST CONDITIONS
+14 dBm setting
MIN
TYP
MAX UNIT
Below 710 MHz
(ARIB T-108)
< -36
dBm
710 MHz to 900 MHz
(ARIB T-108)
+14 dBm setting
+14 dBm setting
+14 dBm setting
+14 dBm setting
+14 dBm setting
< -55
< -55
< -55
< -45
< -30
dBm
dBm
dBm
dBm
dBm
900 MHz to 915 MHz
(ARIB T-108)
Spurious emissions out-
of-band
Regular PA, 920.6/928
930 MHz to 1000 MHz
(ARIB T-108)
MHz (2)
1000 MHz to 1215 MHz
(ARIB T-108)
Above 1215 MHz
(ARIB T-108)
+14 dBm setting, 868 MHz
< -30
< -30
< -30
< -42
< -30
< -30
< -30
< -42
< -30
< -42
< -30
< -42
Second harmonic
Third harmonic
Fourth harmonic
Fifth harmonic
dBm
dBm
dBm
dBm
+14 dBm setting, 915 MHz
+14 dBm setting, 868 MHz
+14 dBm setting, 915 MHz
Harmonics
Regular PA
+14 dBm setting, 868 MHz
+14 dBm setting, 915 MHz
+14 dBm setting, 868 MHz
+14 dBm setting, 915 MHz
Second harmonic
Third harmonic
Fourth harmonic
Fifth harmonic
+20 dBm setting, VDDS = 3.3 V, 915 MHz
+20 dBm setting, VDDS = 3.3 V, 915 MHz
+20 dBm setting, VDDS = 3.3 V, 915 MHz
+20 dBm setting, VDDS = 3.3 V, 915 MHz
dBm
dBm
dBm
dBm
Harmonics
High power PA
Adjacent Channel Power
Adjacent channel power, Adjacent channel, 20 kHz offset. 9.6
regular 14 dBm PA kbps, h=0.5
12.5 dBm setting. 868.3 MHz. 14 kHz channel
BW
-23
-30
dBm
dBm
Alternate channel power, Alternate channel, 40 kHz offset. 9.6
regular 14 dBm PA kbps, h=0.5
12.5 dBm setting. 868.3 MHz. 14 kHz channel
BW
(1) Some combinations of frequency, data rate and modulation format requires use of external crystal load capacitors for regulatory
compliance. More details can be found in the device errata.
(2) Suitable for systems targeting compliance with EN 300 220, EN 303 131, EN 303 204, FCC CFR47 Part 15, ARIB STD-T108.
(3) Spurious emissions increase for supply voltages below 2.2 V. As such, care must be taken to ensure regulatory requirements are met
when operating at low supply voltage levels. An alternative is to use the Sub-1 GHz PA below 2.2 V.
8.12 861 MHz to 1054 MHz - PLL Phase Noise Wideband Mode
When measured on the CC1311-P3EM-7XD7793-PA915 reference design with Tc = 25 °C, VDDS = 3.0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±10 kHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–76
±100 kHz offset
±200 kHz offset
±400 kHz offset
±1000 kHz offset
±2000 kHz offset
±10000 kHz offset
–98
–106
–113
–122
–130
–140
Phase noise in the 868- and 915-MHz bands
20 kHz PLL loop bandwidth
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8.13 861 MHz to 1054 MHz - PLL Phase Noise Narrowband Mode
When measured on the CC1311-P3EM-7XD7793-PA915 reference design with Tc = 25 °C, VDDS = 3.0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±10 kHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–95
±100 kHz offset
±200 kHz offset
±400 kHz offset
±1000 kHz offset
±2000 kHz offset
±10000 kHz offset
–94
–94
Phase noise in the 868- and 915-MHz bands
150 kHz PLL loop bandwith
–103
–119
–129
–138
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8.14 359 MHz to 527 MHz - Receive (RX)
When measured on a CC1311-P3EM-7XD7793-PA915 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
General Parameters
Spurious emissions 25 MHz to 1 GHz
Spurious emissions 1 GHz to 13 GHz
< -57
< -47
dBm
dBm
433.92 MHz
Conducted emissions measured according to ETSI EN 300 220
IEEE 802.15.4, 50 kbps, ±25 kHz Deviation, 2-GFSK, 78 kHz RX Bandwidth
Sensitivity
BER = 10–2, 433.92 MHz
BER = 10–2, 433.92 MHz
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
dBm
dBm
dB
–110
10
Saturation limit
Selectivity, +200 kHz
Selectivity, -200 kHz
Selectivity, +400 kHz
Selectivity, -400 kHz
Blocking, +1 MHz
Blocking, -1 MHz
Blocking, +2 MHz
Blocking, -2 MHz
Blocking, +10 MHz
Blocking, -10 MHz
48
43
dB
53
dB
44
dB
60
dB
54
dB
62
dB
61
dB
75
dB
75
dB
Image rejection (image compensation
enabled)
BER = 10–2, 433.92 MHz(1)
44
dB
RSSI dynamic range
RSSI accuracy
Starting from the sensitivity limit
95
±3
dB
dB
Starting from the sensitivity limit across the given dynamic range
200 kbps, ±50 kHz Deviation, 2-GFSK, 273 kHz RX Bandwidth
Sensitivity
BER = 10–2, 433.92 MHz
dBm
dBm
dB
–104
10
Saturation limit
BER = 10–2, 433.92 MHz
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
Selectivity, ±400 kHz
Blocking, ±1 MHz
Blocking, ±2 MHz
Blocking, ±10 MHz
48
52
dB
55
dB
68
dB
Image rejection (image compensation
enabled)
BER = 10–2, 433.92 MHz(1)
45
dB
RSSI dynamic range
RSSI accuracy
Starting from the sensitivity limit
89
±3
dB
dB
Starting from the sensitivity limit across the given dynamic range
SimpleLink™ Long Range, 2.5/5 kbps (20 ksps), ±5 kHz Deviation, 2-GFSK, 34 kHz RX Bandwidth, FEC = 1:2, DSSS = 1:4/1:2
Sensitivity
2.5 kbps, BER = 10–2, 433.92 MHz
5 kbps, BER = 10–2, 433.92 MHz
5 kbps, BER = 10–2, 433.92 MHz
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
-121
-119
10
dBm
dBm
dBm
dB
Sensitivity
Saturation limit
Selectivity, +100 kHz
Selectivity, -100 kHz
Blocking, +1 MHz
Blocking, -1 MHz
Blocking, +2 MHz
Blocking, -2 MHz
Blocking, +10 MHz
Blocking, -10 MHz
55
53
dB
69
dB
65
dB
71
dB
70
dB
84
dB
84
dB
Image rejection (image compensation
enabled)
5 kbps, BER = 10–2, 433.92 MHz
Starting from the sensitivity limit
49
dB
dB
RSSI dynamic range
101
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When measured on a CC1311-P3EM-7XD7793-PA915 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RSSI accuracy
Starting from the sensitivity limit across the given dynamic range
±3
dB
(1) Wanted signal 3 dB above sensitivity limit
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8.15 359 MHz to 527 MHz - Transmit (TX)
Measured on the LAUNCHXL-CC1352P-4 reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless
otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
General parameters
Max output power,
Regular PA
433.92 MHz, without BOOST (VDDR = 1.7 V)
433.92 MHz, without BOOST (VDDR = 1.7 V)
13
24
dBm
dB
Output power programmable range
Regular PA
+13 dBm setting. 433.92 MHz
Over recommended temperature operating
range
Output power variation over temperature, regular PA
±1.5
dB
Spurious emissions and harmonics
+10 dBm setting
ETSI restricted bands
< -54
< -36
< -30
< -26
< -55
< -55
< -55
< -45
< -30
< -36
< -30
< -30
< -30
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
30 MHz to 1 GHz
Spurious emissions
+10 dBm setting
ETSI outside restricted bands
(excluding harmonics)
Regular PA (2)
1 GHz to 12.75 GHz
(outside ETSI restricted bands)
+10 dBm setting
measured in 1 MHz bandwidth (ETSI)
Outside the necessary requency band
(ARIB T-67)
+10 dBm setting
710 MHz to 900 MHz
(ARIB T-67)
+10 dBm setting
900 MHz to 915 MHz
+10 dBm setting
Spurious emissions out-
(ARIB T-67)
of-band
Regular PA, 429 MHz (2)
930 MHz to 1000 MHz
(ARIB T-67)
+10 dBm setting
1000 MHz to 1215 MHz
(ARIB T-67)
+10 dBm setting
Above 1215 MHz
(ARIB T-67)
+10 dBm setting
Harmonics
Regular PA
Second harmonic
Third harmonic
Fourth harmonic
Fifth harmonic
+13 dBm setting, 433 MHz
+13 dBm setting, 433 MHz
+13 dBm setting, 433 MHz
+13 dBm setting, 433 MHz
Harmonics
Regular PA
Harmonics
Regular PA
Harmonics
Regular PA
(1) Some combinations of frequency, data rate and modulation format requires use of external crystal load capacitors for regulatory
compliance. More details can be found in the device errata.
(2) Suitable for systems targeting compliance with EN 300 220, EN 303 131, EN 303 204, FCC CFR47 Part 15, ARIB STD-T108.
8.16 359 MHz to 527 MHz - PLL Phase Noise
When measured on the LAUNCHXL-CC1352P-4 reference design with Tc = 25 °C, VDDS = 3.0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
-82
MAX
UNIT
±10 kHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
±100 kHz offset
±200 kHz offset
±400 kHz offset
±1000 kHz offset
±2000 kHz offset
±10000 kHz offset
-105
-112
-119
-127
-133
-141
Phase noise in the 433 MHz band
20 kHz PLL loop bandwidth
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8.17 Timing and Switching Characteristics
8.17.1 Reset Timing
PARAMETER
MIN
TYP
MAX
UNIT
RESET_N low duration
1
µs
8.17.2 Wakeup Timing
Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not
include software overhead.
PARAMETER
TEST CONDITIONS
MIN
TYP
850 - 4000
850 - 4000
160
MAX
UNIT
MCU, Reset to Active(1)
µs
µs
µs
µs
µs
MCU, Shutdown to Active(1)
MCU, Standby to Active
MCU, Active to Standby
MCU, Idle to Active
36
14
(1) The wakeup time is dependent on remaining charge on VDDR capacitor when starting the device, and thus how long the device has
been in Reset or Shutdown before starting up again. The wake up time increases with a higher capacitor value.
8.17.3 Clock Specifications
8.17.3.1 48 MHz Crystal Oscillator (XOSC_HF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(1)
PARAMETER
MIN
TYP
MAX
UNIT
Crystal frequency
48
MHz
Equivalent series resistance
6 pF < CL ≤9 pF
ESR
ESR
20
60
80
Ω
Equivalent series resistance
5 pF < CL ≤ 6 pF
Ω
Motional inductance, relates to the load capacitance that is used for the crystal (CL
in Farads)(5)
2
LM
CL
< 3 × 10–25 / CL
H
Crystal load capacitance(4)
Start-up time(2)
5
7(3)
9
pF
µs
200
(1) Probing or otherwise stopping the crystal while the DC/DC converter is enabled may cause permanent damage to the device.
(2) Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.
(3) On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed
through software in the Customer Configuration section (CCFG).
(4) Adjustable load capacitance is integrated into the device. External load capacitors are required for systems targeting compliance with
certain regulations. See the device errata for further details.
(5) The crystal manufacturer's specification must satisfy this requirement for proper operation.
8.17.3.2 48 MHz RC Oscillator (RCOSC_HF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
MHz
%
Frequency
48
Uncalibrated frequency accuracy
Calibrated frequency accuracy(1)
Start-up time
±1
±0.25
5
%
µs
(1) Accuracy relative to the calibration source (XOSC_HF)
8.17.3.3 32.768 kHz Crystal Oscillator (XOSC_LF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
32.768
30
MAX
UNIT
kHz
kΩ
Crystal frequency
ESR
Equivalent series resistance
100
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Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
CL
Crystal load capacitance
6
7(1)
12
pF
(1) Default load capacitance using TI reference designs including parasitic capacitance. Crystals with different load capacitance may be
used.
8.17.3.4 32 kHz RC Oscillator (RCOSC_LF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
Calibrated frequency
Calibrated
32.8
kHz
RTC
Calibrated periodically against XOSC_HF(2)
±600(3)
50
ppm
variation(1)
Temperature coefficient.
ppm/°C
(1) When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time
Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This
functionality is available through the TI-provided Power driver.
(2) TI driver software calibrates the RTC every time XOSC_HF is enabled.
(3) Some device's variation can exceed 1000 ppm. Further calibration will not improve variation.
8.17.4 Synchronous Serial Interface (SSI) Characteristics
8.17.4.1 Synchronous Serial Interface (SSI) Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
PARAMETER
MIN
TYP
MAX
UNIT
NO.
S1
tclk_per
tclk_high
tclk_low
SSIClk cycle time
12
65024
System Clocks (2)
tclk_per
S2(1)
S3(1)
SSIClk high time
SSIClk low time
0.5
0.5
tclk_per
(1) Refer to SSI timing diagrams 图8-1, 图8-2, and 图8-3.
(2) When using the TI-provided Power driver, the SSI system clock is always 48 MHz.
S1
S2
SSIClk
S3
SSIFss
SSITx
MSB
LSB
SSIRx
4 to 16 bits
图8-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
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S2
S1
SSIClk
S3
SSIFss
SSITx
SSIRx
MSB
LSB
8-bit control
0
MSB
LSB
4 to 16 bits output data
图8-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer
S1
S2
SSIClk
(SPO = 0)
S3
SSIClk
(SPO = 1)
SSITx
(Master)
MSB
LSB
SSIRx
(Slave)
MSB
LSB
SSIFss
图8-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1
8.17.5 UART
8.17.5.1 UART Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
UART rate
3
MBaud
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8.18 Peripheral Characteristics
8.18.1 ADC
8.18.1.1 Analog-to-Digital Converter (ADC) Characteristics
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
Input voltage range
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
0
VDDS
12
Bits
ksps
LSB
LSB
LSB
LSB
Sample Rate
200
Offset
Internal 4.3 V equivalent reference(2)
–0.24
7.14
>–1
±4
Gain error
Internal 4.3 V equivalent reference(2)
DNL(4)
INL
Differential nonlinearity
Integral nonlinearity
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
9.8
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone, DC/DC enabled
9.8
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
10.1
Internal reference, voltage scaling disabled,
32 samples average (software), 200 kSamples/s, 300 Hz input
tone
ENOB
Effective number of bits
Bits
11.1
Internal reference, voltage scaling disabled,
11.3
11.6
14-bit mode, 200 kSamples/s, 300 Hz input tone (5)
Internal reference, voltage scaling disabled,
15-bit mode, 200 kSamples/s, 300 Hz input tone (5)
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
–65
–70
–72
THD
Total harmonic distortion
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
dB
dB
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
60
63
Signal-to-noise
and
distortion ratio
SINAD,
SNDR
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
Internal reference, voltage scaling disabled,
32 samples average (software), 200 kSamples/s, 300 Hz input
tone
68
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
70
73
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
SFDR
Spurious-free dynamic range
dB
Internal reference, voltage scaling disabled,
32 samples average (software), 200 kSamples/s, 300 Hz input
tone
75
Conversion time
Serial conversion, time-to-output, 24 MHz clock
Internal 4.3 V equivalent reference(2)
VDDS as reference
50
0.39
0.56
Clock Cycles
Current consumption
Current consumption
mA
mA
Equivalent fixed internal reference (input voltage scaling
enabled). For best accuracy, the ADC conversion should be
initiated through the TI-RTOS API in order to include the gain/
offset compensation factors stored in FCFG1
Reference voltage
4.3(2) (3)
V
Fixed internal reference (input voltage scaling disabled). For
best accuracy, the ADC conversion should be initiated through
the TI-RTOS API in order to include the gain/offset
compensation factors stored in FCFG1. This value is derived
from the scaled value (4.3 V) as follows:
Reference voltage
1.48
V
Vref = 4.3 V × 1408 / 4095
Reference voltage
Reference voltage
VDDS as reference, input voltage scaling enabled
VDDS as reference, input voltage scaling disabled
VDDS
V
V
VDDS /
2.82(3)
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8.18.1.1 Analog-to-Digital Converter (ADC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200 kSamples/s, voltage scaling enabled. Capacitive input,
Input impedance depends on sampling frequency and sampling
time
Input impedance
>1
MΩ
(1) Using IEEE Std 1241-2010 for terminology and test methods
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V
(3) Applied voltage must be within Absolute Maximum Ratings at all times
(4) No missing codes
(5) ADC_output = Σ(4n samples ) >> n, n = desired extra bits
8.18.2 DAC
8.18.2.1 Digital-to-Analog Converter (DAC) Characteristics
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
General Parameters
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
8
Bits
Any load, any VREF, pre-charge OFF, DAC charge-pump ON
1.8
2.0
3.8
3.8
External Load(4), any VREF, pre-charge OFF, DAC charge-pump
OFF
VDDS
Supply voltage
V
Any load, VREF = DCOUPL, pre-charge ON
Buffer ON (recommended for external load)
Buffer OFF (internal load)
2.6
16
16
3.8
250
FDAC
Clock frequency
kHz
1000
VREF = VDDS, buffer OFF, internal load
VREF = VDDS, buffer ON, external capacitive load = 20 pF(3)
13
13.8
20
Voltage output settling time
1 / FDAC
External capacitive load
External resistive load
Short circuit current
200
400
pF
MΩ
µA
10
VDDS = 3.8 V, DAC charge-pump OFF
VDDS = 3.0 V, DAC charge-pump ON
VDDS = 3.0 V, DAC charge-pump OFF
VDDS = 2.0 V, DAC charge-pump ON
VDDS = 2.0 V, DAC charge-pump OFF
VDDS = 1.8 V, DAC charge-pump ON
VDDS = 1.8 V, DAC charge-pump OFF
50.8
51.7
53.2
48.7
70.2
46.3
88.9
Max output impedance Vref =
VDDS, buffer ON, CLK 250
kHz
ZMAX
kΩ
Internal Load - Continuous Time Comparator / Low Power Clocked Comparator
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
FDAC = 250 kHz
Differential nonlinearity
Differential nonlinearity
±1
DNL
LSB(1)
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
±1.2
FDAC = 16 kHz
VREF = VDDS = 3.8 V
±0.64
±0.81
±1.27
±3.43
±2.88
±2.37
VREF = VDDS= 3.0 V
Offset error(2)
Load = Continuous Time
Comparator
VREF = VDDS = 1.8 V
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
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8.18.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.78
±0.77
±3.46
±3.44
±4.70
±4.11
±1.53
±1.71
±2.10
±6.00
±3.85
±5.84
±2.92
±3.06
±3.91
±7.84
±4.06
±6.94
0.03
MAX
UNIT
VREF = VDDS= 3.8 V
VREF = VDDS = 3.0 V
VREF = VDDS= 1.8 V
Offset error(2)
Load = Low Power Clocked
Comparator
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS = 3.8 V
VREF = VDDS = 3.0 V
Max code output voltage
variation(2)
Load = Continuous Time
Comparator
VREF = VDDS= 1.8 V
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS= 3.8 V
VREF =VDDS= 3.0 V
Max code output voltage
variation(2)
Load = Low Power Clocked
Comparator
VREF = VDDS= 1.8 V
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS = 3.8 V, code 1
VREF = VDDS = 3.8 V, code 255
VREF = VDDS= 3.0 V, code 1
VREF = VDDS= 3.0 V, code 255
VREF = VDDS= 1.8 V, code 1
VREF = VDDS = 1.8 V, code 255
VREF = DCOUPL, pre-charge OFF, code 1
VREF = DCOUPL, pre-charge OFF, code 255
VREF = DCOUPL, pre-charge ON, code 1
VREF = DCOUPL, pre-charge ON, code 255
VREF = ADCREF, code 1
3.62
0.02
2.86
0.01
Output voltage range(2)
Load = Continuous Time
Comparator
1.71
V
0.01
1.21
1.27
2.46
0.01
VREF = ADCREF, code 255
1.41
VREF = VDDS = 3.8 V, code 1
VREF = VDDS= 3.8 V, code 255
VREF = VDDS= 3.0 V, code 1
VREF = VDDS= 3.0 V, code 255
VREF = VDDS = 1.8 V, code 1
VREF = VDDS = 1.8 V, code 255
VREF = DCOUPL, pre-charge OFF, code 1
VREF = DCOUPL, pre-charge OFF, code 255
VREF = DCOUPL, pre-charge ON, code 1
VREF = DCOUPL, pre-charge ON, code 255
VREF = ADCREF, code 1
0.03
3.61
0.02
2.85
0.01
Output voltage range(2)
Load = Low Power Clocked
Comparator
1.71
V
0.01
1.21
1.27
2.46
0.01
VREF = ADCREF, code 255
1.41
External Load (Keysight 34401A Multimeter)
VREF = VDDS, FDAC = 250 kHz
±1
±1
±1
±1
INL
Integral nonlinearity
VREF = DCOUPL, FDAC = 250 kHz
VREF = ADCREF, FDAC = 250 kHz
VREF = VDDS, FDAC = 250 kHz
LSB(1)
LSB(1)
DNL
Differential nonlinearity
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8.18.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.20
±0.25
±0.45
±1.55
±1.30
±1.10
±0.60
±0.55
±0.60
±3.45
±2.10
±1.90
0.03
MAX
UNIT
VREF = VDDS= 3.8 V
VREF = VDDS= 3.0 V
VREF = VDDS = 1.8 V
Offset error
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS= 3.8 V
VREF = VDDS= 3.0 V
VREF = VDDS= 1.8 V
Max code output voltage
variation
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS = 3.8 V, code 1
VREF = VDDS = 3.8 V, code 255
VREF = VDDS = 3.0 V, code 1
VREF = VDDS= 3.0 V, code 255
VREF = VDDS= 1.8 V, code 1
VREF = VDDS = 1.8 V, code 255
VREF = DCOUPL, pre-charge OFF, code 1
VREF = DCOUPL, pre-charge OFF, code 255
VREF = DCOUPL, pre-charge ON, code 1
VREF = DCOUPL, pre-charge ON, code 255
VREF = ADCREF, code 1
3.61
0.02
2.85
0.02
Output voltage range
Load = Low Power Clocked
Comparator
1.71
V
0.02
1.20
1.27
2.46
0.02
VREF = ADCREF, code 255
1.42
(1) 1 LSB (VREF 3.8 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 14.10 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV
(2) Includes comparator offset
(3) A load > 20 pF will increases the settling time
(4) Keysight 34401A Multimeter
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8.18.3 Temperature and Battery Monitor
8.18.3.1 Temperature Sensor
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
°C
Resolution
Accuracy
Accuracy
2
-40 °C to 0 °C
0 °C to 105 °C
±4.0
±2.5
3.9
°C
°C
Supply voltage coefficient(1)
°C/V
(1) The temperature sensor is automatically compensated for VDDS variation when using the TI-provided driver.
8.18.3.2 Battery Monitor
Measured on a Texas Instruments reference design with Tc = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
V
Resolution
Range
25
1.8
3.8
Integral nonlinearity (max)
Accuracy
23
22.5
-32
-1
mV
mV
mV
%
VDDS = 3.0 V
Offset error
Gain error
8.18.4 Comparator
8.18.4.1 Continuous Time Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Input voltage range(1)
0
VDDS
Offset
Measured at VDDS / 2
Step from –10 mV to 10 mV
Internal reference
±5
0.78
9.2
mV
µs
Decision time
Current consumption
µA
(1) The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using
the DAC
8.18.5 GPIO
8.18.5.1 GPIO DC Characteristics
PARAMETER
TA = 25 °C, VDDS = 1.8 V
TEST CONDITIONS
MIN
TYP
MAX UNIT
GPIO VOH at 8 mA load
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
1.56
0.24
1.59
0.21
73
V
V
GPIO VOL at 8 mA load
GPIO VOH at 4 mA load
V
GPIO VOL at 4 mA load
IOCURR = 1
V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
Input mode, pulldown enabled, Vpad = VDDS
IH = 1, transition voltage for input read as 0 →1
IH = 1, transition voltage for input read as 1 →0
µA
µA
V
GPIO pulldown current
19
GPIO low-to-high input transition, with hysteresis
GPIO high-to-low input transition, with hysteresis
1.08
0.73
V
IH = 1, difference between 0 →1
and 1 →0 points
GPIO input hysteresis
0.35
V
TA = 25 °C, VDDS = 3.0 V
GPIO VOH at 8 mA load
GPIO VOL at 8 mA load
GPIO VOH at 4 mA load
GPIO VOL at 4 mA load
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
2.59
0.42
2.63
0.40
V
V
V
V
IOCURR = 1
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MAX UNIT
8.18.5.1 GPIO DC Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
TA = 25 °C, VDDS = 3.8 V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
282
110
µA
µA
V
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
IH = 1, transition voltage for input read as 0 →1
IH = 1, transition voltage for input read as 1 →0
GPIO low-to-high input transition, with hysteresis
GPIO high-to-low input transition, with hysteresis
1.97
1.55
V
IH = 1, difference between 0 →1
and 1 →0 points
GPIO input hysteresis
TA = 25 °C
0.42
V
Lowest GPIO input voltage reliably interpreted as a
High
VIH
0.8*VDDS
V
Highest GPIO input voltage reliably interpreted as a
Low
VIL
0.2*VDDS
V
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8.19 Typical Characteristics
All measurements in this section are done with Tc = 25 °C and VDDS = 3.0 V, unless otherwise noted. See
Recommended Operating Conditions, 节 8.3, for device limits. Values exceeding these limits are for reference
only.
8.19.1 MCU Current
图8-4. Active Mode (MCU) Current vs. Supply
图8-5. Standby Mode (MCU) Current vs.
Voltage (VDDS)
Temperature
8.19.2 RX Current
RX Current vs. Temperature
50 kbps, 868.3 MHz
8
7.8
7.6
7.4
7.2
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D008
图8-7. RX Current vs. Temperature (50 kbps, 868.3
图8-6. RX Current vs. Temperature (50 kbps, 868.3
MHz, VDDS = 3.6 V)
MHz)
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RX Current vs. VDDS
50 kbps, 868.3 MHz
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D012
图8-8. RX Current vs. Supply Voltage (VDDS) (50 kbps, 868.3 MHz)
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8.19.3 TX Current
TX Current vs. Temperature
50 kbps, 868.3 MHz, +10 dBm, VDDS = 3.6 V
TX Current vs. Temperature
50 kbps, 915 MHz, +20 dBm PA, VDDS = 3.3 V
18
17.7
17.4
17.1
16.8
16.5
16.2
15.9
15.6
15.3
15
85
80
75
70
65
60
55
50
45
40
35
30
25
+20 dBm
+19 dBm
+18 dBm
+17 dBm
+16 dBm
+15 dBm
+14 dBm
14.7
14.4
14.1
13.8
13.5
13.2
12.9
12.6
12.3
12
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110
Temperature [°C]
Temperature [°C]
D015
D016
图8-9. TX Current vs. Temperature (50 kbps, 868.3
图8-10. TX Current vs. Temperature (50 kbps, 915
MHz, VDDS = 3.6 V)
MHz, VDDS = 3.3 V)
TX Current vs. VDDS
50 kbps, 868.3 MHz, +10 dBm
TX Current vs. VDDS
50 kbps, 915 MHz, +20 dBm PA
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
70
+20 dBm
+19 dBm
65
+18 dBm
+17 dBm
60
+16 dBm
+15 dBm
55
+14 dBm
50
45
40
35
30
25
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
Voltage [V]
Voltage [V]
D023
D022
图8-12. TX Current vs. Supply Voltage (VDDS) (50
图8-11. TX Current vs. Supply Voltage (VDDS) (50
kbps, 915 MHz)
kbps, 868.3 MHz)
表8-2 shows typical TX current and output power for different output power settings.
表8-1. Typical TX Current and Output Power, high power PA (915 MHz, VDDS = 3.3 V)
CC1311P3 at 915 MHz, VDDS = 3.3 V (Measured on CC1311-P3EM-7XD7793-PA915)
txPower
0x1B8ED2
0x448CF
0x48022
0x2661C
0x5618
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
20
19
18
17
16
15
14
20.6
19.5
18.0
17.1
16.2
15.2
14.0
64.9
55.4
46.0
41.5
37.6
33.9
30.2
0x4812
0x380D
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表8-2. Typical TX Current and Output Power (868 MHz, VDDS = 3.0 V)
CC1311P3 at 868 MHz, VDDS = 3.0 V (Measured on CC1311-P3EM-7XD7793-PA915)
txPower
0x013F1
0xB224
0x895E
0x669A
0x3E92
0x3EDC
0x2CD8
0x26D4
0x20D1
0x1CCE
0x16CD
0x14CB
0x12CA
0x12C9
0x10C8
0xAC4
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
14
12.5
12
11
10
9
13.8
12.2
11.8
10.8
9.8
30.0
21.5
20.3
18.1
16.4
15.5
14.5
13.3
12.2
10.9
10.5
9.7
8.9
8
8.1
7
7.0
6
5.8
5
4.4
4
3.7
3
2.2
2
1.5
9.2
1
0.6
8.8
0
-0.5
-7.3
-13.1
-18.3
-22.6
8.3
-5
-10
-15
-20
6.5
0xAC2
5.6
0x6C1
5.2
0x4C0
4.9
1
Boost mode enabled. VDDR regulated to 1.95 V.
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8.19.4 RX Performance
Sensitivity vs. Frequency
50 kbps
Sensitivity vs. Frequency
50 kbps
-105
-106
-107
-108
-109
-110
-111
-112
-113
-114
-115
-105
-106
-107
-108
-109
-110
-111
-112
-113
-114
-115
863
864
865
866
867
868
869
870
900
903
906
909
912
915
918
921
924
927
930
Frequency [MHz]
Frequency [MHz]
D026
D027
图8-13. Sensitivity vs. Frequency (50 kbps, 868
图8-14. Sensitivity vs. Frequency (50 kbps, 915
MHz)
MHz)
Sensitivity vs. VDDS
50 kbps, 868.3 MHz
Sensitivity vs. Temperature
50 kbps, 868.3 MHz
-105
-106
-107
-108
-109
-110
-111
-112
-113
-114
-115
-105
-106
-107
-108
-109
-110
-111
-112
-113
-114
-115
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Temperature [°C]
Voltage [V]
D030
D033
图8-15. Sensitivity vs. Temperature (50 kbps, 868.3
图8-16. Sensitivity vs. Supply Voltage (VDDS) (50
MHz)
kbps, 868.3 MHz)
Selectivity vs. Frequency Offset
50 kbps, 868.3 MHz
Packet error rate vs level and frequency offset for SLR 5 kbps.
100
0
80
60
40
20
0
90
-20
80
70
-40
60
-60
50
40
-80
30
-100
20
10
-120
-20
-10
-8
-6
-4
-2
0
2
4
6
8
10
0
-30
-20
-10
0
10
20
30
Frequency [MHz]
D038
Offset frequency [ppm]
图8-17. Selectivity vs. Frequency Offset (50 kbps,
图8-18. PER vs. Level vs. Frequency (SimpleLink
868.3 MHz)
™ Long Range 5 kbps, 868 MHz)
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图8-20. Narrowband, 9.6 kbps ±2.4 kHz deviation,
图8-19. 802.15.4, 50 kbps, ±25 kHz deviation, 2-
2-GFSK, 868 MHz, 17.1 kHz RX Bandwidth
GFSK, 100 kHz RX Bandwidth
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8.19.5 TX Performance
Output Power vs. Temperature
50 kbps, 915 MHz, +20 dBm PA, VDDS = 3.3 V
Output Power vs. Temperature
50 kbps, 868.3 MHz, +14 dBm
26
24
22
20
18
16
14
12
14
13.8
13.6
13.4
13.2
13
+20 dBm
+19 dBm
+18 dBm
+17 dBm
+16 dBm
+15 dBm
+14 dBm
12.8
12.6
12.4
12.2
12
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90 100
Temperature [°C]
Temperature [°C]
D039
D040
图8-21. Output Power vs. Temperature (50 kbps,
图8-22. Output Power vs. Temperature (50 kbps,
868.3 MHz)
915 MHz)
Output Power vs. VDDS
50 kbps, 868.3 MHz, +14 dBm
Output Power vs. VDDS
50 kbps, 915 MHz, +20 dBm PA
14
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
13
22
+20 dBm
+19 dBm
+18 dBm
20
+17 dBm
+16 dBm
+15 dBm
18
+14 dBm
16
14
12
10
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
Voltage [V]
Voltage [V]
D045
D044
图8-24. Output Power vs. Supply Voltage (VDDS)
图8-23. Output Power vs. Supply Voltage (VDDS)
(50 kbps, 915 MHz)
(50 kbps, 868.3 MHz)
Output Power vs. Frequency
50 kbps, +14 dBm
Output Power vs. Frequency
50 kbps, +14 dBm
14
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
13
14
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
13
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
863
864
865
866
867
868
869
870
902 904 906 908 910 912 914 916 918 920 922 924 926 928
Frequency [MHz]
Frequency [MHz]
D052
D053
图8-25. Output Power vs. Frequency (50 kbps, 868 图8-26. Output Power vs. Frequency (50 kbps, 915
MHz)
MHz)
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Output Power vs. Frequency
50 kbps, +20 dBm PA, VDDS = 3.3 V
22
21.6
21.2
20.8
20.4
20
+20 dBm
+17 dBm
19.6
19.2
18.8
18.4
18
17.6
17.2
16.8
16.4
16
902 904 906 908 910 912 914 916 918 920 922 924 926 928
Frequency [MHz]
D056
图8-27. Output Power vs. Frequency (50 kbps, 915 MHz, VDDS = 3.3 V)
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8.19.6 ADC Performance
ENOB vs. Input Frequency
ENOB vs. Sampling Frequency
Vin = 3.0 V Sine wave, Internal reference,
Fin = Fs / 10
11.4
11.1
10.8
10.5
10.2
9.9
Internal Reference, No Averaging
Internal Unscaled Reference, 14-bit Mode
10.2
10.15
10.1
10.05
10
9.95
9.9
9.85
9.8
9.6
1
2
3
4
5
6
7 8 10
20
30 40 50 70 100
200
0.2 0.3
0.5 0.7
1
2
3
4
5
6 7 8 10
20
30 40 50 70 100
Frequency [kHz]
Frequency [kHz]
D062
D061
图8-29. ENOB vs. Sampling Frequency
图8-28. ENOB vs. Input Frequency
INL vs. ADC Code
Vin = 3.0 V Sine wave, Internal reference,
200 kSamples/s
DNL vs. ADC Code
Vin = 3.0 V Sine wave, Internal reference,
200 kSamples/s
1.5
1
2.5
2
0.5
0
1.5
1
-0.5
-1
0.5
0
-1.5
-0.5
0
400
800
1200 1600 2000 2400 2800 3200 3600 4000
0
400
800
1200 1600 2000 2400 2800 3200 3600 4000
ADC Code
ADC Code
D064
D065
图8-30. INL vs. ADC Code
图8-31. DNL vs. ADC Code
ADC Accuracy vs. VDDS
Vin = 1 V, Internal reference,
200 kSamples/s
ADC Accuracy vs. Temperature
Vin = 1 V, Internal reference,
200 kSamples/s
1.01
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
1.01
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Temperature [°C]
Voltage [V]
D066
D067
图8-32. ADC Accuracy vs. Temperature
图8-33. ADC Accuracy vs. Supply Voltage (VDDS)
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9 Detailed Description
9.1 Overview
节4 shows the core modules of the CC1311P3 device.
9.2 System CPU
The CC1311P3 SimpleLink™ Wireless MCU contains an Arm® Cortex®-M4 system CPU, which runs the
application and the higher layers of radio protocol stacks.
The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
Its features include the following:
• ARMv7-M architecture optimized for small-footprint embedded applications
• Arm Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm
core in a compact memory size
• Fast code execution permits increased sleep mode time
• Deterministic, high-performance interrupt handling for time-critical applications
• Single-cycle multiply instruction and hardware divide
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Saturating arithmetic for signal processing
• Full debug with data matching for watchpoint generation
– Data Watchpoint and Trace Unit (DWT)
– JTAG Debug Access Port (DAP)
– Flash Patch and Breakpoint Unit (FPB)
• Trace support reduces the number of pins required for debugging and tracing
– Instrumentation Trace Macrocell Unit (ITM)
– Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO)
• Optimized for single-cycle flash memory access
• Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait
states
• Ultra-low-power consumption with integrated sleep modes
• 48 MHz operation
• 1.25 DMIPS per MHz
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9.3 Radio (RF Core)
The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor that
interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and
assembles the information bits in a given packet structure. The RF core offers a high level, command-based API
to the main CPU that configurations and data are passed through. The Arm Cortex-M0 processor is not
programmable by customers and is interfaced through the TI-provided RF driver that is included with the
SimpleLink Software Development Kit (SDK).
The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the main
CPU, which reduces power and leaves more resources for the user application. Several signals are also
available to control external circuitry such as RF switches or range extenders autonomously.
The various physical layer radio formats are partly built as a software defined radio where the radio behavior is
either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with
the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards
even with over-the-air (OTA) updates while still using the same silicon.
备注
Not all combinations of features, frequencies, data rates, and modulation formats described in this
chapter are supported. Over time, TI can enable new physical radio formats (PHYs) for the device and
provides performance numbers for selected PHYs in the data sheet. Supported radio formats for a
specific device, including optimized settings to use with the TI RF driver, are included in the SmartRF
Studio tool with performance numbers of selected formats found in 节8.
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9.3.1 Proprietary Radio Formats
The CC1311P3 radio can support a wide range of physical radio formats through a set of hardware peripherals
combined with firmware available in the device ROM, covering various customer needs for optimizing towards
parameters such as speed or sensitivity. This allows great flexibility in tuning the radio both to work with legacy
protocols as well as customizing the behavior for specific application needs.
表 9-1 gives a simplified overview of features of the various radio formats available in ROM. Other radio formats
may be available in the form of radio firmware patches or programs through the Software Development Kit (SDK)
and may combine features in a different manner, as well as add other features.
表9-1. Feature Support
Feature
Main 2-(G)FSK Mode
High Data Rates
Low Data Rates
SimpleLink™ Long Range
Programmable preamble,
sync word and CRC
Yes
Yes
Yes
No
Programmable receive
bandwidth
Yes
Yes
Yes (down to 4 kHz)
Yes
Data / Symbol rate(3)
20 to 1000 kbps
2-(G)FSK
≤2 Msps
≤100 ksps
≤20 ksps
2-(G)FSK
2-(G)FSK
4-(G)FSK
2-(G)FSK
4-(G)FSK
Modulation format
Dual Sync Word
Carrier Sense (1) (2)
Preamble Detection(2)
Data Whitening
Digital RSSI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
CRC filtering
1:2
1:4
1:8
Direct-sequence spread
spectrum (DSSS)
No
No
No
Forward error correction
(FEC)
No
No
No
Yes
Yes
Link Quality Indicator (LQI)
Yes
Yes
Yes
(1) Carrier Sense can be used to implement HW-controlled listen-before-talk (LBT) and Clear Channel Assessment (CCA) for compliance
with such requirements in regulatory standards. This is available through the CMD_PROP_CS radio API.
(2) Carrier Sense and Preamble Detection can be used to implement sniff modes where the radio is duty cycled to save power.
(3) Data rates are only indicative. Data rates outside this range may also be supported. For some specific combinations of settings, a
smaller range might be supported.
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9.4 Memory
The up to 352-KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is in-
system programmable and erasable. The last flash memory sector must contain a Customer Configuration
section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is
done through the ccfg.c source file that is included in all TI provided examples.
The ultra-low leakage system static RAM (SRAM) is a single 32-KB block and can be used for both storage of
data and execution of code. Retention of SRAM contents in Standby power mode is enabled by default and
included in Standby mode power consumption numbers.
To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way
nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the system CPU.
The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area
(CCFG).
The ROM contains a serial (SPI and UART) bootloader that can be used for initial programming of the device.
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9.5 Cryptography
The CC1311P3 device comes with a wide set of cryptography-related hardware accelerators, reducing code
footprint and execution time for cryptographic operations. It also has the benefit of being lower power and
improves availability and responsiveness of the system because the cryptography operations run in a
background hardware thread.
The hardware accelerator modules are:
• True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for the
purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is
built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit.
• Advanced Encryption Standard (AES) with 128 bit key lengths
Together with the hardware accelerator module, a large selection of open-source cryptography libraries provided
with the Software Development Kit (SDK), this allows for secure and future proof IoT applications to be easily
built on top of the platform. The TI provided cryptography drivers are:
• Key Agreement Schemes
– Elliptic curve Diffie–Hellman with static or ephemeral keys (ECDH and ECDHE)
• Signature Generation
– Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA)
• Curve Support
– Short Weierstrass form (full hardware support), such as:
• NIST-P256
– Montgomery form (hardware support for multiplication), such as:
• Curve25519
• Hash
– SHA256
• MACs
– HMAC with SHA256
– AES CBC-MAC
• Block ciphers
– AESECB
– AESCBC
– AESCTR
• Authenticated Encryption
– AESCCM
• Random number generation
– True Random Number Generator
– AES CTR DRBG
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9.6 Timers
A large selection of timers are available as part of the CC1311P3 device. These timers are:
• Real-Time Clock (RTC)
A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF)
This timer is available in all power modes except Shutdown. The timer can be calibrated to compensate for
frequency drift when using the LF RCOSC as the low frequency system clock. If an external LF clock with
frequency different from 32.768 kHz is used, the RTC tick speed can be adjusted to compensate for this.
When using TI-RTOS, the RTC is used as the base timer in the operating system and should thus only be
accessed through the kernel APIs such as the Clock module. By default, the RTC halts when a debugger
halts the device.
• General Purpose Timers (GPTIMER)
The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on up to 48
MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or periodic counting,
pulse width modulation (PWM), time counting between edges and edge counting. The inputs and outputs of
the timer are connected to the device event fabric, which allows the timers to interact with signals such as
GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available in Active and Idle power modes.
• Radio Timer
A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is
typically used as the timing base in wireless network communication using the 32-bit timing word as the
network time. The radio timer is synchronized with the RTC by using a dedicated radio API when the device
radio is turned on or off. This ensures that for a network stack, the radio timer seems to always be running
when the radio is enabled. The radio timer is in most cases used indirectly through the trigger time fields in
the radio APIs and should only be used when running the accurate 48 MHz high frequency crystal is the
source of SCLK_HF.
• Watchdog timer
The watchdog timer is used to regain control if the system operates incorrectly due to software errors. It is
typically used to generate an interrupt to and reset of the device for the case where periodic monitoring of the
system components and tasks fails to verify proper functionality. The watchdog timer runs on a 1.5 MHz clock
rate and cannot be stopped once enabled. The watchdog timer pauses to run in Standby power mode and
when a debugger halts the device.
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9.7 Serial Peripherals and I/O
The SSI is a synchronous serial interface that is compatible with SPI, MICROWIRE, and TI's synchronous serial
interfaces. The SSI support both SPI master and slave up to 4 MHz. The SSI module support configurable phase
and polarity.
The UART implement universal asynchronous receiver and transmitter functions. It support flexible baud-rate
generation up to a maximum of 3 Mbps.
The I2S interface is used to handle digital audio and can also be used to interface pulse-density modulation
microphones (PDM).
The I2C interface is also used to communicate with devices compatible with the I2C standard. The I2C interface
can handle 100 kHz and 400 kHz operation, and can serve as both master and slave.
The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a
programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs
have high-drive capabilities, which are marked in bold in 节 7. All digital peripherals can be connected to any
digital pin on the device.
For more information, see the CC13x1x3, CC26x1x3 SimpleLink™ Wireless MCU Technical Reference Manual.
9.8 Battery and Temperature Monitor
A combined temperature and battery voltage monitor is available in the CC1311P3 device. The battery and
temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage and
respond to changes in environmental conditions as needed. The module contains window comparators to
interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can
also be used to wake up the device from Standby mode through the Always-On (AON) event fabric.
9.9 µDMA
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload
data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available
bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA
controller has dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory when the peripheral is ready to transfer more data.
Some features of the µDMA controller include the following (this is not an exhaustive list):
• Highly flexible and configurable channel operation of up to 32 channels
• Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral
• Data sizes of 8, 16, and 32 bits
• Ping-pong mode for continuous streaming of data
9.10 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface.
The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.
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9.11 Power Management
To minimize power consumption, the CC1311P3 supports a number of power modes and power management
features (see 表9-2).
表9-2. Power Modes
SOFTWARE CONFIGURABLE POWER MODES
RESET PIN
HELD
MODE
ACTIVE
Active
On
IDLE
Off
STANDBY
Off
SHUTDOWN
CPU
Off
Off
Off
Off
Off
No
No
Off
Off
Off
Off
Off
No
No
Flash
Available
On
Off
SRAM
On
Retention
Off
Radio
Available
On
Available
On
Supply System
Register and CPU retention
SRAM retention
Duty Cycled
Partial
Full
Full
Full
Full
Full
48 MHz high-speed clock
(SCLK_HF)
XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
Off
Off
Off
Off
Off
32 kHz low-speed clock
(SCLK_LF)
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Peripherals
Available
Available
Available
On
Available
Available
Available
On
Off
Available
Available
On
Off
Off
Off
Off
Off
On
Off
Off
Off
Wake-up on RTC
Wake-up on pin edge
Wake-up on reset pin
Brownout detector (BOD)
Power-on reset (POR)
Watchdog timer (WDT)
Available
On
On
On
Duty Cycled
On
Off
On
On
Off
Available
Available
Paused
Off
In Active mode, the application system CPU is actively executing code. Active mode provides normal operation
of the processor and all of the peripherals that are currently enabled. The system clock can be any available
clock source (see 表9-2).
In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked
and no code is executed. Any interrupt event brings the processor back into active mode.
In Standby mode, only the always-on (AON) domain is active. An external wake-up event or RTC event is
required to bring the device back to active mode. MCU peripherals with retention do not need to be reconfigured
when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are
latched in standby mode.
In Shutdown mode, the device is entirely turned off (including the AON domain), and the I/Os are latched with
the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from
shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in
this way and reset-by-reset pin or power-on reset by reading the reset status register. The only state retained in
this mode is the latched I/O state and the flash memory contents.
备注
The power, RF and clock management for the CC1311P3 device require specific configuration and
handling by software for optimized performance. This configuration and handling is implemented in the
TI-provided drivers that are part of the CC1311P3 software development kit (SDK). Therefore, TI
highly recommends using this software framework for all application development on the device. The
complete SDK with TI-RTOS (optional), device drivers, and examples are offered free of charge in
source code.
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9.12 Clock Systems
The CC1311P3 device has several internal system clocks.
The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by the
internal 48 MHz RC Oscillator (RCOSC_HF) or an external 48 MHz crystal (XOSC_HF). Radio operation
requires an external 48 MHz crystal.
SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used for the RTC and to synchronize
the radio timer before or after Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC
Oscillator (RCOSC_LF), a 32.768 kHz watch-type crystal, or a clock input on any digital IO.
When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to other
devices, thereby reducing the overall system cost.
9.13 Network Processor
Depending on the product configuration, the CC1311P3 device can function as a wireless network processor
(WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as
a system-on-chip (SoC) with the application and protocol stack running on the system CPU inside the device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second case,
the application must be written according to the application framework supplied with the wireless protocol stack.
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10 Application, Implementation, and Layout
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
For general design guidelines and hardware configuration guidelines, refer to CC13xx/CC26xx Hardware
Configuration and PCB Design Considerations Application Report.
For optimum RF performance, especially when using the high-power PA, it is important to accurately follow the
reference design with respect to component values and layout. Failure to do so may lead to reduced RF
performance due to balun mismatch. The amplitude- and phase balance through the balun must be <1 dB and
<6 degrees, respectively.
PCB stack-up is also critical for proper operation. The CC1311P3 EVMs and characterization boards use a
finished thickness between the top layer (RF signals) and layer 2 (ground plane) of 175 µm. It is very important
to use the same substrate thickness, or slightly thicker, in an end product implementing the CC1311P3 device.
10.1 Reference Designs
The following reference designs should be followed closely when implementing designs using the CC1311P3
device.
Special attention must be paid to RF component placement, decoupling capacitors and DCDC regulator
components, as well as ground connections for all of these.
CC1311-P3EM-7XD7793-
PA915 Design Files
The CC1311P3EM-XD7793-PA915 reference design provides schematic, layout
and production files for the characterization board used for deriving the
performance number found in this document. This reference design is intended for
operation in the 868 MHz and 915 MHz bands.
LP-CC1311P3 Design
Files
The CC1311P3 LaunchPad Design Files contain detailed schematics and layouts
to build application specific boards using the CC1311P3 device. This LaunchPad is
intended for operation in the 868 MHz and 915 MHz bands.
Sub-1 GHz and 2.4 GHz
Antenna Kit for LaunchPad™
Development Kit and
SensorTag
The antenna kit allows real-life testing to identify the optimal antenna for your
application. The antenna kit includes 16 antennas for frequencies from 169 MHz
to 2.4 GHz, including:
• PCB antennas
• Helical antennas
• Chip antennas
• Dual-band antennas for 868 MHz and 915 MHz combined with 2.4 GHz
The antenna kit includes a JSC cable to connect to the Wireless MCU
LaunchPad Development Kits and SensorTags.
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed as follows.
11.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and/or date-
code. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example, XCC1311P3 is
in preview; therefore, an X prefix/identification is assigned).
Device development evolutionary flow:
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, RGZ).
For orderable part numbers of CC1311P3 devices in the RGZ (7-mm x 7-mm) package type, see the Package
Option Addendum of this document, the Device Information in 节 3, the TI website (www.ti.com), or contact your
TI sales representative.
CC1311
P
3
1
T
0
RGZ R
PREFIX
X = Experimental device
Blank = Qualified devie
R = Large Reel
PACKAGE
RGZ = 48-pin VQFN (Very Thin Quad Flatpack No-Lead)
RKP = 40-pin VQFN (Very Thin Quad Flatpack No-Lead)
DEVICE
SimpleLink™ Ultra-Low-Power
Wireless MCU
PRODUCT REVISION
CONFIGURATION
R = Regular
P = +20 dBm PA included
TEMPERATURE
T = 105 C Ambient
FLASH SIZE
SRAM SIZE
3 = 352 kB
1 = 32kB
图11-1. Device Nomenclature
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11.2 Tools and Software
The CC1311P3 device is supported by a variety of software and hardware development tools.
Development Kit
Software
SimpleLink™
CC13XX-
CC26XX SDK
The SimpleLink CC13xx and CC26xx Software Development Kit (SDK) provides a complete
package for the development of wireless applications on the CC13XX / CC26XX family of
devices. The SDK includes a comprehensive software package for the CC1311P3 device,
including the following protocol stacks:
• Bluetooth Low Energy 4 and 5.2
• Thread (based on OpenThread)
• Zigbee 3.0
• Wi-SUN®
• TI 15.4-Stack - an IEEE 802.15.4-based star networking solution for Sub-1 GHz and
2.4 GHz
• Proprietary RF - a large set of building blocks for building proprietary RF software
• Multiprotocol support - concurrent operation between stacks using the Dynamic
Multiprotocol Manager (DMM)
The SimpleLink CC13XX-CC26XX SDK is part of TI’s SimpleLink MCU platform, offering a
single development environment that delivers flexible hardware, software and tool options for
customers developing wired and wireless applications. For more information about the
SimpleLink MCU Platform, visit http://www.ti.com/simplelink.
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Development Tools
Code Composer
Studio™ Integrated
Development
Code Composer Studio is an integrated development environment (IDE) that supports TI's
Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a
suite of tools used to develop and debug embedded applications. It includes an optimizing
C/C++ compiler, source code editor, project build environment, debugger, profiler, and
many other features. The intuitive IDE provides a single user interface taking you through
each step of the application development flow. Familiar tools and interfaces allow users to
get started faster than ever before. Code Composer Studio combines the advantages of the
Eclipse® software framework with advanced embedded debug capabilities from TI resulting
in a compelling feature-rich development environment for embedded developers.
Environment (IDE)
CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace™
software (application energy usage profiling). A real-time object viewer plugin is available
for TI-RTOS, part of the SimpleLink SDK.
Code Composer Studio is provided free of charge when used in conjunction with the XDS
debuggers included on a LaunchPad Development Kit.
Code Composer
Studio™ Cloud
IDE
Code Composer Studio (CCS) Cloud is a web-based IDE that allows you to create, edit and
build CCS and Energia™ projects. After you have successfully built your project, you can
download and run on your connected LaunchPad. Basic debugging, including features like
setting breakpoints and viewing variable values is now supported with CCS Cloud.
IAR Embedded
Workbench® for
Arm®
IAR Embedded Workbench® is a set of development tools for building and debugging
embedded system applications using assembler, C and C++. It provides a completely
integrated development environment that includes a project manager, editor, and build
tools. IAR has support for all SimpleLink Wireless MCUs. It offers broad debugger support,
including XDS110, IAR I-jet™ and Segger J-Link™. A real-time object viewer plugin is
available for TI-RTOS, part of the SimpleLink SDK. IAR is also supported out-of-the-box on
most software examples provided as part of the SimpleLink SDK.
A 30-day evaluation or a 32 KB size-limited version is available through iar.com.
SmartRF™ Studio
SmartRF™ Studio is a Windows® application that can be used to evaluate and configure
SimpleLink Wireless MCUs from Texas Instruments. The application will help designers of
RF systems to easily evaluate the radio at an early stage in the design process. It is
especially useful for generation of configuration register values and for practical testing and
debugging of the RF system. SmartRF Studio can be used either as a standalone
application or together with applicable evaluation boards or debug probes for the RF
device. Features of the SmartRF Studio include:
• Link tests - send and receive packets between nodes
• Antenna and radiation tests - set the radio in continuous wave TX and RX states
• Export radio configuration code for use with the TI SimpleLink SDK RF driver
• Custom GPIO configuration for signaling and control of external switches
CCS UniFlash
CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs.
UniFlash has a GUI, command line, and scripting interface. CCS UniFlash is available free
of charge.
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11.2.1 SimpleLink™ Microcontroller Platform
The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of wired
and wireless Arm® MCUs (System-on-Chip) in a single software development environment. Delivering flexible
hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software
development kit and use throughout your entire portfolio. Learn more on ti.com/simplelink.
11.3 Documentation Support
To receive notification of documentation updates on data sheets, errata, application notes and similar, navigate
to the device product folder on ti.com/product/CC1311P3. In the upper right corner, click on Alert me to register
and receive a weekly digest of any product information that has changed. For change details, review the revision
history included in any revised document.
The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as
follows.
TI Resource Explorer
TI Resource Explorer
Software examples, libraries, executables, and documentation are available for your
device and development board.
Errata
CC1311P3 Silicon
Errata
The silicon errata describes the known exceptions to the functional specifications for
each silicon revision of the device and description on how to recognize a device
revision.
Application Reports
All application reports for the CC1311P3 device are found on the device product folder at: ti.com/product/
CC1311P3/#tech-docs.
Technical Reference Manual (TRM)
CC13x1x, CC26x1x SimpleLink™
Wireless MCU TRM
The TRM provides a detailed description of all modules and
peripherals available in the device family.
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.5 Trademarks
SimpleLink™, Code Composer Studio™, EnergyTrace™, and TI E2E™ are trademarks of Texas Instruments.
I-jet™ is a trademark of IAR Systems AB.
J-Link™ is a trademark of SEGGER Microcontroller Systeme GmbH.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
CoreMark® is a registered trademark of Embedded Microprocessor Benchmark Consortium Corporation.
Arm Thumb® is a registered trademark of Arm Limited (or its subsidiaries).
Wi-SUN® is a registered trademark of Wi-SUN Alliance Inc.
Eclipse® is a registered trademark of Eclipse Foundation.
IAR Embedded Workbench® is a registered trademark of IAR Systems AB.
Windows® is a registered trademark of Microsoft Corporation.
所有商标均为其各自所有者的财产。
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: CC1311P3
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11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2022 Texas Instruments Incorporated
54
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Product Folder Links: CC1311P3
CC1311P3
ZHCSQ71 –MARCH 2022
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12 Mechanical, Packaging, and Orderable Information
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: CC1311P3
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CC1311P31T0RGZR
ACTIVE
VQFN
RGZ
48
2500 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
CC1311
P31
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2022,德州仪器 (TI) 公司
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