C3216X7R2A104K [TI]
LM5020 100V Current Mode PWM Controller; LM5020 100V电流模式PWM控制器
| 型号： | C3216X7R2A104K |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LM5020 100V Current Mode PWM Controller |
| 文件： | 总17页 (文件大小：892K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5020
www.ti.com
SNVS275F –MAY 2004–REVISED APRIL 2006
LM5020 100V Current Mode PWM Controller
Check for Samples: LM5020
1
FEATURES
PACKAGES
2
•
•
•
•
•
•
Internal Start-up Bias Regulator
Error Amplifier
•
•
VSSOP-10
WSON-10 (4 mm x 4 mm)
Precision Voltage Reference
Programmable Softstart
1A Peak Gate Driver
DESCRIPTION
The LM5020 high voltage pulse-width-modulation
(PWM) controller contains all of the features needed
to implement single ended primary power converter
topologies. Output voltage regulation is based on
current-mode control, which eases the design of loop
compensation while providing inherent line feed-
forward. The LM5020 includes a high-voltage start-up
regulator that operates over a wide input range up to
100V. The PWM controller is designed for high speed
capability including an oscillator frequency range to
1MHz and total propagation delays less than 100ns.
Additional features include an error amplifier,
precision reference, line under-voltage lockout, cycle-
by-cycle current limit, slope compensation, softstart,
oscillator synchronization capability and thermal
shutdown. The controller is available in both VSSOP-
10 and WSON-10 packages.
Maximum Duty Cycle Limiting (80% for
LM5020-1 or 50% for LM5020-2)
•
Programmable Line Under Voltage Lockout
(UVLO) with Adjustable Hysteresis
•
•
•
Cycle-by-Cycle Over-Current Protection
Slope Compensation (LM5020-1)
Programmable Oscillator Frequency with
Synchronization Capability
•
•
Current Sense Leading Edge Blanking
Thermal Shutdown Protection
APPLICATIONS
•
•
•
Telecommunication Power Converters
Industrial Power Converters
+42V Automotive Systems
Typical Application Circuit
V
IN
VIN
V
VCC
OUT
LM5020
UVLO
SS
OUT
CS
RT SYNC
/
FB
GND
COMP
COMPENSATION
Figure 1. Non-Isolated Flyback Converter
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2006, Texas Instruments Incorporated
LM5020
SNVS275F –MAY 2004–REVISED APRIL 2006
www.ti.com
Connection Diagram
Top View
1
2
3
4
5
10
SS
VIN
FB
9
8
7
6
RT/SYNC
CS
COMP
VCC
UVLO
GND
OUT
Figure 2. 10-Lead VSSOP, WSON
PIN DESCRIPTIONS
Pin
1
Name
VIN
Description
Application Information
Source Input Voltage
Feedback Signal
Input to the start-up regulator. Input range is 13V to 100V.
2
FB
Inverting input of the internal error amplifier. The non-
inverting input is internally connected to a 1.25V reference.
3
4
COMP
VCC
The output of the error amplifier and input to the
Pulse Width Modulator
COMP pull-up is provided by an internal 5K resistor which
may be used to bias an opto-coupler transistor.
Output of the internal high voltage series pass
regulator. Regulated output voltage is 7.7V
If an auxiliary winding raises the voltage on this pin above
the regulation set point, the internal series pass regulator
will shut down, reducing the internal power dissipation.
5
6
7
OUT
GND
Output of the PWM controller
Ground return
Gate driver output with a 1A peak current capability.
UVLO
Line Under-Voltage Shutdown
An external resistor divider from the power converter
source voltage sets the shutdown levels. The threshold at
this pin is 1.25V. Hysteresis is set by a switched internal
20µA current source.
8
CS
Current Sense input
Current sense input for current mode control and over-
current protection. Current limiting is accomplished using a
dedicated current sense comparator. If the CS pin voltage
exceeds 0.5V the OUT pin switches low for cycle-by-cycle
current limiting. CS is held low for 50ns after OUT switches
high to blank leading edge current spikes.
9
RT / SYNC Oscillator timing resistor pin and synchronization
input
An external resistor connected from RT to GND sets the
oscillator frequency. This pin also accepts synchronization
pulses from an external clock.
10
SS
Softstart Input
An external capacitor and an internal 10µA current source
set the soft-start ramp rate.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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SNVS275F –MAY 2004–REVISED APRIL 2006
Absolute Maximum Ratings(1)(2)
VIN to GND
-0.3V to 100V
-0.3V to 16V
-0.3V to 5.5V
-0.3V to 7V
Internally Limited
2kV
VCC to GND
RT to GND
All other pins to GND
Power Dissipation
ESD Rating(3)
Human Body Model
Storage Temperature
Junction Temperature
-65°C to +150°C
150°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor.
Operating Ratings
VIN Voltage
13V to 90V
8V to 15V
External Voltage applied to VCC
Operating Junction Temperature
-40°C to +125°C
Electrical Characteristics
Specifications in standard type face are for TJ= +25°C and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, and RT = 31.6kΩ.(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Startup Regulator
VCCReg
VCC Regulation
VCC Current Limit
VCC = Open
See(2)
7.4
15
7.7
22
8.0
V
mA
µA
µA
I-VIN
Startup Regulator Leakage
Shutdown Current
VIN = 100V
150
250
500
350
IIN
VUVLO = 0V, VCC = open
VCC Supply
VCC UVLO (Rising)
VccReg
- 300mV
VccReg -
100mV
V
VCC UVLO (Falling)
Supply Current
5.3
6.0
2
6.7
3
V
ICC
Cload = 0
mA
Error Amplifier
GBW
Gain Bandwidth
DC Gain
4
75
MHz
dB
Reference Voltage
COMP Sink Capability
FB = COMP
1.225
5
1.25
17
1.275
V
FB = 1.5V COMP= 1V
mA
UVLO Pin
Shutdown Threshold
1.225
16
1.25
20
1.275
24
V
Undervoltage Shutdown Hysteresis
Current Source
µA
Current Limit
ILIM Delay to Output
CS step from 0 to 0.6V
Time to onset of OUT
Transition (90%)
30
ns
Cycle by Cycle CS Threshold
Voltage
0.45
0.5
50
0.55
V
Leading Edge Blanking Time
ns
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL).
(2) Device thermal limitations may limit usable range.
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Electrical Characteristics (continued)
Specifications in standard type face are for TJ= +25°C and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, and RT = 31.6kΩ.(1)
Symbol
Parameter
Conditions
Min
Typ
Max
55
Units
CS Sink Impedance (clocked)
35
Ω
Soft Start
Softstart Current Source
Softstart to COMP Offset
7
10
13
µA
V
0.35
0.55
0.75
Oscillator
Frequency1 (RT = 31.6k)
Frequency2 (RT = 9.76k)
Sync threshold
See(3)
See(3)
175
560
2.4
200
630
3.2
225
700
3.8
kHz
kHz
V
PWM Comparator
Delay to Output
COMP set to 2V,
CS stepped 0 to 0.4V,
Time to onset of OUT
transition low
25
ns
Min Duty Cycle
COMP=0V
0
%
%
%
Max Duty Cycle (-1 Device)
Max Duty Cycle (-2 Device)
COMP to PWM Comparator Gain
COMP Open Circuit Voltage
COMP Short Circuit Current
75
80
50
85
0.33
5.2
1.1
4.3
0.6
6.1
1.5
V
COMP=0V
mA
Slope Compensation
Slope Comp Amplitude
(LM5020-1 Device Only)
Delta increase at PWM
Comparator to CS
80
105
130
mV
Output Section
Output High Saturation
Output Low Saturation
Rise Time
Iout = 50mA, VCC - VOUT
IOUT = 100mA, VOUT
Cload = 1nF
0.25
0.25
18
0.75
0.75
V
V
ns
ns
Fall Time
Cload = 1nF
15
Thermal Shutdown
Tsd Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
165
25
°C
°C
(3) Specification applies to the oscillator frequency. The operational frequency of the LM5020-2 devices is divided by two.
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SNVS275F –MAY 2004–REVISED APRIL 2006
Typical Performance Characteristics
Unless otherwise specified: TJ = 25°C.
VCC and VIN
VCC
vs
ICC (VIN = 48V)
vs
VIN
9
8
7
6
5
4
3
2
1
20
18
16
14
12
10
8
6
4
2
0
0
20
0
5
10
15
20
25
10
V
(V)
IN
ICC (mA)
Figure 3.
Figure 4.
Oscillator Frequency
vs
Oscillator Frequency
vs
Temperature
RT = 31.6kΩ
RT
210
205
200
195
190
1.00E+06
1.00E+05
1.00E+04
1
10
RT (kW)
100
-40
10
110
60
TEMPERATURE (oC)
Figure 5.
Figure 6.
Soft Start Current
vs
Temperature
Error Amp. Gain/Phase Plot
13.0
11.8
10.6
9.4
50
40
225
180
135
90
30
20
10
45
0
0
-45
-90
-135
-180
-225
-10
-20
-30
-40
-50
8.2
7.0
-40
100k
1M
10M
10k
110
10
60
TEMPERATURE (oC)
FREQUENCY (Hz)
Figure 7.
Figure 8.
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Block Diagram
7.7V SERIES
REGULATOR
VCC
VIN
5V
1.25V
REFERENCE
ENABLE
UVLO
+
-
LOGIC
1.25V
UVLO
HYSTERESIS
CLK
(20 mA)
RT/SYNC
OSC
V
CC
DRIVER
SLOPECOMP
OUT
GND
50 mA
RAMP
GENERATOR
(LM5020-1 Only)
Max Duty Limit
LM5020-1 (80%)
LM5020-2 (50%)
S
R
Q
Q
0
5V
COMP
1.25V
5k
2R
PWM
+
-
FB
LOGIC
1.4V
R
SS
SS
10 mA
SS
CS
+
-
0.5V
2k
CLK + LEB
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SNVS275F –MAY 2004–REVISED APRIL 2006
DETAILED OPERATING DESCRIPTION
The LM5020 High Voltage PWM controller contains all of the features needed to implement single ended primary
power converter topologies. The LM5020 includes a high-voltage startup regulator that operates over a wide
input range to 100V. The PWM controller is designed for high speed capability including an oscillator frequency
range to 1MHz and total propagation delays less than 100ns. Additional features include an error amplifier,
precision reference, line under-voltage lockout, cycle-by-cycle current limit, slope compensation, softstart,
oscillator sync capability and thermal shutdown. The functional block diagram of the LM5020 is shown in Figure
1. The LM5020 is designed for current-mode control power converters, which require a single drive output, such
as Flyback and Forward topologies. The LM5020 provides all of the advantages of current-mode control
including line feed-forward, cycle-by-cycle current limiting and simplified loop compensation .
High Voltage Start-Up Regulator
The LM5020 contains an internal high voltage startup regulator, that allows the input pin (Vin) to be connected
directly to line voltages as high as 100V. The regulator output is internally current limited to 15mA. When power
is applied, the regulator is enabled and sources current into an external capacitor connected to the VCC pin. The
recommended capacitance range for the Vcc regulator is 0.1µF to 100µF. When the voltage on the VCC pin
reaches the regulation level of 7.7V, the controller output is enabled. The controller will remain enabled until VCC
falls below 6V.
In typical applications, a transformer auxiliary winding is connected through a diode to the VCC pin. This winding
should raise the VCC voltage above 8V to shut off the internal startup regulator. Powering VCC from an auxiliary
winding improves conversion efficiency while reducing the power dissipated in the controller. The external VCC
capacitor must be selected such that the capacitor maintains the Vcc voltage greater than the VCC UVLO falling
threshold (6V) during the initial start-up. During a fault condition when the converter auxiliary winding is inactive,
external current draw on the VCC line should be limited such that the power dissipated in the start-up regulator
does not exceed the maximum power dissipation capability of the controller.
An external start-up or other bias rail can be used instead of the internal start-up regulator by connecting the VCC
and the Vin pins together and feeding the external bias voltage (8-15V) to the two pins.
Line Under Voltage Detector
The LM5020 contains a line Under Voltage Lock Out (UVLO) circuit. An external set-point voltage divider from
Vin to GND sets the operational range of the converter. The resistor divider must be designed such that the
voltage at the UVLO pin is greater than 1.25V when Vin is in the desired operating range. If the under voltage
threshold is not met, all functions of the controller are disabled and the controller remains in a low power standby
state.
UVLO hysteresis is accomplished with an internal 20µA current source that is switched on or off into the
impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to
instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25V threshold the
current source is turned off, causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to
implement a remote enable / disable function. If an external transistor pulls the UVLO pin below the 1.25V
threshold, the converter is disabled.
Error Amplifier
An internal high gain error amplifier is provided within the LM5020. The amplifier's non-inverting input is internally
set to a fixed reference voltage of 1.25V. The inverting input is connected to the FB pin. In non-isolated
applications, the power converter output is connected to the FB pin via voltage scaling resistors. Loop
compensation components are connected between the COMP and FB pins. For most isolated applications the
error amplifier function is implemented on the secondary side of the converter and the internal error amplifier is
not used. The internal error amplifier is configured as an open drain output and can be disabled by connecting
the FB pin to ground. An internal 5K pull-up resistor between a 5V reference and COMP can be used as the pull-
up for an optocoupler in isolated applications.
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Current Limit/Current Sense
The LM5020 provides a cycle-by-cycle over current protection function. Current limit is accomplished by an
internal current sense comparator. If the voltage at the current sense comparator input exceeds 0.5V, the output
is immediately terminated. A small RC filter, located near the controller, is recommended to filter noise from the
current sense signal. The CS input has an internal MOSFET which discharges the CS pin capacitance at the
conclusion of every cycle. The discharge device remains on an additional 50ns after the beginning of the new
cycle to attenuate the leading edge spike on the current sense signal.
The LM5020 current sense and PWM comparators are very fast, and may respond to short duration noise
pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated
with the CS filter must be located very close to the LM5020 and connected directly to the pins of the controller
(CS and GND). If a current sense transformer is used, both leads of the transformer secondary should be routed
to the sense resistor and the current sense filter network. A sense resistor located in the source of the primary
power MOSFET may be used for current sensing, but a low inductance resistor is required. When designing with
a current sense resistor all of the noise sensitive low power ground connections should be connected together
local to the controller and a single connection should be made to the high current power ground (sense resistor
ground point).
Oscillator and Sync Capability
A single external resistor connected between the RT and GND pins sets the LM5020 oscillator frequency.
Internal to the LM5020-2 device (50% duty cycle limited option) is an oscillator divide by two circuit. This divide
by two circuit creates an exact 50% duty cycle pulse which is used internally to create a precise 50% duty cycle
limit function. Because of this, the internal oscillator actually operates at twice the frequency of the output (OUT).
For the LM5020-1 device the oscillator frequency and the operational output frequency are the same. To set a
desired output operational frequency (F), the RT resistor can be calculated from:
LM5020-1:
1
RT =
F x 158 x 10-12
(1)
LM5020-2:
1
RT =
F x 316 x 10-12
(2)
The LM5020 can also be synchronized to an external clock. The external clock must have a higher frequency
than the free running oscillator frequency set by the RT resistor. The clock signal should be capacitively coupled
into the RT pin through a 100pF capacitor. A peak voltage level greater than 3.7 Volts at the RT pin is required
for detection of the sync pulse. The sync pulse width should be set between 15 to 150ns by the external
components. The RT resistor is always required, whether the oscillator is free running or externally synchronized.
The voltage at the RT pin is internally regulated at 2 Volts. The RT resistor should be located very close to the
device and connected directly to the pins of the controller (RT and GND).
PWM Comparator / Slope Compensation
The PWM comparator compares the current ramp signal with the loop error voltage derived from the error
amplifier output. The error amplifier output voltage at the COMP pin is offset by 1.4V and then further attenuated
by a 3:1 resistor divider. The PWM comparator polarity is such that 0 Volts on the COMP pin will result in a zero
duty cycle at the controller output. For duty cycles greater than 50 percent, current mode control circuits are
subject to sub-harmonic oscillation. By adding an additional fixed slope voltage ramp signal (slope compensation)
to the current sense signal, this oscillation can be avoided. The LM5020-1 integrates this slope compensation by
summing a current ramp generated by the oscillator with the current sense signal. Additional slope compensation
may be added by increasing the source impedance of the current sense signal. Since the LM5020-2 is not
capable of duty cycles greater than 50%, there is no slope compensation feature in this device.
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Soft Start
The softstart feature allows the power converter to gradually reach the initial steady state operating point, thereby
reducing start-up stresses and current surges. At power on, after the VCC and the line undervoltage lockout
thresholds are satisfied, an internal 10µA current source charges an external capacitor connected to the SS pin.
The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and the duty cycle of the output
pulses.
Gate Driver and Maximum Duty Cycle Limit
The LM5020 provides an internal gate driver (OUT), which can source and sink a peak current of 1 Amp. The
LM5020 is available in two duty cycle limit options. The maximum output duty cycle is typically 80% for the
LM5020-1 option and precisely equal to 50% for the LM5020-2 option. The maximum duty cycle function for the
LM5020-2 is accomplished with an internal toggle flip-flop which ensures an accurate duty cycle limit. The
internal oscillator frequency of the LM5020-2 is therefore twice the operating frequency of the PWM controller
(OUT pin).
The 80% maximum duty cycle limit of the LM5020-1 is determined by the internal oscillator and varies more than
the 50% limit of the LM5020-2. For the LM5020-1 the internal oscillator frequency and the operational frequency
of the PWM controller are equal.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction
temperature is exceeded. This feature prevents catastrophic failures from accidental device overheating. When
activated, typically at 165 degrees Celsius, the controller is forced into a low power standby state, disabling the
output driver and the bias regulator. After the temperature is reduced (typical hysteresis = 25°C) the VCC
regulator is enabled and a softstart sequence initiated.
Typical Application Circuit: 36V - 75 VIN and 3.3V, 4.5A OUT
J2
+3.3V
C12
470 pF
R10
R13
20
C9
0.1 mF
2
T1
V+
J1
30-75V IN
1
D2
10, 1W
1
CMPD2838E
C13
C14
C15
GND
OUT RTN
100 mF 100 mF 270 mF
D3
GND
2
MBRD835L
GND
GND
GND
GND
R2
61.9k
R1
10
C1
2.2 mF
C2
2.2 mF
Z1
GND
GND
1SMB5936B
GND
GND
GND
D1
CMPD2838E
C4
0.1 mF
C10
4.7 mF
Shutdown
R3
2.87k
GND GND
U1
Q1
Si7898DP
C3
0.01 mF
R4
1.00k
R11
2.43k
1
7
4
VIN
VCC
GND
GND
UVLO
5
OUT
R12
1.47k
3
R7
COMP
8
2
6
CS
FB
SYNC
9
RT/
SYNC
SS
100
R8
0.47
Input
10
C8
R9
0.47
GND
GND
100 pF
R5
C11
1000 pF
R6
12.4k
LM5020
15.0k
C6
220 pF
C5
GND
GND
GND
0.01 mF
C7
3300 pF
GND
GND
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Table 1. Bill Of Materials
ITEM
PART NUMBER
DESCRIPTION
VALUE
2.2µF, 100V
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
D
D
1
2
C4532X7R2A225M
C4532X7R2A225M
C2012X7R1H103K
C3216X7R2A104K
C2012X7R1H103K
C2012C0G1H221J
C2012C0G1H332J
C2012C0G1H101J
C2012X7R1H104K
C3216X7R1C475K
C2012C0G1H102J
C2012C0G1H471J
C4532X7S0G107M
C4532X7S0G107M
A700X277M0004AT
CMPD2838E-NSA
CMPD2838E-NSA
MBRD835L
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, CER, KEMET
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, ALUM ORGANIC, KEMET
DIODE, SIGNAL, CENTRAL
DIODE, SIGNAL, CENTRAL
2.2µF, 100V
0.01µF, 50V
0.1µF, 100V
0.01µF, 50V
220pF, 50V
3300pF, 50V
100pF, 50V
0.1µF, 50V
4.7µF, 16V
1000pF, 50V
470p, 50V
3
4
5
6
7
8
9
10
11
12
13
14
15
1
100µF, 4V
100µF, 4V
270µF, 4V
2
3
DIODE, RECTIFIER, ON
SEMICONDUCTOR
J
J
1
2
MKDS 1/2-3.81
MKDS 1/2-3.81
TERM BLK, MINI, 2 POS, PHOENIX
CONTACT
TERM BLK, MINI, 2 POS, PHOENIX
CONTACT
Q
R
R
R
R
R
R
R
R
R
R
R
R
R
T
1
1
SI7898DP
FET, SILICONIX
RESISTOR
150V, 85mΩ
10
CRCW120610R0F
CRCW12066192F
CRCW08052871F
CRCW08051001F
CRCW08051502F
CRCW08051242F
CRCW08051000F
CRCW12060R47F
CRCW12060R47F
CRCW251210R0F
CRCW08052431F
CRCW08051471F
CRCW080520R0F
B0695-A COILCRAFT
PA0751 PULSE
2
RESISTOR
61.9kΩ
2.87kΩ
1.00kΩ
15.0kΩ
12.4kΩ
100
3
RESISTOR
4
RESISTOR
5
RESISTOR
6
RESISTOR
7
RESISTOR
8
RESISTOR
0.47
9
RESISTOR
0.47
10
11
12
13
1
RESISTOR
10, 1W
2.43K
1.47K
20
RESISTOR
RESISTOR
RESISTOR
TRANSFORMER, FLYBACK, EFD20 CORE
T
1
TRANSFORMER, FLYBACK, EFD20 CORE ALTERNATE
U
1
LM5020-2MM
CONTROLLER, SINGLE OUT, PWM,
NATIONAL
Z
1
1SMB5936B
DIODE, ZENER, SMB, 30V
10
Submit Documentation Feedback
Copyright © 2004–2006, Texas Instruments Incorporated
Product Folder Links: LM5020
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
LM5020MM-1
ACTIVE
VSSOP
VSSOP
DGS
10
10
1000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
SBLB
LM5020MM-1/NOPB
ACTIVE
DGS
1000
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
SBLB
LM5020MM-2
ACTIVE
ACTIVE
VSSOP
VSSOP
DGS
DGS
10
10
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
SBNB
SBNB
LM5020MM-2/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM5020MMX-1
ACTIVE
ACTIVE
VSSOP
VSSOP
DGS
DGS
10
10
3500
3500
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
SBLB
SBLB
LM5020MMX-1/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM5020MMX-2
ACTIVE
ACTIVE
VSSOP
VSSOP
DGS
DGS
10
10
3500
3500
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
SBNB
SBNB
LM5020MMX-2/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM5020SD-1
ACTIVE
ACTIVE
WSON
WSON
DPR
DPR
10
10
1000
1000
TBD
Call TI
SN
Call TI
-40 to 125
-40 to 125
5020-1
5020-1
LM5020SD-1/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM5020SD-2/NOPB
ACTIVE
WSON
DPR
10
1000
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
5020-2
LM5020SDX-1
ACTIVE
ACTIVE
WSON
WSON
DPR
DPR
10
10
4500
4500
TBD
Call TI
SN
Call TI
-40 to 125
-40 to 125
5020-1
5020-1
LM5020SDX-1/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM5020SDX-2
ACTIVE
ACTIVE
WSON
WSON
DPR
DPR
10
10
4500
4500
TBD
Call TI
SN
Call TI
-40 to 125
-40 to 125
5020-2
5020-2
LM5020SDX-2/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5020MM-1
LM5020MM-1/NOPB
LM5020MM-2
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DPR
DPR
DPR
DPR
DPR
DPR
DPR
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
1000
1000
1000
1000
3500
3500
3500
3500
1000
1000
1000
4500
4500
4500
4500
178.0
178.0
178.0
178.0
330.0
330.0
330.0
330.0
178.0
178.0
178.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
3.4
3.4
3.4
3.4
3.4
3.4
3.4
3.4
4.3
4.3
4.3
4.3
4.3
4.3
4.3
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.3
1.3
1.3
1.3
1.3
1.3
1.3
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
LM5020MM-2/NOPB
LM5020MMX-1
LM5020MMX-1/NOPB
LM5020MMX-2
LM5020MMX-2/NOPB
LM5020SD-1
LM5020SD-1/NOPB
LM5020SD-2/NOPB
LM5020SDX-1
LM5020SDX-1/NOPB
LM5020SDX-2
LM5020SDX-2/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5020MM-1
LM5020MM-1/NOPB
LM5020MM-2
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DPR
DPR
DPR
DPR
DPR
DPR
DPR
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
1000
1000
1000
1000
3500
3500
3500
3500
1000
1000
1000
4500
4500
4500
4500
203.0
203.0
203.0
203.0
367.0
367.0
367.0
367.0
203.0
203.0
203.0
367.0
367.0
367.0
367.0
190.0
190.0
190.0
190.0
367.0
367.0
367.0
367.0
190.0
190.0
190.0
367.0
367.0
367.0
367.0
41.0
41.0
41.0
41.0
35.0
35.0
35.0
35.0
41.0
41.0
41.0
35.0
35.0
35.0
35.0
LM5020MM-2/NOPB
LM5020MMX-1
LM5020MMX-1/NOPB
LM5020MMX-2
LM5020MMX-2/NOPB
LM5020SD-1
LM5020SD-1/NOPB
LM5020SD-2/NOPB
LM5020SDX-1
LM5020SDX-1/NOPB
LM5020SDX-2
LM5020SDX-2/NOPB
Pack Materials-Page 2
MECHANICAL DATA
DPR0010A
SDC10A (Rev A)
www.ti.com
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