C1608X5R1E105K [TI]
Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO; 中等集成电源解决方案使用双DC / DC转换器和一个LDO
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TEXAS INSTRUMENTS |
| 描述： | Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO |
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Application Report
SLVA343A–June 2009–Revised May 2010
Medium Integrated Power Solution Using a Dual DC/DC
Converter and an LDO
Ambreesh Tripathi .......................................................................... PMP - DC/DC Low-Power Converters
ABSTRACT
This reference design is intended for users designing with the TMS320C6742, TMS320C6746,
TMS320C6748, or OMAP-L138 processor. Using sequenced power supplies, this reference design
describes a system having a 3.3-V input voltage and a high-efficiency dc/dc converter with integrated
FETs for a small, simple design.
Sequenced power supply architectures are becoming commonplace in high-performance microprocessor
and digital signal processor (DSP) systems. To save power and increase processing speeds, processor
cores have smaller geometry cells and require lower supply voltages than the system bus voltages. Power
management in these systems requires special attention. This application report addresses these topics
and suggests solutions for output voltage sequencing.
Contents
1
2
3
4
Introduction .................................................................................................................. 2
Power Requirements ....................................................................................................... 2
Features ...................................................................................................................... 3
Bill of Materials .............................................................................................................. 6
List of Figures
1
2
3
4
5
PMP4978 Reference Design Schematic.................................................................................
Optional Circuit for DVDD_A, DVDD_B and DVDD_C.................................................................
Sequencing in Start-up Waveform........................................................................................
Efficiency VOUT2 = 1.8 V.....................................................................................................
Efficiency VOUT1 = 1.1 V.....................................................................................................
4
5
7
7
7
List of Tables
1
2
Power Requirements .......................................................................................................
PMP4978 Bill of Materials .................................................................................................
2
6
EasyScale is a trademark of Texas Instruments.
SLVA343A–June 2009–Revised May 2010
1
Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO
Copyright © 2009–2010, Texas Instruments Incorporated
Introduction
www.ti.com
1
Introduction
In dual voltage architectures, coordinated management of power supplies is necessary to avoid potential
problems and ensure reliable performance. Power supply designers must consider the timing and voltage
differences between core and input/output (I/O) voltage supplies during power-up and power-down
operations.
Sequencing refers to the order, timing, and differential in which the two voltage rails are powered up and
down. A system designed without proper sequencing may be at risk for two types of failures. The first of
these represents a threat to the long-term reliability of the dual voltage device, whereas the second is
more immediate, with the possibility of damaging interface circuits in the processor or system devices
such as memory, logic or data converter integrated circuits (IC).
Another potential problem with improper supply sequencing is bus contention. Bus contention is a
condition when the processor and another device both attempt to control a bidirectional bus during power
up. Bus contention may also affect I/O reliability. Power supply designers must check the requirements
regarding bus contention for individual devices.
The power-on sequencing for the OMAP-L138, TMS320C6742, TMS320C6746, and TMS320C6748 are
shown in Table 1. No specific voltage ramp rate is required for any of the supplies as long as the 3.3-V rail
never exceeds the 1.8-V rail by more than 2 V.
2
Power Requirements
The power requirements are as specified in Table 1.
Table 1. Power Requirements
(1) (2)
VOLTAGE
(V)
Imax
(mA)
SEQUENCING
ORDER
TIMING
DELAY
PIN NAME
RTC_CVDD
CVDD(4)
TOLERANCE
I/O
1.2
1 / 1.1 / 1.2
1.2
1
–25%, +10%
–9.75%, +10%
–5%, +10%
1(3)
Core
I/O
600
200
2
RVDD, PLL0_VDDA,
3
PLL1_VDDA, SATA_VDD,
USB_CVDD, USB0_VDDA12
I/O
USB0_VDDA18, USB1_VDDA18,
DDR_DVDD18, SATA_VDDR,
DVDD18
1.8
180
±5%
4
I/O
I/O
USB0_VDDA33, USB1_VDDA33
3.3
24
50 / 90(5)
±5%
±5%
5
DVDD3318_A, DVDD3318_B,
DVDD3318_C
1.8 / 3.3
4 / 5
(1)
(2)
If 1.8-V LVCMOS is used, power rails up with the 1.8-V rails. If 3.3-V LVCMOS is used, power it up with the ANALOG33 rails
(VDDA33_USB0/1).
No specific voltage ramp rate is required for any of the supplies LVCMOS33 (USB0_VDDA33, USB1_VDDA33) if STATIC18
(USB0_VDDA18, USB1_VDDA18, DDR_DVDD18, SATA_VDDR, DVDD18) never exceeds more than 2 volts.
If RTC is not used/maintained on a separate supply, it can be included in the STATIC12 (fixed 1.2 V) group.
If using CVDD at fixed 1.2 V, all 1.2-V rails may be combined.
If DVDD3318_A, B, and C are powered independently, maximum power for each rail is 1/3 the above maximum power.
(3)
(4)
(5)
2
Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO
SLVA343A–June 2009–Revised May 2010
Copyright © 2009–2010, Texas Instruments Incorporated
www.ti.com
Features
3
Features
The design uses the following high-efficiency dc/dc converter with integrated FETs.
INPUT VOLTAGE
~3.3 V
INTEGRATION AND HIGH EFFICIENCY
(Without DVFS)
COMBINE RTC AND STATIC 1.2
Core 1.2 V at 600 mA
TPS62420 (DCDC1)
Static 1.2 V + VRTC at 251 mA
Static 1.8 V at 230 mA
TPS62420 (DCDC2)
TPS71733 (DRV)
Static 3.3 V at 115 mA
In the preceding table, VRTC is included in the STATIC12 (fixed 1.2 V) group.
TPS62420
•
•
•
•
•
•
High efficiency – up to 95%
VIN range From 2.5 V to 6 V
Output current 600 mA and 1000 mA
EasyScale™ optional 1-pin serial interface for dynamic output voltage adjustment
Power-Save mode at light-load currents
Available in a 10-pin QFN (3×3mm)
TPS71733
•
•
•
•
150-mA low-dropout (LDO) regulator with enable
Low noise: 30 mV typical (100 Hz to 100 kHz)
Excellent load/line transient response
Small SC70-5, 2 mm × 2 mm SON-6, and 1,5 mm × 1,5 mm SON-6 packages
More information on the devices can be found in the data sheets.
•
•
TPS62420, SLVS676
TPS71733, SBVS068
3
SLVA343A–June 2009–Revised May 2010
Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO
Copyright © 2009–2010, Texas Instruments Incorporated
Features
www.ti.com
Figure 1. PMP4978 Reference Design Schematic
4
Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO
SLVA343A–June 2009–Revised May 2010
Copyright © 2009–2010, Texas Instruments Incorporated
www.ti.com
Features
Proper sequencing is ensured in the design with the use of a NPN transistor and a N-channel MOSFET.
As required, Core 1.2 V at 600 mA comes first , which in turn pulls up the gate of a N-channel MOSFET to
3.3 V with the use of a NPN transistor. Then 1.2 V + VRTC at 251 mA comes up. This 1.2 V further
enables the DCDC1 and sequentially 1.8 V comes up, which again enables an LDO to give 3.3 V at 115
mA.
(1) Use three such LDOs to power up DVDDA, DVDDB, and DVDDC. (It can be either 1.8 V or 3.3 V.)
(2) Rx = 0.499 MΩ, Ry = 1 MΩ for Vout = 1.8 V
(3) Rx = 1.8 MΩ, Ry = 1 MΩ for Vout = 3.3 V
(4) For proper sequencing of output, enable of the LDOs are fed either from a 1.2-V output from TPS62420
DCDC2 if DVDDX is 1.8 V or from a 1.8-V output from TPS62420 DCDC1 if DVDDX is 3.3 V.
Figure 2. Optional Circuit for DVDD_A, DVDD_B and DVDD_C
5
SLVA343A–June 2009–Revised May 2010
Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO
Copyright © 2009–2010, Texas Instruments Incorporated
Bill of Materials
www.ti.com
4
Bill of Materials
Table 2. PMP4978 Bill of Materials
Count RefDes Value
Description
Size
Part Number
MFR
Std
Area
1
1
6
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
J1
0.1 mF
33pF
Capacitor, Ceramic, 50V, C0G, 5%
Capacitor, Ceramic, 50V, C0G, 5%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 16V, X5R, 10%
Capacitor, Ceramic, 25V, X5R, 10%
Capacitor, Ceramic, 50V, X7R, 10%
0603
Std
5650
0603
Std
Std
5650
10 mF
0805
C2012X5R0J106M
C2012X5R0J106M
C2012X5R0J106M
C2012X5R0J106M
C2012X5R0J106M
C2012X5R0J106M
C1608X5R1C225K
C1608X5R1E105K
C1608X7R1H103K
PEC36SAAN
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
Sullins
10560
10560
10560
10560
10560
10560
5650
10 mF
0805
10 mF
0805
10 mF
0805
10 mF
0805
10 mF
0805
1
1
1
1
2.2 mF
1.0 mF
0.01 mF
PEC36SAAN
0603
0603
5650
0603
5650
Header, Male 5-pin, 100mil spacing, (36-pin
strip)
0.100 inch × 5
60000
2
2
L1
2.2 mH
2.2 mH
2N3904
2N3904
Si1012R/X
10k
Inductor, SMT, 1.2A, 100mΩ
Inductor, SMT, 1.2A, 100mΩ
Transistor, NPN, 40V, 200mA, 625mW
Transistor, NPN, 40V, 200mA, 625mW
MOSFET, N-ch, 20V, 600mA, 0.7ohms
Resistor, Chip, 1/16W, 1%
0.102 × 0.110 inch
0.102 × 0.110 inch
TO-92
VLF3014AT-2R2M1R2
VLF3014AT-2R2M1R2
2N3904
TDK
TDK
24,7
24,7
L2
Q1
Q2
Q3
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
U1
U2
Fairchild 37800
Fairchild 37800
TO-92
2N3904
1
2
SC89-3
0603
Si1012R/X
CRCW0603-xxxx-F
CRCW0603-xxxx-F
CRCW0603-xxxx-F
CRCW0603-xxxx-F
Std
Vishay
Vishay
Vishay
Vishay
Vishay
Std
12125
9100
9100
9100
9100
5650
5650
5650
5650
5650
5650
40500
18.6
10k
Resistor, Chip, 1/16W, 1%
0603
1
1
3
100k
Resistor, Chip, 1/16W, 1%
0603
20k
Resistor, Chip, 1/16W, 1%
0603
365K
365K
10K
Resistor, Chip, 1/16W, 1%
0603
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
1
Resistor, Chip, 1/16W, 1%
0603
Std
Std
12.5K
365K
182K
Resistor, Chip, 1/16W, 1%
0603
Std
Std
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
1
1
Resistor, Chip, 1/16W, 1%
0603
Std
Std
TPS62420DRC IC, 2.25 MHz Dual Step Down Converter
QFN10
SC70
TPS62420DRC
TPS71728DCK
TI
TPS71733DCK IC, 150mA, Low Iq, Wide Bandwidth, LDO
Linear Regulators
TI
Notes: 1. These assemblies are ESD sensitive, ESD precautions shall be observed.
2. These assemblies must be clean and free from flux and all contaminants. Failure to use clean flux is unacceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Reference designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's
components.
6
Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO
SLVA343A–June 2009–Revised May 2010
Copyright © 2009–2010, Texas Instruments Incorporated
www.ti.com
Bill of Materials
4.1 Test Result
The start-up waveform (Figure 3) specifies the sequencing order that is required.
Figure 3. Sequencing in Start-up Waveform
100
90
100
V
= 1.8 V
OUT2
V
= 1.1 V
OUT1
90
80
80
V
= 2.7 V
IN
V
= 2.7 V
IN
V
= 2.7 V
70
60
70
60
V
= 2.7 V
IN
IN
V
= 3.6 V
IN
V
V
= 3.6 V
= 5 V
IN
IN
V
= 3.6 V
V
V
= 3.6 V
= 5 V
IN
= 5 V
IN
IN
V
= 5 V
IN
V
50
40
30
20
50
40
30
20
IN
Power Save Mode
MODE/DATA = 0
Forced PWM Mode
MODE/DATA = 1
Power Save Mode
MODE/DATA = 0
Forced PWM Mode
MODE/DATA = 1
10
0
10
0
0.01
0.1
1
10
- mA
100
1000
0.01
0.1
1
10
- mA
100
1000
I
I
OUT
OUT
Figure 4. Efficiency VOUT2 = 1.8 V
Figure 5. Efficiency VOUT1 = 1.1 V
7
SLVA343A–June 2009–Revised May 2010
Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO
Copyright © 2009–2010, Texas Instruments Incorporated
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