C1608X5R0J475K [TI]
Simple Power Solution Using LDOs; 简单的电源解决方案使用的LDO
| 型号： | C1608X5R0J475K |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Simple Power Solution Using LDOs |
| 文件： | 总8页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Application Report
SLVA342A–June 2009–Revised May 2010
Simple Power Solution Using LDOs
Ambreesh Tripathi .......................................................................... PMP - DC/DC Low-Power Converters
ABSTRACT
This reference design helps those desiring to design-in the TMS320C6742, TMS320C6746,
TMS320C6748, and OMAP-L138. This design, employing sequenced power supplies, describes a system
with an input voltage of 3.3 V, and uses LDOs for a small, simple system.
Sequenced power supply architectures are becoming commonplace in high-performance microprocessor
and digital signal processor (DSP) systems. To save power and increase processing speeds, processor
cores have smaller geometry cells and require lower supply voltages than the system bus voltages. Power
management in these systems requires special attention. This application report addresses these topics
and suggests solutions for output voltage sequencing.
Contents
1
2
3
4
Introduction .................................................................................................................. 2
Power Requirements ....................................................................................................... 2
Features ...................................................................................................................... 3
List of Material ............................................................................................................... 6
List of Figures
1
2
3
PMP4980 Reference Design Schematic.................................................................................
Optional Circuit for DVDD_A, DVDD_B, and DVDD_C................................................................
Sequencing in Start-Up Waveform .......................................................................................
4
5
7
List of Tables
1
2
Power Requirements .......................................................................................................
PMP4980 List of Material ..................................................................................................
2
6
1
SLVA342A–June 2009–Revised May 2010
Simple Power Solution Using LDOs
Copyright © 2009–2010, Texas Instruments Incorporated
Introduction
www.ti.com
1
Introduction
In dual voltage architectures, coordinated management of power supplies is necessary to avoid potential
problems and ensure reliable performance. Power supply designers must consider the timing and voltage
differences between core and I/O voltage supplies during power-up and power-down operations.
Sequencing refers to the order, timing and differential in which the two voltage rails are powered up and
down. A system designed without proper sequencing may be at risk for two types of failures. The first of
these represents a threat to the long term reliability of the dual voltage device, while the second is more
immediate, with the possibility of damaging interface circuits in the processor or system devices such as
memory, logic or data converter ICs
Another potential problem with improper supply sequencing is bus contention. Bus contention is a
condition when the processor and another device both attempt to control a bidirectional bus during power
up. Bus contention also may affect I/O reliability. Power supply designers must check the requirements
regarding bus contention for individual devices.
The power-on sequencing for the OMAP-L138, TMS320C6742, TMS320C6746, and TMS320C6748 are
shown in Table 1. No specific voltage ramp rate is required for any of the supplies as long as the 3.3-V rail
never exceeds the 1.8-V rail by more than 2 volts.
2
Power Requirements
The power requirements are as specified in the following table.
Table 1. Power Requirements
(1) (2)
VOLTAGE
(V)
Imax
(mA)
SEQUENCING
ORDER
TIMING
DELAY
PIN NAME
RTC_CVDD
CVDD(4)
TOLERANCE
I/O
1.2
1.0 / 1.1 / 1.2
1.2
1
–25%, +10%
–9.75%, +10%
–5%, +10%
1(3)
Core
I/O
600
200
2
RVDD, PLL0_VDDA,
3
PLL1_VDDA, SATA_VDD,
USB_CVDD, USB0_VDDA12
I/O
USB0_VDDA18, USB1_VDDA18,
DDR_DVDD18, SATA_VDDR,
DVDD18
1.8
180
±5%
4
I/O
I/O
USB0_VDDA33, USB1_VDDA33
3.3
24
50 / 90(5)
±5%
±5%
5
DVDD3318_A, DVDD3318_B,
DVDD3318_C
1.8 / 3.3
4 / 5
(1)
(2)
If 1.8-V LVCMOS is used, power rails up with the 1.8-V rails. If 3.3-V LVCMOS is used, power it up with the ANALOG33 rails
(VDDA33_USB0/1)
No specific voltage ramp rate is required for any of the supplies as long asa LVCMOS33 (USB0_VDDA33, USB1_VDDA33)
never exceeds STATIC18 (USB0_VDDA18, USB1_VDDA18, DDR_DVDD18, SATA_VDDR, DVDD18) by more than 2 volts.
If RTC is not used/maintained on a separate supply, it can be included in the STATIC12 (fixed 1.2 V) group.
If using CVDD at fixed 1.2 V, all 1.2-V rails may be combined.
If DVDD3318_A, B, and C are powered independently, maximum power for each rail is 1/3 the above maximum power.
(3)
(4)
(5)
2
Simple Power Solution Using LDOs
SLVA342A–June 2009–Revised May 2010
Copyright © 2009–2010, Texas Instruments Incorporated
www.ti.com
Features
3
Features
The design uses the LDOs.
INPUT VOLTAGE
~3.3 V
Simple (no DVFS)
COMBINE RTC AND STATIC 1.2
Core 1.2 V at 600 mA
TPS74801
TPS74701
TPS71718
TPS74801
Static 1.2 V + VRTC at 251 mA
Static 1.8 V at 230 mA
Static 3.3 V at 115 mA
Here VRTC is included in the STATIC12 (fixed 1.2V) group.
TPS74801 and TPS74701
•
•
•
•
•
VOUT Range: 0.8 V to 3.6 V
2% Accuracy Over Line/Load/Temperature
Programmable Soft-Start Provides Linear Voltage Startup
Stable with Any Output Capacitor ≥ 2.2 mF
Available in a Small 3-mm × 3-mm × 1-mm SON-10 and 5 × 5 QFN-20 Packages
TPS71718
•
•
•
•
150-mA Low-Dropout Regulator with Enable
Low Noise: 30 mV typical (100 Hz to 100 kHz)
Excellent Load/Line Transient Response
Small SC70-5, 2-mm × 2-mm SON-6, and 1,5-mm × 1,5-mm SON-6 Packages
More information on the devices can be found from the data sheets.
•
•
•
TPS74801, http://focus.ti.com/lit/ds/symlink/tps74801.pdf
TPS74701, http://focus.ti.com/lit/ds/symlink/tps74701.pdf
TPS71718, http://focus.ti.com/lit/ds/symlink/tps71718.pdf
3
SLVA342A–June 2009–Revised May 2010
Simple Power Solution Using LDOs
Copyright © 2009–2010, Texas Instruments Incorporated
Features
www.ti.com
Figure 1. PMP4980 Reference Design Schematic
Proper sequencing is ensured in the design with the use of enable pins. As required, Core 1.2 V at 600
mA comes first, followed by Static 1.2 V + VRTC at 251 mA, Static 1.8 V at 230 mA which in turn enable
the LDO and hence at last Static 3.3 V at 115 mA comes up.
4
Simple Power Solution Using LDOs
SLVA342A–June 2009–Revised May 2010
Copyright © 2009–2010, Texas Instruments Incorporated
www.ti.com
Features
(1) Use three such LDOs to power up DVDDA, DVDDB, DVDDC (It can either be 1.8 V or 3.3 V)
(2) Rx = 0.499 MΩ, Ry = 1 MΩ for Vout = 1.8 V
(3) Rx = 1.8 MΩ, Ry = 1 MΩ for Vout = 3.3 V
(4) For proper sequencing of output, enable of the LDOs are fed either from 1.2-V output from TPS74701 if
DVDDX is 1.8 V or from 1.8-V output from TPS71718 if DVDDX is 3.3 V.
Figure 2. Optional Circuit for DVDD_A, DVDD_B, and DVDD_C
5
SLVA342A–June 2009–Revised May 2010
Simple Power Solution Using LDOs
Copyright © 2009–2010, Texas Instruments Incorporated
List of Material
www.ti.com
4
List of Material
Table 2. PMP4980 List of Material
Count RefDes
Value
1.0uF
4.7uF
4.7uF
4.7uF
1uF
Description
Size
Part Number
MFR
TDK
TDK
TDK
TDK
Area
5650
5650
5650
5650
5650
5650
5650
5650
5650
5650
2800
5650
5650
5650
1
2
2
3
1
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
J1
Capacitor, Ceramic, 25V, X5R, 10%
Capacitor, Ceramic, 6.3V, X5R, 10%
Capacitor, Ceramic, 6.3V, X5R, 10%
Capacitor, Ceramic,4.7uF, 6.3V, X5R
Capacitor, Ceramic,1uF, 16V, X5R
Capacitor, Ceramic,4.7uF, 6.3V, X5R
Capacitor, Ceramic,4.7uF, 6.3V, X5R
Capacitor, Ceramic, 1000pF, 50V, X7R, 10%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 6.3V, X5R, 20%
Capacitor, Ceramic, 50V, COG, 10%
Capacitor, Ceramic, 25V, X5R, 10%
Capacitor, Ceramic, 6.3V, X5R, 10%
Capacitor, Ceramic, 6.3V, X5R, 10%
Header, Male 5-pin, 100mil spacing, (36-pin strip)
Resistor, Chip, 1/16W, 1%
0603
C1608X5R1E105K
C1608X5R0J106M
C1608X5R0J475K
C1608X5R0J475M
0603
0603
0603
0603
C1608X5R1C105K TDK
4.7uF
4.7uF
1nF
0603
C1608X5R0J475M
C1608X5R0J475M
TDK
TDK
0603
1
2
0603
C1608X7R1H102K TDK
C1608X5R1E105M TDK
C1608X5R1E105M TDK
1uF
0603
1uF
0603
1
1
0.01uF
1.0uF
4.7uF
4.7uF
PEC36SAAN
2.49k
4.99k
10.0k
10k
0402
Std
Std
0603
C1608X5R1E105K
TDK
TDK
TDK
0603
C1608X5R0J106M
0603
C1608X5R0J475K
1
1
1
2
1
1
1
1
1
0.100 inch × 5
0603
PEC36SAAN
Std
Sullins
Std
Std
Std
Std
Std
Std
Std
Std
Std
60000
5650
5650
5650
5,650
5,650
5,650
5650
5650
5650
R1
R2
R3
R4
R5
R6
R7
R8
R9
TP1
Resistor, Chip, 1/16W, 1%
0603
Std
Resistor, Chip, 1/16W, 1%
0603
Std
Resistor, Chip, 10k-Ohms 1/16W, 5%
Resistor, Chip, 2k49-Ohms, 1/16W, 5%
Resistor, Chip, 4k99-Ohms, 1/16W, 5%
Resistor, Chip, 1/16W, 1%
0603
Std
2.49k
4.99k
3.57k
1.15k
10.0k
5000
0603
Std
0603
Std
0603
Std
Resistor, Chip, 1/16W, 1%
0603
Std
Resistor, Chip, 1/16W, 1%
0603
Std
2
Test Point, Red, Thru Hole Color Keyed
0.100 × 0.100
5000
Keyston 10
e
TP2
TP3
5000
5001
Test Point, Red, Thru Hole Color Keyed
Test Point, Black, Thru Hole Color Keyed
0.100 × 0.100
5000
5001
Keyston 10
e
1
0.100 × 0.100 inch
Keyston 10
e
2
1
1
U1
U2
U3
TPS74801DRC IC, 1.5A LDO Regulator with Soft-Start
TPS74701DRC IC, 1.5A LDO Regulator with Soft-Start
SON-10
SON-10
SC70
TPS74801DRC
TPS74701DRC
TPS71718
TI
TI
TI
30400
30400
18600
TPS71718
IC, 150mA, Low Iq, Wide Bandwidth, LDO Linear
Regulators
U4
TPS74801DRC IC, 1.5A LDO Regulator with Soft-Start
SON-10
TPS74801DRC
TI
30400
Notes: 1. These assemblies are ESD sensitive, ESD precautions shall be observed.
2. These assemblies must be clean and free from flux and all contaminants.
Use of unclean flux is unacceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk ('**') cannot be substituted.
All other components can be substituted with equivalent MFG's components.
6
Simple Power Solution Using LDOs
SLVA342A–June 2009–Revised May 2010
Copyright © 2009–2010, Texas Instruments Incorporated
www.ti.com
List of Material
4.1 Test Results
The start-up waveform is shown in Figure 3, which specifies the sequencing order that is required.
Figure 3. Sequencing in Start-Up Waveform
7
SLVA342A–June 2009–Revised May 2010
Simple Power Solution Using LDOs
Copyright © 2009–2010, Texas Instruments Incorporated
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