BQ76200 [TI]
高侧 N 沟道 FET 驱动器;
| 型号： | BQ76200 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高侧 N 沟道 FET 驱动器 驱动 驱动器 |
| 文件： | 总28页 (文件大小：1591K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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bq76200
ZHCSED8 –NOVEMBER 2015
bq76200 高压电池组前端充电/放电高侧 NFET 驱动器
1 特性
3 说明
1
•
CHG 和 DSG 高侧 N 沟道金属氧化物半导体
bq76200 器件是一款低功耗、高侧 N 沟道系统。 高侧
(NMOS) 场效应晶体管 (FET) 驱动器，可控制电池
保护快速 FET 导通和关断次数
保护可防止系统的接地引脚断开连接，同时允许电池组
与主机系统之间进行持续通信。 该器件的附加 P 沟道
FET 控制功能支持对深度耗尽型电池进行低电流预充
电，其 PACK+ 电压监控控制功能支持主机感测
PACK+ 电压。
•
预充电 P 沟道场效应晶体管 (PFET) 驱动器（用于
为显著耗尽的电池组进行限流预充电）
•
•
•
独立的数字使能充/放电控制
所需外部组件最少
独立的使能输入允许单独导通和关断 CHG 与 DSG
FET，从而提供灵活的电池系统实施方案。
基于可扩展外部电容的电荷泵，适用于不同范围内
的并行 FET
•
•
•
•
耐受高压（绝对最高电压为 100V）
使能电池组电压感测的内部开关
支持通用和独立的充/放电路径配置
bq76200 器件可与配套的模拟前端器件搭配使用，例
如 bq76920/30/40 系列、3 节至 15 节电池模拟前端监
控以及主机微控制器或专用的充电状态 (SOC) 跟踪电
量监测计器件。
设计为直接与 bq76940、bq76930 和 bq76920 电
池监控器搭配使用
•
电流消耗：
器件信息(1)
部件号
封装
封装尺寸（标称值）
–
–
正常模式：40μA
5.00mm × 4.40mm ×
1.00mm
关断模式：< 10µA（最大值）
bq76200
TSSOP (16)
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用
•
电动自行车 (eBike)、电动踏板车 (eScooter) 和电
动摩托车 (eMotorcycles)
储能系统和不间断电源 (UPS)
便携式医疗系统
•
•
•
•
•
无线基站电池系统
铅酸 (PbA) 备用电池
12V 至 48V 电池组
简化电路原理图
1 Mꢀ
t!/Y+
10 Mꢀ
10 Mꢀ
bq76200
VDDCP
CHG
NC
100 ꢀ
100 ꢀ
470 nF
BAT
NC
PCHG
NC
0.01 µF
CHG_EN
CP_EN
DSG_EN
DSG
PACK
From AFE
or
MCU
PMON_EN PACKDIV
PCHG_EN
0.01 µF
VSS
Ra
Rb
To ADC
t!/Y-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSC16
bq76200
ZHCSED8 –NOVEMBER 2015
www.ti.com.cn
目录
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Applications ................................................ 17
Power Supply Recommendations...................... 19
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics ............................................. 7
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 9
8
9
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 器件和文档支持 ..................................................... 21
11.1 文档支持................................................................ 21
11.2 社区资源................................................................ 21
11.3 商标....................................................................... 21
11.4 静电放电警告......................................................... 21
11.5 Glossary................................................................ 21
12 机械、封装和可订购信息....................................... 21
7
4 修订历史记录
日期
修订版本
注释
2015 年 11 月
*
最初发布版本
2
Copyright © 2015, Texas Instruments Incorporated
bq76200
www.ti.com.cn
ZHCSED8 –NOVEMBER 2015
5 Pin Configuration and Functions
PW Package
16-pin TSSOP
Top View
VDDCP
BAT
1
2
3
4
5
6
7
8
16
15
14
CHG
NC
NC
PCHG
CHG_EN
CP_EN
13 NC
DSG
12
11
DSG_EN
PMON_EN
PCHG_EN
PACK
10 PACKDIV
9
VSS
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
BAT
CHG(2)
NO.
2
I/O
P
O
I
Top of battery stack
16
4
Gate drive for charge FET
Charge FET enable
CHG_EN(3)
CP_EN(3)
5
I
Charge pump enable (internally logic ORed with CHG_EN and DSG_EN
signals)
DSG(2)
DSG_EN(3)
NC
12
O
I
Gate drive for discharge FET
6
Discharge FET enable
3, 13, 15
—
P
O
O
I
No connect. Leave the pin floating
Analog input from PACK+ terminal
PACK voltage after internal switch (connect to MCU ADC via resistor divider).
Gate drive for pre-charge FET
PACK
11
10
14
8
PACKDIV(2)
PCHG(2)
PCHG_EN(3)
PMON_EN(3)
Pre-charge FET enable
7
I
Pack monitor enable (allows connection of internal switch between PACK
and PACKDIV)
VDDCP
VSS
1
9
O
P
Charge pump output. Connect a capacitor to BAT pin. Do not load this pin.
Ground reference
(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output
(2) Leave the pin float if function is not used.
(3) Recommended to connect the pin to ground if function is not used.
Copyright © 2015, Texas Instruments Incorporated
3
bq76200
ZHCSED8 –NOVEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–40
MAX
100
15
UNIT
V
BAT, PACK (both under charge pump disabled condition)
Input voltage range, VIN
CHG_EN, DSG_EN, PCHG_EN, PMON_EN, CP_EN(2)
CHG, DSG, PCHG, PACKDIV, VDDCP
Functional Temperature
V
Output voltage range, VO
TFUNC
100
110
150
V
°C
°C
Storage temperature, Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The enable inputs need to be current limited with max current not exceeding 5 mA.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-
001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification
JESD22-C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Typical values stated where TA = 25°C and VBAT = 48.8 V, Min/Max values stated where TA = –40°C to 85°C and BAT = 8 V
to 75 V (unless otherwise noted)
MIN
8
NOM
MAX
75
UNIT
V
VBAT
Battery cell input supply voltage range
VPACK
VIN
CVDDCP
TOPR
Charger/Load voltage range
0
75
V
Input voltage range CHG_EN, DSG_EN, PCHG_EN, PMON_EN, CP_EN
Capacitor Between VDDCP and BAT
0
14
V
470
nF
°C
Operating free-range temperature
–40
85
6.4 Thermal Information
TSSOP (PW)
16 PINS
106.8
41.5
THERMAL METRIC(1)
UNIT
RθJA, High K
RθJC(top)
RθJB
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
51.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
3.8
ψJB
51.3
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
bq76200
www.ti.com.cn
ZHCSED8 –NOVEMBER 2015
6.5 Electrical Characteristics
Typical values stated at TA = 25°C and V(BAT) = 48 V. MIN/MAX values stated with TA = –40°C to 85°C and V(BAT) = 8 to 75 V
unless otherwise noted.
PARAMETER
DESCRIPTION
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY AND LEAKAGE CURRENT
C(VDDCP) = 470 nF, V(BAT) = V(PACK)
CL = 10 nF
,
I(BAT)
Ishut
NORMAL mode current(1)
40
6
50
µA
µA
Sum of current into BAT and
PACK pin
Shutdown Mode, PACK = 0 V, BAT = 8 V
9.5
CHARGE PUMP
V(VDDCP)
Charge pump voltage
No Load, CP_EN = hi, V(VDDCP) – V(BAT)
9
14
V
Charge pump start up time from C(VDDCP) = 470 nF, 10% to 90% of
tCPON
100
ms
zero volt
V(VDDCP)
INPUT ENABLE CONTROL SIGNALS
Digital low input level for
VIL
CHG_EN, DSG_EN,
0.6
V
PCHG_EN, CP_EN, PMON_EN
Digital high input level for
CHG_EN, DSG_EN,
PCHG_EN, CP_EN, PMON_EN
VIH
1.2
0.6
V
RPD
Internal Pull down
VIN = 5 V
1
4
MΩ
CHARGE FET DRIVER
CL = 10 nF, CHG_EN = Hi, V(BAT)
V(PACK), V(CHG) – V(BAT)
=
V(CHGFETON)
R(CHGFETON)
R(CHGFETOFF)
CHG gate drive voltage (on)
9
12
1.1
0.3
14
V
V(VDDCP) – V(BAT) = 12 V, CHG_EN = Hi,
V(BAT) = V(PACK)
CHG FET driver on resistance
CHG FET driver off resistance
kΩ
kΩ
V(VDDCP) – V(BAT) = 12 V, CHG_EN = Lo,
V(BAT) = V(PACK)
DISCHARGE FET DRIVER
CL = 10 nF, DSG_EN = Hi, V(BAT)
V(PACK), V(DSG) – V(PACK)
=
V(DSGFETON)
R(DSGFETON)
R(DSGFETOFF)
DSG gate drive voltage (on)
9
12
3.5
1
14
V
V(VDDCP) – V(BAT) = 12 V, DSG_EN = Hi,
V(BAT) = V(PACK)
DSG FET driver on resistance
DSG FET driver off resistance
kΩ
kΩ
V(VDDCP) – V(BAT) = 12 V, DSG_EN = Lo,
V(BAT) = V(PACK)
PRECHARGE FET DRIVER
V(PACK) > 17 V, V(BAT) < V(PACK), V(PACK)
V(PCHG)
–
V(PCHGFETON)
PCHG gate drive voltage (on)
5
12
14
V
PACK MONITOR (PACK_DIV)
On resistance of internal FET
R(PMONFET)
(R between PACK and
PACKDIV)
PMON_EN = hi
1.5
2.5
3.5
kΩ
(1) NORMAL mode is defined as CHG_EN = Hi, DSG_EN = Hi, CP_EN = Hi, PCHG_EN = Lo, PMON_EN = Lo. Current value is averaged
out over time.
版权 © 2015, Texas Instruments Incorporated
5
bq76200
ZHCSED8 –NOVEMBER 2015
www.ti.com.cn
6.6 Timing Requirements
Parameter
Description
TEST CONDITION
MIN
TYP
MAX
UNIT
CL = 10 nF, (20% of CHG_EN from Lo
to Hi) to (80% of V(CHGFETON)), CP_EN =
Hi, (CP is already on)
CHG on rise time + propagation
delay
tCHGFETON
27
7
45
20
µs
CL= 10 nF, (80% of CHG_EN from Hi to
Lo) to (20% of V(CHGFETON)) , CHG_EN
= Hi to Lo
CHG off fall time + progation
delay
tCHGFETOFF
tPROP _CHG
tDSGFETON
µs
µs
µs
CL= 10 nF, CP_EN = Hi, (CP is already
on), see timing diagram
CHG EN to CHG output
0.5
24
CL = 10 nF, (20% of DSG_EN from Lo
to Hi) to (80% of V(DSGFETON)), CP_EN =
Hi, (CP is already on)
DSG on rise time + propagation
delay
50
20
DSG off fall time + propagation CL = 10 nF, (80% of DSG_EN from Hi to
tDSGFETOFF
tPROP_DSG
tPCHGOFF
7
0.5
30
µs
µs
µs
µs
µs
µs
delay
Lo) to (20% of V(DSGFETON))
DSG EN to DSG output
propagation delay
CL= 10 nF, CP_EN = Hi, (CP already
on), see timing Diagram
PCHG turn off time +
propagation delay
CL = 1 nF, (20% of PCHG_EN from Hi
55
55
to Lo) to (80% of V(PCHGFETON)
)
PCHG turn on time +
propagation delay
CL = 1 nF, (80% of PCHG_EN from Lo
tPCHGON
34
to Hi) to (20% of V(PCHGFETON)
CL = 1 nF
)
PCH_EN to PCHG propagation
delay
tPROP_PCHG
tPROP_PMON
0.5
0.5
PMON_EN and PACKDIV =
PACK propagation delay
80%
CHG_EN/
DSG_EN/
20%
80%
CHG/
DSG/
20%
Tprop
Tprop
TFETON
TFETOFF
图 1. Timing Characteristics - ( CP assumed to be already On)
6
版权 © 2015, Texas Instruments Incorporated
bq76200
www.ti.com.cn
ZHCSED8 –NOVEMBER 2015
6.7 Typical Characteristics
36
34
32
30
28
26
24
22
7
6.5
6
Min
Average
Max
Min
Average
Max
5.5
5
4.5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
Temperature (èC)
Temperature (èC)
D001
D002
图 2. Normal Mode Current Vs Battery
图 3. Shutdown Mode Current vs Battery
1.75
11.5
11.25
11
-40èC
25èC
105èC
Min
Average
Max
1.5
1.25
1
10.75
10.5
10.25
10
0.75
0.5
9.75
9.5
0
2
4
6
8
10
12
14
16
-50
-25
0
25
50
75
100
Input Voltage (V)
Temperature (èC)
D003
D0041
图 4. Input Pin Voltage for Internal Pull-Down Resistance
图 5. CHG/DSG FET On Voltage vs Temperature
(Rpd)
16
Min
Average
Max
14
12
10
8
6
-50
-25
0
25
50
75
100
Temperature (èC)
D005
图 6. PCHG On Voltage vs Temperature
版权 © 2015, Texas Instruments Incorporated
7
bq76200
ZHCSED8 –NOVEMBER 2015
www.ti.com.cn
7 Detailed Description
7.1 Overview
The bq76200 device is a low-power, high-side, N-Channel MOSFET driver for battery-pack protection systems,
allowing a low-side battery-protection system to be implemented into a high-side protection system.
High-side charge/discharge FETs offer a huge advantage versus their low-side counterparts; with high-side
implementation, a system-side processor can always communicate with the monitor or micro-controller (MCU)
within the battery pack, regardless of whether the FETs are on or off — this is not easily supported in a low-side
switching architecture due to the lack of a shared ground reference. One key benefit of an ever-present
communication link is the ability to read out critical pack parameters despite safety faults, thereby enabling the
system to assess pack conditions before determining if normal operation may resume.
The device allows independent control on charging and discharge via the digital enable pins. The device has
integrated charge pump which is enabled by the CP_EN pin. The enable inputs, CHG_EN, DSG_EN, and
PCHG_EN control the CHG, DSG, and PCHG FET gate drivers, respectively. The enable inputs can be
connected to low-side FET driver outputs of an Analog Front End (AFE) such as Texas Instruments bq769x0
series, a general purpose microcontroller, or dedicated battery pack controller such as the bq783xx series.
In normal mode, the AFE or MCU enables the CHG_EN and DSG_EN, turning on the CHG and DSG FET
drivers to connect the battery power to the PACK+ terminal. When a fault is detected by the AFE or the
microcontroller, it can disable the CHG_EN and/or DSG_EN to open the charge or discharge path for protection.
Note that when either the CHG_EN or DSG_EN is enabled, the charge pump will be automatically enabled even
if the CP_EN is in the disable state. It is recommended to enable the charge pump via CP_EN pin during system
start-up to avoid adding the tCPON time into the FET switching time during normal operation.
A lower charging current is usually applied to a deeply depleted battery pack. The bq76200 PCHG_EN input
provides an option to implement a P-Channel MOSFET pre-charge path (current-limited path) in the battery pack.
An AFE usually provides individual cell voltages and/or battery stack voltage measurements, but it is not
necessary to have PACK+ voltage measurement. The bq76200 PMON_EN pin, when enabled, will connect the
PACK+ voltage onto the PACKDIV pin, which is connected to an external resistor divider to scale down the
PACK+ voltage. This scaled down PACK+ voltage can be connected to a microcontroller's ADC input for voltage
measurement. The system can use this information for charger detection or to implement advanced charging
control.
For safety purposes, all the enable inputs are internally pulled down. If the AFE or microcontroller is turned off, or
if the PCB trace is damaged, the internal pull down of the enable inputs will keep CHG, DSG, PCHG in an off
state and the PACK+ voltage does not switch onto the PACKDIV pin.
8
版权 © 2015, Texas Instruments Incorporated
bq76200
www.ti.com.cn
ZHCSED8 –NOVEMBER 2015
7.2 Functional Block Diagram
BAT
PACK
PACKDIV
Vcommon
UVLO
Reference
PMON_EN
CHG_EN
CHG
Charge
Pump
CP_EN
VDDCP
DSG
I/O
DSG_EN
Vcommon
PCHG
PCHG_EN
VSS
图 7. Functional Block Diagram
7.3 Feature Description
7.3.1 Charge Pump Control
The bq76200 device has an integrated charge pump. A minimum of 470-nF capacitor is required on the V(VDDCP)
pin to the BAT pin to ensure proper function of the charge pump. If the V(VDDCP) capacitor is disconnected, a
residual voltage could reside at the CHG and/or DSG output if CHG_EN and/or DSG_EN are enabled. Such a
fault condition can put the external FETs in high Rdson state and result in FET damage.
版权 © 2015, Texas Instruments Incorporated
9
bq76200
ZHCSED8 –NOVEMBER 2015
www.ti.com.cn
Feature Description (接下页)
The V(VDDCP) capacitor can be scaled up to support more FETs in parallel (such as high-total FET-gate
capacitance) than the value specified in the electrical characteristics table. A higher VDDCP capacitance results
in longer tCPON time. See the Application Information section for more information. Note that probing the VDDCP
pin may increase the loading on the charge pump and result in lower measurement value than the V(VDDCP)
specification. Using higher impedance probe can reduce such effect on the measurement.
The charge pump is controlled by CP_EN and also OR'ed with the CHG_EN and DSG_EN inputs. This means
by enabling CHG_EN or DSG_EN alone, the charge pump will automatically turn on even if the CP_EN pin is
disabled. The PCHG_EN controls the PCHG pin, which is a P-channel FET driver and does not require the
function of the charge pump. The charge pump is turned off by default. When CP_EN is high, the charge pump
turns on regardless of the status of the CHG_EN and DSG_EN inputs.
When CP_EN is enabled, the charge pump voltage starts to ramp up. Once the voltage is above an internal
UVLO level, about 9-V typical above VBAT, the charge pump is considered on. The charge pump voltage should
continuously ramp to the V(VDDCP) level. If the CHG_EN and/or DSG_EN is enabled, the CHG and/or DSG
voltage will starts to turn on after the charge pump voltage is above the UVLO level, and ramp up along the
charge pump voltage to the V(VDDCP) level. Otherwise, the CHG and DSG do not turn on if the charge pump
voltage fails to ramp up above UVLO. For example, if the C(VDDCP) is not scaled properly to support the number
of FETs in parallel, the heavy loading would prevent the charge pump to ramp up above UVLO. CHG and DSG
would not be turned on in this case.
When CHG_EN and/or DSG_EN is enabled after the charge pump is fully turned on, the CHG_EN-enable to
CHG-on delay (or DSG_EN-enable to DSG-on delay) is simply the sum of (tprop + FET rise time). A system
configuration example for this scenario will be connecting the CP_EN to the host MCU, enable CP_EN at system
start-up and keep the CP_EN enabled during normal operation. This is the recommended configuration, because
the charge pump ramp-up time, tCPON, becomes part of the system start-up time and does not add onto the FET
switch delay during normal operation.
If CP_EN is not used (it is highly recommended to connect the CP_EN to ground), the charge pump on- and off-
state is controlled by CHG_EN or DSG_EN. The CHG or DSG output will only be on after the charge-pump
voltage is ramped up above UVLO. This means the CHG_EN-enable to CHG-on delay (or DSG_EN-enable to
DSG-on delay) will be (tCPON + tprop + FET rise time).
The charge pump is turned off when CP_EN AND CHG_EN AND DSG_EN signals are all low. The charge pump
is not actively driven low and the voltage on the V(VDDCP) capacitor bleeds off passively. If any of the CP_EN,
CHG_EN, or DSG_EN signals is switched high again while the V(VDDCP) capacitor is still bleeding off its charge,
the charge pump start up time, tCPON, will be shorter.
7.3.2 Pin Enable Controls
The bq76200 has four digital enable inputs that control the state of associated output signals as defined in the
following table. The VIH and VIL levels of these enable pins are low enough to work with most MCUs. At the
same times, the pins have high enough tolerant to allow direct control from an AFE FET driver. This gives
system maker a flexible option to architect the battery pack configuration.
INPUT PIN
CHG_EN
ASSOCIATED OUTPUT PIN
DESCRIPTION
Charge FET control
Discharge FET control
Pre-charge FET control
Pack monitor control
CHG
DSG
DSG_EN
PCHG_EN
PMON_EN
PCHG
PACKDIV
10
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bq76200
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7.3.2.1 External Control of CHG and DSG Output Drivers
The CHG_EN and DSG_EN pins provide direct control of the CHG and DSG FET driver. 表 1 summarizes the
CHG and DSG statute with respect to the CP_EN, CHG_EN and DSG_EN inputs.
表 1. CHG and DSG with Respect to CP_EN, CHG_EN, and DSG_EN
CP_EN
CHG_EN
DSG_EN
CHARGE PUMP
CHG
OFF (default)
OFF
DSG
OFF (default)
ON
Lo (default)
Lo (default)
Lo (default)
OFF (default)
Lo
Lo
Lo
Hi
Hi
Hi
Hi
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Hi
Lo
Hi
Lo
Hi
Lo
Hi
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
ON
OFF
OFF
OFF
ON
ON
OFF
ON
ON
7.3.2.2 External Control of PCHG Output Driver
The PCHG output driver is designed to drive a P-channel FET and is controlled by the PCHG_EN pin. The
PCHG driver provides an option to implement a separate charging path with a P-channel FET to charge the
battery when the cells are deeply depleted. A resistor should be added in series to the P-channel pre-charge
FET to limit the charging current. A pre-charge current is usually at or less than 1/20 of the normal charge
current if the charger does not support lower current pre-charge. Refer to the battery cell specification from the
cell manufacturer charging for the appropriate current limit.
PCHG_EN
Lo (default)
Hi
PCHG
OFF (default)
ON
7.3.2.3 Pack Monitor Enable
The bq76200 device provides an internal-switch control to post the PACK+ voltage on to the PACKDIV pin. A
resistor divider can be connected to the PACKDIV pin externally to divide down the PACK+ voltage into a
measurable range of an MCU. The PMON_EN controls the internal switch between PACK pin and PACKDIV pin.
The internal switch has an on resistance of R(PMONFET). The external resistor divider for PACKDIV pin should be
selected to avoid exceeding the absolute maximum of the PACKDIV pin and should also keep the loading current
< 500 µA. If this function is not used, the PACKDIV pin should leave floating. To reduce power consumption, the
PMON_EN should be enabled only when PACK+ voltage measurement is needed.
PMON_EN
Lo (default)
Hi
PACKDIV
DISABLED (default)
ENABLED
7.4 Device Functional Modes
•
In NORMAL mode, the bq76200 charge pump is turned on by enabling either CP_EN, CHG_EN, or DSG_EN.
In this mode, typically the CHG and DSG outputs are driven to V(BAT) + V(VDDCP)
.
•
In SHUTDOWN mode, the bq76200 is completely powered down. When CHG_EN, DSG_EN, and CP_EN are
driven low, the device enters SHUTDOWN mode, and the outputs are driven low.
DEVICE MODES
NORMAL
SHUTDOWN
CONDITION
CHG_EN = Hi, DSG_EN = Hi, CP_EN = Hi, PCHG_EN = don't care, PMON_EN = don't care
CHG_EN = Lo, DSG_EN = Lo, CP_EN = Lo, PCHG_EN = Lo, PMON_EN = Lo
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The bq76200 device is a high-side NMOS FET driver with integrated charge pump. The device can convert a
low-side battery protection system into a high-side protection system, allowing the battery monitor device or
battery MCU to always maintain communication to the host system regardless if the protection FETs are on or
off. The device provides independent enables to control charge and discharge of a battery pack.
The following section highlights several recommended implementations when using this device. A detail bq76200
Application Note, SLVA729, is available at www.ti.com.
8.1.1 Recommended System Implementation
8.1.1.1 The bq76200 is a Slave Device
The bq76200 is a FET driver. It controls the output pins (CHG, DSG, PCHG, and PACKDIV) according to the
input pin (CHG_EN, DSG_EN, PCHG_EN, CP_EN, and PMON_EN) status. The device does not validate if the
inputs should or should not be turned on or off. For example, if both CHG_EN and PCHG_EN are enabled,
bq76200 will turn on both CHG and PCHG simultaneously, enabling two charging paths to the system. The
system designer should avoid undesirable enable combination via schematic, AFE, or host MCU implementation.
8.1.1.2 Flexible Control via AFE or via MCU
The bq76200 device has simple-logic input pins (CHG_EN, DSG_EN, PCHG_EN, CP_EN, and PMON_EN) that
can accept a control signal from any MCU I/O. At the same time, the input pins are designed to tolerate high
voltage signal such as the FET driver output from an AFE. This flexibility allows a mix of control input driving
from AFE and/or MCU to optimize the system design.
For example, it is recommended to control the CP_EN pin via MCU which the system can turn on the charge
pump at system start-up, excluding the extra FET delay due to charge pump voltage ramping. On the other hand,
the CHG_EN and DSG_EN can be driven by the AFE FET driver output, especially if the AFE has hardware
protection features (such as the bq76920/30/40 family), to optimize the FET reaction time.
All the input pins have internal pull-down resistor. The outputs are default to be off if any of the input pins are at
high-Z state.
8.1.1.3 Scalable VDDCP Capacitor to Support Multiple FETs in Parallel
The bq76200 requires a minimum 470-nF capacitor to be connected between the VDDCP pin and BAT pin in
order to turn on the integrated charge pump. The Electrical Characteristics Specification of this document
specified the device performance based on 10 nF loading with 470-nF VDDCP capacitor. The loading
capacitance varies with FET choices, number of FETs in use, and in parallel and simultaneous switching versus
sequential switching of CHG and DSG FET.
The more FETs that are in parallel, the higher the loading capacitance. Similarly, simultaneously switching of the
CHG and DSG FET loads down the charge pump more than sequentially switching both FETs. Eventually, the
loading capacitance can exceed the supported range of a 470-nF VDDCP capacitor. A > 470-nF VDDCP
capacitor can be used to support higher-loading capacitance.
12
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Application Information (接下页)
t!/Y+
bq76200
VDDCP
CHG
NC
100 ꢀ
CVDDCP
BAT
NC
PCHG
NC
0.01 µF
CHG_EN
CP_EN
DSG_EN
DSG
PACK
PMON_EN PACKDIV
PCHG_EN
VSS
t!/Y-
图 8. Scale CVDDCP to Support Multiple FETs in Parallel (Partial Schematic Shown)
Based on test results, 470-nF VDDCP capacitor can support up to approximately 30-nF loading capacitance.
Using a 470-nF/20-nF ratio (to include some design margin), a 2.1-µF VCCDP capacitor can support up to ~90
nF loading capacitance. Note that a larger VDDCP capacitor increases the charge pump start up time; a higher
loading capacitance increases the FET on and off time. System designers should test across the operation range
to ensure the design margin and system performance. Refer to the bq76200 Application note for more test
results.
Also notice that any damage or disconnection of the VDDCP capacitor during operation can leave a residual
voltage on the FET driver output if the inputs are enabled. This can result in putting the external FETs in a high-
Rdson state and cause FET damage.
8.1.1.4 Pre-Charge and Pre-Discharge Support
For a deeply depleted battery pack, a much lower charging current, for example, a C/10 rate, is usually used to
pre-charge the battery cells. This allows the passivating layer of the cell to be recovered slowly (the passivating
layer might be dissolved in the deep discharge state).
The bq76200 has a PCHG output to drive an external P-channel FET to support battery pre-charge. In this
scenario, the external P-channel FET is placed in parallel with the CHG FET and a power resistor can be
connected in series of the P-channel FET to limit the charging current during the pre-charge state. The MCU can
be used to control the PCHG_EN pin to determine the entry and exit of the pre-charge mode.
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Application Information (接下页)
Rpchg
t!/Y+
bq76200
VDDCP
CHG
NC
100 ꢀ
470 nF
0.01 µF
BAT
NC
PCHG
NC
CHG_EN
CP_EN
DSG_EN
DSG
PACK
PMON_EN PACKDIV
PCHG_EN
VSS
From MCU
t!/Y-
图 9. P-channel FET in Parallel With CHG FET for Pre-Charging (Partial Schematic Shown)
Alternatively, the CHG pin can also be used to pre-charge a battery pack given if the charging current is
controlled by the system (i.e. does not require external component to limit the charging current such as a smart
charger) and the battery stack voltage is higher than minimum operation voltage of the bq76200 (i.e. the charge
pump can start to turn on the CHG FET). PCHG should leave floating if it is not used in the application.
The PCHG output can be used to pre-discharge a high-capacitive system. For example, a load removal can be
one of the recovery requirements after a discharge related fault has been detected. In a high-capacitive system,
the residual voltage at the system side can take a significant time to bleed off. This results in an additional delay
in fault recovery. The PCHG output can be used to control an external P-channel FET placed in parallel with the
DSG FET to pre-discharge the residual voltage in order to speed up the fault recovery process.
14
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Application Information (接下页)
Rpdsg
t!/Y+
10 Mꢀ
10 Mꢀ
bq76200
VDDCP
CHG
NC
100 ꢀ
470 nF
0.01 µF
BAT
NC
PCHG
NC
CHG_EN
CP_EN
DSG
PACK
DSG_EN
PMON_EN PACKDIV
PCHG_EN
VSS
From MCU
t!/Y-
图 10. P-channel FET in Parallel with DSG FET for Pre-Discharging (Partial Schematic Shown)
8.1.1.5 Optional External Gate Resistor
The CHG and DSG have certain internal on and off resistance. However, an optional external gate resistor can
be added to CHG and/or DSG FET to slow down the FET on and off timing.
8.1.1.6 Separate Charge and Discharge paths
In some systems, the charging current might be significantly lower than the discharge current. In such systems,
the system designer may prefer to implement a separate charge and discharge paths in which the number of
FET in parallel for charge and discharge can be different to reduce to BOM cost.
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Application Information (接下页)
/harge
5ischarge
bq76200
VDDCP
CHG
NC
100 ꢀ
470 nF
BAT
NC
PCHG
NC
0.01 µF
CHG_EN
CP_EN
DSG_EN
DSG
PACK
PMON_EN PACKDIV
PCHG_EN
VSS
t!/Y-
图 11. Separate Charge and Discharge Paths (Partial Schematic Shown)
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8.2 Typical Applications
1 Mꢀ
Rpchg
10 Mꢀ
Rgs
Rc
Cc
t!/Y+
10 Mꢀ
Rgs
10 Mꢀ
Rgs
Rc
Cc
Rc
Cc
Rc
Cc
Rc
Cc
VC10x
Cc
Rc
B
Analog Front End
VC15
Rf
Rc
Cc
470 nF
CVDDCP
100 ꢀ
Rfilter
bq76200
100 ꢀ
Rfilter
VC14
VC13
VC12
VC11
VC10b
VC10
VC9
BAT
CHG
NC
VDDCP
Rc
Cc
CAP3
BAT
0.01 µF
Cfilter
TS3
PCHG
NC
NC
Cf
Rc
Cc
10k
10k
1 µF
1 µF
Rf
Rf
CHG_EN
CP_EN
DSG_EN
DSG
PACK
Rc
Cc
VC10x
CAP2
A
0.01 µF
Cfilter
PMON_EN PACKDIV
VC8
TS2
Cf
Rc
Cc
PCHG_EN
VSS
bq76940
VC7
VC6
VC5b
VC5
VC4
VC3
VC2
VC1
VC0
SRP
SRN
ALERT
VC5x
Ra
Cc
Rc
VC5x
REGSRC
REGOUT
CAP1
A
Rc
Cc
10 kΩ
10 kꢀ
Rc
Cc
TS1
1 µF
Cf
1 µF
4.7 µF
SCL
SDA
VSS
CHG
DSG
Rc
Cc
Rc
Cc
GPIO
GPIO
GPIO
VCC
SCL
PUSH-BUTTON FOR BOOT
Rc
Cc
ADC_IN
µC
SDA
GPIO
VSS
Cc
Rc
Rb
0.1 µF 0.1 µF 0.1 µF
100 ꢀ
100 ꢀ
Rsns
t!/Y-
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 2.
表 2. Design Parameters
PARAMETER
EXTERNAL COMPONENT
NOTE
BAT and PACK Filters
Rfilter and Cfilter
Recommended to use 100 Ω and 0.01 µF.
A minimum of 470 µF is required. A higher value can be used to
support higher-loading capacitance. See Recommended
Implementation and bq76200 Application Note () for details.
VDDCP capacitor
CVDDCP
Ra and Rb
Rgs
Based on the max PACK voltage of the application, calculate the
total value of (Ra + Rb) that can keep the PACKDIV current below
500 µA.
PACKDIV resistor divider
Recommended to use 10 MΩ. A different Rgs value may change the
loading level of the charge pump. System designer should perform
thorough system testing if a different Rgs is used.
CHG, DSG, PCHG gate-source
resistor
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8.2.2 Detailed Design Procedure
1. Determine if CP_EN pin will be driven by MCU. It is highly recommended to use CP_EN to turn on the
charge pump at system start-up. However, it is not a must to operate the bq76200 to switch on CHG and
DSG pins. System designer should ensure the FET's turn on time is acceptable during normal operation if
CP_EN is not enabled at system startup.
2. Select the correct VDDCP capacitance. Scaling up the VDDCP capacitance allows support for a higher
number of FETs in parallel. This test result of various parallel FETs versus VDDCP capacitance in the
bq76200 application is for general reference only. System designer should always validate their design
tolerant across operation temperature range.
3. If the PMON_EN is used, the PACKDIV resistor divider, Ra and Rb, must be selected to satisfy (Ra+Rb) <
500uA, AND [Rb/(Ra + Rb)] < (max ADC input range)/(max PACK+ voltage). For example, In a 48V system,
if the max charger voltage is 50.4V and a MCU's max ADC input is 3V. To meet both (Ra + Rb) < 500uA,
AND [Rb/(Ra + Rb)] < (3V/50.4V) requirements, the Ra value might be 100 kΩ or less and Rb value might be
6 KΩ or less.
4. Follow the application schematic (see Typical Applications) to connect the device.
8.2.3 Application Curves
CHG output reacts to the CHG_EN signal immediately. Similar
behavior applies to DSG pin.
CHG output reacts to the CHG_EN signal after charge pump
startup delay. Similar behavior applies to DSG pin.
图 12. CHG_EN Switched On After Charger Pump Turns
图 13. CHG_EN Enabled Before Charge Pump is Turned
On and is Stable
On
With 10 nF loading and no Rgs on DSG output. Note the time scale was 800ns/div. Hence, the DSG waveform above was
basically the DSG FET fall time
图 14. DSG_EN to DSG Output Propagation Delay
18
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ZHCSED8 –NOVEMBER 2015
9 Power Supply Recommendations
The maximum recommended operation voltage on the BAT and PACK pins is 75 V. The charge pump, when it
turns on, will add 14 V maximum voltage on top of the BAT or PACK voltage to the device, pushing the total
device voltage to approximately 89 V.
The bq76200 has high voltage (100 V) tolerant pins, but system designer should take into account the worse-
case transient voltage and the maximum charge pump on voltage to determine the maximum voltage applying to
BAT and PACK pins.
10 Layout
10.1 Layout Guidelines
For the following procedure, see 图 15 and 图 16.
1. Place CVDDCP capacitor close to the device.
2. Place BAT and PACK RC filters close to the device.
3. Generally, a typical system using an AFE, MCU, and bq76200 usually have a high-current ground
trace/plane and low-current ground plane in the PCB layout. If so, the bq76200 ground should be connected
to the low-current ground plane of the PCB layout to remove noise affecting the ENABLE signals.
10.2 Layout Example
PACK+
bq76200
CHG
NC
VDDCP
BAT
100 ꢀ
CVDDCP
NC
PCHG
NC
0.01 µF
CHG_EN
CP_EN
100 ꢀ
DSG
DSG_EN
PMON_EN
PCHG_EN
PACK
PACKDIV
VSS
0.01 µF
PACK-
Place these components close to the device pins
图 15. Place CVDDCP and Filter Components Close to Device
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Layout Example (接下页)
Power Trace Line
PACK+
Low power
ground plane
bq76200
bq76200 ground should connect to
the low power ground plane of the
PCB layout
Battery
cell
stack
comm
AFE
MCU
Rsense
PACK-
Low power ground and high power
ground connect here
图 16. Connect bq76200 to Low Power Ground Plane on PCB Layout
20
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ZHCSED8 –NOVEMBER 2015
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
如需相关文档，请参见《bq76200 FET 配置测试结果》（文献编号：SLVA729）。
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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Copyright © 2015, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ76200PW
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
16
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
BQ7620B
BQ7620B
BQ76200PWR
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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