BQ4013MA-85N [TI]
IC,NOVRAM,128KX8,CMOS,DIP,32PIN,PLASTIC;
| 型号： | BQ4013MA-85N |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,NOVRAM,128KX8,CMOS,DIP,32PIN,PLASTIC 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总13页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq4013/Y
128Kx8 Nonvolatile SRAM
The bq4013/Y uses an extremely
Features
General Description
low standby current CMOS SRAM,
coupled with a small lithium coin
cell to provide nonvolatility without
long write-cycle times and the
write-cycle limitations associated
with EEPROM.
➤ Data retention for at least 10
The CMOS bq4013/Y is a nonvolatile
1,048,576-bit static RAM organized as
131,072 words by 8 bits. The integral
control circuitry and lithium energy
source provide reliable nonvolatility
coupled with the unlimited write cy-
cles of standard SRAM.
years without power
➤ Automatic write-protection during
power-up/power-down cycles
➤ Conventional SRAM operation,
The bq4013/Y requires no external
circuitry and is socket-compatible
with industry-standard SRAMs and
most EPROMs and EEPROMs.
including unlimited write cycles
The control circuitry constantly
monitors the single 5V supply for an
out-of-tolerance condition. When
➤ Internal isolation of battery be-
fore power application
➤ Industry standard 32-pin DIP
V
CC falls out of tolerance, the SRAM
pinout
is unconditionally write-protected to
prevent inadvertent write operation.
At this time the integral energy
source is switched on to sustain the
memory until after VCC returns valid.
Pin Connections
Pin Names
A0–A16
Address inputs
WE
NC
Write enable input
No connect
DQ0–DQ7 Data input/output
CE
OE
Chip enable input
VCC
VSS
Supply voltage input
Ground
Output enable input
Selection Guide
Maximum
Negative
Supply
Tolerance
Maximum
Negative
Supply
Tolerance
Part
Number
Access
Part
Number
Access
Time (ns)
Time (ns)
bq4013YMA -70
bq4013YMA -85
bq4013YMA-120
70
85
-10%
-10%
-10%
bq4013MA -85
bq4013MA-120
85
-5%
-5%
120
120
9/96 D
1
bq4013/Y
As VCC falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
which provides data retention until valid VCC is applied.
Functional Description
When power is valid, the bq4013/Y operates as a stan-
dard CMOS SRAM. During power-down and power-up
cycles, the bq4013/Y acts as a nonvolatile memory, auto-
matically protecting and preserving the memory con-
tents.
When VCC returns to a level above the internal backup
cell voltage, the supply is switched back to VCC
. After
VCC ramps above the VPFD threshold, write-protection
continues for a time tCER (120ms maximum) to allow for
processor stabilization. Normal memory operation may
resume after this time.
Power-down/power-up control circuitry constantly moni-
tors the VCC supply for a power-fail-detect threshold
V
PFD. The bq4013 monitors for VPFD = 4.62V typical for
The internal coin cell used by the bq4013/Y has an ex-
tremely long shelf life and provides data retention for
more than 10 years in the absence of system power.
use in systems with 5% supply tolerance. The bq4013Y
monitors for VPFD = 4.37V typical for use in systems
with 10% supply tolerance.
As shipped from Unitrode, the integral lithium cell of
the MA-type module is electrically isolated from the
memory. (Self-discharge in this condition is approxi-
mately 0.5% per year.) Following the first application of
When VCC falls below the VPFD threshold, the SRAM au-
tomatically write-protects the data. All outputs become
high impedance, and all inputs are treated as “don’t
care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to com-
pletion. If the memory cycle fails to terminate within
time tWPT, write-protection takes place.
V
CC, this isolation is broken, and the lithium backup cell
provides data retention on subsequent power-downs.
Block Diagram
OE
A –A
0
16
128K x 8
SRAM
Block
WE
DQ –DQ
0
7
Power
CE
CE
CON
V
CC
Power-Fail
Control
Lithium
Cell
BD-42
2
bq4013/Y
Truth Table
Mode
Not selected
Output disable
Read
CE
H
L
WE
X
OE
X
I/O Operation
High Z
High Z
DOUT
Power
Standby
Active
Active
Active
H
H
L
L
H
Write
L
L
X
DIN
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
DC voltage applied on any pin excluding VCC
relative to VSS
VT
VT ≤ VCC + 0.3
-0.3 to 7.0
V
0 to +70
-40 to +85
-40 to +70
-40 to +85
-10 to +70
-40 to +85
+260
°C
°C
°C
°C
°C
°C
°C
Commercial
TOPR
Operating temperature
Storage temperature
Temperature under bias
Industrial “N”
Commercial
TSTG
Industrial “N”
Commercial
TBIAS
Industrial “N”
For 10 seconds
TSOLDER Soldering temperature
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con-
ditions beyond the operational limits for extended periods of time may affect device reliability.
3
bq4013/Y
Recommended DC Operating Conditions (T = T
)
OPR
A
Symbol
Parameter
Minimum
4.5
Typical
Maximum
Unit
V
Notes
5.0
5.0
0
5.5
5.5
bq4013Y
bq4013
VCC
Supply voltage
4.75
0
V
VSS
VIL
VIH
Supply voltage
0
V
Input low voltage
Input high voltage
-0.3
-
0.8
V
2.2
-
VCC + 0.3
V
Note:
Typical values indicate operation at TA = 25°C.
DC Electrical Characteristics (T = T
≤ V
≤ V
CC CCmax)
A
OPR, VCCmin
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions/Notes
VIN = VSS to VCC
ILI
Input leakage current
-
-
1
µA
CE = VIH or OE = VIH or
WE = VIL
µA
ILO
Output leakage current
-
-
1
VOH
VOL
ISB1
Output high voltage
Output low voltage
Standby supply current
2.4
-
-
-
0.4
7
V
V
IOH = -1.0 mA
IOL = 2.1 mA
CE = VIH
-
-
4
mA
CE ≥ VCC - 0.2V,
0V ≤ VIN ≤ 0.2V,
or VIN ≥ VCC - 0.2V
ISB2
Standby supply current
Operating supply current
-
-
2.5
75
4
mA
mA
Min. cycle, duty = 100%,
CE = VIL, II/O = 0mA
ICC
105
4.55
4.30
-
4.62
4.37
3
4.75
4.50
-
V
V
V
bq4013
VPFD
Power-fail-detect voltage
Supply switch-over voltage
bq4013Y
VSO
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V.
Capacitance (T = 25°C, F = 1MHz, V
= 5.0V)
CC
A
Symbol
CI/O
Parameter
Minimum
Typical
Maximum
Unit
pF
Conditions
Output voltage = 0V
Input voltage = 0V
Input/output capacitance
Input capacitance
-
-
-
-
10
10
CIN
pF
Note:
These parameters are sampled and not 100% tested.
4
bq4013/Y
AC Test Conditions
Parameter
Test Conditions
0V to 3.0V
5 ns
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
1.5 V (unless otherwise specified)
See Figures 1 and 2
Figure 1. Output Load A
Figure 2. Output Load B
Read Cycle (T = T
≤ V
≤ V
CC CCmax)
A
OPR, VCCmin
-70/-70N
-85/-85N
-120
Min. Min. Min. Max. Min. Max.
Symbol
tRC
Parameter
Read cycle time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
70
-
-
85
-
-
120
-
-
120
120
60
-
tAA
Address access time
70
70
35
-
85
85
45
-
Output load A
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
tACE
tOE
Chip enable access time
-
-
-
Output enable to output valid
Chip enable to output in low Z
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output in high Z
Output hold from address change
-
-
-
tCLZ
tOLZ
tCHZ
tOHZ
tOH
5
0
0
0
10
5
0
0
0
10
5
-
-
0
-
25
25
-
35
25
-
0
45
35
-
0
10
5
bq4013/Y
Read Cycle No. 1 (Address Access) 1,2
Read Cycle No. 2 (CE Access) 1,3,4
1,5
Read Cycle No. 3 (OE Access)
Notes:
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL
.
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL
5. Device is continuously selected: CE = VIL
.
.
6
bq4013/Y
Write Cycle (T =T
≤ V
≤ V
)
CCmax
A
OPR , VCCmin
CC
-70/-70N
-85/-85N
-120
Units
Min. Max. Min. Max. Min. Max.
Symbol
Parameter
Conditions/Notes
tWC
Write cycle time
70
65
-
-
85
75
-
-
120
100
-
-
ns
ns
Chip enable to end of
write
tCW
tAW
tAS
(1)
(1)
Address valid to end of
write
65
0
-
-
75
0
-
-
100
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Measured from address valid
to beginning of write. (2)
Address setup time
Write pulse width
Measured from beginning of
write to end of write. (1)
tWP
tWR1
tWR2
tDW
tDH1
tDH2
tWZ
55
5
-
65
5
-
85
5
-
Write recovery time
(write cycle 1)
Measured from WE going high
to end of write cycle. (3)
-
-
-
Write recovery time
(write cycle 2)
Measured from CE going high
to end of write cycle. (3)
15
30
0
-
15
35
0
-
15
45
0
-
Data valid to end of
write
Measured to first low-to-high
transition of either CE or WE.
-
-
-
Data hold time
(write cycle 1)
Measured from WE going high
to end of write cycle. (4)
-
-
-
Data hold time
(write cycle 2)
Measured from CE going high
to end of write cycle. (4)
10
0
-
10
0
-
10
0
-
Write enabled to output
in high Z
25
-
30
-
40
-
I/O pins are in output state. (5)
I/O pins are in output state. (5)
Output active from end
of write
tOW
0
0
0
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
7
bq4013/Y
1,2,3
Write Cycle No. 1 (WE-Controlled)
1,2,3,4,5
Write Cycle No. 2 (CE-Controlled)
Notes:
1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
8
bq4013/Y
Power-Down/Power-Up Cycle (T = T
A
OPR)
Typical
Symbol
tPF
Parameter
Minimum
Maximum
Unit
µs
Conditions
VCC slew, 4.75 to 4.25 V
VCC slew, 4.25 to VSO
300
10
0
-
-
-
-
-
-
tFS
µs
tPU
VCC slew, VSO to VPFD (max.)
µs
Time during which
SRAM is
tCER
Chip enable recovery time
40
80
120
ms
write-protected after
V
CC passes VPFD on
power-up.
Data-retention time in
absence of VCC
tDR
TA = 25°C. (2)
10
6
-
-
-
-
years
years
Data-retention time in
absence of VCC
TA = 25°C (2); industrial
temperature range only
tDR-N
Delay after VCC slews
down past VPFD before
SRAM is
µs
tWPT
Write-protect time
40
100
150
write-protected.
Notes:
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
9
bq4013/Y
MA: 32-Pin A-Type Module
Dimension
Minimum
0.365
0.015
0.017
0.008
1.670
0.710
0.590
0.090
0.120
0.075
Maximum
0.375
-
A
A1
B
C
D
E
e
0.023
0.013
1.700
0.740
0.630
0.110
0.150
0.110
G
L
S
All dimensions are in inches.
MS: 34-Pin Leaded Chip carrier for LIFETIME LITHIUM Module
34-Pin LCR LIFETIME LITHIUM Module
Dimension
Minimum
0.920
0.980
-
Maximum
0.930
0.995
0.080
0.060
0.055
0.025
0.030
0.090
0.073
A
B
C
D
E
F
G
H
J
0.052
0.045
0.015
0.020
-
0.053
All dimensions are in inches.
1
2
3
Centerline of lead within ±±0±±ꢀ of true position0
Leads coplanar within ±±0±±ꢁ at seatinꢂ plane0
Components and location may vary0
10
bq4013/Y
MS: LIFETIME LITHIUM Module Housing
LIFETIME LITHIUM Module Housing
Dimension
Minimum
0.845
Maximum
0.855
A
B
C
D
E
0.955
0.965
0.210
0.220
0.065
0.075
0.065
0.075
All dimensions are in inches.
1
Edꢂes coplanar within ±±0±2ꢀ0
MS: LIFETIME LITHIUM Module with LCR attached
LIFETIME LITHIUM Module
Dimension
Minimum
0.955
Maximum
A
B
C
D
E
F
0.965
0.995
0.250
0.060
0.055
0.025
0.980
0.240
0.052
0.045
0.015
All dimensions are in inches.
1
2
Leads coplanar within ±±0±±ꢁ at seatinꢂ plane0
Components and location may vary0
11
bq4013/Y
Data Sheet Revision History
Change No.
Page No.
2, 3, 4, 6, 8, 9
1, 4, 6, 9
Description
Added industrial temperature range.
1
2
3
Added 70ns speed grade for bq4013Y-70.
Removed industrial temperature range for bq4013YMA-120N
Notes:
Change 1 = Sept. 1992 B changes from Sept. 1990 A.
Change 2 = Aug. 1993 C changes from Sept. 1991 B.
Change 3 = Sept. 1996 D changes from Aug. 1993 C.
Ordering Information
bq4013 xx -
Temperature:
blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)1
Speed Options:
70 = 70 ns
85 = 85 ns
120 = 120 ns
Package Option:
MA = A-type Module
Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance
Device:
bq4013 128K x 8 NVSRAM
Notes:
1. Only 10% supply MA module (“Y-MA”) version is available in industrial
temperature range; contact factory for speed grade availability.
12
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13
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