BQ296229DSGR [TI]
适用于 2 节、3 节和 4 节串联锂离子电池的过压保护 | DSG | 8 | -40 to 110;型号: | BQ296229DSGR |
厂家: | TEXAS INSTRUMENTS |
描述: | 适用于 2 节、3 节和 4 节串联锂离子电池的过压保护 | DSG | 8 | -40 to 110 电池 光电二极管 |
文件: | 总31页 (文件大小:2647K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
BQ2961, BQ2962
SLUSBU5P – NOVEMBER 2013 – REVISED AUGUST 2021
BQ296xxx Overvoltage Protection for 2-Series, 3-Series, and 4-Series Cell
Li-Ion Batteries with Regulated Output Supply
1 Features
3 Description
•
•
•
2-series, 3-series, and 4-series cell overvoltage
protection (OVP)
Fixed delay timer to trigger FET drive output
(3-s, 4-s, 5.5-s, or 6.5-s options)
Factory programmed OVP threshold (threshold
range 3.85 V to 4.6 V)
Output options: active high
High-accuracy overvoltage protection:
±10 mV
The BQ296xxx family is a high-accuracy, low-power
overvoltage protector with a 2-mA regulated output
supply for Li-ion battery pack applications.
Each cell in a 2-series to 4-series cell stack is
individually monitored for an overvoltage condition. An
internally fixed-delay timer is initiated upon detection
of an overvoltage condition on any cell. Upon
expiration of the delay timer, an output pin is triggered
into an active state to indicate that an overvoltage
condition has occurred.
•
•
•
Regulated supply output with self-disable and/or
external enable/disable control
The regulated output supply delivers up to 2-mA
(max) output current to drive always-on circuits, such
as a real-time clock (RTC) oscillator. The BQ296xxx
family has a self-disable function to turn off the
regulated output if any cell voltage falls below a
certain threshold, thereby preventing drain on the
battery, and provides an external control to enable or
disable the regulated output.
– Options: 3.3 V, 2.5 V, and 1.8 V (BQ2961)
– Options: 3.3 V, 3.15 V, 3.0 V (BQ2962)
Low power consumption ICC ~ 4 µA
•
•
(VCELL(ALL) < VPROTECT
)
Extra low power consumption with reg output
disabled, ICC ~ 1.2 µA
Low leakage current per cell input < 100 nA
Small package footprint
•
•
– 8-Pin WSON (2 mm × 2 mm)
Device Information
PART NUMBER(1)
BQ2961
PACKAGE
BODY SIZE (NOM)
2 Applications
•
•
•
•
Notebook PC
Ultrabooks
Medical
WSON (8)
2.00 mm × 2.00 mm
BQ2962
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
UPS battery backup
Pack +
Protector
FETs
100 Ω
OUT
REG
VDD
V4
External
Circuit
e.g., RTC
1 kΩ
5 ꢀ (*)
0.1µF
0.1µF
0.1µF
VCELL4
VCELL3
1 kΩ
1 kΩ
V3
V2
VSS
V1
* can be removed if Vss will be
connected first during cell
connection
PWPD
VCELL2
VCELL1
1 kΩ
0.1µF
0.47 µF
0.1µF
Pack œ
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
BQ2961, BQ2962
SLUSBU5P – NOVEMBER 2013 – REVISED AUGUST 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................11
9 Application and Implementation..................................13
9.1 Application Information............................................. 13
9.2 Typical Application.................................................... 13
10 Power Supply Recommendations..............................15
11 Layout...........................................................................16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................16
12.1 Third-Party Products Disclaimer............................. 16
12.2 Receiving Notification of Documentation Updates..16
12.3 Support Resources................................................. 16
12.4 Trademarks.............................................................16
12.5 Electrostatic Discharge Caution..............................17
12.6 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision O (July 2021) to Revision P (August 2021)
Page
•
Changed the BQ296227 and BQ296233 devices to Production Data in the Device Comparison Table ...........3
Changes from Revision N (June 2021) to Revision O (July 2021)
Page
•
Changed the BQ296115 device to Production Data in the Device Comparison Table ...................................... 3
Changes from Revision M (June 2021) to Revision N (June 2021)
Page
•
Added the BQ296227 and BQ296233 PRODUCT PREVIEW devices to the Device Comparison Table ......... 3
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5 Device Comparison Table
Table 5-1. BQ2961 Device Options
BQ2961
BQ296100
BQ296103
BQ296106
BQ296107
BQ296111
BQ296112
BQ296113
BQ296114
BQ296115
BQ296116(1)
BQ2961
OVP (V)
OVP DELAY (s)
UV (V)
LDO (V)
4.35
6.5
2.5
3.3
3.3
4.50
6.5
2.5
4.45
6.5
2.8
3.3
4.50
6.5
2.8
3.3
4.45
4.0
2.5
3.3
4.50
3.0
2.5
3.3
4.35
3.0
2.5
3.3
4.50
4.0
2.5
3.3
4.25
4.50
6.5
6.5
2.0
2.5
2.5
1.8
3.85 V–4.60 V (50-mV step)
3.0, 4.0, 5.5, 6.5
2.0 V–2.8 V (50-mV step)
1.8, 2.5, 3.3
(1) PRODUCT PREVIEW. Contact TI for more information.
Table 5-2. BQ2962 Device Options
BQ2962
OVP (V)
4.45
4.50
4.50
4.35
4.50
4.55
4.55
4.55
4.50
4.50
4.50
4.5
OVP DELAY (s)
UV (V)
LDO (V)
3.3
BQ296202
BQ296203
BQ296212
BQ296213
BQ296215
BQ296216
BQ296217
BQ296221
BQ296222
BQ296223
BQ296224
BQ296226
BQ296227
BQ296228
bq296229
BQ296230
BQ296231
BQ296232
BQ296233
BQ2962
6.5
6.5
3.0
3.0
6.5
6.5
6.5
6.5
6.5
6.5
6.5
6.5
6.5
6.5
6.5
6.5
6.5
6.5
6.5
2.5
2.5
3.3
2.5
3.3
2.5
3.3
2.5
3.0
2.5
3.0
2.8
3.3
2.5
3.3
3.0
3.0
2.5
3.3
2.5
3.0
2.8
3.3
4.55
4.55
4.60
4.35
4.60
4.55
4.45
2.8
3.3
2.5
3.0
2.5
3.0
3.0
3.0
2.5
3.3
3.0
2.5
3.0
3.3
3.85 V–4.60 V (50-mV step)
3.0, 4.0, 5.5, 6.5
2.0 V–2.8 V (50-mV step)
3, 3.15, 3.3
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6 Pin Configuration and Functions
OUT
REG
1
2
VDD
V4
8
7
VSS
V1
3
4
V3
V2
6
5
Figure 6-1. 2-Series to 4-Series BQ2961 (Top View)
REG
OUT
1
2
VDD
V4
8
7
VSS
V1
3
4
V3
V2
6
5
Figure 6-2. 2-Series to 4-Series BQ2962 (Top View)
Table 6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
BQ2961
BQ2962
Analog output drive for an overvoltage fault signal; CMOS output high or open-
drain active low
OUT
8
7
OA
PWPD
REG
9
7
9
8
P
TI recommends connecting the exposed pad to VSS on PCB.
OA
Regulated supply output. Requires an external ceramic capacitor for stability
Regulated supply output enable. A "high" to enable REG output and "low" to
disable REG output
REG_EN
—
—
IA
V1
V2
5
4
3
2
1
5
4
3
2
1
IA
IA
IA
IA
P
Sense input for positive voltage of the lowest cell from the bottom of the stack
Sense input for positive voltage of the second cell from the bottom of the stack
Sense input for positive voltage of the third cell from the bottom of the stack
Sense input for positive voltage of the fourth cell from the bottom of the stack
Power supply input
V3
V4
VDD
Electrically connected to integrated circuit ground and negative terminal of the
lowest cell in the stack
VSS
6
6
P
(1) IA = Analog input, OA = Analog Output, P = Power connection
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
30
UNIT
Supply voltage
Input voltage
VDD – VSS
–0.3
V4 – V3, V3 – V2, V2 – V1, V1 – VSS
REG – VSS
–0.3
30
–0.3
3.6
28
V
REG_EN – VSS
OUT – VSS
–0.3
Output voltage
–0.3
See Section 7.4.
300
30
Continuous total power dissipation, PTOT
Lead temperature (soldering, 10 s), TSOLDER
Storage temperature, Tstg
300
150
°C
°C
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
2000
500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
3
NOM
MAX
UNIT
(1)
Supply voltage, VDD
20
Supply voltage,
VDD
V
(1)
Supply voltage, VDD with REG output on
Vn – Vn-1, V1 – VSS
4
0
5
15
V
V
Input voltage
range
REG_EN
0
Operating ambient temperature range, TA
(1) See Section 9.2.
–40
110
°C
7.4 Thermal Information
BQ296xxx
THERMAL METRIC(1)
DSG (WSON)
UNIT
8 PINS
62
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
72
32.5
1.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
33
RθJC(bot)
10
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to +110°C, and VDD
3 V to 15 V (unless otherwise noted).
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Voltage Protection Thresholds
V(PROTECT) Overvoltage
Detection
Applicable Voltage: 3.85 V to
4.6 V in 50-mV steps
VOV
RIN = 1 kΩ
V
VHYS
VOA
OV Detection Hysteresis
OV Detection Accuracy
250
–10
–40
–20
–24
–54
–54
300
400
10
40
20
24
54
54
mV
mV
mV
mV
mV
mV
mV
TA = 25°C
TA = –40°C
TA = 0°C
OV Detection Accuracy
Across Temperature
VOADRIFT
TA = 60°C
TA = 110°C
TA = 110°C
Supply and Leakage Current
(Vn – Vn-1) = 2 V to 4.15 V, n = TA = 0°C to 60°C
Supply Current with REG 1 to 4, VDD = top Vn voltage
4
1
6
8
µA
µA
IDD
on
(V1 – VSS) > VUVREG , IREG = 0
mA,
TA = –40°C to 110°C
(Vn – Vn-1) = 2 V to 4.15 V, n = TA = 0°C to 60°C
1 to 4, VDD = top Vn voltage
TA = –40°C to 110°C
(V1 – VSS) < VUVREG
2
4
µA
µA
Supply Current with REG
off
IDD
(Vn – Vn-1) = (V1 – VSS) = 3.8 V, VDD = top Vn voltage,
TA = 25°C
IIN
Input Current at Vx Pins
–0.1
6
0.1
µA
Output Drive OUT, CMOS Active High
(Vn – Vn-1) or (V1 – VSS) > VOV, IOH = 100 µA, VDD =
top Vn voltage
7
8
V
V
If three of four cells are short circuited, only one cell
remains powered and > VOV, VDD = Vn (the remaining
cell voltage), IOH = 100 µA
Output Drive Voltage,
Active High
VDD –
0.3
VOUT
(Vn – Vn-1) and (V1 – VSS) < VOV, VDD = sum of the
cell stack voltage, IOL = 100 µA measured into OUT pin
250
400
4.5
mV
mA
(Vn – Vn-1), (V3 – V2), or (V1 – VSS) > VOV, VDD = top
Vn voltage,
OUT Source Current
(during OV)
IOUTH
forced OUT = 0 V, measured out of OUT pin
(Vn – Vn-1) and (V1 – VSS) < VOV, VDD = top Vn
voltage, forced OUT = VDD, measured into OUT pin.
Pull-up resistor RPU = 5 kΩ to VDD
OUT Sink Current (no
OV)
IOUTL
0.5
14
mA
Internal Fixed Delay Timer
Internal Fixed Delay, 3-s delay option
Internal Fixed Delay, 4-s delay option
Internal Fixed Delay, 5.5-s delay option
Internal Fixed Delay, 6.5-s delay option
2.4
3.2
4.4
5.2
3
4
3.6
4.8
6.6
7.8
s
s
s
s
tDELAY
OV Delay Time(1)
5.5
6.5
Fault Detection Delay
Time in Test Mode OV
Delay Time
tDELAY_CTM
Internal Fixed Delay
15
ms
OV delay timer count
reset time; tDELAY resets
when the cell voltage
tDELAY_RESET
Internal Fixed Delay
0.6
ms
falls below VOV for
(1)
tDELAY_RESET
.
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7.5 Electrical Characteristics (continued)
Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to +110°C, and VDD
=
3 V to 15 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Regulated Supply Output, REG
VREG = 3.3 V,
3.234
3.087
3.300
3.150
3.366
3.213
VREG = 3.15 V,
BQ2962
VREG = 3.0 V,
BQ2962
REG Supply at
500 µA load
VDD ≥ 4 V, IREG = 500 µA,
CREG = 0.47 µF
2.940
2.450
1.764
3.200
3.050
2.900
2.425
3.000
2.500
1.800
3.300
3.150
3.000
2.500
1.800
3.060
V
VREG
VREG = 2.5 V,
BQ2961
2.550
1.836
3.400
3.250
VREG = 1.8 V,
BQ2961
VREG = 3.3 V,
BQ2961, BQ2962
VREG = 3.15 V,
BQ2962
VDD ≥ 4 V, IREG = 0 µA to 2
mA,
CREG = 0.47 µF
REG Supply from 0 to 2
mA load
VREG = 3.0 V,
BQ2962
VREG
3.100
2.575
V
VREG = 2.5 V,
BQ2961
VREG = 1.8 V,
BQ2961
1.746
1.854
2
IREG
REG Current Output
VDD ≥ 4 V, CREG = 0.47 µF
REG = VSS, CREG = 0.47 µF
REG is disabled.
0
4
mA
mA
kΩ
REG Output Short Circuit
Current Limit
IREG_ SC_Limit
RREG_ PD
REG pull-down resistor
20
30
45
Regulated Supply Output Enable, REG_EN
VIH
VIL
High-level Input
1.6
V
V
Low-level Input
0.4
0.1
ILKG
Input Leakage Current
VIH < 6 V
µA
Regulated Supply Undervoltage Self-Disable
Factory Configuration: 2.0 V to 2.8 V in 50 mV steps,
TA = 25°C
VUVREG
VUVHYS
tUVDELAY
VUVQUAL
Undervoltage detection
–50
250
4.5
50
400
7.5
mV
mV
s
Undervoltage Detection
Hysteresis
300
6
Undervoltage Detection
Delay
Cell voltage to qualify for
UV detection
0.5
V
(1) Specified by design. Not 100% tested in production.
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7.6 Typical Characteristics
15
10
5
350
340
330
320
310
300
290
280
Mean
Min
Max
0
-5
-10
-15
-20
-25
Mean
Min
Max
-60
-40
-20
0
20
40
60
80
100 120
-60
-40
-20
0
20
40
60
80
100 120
Temperature (èC)
Temperature (èC)
D002
D001
Figure 7-2. Hysteresis VHYS vs. Temperature
Figure 7-1. Overvoltage Threshold (VOV) vs.
Temperature
5
5
4.5
4
0
-5
3.5
3
-10
-15
Mean
Min
Max
Mean
Min
Max
2.5
-20
-60
2
-60
-40
-20
0
20
40
60
80
100 120
-40
-20
0
20
40
60
80
100 120
Temperature (èC)
Temperature (èC)
D003
D004
Figure 7-3. Undervoltage Accuracy
Figure 7-4. IDD with Regulator On
3.31
3.305
3.3
1.4
Mean
Min
Max
1.2
1
0.8
0.6
0.4
0.2
0
3.295
3.29
Mean
Min
Max
3.285
-60
-40
-20
0
20
40
60
80
100 120
-60
-40
-20
0
20
40
60
80
100 120
Temperature (èC)
D006
Temperature (èC)
D005
Figure 7-6. Regulator Output Without Load
Figure 7-5. IDD with Regulator Off
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-3.35
-3.4
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8
7
6
5
4
3
2
1
0
Mean
Min
Max
-3.45
-3.5
-3.55
-3.6
-3.65
-3.7
-60
-40
-20
0
20
40
60
80
100 120
0
5
10
15
Supply Voltage (V)
20
25
30
Temperature (èC)
D008
D009
Figure 7-7. IOUTH vs Temperature
Figure 7-8. VOUT vs VDD
8 Detailed Description
8.1 Overview
The BQ2961 and BQ2962 devices are second-level overvoltage (OV) protectors with a regulated output. Each
cell is monitored independently by comparing the actual cell voltage to an overvoltage threshold VOV. The
overvoltage threshold is preprogrammed at the factory with a range between 3.85 V to 4.65 V.
The regulated output is enabled unless any of the cell voltages fall below the VUVREG threshold. This threshold is
preprogrammed at the factory with a range between 2 V to 2.8 V.
Table 8-1. Programmable Parameters
OVERVOLTAGE RANGE (V)
OVERVOLTAGE DELAY (s)
UNDERVOLTAGE RANGE (V)
REGULATOR (V)
1.8, 2.5, 3.3 (BQ2961)
3.0, 3.15, 3.3 (BQ2962)
3.85 to 4.6 in 50-mV step
3, 4, 5.5, 6.5
2.0 to 2.8 in 50-mV step
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8.2 Functional Block Diagram
PACK+
R
VD
C
VD
VDD
1
Vref
V4
R
+
Amp
IN
2
-
Comp
C
IN
+
R
V3
IN
UVP_Vref
3
4
5
-
REG
7
REG_EN
C
C
C
IN
IN
IN
R
R
V2
V1
IN
IN
Programmable
setting
Enable
Active
V
OV
OUT
8
Delay
Timer
Delay Charging/
Discharge circuit
REG_EN
VSS
6
9
PWPD
PACKœ
8.3 Feature Description
8.3.1 Pin Details
8.3.1.1 Input Sense Voltage, Vx
These inputs sense each battery cell voltage. A series resistor and a capacitor across the cell for each input is
required for noise filtering and stable voltage monitoring.
8.3.1.2 Output Drive, OUT
This terminal serves as the fault signal output in active high.
8.3.1.3 Supply Input, VDD
This terminal is the unregulated input power source for the device. A series resistor is connected to limit the
current, and a capacitor is connected to ground for noise filtering.
8.3.1.4 Regulated Supply Output, REG
This terminal is connected to an external capacitor and provides a regulated supply to power a circuit such as a
real-time clock integrated circuit, or functions requiring a well-regulated supply. Maximum current load on this pin
cannot exceed IREG mA.
The REG output has protection for overcurrent, using a current limit protection circuit, and also detects and
protects for excessive power dissipation due to short circuit of the external load. This pin requires a ceramic 1-µF
capacitor connection to VSS for improved stability, noise immunity, and ESD performance of the supply output.
This capacitor must be placed close to the REG and VSS pins for connection.
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8.3.2 Overvoltage Sensing for OUT
In the BQ296xxx device, each cell is monitored independently. Overvoltage is detected by comparing the actual
cell voltage to a protection voltage reference, VOV. If any cell voltage exceeds the programmed OV value, an
internal timer circuit is activated. This timer circuit causes a factory pre-programmed fixed delay before the OUT
terminal goes from inactive to active state.
VOV
VOV - VHYS
tDELAY
OUT (V)
Figure 8-1. Timing for Overvoltage Sensing for OUT
8.3.3 Regulated Output Voltage and REG_EN Pin
For BQ2961, there are three factory-preprogrammed options for the regulated output voltage, 3.3 V, 2.5 V, and
1.8 V. For BQ2962, the regulated output voltage options are 3.3 V, 3.15 V, and 3.0 V. Potentially, the BQ2962xy
device can provide other regulated voltage output between 3.3 V to 3.0 V. Contact Texas Instruments for details.
At power up, the regulated output is on by default. If any cell voltage is below VUVREG at device power up, the
regulated output will remain on until the tUV_DELAY time has passed, the regulated output turns off after the delay
time.
During discharge, if any cell voltage falls below the VUVREG threshold for tUV_DELAY time, the regulated output is
self-disabled. The regulated output turns on again when all the cell voltages are above VUVREG + VUVHYS
.
VUVREG + VUVHYS
VUVREG
tUVDELAY
REG (V)
Figure 8-2. REG Output Timing
8.4 Device Functional Modes
8.4.1 NORMAL Mode
When all of the cell voltages are below the VOV threshold AND above VUVREG threshold, the device operates
in NORMAL mode. The device monitors the differential cell voltages connected across (V1–VSS), (V2–V1), (V3–
V2), and (V4–V3). The OUT pin is inactive in this mode. The regulated output is always enabled for BQ2961.
8.4.2 OVERVOLTAGE Mode
OVERVOLTAGE mode is detected if any of the cell voltages exceed the overvoltage threshold, VOV, for a
configured OV delay time. The OUT pin is activated after a delay time preprogrammed at the factory. The OUT
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pin will pull high internally. Then an external FET is turned on, shorting the fuse to ground, which allows the
battery and/or charger power to blow the fuse. When all of the cell voltages fall below (VOV – VHYS), the device
returns to NORMAL mode. The regulated output (if enabled) remains on in this mode.
8.4.3 UNDERVOLTAGE Mode
The UNDERVOLTAGE mode is detected if any of the cell voltage across (V1–VSS), (V2–V1), (V3–V2), or (V4–
V3) is below the VUVREG threshold for tUV_DELAY time. In this mode, the regulated output is disabled. To return to
the NORMAL mode, all the cell voltages must be above (VUVREG + VUVHYS).
For a low cell configuration, Vn pin can be shorted to the (Vn – 1) pin. The device ignores any differential cell
voltage below VUVQUAL threshold for undervoltage detection.
8.4.4 CUSTOMER TEST MODE
The Customer Test Mode (CTM) helps to reduce test time for checking the overvoltage delay-timer parameter
once the circuit is implemented into the battery pack. To enter CTM, the VDD pin should be set at least 10 V
higher than V3 (see Figure 8-3). The delay timer is greater than 10 ms, but considerably shorter than the timer
delay in normal operation. To exit CTM, remove the VDD to VC3 voltage differential of 10 V, so that the decrease
in the value automatically causes an exit.
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the device into CTM.
Also avoid exceeding Absolute Maximum Voltages for the individual cell voltages (V3–V2), (V2–V1)
and (V1–VSS). Stressing the pins beyond the rated limits can cause permanent damage to the
device.
Figure 8-3 shows the timing for the Customer Test Mode.
VDD œ V3 = 10V
VDD
V3
> 10ms
OUT (V)
Figure 8-3. Timing for Customer Test Mode
Figure 8-4 shows the measurement for current consumption of the product for both VDD and Vx.
ICC
OUT 8
REG 7
1
VDD
V3
IIN
VDC
2
3
4
3.6 V
3.6 V
3.6 V
0.47 µF
IIN
V2
VSS
6
5
IIN
V1
REG_EN
Figure 8-4. Configuration for Integrated Circuit Current Consumption Test
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The BQ296xxx family of second-level protectors is used for overvoltage protection of the battery pack in the
application. A regulated output is available to drive a small circuit with maximum IREG loading. The device OUT
pin is active high, which drives a NMOS FET that connects the fuse to ground in the event of a fault condition.
This provides a shorted path to use the battery and/or charger power to blow the fuse and cut the power path.
9.2 Typical Application
Application Schematic shows the recommended reference design components.
Pack +
Protector
FETs
100 Ω
OUT
REG
VDD
V4
External
Circuit
e.g., RTC
1 kΩ
1 kΩ
1 kΩ
5 ꢀ (*)
0.1µF
0.1µF
0.1µF
VCELL4
VCELL3
V3
V2
VSS
V1
* can be removed if Vss will be
connected first during cell
connection
PWPD
VCELL2
VCELL1
1 kΩ
0.1µF
0.47 µF
0.1µF
Pack œ
Figure 9-1. Application Schematic
Note
9.2.1 Design Requirements
Changes to the ranges shown in Table 9-1 will impact the accuracy of the cell measurements.
Table 9-1. Parameters
PARAMETER
Voltage monitor filter resistance
EXTERNAL COMPONENT
MIN
NOM
1000
MAX
4700
UNIT
RIN
CIN
900
0.01
0.1
Ω
Voltage monitor filter capacitance
Supply voltage filter resistance
Supply voltage filter capacitance
REG output capacitance
0.1
—
0.1
1
1.0
1
µF
KΩ
µF
µF
RVD
CVD
CREG
—
1.0
—
0.47
Note
The device is calibrated using an RIN value = 1 kΩ. Using a value other than the recommended value
changes the accuracy of the cell voltage measurements and VOV trigger level.
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9.2.2 Detailed Design Procedure
Note
The device VSS must be connected first during PCB test or cell attachment. Failure to do so can
damage the REG pin.
1. If the VSS pin cannot be connected first, it is required to add a resistor of a minimum of 5 Ω to a maximum of
10 Ω (a 5-Ω resistor is used in the reference schematic, Figure 9-2) in series with the REG capacitor. When
VSS is floating, the REG capacitor always charges up to the VDD voltage. When VSS is finally connected,
the REG capacitor will be discharged. Adding a small resistor in series reduces the current strength and
avoids any potential damage to the REG pin. The 5-Ω resistor can be placed in series with the REG connect
circuit (as shown in Figure 9-2) or in series of the REG capacitor (as shown in Figure 9-3). Placing the
resistor in series with the REG circuit results in a small drop of VREG (for example: max loading of IREG mA
with a 5-Ω resistor will drop 5 mV on VREG), but such a connection can protect again rush current discharge
from a REG capacitor or an external filter capacitor connected to the REG pin. Placing the resistor in series
with the REG capacitor is an alternative to avoiding an additional drop in VREG if the filter capacitor used by
the external circuit is much smaller than the REG capacitor.
2. After VSS is connected, the device allows a random cell connection to the Vx pin.
3. The cell should be connected to the lower Vn pin; the unused Vn pin should be shorted to the (Vn-1) pin. See
Figure 9-2 for details.
Pack +
Protector
FETs
100 Ω
OUT
REG
VDD
External
Circuit
e.g., RTC
5 Ω (*)
V4
V3
1 kΩ
0.1µF
bq2961
bq2962
VSS
V1
VCELL3
VCELL2
1 kΩ
V2
0.1µF
PWPD
0.1µF
0.47 µF
1 kΩ
0.1µF
VCELL1
Pack œ
Copyright © 2017, Texas Instruments Incorporated
Figure 9-2. 3-Series BQ2961 and BQ2962 Schematic
4. A Zener diode can be added to the REG pin to VSS, as shown in Figure 9-3. This is recommended to protect
the circuit connected to the REG pin if floating VSS in the field is a risk concern. When VSS is floating
(during cell connection when VSS is not connected first or in a system fault with a broken BAT– wire), the
REG voltage always pulls up to VDD. In a 4-series configuration, the REG voltage can reach approximately
16 V with VSS floating. Adding a Zener diode clamps the REG voltage to a safe level for the external circuits
connected to the REG pin. Having the Zener diode can also protect the external circuits if the REG pin is
shorted to the OUT pin or any other high-voltage output terminal. If a Zener diode is used, TI recommends
putting the diode on the battery side with the BQ296xxx device to allow protection on the REG pin, as well as
the circuit connected to REG under the floating VSS condition. The resistor in series with the REG pin is not
required in this case.
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REG
The 5-Ω resistor limits the rush current
discharge from the capacitor during cell
connection when Vss is not connected
first.
Loss of Vss connection or REG shorted to
high voltage can bring the REG above the
regulated range. This optional zener
clamp can protect the downstream circuit
under such an event.
5 Ω
0.47 µF
This resistor is not required if Vss is
connected first in the cell connection
sequence.
Figure 9-3. 5-V Zener Diode
9.2.3 Application Curves
Figure 9-5. Overvoltage Protection Release
Figure 9-4. Overvoltage Protection
Figure 9-7. Undervoltage Release to Switch On the
Regulator
Figure 9-6. Undervoltage Detection to Turn Off the
Regulator
10 Power Supply Recommendations
The maximum power is 20 V for BQ2961 and BQ2962 on VDD.
Note
Connect VSS first during power up.
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11 Layout
11.1 Layout Guidelines
Use the following layout guidelines:
1. Ensure the RC filters for the Vx pins and VDD pin are placed as close as possible to the target terminal,
reducing the tracing loop area.
2. The capacitor for REG should be placed close to the device terminals.
3. Ensure the trace connecting the fuse to the gate, source of the NFET to the Pack– is sufficient to withstand
the current during a fuse blown event.
11.2 Layout Example
Place the RC filters close
to device terminals
Power Trace Line
Pack +
VDD
V4
OUT
REG
External
Circuit
e.g., RTC
5 ꢀ (*)
V3
V2
VSS
Pack œ
VCELL3
VCELL2
VCELL1
PWPD
V1
* can be removed if Vss
will be connected first
during cell connection
Ensure trace can support sufficient
current flow for fuse blow
Figure 11-1. Layout Example
12 Device and Documentation Support
12.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ296100DSGR
BQ296100DSGT
BQ296103DSGR
BQ296103DSGT
BQ296106DSGR
BQ296106DSGT
BQ296107DSGR
BQ296107DSGT
BQ296111DSGR
BQ296111DSGT
BQ296112DSGR
BQ296112DSGT
BQ296113DSGR
BQ296113DSGT
BQ296114DSGR
BQ296114DSGT
BQ296115DSGR
BQ296202DSGR
BQ296202DSGT
BQ296203DSGR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
6100
6100
6103
6103
6106
6106
6107
6107
6111
6111
6112
6112
6113
6113
6114
6114
6115
6202
6202
6203
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
3000 RoHS & Green
3000 RoHS & Green
250
RoHS & Green
3000 RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ296203DSGT
BQ296212DSGR
BQ296212DSGT
BQ296213DSGR
BQ296213DSGT
BQ296215DSGR
BQ296215DSGT
BQ296216DSGR
BQ296216DSGT
BQ296217DSGR
BQ296217DSGT
BQ296221DSGR
BQ296221DSGT
BQ296222DSGR
BQ296222DSGT
BQ296223DSGR
BQ296223DSGT
BQ296224DSGR
BQ296224DSGT
BQ296226DSGR
BQ296226DSGT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
6203
6212
6212
6213
6213
6215
6215
6216
6216
6217
6217
6221
6221
6222
6222
6223
6223
6224
6224
6226
6226
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
250
RoHS & Green
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ296227DSGR
BQ296228DSGR
BQ296228DSGT
BQ296229DSGR
BQ296229DSGT
BQ296230DSGR
BQ296230DSGT
BQ296231DSGR
BQ296231DSGT
BQ296232DSGR
BQ296232DSGT
BQ296233DSGR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
-40 to 110
6227
6228
6228
6229
6229
6230
6230
6231
6231
6232
6232
6233
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
250
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ296100DSGR
BQ296100DSGT
BQ296103DSGR
BQ296103DSGR
BQ296103DSGT
BQ296103DSGT
BQ296106DSGR
BQ296106DSGR
BQ296106DSGT
BQ296106DSGT
BQ296107DSGR
BQ296107DSGR
BQ296107DSGT
BQ296107DSGT
BQ296111DSGR
BQ296111DSGT
BQ296112DSGR
BQ296112DSGT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
3000
250
250
3000
3000
250
250
3000
3000
250
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Oct-2021
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ296113DSGR
BQ296113DSGT
BQ296114DSGR
BQ296114DSGT
BQ296115DSGR
BQ296202DSGR
BQ296202DSGR
BQ296202DSGT
BQ296202DSGT
BQ296203DSGR
BQ296203DSGR
BQ296203DSGT
BQ296203DSGT
BQ296212DSGR
BQ296212DSGT
BQ296213DSGR
BQ296213DSGT
BQ296215DSGR
BQ296215DSGT
BQ296216DSGR
BQ296216DSGR
BQ296216DSGT
BQ296216DSGT
BQ296217DSGR
BQ296217DSGR
BQ296217DSGT
BQ296217DSGT
BQ296221DSGR
BQ296221DSGT
BQ296222DSGR
BQ296222DSGT
BQ296223DSGR
BQ296223DSGT
BQ296224DSGR
BQ296224DSGT
BQ296226DSGR
BQ296226DSGT
BQ296227DSGR
BQ296228DSGR
BQ296228DSGT
BQ296229DSGR
BQ296229DSGT
BQ296230DSGR
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
3000
250
3000
3000
3000
250
250
3000
3000
250
250
3000
250
3000
250
3000
250
3000
3000
250
250
3000
3000
250
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
3000
250
3000
250
3000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Oct-2021
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ296230DSGT
BQ296231DSGR
BQ296231DSGT
BQ296232DSGR
BQ296232DSGT
BQ296233DSGR
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
250
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
3000
250
3000
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ296100DSGR
BQ296100DSGT
BQ296103DSGR
BQ296103DSGR
BQ296103DSGT
BQ296103DSGT
BQ296106DSGR
BQ296106DSGR
BQ296106DSGT
BQ296106DSGT
BQ296107DSGR
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
3000
250
250
3000
3000
250
250
3000
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Oct-2021
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ296107DSGR
BQ296107DSGT
BQ296107DSGT
BQ296111DSGR
BQ296111DSGT
BQ296112DSGR
BQ296112DSGT
BQ296113DSGR
BQ296113DSGT
BQ296114DSGR
BQ296114DSGT
BQ296115DSGR
BQ296202DSGR
BQ296202DSGR
BQ296202DSGT
BQ296202DSGT
BQ296203DSGR
BQ296203DSGR
BQ296203DSGT
BQ296203DSGT
BQ296212DSGR
BQ296212DSGT
BQ296213DSGR
BQ296213DSGT
BQ296215DSGR
BQ296215DSGT
BQ296216DSGR
BQ296216DSGR
BQ296216DSGT
BQ296216DSGT
BQ296217DSGR
BQ296217DSGR
BQ296217DSGT
BQ296217DSGT
BQ296221DSGR
BQ296221DSGT
BQ296222DSGR
BQ296222DSGT
BQ296223DSGR
BQ296223DSGT
BQ296224DSGR
BQ296224DSGT
BQ296226DSGR
BQ296226DSGT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
250
3000
250
3000
250
3000
250
3000
250
3000
3000
3000
250
250
3000
3000
250
250
3000
250
3000
250
3000
250
3000
3000
250
250
3000
3000
250
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Oct-2021
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ296227DSGR
BQ296228DSGR
BQ296228DSGT
BQ296229DSGR
BQ296229DSGT
BQ296230DSGR
BQ296230DSGT
BQ296231DSGR
BQ296231DSGT
BQ296232DSGR
BQ296232DSGT
BQ296233DSGR
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
3000
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
3000
250
3000
Pack Materials-Page 5
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.32
0.18
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
8X
0.4
0.2
PIN 1 ID
8X
0.1
C A B
C
0.05
4218900/D 04/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/D 04/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/D 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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