BQ25898C [TI]
用于并联充电应用的 I2C 单节 3A 降压电池充电器;
| 型号： | BQ25898C |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于并联充电应用的 I2C 单节 3A 降压电池充电器 电池 |
| 文件： | 总55页 (文件大小：1358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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bq25898C
ZHCSG51B –MARCH 2016–REVISED MARCH 2017
bq25898C I2C 控制单节 3A 充电器实现高输入电压采用紧凑型 DSBGA 封
装
1 特性
2 应用
1
•
作为从充电器运行，在双充电器操作下提供快速充
电
•
•
•
智能手机
平板电脑
•
•
配置简单，物料清单 (BOM) 极低
便携式网络设备
高效率 3A、1.5MHz 开关模式降压充电器
3 说明
–
充电效率高达 92%（3A 充电电流下）和
94%（2A 充电电流下）
bq25898C 是一款适用于单节锂离子电池和锂聚合物电
池的高度集成型开关模式电池充电管理和系统电源路径
管理器件。该器件支持高输入电压充电。其低阻抗电源
路径对开关模式运行效率进行了优化、缩短了电池充电
时间并延长了放电阶段的电池使用寿命。具有充电和系
统设置的 I2C 串行接口使得该器件成为真正具有灵活
性的解决方案。bq25898C 采用 2.8mm x 2.5mm 42
焊球 DSBGA 封装。
–
–
针对高电压输入 (9V/12V) 进行了优化
低功耗 PFM 模式，适用于轻负载操作
•
•
单个输入，支持 USB 输入和可调高压适配器
–
–
支持 3.9V 至 14V 输入电压范围
输入电流限制（100mA 至 3.25A，分辨率为
50mA），支持 USB2.0、USB3.0 标准和高压
适配器
–
宽输入动态电源管理 (DPM) 范围
器件信息(1)
借助 5mΩ 电池放电金属氧化物半导体场效应晶体
管 (MOSFET) 实现最高电池放电效率，放电电流高
达 9A电池 MOSFET
器件型号
bq25898C
封装
封装尺寸（标称值）
DSBGA (42)
2.80mm x 2.50mm
•
•
默认禁用充电
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
集成 ADC，用于系统监视
（输入、系统和电池电压、温度和充电电流）
灵活的自主和 I2C 模式，可实现最优系统性能
简化电路原理图
•
•
•
INPUT
3.9Vœ14V
远程电池感测
USB
高集成度，包括所有 MOSFET、电流感测和环路补
偿
•
高精度
–
–
–
±0.5% 充电电压调节
±5% 充电电流调节
±7.5% 输入电流调节
ICHG
I2C BUS
•
安全
Host
–
–
–
–
热调节和热关断
Host Control
输入 UVLO/过压保护
电池 OVP
安全定时器
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCH6
bq25898C
ZHCSG51B –MARCH 2016–REVISED MARCH 2017
www.ti.com.cn
目录
8.3 Device Functional Modes........................................ 23
8.4 Register Map........................................................... 25
Application and Implementation ........................ 42
9.1 Application Information............................................ 42
9.2 Typical Application Diagram ................................... 42
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements................................................ 9
7.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 12
8.1 Functional Block Diagram ....................................... 13
8.2 Feature Description................................................. 14
9
10 Power Supply Recommendations ..................... 46
11 Layout................................................................... 46
11.1 Layout Guidelines ................................................. 46
11.2 Layout Example .................................................... 46
12 器件和文档支持 ..................................................... 47
12.1 器件支持 ............................................................... 47
12.2 接收文档更新通知 ................................................. 47
12.3 社区资源................................................................ 47
12.4 商标....................................................................... 47
12.5 静电放电警告......................................................... 47
12.6 Glossary................................................................ 47
13 机械、封装和可订购信息....................................... 47
8
4 修订历史记录
Changes from Revision A (December 2016) to Revision B
Page
•
完整数据表已更新到产品文件夹 ............................................................................................................................................ 1
Changes from Original (March 2016) to Revision A
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
已添加 电池 MOSFET 更改为最高电池放电效率特性............................................................................................................. 1
已更改 集成 ADC，用于系统监视特性 ................................................................................................................................... 1
已更改 “充电已禁用”更改为“快速充电和预充电均已禁用” ....................................................................................................... 3
已更改 PG 已更改为 PG（在“说明”中） ................................................................................................................................ 3
Changed anode to cathode in BTST ..................................................................................................................................... 5
Changed cathode to anode in REGN .................................................................................................................................... 5
Deleted I(BOOST) from Electrical Characteristics....................................................................................................................... 6
Changed falling to rising in tACOV_RISING test conditions in Electrical Characteristics .............................................................. 6
已更改 128 mA to 0 mA (precharge disabled) in 表 2 ......................................................................................................... 16
已更改 128 mA to 0 mA (precharge disabled) in 表 3 ......................................................................................................... 17
已更改 Fast Charge Current from 4032 mA to 3008 mA in 图 10........................................................................................ 18
已更改 charge to both fast charge and precharge in 表 10 ................................................................................................. 29
已更改 128mA (0001) to 0mA when REG04[5:0] = 000000 in 表 11 ................................................................................... 30
已更改 REG09 bits 5 - 2 from R/W to R .............................................................................................................................. 34
已更改 bit 5 in 表 15 ............................................................................................................................................................ 34
已更改 REG0B bit1 from x to 1 ........................................................................................................................................... 36
已添加 note to 图 40 ............................................................................................................................................................ 42
2
版权 © 2016–2017, Texas Instruments Incorporated
bq25898C
www.ti.com.cn
ZHCSG51B –MARCH 2016–REVISED MARCH 2017
5 说明 （续）
bq25898C 是一款适用于单节锂离子电池和锂聚合物电池的高度集成型 3A 开关模式电池充电管理器件。作为一款
经济高效的微型器件，它还可以配置为从充电器，以在双充电器应用中提供快速 充电的输出电流传感电阻器和运算
放大器而得以实现。
该器件 支持 高输入电压快速充电，适用于各类智能手机、平板电脑和便携式设备。其低阻抗电源路径对开关模式
运行效率进行了优化、缩短了电池充电时间并延长了放电阶段的电池使用寿命。该解决方案高度集成输入反向阻断
场效应晶体管 (FET)（RBFET，Q1）、高侧开关 FET（HSFET，Q2）、低侧开关 FET（LSFET，Q3）以及充电
电流感测电路。它还集成了自举二极管以进行高侧栅极驱动和电池监视，从而简化系统设计。具有充电和系统设置
的 I2C 串行接口使得此器件成为一个真正地灵活解决方案。
该器件支持多种输入源，包括标准 USB 主机端口、USB 充电端口以及兼容 USB 的可调节高电压适配器。为了设
定默认输入电流限值，该器件获取系统检测电路（如 USB PHY 器件）中的结果。该器件符合 USB 2.0 和 USB
3.0 电源规范，具有输入电流和电压调节功能。
默认充电电流设置为 0mA（快速充电和预充电均已禁用）。启用充电后，器件可在软件控制下启动并完成一个充电
周期。
此充电器提供针对电池充电和系统运行的多种安全 特性 ，其中包括充电安全定时器和过压/过流保护。当结温超过
120°C（可设定）时，热调节减少充电电流。STAT 输出报告充电状态和任何故障条件。PG 输出指示电源是否正
常。当故障发生时，INT 会立即通知主机。
该器件采用 2.80mm x 2.50mm 42 焊球 DSBGA 封装。
Copyright © 2016–2017, Texas Instruments Incorporated
3
bq25898C
ZHCSG51B –MARCH 2016–REVISED MARCH 2017
www.ti.com.cn
6 Pin Configuration and Functions
YFF Package
42-Pin DSBGA
Top View
1
2
3
4
5
6
A
SYS
REGN
BAT
PGND
CE
SCL
SDA
BTST
NC
SYS
BAT
BAT
B
C
NC
PGND
PSEL
PG
SYS
SYS
SW
PGND
PMID
BAT
D
E
F
SW
SW
PGND
PGND
PGND
PGND
BAT
SYS
INT
VBUS
VBUS
VBUS
PMID
PMID
PMID
BATSEN
SW
SW
G
STAT
PGND
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
VBUS
PSEL
PG
NO.
E3-G3
C3
Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS
and PMID with VBUS on source. Place a 1-uF ceramic capacitor from VBUS to PGND and place it as close as
possible to IC.
P
DI
Power source selection input. High indicates a USB host source and Low indicates an adapter source.
Open drain active low power good indicator. Connect to the pull up rail via 10-kohm resistor. LOW indicates a
good input source if the input voltage is within VVBUS_OP, above SLEEP mode threshold (VSLEEPZ), and
current limit is above IBATSRC (30mA).
D3
DO
Open-drain interrupt output. Connect to the INT to a logic rail via 10-kohm resistor. The INT pin sends active
low, 256-us pulse to host to report charger device status and fault.
STAT
G1
DO
SCL
SDA
A3
B3
DI
I2C Interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
I2C Interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
DIO
Open-drain Interrupt Output. Connect the INT to a logic rail via 10-kΩ resistor. The INT pin sends active low,
256-μs pulse to host to report charger device status and fault.
INT
F2
DO
DI
Active low charge enable pin. Battery charging is enabled when CHG_CONFIG = 1 and CE pin = Low. CE pin
must be pulled High or Low.
CE
NC
B4
B5-B6
A1-E1
No connect. Float the pin.
Battery connection point to the positive terminal of the battery pack. The internal current sensing circuitry is
connected between SYS and BAT. Connect a 10uF closely to the BAT pin.
BAT
P
(1) DI (Digital Input), DO (Digital Output), DIO (Digital Input/Output), AI (Analog Input), AO (Analog Output), AIO (Analog Input/Output)
4
Copyright © 2016–2017, Texas Instruments Incorporated
bq25898C
www.ti.com.cn
ZHCSG51B –MARCH 2016–REVISED MARCH 2017
Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Converter output connection point. The internal current sensing circuitry is connected between SYS and BAT.
Connect a 20uF closely to the SYS pin.
SYS
A2-E2
P
Power ground connection for high-current power converter node. Internally, PGND is connected to the source
of the n-channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors
of the charger. A single point connection is recommended between power PGND and the analog GND near the
IC PGND pin.
C4,C6-
G6,A4,G2
PGND
P
Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel
HSFET and the drain of the n-channel LSFET. Connect the 0.047μF bootstrap capacitor from SW to BTST.
SW
C5-G5
A6
P
P
PWM high side driver positive supply. Internally, the BTST is connected to the cathode of the boost-strap
diode. Connect the 0.047μF bootstrap capacitor from SW to BTST.
BTST
PWM low side driver positive supply output. Internally, REGN is connected to the anode of the boost-strap
diode. Connect a 4.7μF (10 V rating) ceramic capacitor from REGN to analog GND. The capacitor should be
placed close to the IC.
REGN
A5
P
Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Given the total
input capacitance, put 1μF on VBUS to PGND, and the rest capacitance on PMID to PGND.
PMID
D4-G4
F1
DO
AI
BATSEN
Remote battery sense input. The typical pin resistance is 800 kΩ. Connect as close to battery as possible.
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–2
MAX
22
22
20
7
VALUE
VBUS (converter not switching)
V
V
PMID (converter not switching)
–0.3
–0.3
–0.3
–0.3
–0.3
–3
STAT
PG
V
V
PSEL
7
V
BTST
20
16
6
V
Voltage range (with respect to GND)
SW
V
BAT, SYS (converter not switching)
SDA, SCL, INT, REGN, CE
BTST TO SW
–0.3
–0.3
–0.3
–0.3
–0.3
V
7
V
7
V
PGND to GND
0.3
7
V
BATSEN
V
INT, STAT
6
mA
mA
°C
°C
Output sink current
PG
6
Junction temperature
–40
–65
150
150
Storage temperature range, Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
7.2 ESD Ratings
VALUE
UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
±2000
V
VESD
Electrostatic discharge
Charged device model (CDM), per JEDEC specification
JESD22-C101(2)
±250
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2016–2017, Texas Instruments Incorporated
5
bq25898C
ZHCSG51B –MARCH 2016–REVISED MARCH 2017
www.ti.com.cn
MAX UNIT
7.3 Recommended Operating Conditions
MIN
VIN
Input voltage
3.9
14(1)
V
A
A
V
A
A
IIN
Input current (VBUS)
Output current (SW)
Battery voltage
3.25
ISYS
VBAT
3
4.608
3
Fast charging current
Up to 6 (continuos)
IBAT
Discharging current with internal MOSFET
Operating free-air temperature range
9 (peak)
(Up to 1 sec duration)
A
TA
–40
85
°C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight
layout minimizes switching noise.
7.4 Thermal Information
bq25898C
THERMAL METRIC(1)
YFF (DSBGA)
UNIT
42-BALL
53.5
0.2
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
8.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJB
8.2
RθJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QUIESCENT CURRENTS
VBAT = 4.2 V, V(VBUS) < V(UVLO), leakage
between BAT and VBUS
5
µA
µA
High-Z Mode, No VBUS, BATFET Disabled
(REG09[5] = 1), Battery Monitor Disabled, TJ
< 85°C
12
32
23
IBAT
Battery discharge current (BAT, SW, SYS) in buck mode
High-Z Mode, No VBUS, BATFET Enabled
(REG09[5] = 0), Battery Monitor Disabled, TJ
< 85°C
60
µA
V(VBUS)= 5 V, High-Z Mode, No Battery,
Battery Monitor Disabled
15
25
1.5
3
35
50
3
µA
µA
Input supply current (VBUS) in buck mode when High-Z mode
is enabled
I(VBUS_HIZ)
V(VBUS)= 12 V, High-Z Mode, No Battery,
Battery Monitor Disabled
VBUS > V(UVLO), VBUS > VBAT, Converter not
switching
mA
mA
mA
VBUS > V(UVLO), VBUS > VBAT, Converter
switching, VBAT = 3.2V, ISYS = 0A
I(VBUS)
Input supply current (VBUS) in buck mode
VBUS > V(UVLO), VBUS > VBAT, Converter
switching, VBAT = 3.8 V, ISYS = 0 A
3
VBUS/BAT POWER UP
V(VBUS_OP)
VBUS operating range
3.9
3.6
14
V
V
VBUS for active I2C, no battery
Sleep mode falling threshold
Sleep mode rising threshold
VBUS over-voltage rising threshold
VBUS over-voltage falling threshold
ACOV rising deglitch
V(VBUS_UVLOZ)
V(SLEEP)
25
130
65
120
370
mV
mV
V
V(SLEEPZ)
250
13.9
13.3
14.6
13.9
V(ACOV)
V
tACOV_RISING
VVBUS rising
1
µs
6
Copyright © 2016–2017, Texas Instruments Incorporated
bq25898C
www.ti.com.cn
ZHCSG51B –MARCH 2016–REVISED MARCH 2017
Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tACOV_FALLING
VBAT(UVLOZ)
ACOV falling deglitch
VVBUS falling
1
ms
Battery for active I2C, no VBUS
Battery depletion falling threshold
Battery depletion rising threshold
Bad adapter detection threshold
Bad adapter detection current source
2.3
V
VBAT(DPL)
VBAT(DPLZ)
V(VBUSMIN)
I(BADSRC)
2.15
2.35
2.5
2.7
V
V
3.8
30
V
mA
POWER-PATH MANAGEMENT
I(SYS) = 0 A, VBAT> VSYS(MIN), BATFET
Disabled (REG09[5]=1)
VBAT
50 mV
+
V
V
V
V
VSYS
Typical system regulation voltage
Isys = 0 A, VBAT< VSYS(MIN), BATFET
Disabled (REG09[5]=1)
VSYS(MIN)
250 mV
+
VBAT< VSYS(MIN), SYS_MIN = 3.5 V
(REG03[3:1] = 101), ISYS= 0 A
VSYS(MIN)
VSYS(MAX)
Minimum DC system voltage output
Maximum DC system voltage output
3.60
3.75
4.40
VBAT = 4.35 V, SYS_MIN = 3.5 V
(REG03[3:1] = 101), ISYS= 0 A
4.42
TJ = -40°C - 85°C
28
28
24
24
12
12
30
40
47
33
40
18
21
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mV
Top reverse blocking MOSFET(RBFET) on-resistance between
VBUS and PMID
RON(RBFET)
RON(HSFET)
RON(LSFET)
TJ = -40°C - 125°C
TJ = -40°C - 85°C
Top switching MOSFET (HSFET) on-resistance between PMID
and SW
TJ = -40°C - 125°C
TJ = -40°C - 85°C
Bottom switching MOSFET (LSFET) on-resistance between
SW and GND
TJ = -40°C - 125°C
BAT discharge current 10 mA
V(FWD)
BATFET forward voltage in supplement mode
BATTERY CHARGER
VBAT(REG_RANGE)
VBAT(REG_STEP)
Typical charge voltage range
Typical charge voltage step
3.840
4.608
V
16
64
mV
VBAT = 4.208 V (REG06[7:2] = 010111) or
VBAT = 4.352 V (REG06[7:2] = 100000)
TJ = -40°C - 85°C
VBAT(REG)
Charge voltage resolution accuracy
-0.5%
0
0.5%
3008
I(CHG_REG_RANGE)
I(CHG_REG_STEP)
Typical fast charge current regulation range
Typical fast charge current regulation step
mA
mA
VBAT= 3.1 V or 3.8 V, ICHG = 256 mA
TJ = -40°C - 85°C
-20%
-5%
2.6
20%
5%
I(CHG_REG_ACC)
Fast charge current regulation accuracy
VBAT= 3.1 V or 3.8 V, ICHG = 1792 mA
TJ = -40°C - 85°C
Fast charge to precharge, BATLOWV
(REG06[1]) = 1
Battery LOWV falling threshold
Battery LOWV rising threshold
Battery LOWV falling threshold
Battery LOWV rising threshold
2.8
3.0
2.6
2.8
2.9
V
V
V
V
Precharge to fast charge, BATLOWV
(REG06[1]) = 1
(Typical 200-mV hysteresis)
2.8
2.5
3.15
2.7
VBAT(LOWV)
Fast charge to precharge, BATLOWV
(REG06[1]) = 0
Precharge to fast charge, BATLOWV
(REG06[1]) = 0
(Typical 200-mV hysteresis)
2.7
64
2.9
I(PRECHG_RANGE)
I(PRECHG_STEP)
I(PRECHG_ACC)
I(TERM_RANGE)
I(TERM_STEP)
Precharge current range
1024
mA
mA
Typical precharge current step
Precharge current accuracy
Termination current range
Typical termination current step
64
64
VBAT = 2.6 V, IPRECHG = 256 mA
–20%
64
20%
1024
mA
mA
ITERM = 256 mA, ICHG≤ 1344 mA
TJ = -20°C - 85°C
-20%
-20%
20%
20%
I(TERM_ACC)
Termination current accuracy
ITERM = 256 mA, ICHG> 1344 mA
TJ = -20°C - 85°C
V(SHORT)
Battery short voltage
VBAT falling
2.0
200
110
100
200
V
V(SHORT_HYST)
I(SHORT)
Battery short voltage hysteresis
Battery short current
VBAT rising
mV
mA
mV
mV
VBAT < 2.2 V
VBAT falling, VRECHG (REG06[0] = 0) = 0
VBAT falling, VRECHG (REG06[0] = 0) = 1
V(RECHG)
Recharge threshold below VBATREG
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Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mΩ
mΩ
kΩ
TJ = 25°C
5
7
RON(BATFET)
RBATSEN
SYS-BAT MOSFET (BATFET) on-resistance
BATSEN input resistance
TJ = -40°C - 125°C
5
10
800
INPUT VOLTAGE / CURRENT REGULATION
VIN(DPM_RANGE)
VIN(DPM_STEP)
VIN(DPM_ACC)
IIN(DPM_RANGE)
IIN(DPM_STEP)
Typical input voltage regulation range
3.9
15.3
V
Typical input voltage regulation step
Input voltage regulation accuracy
Typical input current regulation range
Typical input current regulation step
100
mV
VINDPM = 4.4 V, 7.8 V, 10.8 V
IINLIM (REG00[5:0]) = 100 mA
-3%
100
3%
3250
mA
mA
50
90
Input current 100mA regulation accuracy
VBAT = 5V, current pulled from SW
IIN(DPM100_ACC)
85
100
mA
USB150, IINLIM (REG00[5:0]) = 150 mA
USB500, IINLIM (REG00[5:0]) = 500 mA
USB900, IINLIM (REG00[5:0]) = 900 mA
125
440
750
135
470
825
150
500
900
mA
mA
mA
Input current regulation accuracy
VBAT = 5V, current pulled from SW
IIN(DPM_ACC)
Adapter 1.5 A, IINLIM (REG00[5:0]) = 1500
mA
1300
1400
1500
200
mA
mA
IIN(START)
Input current regulation during system start up
VSYS = 2.2 V, IINLIM (REG00[5:0]) ≥ 200 mA
BAT OVER-VOLTAGE/CURRENT PROTECTION
VBAT(OVP)
Battery over-voltage threshold
Battery over-voltage hysteresis
System over-current threshold
VBAT rising, as percentage of VBAT(REG)
VBAT falling, as percentage of VBAT(REG)
104%
2%
VBAT(OVP_HYST)
IBAT(FET_OCP)
9
A
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG
Junction temperature regulation accuracy
Thermal shutdown rising temperature
Thermal shutdown hysteresis
REG08[1:0] = 11
Temperature rising
Temperature falling
120
160
30
°C
°C
°C
TSHUT
TSHUT(HYS)
PWM
FSW
PWM switching frequency, and digital clock
Maximum PWM duty cycle
Oscillator frequency
1.32
1.68
6.4
MHz
DMAX
97%
REGN LDO
V(VBUS) = 9 V, I(REGN) = 40 mA
V(VBUS) = 5 V, I(REGN) = 20 mA
V(VBUS) = 9 V, V(REGN) = 3.8 V
5.6
4.7
50
6
V
V
V(REGN)
REGN LDO output voltage
REGN LDO current limit
4.8
I(REGN)
mA
ANALOG-TO-DIGITAL CONVERTER (ADC)
RES
Resolution
Rising threshold
7
bits
V
V(VBUS) > VBAT + V(SLEEP)
V(VBUS) < VBAT + V(SLEEP)
2.304
4.848
4.848
VBAT(RANGE)
V(BAT_RES)
V(SYS_RANGE)
Typical battery voltage range
Typical battery voltage resolution
Typical system voltage range
VSYS_MIN
V
20
mV
V
V(VBUS) > VBAT + V(SLEEP)
V(VBUS) < VBAT + V(SLEEP)
2.304
4.848
4.848
VSYS_MIN
V
V(SYS_RES)
Typical system voltage resolution
Typical VVBUS voltage range
20
mV
V
V(VBUS_RANGE)
V(VBUS_RES)
V(VBUS) > VBAT + V(SLEEP)
2.6
0
15.3
Typical VVBUS voltage resolution
100
mV
V(VBUS) > VBAT + V(SLEEP) and VBAT
VBAT(SHORT)
>
IBAT(RANGE)
IBAT(RES)
Typical battery charge current range
3.008
A
Typical battery charge current resolution
50
mA
LOGIC I/O PIN (CE, PSEL)
VIH
Input high threshold level
1.3
V
V
VIL
Input low threshold level
High level leakage current
0.4
1
IIN(BIAS)
Pull-up rail 1.8 V
µA
LOGIC I/O PIN (INT, STAT, PG)
VOL
Output low threshold level
High level leakage current
Sink Current = 5 mA, Sink current
Pull-up rail 1.8 V
0.4
1
V
IOUT_BIAS
µA
I2C INTERFACE (SCL, SDA)
VIH
VIL
Input high threshold level, SCL and SDA
Input low threshold level
Pull-up rail 1.8 V
Pull-up rail 1.8 V
1.3
V
V
0.4
8
Copyright © 2016–2017, Texas Instruments Incorporated
bq25898C
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ZHCSG51B –MARCH 2016–REVISED MARCH 2017
Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
Output low threshold level
High level leakage current
TEST CONDITIONS
Sink Current = 5 mA, Sink current
Pull-up rail 1.8 V
MIN
TYP
MAX
0.4
1
UNIT
V
VOL
IBIAS
µA
7.6 Timing Requirements
MIN
NOM
MAX UNIT
VBUS/BAT POWER UP
tBADSRC
Bad adapter detection duration
30
msec
BAT OVER-VOLTAGE PROTECTION
Battery over-voltage deglitch time to disable
charge
tBATOVP
1
µs
BATTERY CHARGER
tRECHG
Recharge deglitch time
20
8
msec
BATTERY MONITOR
tCONV
Conversion time
CONV_RATE(REG02[6]) = 0
1000 msec
I2C INTERFACE
fSCL
SCL clock frequency
400
KHz
DIGITAL CLOCK and WATCHDOG TIMER
fLPDIG
fDIG
Digital low power clock
Digital clock
REGN LDO disabled
REGN LDO enabled
18
30
45
KHz
KHz
1320
1500
1680
WATCHDOG
(REG07[5:4])=11, REGN LDO
disabled
100
136
160
160
sec
sec
tWDT
Watchdog reset time
WATCHDOG
(REG07[5:4])=11, REGN LDO
enabled
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7.7 Typical Characteristics
96
94
92
90
88
86
84
82
80
95
93
91
89
87
85
83
81
79
77
75
VBUS = 5V
VBUS = 9V
VBUS = 12V
VBUS = 5V
VBUS = 9V
VBUS = 12V
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
Charge Current (A)
System Load Current (A)
D001
D001
VBAT = 3.8 V
DCR = 10 mΩ
图 1. Charge Efficiency vs Charge Current
图 2. System Light Load Efficiency vs System Light Load
Current
8
6
3.82
3.78
3.74
3.70
3.66
3.62
3.58
3.54
3.50
4
2
0
-2
-4
-6
-8
VBAT = 3.1V
VBAT = 3.8V
0.5
1
1.5
2
2.5
3
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Charge Current (A)
Load Current (A)
D001
D001
VBUS = 5 V
VBAT = 2.6 V
VBUS = 5 V
SYSMIN = 3.5 V
图 3. Charge Current Accuracy vs Charge Current I2C
图 4. SYS Voltage Regulation vs System Load Current
Setting
4.5
4.45
4.4
4.30
4.28
4.26
4.24
4.22
4.20
4.18
4.16
4.14
4.12
4.10
4.35
4.3
4.25
4.2
4.15
4.1
4.05
4
0
0.5
1
1.5
2
2.5
3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
Load Current (A)
D001
D001
VBAT = 4.2 V
图 5. SYS Voltage Regulation vs System Load Current
VBUS = 5 V
图 6. BAT Voltage vs Temperature
10
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ZHCSG51B –MARCH 2016–REVISED MARCH 2017
Typical Characteristics (接下页)
1600
-0.10
-0.15
-0.20
-0.25
-0.30
1400
1200
1000
800
600
400
200
0
IINLIM = 500mA
IINLIM = 900mA
IINLIM = 1.5A
VBUS = 5V
VBUS = 9V
VBUS = 12
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
3.8 3.85 3.9 3.95
4
4.05 4.1 4.15 4.2 4.25
Battery Charge Voltage (V)
D001
D001
图 7. Input Current Limit vs Temperature
图 8. Charge Voltage Accuracy
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8 Detailed Description
The device is a highly integrated 3-A switch-mode battery charger for single cell Li-Ion and Li-polymer battery. It
is highly integrated with the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2) ,
low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4). The device also integrates the boostrap
diode for the high-side gate drive.
12
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ZHCSG51B –MARCH 2016–REVISED MARCH 2017
8.1 Functional Block Diagram
VBUS
RBFET
PMID
(Q1)
VVBUS_UVLOZ
UVLO
Q1 Gate
Control
NC
V
BATZ +80mV
REGN
LDO
SLEEP
ACOV
REGN
BTST
EN_HIZ
V
ACOV
FBO
BATSEN
BATOVP
104%xVBAT_REG
VINDPM
SW
I LSFET_UCP
IQ3
UCP
HSFET (Q2)
REGN
CONVERTER
CONTROL
IINDPM
BATSEN
V BAT_REG
LSFET (Q3)
PGND
IQ2
Q2_OCP
SYS
I HSFET_OCP
VSYSMIN
EN_HIZ
EN_CHARGE
V BTST -VSW
ICHG_REG
REFRESH
VBTST_REFRESH
SYS
ICHG
REF
DAC
V BAT_REG
I CHG_REG
Q4 Gate
Control
IBADSRC
IDC
BATFET
(Q4)
BAD_SRC
Converter
Control State
Machine
IC TJ
BAT
TSHUT
TSHUT
BATSEN
BATSEN
VBATGD
BAT_GD
Input
Source
Detection
USB
PSEL
PG
ICHG
Adapter
ADC Control
VBUS
-VRECHG
VREG
BATSEN
SYS
RECHRG
ADC
BATSEN
ICHG
TERMINATION
BATLOWV
CHARGE
CONTROL
STATE
ITERM
INT
V BATLOWV
BATSEN
MACHINE
V SHORT
I2C
Interface
BATSHORT
SUSPEND
STAT
BATSEN
bq25898C
SCL SDA
CE
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8.2 Feature Description
8.2.1 Device Power-On-Reset (POR)
The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS rises above
VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET
driver are active. I2C interface is ready for communication and all the registers are reset to default value. The
host can access all the registers after POR.
8.2.2 Device Power Up from Battery without Input Source
If only battery is present and the voltage is above depletion threshold (VBAT_DPLZ), the BATFET turns on and
connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDS(ON) of
BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
The device always monitors the discharge current through BATFET. When the system is overloaded or shorted
(IBAT > IBATFET_OCP), the device turns off BATFET immediately until the input source plugs in again to re-enable
BATFET.
8.2.3 Device Power Up from Input Source
When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the
bias circuits. It detects and sets the input current limit before the buck converter is started when
AUTO_DPDM_EN bit is set. The power up sequence from input source is as listed:
1. Power Up REGN LDO
2. Poor Source Qualification
3. Input Source Type Detection based on PSEL to set default Input Current Limit (IINLIM) register and input
source type
4. Input Voltage Limit Threshold Setting (VINDPM threshold)
5. Converter Power-up
8.2.3.1 Power Up REGN Regulation (LDO)
The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also
provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The
REGN is enabled when all the below conditions are valid.
1. VBUS above VVBUS_UVLOZ
2. VBUS above VBAT + VSLEEPZ in buck mode
3. After 220 ms delay is completed
If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The
device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when the device
is in HIZ.
8.2.3.2 Poor Source Qualification
After REGN LDO powers up, the device checks the current capability of the input source. The input source has
to meet the following requirements in order to start the buck converter.
1. VBUS voltage below VACOV
2. VBUS voltage above VVBUSMIN when pulling IBADSRC (typical 30mA)
Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT
pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source qualification
every 2 seconds.
8.2.3.3 Input Source Type Detection
After the VBUS_GD bit is set and REGN LDO is powered, the charger device runs Input Source Type Detection
when AUTO_DPDM_EN bit is set.
After input source type detection, an INT pulse is asserted to the host. In addition, the following registers and pin
are changed:
14
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Feature Description (接下页)
1. Input Current Limit (IINLIM) register is changed to set current limit
2. PG_STAT bit is set
The host can over-write IINLIM register to change the input current limit if needed. The charger input current is
always limited by the lower of IINLIM register at all-time.
When AUTO_DPDM_EN is disabled, the Input Source Type Detection is bypassed. The Input Current Limit
(IINLIM) register, VBUS_STAT, and SPD_STAT bits are unchanged from previous values.
8.2.3.3.1 PSEL Pin Sets Input Current Limit
The bq25898C has PSEL interface for input current limit setting to interface with USB PHY. It directly takes the
USB PHY device output to decide whether the input is USB host or charging port. To implement USB100 in the
system, the host can enter HiZ mode by setting EN_HIZ bit after 2 min charging with 500 mA input current limit.
表 1. bq25898C Result
INPUT CURRENT LIMIT
INPUT DETECTION
BAT VOLTAGE
PSEL PIN
SDP_STAT
VBUS_STAT
(IINLIM)
500 mA
1.5 A
USB SDP (USB500)
Adapter
X
X
High
Low
1
001
010
8.2.3.3.2 Force Input Current Limit Detection
In host mode, the host can force the device to run by setting FORCE_DPDM bit. After the detection is completed,
FORCE_DPDM bit returns to 0 by itself and Input Result is updated.
8.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
The device supports wide range of input voltage limit (3.9 V – 14 V) for high voltage charging and provides two
methods to set Input Voltage Limit (VINDPM) threshold to facilitate autonomous detection.
1. Absolute VINDPM (FORCE_VINDPM=1)
By setting FORCE_VINDPM bit to 1, the VINDPM threshold setting algorithm is disabled. Register VINDPM
is writable and allows host to set the absolute threshold of VINDPM function.
2. Relative VINDPM based on VINDPM_OS registers (FORCE_VINDPM=0) (Default)
When FORCE_VINDPM bit is 0 (default), the VINDPM threshold setting algorithm is enabled. The VINDPM
register is read only and the charger controls the register by using VINDPM Threshold setting algorithm. The
algorithm allows a wide range of adapter (VVBUS_OP) to be used with flexible VINDPM threshold.
After Input Voltage Limit Threshold is set, an INT pulse is generated to signal to the host.
8.2.3.5 Converter Power-Up
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input
current limit is forced to the lower of 200 mA or IINLIM register setting. After the system rises above 2.2 V, the
device limits input current to the IILIM register.
As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current and temperature, simplifying output filter design.
A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-
tooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp
height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.
In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below
minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is
set by the ratio of SYS and VBUS.
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8.2.4 Power Path Management
The device accommodates a wide range of input sources from USB, wall adapter, to car battery. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.
8.2.4.1 Dynamic Power Management
To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic
Power Management (DPM), which continuously monitors the input current and input voltage. When input source
is over-loaded, either the current exceeds the input current limit (IINLIM or IDPM_LIM) or the voltage falls below
the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls below
the input current limit and the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to
drop. Once the system voltage falls below the battery voltage, the device automatically enters the where the
BATFET turns on and battery starts discharging so that the system is supported from both the input source and
battery.
During DPM mode, the status register bits VDPM_STAT (VINDPM) and/or IDPM_STAT (IINDPM) is/are set high.
图 9 shows the DPM response with 9V/1.2A adapter, 3.2-V battery, 2.8-A charge current and 3.4-V minimum
system voltage setting.
ëoltage
VBUS
SYS
BAT
3.6V
3.4V
3.2V
3.18V
/urrent
4A
ICHG
3.2A
2.8A
ISYS
1.2A
1.0A
IIN
0.5A
-0.6A
DPM
DPM
Supplement
图 9. DPM Response
8.2.5 Battery Charging Management
The device charges 1-cell Li-Ion battery with up to 3-A charge current for high capacity battery. The 5-mΩ
BATFET improves charging efficiency and minimize the voltage drop during discharging.
8.2.5.1 Autonomous Charging Cycle
With battery charging enabled (CHG_CONFIG bit = 1, CE pin is low, and REG04[6:0] is not set to 0 mA), the
device autonomously completes a charging cycle without host involvement. The device default charging
parameters are listed in . The host can always control the charging operations and optimize the charging
parameters by writing to the corresponding registers through I2C.
表 2. Charging Parameter Default Setting
DEFAULT MODE
Charging Voltage
Charging Current
Pre-charge Current
Termination Current
bq25898C
4.208 V
0 A (charge disable)
0 mA (precharge disabled)
256 mA
16
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bq25898C
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ZHCSG51B –MARCH 2016–REVISED MARCH 2017
表 2. Charging Parameter Default Setting (接下页)
DEFAULT MODE
bq25898C
Safety Timer
12 hour
A new charge cycle starts when the following conditions are valid:
•
•
•
•
Converter starts
Battery charging is enabled by setting CHG_CONFIG bit, /CE pin is low and ICHG register is not 0 mA
No safety timer fault
BATFET is not forced to turn off (BATFET_DIS bit = 0)
The charger device automatically terminates the charging cycle when the charging current is below termination
threshold, charge voltage is above recharge threshold, and device not in DPM mode or thermal regulation. When
a full battery voltage is discharged below recharge threshold (threshold selectable via VRECHG bit), the device
automatically starts a new charging cycle. After the charge is done, either toggle CE pin or CHG_CONFIG bit
can initiate a new charging cycle.
The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH)
or charging fault (Blinking). The STAT output can be disabled by setting STAT_DIS bit. In addition, the status
register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast
charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is completed, an
INT is asserted to notify the host.
8.2.5.2 Battery Charging Profile
The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the
beginning of a charging cycle, the device checks the battery voltage and regulates current / voltage.
表 3. Charging Current Setting
VBAT
< 2 V
CHARGING CURRENT
IBATSHORT
REG DEFAULT SETTING
–
CHRG_STAT
01
01
00
2 V – 3 V
> 3 V
IPRECHG
0 mA (precharge disabled)
0 (charge disabled)
ICHG
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If the charger device is in DPM regulation or thermal regulation during charging, the charging current can be less
than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is
counted at half the clock rate.
wegulation ëoltage
(3.84ë t 4.608ë)
ꢀattery ëoltage
Cast /harge /urrent
(128m!-3008m!)
/harge /urrent
ë
ꢀ!Ç_[ꢁíë (2.8ëꢂ3ë
or 2.6ëꢂ2.8ë)
ë
ꢀ!Ç_{IꢁwÇ (2ë)
L
ꢃw9/I!wD9 (64m!-1024m!)
Ç9wꢄLb!ÇLꢁb (64m!-1024m!)
ꢀ!Ç{IꢁwÇ (100m!)
L
L
Cast /harge and ëoltage wegulation
Çrickle /harge
ꢃre-charge
{afety Çimer
9xpiration
图 10. Battery Charging Profile
8.2.5.3 Charging Termination
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn on again to engage .
When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host.
Termination is temporarily disabled when the charger device is in input current, voltage or thermal regulation.
Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.
8.2.5.4 Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The
safety timer is 4 hours when the battery is below VBATLOWV threshold. The user can program fast charge safety
timer through I2C (CHG_TIMER bits). When safety timer expires, the fault register CHRG_FAULT bits are set to
11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C by setting EN_TIMER bit.
During input voltage, current or thermal regulation, the safety timer counts at half clock rate as the actual charge
current is likely to be below the register setting. For example, if the charger is in input current regulation
(IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will
expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.
8.2.6 Battery Monitor
The device includes a battery monitor to provide measurements of VBUS voltage, battery voltage, system
voltage, thermistor ratio, and charging current, and charging current based on the device’s modes of operation.
The measurements are reported in Battery Monitor Registers (REG0E-REG12). The battery monitor can be
configured as two conversion modes by using CONV_RATE bit: one-shot conversion (default) and 1 second
continuous conversion.
For one-shot conversion (CONV_RATE = 0), the CONV_START bit can be set to start the conversion. During the
conversion, the CONV_START is set and it is cleared by the device when conversion is completed. The
conversion result is ready after tCONV (maximum 1 second).
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For continuous conversion (CONV_RATE = 1), the CONV_RATE bit can be set to initiate the conversion. During
active conversion, the CONV_START is set to indicate conversion is in progress. The battery monitor provides
conversion result every 1 second automatically. The battery monitor exits continuous conversion mode when
CONV_RATE is cleared.
When battery monitor is active, the REGN power is enabled and can increase device quiescent current.
表 4. Battery Monitor Modes of Operation
MODES OF OPERATION
PARAMETER
REGISTER
DISABLE CHARGE
MODE
CHARGE MODE
BATTERY ONLY MODE
Battery Voltage (VBAT
)
REG0E
REG0F
REG11
REG12
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NA
Yes
Yes
NA
System Voltage (VSYS
VBUS Voltage (VVBUS
Charge Current (IBAT
)
)
)
NA
8.2.7 Status Outputs (PG, STAT, and INT)
8.2.7.1 Power Good Indicator (PG)
In bq25898C, the PG goes LOW to indicate a good input source when:
1. VBUS above VVBUS_UVLO
2. VBUS above battery (not in sleep)
3. VBUS below VACOV threshold
4. VBUS above VVBUSMIN (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
5. Completed Input Source Type Detection
8.2.7.2 Charging Status Indicator (STAT)
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as shown in . The
STAT pin function can be disable by setting STAT_DIS bit.
表 5. STAT Pin State
CHARGING STATE
Charging in progress (including recharge)
STAT INDICATOR
LOW
Charging complete
HIGH
Sleep mode, charge disable
HIGH
Charge suspend (Input overvoltage, timer fault, input or system overvoltage)
blinking at 1 Hz
8.2.7.3 Interrupt to Host (INT)
In some applications, the host does not always monitor the charger operation. The INT notifies the system on the
device operation. The following events will generate 256-µs INT pulse.
•
•
USB/adapter source identified (through PSEL detection)
Good input source detected
–
–
–
VBUS above battery (not in sleep)
VBUS below VACOV threshold
VBUS above VVBUSMIN (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
•
•
•
Input removed
Charge Complete
Any FAULT event in REG0C
When a fault occurs, the charger device sends out INT and keeps the fault state in REG0C until the host reads
the fault register. Before the host reads REG0C and all the faults are cleared, the charger device would not send
any INT upon new faults. To read the current fault status, the host has to read REG0C two times consecutively.
The 1st read reports the pre-existing fault register status and the 2nd read reports the current fault register status.
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8.2.8 Thermal Regulation and Thermal Shutdown
8.2.8.1 Thermal Protection in Buck Mode
The device monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface
temperature in buck mode. When the internal junction temperature exceeds the preset thermal regulation limit
(TREG bits), the device lowers down the charge current. The wide thermal regulation range from 60ºC to 120ºC
allows the user to optimize the system thermal performance.
During thermal regulation, the actual charging current is usually below the programmed battery charging current.
Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register
THERM_STAT bit goes high.
Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface
temperature exceeds TSHUT. The fault register CHRG_FAULT is set to 10 and an INT is asserted to the host. The
BATFET and converter is enabled to recover when IC temperature is below TSHUT_HYS
.
8.2.9 Voltage and Current Monitoring in Buck
8.2.9.1 Voltage and Current Monitoring in Buck Mode
The device closely monitors the input and system voltage, as well as HSFET current for safe buck mode
operations.
8.2.9.1.1 Input Overvoltage (ACOV)
The input voltage for buck mode operation is VVBUS_OP. If VBUS voltage exceeds VACOV, the device stops
switching immediately. During input over voltage (ACOV), the fault register CHRG_FAULT bits sets to 01. An INT
is asserted to the host.
8.2.9.1.2 System Overvoltage Protection (SYSOVP)
The charger device clamps the system voltage during load transient so that the components connect to system
would not be damaged due to high voltage. When SYSOVP is detected, the converter stops immediately to
clamp the overshoot.
8.2.10 Battery Protection
8.2.10.1 Battery Overvoltage Protection (BATOVP)
The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage
occurs, the charger device immediately disables charge. The fault register BAT_FAULT bit goes high and an INT
is asserted to the host.
8.2.10.2 Battery Over-Discharge Protection
When battery is discharged below VBAT_DPL, the BATFET is turned off to protect battery from over discharge. To
recover from over-discharge, an input source is required at VBUS. When an input source is plugged in, the
BATFET turns on. Thy is charged with IBATSHORT (typically 100 mA) current when the VBAT < VSHORT, or
precharge current as set in IPRECHG register when the battery voltage is between VSHORT and VBATLOWV
.
8.2.11 Serial Interface
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial
data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing
data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals
to permit that transfer. At that time, any device addressed is considered a slave.
The device operates as a slave device with address 6BH, receiving control inputs from the master device like
micro controller or a digital signal processor through REG00-REG14. Register read beyond REG14 (0x14)
returns 0xFF. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits).
When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be connected to the
positive supply voltage via a current source or pull-up resistor.
20
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8.2.11.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
SDA
SCL
Change
of data
allowed
Data line stable;
Data valid
图 11. Bit Transfer on the I2C Bus
8.2.11.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
{5!
{/[
{5!
{/[
{Çht (t)
{Ç!wÇ ({)
图 12. START and STOP conditions
8.2.11.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data
transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
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!cknoꢁledgement
signal from revceiver
!cknoꢁledgement
signal from slave
ꢀ{.
1
ꢂ or
{r
{ or {r
2
7
8
9
!/Y
1
2
8
9
!/Y
{Ç!wÇ or
wepeated
{Ç!wÇ
{Çhꢂ or
wepeated
图 13. Data Transfer on the I2C Bus
8.2.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge 9th clock pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
8.2.11.5 Slave Address and Data Direction Bit
After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction
bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
{5!
{
8
9
8
9
8
9
t
{/[
1-7
1-7
1-7
{Ç!wÇ
!55wꢀ{{
wꢁí !/Y
5!Ç!
!/Y
5!Ç!
!/Y
{Çht
图 14. Complete Data Transfer
8.2.11.6 Single Read and Write
1
8
1
1
7
1
0
1
1
8
Slave Address
ACK
Reg Addr
ACK
P
S
ACK
Data Addr
图 15. Single Write
1
8
1
1
1
7
1
0
1
1
1
7
Slave Address
ACK
Reg Addr
ACK
S
S
ACK
Slave Address
1
1
8
P
Data
NCK
图 16. Single Read
If the register address is not defined, the charger IC send back NACK and go back to the idle state.
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8.2.11.7 Multi-Read and Multi-Write
The charger device supports multi-read and multi-write on REG00 through REG14 except REG0C.
图 17. Multi-Write
图 18. Multi-Read
REG0C is a fault register. It keeps all the fault information from last read until the host issues a new read. For
example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG0C reports the
fault when it is read the first time, but returns to normal when it is read the second time. In order to get the fault
information at present, the host has to read REG0C for the second time. The only exception is NTC_FAULT
which always reports the actual condition on the TS pin. In addition, REG0C does not support multi-read and
multi-write.
8.3 Device Functional Modes
8.3.1 Host Mode and Default Mode
The device is a host controlled charger. The device cannot operate in default mode without host management
because default charge current is set to 0 mA (charge disabled).
All the device parameters can be programmed by the host. To keep the device in host mode, the host has to
reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT
bit is set), or disable watchdog timer by setting WATCHDOG bits=00.
When the watchdog timer (WATCHDOG_FAULT bit = 1) is expired, the device returns to default mode and all
registers are reset to default values except IINLIM, VINDPM, VINDPM_OS bits.
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Device Functional Modes (接下页)
thw
ꢀaꢁcꢂdog ꢁimer expired
weseꢁ regisꢁers
L2/ inꢁerface enabled
Iosꢁ ꢃode
{ꢁarꢁ ꢀaꢁcꢂdog ꢁimer
Iosꢁ programs regisꢁers
ò
L2/ íriꢁe?
ꢄ
5efaulꢁ ꢃode
weseꢁ ꢀaꢁcꢂdog ꢁimer
weseꢁ selecꢁive regisꢁers
ò
í5_w{Ç biꢁ = 1?
ꢄ
ò
ꢄ
L2/ íriꢁe?
ò
ꢄ
íaꢁcꢂdog Çimer
9xpired?
图 19. Watchdog Timer Flow Chart
24
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8.4 Register Map
I2C Slave Address: 6BH (1101011B + R/W)
8.4.1 REG00
图 20. REG00
7
0
6
1
5
0
4
1
3
1
2
1
1
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 6. REG00
Bit
Field
Type
Reset
Description
Enable HIZ Mode
0 – Disable (default)
1 – Enable
by REG_RST
by Watchdog
7
EN_HIZ
R/W
6
5
4
3
2
1
0
Reserved
IINLIM[5]
IINLIM[4]
IINLIM[3]
IINLIM[2]
IINLIM[1]
IINLIM[0]
R
N/A
Reserved Always reads 1
R/W
R/W
R/W
R/W
R/W
R/W
by REG_RST
by REG_RST
by REG_RST
by REG_RST
by REG_RST
by REG_RST
1600mA
Input Current Limit
Offset: 100mA
800mA
400mA
200mA
100mA
50mA
Range: 100mA (000000) – 3.25A (111111)
Default:011100 (1500mA)
(Actual input current limit is the lower of I2C or ILIM pin)
IINLIM bits are changed automatically after input source
type detection is completed
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8.4.2 REG01
图 21. REG01
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
1
R
R
R
R
R
R
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 7. REG01
Bit
7
Field
Type
R
Reset
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved, Always read 0
Reserved, Always read 0
Reserved, Always read 0
Reserved, Always read 0
Reserved, Always read 0
Reserved, Always read 0
Reserved, Always read 0
6
R
5
R
4
R
3
R
2
R
1
R
VINDPM offset threshold
Default 600mV (1)
0 - 400mA offset
0
VDPM_OS
R/W
by REG_RST
1 - 600mA offset
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8.4.3 REG02
图 22. REG02
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
1
R/W
R/W
R
R
R
R
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 8. REG02
Bit
Field
Type
Reset
Description
ADC Conversion Start Control
0 – ADC conversion not active (default).
1 – Start ADC Conversion
This bit is read-only when CONV_RATE = 1. The bit stays high during
ADC conversion and during input source detection.
by REG_RST
by Watchdog
7
CONV_START
R/W
ADC Conversion Rate Selection
0 – One shot ADC conversion (default)
1 – Start 1s Continuous Conversion
by REG_RST
by Watchdog
6
CONV_RATE
R/W
5
4
3
2
Reserved
Reserved
Reserved
Reserved
R
R
R
R
N/A
N/A
N/A
N/A
Reserved, Always read 0
Reserved, Always read 0
Reserved, Always read 0
Reserved, Always read 0
Force PSEL Detection
0 – Not in PSEL detection (default)
1 – Force PSEL detection
by REG_RST
by Watchdog
1
0
FORCE_DPDM
R/W
R/W
Automatic Detection Enable
0 –Disable PSEL detection when VBUS is plugged-in
1 –Enable PEL detection when VBUS is plugged-in (default)
AUTO_DPDM_EN
by REG_RST
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8.4.4 REG03
图 23. REG03
7
0
6
0
5
0
4
1
3
1
2
0
1
1
0
0
R
R/W
R
R/W
R/W
R/W
R/W
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 9. REG03
Bit
Field
Type
Reset
Description
7
Reserved
R
N/A
Reserved Always read 0
I2C Watchdog Timer Reset
0 – Normal (default)
1 – Reset (Back to 0 after timer reset)
by REG_RST
by Watchdog
6
5
4
WD_RST
R/W
R
Reserved
N/A
Reserved Always read 0
Charge Enable Configuration
0 - Charge Disable
1- Charge Enable (default)
by REG_RST
by Watchdog
CHG_CONFIG
R/W
3
2
1
0
SYS_MIN[2]
SYS_MIN[1]
SYS_MIN[0]
Reserved
R/W
R/W
R/W
R
by REG_RST
by REG_RST
by REG_RST
N/A
0.4V
0.2V
0.1V
Minimum System Voltage Limit
Offset: 3.0V
Range 3.0V-3.7V
Default: 3.5V (101)
Reserved Always read 0
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8.4.5 REG04
图 24. REG04
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 10. REG04
Bit
7
Field
Type
R
Reset
N/A
Description
Reserved
Reserved
Reserved Always reads 0
Reserved Always reads 0
6
R
N/A
by REG_RST
by Watchdog
5
4
3
2
1
0
ICHG[5]
ICHG[4]
ICHG[3]
ICHG[2]
ICHG[1]
ICHG[0]
R/W
R/W
R/W
R/W
R/W
R/W
2048mA
by REG_RST
by Watchdog
Fast Charge Current Limit
Offset: 0mA
Range: 0mA (000000) – 3008mA (101111) Default: 0mA
(000000)
Note:
ICHG=000000 (0mA) disables both fast charge and
precharge
ICHG > 101111 (3008mA) is clamped to register value
101111 (3008mA)
1024mA
512mA
256mA
128mA
64mA
by REG_RST
by Watchdog
by REG_RST
by Watchdog
by REG_RST
by Watchdog
by REG_RST
by Watchdog
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8.4.6 REG05
图 25. REG05
7
0
6
0
5
0
4
1
3
0
2
0
1
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 11. REG05
Bit
Field
Type
Reset
Description
by REG_RST
by Watchdog
7
IPRECHG[3]
R/W
512mA
by REG_RST
by Watchdog
Precharge Current Limit
Offset: 64mA
Range: 64mA – 1024mA
6
5
4
3
2
1
0
IPRECHG[2]
IPRECHG[1]
IPRECHG[0]
ITERM[3]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
256mA
128mA
64mA
by REG_RST
by Watchdog
Default: 0mA when REG04[5:0] = 000000
by REG_RST
by Watchdog
by REG_RST
by Watchdog
512mA
256mA
128mA
64mA
by REG_RST
by Watchdog
Termination Current Limit
Offset: 64mA
Range: 64mA – 1024mA
Default: 256mA (0011)
ITERM[2]
by REG_RST
by Watchdog
ITERM[1]
by REG_RST
by Watchdog
ITERM[0]
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8.4.7 REG06
图 26. REG06
7
0
6
1
5
0
4
1
3
1
2
1
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 12. REG06
Bit
Field
Type
Reset
Description
by REG_RST
by Watchdog
7
VREG[5]
R/W
512mV
by REG_RST
by Watchdog
6
5
4
3
2
VREG[4]
VREG[3]
VREG[2]
VREG[1]
VREG[0]
R/W
R/W
R/W
R/W
R/W
256mV
128mV
64mV
32mV
16mV
Charge Voltage Limit
Offset: 3.840V
Range: 3.840V – 4.608V (110000)
Default: 4.208V (010111)
Note:
by REG_RST
by Watchdog
by REG_RST
by Watchdog
VREG > 110000 (4.608V) is clamped to register value
110000 (4.608V)
by REG_RST
by Watchdog
by REG_RST
by Watchdog
Battery Precharge to Fast Charge Threshold
0 – 2.8V
1 – 3.0V (default)
by REG_RST
by Watchdog
1
0
BATLOWV
VRECHG
R/W
R/W
Battery Recharge Threshold Offset
(below Charge Voltage Limit)
0 – 100mV (VRECHG) below VREG (REG06[7:2]) (default)
1 – 200mV (VRECHG) below VREG (REG06[7:2])
by REG_RST
by Watchdog
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8.4.8 REG07
图 27. REG07
7
1
6
0
5
0
4
1
3
1
2
1
1
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 13. REG07
Bit
Field
Type
Reset
Description
Charging Termination Enable
0 – Disable
1 – Enable (default)
by REG_RST
by Watchdog
7
EN_TERM
R/W
STAT Pin Disable
0 – Enable STAT pin function (default)
1 – Disable STAT pin function
by REG_RST
by Watchdog
6
STAT_DIS
R/W
by REG_RST
by Watchdog
I2C Watchdog Timer Setting
00 – Disable watchdog timer
01 – 40s (default)
10 – 80s
5
4
WATCHDOG[1]
WATCHDOG[0]
R/W
R/W
by REG_RST
by Watchdog
11 – 160s
Charging Safety Timer Enable
0 – Disable
1 – Enable (default)
by REG_RST
by Watchdog
3
2
EN_TIMER
R/W
R/W
by REG_RST
by Watchdog
Fast Charge Timer Setting
00 – 5 hrs
CHG_TIMER[1]
01 – 8 hrs
10 – 12 hrs (default)
11 – 20 hrs
by REG_RST
by Watchdog
1
0
CHG_TIMER[0]
Reserved
R/W
R
N/A
Reserved always reads 1
32
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8.4.9 REG08
图 28. REG08
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
1
R
R
R
R
R
R
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 14. REG08
Bit
7
Field
Type
R
Reset
N/A
N/A
N/A
N/A
N/A
N/A
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6
R
Reserved Always reads 000
Reserved Always reads 000
5
R
4
R
3
R
2
R
by REG_RST
by Watchdog
Thermal Regulation Threshold
00 – 60°C
01 – 80°C
10 – 100°C
11 – 120°C (default)
1
0
TREG[1]
TREG[0]
R/W
R/W
by REG_RST
by Watchdog
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8.4.10 REG09
图 29. REG09
7
0
6
1
5
0
4
0
3
0
2
1
1
0
0
0
R
R/W
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 15. REG09
Bit
Field
Type
Reset
Description
Reserved Always reads 0
Safety Timer Setting during DPM or Thermal Regulation
7
Reserved
R
N/A
0 – Safety timer not slowed by 2X during input DPM or thermal
6
TMR2X_EN
R/W
by Watchdog
regulation
1 – Safety timer slowed by 2X during input DPM or thermal regulation
(default)
Force BATFET off to enable ship mode with tSM_DLY delay time
0 – Allow BATFET turn on (default)
5
BATFET_DIS
R/W
by REG_RST
1 – Force BATFET off
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
Reserved Always reads 0
Reserved Always reads 0
Reserved Always reads 1
Reserved Always reads 0
Reserved Always reads 0
34
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8.4.11 REG0A
图 30. REG0A
7
0
6
1
5
1
4
1
3
0
2
1
1
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 16. REG0A
Bit
7
Field
Type
R
Reset
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved Always reads 0
Reserved Always reads 1
Reserved Always reads 1
Reserved Always reads 1
Reserved Always reads 0
Reserved Always reads 1
Reserved Always reads 0
Reserved Always reads 0
6
R
5
R
4
R
3
R
2
R
1
R
0
R
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8.4.12 REG0B
图 31. REG0B
7
x
6
x
5
x
4
x
3
x
2
x
1
1
0
x
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 17. REG0B
Bit
7
Field
Type
R
Reset
N/A
Description
VBUS_STAT[2]
VBUS_STAT[1]
VBUS Status register
000: No Input
001: USB Host SDP
010: Adapter (3.25A)
111: N/A
6
R
N/A
5
4
VBUS_STAT[0]
CHRG_STAT[1]
R
R
N/A
N/A
Note: Software current limit is reported in IINLIM register
Charging Status
00 – Not Charging
01 – Pre-charge ( < VBATLOWV
10 – Fast Charging
)
3
CHRG_STAT[0]
R
N/A
11 – Charge Termination Done
Power Good Status
0 – Not Power Good
1 – Power Good
2
1
0
PG_STAT
Reserved
R
R
R
N/A
N/A
N/A
Reserved
VSYS Regulation Status
0 – Not in VSYSMIN regulation (BAT > VSYSMIN)
1 – In VSYSMIN regulation (BAT < VSYSMIN)
VSYS_STAT
36
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8.4.13 REG0C
图 32. REG0C
7
x
6
x
5
x
4
x
3
x
2
x
1
x
0
x
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 18. REG0C
Bit
Field
Type
Reset
Description
Watchdog Fault Status
Status 0 – Normal
7
WATCHDOG_FAULT
R
N/A
1- Watchdog timer expiration
6
5
Reserved
R
R
N/A
N/A
Reserved
CHRG_FAULT[1]
Charge Fault Status
00 – Normal
01 – Input fault (VBUS > VACOV or VBAT < VBUS < VVBUSMIN(typical 3.8V)
)
4
CHRG_FAULT[0]
R
N/A
10 - Thermal shutdown
11 – Charge Safety Timer Expiration
Battery Fault Status
0 – Normal
3
BAT_FAULT
R
N/A
1 – BATOVP (VBAT > VBATOVP
)
2
1
0
Reserved
Reserved
Reserved
R
R
R
N/A
N/A
N/A
Reserved
Reserved
Reserved
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8.4.14 REG0D
图 33. REG0D
7
0
6
0
5
0
4
1
3
0
2
0
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 19. REG0D
Bit
Field
Type
Reset
Description
VINDPM Threshold Setting Method
7
FORCE_VINDPM
R/W
by REG_RST
0 – Run Relative VINDPM Threshold (default)
1 – Run Absolute VINDPM Threshold
6
5
4
3
2
1
0
VINDPM[6]
VINDPM[5]
VINDPM[4]
VINDPM[3]
VINDPM[2]
VINDPM[1]
VINDPM[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
by REG_RST
by REG_RST
by REG_RST
by REG_RST
by REG_RST
by REG_RST
by REG_RST
6400mV
3200mV
1600mV
800mV
400mV
200mV
100mV
Absolute VINDPM Threshold
Offset: 2.6V
Range: 3.9V (0001101) – 15.3V (1111111)
Default: 4.4V (0010010)
Note:
Value < 0001101 is clamped to 3.9V (0001101)
Register is read only when FORCE_VINDPM=0 and can
be written by internal control based on relative VINDPM
threshold setting
Register can be read/write when FORCE_VINDPM = 1
8.4.15 REG0E
图 34. REG0E
7
x
6
x
5
x
4
x
3
x
2
x
1
x
0
x
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 20. REG0E
Bit
Field
Type
Reset
Description
Thermal Regulation Status
0 – Normal
7
THERM_STAT
R
N/A
1 – In Thermal Regulation
6
5
4
3
2
1
0
BATV[6]
BATV[5]
BATV[4]
BATV[3]
BATV[2]
BATV[1]
BATV[0]
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1280mV
640mV
320mV
160mV
80mV
40mV
20mV
ADC conversion of Battery Voltage (VBAT)
38
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8.4.16 REG0F
图 35. REG0F
7
0
6
x
5
x
4
x
3
x
2
x
1
x
0
x
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 21. REG0F
Bit
7
Field
Type
R
Reset
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Reserved
SYSV[6]
SYSV[5]
SYSV[4]
SYSV[3]
SYSV[2]
SYSV[1]
SYSV[0]
Reserved: Always reads 0
6
R
1280mV
640mV
320mV
5
R
4
R
3
R
160mV
80mV
40mV
20mV
ADC conversion of System Voltage (VSYS)
2
R
1
R
0
R
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8.4.17 REG11
图 36. REG11
7
x
6
x
5
x
4
x
3
x
2
x
1
x
0
x
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 22. REG11
Bit
Field
Type
Reset
Description
VBUS Good Status
0 – Not VBUS attached
1 – VBUS Attached
7
VBUS_GD
R
N/A
6
5
4
3
2
1
0
VBUSV[6]
VBUSV[5]
VBUSV[4]
VBUSV[3]
VBUSV[2]
VBUSV[1]
VBUSV[0]
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
6400mV
3200mV
1600mV
800mV
400mV
200mV
100mV
ADC conversion of VBUS voltage (VBUS
Offset: 2.6V
Range 2.6V (0000000) – 15.3V (1111111)
Default: 2.6V (0000000)
)
8.4.18 REG12
图 37. REG12
7
0
6
x
5
x
4
x
3
x
2
x
1
x
0
x
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 23. REG12
Bit
7
Field
Type
R
Reset
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Always reads 0
3200mA
Reserved
ICHGR[6]
ICHGR[5]
ICHGR[4]
ICHGR[3]
ICHGR[2]
ICHGR[1]
ICHGR[0]
6
R
5
R
1600mA
800mA
400mA
200mA
100mA
50mA
ADC conversion of Charge Current (IBAT) when VBAT
VBATSHORT
Offset: 0mA
Range 0mA (0000000) – 6350mA (1111111)
Default: 0mA (0000000)
>
4
R
3
R
2
R
Note:
This register returns 0000000 for VBAT < VBATSHORT
1
R
0
R
40
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8.4.19 REG13
图 38. REG13
7
x
6
x
5
x
4
x
3
x
2
x
1
x
0
x
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 24. REG13
Bit
Field
Type
Reset
Description
VINDPM Status
0 – Not in VINDPM
1 – VINDPM
7
VDPM_STAT
R
N/A
IINDPM Status
0 – Not in IINDPM
1 – IINDPM
6
IDPM_STAT
R
N/A
5
4
3
2
1
0
IDPM_LIM[5]
IDPM_LIM[4]
IDPM_LIM[3]
IDPM_LIM[2]
IDPM_LIM[1]
IDPM_LIM[0]
R
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
1600mA
800mA
400mA
Input Current Limit in effect
200mA
100mA
50mA
8.4.20 REG14
图 39. REG14
7
0
6
x
5
0
4
0
3
1
2
1
1
0
0
1
R/W
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 25. REG14
Bit
Field
Type
Reset
Description
Register Reset
0 – Keep current register setting (default)
7
REG_RST
R/W
N/A
1 – Reset to default register value and reset safety timer
Note:
Reset to 0 after register reset is completed
6
5
4
3
2
1
0
Reserved
PN[2]
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Reserved
Device Configuration
001: bq25898C
PN[1]
PN[0]
Reserved
DEV_REV[1]
DEV_REV[0]
Reserved Always reads 1
Device Revision: 01
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A typical application consists of the device configured as an I2C controlled power path management device and a
single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smartphones and other
portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2),
low-side switching FET (LSFET, Q3), and BATFET (Q4) between the system and battery. The device also
integrates a bootstrap diode for the high-side gate drive.
9.2 Typical Application Diagram
Input
3.9Vœ14V@3A
1mH
USB
1mF
8.2mF
10mF
10mF
Ichg=3A
VREF
10mF
Host
Copyright © 2016, Texas Instruments Incorporated
VREF is the pull up voltage of I2C communication interface
图 40. bq25898C Application Diagram as Slave Charger
9.2.1 Design Requirements
For this design example, use the parameters shown in 表 26.
表 26. Design Parameters
PARAMETER
Input voltage range
Input current limit
Fast charge current
Output voltage
VALUE
3.9 V to 14 V
1.5 A
3000 mA
4.208 V
42
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ZHCSG51B –MARCH 2016–REVISED MARCH 2017
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The device has 1.5 MHz switching frequency to allow the use of small inductor and capacitor values. The
Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
I
³ I
+ (1/2) I
BAT
CHG
RIPPLE
(1)
The inductor ripple current depends on input voltage (VBUS), duty cycle (D = VBAT/VVBUS), switching frequency (fs)
and inductance (L):
V
x D x (1-D)
BUS
I
=
RIPPLE
f s x L
(2)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in
the range of (20–40%) maximum charging current as a trade-off between inductor size and efficiency for a
practical design.
9.2.2.2 Buck Input Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at
50% duty cycle, then the worst case capacitor RMS current IPMID occurs where the duty cycle is closest to 50%
and can be estimated by 公式 3:
I
= I x D x (1 - D)
CHG
PMID
(3)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. 25 V rating or higher capacitor is preferred
for up to 14-V input voltage. 8.2-μF capacitance is suggested.
9.2.2.3 System Output Capacitor
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current ICOUT is given:
I
RIPPLE
I
=
» 0.29 x I
RIPPLE
CSYS
2 x
3
(4)
The output capacitor voltage ripple can be calculated as follows:
æ
ö
÷
÷
÷
V
V
SYS
SYS
ç
DV
=
ç1-
O
ç
ç
è
2
÷
ø
V
BUS
8 LC
SYS
f s
(5)
At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC. The charger device has internal loop compensator. To get good loop stability, 1-µH and minimum
of 20-µF output capacitor is recommended. The preferred ceramic capacitor is 6V or higher rating, X7R or X5R.
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9.2.3 Application Curves
VBAT = 3.2 V,
VBUS = 5 V
VBAT = 3.2 V,
VBUS = 5 V
图 41. Power Up with Charge Disabled
图 42. Power Up with Charge Enabled
VBUS = 5 V
VBUS = 5 V
图 43. Charge Enable
图 44. Charge Disable
VBUS = 12 V
VBAT = 3.8 V
ICHG = 3 A
VBUS = 9V
No Battery
ISYS = 20 mA,
Charge Disable
图 45. PWM Switching Waveform
图 46. PFM Switching Waveform
44
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ZHCSG51B –MARCH 2016–REVISED MARCH 2017
VBAT = 3.2 V
VBUS = 12 V
VBUS = 12 V
图 47. Power Up with Charge Disabled
图 48. Charge Enable
VBUS = 12 V
VBUS = 12 V
VBAT = 3.8 V
ICHG = 3 A
图 49. Charge Disable
图 50. PWM Switching Waveform
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10 Power Supply Recommendations
In order to provide an output voltage on SYS, the device requires a power supply between 3.9 V and 14 V input
with at least 100-mA current rating connected to VBUS or a single-cell Li-Ion battery with voltage > VBATUVLO
connected to BAT. The source current rating needs to be at least 3 A in order for the buck converter of the
charger to provide maximum output power to SYS.
11 Layout
11.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see 图 51) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout PCB according to this specific order is essential.
1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper
trace connection or GND plane.
2. Put output capacitor near to the inductor and the IC.
3. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
4. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
5. Connect all grounds together to reduce PCB size and improve thermal dissipation.
6. Avoid ground planes in parallel with high frequency traces in other layers.
11.2 Layout Example
图 51. High Frequency Current Path
46
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12 器件和文档支持
12.1 器件支持
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
版权 © 2016–2017, Texas Instruments Incorporated
47
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25898CYFFR
BQ25898CYFFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
42
42
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
BQ25898C
BQ25898C
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25898CYFFR
BQ25898CYFFR
BQ25898CYFFT
BQ25898CYFFT
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
42
42
42
42
3000
3000
250
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
2.66
2.66
2.66
2.66
2.95
2.95
2.95
2.95
0.81
0.81
0.81
0.81
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ25898CYFFR
BQ25898CYFFR
BQ25898CYFFT
BQ25898CYFFT
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
42
42
42
42
3000
3000
250
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
20.0
250
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0042
DSBGA - 0.625 mm max height
S
C
A
L
E
4
.
5
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
BALL TYP
0.30
0.12
2 TYP
SYMM
G
F
E
D
C
D: Max = 2.852 mm, Min =2.792 mm
E: Max = 2.558 mm, Min =2.498 mm
SYMM
2.4
TYP
0.3
0.2
42X
B
A
0.015
C A
B
0.4 TYP
1
2
3
4
5
6
0.4 TYP
4222067/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0042
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
42X ( 0.23)
(0.4) TYP
1
2
4
5
6
A
B
C
SYMM
D
E
F
G
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
0.05 MIN
(
0.23)
(
0.23)
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4222067/A 05/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0042
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
42X ( 0.25)
(R0.05) TYP
1
2
3
4
5
6
A
(0.4)
TYP
B
METAL
TYP
C
D
E
F
SYMM
G
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4222067/A 05/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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