BQ25601RTWT [TI]
具有电源路径和 OTG 的 I2C 单节 3A 降压电池充电器 | RTW | 24 | -40 to 85;
| 型号： | BQ25601RTWT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电源路径和 OTG 的 I2C 单节 3A 降压电池充电器 | RTW | 24 | -40 to 85 电池 |
| 文件： | 总65页 (文件大小：2610K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ25601
ZHCSGA3A –MARCH 2017 –REVISED MARCH 2023
BQ25601 用于高输入电压和NVDC 电源路径管理的I2C 控制型单节电池3A 降
压电池充电器
1 特性
2 应用
• 高效1.5MHz 同步开关模式降压充电器
• 智能手机
• 手机附件
• 医疗设备
– 在2A 电流（5V 输入）下具有92% 的充电效率
– 针对USB 电压输入(5V) 进行了优化
– 用于轻负载运行的可选低功耗脉冲频率调制
(PFM) 模式
3 说明
BQ25601 是一款高度集成的 3A 开关模式电池充电管
理和系统电源路径管理器件，适用于单节锂离子和锂聚
合物电池。其低阻抗电源路径对开关模式运行效率进行
了优化、缩短了电池充电时间并延长了放电阶段的电池
使用寿命。具有充电和系统设置的 I2C 串行接口使得此
器件成为一种真正灵活的解决方案。
• 支持USB On-The-Go (OTG)
– 具有高达1.2A 输出的升压转换器
– 在1A 输出下具有92% 的升压效率
– 精确的恒定电流(CC) 限制
– 高达500µF 容性负载的软启动
– 输出短路保护
器件信息
封装(1)
– 低功耗PFM 模式，适合轻载运行
• 单个输入，支持USB 输入和高电压适配器
封装尺寸（标称值）
器件型号
BQ25601
WQFN (24)
4.00mm x 4.00mm
– 支持3.9V 至13.5V 输入电压范围，绝对最大输
入电压额定值为22V
– 可编程输入电流限制（100mA 至3.2A，分辨率
为100mA），支持USB2.0、USB3.0 标准和高
电压适配器(IINDPM)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 通过高达5.4V 的输入电压限制(VINDPM) 进行
最大功率跟踪
– VINDPM 阈值自动跟踪电池电压
– 自动检测USB SDP、DCP 以及非标准适配器
• 高电池放电效率，电池放电MOSFET 为19.5mΩ
• 窄VDC (NVDC) 电源路径管理
– 无需电池或深度放电的电池即可瞬时启动
– 电池充电模式下实现理想二极管运行
• BATFET 控制，支持运输模式、唤醒和完全系统复
位
• 灵活的自主和I2C 模式，可实现最优系统性能
• 高集成度，包括所有MOSFET、电流检测和环路补
偿
简化版应用
• 高精度
– 充电电压调节范围为±0.5%
– ±5% 1.5A 充电电流调节
• 安全及管理批准：
– IEC 62368-1 终端设备标准
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSCK5
BQ25601
www.ti.com.cn
ZHCSGA3A –MARCH 2017 –REVISED MARCH 2023
Table of Contents
9.5 Programming............................................................ 30
9.6 Register Maps...........................................................34
10 Application and Implementation................................45
10.1 Application Information........................................... 45
10.2 Typical Application.................................................. 46
11 Power Supply Recommendations..............................52
12 Layout...........................................................................53
12.1 Layout Guidelines................................................... 53
12.2 Layout Example...................................................... 53
13 Device and Documentation Support..........................55
13.1 Device Support....................................................... 55
13.2 Documentation Support.......................................... 55
13.3 接收文档更新通知................................................... 55
13.4 支持资源..................................................................55
13.5 Trademarks.............................................................55
13.6 静电放电警告.......................................................... 55
13.7 术语表..................................................................... 55
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Device Comparison Table...............................................4
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 7
8.1 Absolute Maximum Ratings........................................ 7
8.2 ESD Ratings............................................................... 7
8.3 Recommended Operating Conditions.........................7
8.4 Thermal Information....................................................8
8.5 Electrical Characteristics.............................................8
8.6 Timing Requirements................................................13
8.7 Typical Characteristics..............................................14
9 Detailed Description......................................................16
9.1 Overview...................................................................16
9.2 Functional Block Diagram.........................................17
9.3 Feature Description...................................................18
9.4 Device Functional Modes..........................................26
Information.................................................................... 56
4 Revision History
Changes from Revision * (March 2017) to Revision A (March 2023)
Page
• 添加了 IEC 62368-1 特性................................................................................................................................... 1
• 删除了整个数据表中的 WEBENCH.................................................................................................................... 1
• Added 节6 .........................................................................................................................................................4
• Deleted OVPFET_DIS = 1 from Quiescent Currents IBAT and IVBUS_HIZ Test Conditions in 节8.5 ................... 8
• Deleted VREGN MAX values in 节8.5 .................................................................................................................8
• Deleted 节8.5 table note....................................................................................................................................8
• Added 节8.6 ....................................................................................................................................................13
• Added last sentence to 节9.3.3.5 ....................................................................................................................19
• Changed 图9-3 ............................................................................................................................................... 23
• Changed 图9-4 ............................................................................................................................................... 23
• Added 图9-5 ....................................................................................................................................................23
• Added Charge termination is disabled for cool and warm conditions. to third paragraph in 节9.3.7.5 ........... 23
• Changed 图9-6 ............................................................................................................................................... 24
• Changed "fault" to "the timer" in last paragraph of 节9.3.7.7 ..........................................................................24
• Added 节9.4 ....................................................................................................................................................26
• Changed 图9-7 ............................................................................................................................................... 26
• Changed first sentence in 节9.4.3 .................................................................................................................. 27
• Added 节9.5 ....................................................................................................................................................30
• Changed inclusive terminology throughout document......................................................................................30
• Changed 010 to 011 in Description in 表9-13 .................................................................................................42
• Changed Power Path Management Application schematic..............................................................................46
• Added 节10.2.1 ...............................................................................................................................................46
• Changed > to ≤in last paragraph in 节10.2.2.3 ............................................................................................ 47
• Added 节10.2.3 ...............................................................................................................................................48
• Added 节13.2.1 ...............................................................................................................................................55
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5 说明（续）
BQ25601 可为智能手机、平板电脑和便携式设备提供快速充电功能和高输入电压支持。其输入电压和电流调节可
以为电池提供最大的充电功率。它还集成了自举二极管以进行高侧栅极驱动，从而简化系统设计。I2C 串行接口与
充电和系统设置使该器件成为一款真正灵活的解决方案。
该器件支持多种输入源，包括标准 USB 主机端口、USB 充电端口以及兼容USB 的高电压适配器。该器件根据内
置USB 接口设置默认输入电流限值。为了设置默认输入电流限值，该器件从系统检测电路（如USB PHY 器件）
中获取结果。该器件符合 USB 2.0 和 USB 3.0 电源规范，具有输入电流和电压调节功能。该器件还具有高达
1.2A 的恒定电流限制能力，能够为VBUS 提供5.15V 的电压，符合USB On-the-Go (OTG) 运行功率等级规格。
电源路径管理将系统电压调节至稍高于电池电压的水平，但是不会下降至 3.5V 最小系统电压（可编程）以下。借
助于这个特性，即使在电池电量完全耗尽或者电池被拆除时，系统也能保持运行。当达到输入电流限值或电压限
值时，电源路径管理自动将充电电流减少为0。随着系统负载持续增加，电源路径将使电池放电，直到满足系统电
源需求。这种补充模式可防止输入源过载。
此器件无需软件控制即可启动并完成一个充电周期。它可感测电池电压并分三个阶段为电池充电：预充电、恒定
电流和恒定电压。在充电周期结束时，当充电电流低于预设限值并且电池电压高于再充电阈值时，充电器自动终
止。如果充满电的电池降至再充电阈值以下，则充电器自动开启另一个充电周期。
此充电器提供针对电池充电和系统运行的多种安全特性，其中包括电池负温度系数热敏电阻监视、充电安全性计
时器和过压/过流保护。当结温超过 110°C（可编程）时，热调节会减小充电电流。STAT 输出报告充电状态和任
何故障状况。其他安全特性包括针对充电和升压模式的电池温度感应、热调节和热关断以及输入 UVLO 和过压保
护。VBUS_GD 位指示电源是否正常。当故障发生时，INT 输出会立即通知主机。
该器件还提供用于BATFET 使能和复位控制的QON 引脚，以退出低功耗运输模式或完全系统复位功能。
该器件采用24 引脚4mm × 4mm x 0.75mm 薄型WQFN 封装。
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6 Device Comparison Table
BQ25601
BQ25601D
BQ25611D
Programmable charge voltage
3.856 - 4.624 V, 32 mV per step 3.856 - 4.624 V, 32 mV per step 3.5 - 4.3 V (100 mV per step);
4.3 - 4.52 V (10 mV per step)
D+/D- USB detection
Default ICHG
No
2.04 A
6.4 V
200 ns
No
Yes
2.04 A
6.4 V
200 ns
No
Yes
1 A
Default VACOV
14.2 V
130 ns
Yes
VBUS OVP reaction time
Battery remote sensing with open/
short detection
TS profile
JEITA, with fixed temperature
thresholds
JEITA, with fixed temperature
thresholds
JEITA, with adjustable
temperature thresholds
TS ignore bit
No
5 hr, 10 hr (default)
No
No
5 hr, 10 hr (default)
No
Yes
20 hr, 10 hr (default)
Yes
Charge safety timer
Allow QON fire when adapter is
present
Deglitch time for charge ternination
250 ms
250 ms
50 ms
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7 Pin Configuration and Functions
VAC
PSEL
PG
1
2
3
4
5
6
18
17
16
15
14
13
GND
GND
SYS
SYS
BAT
BAT
Thermal
Pad
STAT
SCL
SDA
7
8
9
10 11 12
(Not to scale)
图7-1. RTW Package 24-Pin WQFN Top View
表7-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
13
Battery connection point to the positive terminal of the battery pack. The internal BATFET and current sensing is
connected between SYS and BAT. Connect a 10 µF close to the BAT pin.
BAT
P
14
PWM high side driver positive supply. Internally, the BTST pin is connected to the cathode of the boost-strap diode.
Connect the 0.047-μF bootstrap capacitor from SW to BTST.
BTST
CE
21
P
9
DI
Charge enable pin. When this pin is driven low, battery charging is enabled.
17
18
GND
INT
NC
P
Ground.
Open-drain interrupt Output. Connect the INT to a logic rail through 10-kΩresistor. The INT pin sends an active low,
256-µs pulse to host to report charger device status and fault.
7
DO
—
8
No Connect. Keep the pins float.
10
Open drain active low power good indicator. Connect to the pull up rail through 10-kΩresistor. LOW indicates a
good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current limit
is above 30 mA.
PG
3
23
2
DO
DO
DI
Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Put 10 μF ceramic
capacitor on PMID to GND.
PMID
PSEL
Power source selection input. Set 500 mA input current limit by pulling this pin high and set 2.4A input current limit
by pulling this pin low. Once the device gets into host mode, the host can program different input current limits to
IINDPM register.
BATFET enable/reset control input. When BATFET is in ship mode, a logic low of tSHIPMODE duration turns on
BATFET to exit shipping mode. When VBUS is not plugged in, a logic low of tQON_RST (minimum 8 s) duration resets
SYS (system power) by turning BATFET off for tBATFET_RST (minimum 250 ms) and then re-enable BATFET to
provide full system power reset. The pin contains an internal 200-kΩpull-up to maintain default high logic.
QON
12
22
DI
P
LSFET driver and internal supply output. Internally, REGN is connected to the anode of the boost-strap diode.
Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to GND. The capacitor should be placed close to the
REGN
IC.
I2C interface clock. Connect SCL to the logic rail through a 10-kΩresistor.
I2C interface data. Connect SDA to the logic rail through a 10-kΩresistor.
SCL
SDA
5
6
DI
DIO
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表7-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Open-drain charge status output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin indicates
charger status. Collect a current limit resister and a LED from a rail to this pin.
Charge in progress: LOW
STAT
4
DO
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): 1-Hz, 50% duty cycle Pulses
This pin can be disabled via EN_ICHG_MON[1:0] register bits.
19
20
15
16
SW
P
P
Switching node output. Connected to output inductor. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
Converter output connection point. The internal current sensing network is connected between SYS and BAT.
Connect a 20 µF capacitor close to the SYS pin.
SYS
Temperature qualification voltage input to support JEITA profile. Connect a negative temperature coefficient
thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when
TS pin is out of range. When TS pin is not used, connect a 10-kΩresistor from REGN to TS and connect a 10-kΩ
resistor from TS to GND. It is recommended to use a 103AT-2 thermistor.
TS
11
AI
VAC
1
AI
P
Charge input voltage sense. This pin must be connected to VBUS pin.
Charger input. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID
pins. Place a 1-uF ceramic capacitor from VBUS to GND close to device.
VBUS
24
Thermal pad and ground reference. This pad is ground reference for the device and it is also the thermal pad used
Thermal Pad
P
to conduct heat from the device. This pad should be tied externally to a ground plane through PCB vias under the
pad.
—
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output,
P = Power
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Voltage Range (with respect to
VAC, VBUS (converter not switching)(2)
GND)
22
V
–2
Voltage Range (with respect to
BTST, PMID (converter not switching)(2)
GND)
22
V
–0.3
Voltage Range (with respect to
GND)
SW
16
7
V
V
–2
Voltage Range (with respect to
GND)
BTST to SW
–0.3
Voltage Range (with respect to
GND)
PSEL
7
7
V
V
–0.3
–0.3
Voltage Range (with respect to
GND)
REGN, TS, CE, PG, BAT, SYS (converter not switching)
Output Sink Current
STAT
6
7
mA
V
Voltage Range (with respect to
GND)
SDA, SCL, INT, QON, STAT
–0.3
–0.3
Voltage Range (with respect to
GND)
PGND to GND (QFN package only)
INT
0.3
V
Output Sink Current
6
mA
°C
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
–40
–65
°C
(1) Stresses beyond those listed under Absolute maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.
(2) VBUS is specified up to 22 V for a maximum of one hour at room temperature
8.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
MIN
NOM
MAX UNIT
VBUS
Iin
Input voltage
3.9
13.5 (1)
V
A
A
V
A
A
Input current (VBUS)
Output current (SW)
Battery voltage
3.25
3.25
4.624
3.0
ISWOP
VBATOP
IBATOP
IBATOP
Fast charging current
Discharging current (continuous)
6
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MAX UNIT
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8.3 Recommended Operating Conditions (continued)
MIN
NOM
TA
Operating ambient temperature
85
°C
–40
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum voltage rating on either the BTST or SW pins. A
tight layout minimizes switching noise.
8.4 Thermal Information
BQ25601
THERMAL METRIC(1)
RTW (WQFN)
UNIT
24 PINS
35.6
22.7
11.9
0.2
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
12
ΨJB
RθJC(bot)
2.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
8.5 Electrical Characteristics
VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QUIESCENT CURRENTS
VBAT = 4.5 V, VBUS < VAC-UVLOZ
leakage between BAT and VBUS,
TJ< 85°C
,
Battery discharge current (BAT,
SW, SYS) in buck mode
IBUS
5
µA
µA
VBAT = 4.5 V, HIZ Mode or No VBUS,
I2C disabled, BATFET Disabled. TJ <
85°C
Battery discharge current (BAT)
in buck mode
IBAT
17
33
VBAT = 4.5 V, HIZ Mode or No VBUS,
I2C Disabled, BATFET Enabled. TJ <
85°C
Battery discharge current (BAT,
SW, SYS)
IBAT
58
37
85
50
µA
µA
IVBUS_HIZ
Input supply current (VBUS) in
buck mode
VVBUS = 5 V, High-Z Mode, No
battery
Input supply current (VBUS) in
buck mode
VVBUS = 12 V, High-Z Mode, No
battery
IVBUS_HIZ
IVBUS
68
90
3
µA
Input supply current (VBUS) in
buck mode
VVBUS = 12 V, VVBUS > VVBAT
converter not switching
,
1.5
mA
VVBUS > VUVLO, VVBUS > VVBAT
converter switching, VBAT = 3.8V,
ISYS = 0A
,
Input supply current (VBUS) in
buck mode
IVBUS
3
3
mA
mA
Battery Discharge Current in
boost mode
VBAT = 4.2 V, boost mode, IVBUS = 0
A, converter switching
IBOOST
VBUS, VAC AND BAT PIN POWER-UP
VBUS_OP
VBUS operating range
VVBUS rising
VVAC rising
3.9
13.5
3.6
V
V
VBUS for active I2C, no battery
Sense VAC pin voltage
VVAC_UVLOZ
3.3
VVAC_UVLOZ_HYS
VVAC_PRESENT
I2C active hysteresis
VAC falling from above VVAC_UVLOZ
VVAC rising
300
mV
V
One of the conditions to turn on
REGN
3.65
3.9
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8.5 Electrical Characteristics (continued)
VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VVAC falling
(VVAC–VVBAT ), VBUSMIN_FALL
MIN
TYP
MAX
UNIT
One of the conditions to turn on
REGN
mV
VVAC_PRESENT_HYS
VSLEEP
500
≤
≤
Sleep mode falling threshold
Sleep mode rising threshold
15
60
110
mV
V
BAT ≤VREG, VAC falling
(VVAC–VVBAT ), VBUSMIN_FALL
BAT ≤VREG, VAC rising
VSLEEPZ
115
6.1
220
6.4
340
6.7
mV
V
V
VAC 6.5-V Overvoltage rising
threshold
VVAC_OV_RISE
VVAC_OV_RISE
VVAC_OV_RISE
VVAC_OV_HYS
VVAC_OV_HYS
VAC rising; OVP (REG06[7:6]) = '01'
VAC rising, OVP (REG06[7:6]) = '10'
VAC rising, OVP (REG06[7:6]) = '11'
VAC falling, OVP (REG06[7:6]) = '01'
VAC falling, OVP (REG06[7:6]) = '10'
VAC 10.5-V Overvoltage rising
threshold
10.35
13.5
10.9
14.2
320
11.5
V
VAC 14-V Overvoltage rising
threshold
14.85
V
VAC 6.5-V Overvoltage
hysteresis
mV
mV
VAC 10.5-V Overvoltage
hysteresis
250
300
VVAC_OV_HYS
VBAT_UVLOZ
VBAT_DPL_FALL
VBAT_DPL_RISE
VAC 14-V Overvoltage hysteresis VAC falling, OVP (REG06[7:6]) = '11'
mV
V
BAT for active I2C, no adapter
Battery Depletion Threshold
Battery Depletion Threshold
VBAT rising
VBAT falling
VBAT rising
2.5
2.2
2.6
2.8
V
2.35
V
Battery Depletion rising
hysteresis
VBAT_DPL_HYST
VBAT rising
VBUS falling
180
mV
Bad adapter detection falling
threshold
VBUSMIN_FALL
VBUSMIN_HYST
IBADSRC
3.75
3.9
80
30
4.0
V
Bad adapter detection hysteresis
mV
mA
Bad adapter detection current
source
Sink current from VBUS to GND
POWER-PATH
VSYS_MIN
VBAT < SYS_MIN[2:0] = 101,
BATFET Disabled (REG07[5] = 1)
System regulation voltage
System Regulation Voltage
3.5
4.4
3.68
V
V
ISYS = 0 A, VVBAT > VSYS_MIN, VVBAT
= 4.400 V, BATFET disabled
(REG07[5] = 1)
VBAT + 50
mV
VSYS
Maximum DC system voltage
output
ISYS = 0 A, , Q4 off, VVBAT≤4.400 V,
VVBAT > VSYS_MIN = 3.5V
VSYSMAX
4.45
45
4.48
V
Top reverse blocking MOSFET
on-resistance between VBUS and
PMID - Q1
RON(RBFET)
-40°C≤TA ≤125°C
mΩ
Top switching MOSFET on-
resistance between PMID and
SW - Q2
RON(HSFET)
62
71
VREGN = 5 V , -40°C≤TA ≤125°C
VREGN = 5 V , -40°C≤TA ≤125°C
mΩ
mΩ
Bottom switching MOSFET on-
resistance between SW and GND
- Q3
RON(LSFET)
BATFET forward voltage in
supplement mode
VFWD
30
mV
QFN package, Measured from BAT
to SYS, VBAT = 4.2V, TJ = 25°C
RON(BAT-SYS)
SYS-BAT MOSFET on-resistance
19.5
24
mΩ
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8.5 Electrical Characteristics (continued)
VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QFN package, Measured from BAT
to SYS, VBAT = 4.2V, TJ = –40 -
125°C
RON(BAT-SYS)
SYS-BAT MOSFET on-resistance
19.5
30
mΩ
BATTERY CHARGER
VBATREG_RANGE Charge voltage program range
VBATREG_STEP
3.856
4.624
V
Charge voltage step
32
mV
VREG (REG04[7:3]) = 4.208 V
(01011), V, –40 ≤TJ ≤85°C
4.187
4.330
4.208
4.229
4.374
V
V
VBATREG
Charge voltage setting
VREG (REG04[7:3]) = 4.352 V
(01111), V, –40 ≤TJ ≤85°C
4.352
VBAT = 4.208 V or VBAT = 4.352 V, –
40 ≤TJ ≤85°C
VBATREG_ACC
Charge voltage setting accuracy
0.5%
3000
–0.5%
ICHG_REG_RANGE
ICHG_REG_STEP
Charge current regulation range
Charge current regulation step
0
mA
mA
60
ICHG = 240 mA, VVBAT = 3.1V or
VVBAT = 3.8 V
ICHG_REG
Charge current regulation setting
0.216
0.24
0.264
A
Charge current regulation
accuracy
ICHG = 240 mA, VVBAT = 3.1 V or
VVBAT = 3.8 V
ICHG_REG_ACC
ICHG_REG
10%
–10%
Charge current regulation setting ICHG = 720 mA, VVBAT = 3.1 V or
VVBAT = 3.8 V
0.685
0.720
171
0.755
A
Charge current regulation
accuracy
ICHG_REG = 720 mA, VBAT = 3.1 V or
VBAT = 3.8 V
ICHG_REG
IPRECHG
-5%
153
5%
189
5
Precharge current regulation
IPRECHG[3:0] = '0010' = 180 mA
IPRECHG[3:0] = '0010' = 180 mA
mA
%
Precharge current regulation
accuracy
IPRECHG_ACC
–15
VBATLOWV_FALL
VBATLOWV_RISE
Battery LOWV falling threshold
Battery LOWV rising threshold
ICHG = 240 mA
2.7
3.0
2.8
2.9
V
V
Pre-charge to fast charge
3.12
3.24
ICHG = 1.38 A, VVBAT = 3.1 V or
VVBAT = 3.8 V
ICHG_REG
Charge current regulation setting
1.311
1.380
180
1.449
A
Charge current regulation
accuracy
ICHG = 720 mA or ICHG = 1.38 A,
VVBAT = 3.1 V or VVBAT = 3.8 V
ICHG_REG_ACC
ITERM
5%
–5%
Termination current regulation
ICHG > 780 mA, ITERM[3:0] = '0010'
= 180 mA, VVBAT = 4.208 V
150
216
mA
Termination current regulation
accuracy
ICHG > 780 mA, , ITERM[3:0] = '0010'
= 180 mA, VVBAT = 4.208 V
ITERM_ACC
ITERM
ITERM_ACC
ITERM
-16.7%
162
20%
192
I
CHG ≤780 mA, , ITERM[3:0] =
Termination current regulation
180
60
mA
mA
'0010' = 180 mA
Termination current regulation
accuracy
I
CHG ≤780 mA, , ITERM[3:0] =
-10%
45
10%
75
'0010' = 180 mA
Termination current regulation
ICHG = 600 mA, ITERM[3:0] = '0000'
= 60 mA, VBAT = 4.208 V
Termination current regulation
accuracy
ICHG = 600 mA, ITERM[3:0] = '0000'
= 60 mA, VBAT = 4.208 V
ITERM_ACC
25%
–25%
VSHORT
VSHORTZ
ISHORT
Battery short voltage
Battery short voltage
Battery short current
VBAT falling
1.85
2.15
70
2
2.25
90
2.15
2.35
110
V
V
VBAT rising
VBAT < VSHORTZ
mA
Recharge Threshold below
VBAT_REG
VRECHG
VBAT falling, REG04[0] = 0
90
120
150
mV
Copyright © 2023 Texas Instruments Incorporated
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8.5 Electrical Characteristics (continued)
VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VBAT falling, REG04[0] = 1
VSYS = 4.2 V
MIN
TYP
230
30
MAX
UNIT
mV
Recharge Threshold below
VBAT_REG
VRECHG
200
265
ISYSLOAD
System discharge load current
mA
INPUT VOLTAGE AND CURRENT REGULATION
VINDPM (REG06[3:0] = 0000) = 3.9
V
VINDPM
Input voltage regulation limit
Input voltage regulation accuracy
Input voltage regulation limit
Input voltage regulation accuracy
3.78
–3%
4.268
3.95
4.1
5%
V
VINDPM_ACC
VINDPM
VINDPM (REG06[3:0] = 0110) = 4.4
V
4.4
4.3
4.532
V
V
VINDPM_ACC
VDPM_VBAT
3%
–3%
Input voltage regulation limit
tracking VBAT
VINDPM = 3.9V,
VDPM_VBAT_TRACK = 300mV,
VBAT = 4.0V
4.171
4.43
VDPM_VBAT_ACC
Input voltage regulation accuracy
tracking VBAT
3%
500
900
1.5
–3%
VVBUS = 5 V, current pulled from SW,
IINDPM (REG[4:0] = 00100) = 500
mA, –40 ≤TJ ≤85°C
450
mA
mA
VVBUS = 5 V, current pulled from SW,
IINDPM (REG[4:0] = 01000) = 900
mA, –40 ≤TJ ≤85°C
IINDPM
USB input current regulation limit
750
1.3
VVBUS = 5 V, current pulled from SW,
IINDPM (REG[4:0] = 01110) = 1.5 A,
–40 ≤TJ ≤85°C
A
Input current limit during system
start-up sequence
IIN_START
200
mA
BAT PIN OVERVOLTAGE PROTECTION
VBATOVP_RISE Battery overvoltage threshold
VBATOVP_FALL Battery overvoltage threshold
THERMAL REGULATION AND THERMAL SHUTDOWN
VBAT rising, as percentage of
VBAT_REG
103
101
104
102
105
103
%
%
VBAT falling, as percentage of
VBAT_REG
Temperature Increasing, TREG
(REG05[1] = 1) = 110℃
Junction temperature regulation
threshold
TJUNCTION_REG
TJUNCTION_REG
110
90
°C
°C
Junction temperature regulation Temperature Increasing, TREG
threshold
(REG05[1] = 0) = 90℃
Thermal shutdown rising
temperature
TSHUT
Temperature Increasing
160
30
°C
°C
TSHUT_HYST
Thermal shutdown hysteresis
JEITA Thermistor Comparator (BUCK MODE)
T1 (0°C) threshold, charge
suspended T1 below this
temperature.
Charger suspends charge. As
Percentage to VREGN
VT1
VT1
VT2
VT2
72.4%
69%
73.3%
71.5%
68%
74.2%
74%
Falling
As Percentage to VREGN
As percentage of VREGN
As Percentage to VREGN
T2 (10°C) threshold, charge back
to ICHG/2 and 4.2 V below this
temperature
67.2%
66%
69%
Falling
66.8%
67.7%
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8.5 Electrical Characteristics (continued)
VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
43.8%
45.1%
33.7%
34.5%
TYP
44.7%
45.7%
34.2%
35.3%
MAX
45.8%
46.2%
35.1%
36.2%
UNIT
T3 (45°C) threshold, charge back
to ICHG and 4.05V above this
temperature.
Charger suspends charge. As
Percentage to VREGN
VT3
VT3
VT5
VT5
Falling
As Percentage to VREGN
As Percentage to VREGN
As Percentage to VREGN
T5 (60°C) threshold, charge
suspended above this
temperature.
Falling
COLD OR HOT THERMISTER COMPARATOR (BOOST MODE)
As Percentage to VREGN (Approx.
-20°C w/ 103AT), TJ = –20°C -
125°C
Cold temperature threshold, TS
pin voltage rising threshold
VBCOLD
VBCOLD
VBHOT
VBHOT
79.5%
78.5%
30.2%
33.8%
80%
79%
80.5%
79.5%
32.2%
34.9%
Falling
TJ = –20°C - 125°C
As Percentage to VREGN (Approx.
60°C w/ 103AT), TJ = –20°C -
125°C
Hot temperature threshold, TS
pin voltage falling threshold
31.2%
34.4%
Rising
TJ = –20°C - 125°C
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
HSFET cycle-by-cycle over-
IHSFET_OCP
5.2
6.0
8.0
A
A
current threshold
IBATFET_OCP
System over load threshold
CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
LSFET under-current falling
threshold
VLSFET_UCP
From sync mode to non-sync mode
160
mA
PWM
Oscillator frequency, buck mode
Oscillator frequency, boost mode
1320
1150
1500
1412
97%
1680
1660
kHz
kHz
fSW
PWM switching frequency
Maximum PWM duty cycle
DMAX
BOOST MODE OPERATION
VBAT = 3.8 V, I(PMID) = 0 A,
BOOSTV[1:0] = '10' = 5.15 V
VOTG_REG
Boost mode regulation voltage
4.972
-3
5.126
5.280
3
V
Boost mode regulation voltage
accuracy
VBAT = 3.8 V, I(PMID) = 0 A,
BOOSTV[1:0] = '10' = 5.15 V
VOTG_REG_ACC
%
VBAT falling, MIN_VBAT_SEL
(REG01[0]) = 0
2.6
2.9
2.8
3.0
2.9
V
V
VBAT rising, MIN_VBAT_SEL
(REG01[0]) = 0
3.15
Battery voltage exiting boost
mode
VBATLOWV_OTG
VBAT falling, MIN_VBAT_SEL
(REG01[0]) = 1
2.4
2.7
2.5
2.8
1.4
2.6
2.9
V
V
VBAT rising, MIN_VBAT_SEL
(REG01[0]) = 1
IOTG
OTG mode output current
BOOST_LIM (REG02[7]) = 1
BOOST_LIM = 0.5 A (REG02[7] = 0)
Rising threshold
1.2
0.5
1.6
0.722
6.15
A
A
Boost mode RBFET over-current
protection accuracy
IOTG_OCP_ACC
VOTG_OVP
IOTG_HSZCP
REGN LDO
OTG overvoltage threshold
5.55
5.8
V
HSFET under current falling
threshold
100
mA
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8.5 Electrical Characteristics (continued)
VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VVBUS = 9V, IREGN = 40mA
VVBUS = 5V, IREGN = 20mA
MIN
5.6
TYP
6
MAX
UNIT
V
VREGN
VREGN
REGN LDO output voltage
REGN LDO output voltage
4.6
4.7
V
LOGIC I/O PIN CHARACTERISTICS ( CE, PSEL, SCL, SDA,, INT)
VILO
VIH
Input low threshold CE
0.4
V
V
Input high threshold CE
High-level leakage current CE
Input low threshold PSEL
Input high threshold PSEL
1.3
1.3
IBIAS
VILO
VIH
Pull up rail 1.8 V
1
µA
V
0.4
V
IBIAS
High-level leakage current PSEL Pull up rail 1.8V
1
µA
LOGIC I/O PIN CHARACTERISTICS ( PG, STAT)
VOL Low-level output voltage
0.4
V
8.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VBUS/BAT POWER UP
VAC rising above ACOV threshold to
turn off Q2
tACOV
VAC OVP reaction time
200
30
ns
tBADSRC
Bad adapter detection duration
ms
BATTERY CHARGER
tTERM_DGL
Deglitch time for charge termination
250
250
ms
ms
tRECHG_DGL
Deglitch time for recharge
System over-current deglitch time to
turn off Q4
tSYSOVLD_DGL
100
1
µs
µs
Battery overvoltage deglitch time to
disable charge
tBATOVP
tSAFETY
Charge Safety Timer Range
Top-Off Timer Accuracy
CHG_TIMER = 1
8
10
30
12
36
hr
tTOP_OFF
TOP_OFF_TIMER[1:0] = 10 (30 min)
24
min
QON Timing
QON low time to turn on BATFET and
exit ship mode
tSHIPMODE
tQON_RST_2
tBATFET_RST
tSM_DLY
0.9
8
1.3
12
s
s
TJ = -10℃to 60℃
TJ = -10℃to 60℃
TJ = -10℃to 60℃
TJ = -10℃to 60℃
QON low time to reset BATFET
BATFET off time during full system
reset
250
10
400
15
ms
s
Enter ship mode delay
DIGITAL CLOCK AND WATCHDOG TIMER
tWDT
fLPDIG
fDIG
Watchdog reset time
Digital Low Power Clock
Digital Clock
REGN LDO disabled
REGN LDO disabled
REGN LDO enabled
40
30
s
18
45
kHz
kHz
kHz
500
fSCL
SCL clock frequency
400
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8.7 Typical Characteristics
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
VBUS Voltage
5 V
VBAT = 3.2 V
VBAT = 3.8 V
VBAT = 4.1 V
9 V
12 V
0
0.5
1
1.5
Charge Current (A)
2
2.5
3
0.2
0.4
0.6
0.8
OTG Current (A)
1
1.2
1.4
D001
D001
fSW = 1.5 MHz
VBAT=3.8V
VOTG = 5.15 V
图8-2. Efficiency vs. OTG Current
inductor DCR = 18 mΩ
inductor DCR = 18 mΩ
图8-1. Charge Efficiency vs. Charge Current
6
5
4
3
2
1
0
6
4
2
0
-2
-4
-6
-8
0
0.2
0.4
0.6
Output Current (A)
0.8
1
1.2
1.4
1.6
0.5 0.75
1
1.25 1.5 1.75 2
Charge Current (A)
2.25 2.5 2.75
3
D001
D001
图8-4. Charge Current Accuracy
IOTG = 1.2 A
VOTG = 5.15 V
VVBAT = 3.8 V
图8-3. OTG Output Voltage vs. Output Current
3.85
4.5
4.4
4.3
4.2
4.1
4
VBATREG = 4.208 V
VBATREG = 4.352 V
3.8
3.75
3.7
3.65
3.6
3.55
3.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
D001
D001
图8-5. SYS_MIN Voltage vs. Junction Temperature
图8-6. BATREG Charge Voltage vs. Junction Temperature
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8.7 Typical Characteristics (continued)
2.5
2
1.8
1.6
1.4
1.2
1
IINDPM = 0.5 A
IINDPM = 0.9 A
IINDPM = 1.5 A
ICHG = 0.24 A
ICHG = 0.72 A
ICHG = 1.38 A
2.25
2
1.75
1.5
1.25
1
0.8
0.6
0.4
0.2
0
0.75
0.5
0.25
0
-40
-25
-10
5
20
35
50
Junction Temperature (°C)
65
80
95
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
D001
D001
图8-7. Input Current Limit vs. Junction Temperature
图8-8. Charge Current vs. Junction Temperature
2.25
2
1.75
1.5
1.25
1
0.75
0.5
110 °C
90 °C
0.25
0
55
65
75
85
95
105
Junction Temperature (°C)
115
125
135
D001
图8-9. Charge Current vs. Junction Temperature
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9 Detailed Description
9.1 Overview
The BQ25601 is a highly integrated 3.0-A switch-mode battery charger for single cell Li-ion and Li-polymer
batteries. It includes an input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-
side switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side gate
drive.
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9.2 Functional Block Diagram
VBUS
PMID
VVBUS_UVLOZ
RBFET (Q1)
+
UVLO
SLEEP
ACOV
VVBUS
Q1 Gate
Control
œ
IIN
VBAT + VSLEEP
+
REGN
EN_REGN
EN_HIZ
VVBUS
REGN
LDO
œ
VVBUS
+
VVAC_OV
œ
BTST
FBO
VVBUS
VBUS_OVP_BOOST
+
VOTG_OVP
œ
IQ2
Q2_UCP_BOOST
Q3_OCP_BOOST
+
VOTG_HSZCP
VVBUS
œ
œ
HSFET (Q2)
LSFET (Q3)
IQ3
VINDPM
SW
+
+
VOTG_BAT
IIN
+
IINDPM
CONVERTER
Control
œ
REGN
BAT
+
œ
BATOVP
UCP
104% × V BAT_REG
IC TJ
PGND
œ
+
ILSFET_UCP
TREG
IQ2
BAT
Q2_OCP
œ
+
œ
+
œ
+
+
IHSFET_OCP
IQ3
SYS
VBAT_REG
œ
œ
œ
VSYSMIN
VBTST - VSW
ICHG
EN_HIZ
EN_CHARGE
EN_BOOST
+
+
REFRESH
VBTST_REFRESH
ICHG_REG
œ
SYS
ICHG
VBAT_REG
ICHG_REG
BATFET
(Q4)
Q4 Gate
Control
BAT
IBADSRC
IDC
BAD_SRC
+
REF
DAC
Converter
Control State
Machine
œ
IC TJ
TSHUT
+
TSHUT
œ
BAT
BAT_GD
+
VQON
VBATGD
Input
Source
Detection
œ
USB
Adapter
PSEL
INT
VREG -VRECHG
BAT
+
RECHRG
/QON
œ
ICHG
+
TERMINATION
BATLOWV
ITERM
œ
CHARGE
CONTROL
STATE
VBATLOWV
STAT /
IMON
+
BAT
MACHINE
œ
BQ25601
VSHORT
+
BATSHORT
SUSPEND
/PG
BAT
I2C
Interface
œ
Battery
Sensing
Thermistor
TS
SCL SDA /CE
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9.3 Feature Description
9.3.1 Power-On-Reset (POR)
The device powers internal bias circuits from the higher voltage of VBUS and BAT. When VBUS rises above
VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET
driver are active. I2C interface is ready for communication and all the registers are reset to default value. The
host can access all the registers after POR.
9.3.2 Device Power Up from Battery without Input Source
If only battery is present and the voltage is above depletion threshold (VBAT _DPL_RISE), the BATFET turns on and
connects battery to system. The REGN stays off to minimize the quiescent current. The low RDSON of BATFET
and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
The device always monitors the discharge current through BATFET (Supplement Mode). When the system is
overloaded or shorted (IBAT > IBATFET_OCP), the device turns off BATFET immediately and set BATFET_DIS bit to
indicate BATFET is disabled until the input source plugs in again or one of the methods described in BATFET
Enable (Exit Shipping Mode) is applied to re-enable BATFET.
9.3.3 Power Up from Input Source
When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all
the bias circuits. It detects and sets the input current limit before the buck converter is started. The power-up
sequence from input source is as listed:
1. Power up REGN LDO
2. Poor source qualification
3. Input source type detection is based on or PSEL to set default input current limit (IINDPM) register or input
source type.
4. Input voltage limit threshold setting (VINDPM threshold)
5. Converter power up
9.3.3.1 Power Up REGN Regulation
The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The REGN also
provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The
REGN is enabled when all the below conditions are valid:
• VVAC above VVAC_PRESENT
• VVAC above VBAT + VSLEEPZ in buck mode or VBUS below VBAT + VSLEEP in boost mode
• After 220-ms delay is completed
If any one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off.
The device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when
the device is in HIZ.
9.3.3.2 Poor Source Qualification
After REGN LDO powers up, the device confirms the current capability of the input source. The input source
must meet both of the following requirements in order to start the buck converter.
• VBUS voltage below VVAC_OV
• VBUS voltage above VVBUSMIN when pulling IBADSRC (typical 30 mA)
Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT
pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source
qualification every 2 seconds.
9.3.3.3 Input Source Type Detection
After the VBUS_GD bit is set and REGN LDO is powered, the device runs input source detection through the
PSEL pin. The BQ25601 sets input current limit through PSEL pins.
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After input source type detection is completed, an INT pulse is asserted to the host. in addition, the following
registers and pin are changed:
1. Input Current Limit (IINDPM) register is changed to set current limit
2. PG_STAT bit is set
3. VBUS_STAT bit is updated to indicate USB or other input source
The host can overwrite IINDPM register to change the input current limit if needed. The charger input current is
always limited by the IINDPM register.
9.3.3.3.1 PSEL Pins Sets Input Current Limit in BQ25601
The BQ25601 has PSEL pin for input current limit setting to interface with USB PHY. It directly takes the USB
PHY device output to decide whether the input is USB host or charging port. When the device operates in host-
control mode, the host needs to IINDET_EN bit to read the PSEL value and update the IINDPM register. When
the device is in default mode, PSEL value updates IINDPM in real time.
表9-1. Input Current Limit Setting from PSEL
INPUT CURRENT LIMIT
INPUT DETECTION
PSEL PIN
VBUS_STAT
(ILIM)
500 mA
2.4A
USB SDP
Adapter
High
Low
001
011
9.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
The device supports wide range of input voltage limit (3.9 V to 5.4 V) for USB. The device VINDPM is set at 4.5
V. The device supports dynamic VINDPM trackingsettings which tracks the battery voltage. This function can be
enabled via the VDPM_BAT_TRACK[1:0] register bits. When enabled, the actual input voltage limit will be the
higher of the VINDPM register and VBAT + VDPM_BAT_TRACK offset.
9.3.3.5 Converter Power Up
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft start when system rail is ramped up. When the system rail is below 2.2 V, the input
current is limited to is to the lower of 200 mA or IINDPM register setting. After the system rises above 2.2 V, the
device limits input current to the value set by IINDPM register.
As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current and temperature, simplifying output filter design.
The device switches to PFM control at light load or when battery is below minimum system voltage setting or
charging is disabled. The PFM_DIS bit can be used to prevent PFM operation in either buck or boost
configuration. PFM mode is only enabled when IINDPM is set ≥ 500 mA. When IINDPM is set ≤ 400 mA, PFM
mode is disabled.
9.3.4 Boost Mode Operation From Battery
The device supports boost converter operation to deliver power from the battery to other portable devices
through USB port. The boost mode output current rating meets the USB On-The-Go 500 mA output requirement.
The maximum output current is up to 1.2 A. The boost operation can be enabled if the conditions are valid:
1. BAT above VOTG_BAT
2. VBUS less than BAT+VSLEEP (in sleep mode)
3. Boost mode operation is enabled (OTG_CONFIG bit = 1)
4. Voltage at TS (thermistor) pin as a percentage of VREGN is within acceptable range (VBHOT < VTS < VBCOLD
5. After 30-ms delay from boost mode enable
)
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During boost mode, the status register VBUS_STAT bits is set to 111, the VBUS output is 5.15 V and the output
current can reach up to 1.2 A , selected through I2C (BOOST_LIM bit). The boost output is maintained when
BAT is above VOTG_BAT threshold.
When OTG is enabled, the device starts up with PFM and later transits to PWM to minimize the overshoot. The
PFM_DIS bit can be used to prevent PFM operation in either buck or boost configuration.
9.3.5 Host Mode and Standalone Power Management
9.3.5.1 Host Mode and Default Mode in BQ25601
The BQ25601 is a host controlled charger, but it can operate in default mode without host management. in
default mode, the device can be used as an autonomous charger with no host or while host is in sleep mode.
When the charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host mode,
WATCHDOG_FAULT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the
registers are in the default settings. During default mode, any change on PSEL pin will make real time IINDPM
register changes.
In default mode, the device keeps charging the battery with default 10-hour fast charging safety timer. At the end
of the 10-hour, the charging is stopped and the buck converter continues to operate to supply system load.
Writing a 1 to the WD_RST bit transitions the charger from default mode to host mode. All the device parameters
can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by
writing 1 to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog
timer by setting WATCHDOG bits = 00.
When the watchdog timer expires (WATCHDOG_FAULT bit = 1), the device returns to default mode and all
registers are reset to default values except IINDPM, VINDPM, BATFET_RST_EN, BATFET_DLY, and
BATFET_DIS bits.
POR
watchdog timer expired
Reset registers
I2C interface enabled
Host Mode
Start watchdog timer
Host programs registers
Y
I2C Write?
N
Default Mode
Reset watchdog timer
Reset selective registers
Y
N
WD_RST bit = 1?
N
N
Y
Y
I2C Write?
Watchdog Timer
Expired?
图9-1. Watchdog Timer Flow Chart
9.3.6 Power Path Management
The device accommodates a wide range of input sources from USB, wall adapter, to car charger. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.
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9.3.7 Battery Charging Management
The device charges 1-cell Li-Ion battery with up to 3.0-A charge current for high capacity tablet battery. The 19.5-
mΩBATFET improves charging efficiency and minimize the voltage drop during discharging.
9.3.7.1 Autonomous Charging Cycle
With battery charging enabled (CHG_CONFIG bit = 1 and CE pin is LOW), the device autonomously completes
a charging cycle without host involvement. The device default charging parameters are listed in 表 9-2. The host
can always control the charging operations and optimize the charging parameters by writing to the
corresponding registers through I2C.
表9-2. Charging Parameter Default Setting
DEFAULT MODE
Charging voltage
Charging current
Precharge current
Termination current
Temperature profile
Safety timer
BQ25601
4.208V
2.048 A
180 mA
180 mA
JEITA
10 hours
A new charge cycle starts when the following conditions are valid:
• Converter starts
• Battery charging is enabled (CHG_CONFIG bit = 1 and ICHG register is not 0 mA and CE is low)
• No thermistor fault on TS
• No safety timer fault
• BATFET is not forced to turn off (BATFET_DIS bit = 0)
The charger device automatically terminates the charging cycle when the charging current is below termination
threshold, battery voltage is above recharge threshold, and device not is in DPM mode or thermal regulation.
When a fully charged battery is discharged below recharge threshold (selectable through VRECHG bit), the
device automatically starts a new charging cycle. After the charge is done, toggle CE pin or CHG_CONFIG bit
can initiate a new charging cycle.
The STAT output indicates the charging status: charging (LOW), charging complete or charge disable (HIGH) or
charging fault (blinking). The STAT output can be disabled by setting EN_ICHG_MON bits = 11. in addition, the
status register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-
fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is
completed, an INT is asserted to notify the host.
9.3.7.2 Battery Charging Profile
The device charges the battery in five phases: battery short, preconditioning, constant current, constant voltage
and top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage
and regulates current and voltage accordingly.
表9-3. Charging Current Setting
REGISTER DEFAULT
VBAT
CHARGING CURRENT
CHRG_STAT
SETTING
100 mA
180 mA
2.048 A
< 2.2 V
2.2 V to 3 V
> 3 V
ISHORT
IPRECHG
ICHG
01
01
10
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If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will
be less than the programmed value. in this case, termination is temporarily disabled and the charging safety
timer is counted at half the clock rate.
Regulation Voltage
VREG[7:3]
Battery Voltage
Charge Current
ICHG[5:0]
Charge Current
VBATLOWV (3 V)
VSHORTZ (2.2 V)
IPRECHG[7:4]
ITERM[3:0]
ISHORT
Fast Charge and Voltage Regulation
Trickle Charge
Pre-charge
Top-off Timer
(optional)
Safety Timer
Expiration
图9-2. Battery Charging Profile
9.3.7.3 Charging Termination
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn on again to engage Supplement Mode.
When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host.
Termination is temporarily disabled when the charger device is in input current, voltage, or thermal regulation .
Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.
At low termination currents, due to the comparator offset, the actual termination current may be 10 mA-20 mA
higher than the termination target. in order to compensate for comparator offset, a programmable top-off timer
can be applied after termination is detected. The termination timer will follow safety timer constraints, such that if
safety timer is suspended, so will the termination timer. Similarly, if safety timer is doubled, so will the termination
timer. TOPOFF_ACTIVE bit reports whether the top off timer is active or not. The host can read CHRG_STAT
and TOPOFF_ACTIVE to find out the termination status.
Top off timer gets reset at one of the following conditions:
1. Charge disable to enable
2. Termination status low to high
3. REG_RST register bit is set
The top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer
value after termination will have no effect unless a recharge cycle is initiated. An INT is asserted to the host
when entering top-off timer segment as well as when top-off timer expires.
9.3.7.4 Thermistor Qualification
The charger device provides a single thermistor input for battery temperature monitor.
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9.3.7.5 JEITA Guideline Compliance During Charging Mode
To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline
emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high
temperature ranges.
To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds
the T1-T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5
range.
At cool temperature (T1-T2), JEITA recommends the charge current to be reduced to half of the charge current
or lower. At warm temperature (T3-T5), JEITA recommends charge voltage less than 4.1 V. Charge termination
is disabled for cool and warm conditions.
The charger provides flexible voltage/current settings beyond the JEITA requirement. The voltage setting at
warm temperature (T3-T5) can be VREG or 4.1V (configured by JEITA_VSET). The current setting at cool
temperature (T1-T2) can be further reduced to 20% of fast charge current (JEITA_ISET).
100
90
VBATREG
4.1V
JEITA_VSET = 1
JEITA_VSET = 0
80
70
60
JEITA_ISET= 0
JEITA_ISET= 1
50
40
30
20
10
0
0
T1
0
T2
T3
T5
55
60 65
5
10 15 20
25
30 35
40
45 50
œ5
T1
0
T2
10 15 20
T3
T5
Battery Thermistor Temperature (°C)
5
25
30 35
40
45 50
55
60 65
70
œ5
图9-4. JEITA Profile: Charging Voltage
Battery Thermistor Temperature (°C)
图9-3. JEITA Profile: Charging Current
REGN
TS
RT1
RT2
RTH
103AT
图9-5. TS Resistor Network
方程式1 through 方程式2 describe updates to the resistor bias network.
1
1
æ
ö
VREGN ´ RTHCOLD ´ RTHHOT
´
-
VT1 VT5
ç
÷
è
ø
RT2 =
V
V
æ
æ
ö
ö
REGN
REGN
RTHHOT
´
- 1 - RTHCOLD
´
ç
- 1
ç
÷
÷
VT5
VT1
è
ø
è
ø
(1)
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æ
ç
è
ö
V
æ
REGN ö
- 1
÷
÷
ç
VT1
è
ø
ø
RT1=
æ
ö
÷
1
1
æ
ö
+
ç
ç
÷
RT2
RTHCOLD ø
è
ø
è
(2)
Select 0°C to 60°C range for Li-ion or Li-polymer battery:
• RTHCOLD = 27.28 KΩ
• RTHHOT = 3.02 KΩ
• RT1 = 5.23 KΩ
• RT2 = 30.9 KΩ
9.3.7.6 Boost Mode Thermistor Monitor During Battery Discharge Mode
For battery protection during boost mode, the device monitors the battery temperature to be within the VBCOLD to
VBHOT thresholds. When temperature is outside of the temperature thresholds, the boost mode is suspended. In
additional, VBUS_STAT bits are set to 000 and NTC_FAULT is reported. Once temperature returns within
thresholds, the boost mode is recovered and NTC_FAULT is cleared.
Temperature Range to Boost
100%
Boost Disabled
V
BCOLD
(œ10°C)
Boost Enabled
Boost Disabled
V
BHOT
(65°C)
0%
图9-6. TS Pin Thermistor Sense Threshold in Boost Mode
9.3.7.7 Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The
safety timer is two hours when the battery is below VBATLOWV threshold and 10 hours when the battery is higher
than VBATLOWV threshold.
The user can program fast charge safety timer through I2C (CHG_TIMER bits). When safety timer expires, the
fault register CHRG_FAULT bits are set to 11 and an INT is asserted to the host. The safety timer feature can be
disabled through I2C by setting EN_TIMER bit.
During input voltage, current, JEITA cool or thermal regulation, the safety timer counts at half clock rate as the
actual charge current is likely to be below the register setting. For example, if the charger is in input current
regulation (IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to five hours, the
safety timer will expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.
During the fault, timer is suspended. Once the fault goes away, the timer resumes counting. If user stops the
current charging cycle, and start again, timer gets reset (toggle CE pin or CHRG_CONFIG bit).
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9.3.8 Protections
9.3.8.1 Voltage and Current Monitoring in Converter Operation
The device closely monitors the input and system voltage, as well as internal FET currents for safe buck and
boost mode operation.
9.3.8.1.1 Voltage and Current Monitoring in Buck Mode
9.3.8.1.1.1 Input Overvoltage (ACOV)
If VBUS voltage exceeds VVAC_OV (programmable via OVP[2:0] bits), the device stops switching immediately.
During input overvoltage event (ACOV), the fault register CHRG_FAULT bits are set to 01. An INT pulse is
asserted to the host. The device will automatically resume normal operation once the input voltage drops back
below the OVP threshold.
9.3.8.1.1.2 System Overvoltage Protection (SYSOVP)
The charger device clamps the system voltage during load transient so that the components connect to system
would not be damaged due to high voltage. SYSOVP threshold is 350 mV above minimum system regulation
voltage when the system is regulate at VSYS_MIN. Upon SYSOVP, converter stops switching immediately to
clamp the overshoot. The charger provides 30-mA discharge current (ISYSLOAD) to bring down the system
voltage.
9.3.8.2 Voltage and Current Monitoring in Boost Mode
The device closely monitors the VBUS voltage, as well as RBFET and LSFET current to ensure safe boost mode
operation.
9.3.8.2.1 VBUS Soft Start
When the boost function is enabled, the device soft-starts boost mode to avoid inrush current.
9.3.8.2.2 VBUS Output Protection
The device monitors boost output voltage and other conditions to provide output short circuit and overvoltage
protection. The boost build in accurate constant current regulation to allow OTG to adapt to various types of
load. If a short circuit is detected on VBUS, boost turns off and retries 7 times. If retries are not successful, OTG
is disabled with OTG_CONFIG bit cleared. In addition, the BOOST_FAULT bit is set and INT pulse is generated.
The BOOST_FAULT bit can be cleared by host by reenabling boost mode
9.3.8.2.3 Boost Mode Overvoltage Protection
When the VBUS voltage rises above regulation target and exceeds VOTG_OVP, the device enters overvoltage
protection which stops switching, clears OTG_CONFIG bit and exits boost mode. At Boost overvoltage duration,
the fault register bit (BOOST_FAULT) is set high to indicate fault in boost operation. An INT is also asserted to
the host.
9.3.8.3 Thermal Regulation and Thermal Shutdown
9.3.8.3.1 Thermal Protection in Buck Mode
The BQ25601 monitors the internal junction temperature TJ to avoid overheat of the chip and limits the IC
surface temperature in buck mode. When the internal junction temperature exceeds thermal regulation limit
(110°C), the device lowers down the charge current. During thermal regulation, the actual charging current is
usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs
at half the clock rate, and the status register THERM_STAT bit goes high.
Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface
temperature exceeds TSHUT(160°C). The fault register CHRG_FAULT is set to 1 and an INT is asserted to the
host. The BATFET and converter is enabled to recover when IC temperature is TSHUT_HYS (30°C) below
TSHUT(160°C).
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9.3.8.3.2 Thermal Protection in Boost Mode
The device monitors the internal junction temperature to provide thermal shutdown during boost mode. When IC
junction temperature exceeds TSHUT (160°C), the boost mode is disabled by setting OTG_CONFIG bit low and
BATFET is turned off. When IC junction temperature is below TSHUT(160°C) - TSHUT_HYS (30°C), the BATFET is
enabled automatically to allow system to restore and the host can re-enable OTG_CONFIG bit to recover.
9.3.8.4 Battery Protection
9.3.8.4.1 Battery Overvoltage Protection (BATOVP)
The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage
occurs, the charger device immediately disables charging. The fault register BAT_FAULT bit goes high and an
INT is asserted to the host.
9.3.8.4.2 Battery Overdischarge Protection
When battery is discharged below VBAT_DPL_FALL, the BATFET is turned off to protect battery from overdischarge.
To recover from overdischarge latch-off, an input source plug-in is required at VBUS. The battery is charged with
ISHORT (typically 100 mA) current when the VBAT < VSHORT, or precharge current as set in IPRECHG register
when the battery voltage is between VSHORTZ and VBAT_LOWV
.
9.3.8.4.3 System Overcurrent Protection
When the system is shorted or significantly overloaded (IBAT > IBATOP) and the current exceeds BATFET
overcurrent limit, the BATFET latches off. Section BATFET Enable (Exit Shipping Mode) can reset the latch-off
condition and turn on BATFET.
9.4 Device Functional Modes
9.4.1 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The
minimum system voltage is set by SYS_MIN bits. Even with a fully depleted battery, the system is regulated
above the minimum system voltage.
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),
and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage rises
above the minimum system voltage, BATFET is fully on and the voltage difference between the system and
battery is the VDS of BATFET.
When the battery charging is disabled and above minimum system voltage setting or charging is terminated, the
system is always regulated at typically 50 mV above battery voltage. The status register VSYS_STAT bit goes
high when the system is in minimum system voltage regulation.
4.4
Minimum System Voltage
SYS (Charge Disabled)
SYS (Charge Enabled)
4.3
4.2
4.1
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
2.7
2.9
3.1
3.3
3.5
BAT (V)
3.7
3.9
4.1
4.3
D002
图9-7. System Voltage vs Battery Voltage
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9.4.2 Dynamic Power Management
To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic
Power management (DPM), which continuously monitors the input current and input voltage. When input source
is over-loaded, either the current exceeds the input current limit (IINDPM) or the voltage falls below the input
voltage limit (VINDPM). The device then reduces the charge current until the input current falls below the input
current limit and the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to
drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement
mode where the BATFET turns on and battery starts discharging so that the system is supported from both the
input source and battery.
During DPM mode, the status register bits VDPM_STAT (VINDPM) or IDPM_STAT (IINDPM) goes high. 图 9-8
shows the DPM response with 9-V/1.2-A adapter, 3.2-V battery, 2.8-A charge current and 3.5-V minimum system
voltage setting.
Voltage
VBUS
9V
SYS
BAT
3.6V
3.4V
3.2V
3.18V
Current
4A
ICHG
3.2A
2.8A
ISYS
1.2A
1.0A
IIN
0.5A
-0.6A
DPM
DPM
Supplement
图9-8. DPM Response
9.4.3 Supplement Mode
When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is
regulated so that the minimum BATFET VDS stays at 30 mV when the current is low. This prevents oscillation
from entering and exiting the supplement mode.
As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until
the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge
current. 图 9-9 shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit
supplement mode when the battery is below battery depletion threshold.
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4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10 15 20 25 30 35 40 45 50 55
V(BAT-SYS) (mV)
D001
Plot1
图9-9. BAFET V-I Curve
9.4.4 Shipping Mode and QON Pin
9.4.4.1 BATFET Disable Mode (Shipping Mode)
To extend battery life and minimize power when system is powered off during system idle, shipping, or storage,
the device can turn off BATFET so that the system voltage is zero to minimize the battery leakage current. When
the host set BATFET_DIS bit, the charger can turn off BATFET immediately or delay by tSM_DLY as configured by
BATFET_DLY bit.
9.4.4.2 BATFET Enable (Exit Shipping Mode)
When the BATFET is disabled (in shipping mode) and indicated by setting BATFET_DIS, one of the following
events can enable BATFET to restore system power:
1. Plug in adapter
2. Clear BATFET_DIS bit
3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)
4. A logic high to low transition on QON pin with tSHIPMODE deglitch time to enable BATFET to exit shipping
mode
9.4.4.3 BATFET Full System Reset
The BATFET functions as a load switch between battery and system when input source is not plugged in. By
changing the state of BATFET from on to off, systems connected to SYS can be effectively forced to have a
power-on-reset. The QON pin supports push-button interface to reset system power without host by changing
the state of BATFET.
When the QON pin is driven to logic low for tQON_RST while input source is not plugged in and BATFET is
enabled (BATFET_DIS = 0), the BATFET is turned off for tBATFET_RST and then it is re-enabled to reset system
power. This function can be disabled by setting BATFET_RST_EN bit to 0.
9.4.4.4 QON Pin Operations
The QON pin incorporates two functions to control BATFET. QON is pulled up to VQON by an internal 200-kΩ
pull-up resistor.
1. BATFET Enable: A QON logic transition from high to low with longer than tSHIPMODE deglitch turns on
BATFET to exit shipping mode. When exiting shipping mode, HIZ is enabled (EN_HIZ = 1) as well. HIZ can
be disabled (EN_HIZ = 0) by the host after exiting shipping mode. OTG cannot be enabled (OTG_CONFIG =
1) until HIZ is disabled.
2. BATFET Reset: When QON is driven to logic low by at least tQON_RST while adapter is not plugged in (and
BATFET_DIS = 0), the BATFET is turned off for tBATFET_RST. The BATFET is re-enabled after tBATFET_RST
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duration. This function allows systems connected to SYS to have power-on-reset. This function can be
disabled by setting BATFET_RST_EN bit to 0.
图9-10 shows the sample external configurations for each.
QON
Press
push button
Press
push button
t
QON_RST
t
SHIPMODE
t
BATFET_RST
Q4 Status
2
Q4
off
Q4 off due to I C or
system overload
Q4 on
Q4 on
Turn on Q4 FET
when BATFET_DIS = 1 or SLEEPZ = 1
Reset Q4 FET
When BATFET_DIS = 0 and SLEEPZ = 0
图9-10. QON Timing
SYS
Q4
Control
BAT
VPULL-UP
+
QON
图9-11. QON Circuit
9.4.5 Status Outputs ( PG, STAT, INT)
9.4.5.1 Power Good Indicator ( PG Pin and PG_STAT Bit)
The PG_STAT bit goes HIGH and PG pin goes LOW to indicate a good input source when:
• VBUS above VVBUS_UVLO
• VBUS above battery (not in sleep)
• VBUS below VVAC_OV threshold
• VBUS above VVBUSMin (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
• Completed input Source Type Detection
9.4.5.2 Charging Status Indicator (STAT)
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED. The STAT pin
function can be disabled by setting the EN_ICHG_MON bits = 11.
表9-4. STAT Pin State
CHARGING STATE
STAT INDICATOR
LOW
Charging in progress (including recharge)
Charging complete
HIGH
Sleep mode, charge disable
HIGH
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表9-4. STAT Pin State (continued)
CHARGING STATE
STAT INDICATOR
Charge suspend (input overvoltage, TS fault, timer fault or system overvoltage)
Boost Mode suspend (due to TS fault)
Blinking at 1 Hz
9.4.5.3 Interrupt to Host ( INT)
In some applications, the host does not always monitor the charger operation. The INT pulse notifies the system
on the device operation. The following events will generate 256-μs INT pulse.
• USB/adapter source identified (through PSEL pin )
• Good input source detected
– VBUS above battery (not in sleep)
– VBUS below VVAC_OV threshold
– VBUS above VVBUSMin (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
• Input removed
• Charge complete
• Any FAULT event in REG09
• VINDPM / IINDPM event detected (maskable)
When a fault occurs, the charger device sends out INT and keeps the fault state in REG09 until the host reads
the fault register. Before the host reads REG09 and all the faults are cleared, the charger device would not send
any INT upon new faults. To read the current fault status, the host has to read REG09 two times consecutively.
The first read reports the pre-existing fault register status and the second read reports the current fault register
status.
9.5 Programming
9.5.1 Serial Interface
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2C is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP
Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices
can be considered as hosts or targets when performing data transfers. A host is the device which initiates a data
transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is
considered a target.
The device operates as a target device with address 6BH, receiving control inputs from the host device like a
microcontroller or a digital signal processor through REG00-REG0B. A register read beyond REG0B (0x0B)
returns 0xFF. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits),
connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines
are HIGH. The SDA and SCL pins are open drain.
9.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
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SDA
SCL
Data line stable;
Data valid
Change of data
allowed
图9-12. Bit Transfer on the I2C Bus
9.5.1.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the host. The
bus is considered busy after the START condition, and free after the STOP condition.
SDA
SCL
SDA
SCL
START (S)
STOP (P)
图9-13. TS START and STOP conditions
9.5.1.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a target cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the host into a wait state (clock stretching). Data
transfer then continues when the target is ready for another byte of data and release the clock line SCL.
Acknowledgement
Acknowledgement
signal from host
signal from target
MSB
SDA
1
2
7
8
9
1
2
8
9
SCL S or Sr
START or
P or Sr
ACK
ACK
STOP or
Repeate
d START
Repeated
START
图9-14. Data Transfer on the I2C Bus
9.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge ninth clock pulse, are generated by the host. The transmitter releases the SDA line during the
acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH
period of this clock pulse.
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When SDA remains HIGH during the ninth clock pulse, this is the Not Acknowledge signal. The host can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
9.5.1.5 Target Address and Data Direction Bit
After the START, a target address is sent. This address is 7 bits long followed by the eighth bit as a data
direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
SDA
1 - 7
8
9
1-7
8
9
1-7
8
9
S
P
SCL
START
ADDRESS
R / W
ACK
DATA
ACK
DATA
ACK
STOP
图9-15. Complete Data Transfer
9.5.1.6 Single Read and Write
If the register address is not defined, the charger IC send back NACK and go back to the idle state.
S
Target Addr
0
ACK
Reg Addr
ACK
Data to Addr
ACK
P
图9-16. Single Write
S
Target Addr
0
ACK
Reg Addr
ACK
S
Target Addr
ACK
1
Data
NCK
P
图9-17. Single Read
9.5.1.7 Multi-Read and Multi-Write
The charger device supports multi-read and multi-write on REG00 through REG0B.
S
Target Addr
0
ACK
Reg Addr
ACK
Data to Addr
ACK
Data to Addr+1 ACK
Data to Addr+N
ACK
P
图9-18. Multi-Write
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S
Target Addr
0
ACK
ACK
S
Target Addr
ACK
Reg Addr
1
Data @ Addr
ACK Data @ Addr+1 ACK
Data @ Addr+N NCK
P
图9-19. Multi-Read
REG09 is a fault register. It keeps all the fault information from last read until the host issues a new read. For
example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the
fault when it is read the first time, but returns to normal when it is read the second time. in order to get the fault
information at present, the host has to read REG09 for the second time. The only exception is NTC_FAULT
which always reports the actual condition on the TS pin. in addition, REG09 does not support multi-read and
multi-write.
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9.6 Register Maps
I2C Target Address: 6BH
9.6.1 REG00
表9-5. REG00 Field Descriptions
Bit Field
POR Type Reset
Description
Comment
7
Enable HIZ Mode
0 –Disable (default)
1 –Enable
by REG_RST
by Watchdog
EN_HIZ
0
0
R/W
0 –Disable, 1 –Enable
6
5
EN_ICHG_MON[1]
EN_ICHG_MON[0]
R/W by REG_RST
R/W
00 –Enable STAT pin function
(default)
01 –Reserved
11 –Disable STAT pin function
(float pin)
0
by REG_RST
4
3
2
1
IINDPM[4]
IINDPM[3]
IINDPM[2]
IINDPM[1]
1
0
1
1
R/W by REG_RST 1600 mA
R/W by REG_RST 800 mA
R/W by REG_RST 400 mA
R/W by REG_RST 200 mA
Input Current Limit
Offset: 100 mA
Range: 100 mA (000000) –3.2 A
(11111)
Default: 2400 mA (10111),
maximum input current limit, not
typical.
IINDPM bits are changed
automatically after input source
detection is completed
PSEL = Hi = 500 mA
0
IINDPM[0]
1
R/W by REG_RST 100 mA
PSEL = Lo = 2.4 A
Host can over-write IINDPM
register bits after input source
detection is completed.
LEGEND: R/W = Read/Write; R = Read only
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9.6.2 REG01
表9-6. REG01 Field Descriptions
Bit Field
POR Type Reset
Description
Comment
R/W
R/W
R/W
0 –Enable PFM
1 –Disable PFM
7
6
PFM _DIS
WD_RST
0
0
by REG_RST
Default: 0 - Enable
by REG_RST I2C Watchdog Timer Reset 0 –
by Watchdog
Default: Normal (0) Back to 0 after
watchdog timer reset
Normal ; 1 –Reset
Default: OTG disable (0)
Note:
1. OTG_CONFIG would over-ride
Charge Enable Function in
CHG_CONFIG
by REG_RST 0 –OTG Disable
by Watchdog
5
4
OTG_CONFIG
CHG_CONFIG
0
1
1 –OTG Enable
R/W
Default: Charge Battery (1)
Note:
1. Charge is enabled when both
CE pin is pulled low AND
CHG_CONFIG bit is 1.
by REG_RST 0 –Charge Disable
by Watchdog
1 –Charge Enable
3
2
SYS_MIN[2]
SYS_MIN[1]
1
0
R/W by REG_RST
R/W by REG_RST
R/W
000: 2.6 V
001: 2.8 V
010: 3 V
011: 3.2 V
100: 3.4 V
101: 3.5 V
110: 3.6 V
111: 3.7 V
System Minimum Voltage
1
0
SYS_MIN[0]
1
0
by REG_RST
Default: 3.5 V (101)
R/W
Minimum battery voltage for OTG
mode. Default falling 2.8 V (0);
Rising threshold 3.0 V (0)
0 –2.8 V BAT falling,
1 –2.5 V BAT falling
MIN_VBAT_SEL
by REG_RST
LEGEND: R/W = Read/Write; R = Read only
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9.6.3 REG02
表9-7. REG02 Field Descriptions
Bit Field
POR Type Reset
Description
Comment
R/W by REG_RST
by Watchdog 0 –0.5 A
1 –1.2 A
Default: 1.2 A (1)
Note:
The current limit options listed are
minimum current limit specs.
7
BOOST_LIM
1
R/W by REG_RST
0 –Use higher Q1 RDSON when
programmed IINDPM < 700mA
(better accuracy)
In boost mode, full FET is always
used and this bit has no effect
6
Q1_FULLON
0
1 –Use lower Q1 RDSON always
(better efficiency)
R/W by REG_RST
by Watchdog
5
4
3
2
1
0
ICHG[5]
ICHG[4]
ICHG[3]
ICHG[2]
ICHG[1]
ICHG[0]
1
0
0
0
1
0
1920 mA
960 mA
480 mA
240 mA
120 mA
60 mA
R/W by REG_RST
by Watchdog
Fast Charge Current
Default: 2040 mA (100010)
Range: 0 mA (0000000) –3000
mA (110010)
by REG_RST
R/W
by Watchdog
Note:
R/W by REG_RST
by Watchdog
ICHG = 0 mA disables charge.
ICHG > 3000 mA (110010 clamped
to register value 3000 mA
(110010))
R/W by REG_RST
by Watchdog
R/W by REG_RST
by Watchdog
LEGEND: R/W = Read/Write; R = Read only
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9.6.4 REG03
表9-8. REG03 Field Descriptions
Bit Field
POR Type Reset
Description
Comment
7
6
5
4
3
2
1
0
IPRECHG[3]
0
0
1
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
by REG_RST
by Watchdog
480 mA
Precharge Current
Default: 180 mA (0010)
Offset: 60 mA
Note: IPRECHG > 780 mA
clamped to 780 mA (1100)
IPRECHG[2]
IPRECHG[1]
IPRECHG[0]
ITERM[3]
by REG_RST
by Watchdog
240 mA
120 mA
60 mA
by REG_RST
by Watchdog
by REG_RST
by Watchdog
by REG_RST
by Watchdog
480 mA
240 mA
120 mA
60 mA
ITERM[2]
by REG_RST
by Watchdog
Termination Current
Default: 180 mA (0010)
Offset: 60 mA
ITERM[1]
by REG_RST
by Watchdog
ITERM[0]
by REG_RST
by Watchdog
LEGEND: R/W = Read/Write; R = Read only
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9.6.5 REG04
表9-9. REG04 Field Descriptions
Description
Bit Field
POR Type Reset
Comment
by REG_RST
by Watchdog
7
6
5
4
3
2
1
0
VREG[4]
0
1
0
1
1
0
0
0
R/W
512 mV
256 mV
128 mV
64 mV
Charge Voltage
Offset: 3.856 V
by REG_RST
by Watchdog
VREG[3]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Range: 3.856 V to 4.624 V (11000)
Default: 4.208 V (01011)
Special Value:
by REG_RST
by Watchdog
VREG[2]
(01111): 4.352 V
by REG_RST
by Watchdog
VREG[1]
Note: Value above 11000 (4.624 V)
is clamped to register value 11000
(4.624 V)
by REG_RST
by Watchdog
VREG[0]
32 mV
by REG_RST
by Watchdog
00 –Disabled (Default)
01 –15 minutes
10 –30 minutes
The extended time following the
termination condition is met. When
disabled, charge terminated when
termination conditions are met
TOPOFF_TIMER[1]
TOPOFF_TIMER[0]
VRECHG
by REG_RST
by Watchdog
11 –45 minutes
by REG_RST
by Watchdog
0 –100 mV
1 –200 mV
Recharge threshold
Default: 100 mV (0)
LEGEND: R/W = Read/Write; R = Read only
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9.6.6 REG05
表9-10. REG05 Field Descriptions
Bit Field
POR Type Reset
Description
Comment
by REG_RST 0 –Disable
7
6
5
4
EN_TERM
1
0
0
1
R/W
R/W
R/W
R/W
Default: Enable termination (1)
by Watchdog
1 –Enable
by REG_RST
by Watchdog
Reserved
Reserved
Reserved
by REG_RST
by Watchdog
WATCHDOG[1]
WATCHDOG[0]
00 –Disable timer, 01 –40 s, 10
–80 s,11 –160 s
Default: 40 s (01)
by REG_RST
by Watchdog
0 –Disable
1 –Enable both fast charge and
precharge timer
by REG_RST
by Watchdog
3
2
1
0
EN_TIMER
CHG_TIMER
TREG
1
1
1
1
R/W
R/W
R/W
R/W
Default: Enable (1)
Default: 10 hours (1)
Default: 110°C (1)
Default: 20% (1)
by REG_RST 0 –5 hrs
by Watchdog
1 –10 hrs
Thermal Regulation Threshold:
0 –90°C
1 –110°C
by REG_RST
by Watchdog
JEITA_ISET
(0C-10C)
by REG_RST 0 –50% of ICHG
by Watchdog
1 –20% of ICHG
LEGEND: R/W = Read/Write; R = Read only
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9.6.7 REG06
表9-11. REG06 Field Descriptions
Description
Bit Field
POR Type Reset
Comment
7
6
5
4
OVP[1]
0
1
1
0
R/W by REG_RST
VAC OVP threshold:
00 - 5.5 V
01 –6.5 V (5-V input)
10 –10.5 V (9-V input)
11 –14 V (12-V input)
Default: 6.5 V (01)
OVP[0]
R/W by REG_RST
BOOSTV[1]
BOOSTV[0]
R/W by REG_RST
R/W by REG_RST
Boost Regulation Voltage:
00 –4.85 V
01 –5.00 V
10 –5.15 V
11 –5.30 V
3
2
1
0
VINDPM[3]
VINDPM[2]
VINDPM[1]
VINDPM[0]
0
1
1
0
R/W by REG_RST 800 mV
R/W by REG_RST 400 mV
R/W by REG_RST 200 mV
R/W by REG_RST 100 mV
Absolute VINDPM Threshold
Offset: 3.9 V
Range: 3.9 V (0000) –5.4 V
(1111)
Default: 4.5 V (0110)
LEGEND: R/W = Read/Write; R = Read only
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9.6.8 REG07
表9-12. REG07 Field Descriptions
Bit Field
POR Type Reset
Description
Comment
0 –Not in input current limit
by REG_RST detection
Returns to 0 after input detection is
complete
7
6
IINDET_EN
0
1
R/W
R/W
by Watchdog
1 –Force input current limit
detection when VBUS is present
0 –Disable
by REG_RST
by Watchdog
1 –Safety timer slowed by 2X
during input DPM (both V and I) or
JEITA cool, or thermal regulation
TMR2X_EN
0 –Allow Q4 turn on, 1 –Turn off
Q4 with tBATFET_DLY delay time
(REG07[3])
5
4
BATFET_DIS
0
0
R/W by REG_RST
Default: Allow Q4 turn on(0)
0 –Set Charge Voltage to 4.1V
( max),
1 –Set Charge Voltage to VREG
JEITA_VSET
(45C-60C)
by REG_RST
R/W
by Watchdog
0 –Turn off BATFET immediately
when BATFET_DIS bit is set
1 –Turn off BATFET after
tBATFET_DLY (typ. 10 s) when
BATFET_DIS bit is set
Default: 1
Turn off BATFET after tBATFET_DLY
(typ. 10 s) when BATFET_DIS bit
is set
3
BATFET_DLY
1
R/W by REG_RST
by REG_RST 0 –Disable BATFET reset function Default: 1
2
1
BATFET_RST_EN
1
0
R/W
by Watchdog
Enable BATFET reset function
1 –Enable BATFET reset function
VDPM_BAT_TRACK[1]
R/W by REG_RST
R/W by REG_RST
00 –Disable function (VINDPM
set by register)
01 –VBAT + 200 mV
10 –VBAT + 250 mV
11 –VBAT + 300 mV
Sets VINDPM to track BAT voltage.
Actual VINDPM is higher of
register value and VBAT +
VDPM_BAT_TRACK
0
VDPM_BAT_TRACK[0]
0
LEGEND: R/W = Read/Write; R = Read only
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9.6.9 REG08
表9-13. REG08 Field Descriptions
Bit Field
POR Type
Reset
Description
7
6
VBUS_STAT[2]
x
x
R
R
NA
VBUS Status register
000 –No input
001 –USB Host SDP (500 mA) →PSEL HIGH
011 –Adapter 2.4 A →PSEL LOW
111 –OTG
VBUS_STAT[1]
VBUS_STAT[0]
CHRG_STAT[1]
NA
5
4
x
x
R
R
NA
NA
Software current limit is reported in IINDPM register
Charging status:
00 –Not Charging
01 –Pre-charge (< VBATLOWV
10 –Fast Charging
11 –Charge Termination
)
3
2
CHRG_STAT[0]
PG_STAT
x
x
R
R
NA
NA
Power Good status:
0 –Power Not Good
1 –Power Good
0 –Not in thermal regulation
1 –In thermal regulation
1
0
THERM_STAT
VSYS_STAT
x
x
R
R
NA
NA
0 –Not in VSYS_MIN regulation (BAT > VSYS_MIN
1 –In VSYS_MIN regulation (BAT < VSYS_MIN
)
)
LEGEND: R/W = Read/Write
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9.6.10 REG09
表9-14. REG09 Field Descriptions
Bit Field
POR Type Reset
Description
7
6
WATCHDOG_FAULT
x
x
R
R
NA
NA
0 –Normal, 1- Watchdog timer expiration
0 –Normal, 1 –VBUS overloaded in OTG, or VBUS OVP, or battery is
too low (any conditions that cannot start boost function)
BOOST_FAULT
5
4
3
2
1
CHRG_FAULT[1]
CHRG_FAULT[0]
BAT_FAULT
x
x
x
x
x
R
R
R
R
R
NA
NA
NA
NA
NA
00 –Normal, 01 –input fault (VAC OVP or VBAT < VBUS < 3.8 V), 10
- Thermal shutdown, 11 –Charge Safety Timer Expiration
0 –Normal, 1 –BATOVP
NTC_FAULT[2]
NTC_FAULT[1]
JEITA
000 –Normal, 010 –Warm, 011 –Cool, 101 –Cold, 110 –Hot
(Buck mode)
0
NTC_FAULT[0]
x
R
NA
000 –Normal, 101 –Cold, 110 –Hot (Boost mode)
LEGEND: R/W = Read/Write; R = Read only
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9.6.11 REG0A
表9-15. REG0A Field Descriptions
Bit Field
POR Type Reset
Description
0 –Not VBUS attached,
1 –VBUS Attached
7
VBUS_GD
x
R
NA
6
5
4
VINDPM_STAT
IINDPM_STAT
Reserved
x
x
x
R
R
R
NA
NA
NA
0 –Not in VINDPM, 1 –in VINDPM
0 –Not in IINDPM, 1 –in IINDPM
0 –Top off timer not counting.
1 –Top off timer counting
3
2
1
0
TOPOFF_ACTIVE
ACOV_STAT
x
x
0
0
R
R
NA
NA
0 –Device is NOT in ACOV
1 –Device is in ACOV
0 –Allow VINDPM INT pulse
1 –Mask VINDPM INT pulse
VINDPM_INT_ MASK
IINDPM_INT_ MASK
R/W by REG_RST
R/W by REG_RST
0 –Allow IINDPM INT pulse
1 –Mask IINDPM INT pulse
LEGEND: R/W = Read/Write; R = Read only
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9.6.12 REG0B
表9-16. REG0B Field Descriptions
Bit Field
POR Type Reset
Description
Register reset
0 –Keep current register setting
1 –Reset to default register value and reset safety timer
Note: Bit resets to 0 after register reset is completed
7
REG_RST
0
R/W NA
6
5
4
3
2
1
0
PN[3]
x
x
x
x
x
x
x
R
R
R
R
R
R
R
NA
NA
NA
NA
NA
NA
NA
PN[2]
BQ25601 : 0010
PN[1]
PN[0]
Reserved
DEV_REV[1]
DEV_REV[0]
LEGEND: R/W = Read/Write; R = Read only
10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
A typical application consists of the device configured as an I2C controlled power path management device and
a single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of Smartphone and other
portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2),
low-side switching FET (LSFET, Q3), and battery FET (BATFET Q4) between the system and battery. The
device also integrates a bootstrap diode for the high-side gate drive.
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10.2 Typical Application
SYSTEM
3.5V œ 4.6V
VAC
1 ꢀH
SW
3.9 V œ 13.5 V
VBUS
10 ꢀF
47 nF
1 ꢀF
BTST
PMID
REGN
10 ꢀF
4.7 µF
GND
SYS
Opt.
SYS
SYS
2.2 kꢁ
2.2 kꢁ
PG
BAT
BQ25601
STAT
VREF
10 ꢀF
3 x 10 kꢁ
REGN
5.23 kꢁ
SDA
SCL
INT
CE
TS
Host
+
30.1 kꢁ 10 kꢁ
QON
PSEL
PHY
Optional
图10-1. Power Path Management Application
10.2.1 Design Requirements
表10-1. Design Parameters
PARAMETER
VVBUS voltage range
VALUE
4 V to 13.5 V
2.4 A
Input current limit (REG00[4:0])
Fast charge current limit (REG02[5:0])
Minimum system voltage (REG01[3:1])
Battery regulation voltage (REG04[7:3])
2.04 A
3.5 V
4.2 V
10.2.2 Detailed Design Procedure
10.2.2.1 Inductor Selection
The 1.5-MHz switching frequency allows the use of small inductor and capacitor values to maintain an inductor
saturation current higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
I
SAT ≥ICHG + (1/2) IRIPPLE
(3)
The inductor ripple current depends on the input voltage (VVBUS), the duty cycle (D = VBAT/VVBUS), the switching
frequency (fS) and the inductance (L).
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VIN ´D ´ (1- D)
=
IRIPPLE
fs ´ L
(4)
The maximum inductor ripple current occurs when the duty cycle (D) is 0.5 or approximately 0.5. Usually
inductor ripple is designed in the range between 20% and 40% maximum charging current as a trade-off
between inductor size and efficiency for a practical design.
10.2.2.2 Input Capacitor
Design input capacitance to provide enough ripple current rating to absorb input switching ripple current. The
worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst case capacitor RMS current ICin occurs where the duty cycle is closest
to 50% and can be estimated using 方程式5.
ICIN = ICHG ´ D ´ (1- D)
(5)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. A rating of 25 V or higher capacitor is
preferred for 15-V input voltage. Capacitance of 22 μF is suggested for typical of 3-A charging current.
10.2.2.3 Output Capacitor
Ensure that the output capacitance has enough ripple current rating to absorb the output switching ripple current.
方程式6 shows the output capacitor RMS current ICOUT calculation.
IRIPPLE
ICOUT
=
» 0.29 ´ IRIPPLE
2 ´
3
(6)
The output capacitor voltage ripple can be calculated as follows:
æ
ç
è
ö
VOUT
8LCfs2
VOUT
V
DVO =
1-
÷
IN ø
(7)
At certain input and output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The charger device has internal loop compensation optimized for ≤20-μF ceramic output capacitance. The
preferred ceramic capacitor is 10-V rating, X7R or X5R.
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10.2.3 Application Curves
VVBUS = 5 V
VVBAT = 3.2 V
VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.2 V
图10-2. Power-Up with Charge Disabled
图10-3. Power-Up with Charge Enabled
VVBUS = 5 V
VVBUS = 9 V
ISYS = 50 mA
Charge Disabled
ISYS = 50 mA
Charge Disabled
图10-4. PFM Switching in Buck Mode
图10-5. PFM Switching in Buck Mode
VVBUS = 12 V
ISYS = 50 mA
VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.8 V
Charge Disabled
图10-6. PFM Switching in Buck Mode
图10-7. PWM Switching in Buck Mode
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VVBUS = 12 V
ICHG = 2 A
VVBAT = 3.8 V
VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.2 V
图10-8. PWM Switching in Buck mode
图10-9. Charge Enable
VVBUS = 5 V
VVBAT = 3.2 V
VVBAT = 4 V
ICHG = 2 A
ILOAD= 50 mA
PFM Enabled
图10-10. Charge Disable
图10-11. OTG Switching
VVBAT = 4 V
ILOAD= 1 A
VVBAT = 4 V
ILOAD= 0 A
PFM Enabled
PFM Disabled
图10-12. OTG Switching
图10-13. OTG Switching
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VVBUS = 5 V
IINDPM = 1 A
ICHG = 1 A
VVBUS = 5 V
IINDPM = 2 A
ICHG = 1 A
ISYS from 0 A to 2 A
VBAT = 3.7 V
ISYS from 0 A to 4 A
VBAT = 3.7 V
图10-14. System Load Transient
图10-15. System Load Transient
VVBUS = 5 V
IINDPM = 1 A
ICHG = 2 A
VVBUS = 5 V
IINDPM = 1 A
ICHG = 2 A
ISYS from 0 A to 2 A
VBAT = 3.7 V
ISYS from 0 A to 4 A
VBAT = 3.7 V
图10-16. System Load Transient
图10-17. System Load Transient
VVBUS = 5 V
IINDPM = 2 A
ICHG = 2 A
VVBUS = 5 V
IINDPM = 2 A
ICHG = 2 A
ISYS from 0 A to 2 A
VBAT = 3.7 V
ISYS from 0 A to 4 A
VBAT = 3.7 V
图10-18. System Load Transient
图10-19. System Load Transient
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VBAT = 3.8 V
CLOAD = 470 µF
Adaptor ILIM = 1 A
图10-20. OTG Start-Up
图10-21. VINDPM Tracking Battery Voltage
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11 Power Supply Recommendations
In order to provide an output voltage on SYS, the BQ25601 device requires a power supply between 3.9-V and
13.5-V input with at least 100-mA current rating connected to VBUS and a single-cell Li-Ion battery with voltage
> VBATUVLO connected to BAT. The source current rating needs to be at least 3 A in order for the buck converter
of the charger to provide maximum output power to SYS.
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12 Layout
12.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see 图 12-1) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the
proper layout.
1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper
trace connection or GND plane.
2. Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
3. Put output capacitor near to the inductor and the device. Ground connections need to be tied to the IC
ground with a short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using thermal pad as the single ground
connection point. Or using a 0-Ωresistor to tie analog ground to power ground.
5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the
device. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
6. Place decoupling capacitors next to the IC pins and make trace connection as short as possible.
7. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on
the other layers.
8. Ensure that the number and sizes of vias allow enough copper for a given current path.
Refer to the BQ25601 and BQ25601D (PWR877) Evaluation Module User's Guide for the recommended
component placement with trace and via locations. For the VQFN information, refer to the Quad Flatpack No-
Lead Logic Packages Application Report and QFN and SON PCB Attachment Application Report.
12.2 Layout Example
+
+
œ
图12-1. High Frequency Current Path
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图12-2. Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• BQ25601 and BQ25601D (PWR877) Evaluation Module User's Guide
13.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25601RTWR
BQ25601RTWT
ACTIVE
ACTIVE
WQFN
WQFN
RTW
RTW
24
24
3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
-40 to 85
-40 to 85
BQ25601
BQ25601
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25601RTWR
BQ25601RTWT
WQFN
WQFN
RTW
RTW
24
24
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ25601RTWR
BQ25601RTWT
WQFN
WQFN
RTW
RTW
24
24
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTW 24
4 x 4, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
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