BQ25121AYFPR [TI]
具有电源路径、集成 LDO 和降压转换器 2.5V 默认输出的 300mA 线性电池充电器 | YFP | 25 | -40 to 85;型号: | BQ25121AYFPR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有电源路径、集成 LDO 和降压转换器 2.5V 默认输出的 300mA 线性电池充电器 | YFP | 25 | -40 to 85 电池 转换器 |
文件: | 总75页 (文件大小:2903K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
BQ25121A
ZHCSI47A –APRIL 2018 –REVISED JANUARY 2021
BQ25121A 适用于可穿戴设备和物联网的低IQ 高度集成式电池充电管理解决方
案
1 特性
2 应用
• 可延长两次充电之间的系统运行时间
– 可配置300mA 降压稳压器
(默认电压2.5V)
• 智能手表和其他可穿戴设备
• 健身附件
• 健康监控医疗附件
• 可充电玩具
– 700nA(典型值) Iq,已启用降压转换器(空
载)
– 可配置负载开关或100mA LDO 输出(默认启用
负载开关)
– 充电电流高达300mA,可实现快速充电。
– 电池稳压精度为0.5%(可配置电压范围为3.6V
至4.65V,阶跃为10mV)
3 说明
BQ25121A 是一款高度集成的电池充电管理 IC,集成
了可穿戴设备的常用功能:线性充电器、稳压输出、负
载开关、带计时器的手动复位以及电池电压监视器。该
集成降压转换器是一款具有低 IQ 的高效率开关,采用
DCS-Control™ 技术,可进一步提高轻负载效率,负载
电流可低至 10µA。运行和关断期间的低静态电流有助
于延长电池寿命。该器件支持 5mA 至 300mA 的充电
电流。
– 可配置的终端电流低至
500µA
– 基于电压的简单电池监控器
– 看门狗计时器已禁用
• 高度集成的小尺寸解决方案
器件信息
封装(1)
– 采用2.5mm x 2.5mm WCSP 封装和六个外部元
件,可更大程度地减小解决方案尺寸
– 通过可调节计时器实现按钮唤醒和复位
– 电源路径管理,用于系统供电和电池充电
– 电源路径管理功能可实现低于50nA 的运输模式
电池静态电流,从而更大限度延长货架期
– 电池充电器在3.4V –5.5VIN(5.5V OVP/20V
容差)范围内正常工作
封装尺寸(标称值)
器件型号
BQ25121A
DSBGA (25)
2.50mm x 2.50mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
PG
PMID
Unregulated
Load
– 用于输入电流限制、充电电流、终止电流和状态
IN
输出的专用引脚
• I2C 通信控制
VINLS
BQ25121A
GND
SYS
SW
– 充电电压和电流
– 终止阈值
MCU /
SYSTEM
CD
– 输入电流限制
– VINDPM 阈值
– 计时器选项
HOST
SDA
SCL
INT
LS / LDO
<100mA
Load
RESET
– 负载开关控制
– 系统输出电压调节
– LDO 输出电压调节
• 安全相关认证:
LSCTRL
BAT
MR
IPRETERM
ISET
TS
IN
NTC
ILIM
– TUV IEC 62368-1 认证
简化原理图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLUSDA7
BQ25121A
ZHCSI47A –APRIL 2018 –REVISED JANUARY 2021
www.ti.com.cn
Table of Contents
9.4 Device Functional Modes..........................................31
9.5 Programming............................................................ 33
9.6 Register Maps...........................................................36
10 Application and Implementation................................50
10.1 Application Information........................................... 50
10.2 Typical Application.................................................. 50
11 Power Supply Recommendations..............................65
12 Layout...........................................................................66
12.1 Layout Guidelines................................................... 66
12.2 Layout Example...................................................... 66
13 Device and Documentation Support..........................67
13.1 Device Support....................................................... 67
13.2 接收文档更新通知................................................... 67
13.3 Trademarks.............................................................67
13.4 支持资源..................................................................67
13.5 静电放电警告.......................................................... 67
13.6 术语表..................................................................... 67
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings........................................ 6
8.2 ESD Ratings............................................................... 6
8.3 Recommended Operating Conditions.........................6
8.4 Thermal Information....................................................7
8.5 Electrical Characteristics.............................................8
8.6 Timing Requirements................................................12
8.7 Typical Characteristics..............................................15
9 Detailed Description......................................................17
9.1 Overview...................................................................17
9.2 Functional Block Diagram.........................................17
9.3 Feature Description...................................................18
Information.................................................................... 67
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (April 2018) to Revision A (January 2021)
Page
• 向特性中添加了安全相关认证.............................................................................................................................1
• Added Device Comparison Table....................................................................................................................... 3
• Changed Storage Temperature.......................................................................................................................... 6
• Changed VD(PPM) to V(DPPM) .............................................................................................................................. 8
• Changed RDS(ON_LDO) ........................................................................................................................................8
• Changed 图8-2 ............................................................................................................................................... 12
• Deleted Update STAT to fault in VIN_UV actions in Fault and Status Condition Responses...........................31
• Changed VIN_UV description...........................................................................................................................37
• Deleted I2C Address from title.......................................................................................................................... 40
• Changed reset state from 0100 1010 to 0100 0010......................................................................................... 49
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDA7
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5 Description (continued)
The battery is charged using a standard Li-Ion charge profile with three phases: precharge, constant current and
constant voltage. A voltage-based JEITA compatible battery pack thermistor monitoring input (TS) is included
that monitors battery temperature and automatically changes charge parameters to prevent the battery from
charging outside of its safe temperature range. The charger is optimized for 5-V USB input, with 20-V tolerance
to withstand line transients. The buck converter is run from the input or battery. When in battery only mode, the
device can run from a battery up to 4.65 V.
A configurable load switch allows system optimization by disconnecting infrequently used devices. The manual
reset with timer allows multiple different configuration options for wake are reset optimization. A simple voltage
based monitor provides battery level information to the host in 2% increments from 60% to 100% of the
programmed V(BATREG)
.
6 Device Comparison Table
DEFAULT
CHARGE
CURRENT
DEFAULT
TERMINATION
CURRENT
PART
NUMBER
DEFAULT
VINDPM
DEFAULT
SYS OUTPUT LDO OUTPUT
DEFAULT
DEFAULT
VBATREG
VDPPM
WATCHDOG
BQ25120A
BQ25121A
BQ25122
BQ25125
Enabled
Enabled
Enabled
Disabled
1.8 V
2.5 V
1.2 V
1.8 V
Load Switch
Load Switch
Load Switch
1.8 V (LDO)
4.2 V
4.2 V
4.2 V
4.2 V
10 mA
10 mA
11 mA
10 mA
2 mA
2 mA
Enabled
Enabled
Enabled
Disabled
Enabled
Disabled
Enabled
Enabled
0.5 mA
2 mA
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English Data Sheet: SLUSDA7
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7 Pin Configuration and Functions
1
2
3
4
5
A
GND
IN
PMID
SW
VINLS
VINLS
PG
PGND
B
PMID
SYS
BAT
BAT
ILIM
INT
CD
C
LS/LDO
ISET
TS
IPRETE
D
RM
GND
RESET
E
MR
LSCTRL
SDA
SCL
图7-1. YFP Package 25-Pin DSBGA Top View
表7-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with
at least 1 µF of capacitance using a ceramic capacitor.
IN
A2
I
High Side Bypass Connection. Connect at least 3µF of ceramic capacitance with DC bias
derating from PMID to GND as close to the PMID and GND pins as possible. When entering
Ship Mode, PMID is discharged by a 20-kΩ internal discharge resistor.
PMID
A3, B3
I/O
GND
A1, D5
A5
Ground connection. Connect to the ground plane of the circuit.
Power ground connection. Connect to the ground plane of the circuit. Connect the output
filter cap from the buck converter to this ground as shown in the layout example.
PGND
Chip Disable. Drive CD low to place the part in High-Z mode with battery only present, or
enable charging when VIN is valid. Drive CD high for Active Battery mode when battery only
is present, and disable charge when VIN is present. CD is pulled low internally with 900 kΩ.
CD
E2
I
I2C Interface Data. Connect SDA to the logic rail through a 10-kΩresistor.
I2C Interface Clock. Connect SCL to the logic rail through a 10-kΩresistor.
SDA
SCL
E4
E5
I/O
I
Adjustable Input Current Limit Programming. Connect a resistor from ILIM to GND to
program the input current limit. The input current includes the system load and the battery
charge current. Connect ILIM to GND to set the input current limit to the internal default
threshold. ILIM can also be updated through I2C.
ILIM
C2
E3
I
I
Load Switch and LDO Control Input. Pull high to enable the LS/LDO output, pull low to
disable the LS/LDO output.
LSCTRL
Fast-Charge Current Programming Input. Connect a resistor from ISET to GND to program
the fast-charge current level. Connect a resistor from ISET to GND to set the charge current
to the internal default. ISET can also be updated through I2C. While charging, the voltage at
ISET reflects the actual charging current and can be used to monitor charge current if an
ISET resistor is present and the device is not in host mode.
ISET
C1
I
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表7-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Termination current programming input. Connect a 0-Ω to 10-kΩ resistor from IPRETERM to
GND to program the termination current between 5% and 20% of the charge current. The
pre-charge current is the same as the termination current setting. Connect IPRETERM to
GND to set the termination current to the internal default threshold. IPRETERM can also be
updated through I2C.
IPRETERM
D1
I
Status Output. INT is an open-drain output that signals charging status and fault interrupts.
INT pulls low during charging. INT is high impedance when charging is complete, disabled,
or the charger is in high impedance mode. When a fault occurs, a 128µs pulse is sent out as
an interrupt for the host. INT charge indicator function is enabled/disabled using the EN_INT
bit in the control register. Connect INT to a logic rail using an LED for visual indication of
charge status or through a 100kΩresistor to communicate with the host processor.
INT
PG
D2
D4
O
O
Open-drain Power Good status indication output. PG pulls to GND when VIN is above V(BAT)
+ VSLP and less that VOVP. PG is high-impedance when the input power is not within
specified limits. Connect PG to the desired logic voltage rail using a 1kΩ to 100kΩ resistor,
or use with an LED for visual indication. PG can also be configured as a push-button voltage
shifted output (MRS) in the registers, where the output of the PG pin reflects the status of
the MR input, but pulled up to the desired logic voltage rail using a 1kΩ to 100kΩ resistor.
Reset Output. RESET is an open drain active low output that goes low when MR is held low
for longer than tRESET, which is configurable by the MRRESET registers. RESET is
deasserted after the tRESET_D, typically 400ms.
RESET
MR
D3
E1
O
I
Manual Reset Input. MR is a push-button input that must be held low for greater than tRESET
to assert the reset output. If MR is pressed for a shorter period, there are two programmable
timer events, tWAKE1 and tWAKE2, that trigger an interrupt to the host. The MR input can also
be used to bring the device out of Ship mode.
SW
A4
B5
O
I
Inductor Connection. Connect to the switched side of the external inductor.
System Voltage Sense Connection. Connect SYS to the system output at the output bulk
capacitors. Bypass SYS locally with at least 4.7 µF of effective ceramic capacitance.
SYS
Load Switch or LDO output. Connect 1 µF of effective ceramic capacitance to this pin to
assure stability. Be sure to account for capacitance bias voltage derating when selecting the
capacitor.
LS/LDO
C5
O
Input to the Load Switch / LDO output. Connect 1 µF of effective ceramic capacitance from
this pin to GND.
VINLS
BAT
B4, C4
B1, B2
I
Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with
at least 1 µF of ceramic capacitance.
I/O
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from VIN to
GND. The NTC is connected from TS to GND. The TS function provides four thresholds for
JEITA compatibility. TS faults are reported by the I2C interface during charge mode.
TS
C3
I
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English Data Sheet: SLUSDA7
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ZHCSI47A –APRIL 2018 –REVISED JANUARY 2021
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
MAX
UNIT
V
IN
wrt GND
wrt GND
20
PMID, VINLS
Input voltage
7.7
V
CD, SDA, SCL, ILIM, ISET, IPRETERM, LSCTRL,
INT, RESET, TS
wrt GND
5.5
V
–0.3
Output voltage
SYS
3.6
400
10
V
Input current
IN
mA
mA
mA
V
Sink current
INT
Sink/Source Current
Output Voltage Continuos
RESET
SW
10
7.7
400
300
150
6.6
125
150
–0.7
SW
mA
mA
mA
V
Output Current Continuous
SYS, BAT
LS/LDO
VBAT, MR,
Current
BAT Operating Voltage
Junction Temperature
Storage Temperature, Tstg
°C
–40
–55
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.4
NOM
MAX
20
UNIT
IN voltage range
5
5
VIN
V
IN operating voltage range, recommended
V(BAT) operating voltage range
VINLS voltage range for Load Switch
VINLS voltage range for LDO
Input Current, IN input
3.4
5.5
V(BAT)
V(VINLS)
V(VINLS)
IIN
5.5(1)
5.5(2)
5.5
V
0.8
2.2
V
V
400
300
300
100
300
125
mA
mA
mA
mA
mA
°C
I(SW)
Output Current from SW, DC
Output Current from PMID, DC
Output Current from LS/LDO
I(PMID)
ILS/LDO
I(BAT), I(SYS) Charging and discharging using internal battery FET
TJ Operating junction temperature range
–40
(1) Any voltage greater than shown should be a transient event.
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English Data Sheet: SLUSDA7
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(2) These inputs will support 6.6 V for less than 10% of the lifetime at V(BAT) or VIN, with a reduced current and/or performance.
8.4 Thermal Information
BQ25121A
THERMAL METRIC(1)
YFP (DSBGA)
UNIT
25 PINS
60
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
0.3
12.0
1.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
12.0
N/A
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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8.5 Electrical Characteristics
Circuit of 图8-1, V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP), TJ = –40°C to 85°C and TJ = 25°C for typical values
(unless otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP) PWM
Switching, –40°C < TJ < 85°C
1
mA
Supply Current for
Control
IIN
V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP) PWM NOT
Switching
3
1.5
1.2
mA
mA
µA
0°C < TJ < 85°C, VIN = 5 V, Charge Disabled
0°C < TJ < 60°C, VIN = 0 V, High-Z Mode, PWM Not
Switching, V(BUVLO) < V(BAT) < 4.65 V
0.7
0.9
0°C < TJ < 60°C, VIN = 0 V, High-Z Mode, PWM Not
Switching, V(BUVLO) < V(BAT) < 6.6 V
1.5
3.5
µA
µA
µA
Battery discharge current
in High Impedance Mode
I(BAT_HIZ)
0°C < TJ < 60°C, VIN = 0 V or floating, High-Z Mode, PWM
Switching, No Load
0.75
1.35
0°C < TJ < 85°C, VIN = 0 V, High-Z Mode, PWM Switching,
LSLDO enabled
4.25
0°C < TJ < 85°C, VIN = 0 V, Active Battery Mode, PWM
Switching, LSLDO enabled, I2C Enabled, V(BUVLO) < V(BAT)
4.65 V
<
6.8
12
µA
Battery discharge current
in Active Battery Mode
I(BAT_ACTIVE)
0°C < TJ < 85°C, 0 < VIN < VIN(UVLO), Active Battery Mode,
PWM Switching, LSLDO disabled, I2C Enabled, CD = Low,
V(BUVLO) < V(BAT) < 4.65 V
6.2
2
11
µA
nA
Battery discharge current
in Ship Mode
I(BAT_SHIP)
0°C < TJ < 85°C, VIN = 0 V, Ship Mode
150
POWER-PATH MANAGEMENT and INPUT CURRENT LIMIT
VDO(IN-PMID)
VIN = 5 V, IIN = 300 mA
125
120
170
160
mV
mV
VIN –V(PMID)
(BAT) –V(PMID)
VDO(BAT-PMID)
VIN = 0 V, V(BAT) > 3 V, Iff = 400 mA
V
V(PMID)
<
(BAT) –25
mV
Enter supplement mode
threshold
V(BSUP1)
V(BAT) > V(BUVLO)
V
V
V
V(PMID)
V(BAT)
<
–
Exit supplement mode
threshold
V(BSUP2)
V(BAT) > V(BUVLO)
5mV
Current Limit, Discharge
Mode
I(BAT_OCP)
V(BAT) > V(BUVLO)
0.85
50
1.15
1.35
400
A
Input Current Limit
Programmable Range, 50-mA steps
mA
Maximum Input Current
using ILIM
K(ILIM)
R(ILIM)
/
I(ILIM)
50 mA to 100 mA
12%
5%
–12%
–5%
175
IILIM accuracy IILIM
accuracy
100 mA to 400 mA
I(ILIM) = 50 mA to 100 mA
I(ILIM) = 100 mA to 400 mA
200
200
225
210
AΩ
AΩ
Maximum input current
factor
K(ILIM)
190
Input voltage threshold
when input current is
reduced
Programmable Range using VIN(DPM) Registers. Can be
disabled using VIN(DPM_ON)
4.2
4.9
3%
V
VIN(DPM)
VIN_DPM threshold
accuracy
–3%
BATTERY CHARGER
PMID voltage threshold
V(DPPM)
when charge current is
reduced
Above V(BATREG)
0.2
V
Internal Battery Charger
MOSFET on-resistance
RON(BAT-PMID)
Measured from BAT to PMID, V(BAT) = 4.35 V, High-Z mode
300
400
4.65
mΩ
Operating in voltage regulation, Programmable Range, 10-
mV steps
Charge Voltage
3.6
V
V(BATREG)
Voltage Regulation
Accuracy
TJ = 0°C to 85°C
0.5%
–0.5%
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8.5 Electrical Characteristics (continued)
Circuit of 图8-1, V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP), TJ = –40°C to 85°C and TJ = 25°C for typical values
(unless otherwise noted)
PARAMETERS
TEST CONDITIONS
V(BATUVLO) < V(BAT) < V(BATREG)
MIN
TYP
MAX
UNIT
Fast Charge Current
Range
5
300
mA
Fast Charge Current
using ISET
K(ISET)
R(ISET)
/
I(CHARGE)
A
Fast Charge Current
Accuracy
5%
210
37
–5%
190
0.5
Fast Charge Current
Factor
K(ISET)
5 mA > I(CHARGE) > 300 mA
200
AΩ
Termination charge
current
Termination current programmable range over I2C
mA
5
10
15
20
% of ISET
% of ISET
% of ISET
% of ISET
I(CHARGE) < 300 mA, R(ITERM) = 15 kΩ
I(CHARGE) < 300 mA, R(ITERM) = 4.99 kΩ
I(CHARGE) < 300 mA, R(ITERM) = 1.65 kΩ
I(CHARGE) < 300 mA, R(ITERM) = 549 Ω
I(TERM) > 4 mA
Termination Current
using IPRETERM
I(TERM)
Accuracy
10%
37
–10%
tDGL(TERM)
TERM deglitch time
Pre-charge current
Both rising and falling, 2-mV over-drive, tRISE, tFALL = 100 ns
Pre-charge current programmable range over I2C
64
ms
0.5
mA
Pre-charge Current using
IPRETERM
I(TERM)
A
I(PRE_CHARGE)
Accuracy
10%
140
–10%
Recharge threshold
voltage
V(RCH)
Below V(BATREG)
100
120
32
mV
ms
Recharge threshold
deglitch time
tDGL(RCHG)
tFALL = 100 ns typ, V(RCH) falling
SYS OUTPUT
RDS(ON_HS)
RDS(ON_LS)
PMID = 3.6 V, I(SYS)
PMID = 3.6 V, I(SYS)
=
=
675
300
850
475
mΩ
mΩ
MOSFET on-resistance
for SYS discharge
RDS(CH_SYS)
22
40
VIN = 3.6 V, IOUT = –10 mA into VOUT pin
Ω
SW Current limit HS
SW Current limit LS
2.2 V < V(PMID) < 5.5 V
2.2 V < V(PMID) < 5.5 V
450
450
600
700
675
850
mA
mA
I(LIMF)
PMOS switch current limit
during softstart
I(LIM_SS)
Current limit is reduced during softstart
Programmable range, 100 mV Steps
80
130
200
mA
V
SYS Output Voltage
Range
1.1
3.3
Output Voltage Accuracy VIN = 5 V, PFM mode, IOUT = 10 mA, V(SYS) = 1.8 V
0
2.5%
–2.5%
VSYS
DC Output Voltage Load
VOUT = 2 V, over load range
Regulation in PWM mode
0.01
%/mA
%/V
DC Output Voltage Line
VOUT = 2 V, IOUT = 100 mA, over VIN range
Regulation in PWM mode
0.01
LS/LDO OUTPUT
Input voltage range for
Load Switch Mode
LS/LDO
0.8
2.2
6.6
6.6
V
V
VIN(LS)
Input voltage range for
LDO Mode
LS/LDO
TJ = 25°C
DC output accuracy
±1%
±2%
2%
3%
3.3
1%
1%
60
–2%
–3%
0.8
VOUT
Over VIN, IOUT, temperature
VLDO
Output range for LS/LDO Programmable Range, 0.1 V steps
V
DC Line regulation
DC Load regulation
Load Transient
VOUT(NOM) + 0.5 V < VIN < 6.6 V, IOUT = 5 mA
0 mA < IOUT < 100 mA
–1%
–1%
–120
ΔVOUT / ΔVIN
2 µA to 100 mA, VOUT = 1. 8 V
mV
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8.5 Electrical Characteristics (continued)
Circuit of 图8-1, V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP), TJ = –40°C to 85°C and TJ = 25°C for typical values
(unless otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RDS(ON_LDO)
FET Rdson
V(VINLS) = 3.6 V
570
800
mΩ
MOSFET on-resistance
for LS/LDO discharge
R(DSCH_LSLDO)
20
1.7 V < V(VINLS) < 6.6 V, ILOAD = –10 mA
Ω
Output Current Limit –
LDO
I(OCL_LDO)
VLS/LDO = 0 V
275
365
475
mA
V(VINLS) = 3.6 V, VLSLDO = 3.3 V
V(VINLS) = 3.3 V, VLSLDO = 0.8 V
V(VINLS) = 2.2 V, VLSLDO = 0.8 V
100
100
10
mA
mA
mA
I(LS/LDO)
Output Current
Quiescent current for
VINLS in LDO mode
0.9
µA
µA
V
IIN(LDO)
OFF-state supply current
0.25
High-level input voltage
for LSCTRL
0.75 x
V(SYS)
VIH(LSCTRL)
VIL(LSCTRL)
1.15 V > V(VINLS) > 6.6 V
1.15 V > V(VINLS) > 6.6 V
6.6
Low-level input voltage
for LSCTRL
0.25 x
V(SYS)
V
PUSHBUTTON TIMER ( MR)
VIL
Low-level input voltage
VBAT > VBUVLO
0.3
V
Internal pull-up
resistance
RPU
120
kΩ
VBAT MONITOR
VBMON
Battery Voltage Monitor
Accuracy
V(BAT) Falling - Including 2% increment
3.5 %V(BATREG)
–3.5
BATTERY-PACK NTC MONITOR
High temperature
threshold
VHOT
VTS falling, 1% VIN Hysteresis
VTS falling, 1% VIN Hysteresis
VTS rising, 1% VIN Hysteresis
14.5
20.1
35.4
15
20.5
36
15.2
%VIN
%VIN
%VIN
Warm temperature
threshold
VWARM
20.8
36.4
Cool temperature
threshold
VCOOL
Low temperature
threshold
VCOLD
VTS rising, 1% VIN Hysteresis
VTS rising, 2% VIN Hysteresis
39.3
55
39.8
40.2
60
%VIN
%VIN
TSOFF
TS Disable threshold
PROTECTION
IC active threshold
voltage
V(UVLO)
VIN rising
3.4
3.6
3.8
V
mV
V
VUVLO(HYS)
IC active hysteresis
VIN falling from above VUVLO
150
Battery Undervoltage
Lockout threshold Range Hysteresis
Programmable Range for V(BUVLO) VBAT falling, 150 mV
2.2
3.0
V(BUVLO)
Default Battery
Undervoltage Lockout
Accuracy
V(BAT) falling
2.5%
–2.5%
Battery short circuit
threshold
V(BATSHORT)
V(BATSHORT_HYS)
I(BATSHORT)
V(SLP)
Battery voltage falling
2
100
V
Hysteresis for
V(BATSHORT)
mV
mA
mV
mV
V
Battery short circuit
charge current
I(PRETERM)
65
Sleep entry threshold, VIN
–V(BAT)
2 V < VBAT < V(BATREG), VIN falling
VIN rising above V(SLP)
120
100
Sleep-mode exit
hysteresis
V(SLP_HYS)
VOVP
40
65
Maximum Input Supply
OVP threshold voltage
VIN rising, 100 mV hysteresis
VIN falling below VOVP, 1V/us
5.35
5.55
5.75
Deglitch time, VIN OVP
falling
tDGL_OVP
32
ms
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8.5 Electrical Characteristics (continued)
Circuit of 图8-1, V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP), TJ = –40°C to 85°C and TJ = 25°C for typical values
(unless otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP
114
11
MAX
UNIT
°C
TSHTDWN
THYS
Thermal trip
VIN > VUVLO
VIN > VUVLO
Thermal hysteresis
°C
Deglitch time, Thermal
shutdown
tDGL_SHTDWN
TJ rising above TSHTDWN
4
µs
I2C INTERFACE
I2C Bus Specification
standard and fast mode
frequency support
100
400
kHz
VIL
VIH
VIH
Input low threshold level VPULLUP = 1.1 V, SDA and SCL
Input high threshold level VPULLUP = 1.1 V, SDA and SCL
Input high threshold level VPULLUP = 3.3 V, SDA and SCL
0.275
V
V
V
0.825
2.475
Output low threshold
VOL
IL = 5 mA, sink current, VPULLUP = 1.1 V
level
0.275
1
V
High-Level leakage
VPULLUP = 1.8 V, SDA and SCL
current
IBIAS
µA
INT, PG, and RESET OUTPUT (Open Drain)
Low level output
threshold
0.25 x
V(SYS)
VOL
Sinking current = 5 mA
V
IIN
Bias current into pin
12
nA
Pin is high impedance, IOUT = 0 mA; TJ = –40°C to 60°C
Input voltage above
VBAT where PG sends
two 128 µs pulses each
minute to signal the host
of the input voltage status
VIN(BAT_DELTA)
VUVLO < VIN < VOVP
0.825
1
1.15
V
INPUT PIN ( CD LSCTRL)
VIL(/CD_LSCTRL)
Input low threshold
V(PULLUP) = VSYS = 3.3 V
V(PULLUP) = VSYS = 3.3 V
0.25 * VSYS
V
V
VIH(/CD_LSCTRL) Input high threshold
0.75 * VSYS
Internal pull-down
RPULLDOWN/CD
900
2
kΩ
resistance
Internal pull-down
R(LSCTRL)
MΩ
resistance
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8.6 Timing Requirements
MIN
TYP
MAX
UNIT
POWER-PATH MANAGEMENT AND INPUT CURRENT LIMIT
Deglitch Time, PMID or SW Short Circuit
during Discharge Mode
tDGL_SC
250
2
µs
s
Recovery time, OUT Short Circuit during
Discharge Mode
tREC_SC
BATTERY CHARGER
Deglitch time transition from ISET short to
I(CHARGE) disable
tDGL_SHORT
Clear fault by disconnecting VIN
1
ms
BATTERY CHARGING TIMERS
tMAXCHG
tPRECHG
Charge safety timer
Programmable range
2
540
min
Precharge safety timer
0.1 x tMAXCHG
SYS OUTPUT
tONMIN
Minimum ON time
Minimum OFF time
VIN = 3.6 V, VOUT = 2 V, IOUT = 0 mA
VIN = 4.2 V
225
50
ns
ns
tOFFMIN
VIN = 5 V, from write on EN_SW_OUT
until output starts to rise
tSTART_SW
SW start up time
5
25
ms
From insertion of BAT > V(BUVLO) or
VIN > V(UVLO)
tSTART_SYS
tSOFTSTART
SYS output time to start switching
350
400
µs
µs
Softstart time with reduced current limit
1200
LS/LDO OUTPUT
tON_LDO
Turn ON time
Turn OFF time
100-mA load
100-mA load
500
5
µs
µs
tOFF_LDO
PUSHBUTTON TIMER
tWAKE1 Push button timer wake 1
0.08
1
1
2
s
s
Programmable Range for wake2
function
tWAKE2
Push button timer wake 2
Programmable Range for reset
function
tRESET
tRESET_D
tDD
Push button timer reset
Reset pulse duration
5
15
s
400
6
ms
µs
Detection delay (from MR, input to
RESET)
For 0s condition
BATTERY-PACK NTC MONITOR
Applies to V(HOT), V(WARM), V(COOL),
and V(COLD)
tDGL(TS)
Deglitch time on TS change
50
ms
I2C INTERFACE
tI2CRESET
I2C interface inactive reset timer
700
ms
ms
Transition time required to enable the I2C
interface from HiZ to Active BAT
tHIZ_ACTIVEBAT
1
INPUT PIN
t/CD_DGL
Deglitch for CD
CD rising/falling
100
µs
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Typical Start-Up Timing and Operation
Remove
Battery
Apply
VIN
Insert
Battery
BAT supplies SYS
when VIN removed
VIN
PMID
VIN > UVLO
PG
SW
After delay of several ms,
switching starts and SYS
starts to rise
SYS
CD
Charging
enabled
Charge
Current
Taper
Charging
disabled
IBAT = ITERM
No SYS Load
0mA
IBAT
VBAT = VBATREG
VBAT
rises
VBAT =
VBATREG - VRCHG
VBAT>VBUVLO
IBAT=ICHRG
SYS Load Applied
VBAT
INT
Shows
Charge
Status
<3uA max
<4uA max
VISET
<5uA max
<4uA max
<3uA max
nA of leakage with VIN present
BAT IQ
Conditions: PGB_MRS = 0, TE = 1, SW_LDO = 1, VINDPM_ON = 0, PG and INT pulled up to SYS, EN_INT = 1
图8-1. Typical Start-Up Timing and Operation
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Conditions: SW_LDO = 1, MRREC = 1, PG and INT pulled up to SYS, ISYS = 10 µA, EN_INT = 1
图8-2. Battery Operation and Sleep Mode
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8.7 Typical Characteristics
12
2.0
1.5
1.0
0.5
0.0
10
8
6
4
2
85èC
60èC
25èC
0èC
85èC
60èC
25èC
0èC
0
3
3.2
3.4
3.6
3.8
BAT (V)
4
4.2
4.4
4.6
3
3.2
3.4
3.6
3.8
BAT (V)
4
4.2
4.4
4.6
D017
D016
1.8 V System Enabled (No Load)
图8-4. Hi-Z BAT, IQ
图8-3. Active BAT, IQ
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
700
600
500
400
300
200
100
0
85èC
60èC
25èC
0èC
3
3.2
3.4
3.6
3.8
BAT (V)
4
4.2
4.4
4.6
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D018
D024
图8-5. Ship Mode BAT, IQ
图8-6. Blocking FET RDS(ON) vs Temperature
400
350
300
250
200
150
100
50
0.5%
0.3%
0.1%
-0.1%
-0.3%
-0.5%
4.35 V(BATREG)
4.2 V(BATREG)
4 V(BATREG)
3.8 V(BATREG)
3.6 V(BATREG)
0
-40
-10
20
50
80
110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Temperature (èC)
D019
D025
图8-8. V(BATREG) Accuracy vs Temperature
图8-7. Battery Discharge FET RDS(ON) vs Temperature
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8.7 Typical Characteristics (continued)
5%
4%
3%
2%
1%
0
5%
3%
-40èC
0èC
25èC
85èC
125èC
1%
-1%
-2%
-3%
-4%
-5%
-1%
-3%
-5%
-40èC
0èC
25èC
85èC
125èC
0.05
0.1
0.15
0.2
0.25
Input Current Limit (A)
0.3
0.35
0.4
0
50
100
150
Charge Current (mA)
200
250
300
D020
D021
图8-9. ILIM Accuracy vs Input Current
图8-10. Charge Current Accuracy vs Charge Current
10%
1000
900
800
700
600
500
400
300
200
100
0
-40èC
0èC
25èC
85èC
125èC
8%
6%
4%
2%
0
-2%
-4%
-6%
-8%
-10%
0
5
10
15
20
25
Pre-Charge Current (mA)
30
35
40
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D022
D0264
图8-11. Pre-Charge Accuracy vs Pre-Charge Current
VIN = 5 V
图8-12. RDS(ON) of High Side MOSFET vs Temperature
400
350
300
250
200
150
100
50
160
Noise Floor
1 mA
10 mA
50 mA
100 mA
140
120
100
80
60
40
20
0
0
10 20 50 100
1000 10000
Frequency (Hz)
100000
1000000
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D028
D027
图8-14. LS/LDO PSRR vs Frequency
VIN = 5 V
图8-13. RDS(ON) of Low Side MOSFET vs Temperature
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9 Detailed Description
9.1 Overview
The following sections describe in detail the functions provided by the BQ25121A. These include linear charger,
PWM output, configurable LS/LDO output, Push-button input, reset timer, functional modes, battery monitor, I2C
configurability and functions, and safety features.
9.2 Functional Block Diagram
PMID
Q1/Q2
Q3
IN
SW
D
S
G
GND
IINLIM
Q4
PWM, LDO, and BAT FET
Control
SYS
VSYSREG
VIN_DPM
VINLS
LDO
Control
S
VBATREG
IBATREG
Thermal
Shutdown
G
D
LDO/ Load Switch
Control
Q5
VSUPPLY
Hi-Z
Mode
LS/LDO
CD
Termination
Reference
VIN
Q7
SDA
SCL
I2C
Interface
IBAT
+
+
LDO/ Load Switch
Host Control
LSCTRL
ILIM
Disable
Input Current Limit
Charge Current
TS COLD
+
+
ISET
1C/
0.5C
TS COOL
TS WARM
BAT
Termination Current
IPRETERM
PG
VBATREG
œ 140mV
+
VBAT(SC)
+
+
Disable
Device Control
TS HOT
VIN
VOVP
INT
VINOVP
VBAT
VBATOVP
BATOVP
+
+
VBAT
BATSHRT
Recharge
VBATSHRT
+
VBATREG œ 0.12 V
VBAT
RESET
Reset and
Timer
MR
TS
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9.3 Feature Description
9.3.1 Ship Mode
Ship Mode is the lowest quiescent current state for the device. Ship Mode latches off the device and BAT FET
until VIN > VBAT + VSLP or the MR button is depressed for tWAKE1 and released. The following list shows the
events that are active during Ship Mode:
1. VIN_UV Comparator
2. MR Input (No clock or delay in this mode for lowest power consumption)
3. PMID active pull down
9.3.1.1 Ship Mode Entry and Exit
The device may only enter Ship Mode when there is not a valid VIN supply present (VIN < VUVLO). Once the IN
supply is removed there are two ways for the device to enter Ship Mode: through I2C command using the
EN_SHIPMODE bit and by doing a long button press when MRREC bit is set to 0. If the EN_SHIPMODE bit is
set while the IN supply is present, the device will enter Ship Mode upon removal of the supply. The
EN_SHIPMODE bit can be cleared using the I2C interface as well while the IN input is valid.
In addition to VIN < VUVLO, CD and MR must be high. Once all of these conditions are met the device will begin
the transition to Ship Mode. All three conditions must remain unchanged for a period of tQUIET to ensure proper
operation. 图 9-1 and 图 9-2 show the correct sequencing to ensure proper entry into the Ship Mode through I2C
command and MR button press respectively.
tQUIET
CD
MR
VIN
Shipmode
2
I C
Write
图9-1. CD, MR and VIN Sequencing for Ship Mode Entry Through I2C Command
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tQUIET
CD
MR
VIN
t > tRESET
Shipmode
2
I C
Write
图9-2. CD, MR and VIN Sequencing for Ship Mode Entry Through Long MR Button Press
The end user can enable the device (exit Ship Mode) by connecting an adapter to IN (VIN > VBAT + VSLP) or by
toggling the MR button. Note that in the case where an adapter is connected while the MR is still held low and
immediately after the RESET timer has expired ( MR low for tRESET), the device will not enter Ship Mode, but
may enter it upon adapter removal (Same behavior as setting the EN_SHIPMODE bit when the adapter is
present). This will not be the case if MR has gone high when the adapter is connected or MR continues to be
held low for a period longer than tWAKE1 after the adapter is connected.
To exit Ship Mode through and MR press the battery voltage must be above the maximum programmable
BUVLO threshold when VIN is not present. Once MR goes low, the device will start to exit Ship Mode, powering
PMID. The device will not complete the transition from Ship Mode until MR has been held low for at least tWAKE1
.
Only after the transition is complete may the host start I2C communication if the device has not entered High
Impedance Mode.
9.3.2 High Impedance Mode
High Impedance mode is the lowest quiescent current state while operating from the battery. During Hi-Z mode
the SYS output is powered by BAT, the MR input is active, and the LSCTRL input is active. All other circuits are
in a low power or sleep state. The LS/LDO output can be enabled in Hi-Z mode with the LSCTRL input. If the
LS/LDO output has been enabled through I2C prior to entering Hi-Z mode, it will stay enabled. The CD pin is
used to put the device in a high-impedance mode when battery is present and VIN < VUVLO. Drive CD high to
enable the device and enter active battery operation when VIN is not valid. When the HZ_MODE bit is written by
the host, the I2C interface is disabled if only battery is present. To resume I2C, the CD pin must be toggled. If the
supply for the CD pull up glitches or experiences a brownout condition , it is recommended to toggle the /CD pin
to resume I2C communication.. The functionality of the pin is shown in 表9-1.
表9-1. CD, State Table
CD, STATE
VIN < VUVLO
VIN > VUVLO
L
Hi-Z
Charge Enabled
Charge Disabled
H
Active Battery
9.3.3 Active Battery Only Connected
When the battery above VBATUVLO is connected with no input source, the battery discharge FET is turned on.
After the battery rises above VBATUVLO and the deglitch time is reached, the SYS output starts to rise. The
current from PMID and SYS is not regulated, but is protected by a short circuit current limit. If the short circuit
limit is reached for the deglitch time (tDGL_SC), the battery discharge FET is turned off for the recovery time
(tREC_SC). After the recovery time, the battery FET is turned on to test if the short has been removed. If it has not,
the FET turns off and the process repeats until the short is removed. This process protects the internal FET from
over current. During this event PMID will likely droop and cause SYS to go out of regulation.
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To provide designers the most flexibility in optimizing their system, an adjustable BATUVLO is provided. When
the voltage drops below the VBATUVLO threshold, the battery discharge FET is turned off. Deeper discharge of the
battery enables longer times between charging, but may shorten the battery life. The BATUVLO is adjustable
with a fixed 150-mV hysteresis.
If a valid VIN is connected during active battery mode, VIN > VUVLO, the supplement and battery discharge FET is
turned on when the battery voltage is above the minimum VBATUVLO
.
Drive CD high or write the CE register to disable charge when VIN > VUVLO is present. CD is internally pulled
down. When exiting this mode, charging resumes if VIN is present, CD is low and charging is enabled.
All HOST interfaces ( CD, SDA/SCL, INT, RESET and LSCTRL) are active no later than 5 ms after SYS reaches
the programmed level.
9.3.4 Voltage Based Battery Monitor
The device implements a simple voltage battery monitor which can be used to determine the depth of discharge.
Prior to entering High-Z mode, the device will initiate a VBMON reading. The host can read the latched value for
the no-load battery voltage, or initiate a reading using VBMON_READ to see the battery voltage under a known
load. The register will be updated and can be read 2ms after a read is initiated. The VBMON voltage threshold is
readable with 2% increments with ±1.5% accuracy between 60% and 100% of VBATREG using the VBMON_TH
registers. Reading the value during charge is possible, but for the most accurate battery voltage indication, it is
recommended to disable charge, initiate a read, and then re-enable charge.
A typical discharge profile for a Li-Ion battery is shown in 表 9-2. The specific battery to be used in the
application should be fully characterized to determine the thresholds that will indicate the appropriate battery
status to the user. Two typical examples are shown below, assuming the VBMON reading is taken with no load
on the battery.
This function enables a simple 5-bar status indicator with the following typical performance with different
VBATREG settings:
表9-2. Discharge Profile for a Li-Ion Battery
95% to 65%
65% to 35%
35% to 5%
VBATREG
BATTERY FULL
BATTERY EMPTY
REMAINING CAPACITY REMAINING CAPACITY REMAINING CAPACITY
4.35 V
4.2 V
VBMON > 90%
VBMON > 98%
VBMON = 88%
VBMON = 86%
VBMON = 84%
VBMON < 82%
VBMON < 84%
VBMON = 94% or 96%
VBMON = 90% or 92%
VBMON = 86% or 88%
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VREF
S0
-2 % BAT TAP
-4 % BAT TAP
-6 % BAT TAP
-8 % BAT TAP
-10 % BAT TAP
S1
90 % VB
D
E
80 % VB
S2
C
O
D
E
R
S3
70 % VB
60 % VB
VB =0. 8 VBAT
图9-3. Voltage Battery Monitor
9.3.5 Sleep Mode
The device enters the low-power sleep mode if the voltage IN falls below the sleep-mode entry threshold and VIN
is higher than the undervoltage lockout threshold. In sleep mode, the input is isolated from the connected
battery. This feature prevents draining the battery during the absence of VIN. When VIN < V(BAT) + VSLP, the
device turns the battery discharge FET on, sends a 128-µs pulse on the INT output, and the FAULT bits of the
register are update over I2C. Once VIN > V(BAT) + VSLP, the device initiates a new charge cycle. The FAULT bits
are not cleared until they are read over I2C and the sleep condition no longer exists. It is not recommended to do
a battery connection or plug in when VUVLO< VIN < VBAT + VSLP as it may cause higher quiescent current to be
drained form the battery.
9.3.6 Input Voltage Based Dynamic Power Management (VIN(DPM)
)
During the normal charging process, if the input power source is not able to support the programmed or default
charging current and System load, the supply voltage decreases. Once the supply approaches VIN(DPM), the
input DPM current and voltage loops will reduce the input current through the blocking FETs, to prevent the
further drop of the supply. The VIN(DPM) threshold is programmable through the I2C register from 4.2 V to 4.9 V in
100-mV steps. It can be disabled completely as well. When the device enters this mode, the charge current may
be lower than the set value and the VINDPM_STAT bit is set. If the 2X timer is set, the safety timer is extended
while VIN(DPM) is active. Additionally, termination is disabled. Note that in a condition where the battery is
connected while VUVLO<VIN < VIN(DPM), the VINDPM loop will prevent the battery from being charged and PMID
will be powered from BAT.
9.3.7 Input Overvoltage Protection and Undervoltage Status Indication
The input overvoltage protection protects the device and downstream components connected to PMID, SYS,
and BAT against damage from overvoltage on the input supply. When VIN > VOVP an OVP fault is determined to
exist. During the OVP fault, the device turns the battery discharge FET on, sends a single 128-µs pulse on INT,
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and the FAULT bits are updated over I2C. Once the OVP fault is removed, after the deglitch time, tDGL_OVP, STAT
and FAULT bits are cleared and the device returns to normal operation. The FAULT bits are not cleared until they
are read in from I2C after the OVP condition no longer exists. The OVP threshold for the device is set to operate
from standard USB sources.
The input under-voltage status indication is used to notify the host or other device when the input voltage falls
below a desired threshold. When VIN < VUVLO, after the deglitch time tDGL_UVLO, a UVLO fault is determined to
exist. During the VIN UVLO fault, the device sends a single 128-µs pulse on INT, and the STAT and FAULT bits
are updated over I2C. The FAULT bits are not cleared until they are read in from I2C after the UVLO condition no
longer exists.
9.3.8 Battery Charging Process and Charge Profile
When a valid input source is connected (VIN > VUVLO and V(BAT) + VSLP < VIN < VOVP and VIN > VIN(DPM)), the CE
bit in the control register determines whether a charge cycle is initiated. When the CE bit is 1 and a valid input
source is connected, the battery discharge FET is turned off, and the output at SYS is regulated depending on
the output configuration. A charge cycle is initiated when the CE bit is written to a 0. Alternatively, the CD input
can be used to enable and disable charge.
The device supports multiple battery chemistries for single-cell applications. Charging is done through the
internal battery MOSFET. There are several loops that influence the charge current: constant current loop (CC),
constant voltage loop (CV), input current limit, VDPPM, and VIN(DPM). During the charging process, all loops are
enabled and the one that is dominant takes control.
The charge current is regulated to ICHARGE until the voltage between BAT and GND reaches the regulation
voltage. The voltage between BAT and GND is regulated to VBATREG (CV Mode) while the charge current
naturally tapers down. When termination is enabled, the device monitors the charging current during the CV
mode, and once the charge current tapers down to the termination threshold, ITERM, and the battery voltage is
above the recharge threshold, the device terminates charge, and turns off the battery charging FET. Termination
is disabled when any loop is active other than CV.
9.3.9 Dynamic Power Path Management Mode
With a valid input source connected, the power-path management circuitry monitors the input voltage and
current continuously. The current into IN is shared at PMID between charging the battery and powering the
system load at PMID, SYS, and LS/LDO. If the sum of the charging and load currents exceeds the current that
the VIN can support, the input DPM loop(VINDPM) reduces the current going into PMID through the input
blocking FETs. This will cause a drop on the PMID voltage if the system demands more current. If PMID drops
below the DPPM voltage threshold(VDPPM), the charging current is reduced by the DPPM loop through the
BATFET in order to stabilize PMID. If PMID continues to drop after BATFET charging current is reduced to zero,
the part enters supplement mode when PMID falls below the supplement mode threshold. Battery termination is
disabled while in DPPM mode. In order to charge the battery, the voltage at PMID has to be greater than
VBATREG + VDPPM threshold.
9.3.10 Battery Supplement Mode
While in DPPM mode, if the charging current falls to zero and the system load current increases beyond the
programmed input current limit, the voltage at PMID reduces further. When the PMID voltage drops below the
battery voltage by V(BSUP1), the battery supplements the system load. The battery stops supplementing the
system load when the voltage on the PMID pin rises above the battery voltage by V(BSUP2). During supplement
mode, the battery supplement current is not regulated, however, the short-circuit protection circuit is active.
Battery termination is disabled while in supplement mode.
9.3.11 Default Mode
The default mode is used when there is no host, or I2C communication is not available. If the externally
programmable pins, ILIM, ISET, and ITERM have resistors connected, that is considered the default mode. If any
one of these resistors is tied to GND, the default register settings are used. The default mode can be entered by
connecting a valid power source to VIN or the RESET bit is written. Default mode is exited by writing to the I2C
interface.
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9.3.12 Termination and Pre-Charge Current Programming by External Components (IPRETERM)
The termination current threshold is user programmable through an external resistor or through registers over
I2C. Set the termination current using the IPRETERM pin by connecting a resistor from IPRETERM to GND. The
termination can be set between 5% and 20% of the programmed output current set by ISET, using 表 9-3 for
guidance:
表9-3. IPRETERM Resistor Settings
RIPRETERM
IPRE_CHARGE and ITERM
KKIPRETERM
(STANDARD 1%
VALUES)
UNIT
TYP
(% of ISET)
RECOMMENDED
RIPRETERM
MIN
MAX
MIN
TYP
MAX
5
180
180
180
180
200
200
200
200
220
220
220
220
15000
4990
1650
549
Ω
Ω
Ω
Ω
10
15
20
Using the I2C register, the termination current can be programmed with a minimum of 500 µA and a maximum of
37 mA.
The pre-charge current is not independently programmable through the external resistor, and is set at the
termination current. The pre-charge and termination currents are programmable using the IPRETERM registers.
If no IPRETERM resistor is connected and the pin is tied to GND, the default values in the IPRETERM registers
are used. The external value can be used in host mode by configuring the IPRETERM registers. If the external
ICHG setting will be used after being in Host mode, the IPRETERM registers should be set to match the desired
external threshold for the highest ICHG accuracy.
Termination is disabled when any loop other than CV is active.
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9.3.13 Input Current Limit Programming by External Components (ILIM)
The input current limit threshold is user programmable through an external resistor or through registers over I2C.
Set the input current limit using the ILIM pin by connecting a resistor from ILIM to GND using 表 9-4 for
guidance. If no ILIM resistor is connected and the pin is tied to GND, the default ILIM register value is used. The
external value is not valid once the device enters host mode.
表9-4. ILIM Resistor Settings
ILIM
TYP
KILIM
RILIM
(STANDARD 1%
VALUES)
UNIT
MIN
MAX
MIN
TYP
MAX
0.048469388
0.09047619
0.146153846
0.19
0.051020408
0.095238095
0.153846154
0.2
0.053571429
0.1
190
190
190
190
190
190
200
200
200
200
200
200
210
210
210
210
210
210
3920
2100
1300
1000
665
Ω
Ω
Ω
Ω
Ω
Ω
0.161538462
0.21
0.285714286
0.380761523
0.30075188
0.400801603
0.315789474
0.420841683
499
The device has register programmable input current limits from 50 mA to 400 mA in 50-mA steps. The device is
USB-IF compliant for inrush current testing, assuming that the input capacitance to the device is selected to be
small enough to prevent a violation (<10 µF), as this current is not limited.
9.3.14 Charge Current Programming by External Components (ISET)
The fast charge current is user programmable through an external resistor or through registers over I2C. Set the
fast charge current by connecting a resistor from ISET to GND. If no ISET resistor is connected and the pin is
tied to GND, the default ISET register value is used. While charging, if the charge current is using the externally
programmed value, the voltage at ISET reflects the actual charging current and can be used to monitor charge
current. The current out of ISET is 1/100 (±10%) of the charge current. The charge current can be calculated by
using 表9-5 for guidance:
表9-5. ISET Resistor Settings
ISET
TYP
KISET
RISET
(STANDARD 1%
VALUES)
UNIT
MIN
MAX
MIN
TYP
MAX
0.285714286
0.19
0.30075188
0.2
0.315789474
0.21
190
190
190
190
190
190
190
190
190
190
190
190
190
190
200
200
200
200
200
200
200
200
200
200
200
200
200
200
210
210
210
210
210
210
210
210
210
210
210
210
210
210
665
1000
1500
2000
2940
3920
4990
6040
7320
10000
15000
20000
29400
39200
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
0.126666667
0.095
0.133333333
0.1
0.14
0.105
0.06462585
0.048469388
0.038076152
0.031456954
0.025956284
0.019
0.068027211
0.051020408
0.04008016
0.033112583
0.027322404
0.02
0.071428571
0.053571429
0.042084168
0.034768212
0.028688525
0.021
0.012666667
0.0095
0.013333333
0.01
0.014
0.0105
0.006462585
0.004846939
0.006802721
0.005102041
0.007142857
0.005357143
9.3.15 Safety Timer
At the beginning of the charge cycle, the device starts the safety timer. If charging has not terminated before the
programmed safety time, tMAXCHG, expires, the device enters idle mode and charging is disabled. The pre-
charge safety time, tPRECHG, is 10% of tMAXCHG. When a safety timer fault occurs, a single 128 µs pulse is sent
on the INT pin and the STAT and FAULT bits of the status registers are updated over I2C. The CD pin or power
must be toggled in order to clear the safety timer fault. The safety timer duration is programmable using the TMR
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bits. When the safety timer is active, changing the safety timer duration resets the safety timer. The device also
contains a 2X_TIMER bit that enables the 2X timer function to prevent premature safety timer expiration when
the charge current is reduced by a load on PMID, SYS, LS/LDO or a NTC condition. When t2X_TIMER function is
enabled, the timer is allowed to run at half speed when any loop is active other than CC or CV.
9.3.16 External NTC Monitoring (TS)
The I2C interface allows the user to easily implement the JEITA standard for systems where the battery pack
thermistor is monitored by the host. Additionally, the device provides a flexible voltage based TS input for
monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a
safe temperature during charging.
To satisfy the JEITA requirements, four temperature thresholds are monitored: the cold battery threshold, the
cool battery threshold, the warm battery threshold, and the hot battery threshold. These temperatures
correspond to the V(COLD), V(COOL), V(WARM), and V(HOT) threshold in 节 8.5. Charging and timers are suspended
when V(TS) < V(HOT) or > V(COLD). When V(COOL) < V(TS) < V(COLD), the charging current is reduced to half of the
programmed charge current. When V(HOT) < V(TS) < V(WARM), the battery regulation voltage is reduced by 140
mV (minimum VBATREG under this condition is 3.6V).
The TS function is voltage based for maximum flexibility. Connect a resistor divider from VIN to GND with TS
connected to the center tap to set the threshold. The connections are shown in 图 9-4. The resistor values are
calculated using 方程式1 and 方程式2. To disable the TS function, pull TS above TSOFF threshold.
VBATREG
1 x Charge/
0.5 x Charge
VDRV
– 140 mV
DISABLE
TS COLD
+
TS COOL
TS WARM
+
+
VDRV
TS HOT
RHI
+
TS
PACK+
TEMP
BQ25121A
RLO
PACK–
图9-4. TS Circuit
æ
ç
ç
è
ö
1
1
÷
V
x R
x R
x
-
IN
(COLD)
(HOT)
÷
V
V
(HOT)
(COLD)
ø
R
=
(LO)
æ
ç
ç
è
ö
æ
ç
ç
è
ö
V
V
IN
IN
V
(COLD)
÷
÷
-1
R
x
-1 - R
x
(HOT)
(COLD)
÷
ø
÷
V
(HOT)
ø
(1)
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æ
ç
ç
è
ö
V
IN
÷
- 1
÷
V
(COLD)
ø
R
=
(HI)
æ
ç
ç
è
ö
÷
÷
ø
1
1
+
R
R
(LO)
(COLD)
(2)
Where
• R(HOT) = the NTC resistance at the hot temperature
• R(COLD) = the NTC resistance at the cold temperature
The warm and cool thresholds are not independently programmable. The cool and warm NTC resistances for a
selected resistor divider are calculated using 方程式3 and 方程式4.
R
x R x V COOL%
(HI)
( )
(LO)
R
=
(COOL)
R
-
R
x V COOL% - R
x V COOL%
( )
(
)) ( (HI)
)
)
(
(LO)
(LO)
(
(3)
(4)
R
x R x V
(HI)
WARM%
(LO)
(
)
R
=
(WARM)
R
-
R
x V
-
R
x V
WARM%
(LO)
(
(LO) WARM% ) ((HI)
)
)
(
(
)
(
)
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9.3.17 Thermal Protection
During the charging process, to prevent overheating in the device, the junction temperature of the die, TJ, is
monitored. When TJ reaches T(SHUTDOWN) the device stops charging, disables the PMID output, disables the
SYS output, and disables the LS/LDO output. During the time that T(SHUTDOWN) is exceeded, the safety timer is
reset . The charge cycle resumes when TJ falls below T(SHUTDOWN) by T(HYS)
.
To avoid reaching thermal shutdown, ensure that the system power dissipation is under the limits of the device.
The power dissipated by the device can be calculated using 方程式5.
PDISS = P(BLOCK) + P(SYS) + P(LS/LDO) + P(BAT)
(5)
Where
• P(BLOCK) = (VIN –V(PMID)) x IIN
• P(SYS) = ISYS 2 x RDS(ON_HS)
• P(LS/LDO) = (V(INLS) –V(LS/LDO)) x I(LS/LDO)
• P(BAT) = (V(PMID) –V(BAT)) x I(BAT)
9.3.18 Typical Application Power Dissipation
The die junction temperature, TJ, can be estimated based on the expected board performance using 方程式6.
TJ = TA + θJA x PDISS
(6)
The θJA is largely driven by the board layout. For more information about traditional and new thermal metrics,
see the IC Package Thermal Metrics application report Semiconductor and IC Package Thermal Metrics
Application Report. Under typical conditions, the time spent in this state is short.
9.3.19 Status Indicators ( PG and INT)
The device contains two open-drain outputs that signal its status and are valid only after the device has
completed start-up into a valid state. If the part starts into a fault, interrupts will not be sent. The PG output
signals when a valid input source is connected. PG pulls to GND when VIN > VUVLO, VIN> VBAT+VSLP and VIN
<
VOVP. PG is high-impedance when the input power is not within specified limits. Connect PG to the desired logic
voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication.
The PG pin can be configured as a MR shifted (MRS) output when the PGB_MRS bit is set to 1. PG is high-
impedance when the MR input is not low, and PG pulls to GND when the MR input is below VOL(TH_MRS)
.
Connect PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor.
The INT pin is pulled low during charging when the EN_INT bit is set to 1 and interrupts are pulled high. When
EN_INT is set to 0, charging status is not indicated on the INT pin. When charge is complete or disabled, INT is
high impedance. The charge status is valid whether it is the first charge or recharge. When a fault occurs, a 128
µs pulse (interrupt) is sent on INT to notify the host.
9.3.20 Chip Disable ( CD)
The device contains a CD input that is used to disable the device and place it into a high impedance mode when
only battery is present. In this case, when CD is low, PMID and SYS remain active, and the battery discharge
FET is turned on. If the LS/LDO output has been enabled prior to pulling CD low, it will stay on. The LSCTRL pin
can also enable/disable the LS/LDO output when the CD pin is pulled low. The CD pin has an internal pull-down.
If VIN is present and the CD input is pulled low, charge is enabled and all other functions remain active. If VIN is
present and the CD input is pulled high, charge is disabled.
9.3.21 Buck (PWM) Output
The device integrates a low quiescent current switching regulator with DCS control allowing high efficiency down
to 10-µA load currents. DCS control combines the advantages of hysteretic and voltage mode control. The
internally compensated regulation network achieves fast and stable operation with small external components
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and low ESR capacitors. During PWM mode, it operates in continuous conduction mode, with a frequency up to
2 MHz. If the load current decreases, the converter enters a power save mode to maintain high efficiency down
to light loads. In this mode, the device generates a single switching pulse to ramp up the inductor current and
recharge the output capacitor, followed by a sleep period where most of the internal circuits are shut down to
achieve a low quiescent current. The duration of the sleep period depends on the load current and the inductor
peak current. For optimal operation and maximum power delivery allow VPMID > VSYS + 0.7V.
The output voltage is programmable using the SYS_SEL and SYS_VOUT bits in the SYS VOUT control register.
The SW output is enabled using the EN_SYS_OUT bit in the register. This bit is for testing and debug only and
not intended to be used in the final system. When the device is enabled, the internal reference is powered up
and the device enters softstart, starts switching, and ramps up the output voltage. When SW is disabled, the
output is in shutdown mode in a low quiescent state. The device provides automatic output voltage discharge so
the output voltage will ramp up from zero once the device in enabled again. Once SYS has been disabled, either
VIN needs to be connected or the MR button must be held low for the tRESET duration to re-enable SYS.
The output is optimized for operation with a 2.2-µH inductor and 10-µF output capacitor. 表 9-6 shows the
recommended LC output filter combinations.
表9-6. Recommended Output Filter
INDUCTOR VALUE (µH)
2.2
OUTPUT CAPACITOR VALUE (µF)
4.7
10
22
Recommended
Possible
Recommended
Possible
The inductor value affects the peak-to-peak ripple current, the PWM-to-PFM transition point where the part
enters and exits Pulse Frequency Modulation to lower the power consumed at low loads, the output voltage
ripple and the efficiency. The selected inductor must be selected for its DC resistance and saturation current.
The inductor ripple current (ΔIL) can be estimated according to 方程式7.
ΔIL = VSYS x (1-(VSYS/VPMID))/(L x f)
(7)
Use 方程式 8 to calculate the maximum inductor current under static load conditions. The saturation current of
the inductor should be rated higher than the maximum inductor current. As the size of the inductor decreases,
the saturation “knee” must be carefully considered to ensure that the inductance does not decrease during
higher load condition or transient. This is recommended because during a heavy load transient the inductor
current rises above the calculated value. A more conservative way is to select the inductor saturation current
above the high-side MOSFET switch current.
IL(max) = ISYS(max) + ΔIL / 2
(8)
Where
• F = Switching Frequency
• L = Inductor Value
• ΔIL = Peak to Peak inductor ripple current
• IL(max) = Maximum Inductor current
In DC/DC converter applications, the efficiency is affected by the inductor AC resistance and by the inductor
DCR value.
表9-7 shows recommended inductor series from different suppliers.
表9-7. Inductor Series
DIMENSIONS
INDUCTANCE (µH)
INDUCTOR TYPE
SUPPLIER (1)
COMMENT
DCR (Ω)
(mm3)
2.2
2.2
0.300
0.170
1.6 x 0.8 x 0.8
1 .6 x 0.8 x 0.8
MDT1608CH2R2N
GLFR1608T2R2M
TOKO
TDK
Smallest size, 75mA max
Smallest size, 150mA max
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表9-7. Inductor Series (continued)
DIMENSIONS
INDUCTANCE (µH)
INDUCTOR TYPE
SUPPLIER (1)
COMMENT
DCR (Ω)
(mm3)
2.2
2.2
2.2
2.2
2.2
0.245
0.23
2.0 x 1.2 x 1.0
2.0 x 1.2 x 1.0
2.0 x 1.6 x 1.0
2.5 x 2.0 x 1.2
3.3 x 3.3 x 1.4
MDT2012CH2R2N
MIPSZ2012 2R2
74438343022
MIPSA2520 2R2
LPS3314
TOKO
TDK
Small size, high efficiency
0.225
0.12
Wurth
TDK
0.145
Coicraft
(1) See Third-Party Products Disclaimer
The PWM allows the use of small ceramic capacitors. Ceramic capacitors with low ESR values have the lowest
output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. At
light load currents, the converter operates in Power Save Mode and the output voltage ripple is dependent on
the output capacitor value and the PFM peak inductor current. Because the PWM converter has a pulsating input
current, a low ESR input capacitor is required on PMID for the best voltage filtering to ensure proper function of
the device and to minimize input voltage spikes. For most applications a 10-µF capacitor value is sufficient. The
PMID capacitor can be increased to 22 µF for better input voltage filtering.
表9-8 shows the recommended input/output capacitors.
表9-8. Capacitors
CAPACITANCE (µF)
SIZE
0603
0402
CAPACITOR TYPE
GRM188R60J106ME84
CL05A106MP5NUNC
SUPPLIER(1)
Murata
COMMENT
Recommended
Smallest size
10
10
Samsung EMA
(1) See Third-Party Products Disclaimer
9.3.22 Load Switch / LDO Output and Control
The device integrates a low Iq load switch which can also be used as a regulated output. The LSCTRL pin can
be used to turn the load on or off. Activating LSCTRL continuously holds the switch in the on state so long as
there is not a fault. The signal is active HI and has a low threshold making it capable of interfacing with low
voltage signals. To limit voltage drop or voltage transients, a small ceramic capacitor must be placed close to
VINLS. Due to the body diode of the PMOS switch, it is recommended to have the capacitor on VINLS ten times
larger than the output capacitor on LS/LDO.
The output voltage is programmable using the LS_LDO bits in the register. The LS/LDO voltage is calculated
using 方程式9.
LS/LDO = 0.8 V + LS_LDOCODE x 100 mV
(9)
If a value greater than 3.3 V is written, the setting goes to pass-through mode where LS/LDO = VINLS -
V
(DROPOUT). 表9-9 summarizes the control of the LS/LDO output based on the I2C or LSCTRL pin setting:
表9-9. LS/LDO Output Control
PIN LSCTRL
I2C LS_LDO_EN
I2C VLDO > 3.3
LS/LDO OUTPUT
Pulldown
Pulldown
VLDO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
LSW
VLDO
LSW
VLDO
LSW
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If the output of the LDO is less than the programmed V(SYS) voltage, connect VINLS to SYS. If the output of the
LDO is greater than the programmed VSYS voltage, connect VINLS to PMID.
The current capability of the LDO depends on the VINLS input voltage and the programmed output voltage. The
full 100-mA output current for 0.8-V output voltage can be achieved when V(VINLS) > 3.25 V. The full 100-mA
output current for 3.3-V output voltage can be achieved when V(VINLS) > 3.6 V.
When the LSLDO output is disabled with LSCTRL or through the register, an internal pull-down discharges the
output.
9.3.23 Manual Reset Timer and Reset Output ( MR and RESET)
The MR input has an internal pull-up to BAT, and MR is functional only when BAT is present or when VIN is valid,
stable, and charge is enabled. If MR input is asserted during a transient condition while VIN ramps up the IC
may incorrectly turn off the SYS buck output, therefore MR should not be asserted during this condition in order
to avoid unwanted shutdown of SYS output rail.The input conditions can be adjusted by using MRWAKE bits for
the wake conditions and MRRESET bits for the reset conditions. When a wake condition is met, a 128-µs pulse
is sent on INT to notify the host, and the WAKE1 and/or WAKE2 bits are updated on I2C. The MR_WAKE bits
and RESET FAULT bits are not cleared until the Push-button Control Register is read from I2C.
When a MR reset condition is met, a 128-µs pulse is sent on INT to notify the host and a RESET signal is
asserted. A reset pulse occurs with duration of tRESET_D only one time after each valid MRRESET condition. The
MR pin must be released (go high) and then driven low for the MRWAKE period before RESET asserts again.
After RESET is asserted with battery only present, the device enters either Ship mode or Hi-Z mode depending
on MRREC register settings. For details on how to properly enter Ship Mode through MR, see 节 9.3.1.1. After
RESET is asserted with a valid VIN present, the device resumes operation prior to the MR button press. If SYS
was disabled prior to RESET, the SYS output is re-enabled if recovering into Hi-Z or Active Battery.
The MRRESET_VIN register can be configured to have RESET asserted by a button press only, or by a button
press and VIN present (VUVLO + VSLP < VIN < VOVP).
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9.4 Device Functional Modes
表9-10. Modes and Functions
READY (PRIOR
HOST MODE
ACTIVE
BATTERY
FUNCTION
TO I2C) AND
READY (AFTER
CHARGE
SHIP MODE
HIGH_Z
AFTER RESET
I2C)
VOVP
VUVLO
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
No
Yes
Yes
No
Yes
Yes
VBATUVLO
Default or
registers
Default or
registers
VINDPM
SYS
If enabled
If enabled
If enabled
No
No
No
No
No
Default or
registers
Default or
registers
If enabled
If enabled
If enabled
If enabled
Default or
registers
Default or
registers
LS/LDO
BATFET
TS
Yes
Yes
Yes
Yes
No
No
Yes
No
Yes
No
Yes (VIN Valid)
Yes (VIN Valid)
Default, registers, Default, registers,
or external or external
IPRETERM
ISET
External
External
External
No
No
No
No
No
No
No
No
No
Default, registers, Default, registers,
or external or external
Default, registers, Default, registers,
ILIM
or external
or external
MR input
LSCTRL input
RESET output
INT output
I2C interface
CD input
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
No
No
No
No
No
No
No
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
Yes
PG output
Yes
Yes
If enabled
Yes
VBMON
Yes
No
No
表9-11. Fault and Status Condition Responses
CHARGER
BEHAVIOR
LS/LDO
BEHAVIOR
FAULT or STATUS
ACTIONS
SYS BEHAVIOR
TS BEHAVIOR
Update VIN_OV status,
Update STAT to fault, interrupt
on INT, PG shown not good
Enabled through
BAT
Enabled through
BAT
VIN_OV
Disabled
Disabled
Update VIN_UV status,
interrupt on INT, PG shown not
good
Enabled through
BAT
Enabled through
BAT
VIN_UV
Disabled
Disabled
Update charge in progress
status, interrupt on INT, input
current is limited
Enabled, input
current limited
VIN_ILIM
OVER_TEMP
BAT_UVLO
Enabled (if enabled) Enabled (if enabled)
Disabled Disabled
Enabled (if enabled) Enabled (if enabled)
Enabled
Disabled
Disabled
Update BAT_UVLO status,
Update STAT to fault, interrupt
on INT
Pre-charge
Enabled if VIN Valid
and VIN Valid
and VIN Valid
SW_SYS_SHORT
LS_LDO_OCP
Enabled
Enabled
Current Limit
Enabled (if enabled)
Current Limit
Enabled
Enabled
Enabled (if enabled)
Update TIMER, Update STAT
to fault, interrupt on INT
TIMER fault
Disabled
Enabled (if enabled) Enabled (if enabled)
Disabled
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表9-11. Fault and Status Condition Responses (continued)
CHARGER
BEHAVIOR
LS/LDO
BEHAVIOR
FAULT or STATUS
ACTIONS
SYS BEHAVIOR
TS BEHAVIOR
Update VINDPM_STAT,
Update STAT to fault, interrupt
on INT
Enabled, input
current reduced
VINDPM
Enabled (if enabled) Enabled (if enabled)
Enabled (if enabled) Enabled (if enabled)
Enabled
Update TS_FAULT to COLD
OR HOT, Update STAT to fault,
interrupt on INT
TS_FAULT COLD
or HOT
Disabled
Enabled
Enabled
Enabled
Enabled
Update TS_FAULT to COOL,
TS_FAULT COOL Update STAT to fault, interrupt Reduce ICHG to ½ Enabled (if enabled) Enabled (if enabled)
on INT
Update TS_FAULT to WARM,
Reduce VBATREG
TS_FAULT WARM Update STAT to fault, interrupt
on INT
Enabled (if enabled) Enabled (if enabled)
Enabled (if enabled) Enabled (if enabled)
by 140 mV
Disabled, monitor
for VBAT falling
below VRCHG
Update STAT to Charge Done,
Charge Done
interrupt on INT
yVBAT>VBAT_UVLO
yVIN<VBAT+VSLP
yCD9
HZ_MODE
/CE
RESET
yVIN_OV
yVIN_UV
yOVER_TEMP
yBAT_SHORT
yBAT_OVP
yCD;|VIN>VUVLO
HIGH_Z
Lowest quiescent current state. SYS
is powered by BAT, MR input is active,
and the LSCTRL input is active.
FAULT
READY STATE
After Reset, all default OTP settings
are used in this state.
A failure occurred. The fault event
must be cleared before going to the
previous state.
!FAULT|/CE
yTIMER
yVIN_OV
yOVER_TEMP
HZ_MODE
yCD9
yCD;|VIN<VUVLO
yTS_FAULT (HOT OR COLD)
yBAT_OVP
yVIN_OV
yTS_FAULT (HOT OR COLD)
yVBAT>VBAT_UVLO
yVIN<VBAT+VSLP
!/CE
!FAULT|
!/CE & DONE
/CE
!FAULT|!/CE
ACTIVE BATTERY
The device is powered from BAT, all
outputs and interfaces are active.
yCHARGING DONE|TE
CHARGING
The system charges the battery using
the programmed register settings,
default OTP settings, or the externally
programmed settings. Safety timers
are active in this state, unless disabled
in OTP or register settings.
DONE
The termination requirements have
been met. VBAT is monitored and
Charging resumes when conditions
are met.
yVIN>VUVLO
yVIN>VBAT+VSLP
yVBAT;
!TE
Comments about naming convention:
^//9^ }Œ ^HZ_ah59^ -> Register name: event caused by user / configuration
^!^ -> Not
^y^ -> Event caused by external influence
^Event|condition^ -> describes the event with a specific condition
图9-5. State Diagram
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ILIM
VINDPM
TS_FAULT
PRE_CHARGE
2X TIMER MODE
VALID CHARGE INPUTS
RESET
CC MODE
CV MODE
DEFAULT MODE CHARGE
ICHRG+ISW+ILDO>ILIM
ICHRG+ISW+ILDO<ILIM
No HOST or I2C is not available, ILIM,
ISET, and ITERM have resistors
populated .
ICHG≤0
PMID<VBAT-VBSUP1
DYNAMIC POWER PATH MODE
Default OTP charge settings are used if
no resistors are populated
Register settings used if changed in
I2C
BAT SUPPLEMENT MODE
BAT supplements the load at
SW/OUT and LSLDO
Charging current is reduced to supply
the load to SW/OUT and LSLDO
Battery Termination is disabled
ICHG>0
PMID<VBAT-VBSUP2
TS_FAULT (COOL)
!TS_FAULT
VBAT>VBATSHORT VBAT<VBATUVLO
VBAT>VBATUVLO + 150mV
VBAT<VBATSHORT
PRE-CHARGE MODE
TS_FAULT (WARM)
!TS_FAULT
½ CHARGE MODE
Charge current is reduced
to the Pre-charge current
level to slowly bring up the
VBAT voltage
Charging current is reduced to half the
programmed or default current
VIN>VIN_DPM
VIN ≤ VIN_DPM
BAT-SHORT MODE
Charge current is reduced to
the Bat-Short current level to
slowly bring up the VBAT
voltage
VBATREG œ 140mV MODE
VBATREG is reduced by 140mV from
the programmed or default VBATREG
VINDPM MODE
Charge current is reduced , 2X TIMER
mode is active (if enabled) and
termination is disabled
Comments about naming convention:
^//9^ }Œ ^HZ_ah59^ -> Register name: event caused by user/ configuration
^!^ -> Not
^y^ -> Event caused by external influence
^Event|condition^ -> describes the event with a specific condition
图9-6. Change State Diagram
9.5 Programming
9.5.1 Serial Interface Description
The device uses an I2C compatible interface to program and read many parameters. I2C is a 2-wire serial
interface developed by NXP. The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures.
When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C
bus through open drain I/O terminals, SDA and SCL. A master device, usually a microcontroller or digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The device works as a slave and supports the following data transfer modes, as defined in the I2C BUS
Specification: standard mode (100 kbps) and fast mode (400kbps). The interface adds flexibility to the battery
management solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. The I2C circuitry is powered from the battery in active battery mode. The
battery voltage must stay above V(BATUVLO) when no VIN is present to maintain proper operation. The host must
also wait for SYS to come up before starting communication with the part.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The device only supports 7-bit addressing. The device 7-bit address is 6A (8-bit
shifted address is D4).
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To avoid I2C hang-ups, a timer (tI2CRESET) runs during I2C transactions. If the SDA line is held low longer than
tI2CRESET, any additional commands are ignored and the I2C engine is reset. The timeout is reset with START
and repeated START conditions and stops when a valid STOP condition is sent.
9.5.2 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in 图 9-7. All I2C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
图9-7. Start Stop Condition
The master then generates the SCL pulses, and transmits the address and the read/write direction bit R/W on
the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the
SDA line to be stable during the entire high period of the clock pulse (see 图 9-8). All devices recognize the
address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates and acknowledge (see 图 9-9) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting the acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
图9-8. Bit Transfer on the Serial Interface
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
8
SCL From
Master
9
1
2
Clock Pulse for
Acknowledgement
START
Condition
图9-9. Acknowledge on the I2C Bus
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The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the
slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An
acknowledge signal can either be generated by the master or by the slave, depending on which on is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see 图9-10). This releases the bus and stops the communication link
with the addressed slave. All I2C compatible devices must recognize the STOP condition. Upon the receipt of a
STOP condition, all devices know that the bus is released, and wait for a START condition followed by a
matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to
prevent the slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses
not listed in this section results in 0xFFh being read out.
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgement
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
or
Sr
or
P
ACK
ACK
Sr
图9-10. Bus Protocol
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9.6 Register Maps
9.6.1 Status and Ship Mode Control Register
Memory location 0x00h, Reset State: xx0x xxx1 (BQ25121A)
图9-11. Status and Ship Mode Control Register
7 (MSB)
6
x
5
4
3
2
1
x
0 (LSB)
x
0
x
x
x
1
R
R
Write Only
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-12. Status and Ship Mode Control Register
Bit
Field
Type
Reset
Description
B7 (MSB) STAT_1
R
x
x
00 –Ready
01 –Charge in Progress
10 –Charge done
11 –Fault
B6
STAT_0
R
Status is current status only.
B5
B4
B3
B2
B1
EN_SHIPMODE
RESET_FAULT
TIMER
Write
Only
0
x
x
x
x
x
0 –Normal Operation
1 –Ship Mode Enabled
R
R
R
R
R
1 –RESET fault. Indicates when the device meets the RESET
conditions, and is cleared after I2C read.
1 –Safety timer fault. Continues to show fault after an I2C read
unless the CD pin or power have been toggled.
VINDPM_STAT
CD_STAT
0 –VIN_DPM is not active
1 –VIN_DPM is active
0 –CD low, IC enabled
1 –CD high, IC disabled
B0 (LSB) SYS_EN_STAT
1 –SW enabled
0 –SW disabled
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9.6.2 Faults and Faults Mask Register
Memory location 0x01h, Reset State: xxxx 0000 (BQ25121A)
图9-12. Faults and Faults Mask Register
7 (MSB)
6
x
5
4
3
2
1
0
0 (LSB)
0
x
x
x
0
0
R
R
R
R
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-13. Faults and Faults Mask Register
Bit
Field
Type
Reset
Description
B7 (MSB) VIN_OV
R
x
1 –VIN overvoltage fault. VIN_OV continues to show fault after
an I2C read as long as OV exists
B6
B5
VIN_UV
R
R
x
x
1 –VIN undervoltage fault. VIN_UV is set when the input falls
below V(UVLO) - VUVLO(HYS). VIN_UV fault shows only one time.
Once read, VIN_UV clears until another UVLO event occurs.
BAT_UVLO
1 –BAT_UVLO fault. BAT_UVLO continues to show fault after
an I2C read as long as BAT_UVLO conditions exist.
1 –BAT_OCP fault. BAT_OCP is cleared after I2C read.
1 –Mask VIN overvoltage fault
B4
B3
B2
B1
BAT_OCP
R
x
0
0
0
0
VIN_OV_M
VIN_UV_M
BAT_UVLO_M
R/W
R/W
R/W
R/W
1 –Mask VIN undervoltage fault
1 –Mask BAT UVLO fault
B0 (LSB) BAT_OCP_M
1 –Mask BAT_OCP fault
If a fault is read on the status register and it is neither of any of the faults in this register or subsequent registers, it indicates an ILIM fault.
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9.6.3 TS Control and Faults Masks Register
Memory location 0x02h, Reset State: 1xxx 1000 (BQ25121A)
图9-13. TS Control and Faults Masks Register (02)
7 (MSB)
1
6
x
5
4
3
2
1
0
0 (LSB)
0
x
x
1
0
R/W
R
R
R
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-14. TS Control and Faults Masks Register, Memory Location 0010
Bit
Field
Type
Reset
Description
B7 (MSB) TS_EN
R/W
1
0 –TS function disabled
1 –TS function enabled
B6
B5
TS_FAULT1
R
R
x
x
TS Fault mode:
00 –Normal, No TS fault
01 –TS temp < TCOLD or TS temp > THOT (Charging
TS_FAULT0
suspended)
10 –TCOOL > TS temp > TCOLD (Charging current reduced by
half)
11 –TWARM < TS temp < THOT (Charging voltage reduced by
140 mV)
B4
B3
Reserved
EN_INT
R
x
Reserved
R/W
1
0 –Disable INT function (INT only shows faults and does not
show charge status)
1 –Enable INT function (INT shows faults and charge status)
B2
B1
WAKE_M
RESET_M
R/W
R/W
0
0
1 –Mask interrupt from Wake Condition from MR
1 –Mask RESET interrupt from MR . The RESET output is not
masked by this bit.
B0 (LSB) TIMER_M
R/W
0
1 –Mask Timer fault interrupt (safety)
To save power, the device will shut off the clock that counts the deglitch time for the faults in the Hi-Z mode. For any of the fault conditions
that contain a deglitch time as specified in the 节8.5, the device will have to be in Active BAT with an I2C transaction or VIN present to
count against the deglitch to clear the fault on the register.
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9.6.4 Fast Charge Control Register
Memory location 0x03h, Reset State: 1000 0000 (BQ25121A)
图9-14. Fast Charge Control Register
7 (MSB)
0
6
0
5
0
4
3
2
1
1
0
0 (LSB)
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-15. Fast Charge Control Register
Bit
Field
Type
Reset
Description
B7 (MSB) ICHRG_RANGE
R/W
0
0 –to select charge range from 5 mA to 35 mA, ICHRG bits are
1-mA steps
1 –to select charge range from 40 mA to 300 mA, ICHRG bits
are 10-mA steps
B6
B5
B4
B3
B2
B1
ICHRG_4
ICHRG_3
ICHRG_2
ICHRG_1
ICHRG_0
CE
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
1
0
Charge current 16 mA or 160 mA
Charge current 8 mA or 80 mA
Charge current 4 mA or 40 mA
Charge current 2 mA or 20 mA
Charge current 1 mA or 10 mA
0 –Charger enabled
1 –Charger is disabled
B0 (LSB) HZ_MODE
R/W
0
0 –Not high impedance mode
1 –High impedance mode
ICHRG_RANGE and ICHRG bits are used to set the charge current. The ICHRG is calculated using the following equation: If
ICHRG_RANGE is 0, then ICHRG = 5 mA + ICHRGCODE x 1 mA. If ICHRG_RANGE is 1, then ICHRG = 40 mA + ICHRGCODE x 10 mA. If a
value greater than 35 mA (ICHRG_RANGE = 0) or 300 mA (ICHRG_RANGE = 1) is written, the setting goes to 35 mA or 300 mA
respectively except if the ICHRG bits are all 1 (that is, 11111), then the externally programmed value is used. The PRETERM bits must also
be set prior to writing all 1s to ensure the external ISET current is used as well as the proper termination and pre-charge values are used.
For IPRETERM = 5%, set the IPRETERM bits to 000001, for IPRETERM = 10%, set the IPRETERM bits to 000010, for IPRETERM = 15%,
set the IPRETERM bits to 000100, and for IPRETERM = 20%, set the iPRETERM bits to 001000. The default may be overridden by the
external resistor on ISET.
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9.6.5 Termination/Pre-Charge Register
Memory location 0x04h, Reset State: 0001 0000 (BQ25121A)
图9-15. Termination/Pre-Charge Register
7 (MSB)
0
6
0
5
4
3
2
1
1
0 (LSB)
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-16. Termination/Pre-Charge Register
Bit
Field
Type
Reset
Description
B7 (MSB) IPRETERM_RANGE
R/W
0
0 –to select termination range from 500 µA to 5 mA,
IPRETERM bits are 500-µA steps
1 –to select charge range from 6 mA to 37 mA, IPRETERM
bits are 1-mA steps
B6
B5
B4
B3
B2
B1
IPRETERM_4
IPRETERM_3
IPRETERM_2
IPRETERM_1
IPRETERM_0
TE
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
1
1
Termination current 8 mA or 16 mA
Termination current 4 mA or 8 mA
Termination current 2 mA or 4 mA
Termination current 1 mA or 2 mA
Termination current 500 µA or 1 mA
0 –Disable charge current termination
1 –Enable charge current termination
B0 (LSB)
R/W
0
IPRETERM_RANGE and IPRETERM bits are used to set the termination and pre-charge current. The ITERM is calculated using the
following equation: If IPRETERM_RANGE is 0, then ITERM = 500 µA + ITERMCODE x 500 µA. If IPRETERM_RANGE is 1, then ITERM = 6
mA + ITERMCODE x 1 mA. If a value greater than 5 mA (IPRETERM_RANGE = 0) is written, the setting goes to 5 mA. Termination is
disabled if any loop other than CC or DV in control, such as VINDPM, and TS/Cool. The default may be overridden by the external resistor
on IPRETERM.
9.6.6 Battery Voltage Control Register
Memory location 0x05h, Reset State: 0111 1000 (BQ25121A)
图9-16. Battery Voltage Control Register
7 (MSB)
0
6
1
5
1
4
1
3
1
2
0
1
0
0 (LSB)
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-17. Battery Voltage Control Register
Bit
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
B7 (MSB) VBREG_6
0
1
1
1
1
0
0
0
Battery Regulation Voltage: 640 mV
Battery Regulation Voltage: 320 mV
Battery Regulation Voltage: 160 mV
Battery Regulation Voltage: 80 mV
Battery Regulation Voltage: 40 mV
Battery Regulation Voltage: 20 mV
Battery Regulation Voltage: 10 mV
B6
B5
VBREG_5
VBREG_4
VBREG_3
VBREG_2
VBREG_1
VBREG_0
B4
B3
B2
B1
B0 (LSB)
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表9-17. Battery Voltage Control Register (continued)
Bit
Field
Type
Reset
Description
VBREG Bits: Use VBREG bits to set the battery regulation threshold. The VBATREG is calculated using the following equation: VBATREG = 3.6
V + VBREGCODE x 10 mV. The charge voltage range is from 3.6 V to 4.65 V. If a value greater than 4.65 V is written, the setting goes to
4.65 V.
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9.6.7 SYS VOUT Control Register
Memory location 0x06h, Reset State: 1011 1000 (BQ25121A)
图9-17. SYS VOUT Control Register
7 (MSB)
1
6
0
5
1
4
3
2
0
1
0
0 (LSB)
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-18. SYS VOUT Control Register
Bit
Field
Type
Reset
Description
B7 (MSB) EN_SYS_OUT
R/W
1
0 –Disable SW
1 –Enable SW
(When disabled, output is pulled low)
B6
B5
SYS_SEL1
SYS_SEL0
R/W
R/W
0
1
00 –1.1 V and 1.2 V selection
01 –1.3 V through 2.8 V selection
10 –1.5V through 2.75 V selection
11 –1.8 V through 3.3 V selection
B4
B3
SYS_VOUT_3
SYS_VOUT_2
SYS_VOUT_1
SYS_VOUT_0
R/W
R/W
R/W
R/W
1
1
0
0
0
OUT Voltage: 800 mV step if SYS_SEL is 01 or 11
OUT Voltage: 400 mV step if SYS_SEL is 01 or 11
OUT Voltage: 200 mV step if SYS_SEL is 01 or 11
OUT Voltage: 100 mV step if SYS_SEL is 01 or 11
B2
B1
B0 (LSB)
SW_VOUT Bits: Use SYS_SEL and SYS_VOUT bits to set the output on SYS. The SYS voltage is calculated using the following equation:
See table below for all VOUT values that can be programmed through SYS_SEL and SYS_VOUT.
If SYS_SEL = 01, then SYS = 1.30 V + SYS_VOUTCODE x 100 mV.
If SYS_SEL = 11, then SYS = 1.80 V + SYS_VOUTCODE x 100 mV.
表9-19. SYS_SEL Codes
SYS_SEL
00
SYS_VOUT
0000
0001
0010
0011
0100
0101
0110
0111
TYP
UNIT
V
1.1
00
1.2
V
00
1.25
1.333
1.417
1.5
V
00
V
00
V
00
V
00
1.583
1.667
1.75
1.833
1.917
2
V
00
V
00
1000
1001
1010
1011
1100
1101
1110
V
00
V
00
V
00
V
00
2.083
2.167
2.25
2.333
1.3
V
00
V
00
V
00
1111
V
01
0000
0001
0010
V
01
1.4
V
01
1.5
V
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表9-19. SYS_SEL Codes (continued)
SYS_SEL
01
01
01
01
01
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
11
SYS_VOUT
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TYP
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1.5
1.583
1.667
1.75
1.833
1.917
2
2.083
2.167
2.25
2.333
2.417
2.5
2.583
2.667
2.75
1.8
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
11
1.9
11
2
11
2.1
11
2.2
11
2.3
11
2.4
11
2.5
11
2.6
11
2.7
11
2.8
11
2.9
11
3
11
3.1
11
3.2
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表9-19. SYS_SEL Codes (continued)
SYS_SEL
SYS_VOUT
TYP
UNIT
11
1111
3.3
V
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9.6.8 Load Switch and LDO Control Register
Memory location 0x07h, Reset State: 0010 1100 (BQ25121A )
图9-18. Load Switch and LDO Control Register
7 (MSB)
R/W
6
1
5
4
3
2
1
0
0 (LSB)
1
1
1
1
x
R/W
R/W
R/W
R/W
R/W
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-20. Load Switch and LDO Control Register
Bit
Field
Type
Reset
Description
B7 (MSB) EN_LS_LDO
R/W
0
0 –Disable LS/LDO
1 –Enable LS/LDO
B6
B5
B4
B3
B2
B1
LS_LDO_4
LS_LDO_3
LS_LDO_2
LS_LDO_1
LS_LDO_0
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
0
x
LS/LDO Voltage: 1600 mV
LS/LDO Voltage: 800 mV
LS/LDO Voltage: 400 mV
LS/LDO Voltage: 200 mV
LS/LDO Voltage: 100 mV
B0 (LSB) MRRESET_VIN
R/W
0 –Reset sent when MR Reset time is met
1 –Reset sent when MR Reset time is met and VUVLO + VSLP
<
VIN < VOVP
LS_LDO Bits: Use LS_LDO bits to set the LS/LDO output. The LS/LDO voltage is calculated using the following equation: LS/LDO = 0.8 V
+ LS_LDOCODE x 100 mV. If a value greater than 3.3 V is written, the setting goes to pass-through mode where LS/LDO = VINLS -
VDROPOUT. The LS_LDO output can only be changed when the EN_LS_LDO and LSCTRL pin has disabled the output.
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9.6.9 Push-button Control Register
Memory location 0x08h, Reset State: 0010 10xx (BQ25121A)
图9-19. Push-button Control Register
7 (MSB)
0
6
1
5
1
4
3
2
0
1
x
0 (LSB)
0
1
x
R/W
R/W
R/W
R/W
R/W
R/W
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-21. Push-button Control Register
Bit
Field
Type
Reset
Description
B7 (MSB) MRWAKE1
R/W
0
MR Timer adjustment for WAKE1:
0 –80 ms < MR
1 –600 ms < MR
B6
B5
MRWAKE2
MRREC
R/W
R/W
1
1
MR Timer adjustment for WAKE2:
0 –1000 ms < MR
1 –1500 ms < MR
0 –After Reset, device enters Ship mode
1 –After Reset, device enters Hi-Z Mode
B4
B3
MRRESET_1
MRRESET_0
R/W
R/W
0
1
MR Timer adjustment for reset:
00 –5 s ± 20%
01 –9 s ± 20%
10 –11 s ± 20%
11 –15 s ± 20%
B2
B1
PGB_MR
WAKE1
R/W
R
0
x
x
0 –Output functions as PG
1 –Output functions as voltage shifted push-button ( MR) input
1 –WAKE1 status. Indicates when the device meets the
WAKE1 conditions, and is cleared after I2C read.
B0 (LSB) WAKE2
R
1 –WAKE2 status. Indicates when the device meets the
WAKE2 conditions, and is cleared after I2C read.
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9.6.10 ILIM and Battery UVLO Control Register
Memory location 0x09h, Reset State: 0010 1010 (BQ25121A)
图9-20. ILIM and Battery UVLO Control Register
7 (MSB)
0
6
0
5
4
3
2
1
1
0 (LSB)
0
0
0
1
0
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-22. ILIM and Battery UVLO Control Register, Memory Location 1001
Bit
Field
Type
Reset
Description
B7 (MSB) RESET
Write
only
0
Write:
1 –Reset all registers to default values
0 –No effect
Read: Always get 0
B6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
0
1
0
N/A
B5
B4
B3
B2
B1
INLIM_2
INLIM_1
INLIM_0
BUVLO_2
BUVLO_1
Input Current Limit: 200 mA
Input Current Limit: 100 mA
Input Current Limit: 50 mA
000, 001 –RESERVED
010 –BUVLO = 3.0 V
011 –BUVLO = 2.8 V
100 –BUVLO = 2.6 V
101 –BULVO = 2.4 V
110 –BUVLO = 2.2 V
111 –BUVLO = 2.2V
B0 (LSB) BUVLO_0
INLIM Bits: Use INLIM bits to set the input current limit. The I(INLIM) is calculated using the following equation: I(INLIM) = 50 mA +
I(INLIM)CODE x 50 mA. The default may be overridden by the external resistor on ILIM.
9.6.11 Voltage Based Battery Monitor Register
Memory location 0x0Ah, Reset State: 0xxx xxxx (BQ25121A)
图9-21. Voltage Based Battery Monitor Register
7 (MSB)
6
5
4
3
2
1
x
0 (LSB)
0
x
x
x
x
x
x
R/W
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-23. Voltage Based Battery Monitor Register, Memory Location 1010
Bit
Field
Type
R/W
R
Reset
Description
B7 (MSB) VBMON_READ
0
x
x
Write 1 to initiate a new VBATREG reading. Read always 0.
B6
B5
VBMON_RANGE_1
VBMON_RANGE_0
11 –90% to 100% of VBATREG
10 –80% to 90% of VBATREG
01 –70% to 80% of VBATREG
00 –60% to 70% of VBATREG
R
B4
B3
B2
VBMON_TH_2
VBMON_TH_1
VBMON_TH_0
R
R
R
x
x
x
111 –Above 8% of VBMON_RANGE
110 –Above 6% of VBMON_RANGE
011 –Above 4% of VBMON_RANGE
010 –Above 2% of VBMON_RANGE
001 –Above 0% of VBMON_RANGE
B1
R
R
x
x
N/A
N/A
B0 (LSB)
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表9-23. Voltage Based Battery Monitor Register, Memory Location 1010 (continued)
Bit
Field
Type
Reset
Description
The VBMON registers are used to determine the battery voltage. Before entering a low power state, the device will determine the voltage
level by starting at VBMON_RANGE 11 (90% to 100%), and if VBMON_TH of 000 is read, then it will move to VBMON_RANGE 10 (80% to
90%) and continue until a non 000 value of VBMON_TH is found. If this does not happen, then VBMON_RANGE and VBMON_TH will be
written with 00 000. The VBMON_READ bit can be used to initiate a new reading by writing a 1 to it. Example: A reading of 10 011
indicated a VBAT voltage of between 84% and 86% of the VBATREG setting.
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9.6.12 VIN_DPM and Timers Register
Memory location 0x0Bh, Reset State: 0100 0010 (BQ25121A)
图9-22. VIN_DPM and Timers Register
7 (MSB)
0
6
1
5
0
4
3
2
0
1
1
0 (LSB)
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-24. VIN_DPM and Timers Register
Bit
Field
Type
Reset
Description
B7 (MSB) VINDPM_ON
R/W
0
0 –enable VINDPM
1 –disable VINDPM
B6
B5
B4
B3
VINDPM_2
VINDPM_1
VINDPM_0
2XTMR_EN
R/W
R/W
R/W
R/W
1
0
0
0
Input V(IN_DPM) voltage: 400 mV
Input V(IN_DPM) voltage: 200 mV
Input V(IN_DPM) voltage: 100 mV
0 –Timer is not slowed at any time
1 –Timer is slowed by 2x when in any control other than CC or
CV
B2
B1
TMR_1
TMR_0
R/W
R/W
0
1
Safety Timer Time Limit
00 –30 minute fast charge
01 –3 hour fast charge
10 –9 hour fast charge
11 –Disable safety timers
B0 (LSB)
0
The VINDPM threshold is set using the following equation: VINDPM = 4.2 + VINDPM_CODE x 100 mV
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
10.1 Application Information
A typical design is shown in 图 10-1. This design uses the BQ25121A with external resistors for ILIM,
IPRETERM, and ISET. These are not needed if these values are set with a host controller through I2C
commands. This design also shows the TS resistors, which is also optional.
When powering up in default mode the battery voltage is the default for the part (4.2 V), the SYS output is the
default (2.5 V). External resistors set the charge current to 40 mA, the termination current to 10% (4 mA), and
the input current limit to 100 mA. If the I2C interface is used the part goes to the internal default settings until
changed by the host.
10.2 Typical Application
`
Unregulated
Load
PG
IN
PMID
4.7 µF
1 µF
VINLS
GND
SYS
SW
2.2 µH
MCU /
SYSTEM
CD
10 µF
SDA
SCL
LS / LDO
<100mA
Load
HOST
INT
1 µF
RESET
LSCTRL
BAT
MR
1 µF
IPRETERM
ISET
14.3 kΩ
NTC
TS
ILIM
14 kΩ
4.99 kΩ
499 Ω
BQ25121A
IN
4 kΩ
图10-1. Typical Application Circuit
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10.2.1 Design Requirements
This application is for a low power system that has varying loads from less than 10 mA up to 300 mA. It must
work with a valid adaptor or USB power input. Below are some of the key components that are needed in normal
operation. For this example, the fast charge current is 50 mA, input current limit is 400 mA and the pre-charge
and termination current is 10% of the fast charge current.
• Supply voltage = 3.4 V to 20 V
• Fast charge current is default to 10 mA with ISET pin shorted to ground. To program the fast charge current,
connect an external resistor from ISET to ground.
• Input current limit is default to 100 mA with ILIM pin shorted to ground. To program the input current limit,
connect an external resistor from ILIM to ground.
• Termination current threshold is default to 2 mA with IPRETERM pin shorted to ground. To program the input
current limit, connect an external resistor from IPRETERM to ground.
• A 2.2-µH inductor is needed between SW pin and SYS pin for PWM output.
• TS- Battery temperature sense needs a NTC connected on TS pin.
10.2.2 Detailed Design Procedure
See 图10-1 for an example of the application diagram.
10.2.2.1 Default Settings
• Connect ISET, ILIM and IPRETERM pins to ground to program fast charge current to 10 mA, input current
limit to 100 mA and pre-charge/termination current to 2 mA.
• BAT_UVLO = 3 V
• VSYS = 2.5 V
• LS/LDO is LS
• VBREG = 4.2 V
• VIN_DPM is enabled and VIN_DPM threshold = 4.6 V
• Safety Timer = 3 hr
• If the function is not needed, connect TS to the center tab of the resistor divider between VIN and the ground
(pullup resistor = 14 kΩ, pulldown resistor = 14.3 kΩ).
10.2.2.2 Choose the Correct Inductance and Capacitance
Refer to 节 9.3.21 for the detailed procedure to determine the optimal inductance and capacitance for the buck
output.
10.2.2.3 Calculations
10.2.2.3.1 Program the Fast Charge Current (ISET)
RISET = KISET/ICHG
(10)
(11)
KISET = 200 AΩ from the 节8 table
RISET = 200 AΩ / 0.05 A = 4 kΩ
Select the closest standard value, which in this case is 4.99 kΩ. Connect this resistor between ISET pin and
GND.
10.2.2.3.2 Program the Input Current Limit (ILIM)
RILIM = KILIM/II_MAX
(12)
(13)
KILIM = 200 AΩ from the 节8 table
RILIM = 200 AΩ / 0.4 A = 500 Ω
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Select the closest standard value, which in this case is 499 Ω. Connect this resistor between ILIM pin and GND.
10.2.2.3.3 Program the Pre-charge/termination Threshold (IPRETERM)
According to 表 9-3, the RIPRETERM is 4990 Ω for 10% termination threshold. Therefore, connect a 4.99-kΩ
resistor between IPRETERM pin and GND.
10.2.2.3.4 TS Resistors (TS)
The voltage at TS is monitored to determine that the battery is at a safe temperature during charging.This device
uses JEITA temperature profile which has four temperature thresholds. Refer to 节 8 for the detailed thresholds
number.
The TS circuit is shown in 图9-4. The resistor values can be calculated using 方程式1 and 方程式2.
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10.2.3 Application Performance Curves
10.2.3.1 Charger Curves
Time 100 ms/div
Time 4 ms/div
图10-3. Power Supply Connected to VIN
图10-2. Battery Connected to V(BAT)
Time 4 ms/div
Time 4 ms/div
图10-5. Exiting DPPM Mode
图10-4. Entering DPPM Mode
Time 4 ms/div
Time 4 ms/div
图10-6. Entering Battery Supplement Mode
图10-7. Exiting Battery Supplement Mode
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Time 2 ms/div
Time 4 ms/div
图10-8. Charger On/Off Using CD
图10-9. OVP Fault
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10.2.3.2 SYS Output Curves
100%
90%
80%
70%
60%
50%
40%
100%
90%
80%
70%
60%
50%
40%
2.7 V BAT
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
2.7 V BAT
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
1E-6
1E-5
0.0001 0.001
Load Current (A)
0.01
0.10.2 0.5
1E-6
1E-5
0.0001 0.001
Load Current (A)
0.01
0.10.2 0.5
D004
D001
TA = 25°C
VSYS = 1.5 V
TA = 25°C
VSYS = 1.2 V
图10-11. 1.5 VSYS System Efficiency
图10-10. 1.2 VSYS System Efficiency
100%
100%
90%
80%
70%
60%
50%
40%
90%
80%
70%
60%
50%
40%
2.7 V BAT
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
1E-6
1E-5
0.0001 0.001
Load Current (A)
0.01
0.10.2 0.5
1E-6
1E-5
0.0001 0.001
Load Current (A)
0.01
0.10.2 0.5
D007
D010
TA = 25°C
VSYS = 1.8 V
TA = 25°C
VSYS = 2.5 V
图10-12. 1.8 VSYS System Efficiency
图10-13. 2.5 VSYS System Efficiency
100%
1.238
1.228
1.218
1.208
1.198
1.188
1.178
1.168
1.158
90%
80%
70%
60%
50%
40%
2.7 V
3 V
3.6 V
3.8 V
4.2 V
3.6 V BAT
3.8 V BAT
4.2 V BAT
1E-6
1E-5
0.0001 0.001
Load Current (A)
0.01
0.1
0.5
1E-6
1E-5
0.0001 0.001
Load Current (A)
0.01
0.10.2 0.5
D003
D013
TA = 25°C
VSYS = 1.2 V
TA = 25°C
VSYS = 3.3 V
图10-15. 1.2 VSYS Load Regulation
图10-14. 3.3 VSYS System Efficiency
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1.5475
1.5275
1.5075
1.4875
1.857
1.837
1.817
1.797
1.777
1.757
1.737
2.7 V BAT
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
2.7 V BAT
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
1.4675
1.4475
1E-6
1E-5
0.0001 0.001
Load Current (A)
0.01
0.1
0.5
1E-6
1E-5
0.0001 0.001
Load Current (A)
0.01
0.1
0.5
D006
D009
TA = 25°C
VSYS = 1.5 V
TA = 25°C
VSYS = 1.8 V
图10-16. 1.5 VSYS Load Regulation
图10-17. 1.8 VSYS Load Regulation
2.5725
3.3845
3.3345
3.2845
3.2345
3.1845
2.5525
2.5325
2.5125
2.4925
2.4725
2.4525
2.4325
2.4125
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
3.8 V BAT
4.2 V BAT
1E-6
1E-5
0.0001 0.001
Load Current (A)
0.01
0.1
0.5
1E-6
1E-5
0.0001 0.001
Load Current (A)
0.01
0.1
0.5
D012
D015
TA = 25°C
VSYS = 2.5 V
TA = 25°C
VSYS = 3.3 V
图10-18. 2.5 VSYS Load Regulation
图10-19. 3.3 VSYS Load Regulation
1.238
1.228
1.218
1.208
1.198
1.188
1.178
1.168
1.158
1.5475
1 PA
1 mA
10 mA
1 PA
1 mA
10 mA
100 mA
10 PA
100 PA
10 PA
100 PA
100 mA
1.5275
1.5075
1.4875
1.4675
1.4475
4
3
3.2
3.4
3.6
VBAT Voltage (V)
3.8
4.2
3
3.2
3.4
3.6
VBAT Voltage (V)
3.8
4
4.2
D005
D002
TA = 25°C
VSYS = 1.5 V
TA = 25°C
VSYS = 1.2 V
图10-21. 1.5 VSYS Line Regulation
图10-20. 1.2 VSYS Line Regulation
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1.857
2.5725
2.5525
2.5325
2.5125
2.4925
2.4725
2.4525
2.4325
2.4125
1.837
1.817
1.797
1.777
1.757
1 PA
1 mA
10 mA
100 mA
10 PA
100 PA
1 PA
10 PA
100 PA
1 mA
10 mA
100 mA
300ma
1.737
3
3
3.2
3.4
3.6
VBAT Voltage (V)
3.8
4
4.2
4
3.2
3.4
3.6
VBAT Voltage (V)
3.8
4.2
D011
D008
TA = 25°C
VSYS = 2.1 V
TA = 25°C
VSYS = 1.8 V
图10-23. 2.1 VSYS Line Regulation
图10-22. 1.8 VSYS Line Regulation
3.3845
1400
1200
1000
800
600
400
200
0
3.3345
3.2845
3.2345
3.1845
1 PA
1 mA
10 mA
100 mA
10 PA
100 PA
5 V VBAT
4.2 V VBAT
3.6 V VBAT
3 V VBAT
2.5 V VBAT
3.8
4
VBAT Voltage (V)
4.2
0
50
100
150
Load Current (mA)
200
250
300
D014
D023
TA = 25°C
VSYS = 3.3 V
图10-25. 1.8 VSYS Switching Frequency vs Load
图10-24. 3.3 VSYS Line Regulation
Current
SW
SW
Time 40 ms/div
Time 40 ms/div
ILOAD = 10 µA
ILOAD = 100 mA
图10-26. Light Load Operation Showing SW
图10-27. Light Load Operation Showing SW
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SW
SW
Time 40 ms/div
Time 2 ms/div
ILOAD = 1 mA
ILOAD = 10 mA
图10-28. Light Load Operation Showing SW
图10-29. Light Load Operation Showing SW
SW
SW
Time 400 ns/div
Time 400 ns/div
ILOAD = 100 mA
ILOAD = 200 mA
图10-30. Light Load Operation Showing SW
图10-31. Light Load Operation Showing SW
SW
SW
Time 400 ns/div
Time 4 ms/div
ILOAD = 300 mA
VSYS = 1.2 V
图10-32. Light Load Operation Showing SW
图10-33. 1.2 VSYS Load Transient, 0 to 50 mA
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SW
SW
Time 4 ms/div
Time 4 ms/div
VSYS = 1.8 V
VSYS = 2.1 V
图10-34. 1.8 VSYS Load Transient, 0 to 50 mA
图10-35. 2.1 VSYS Load Transient, 0 to 50 mA
SW
SW
Time 4 ms/div
Time 4 ms/div
VSYS = 2.5 V
VSYS = 3.3 V
图10-36. 2.5 VSYS Load Transient, 0 to 50 mA
图10-37. 3.3 VSYS Load Transient, 0 to 50 mA
SW
SW
Time 4 ms/div
Time 4 ms/div
VSYS = 1.2 V
VSYS = 1.8 V
图10-38. 1.2 VSYS Load Transient, 0 to 200 mA
图10-39. 1.8 VSYS Load Transient, 0 to 200 mA
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SW
SW
Time 4 ms/div
Time 4 ms/div
VSYS = 2.1 V
VSYS = 2.5 V
图10-40. 2.1 VSYS Load Transient, 0 to 200 mA
图10-41. 2.5 VSYS Load Transient, 0 to 200 mA
SW
Time 4 ms/div
Time 1 ms/div
图10-43. Startup Showing SS on SYS in PWM
Mode
VSYS = 3.3 V
图10-42. 3.3 VSYS Load Transient, 0 to 200 mA
Time 20 ms/div
图10-44. Short Circuit and Recovery for SYS
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10.2.3.3 Load Switch and LDO Curves
Time 20 ms/div
Time 400 ms/div
图10-45. Short Circuit and Recovery for LS
图10-46. Startup Showing SS on LS/LDO Output
Time 4 ms/div
Time 4 ms/div
VSLSDO = 0.8 V
VSLSDO = 1.2 V
图10-47. 0.8 VLSLDO Load Transient, 0 to 10 mA
图10-48. 1.2 VLSLDO Load Transient, 0 to 10 mA
Time 4 ms/div
Time 4 ms/div
VSLSDO = 1.8 V
VSLSDO = 2.5 V
图10-49. 1.8 VLSLDO Load Transient, 0 to 10 mA
图10-50. 2.5 VLSLDO Load Transient, 0 to 10 mA
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Time 4 ms/div
Time 4 ms/div
VSLSDO = 3.3 V
VSLSDO = 0.8 V
图10-51. 3.3 VLSLDO Load Transient, 0 to 10 mA
图10-52. 0.8 VLSLDO Load Transient, 0 to 100 mA
Time 4 ms/div
Time 4 ms/div
VSLSDO = 1.8 V
VSLSDO = 1.2 V
图10-54. 1.8 VLSLDO Load Transient, 0 to 100 mA
图10-53. 1.2 VLSLDO Load Transient, 0 to 100 mA
Time 4 ms/div
Time 4 ms/div
VSLSDO = 2.5 V
VSLSDO = 3.3 V
图10-55. 2.5 VLSLDO Load Transient, 0 to 100 mA
图10-56. 3.3 VLSLDO Load Transient, 0 to 100 mA
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10.2.3.4 LS/LDO Output Curves
Time 400 ms/div
Time 20 ms/div
图10-58. Short Circuit and Recovery for LDO
图10-57. Startup Showing SS on LS/LDO in LDO
Mode
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10.2.3.5 Timing Waveforms Curves
Time 10 ms/div
Time 2 ms/div
图10-59. Show PG and INT Timing (VIN Insertion)
图10-60. Show PG and INT Timing (VIN Removal)
Time 400 ms/div
Time 400 ms/div
图10-61. PG Functions as Shifted MR Output
图10-62. PG Functions as Shifted MR Output
Time 200 ms/div
Time 200 ms/div
Wake1 = 500 ms
Wake2 = 1 s
Wake1 = 50 ms
Wake2 = 1.5 s
图10-63. Show MR Timing
图10-64. Show MR Timing
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Time 1 s/div
Time 1 s/div
RESET = 4 s
RESET = 8 s
图10-65. RESET Timing
图10-66. RESET Timing
Time 2 s/div
Time 2 s/div
RESET = 14 s
图10-68. RESET Timing and Enter Ship Mode
图10-67. RESET Timing
11 Power Supply Recommendations
It is recommended to use a power supply that is capable of delivering 5 V at the input current limit set by the
BQ25121A.
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12 Layout
12.1 Layout Guidelines
• Keep the core components of the system close to each other and the device.
• Keep the PMID, IN, and SYS caps as close to their respective pins as possible. Place the bypass caps for
PMID, SYS, and LSLDO close to the pins.
• Place the GNDs of the PMID and IN caps close to each other.
• Don’t route so the power planes are interrupted.
12.2 Layout Example
图12-1. BQ25121A Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.3 Trademarks
DCS-Control™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
13.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25121AYFPR
BQ25121AYFPT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFP
YFP
25
25
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
BQ25121A
BQ25121A
Samples
Samples
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-May-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25121AYFPR
BQ25121AYFPT
DSBGA
DSBGA
YFP
YFP
25
25
3000
250
180.0
180.0
8.4
8.4
2.65
2.65
2.65
2.65
0.69
0.69
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ25121AYFPR
BQ25121AYFPT
DSBGA
DSBGA
YFP
YFP
25
25
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFP0025
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
0.30
0.25
C
0.5 MAX
SEATING PLANE
0.05 C
0.19
0.13
1.6 TYP
SYMM
E
D
C
SYMM
1.6
TYP
D: Max = 2.56 mm, Min = 2.5 mm
E: Max = 2.498 mm, Min =2.438 mm
B
0.4 TYP
A
3
4
5
2
1
0.25
25X
0.21
0.4 TYP
0.015
C A B
4225306/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YFP0025
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
25X ( 0.23)
(0.4) TYP
3
4
5
1
2
A
B
C
SYMM
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 40X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
(
0.23)
METAL
(
0.23)
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225306/A 09/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFP0025
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
3
25X ( 0.25)
4
5
1
2
A
(0.4) TYP
B
C
METAL
TYP
SYMM
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 40X
4225306/A 09/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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