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bq24260, bq24261, bq24261M, bq24262

SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

bq2426x 3-A, 30-V, Host-Controlled Single-Input, Single-Cell Switched-Mode Li-Ion Battery

Charger With Power-Path Management and USB-OTG Support

Not Recommended for New Designs : bq24260, bq24261

1 Features

2 Applications

1

•

Charge Time Optimizer (Enhanced CC/CV

Transition) for Faster Charging

•

Smart Phones and Tablets

Handheld Products

Integrated FETs for up to 3-A Charge Rate at 5%

Accuracy and 93% Peak Efficiency

Power Banks and External Battery Packs

Small Power Tools

Boost Capability to Supply 5 V at 1 A at IN for

USB OTG Supply

Portable Media Players and Gaming

Integrated 17-mΩ Power-Path MOSFET and

Optional BGATE Control to Maximize Battery Life

and Instantly Start up From a Deeply Discharged

Battery or No Battery

3 Description

The bq24260/bq24261/bq24261M/bq24262 is

a

highly integrated single-cell Li-Ion battery charger and

system power path management device that supports

operation from either a USB port or wall adapter

supply. The power-path feature allows the

bq24260/1/1M/2 to power the system from a high

efficiency DC-DC converter while simultaneously and

independently charging the battery. The power path

also permits the battery to supplement the system

current requirements when the adapter cannot. Many

features are programmable using the I²C interface.

•

30-V Input Rating With Overvoltage Protection

Supports 5-V USB 2.0/3.0 and 12-V USB Power

Delivery (bq24261/1M)

Small Solution Size In a 2.4-mm × 2.4-mm 36-Pin

WCSP or 4-mm × 4-mm 24-Pin QFN Package

–

Total Charging Solution Can be 50 mm²or

Less With WCSP

To

support

USB

OTG

applications,

the

•

Safe and Accurate Battery-Management

Functions Programmed Using I²C Interface

bq24260/1/1M/2 is configurable to boost the battery

voltage to 5 V and supply up to 1 A at the input. The

battery is charged with three phases: precharge,

constant current, and constant voltage. Thermal

regulation prevents the die temperature from

exceeding 125°C. Additionally, a JEITA-compatible

battery pack thermistor monitoring input (TS) is

included to prevent the battery from charging outside

of its safe temperature range.

–

Charge Voltage, Current, Termination

Threshold, Input Current Limit, V_{IN_DPM}

Threshold

–

Voltage-Based, JEITA-Compatible NTC

Monitoring Input

Thermal Regulation Protection for Input

Current Control

Device Information⁽¹⁾

Thermal Shutdown and Protection

PART NUMBER

PACKAGE

DSBGA (36)

QFN (24)

BODY SIZE (NOM)

2.40 mm × 2.40 mm

4.00 mm × 4.00 mm

bq24260/1/1M/2

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

4 Application Schematic

IN

SW

VBUS

Charge Time Optimizer Effect

Charge Cycle 4000mAh Battery 2A Charge Rate

D+

D-

System

Load

GND

PGND

3

BOOT

4.4

4.2

4

`

PMID

2.5

2

SYS

`

3.8

3.6

3.4

3.2

3

D+

D-

More Energy

Delivered to

the Battery

in the Same

Time

BAT

1.5

1

CD

SDA

SCL

bq24260

HOST

INT

PACK+

TEMP

TS

2.8

2.6

2.4

VDRV

0.5

PACK-

V _I/O

0

2000

4000

6000

8000

10000 11000

IBAT_Traditional

Time (sec)

VBAT_CTO

VBAT_Traditional

IBAT_CTO

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Not Recommended for New Designs : bq24260, bq24261

bq24260, bq24261, bq24261M, bq24262

SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

www.ti.com

Table of Contents

9.4 Device Functional Modes........................................ 16

9.5 Programming........................................................... 27

9.6 Register Maps......................................................... 30

10 Application and Implementation........................ 38

10.1 Application Information.......................................... 38

10.2 Typical Application ................................................ 38

11 Power Supply Recommendations ..................... 43

11.1 Requirements for SYS Output .............................. 43

11.2 Requirements for Charging................................... 43

12 Layout................................................................... 43

12.1 Layout Guidelines ................................................. 43

12.2 Layout Example .................................................... 44

13 Device and Documentation Support ................. 45

13.1 Documentation Support ....................................... 45

13.2 Related Links ........................................................ 45

13.3 Trademarks........................................................... 45

13.4 Electrostatic Discharge Caution............................ 45

13.5 Glossary................................................................ 45

1

2

3

4

5

6

7

8

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Application Schematic .......................................... 1

Revision History..................................................... 2

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

8.1 Absolute Maximum Ratings ...................................... 6

8.2 ESD Ratings.............................................................. 6

8.3 Recommended Operating Conditions....................... 6

8.4 Thermal Information ................................................. 7

8.5 Electrical Characteristics........................................... 7

8.6 Switching Characteristics........................................ 11

8.7 Typical Characteristics............................................ 11

Detailed Description ............................................ 13

9.1 Overview ................................................................. 13

9.2 Functional Block Diagram ....................................... 14

9.3 Feature Description................................................. 16

9

14 Mechanical, Packaging, and Orderable

Information ........................................................... 45

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (March 2015) to Revision D

Page

•

Added device bq24261M ....................................................................................................................................................... 1

Changed minimum capacitance for DRV pin from 1 µF to 2.2 µF. ........................................................................................ 5

Changed absolute max voltage for DRV, SYS from 5.0 V to 5.5 V ....................................................................................... 6

Changed VSYSREG(HI) from VBATREG+1.6% to original VBATREG+2.5% typical ........................................................... 7

Added bq24261M VSYSREG(HI) = 1.6% typical .................................................................................................................. 7

Changed ILIM(DISCH) from 9 A to original 6 A typical .......................................................................................................... 7

Added bq24261M ILIM(DISCH) = 9 A typical ........................................................................................................................ 7

Added Explanation for Reg05h B4 Force D+/D- ................................................................................................................. 36

Changed bypass capacitor value from 1 µF to 2.2 µF in the Typical Application Circuit .................................................... 38

Changes from Revision B (March 2014) to Revision C

Page

•

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section .................................................................................................. 1

Changes from Revision A (January 2014) to Revision B

Page

•

Changed global format to new data sheet schema................................................................................................................ 1

Changed device number from "bq24262A" to "bq24262" throughout .................................................................................... 1

Changed V_BATREGaccuracy for 0-125C, added 0-85C, and added mV specific numbers to Elec Charateristics table. ........ 8

Added Switching Characteristics .......................................................................................................................................... 11

Added Power Supply Recommendations............................................................................................................................. 43

Added Device and Documentation Support ......................................................................................................................... 45

2

Submit Documentation Feedback

Product Folder Links: bq24260 bq24261 bq24261M bq24262

Not Recommended for New Designs : bq24260, bq24261

bq24260, bq24261, bq24261M, bq24262

www.ti.com

SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

•

Changed location of Ordering Information to Mechanical, Packaging, and Orderable Information ..................................... 45

Changes from Original (December 2013) to Revision A

Page

•

Added specifications to Electrical Characteristics table pertaining to RGE package............................................................. 7

Added separate lines for I_INLIMcurrent for YFF and RGE packages. ..................................................................................... 9

Changed V_{DO_DRV}spec MAX voltage from "500 mV" to "450 mV"......................................................................................... 9

Changed the wording of the Safety Timer description for clarification. ............................................................................... 22

Changed text in the F/S Mode Protocol section from "...to either transmit data to the slave (R/W bit 1) or receive

data from the slave (R/W bit 0" to "...to either transmit data to the slave (R/W bit 0) or receive data from the slave

(R/W bit 1" for clarification.................................................................................................................................................... 28

Submit Documentation Feedback

3

Product Folder Links: bq24260 bq24261 bq24261M bq24262

Not Recommended for New Designs : bq24260, bq24261

bq24260, bq24261, bq24261M, bq24262

SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

www.ti.com

6 Device Comparison Table

SYSTEM

REGULATION

VOLTAGE

(TYP)

BATTERY

DISCHARGE

CURRENT LIMIT

(MIN)

DEFAULT

V_BATREG

PART

NUMBER

CE BIT

DEFAULT

D+/D–

DETECTION

TIMERS (SAFETY

AND WATCHDOG)

OVP

0

bq24260

bq24261

10.5

14

Yes

No

Yes

4 A

V_BATREG+ 2.5%

3.6 V

(Charge Enabled)

1

(Charge

Disabled)

V_BATREG+ 2.5%

1

BQ24261M

bq24262

14

(Charge

Disabled)

No

Yes

No

6 A

4 A

V_BATREG+ 1.6%

V_BATREG+ 2.5%

3.6 V

4.2 V

0

6.5

(Charge Enabled)

7 Pin Configuration and Functions

YFF Package

36-Pin DSBGA

bq24260 (Top View)

bq24261/2 (Top View)

1

2

3

4

5

6

1

2

3

4

5

6

PGND

SW

PGND

A

B

C

D

E

F

A

B

C

D

E

F

PMID

SW

IN

SW

IN

SW

CD

SW

PMID

SW

IN

SW

IN

SW

IN

SW

CD

SW

BOOT

DRV

SYS

IN

BOOT

IN

SDA

STAT

SCL

INT

D–

D+

TS

SDA

SCL

INT

N.C.

SYS

PSEL

SYS

TS

DRV

SYS

STAT

SYS

AGND

BGATE

BAT

AGND

BGATE

BAT

RGE Package

24-Pin VQFN

(Top View)

PMID

1

18 IN

PMID

1

18 IN

BOOT

DRV

2

3

17 SDA

16 SCL

BOOT

DRV

2

3

17 SDA

16 SCL

bq24260

bq24261

bq24262

CD

TS

4

5

15 D–

14 D+

CD

TS

4

5

15 N.C.

14 PSEL

SYS

6

13 STAT

SYS

6

13 STAT

4

Submit Documentation Feedback

Product Folder Links: bq24260 bq24261 bq24261M bq24262

Not Recommended for New Designs : bq24260, bq24261

bq24260, bq24261, bq24261M, bq24262

www.ti.com

SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

Pin Functions

bq24260

DSBGA VQFN DSBGA VQFN

bq24261/1M/2

I/O

DESCRIPTION

NAME

AGND

BAT

F1

12, 20

8, 9

F1

12, 20

8, 9

Analog Ground. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.

Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at

least 1 μF of ceramic capacitance. See Application and Implementation for additional details.

F3-F6

I/O

O

BGATE

External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFET

to provide a very low resistance discharge path. Connect BGATE to the gate of the external

MOSFET. BGATE is low during high impedance mode or when no input is connected. If no

external FET is required, leave BGATE disconnected. Do not connect BGATE to GND.

F2

11

F2

11

BOOT

CD

High Side MOSFET Gate Driver Supply. Connect 0.033 µF of ceramic capacitance (voltage

rating > 10 V) from BOOT to SW to supply the gate drive for the high side MOSFET.

C6

C5

2

4

C6

C5

2

4

I

IC Hardware Disable Input. Drive CD high to place the bq24260/1/1M/2 in hi-z mode. Drive CD

low for normal operation. CD is pulled low internally with 100 kΩ.

D+

D–

D4

D3

14

15

–

I

D+ and D– Connections for USB Input Adapter Detection. When a source is initially connected

to the input during DEFAULT mode, and a short is detected between D+ and D–, the input

current limit is set to 1.5 A. If a short is not detected, the USB100 mode is selected.

DRV

Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass

DRV to PGND with a 10-V or higher rated, +/-10%, X5R or better 2.2 µF ceramic capacitor. DRV

may be used to drive external loads up to 10mA. DRV is active whenever the input is connected

and V_IN> V_UVLOand V_IN> (V_BAT+ V_SLP).

D6

3

D6

3

O

I

IN

DC Input Power Supply. IN is connected to the external DC supply (AC adapter or USB port).

Bypass IN to PGND with at least a 4.7 μF of ceramic capacitance.

C1-C4

18, 19

C1-C4

18, 19

INT

Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT

pulls low during charging. INT is high impedance when charging is complete, disabled or the

charger is in high impedance mode. When a fault occurs, a 128-μs pulse is sent out as an

interrupt for the host. INT is enabled /disabled using the EN_STAT bit in the control register.

Connect INT to a logic rail through a 100-kΩ resistor to communicate with the host processor.

E2

10

E2

10

O

PGND

PMID

A1-A6

B1

21,22

1

A1-A6

B1

21,22

1

–

I

Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.

High Side Bypass Connection. Connect at least 1 µF of ceramic capacitance from PMID to

PGND as close to the PMID and PGND terminals as possible.

PSEL

Hardware Input Current Limit. In DEFAULT mode, PSEL selects the input current limit. Drive

PSEL high to select USB100 (bq24261/1M) or USB500 (bq24262) mode, drive PSEL low to

select 1.5 A mode.

–

D4

14

I

I²C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor. Do not leave floating.

I²C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.

SCL

D2

D1

16

17

D2

D1

16

17

I

SDA

STAT

I/O

Status Output. STAT is an open-drain output that signals charging status and fault interrupts.

STAT pulls low during charging. STAT is high impedance when charging is complete, disabled

or the charger is high impedance mode. When a fault occurs, a 128-μs pulse is sent out as an

interrupt for the host. STAT is enabled /disabled using the EN_STAT bit in the control register.

Connect STAT to a logic rail using an LED for visual indication or through a 100-kΩ resistor to

communicate with the host processor.

E1

13

E1

13

O

SW

Inductor Connection. Connect to the switched side of the external inductor. The inductance must

be between 1.5 µH and 2.2 µH.

B2-B6

E3-E6

23, 24

6, 7

B2-B6

E3-E6

23, 24

6, 7

O

I

SYS

System Voltage Sense and Charger FET Connection. Connect SYS to the system output at the

output bulk capacitors. Bypass SYS locally with at least 10 μF of ceramic capacitance. The SYS

rail must have at least 20 µF of total capacitance for stable operation. See Application and

Implementation for additional details.

TS

Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND.

The NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA

compatibility. TS faults are reported by the I²C interface. Pull TS high to V_DRVto disable the TS

function if unused. See the NTC Monitor section for more details on operation and selecting the

resistor values.

D5

–

5

–

D5

–

5

–

I

Thermal

Pad

There is an internal electrical connection between the exposed thermal pad and the PGND

terminal of the device. The thermal pad must be connected to the same potential as the PGND

terminal on the printed circuit board. Do not use the thermal pad as the primary ground input for

the device. PGND terminal must be connected to ground at all times.

–

Submit Documentation Feedback

5

Product Folder Links: bq24260 bq24261 bq24261M bq24262

Not Recommended for New Designs : bq24260, bq24261

bq24260, bq24261, bq24261M, bq24262

SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

www.ti.com

8 Specifications

8.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–1.3

–0.3

–0.7

–0.3

MAX

30

20

5

UNIT

IN

BOOT, PMID

Terminal Voltage (with respect to

PGND)

SW

V

BAT, BGATE, CD, INT, PSEL, SDA, SCL, STAT, TS

DRV, SYS

5.5

5

BOOT to SW

V

A

SW

4.5

3.5

6

Output Current (Continuous)

SYS, BAT (charging/ discharging)

BAT (discharging)

Output Current (<20 ms pulse,

<10% duty cycle)

Input Current (Continuous)

Output Sink Current

2.75

10

A

STAT, INT

mA

Operating free-air temperature

Junction temperature, T_J

Storage temperature, T_stg

–40

85

°C

125

300

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.2

NOM

MAX UNIT

28⁽¹⁾

IN voltage range

IN operating voltage range (bq24260)

IN operating voltage range (bq24261/1M)

IN operating voltage range (bq24262)

Input current, IN input

10

V

V_IN

13.2

6.0

I_IN

2.5

3

A

I_SW

Output Current from SW, DC

I_BAT, I_SYSCharging

Discharging, using internal battery FET

Operating junction temperature range

3

A

3

T_J

0

125

°C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW terminals. A

tight layout minimizes switching noise.

6

Submit Documentation Feedback

Product Folder Links: bq24260 bq24261 bq24261M bq24262

Not Recommended for New Designs : bq24260, bq24261

bq24260, bq24261, bq24261M, bq24262

www.ti.com

SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

8.4 Thermal Information

bq2426x

THERMAL METRIC⁽¹⁾

YFF [DSBGA]

RGE [VQFN]

24 PINS

32.6

UNIT

36 PINS

55.8

0.5

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

R_θJCtop

R_θJB

30.5

10

3.3

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.6

0.4

ψ_JB

9.9

9.3

R_θJCbot

N/A

2.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

Circuit of Figure 7, V_UVLO< V_IN< V_OVPAND V_IN> V_BAT+ V_SLP, T_J= –40°C to 125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CURRENTS

V_UVLO< V_IN< V_OVPand V_IN> V_BAT+ V_SLP

PWM switching

15

YFF Package: V_UVLO< V_IN< V_OVPand _VIN> V_BAT+ V_SLP

PWM NOT switching

6.5

mA

μA

I_IN

Supply current for control

RGE Package: V_UVLO< V_IN< V_OVPand _VIN> V_BAT+ V_SLP

PWM NOT switching

6.65

250

15

0°C < T_J< 85°C, V_IN= 5 V, Hi-Z Mode

0°C < T_J< 85°C, V_BAT= 4.2 V, V_IN= 5 V,

SCL, SDA = 0 V or 1.8 V, Hi-Z Mode

Battery discharge current in

High Impedance mode, (BAT,

SW, SYS)

YFF Package: 0°C < T_J< 85°C, V_BAT= 4.2 V, V_IN= 0 V,

SCL, SDA = 0 V or 1.8 V

I_{BAT_HIZ}

77

80

RGE Package: 0°C < T_J< 85°C, V_BAT= 4.2 V, V_IN= 0 V,

SCL, SDA = 0 V or 1.8 V

POWER-PATH MANAGEMENT

V_SYSREG(LO)System Regulation Voltage

V_MINSYS

+ 120

mV

V_MINSYS

+ 80 mV + 100 mV

V_MINSYS

V_BAT< V_MINSYS

V

V_BATREG

+2.2%

V_BATREGV_BATREG

+2.5% +2.77%

bq24260/1/2 - Battery FET turned off, no charging, V_BAT> 3.5

V

V_SYSREG(HI)

System Regulation Voltage

V_BATREG

+1.4%

V_BATREGV_BATREG

bq24261M - Battery FET turned off, no charging, V_BAT> 3.5 V

V_BAT+ V_{DO(SYS_BAT)}< 3.5 V

+1.6%

+1.77%

Minimum System Voltage

Regulation Threshold

V_MINSYS

3.44

3.5

3.55

V

ms

V

Deglitch time, VMINSYS

comparator rising

t_{DGL(MINSYS_CMP)}

8

Enter supplement mode

threshold

V_BAT– 20

mV

V_BSUP1

V_BAT> V_BUVLO

Exit supplement mode

threshold

V_BAT– 5

mV

V_BSUP2

V

bq24260/1/2 - V_LIM(BGATE)= V_BAT– V_SYS

bq24261M - V_LIM(BGATE)= V_BAT– V_SYS

4

6

9

Current Limit, Discharge or

Supplement Mode⁽¹⁾

I_LIM(DISCH)

A

Deglitch Time, SYS Short

Circuit during Discharge or

Supplement Mode

t_DGL(SC1)

Measured from I_BAT= 7A to FET off

250

2

μs

Recovery time, SYS Short

Circuit during Discharge or

Supplement Mode

t_REC(SC1)

s

Battery Range for BGATE

Operation

2.5

4.5

V

(1) Continuous and periodic pulse currents from BAT to SYS are limited by Output Current specifications in Absolute Maximum Ratings

table.

Submit Documentation Feedback

7

Product Folder Links: bq24260 bq24261 bq24261M bq24262

Not Recommended for New Designs : bq24260, bq24261

bq24260, bq24261, bq24261M, bq24262

SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

www.ti.com

Electrical Characteristics (continued)

Circuit of Figure 7, V_UVLO< V_IN< V_OVPAND V_IN> V_BAT+ V_SLP, T_J= –40°C to 125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BATTERY CHARGER

YFF

17

32

25

47

Measured from BAT to SYS,

V_BAT= 4.2 V, Hi-Z mode

Internal battery charger

MOSFET ON-resistance

R_ON(BAT-SYS)

mΩ

RGE

Charge Voltage

Operating in voltage regulation, Programmable Range

T_J= 0°C to 50°C

3.5

4.44

V

RGE Package Voltage

Regulation Accuracy

–0.5%

0.5%

0.7%

0.75%

1.0%

28.1

RGE Package Voltage

Regulation Accuracy

T_J= 0°C to 85°C

T_J= 0°C to 125°C

T_J= 25°C

–0.7%

–0.75%

–1.0%

–29.2

YFF Package Voltage

Regulation Accuracy

V_BATREG

RGE and YFF Package

Voltage Regulation Accuracy

YFF Package Voltage

Regulation Accuracy

YFF Package Voltage

Regulation Accuracy

T_J= 0°C to 85°C

T_J= 0°C to 125°C

–32.0

29.3

mV

mA

YFF Package Voltage

Regulation Accuracy

–40.2

29.3

Fast Charge Current Range

V_BATSHRT≤ V_BAT< V_BAT(REG)

500

–10%

–5%

1.9

3000

10%

5%

I_CHARGE

500 mA ≤ I_CHARGE≤ 1A

Fast Charge Current

Accuracy

I_CHARGE> 1000 mA

V_BATSHRT

Battery short-circuit threshold

Hysteresis for V_BATSHRT

2

2.1

V

V_{BATSHRT_HYS}

Battery voltage falling

V_BATrising or falling

100

mV

Deglitch time for battery short

to fastcharge transition

1

ms

Battery short-circuit charge

current

I_BATSHRT

V_BAT< V_BATSHRT

33.5

50

66.5

mA

I

_TERM≤ 50 mA

50 mA < _ITERM< 200 mA

_TERM≥ 200 mA

–30%

–15%

30%

15%

10%

I_TERM

Termination charge current

I

Both rising and falling, 2-mV over-drive,

t_RISE, t_FALL=100 ns

Deglitch time for charge

termination

t_DGL(TERM)

32

ms

V_RCH

Recharge threshold voltage

Deglitch time

Below V_BATREG

100

120

32

150

mV

ms

t_DGL(RCH)

V_BATfalling below V_RCH, t_FALL=100 ns

Battery detection voltage

threshold

V_DET(SRC1)

During current source (Turn I_{BATSHRT off}

)

V_RCH

V

(TE = 1)

V_RCH

– 200mV

V_DET(SRC2)

V_DET(SNK)

During current source (Turn I_{BATSHRT on}

During current sink

)

V

V_BATSHRT

Battery detection current

before charge done (sink

current)

I_DETECT

Termination enabled (TE = 1)

7

mA

Battery detection time

(sourcing current)

t_DETECT(SRC)

t_DETECT(SNK)

Termination enabled (TE = 1)

2

s

Battery detection time (sinking

current)

250

ms

8

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Electrical Characteristics (continued)

Circuit of Figure 7, V_UVLO< V_IN< V_OVPAND V_IN> V_BAT+ V_SLP, T_J= –40°C to 125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CURRENT LIMITING

I_INLIM=USB100

I_INLIM=USB500

I_INLIM=USB150

I_INLIM=USB900

I_INLIM=1.5 A

90

450

95

475

100

500

125

140

150

800

850

900

1425

1500

1575

USB charge mode, V_IN= 5 V, Current

pulled from SW

I_INLIM=2 A, YFF

Package

I_INLIM

Input current limiting threshold

mA

1850

2300

2225

2000

2500

2150

2200

2700

2825

I_INLIM=2 A, RGE

Package

I_INLIM=2.5 A, YFF

Package

I_INLIM=2.5 A,

RGE Package

Input based DPM threshold

range

Charge mode, programmable via I²C

V_{IN_DPM}

4.2

11.6

3%

V

V_{IN_DPM}threshold Accuracy

–3%

V_DRVBIAS REGULATOR

V_DRVInternal bias regulator voltage V_IN> 5 V

I_DRV

4.3

0

4.8

5.3

10

V

DRV Output Current

DRV Dropout Voltage

mA

V_{DO_DRV}

I_IN= 1 A, V_IN= 4.2 V, I_DRV= 10 mA

450

mV

(V_{IN – VDRV}

)

STATUS OUTPUT (STAT, INT)

Low-level output saturation

V_OL

I_O= 10 mA, sink current

V _STAT= V_INT= 5 V

0.4

1

V

voltage

I_IH

High-level leakage current

µA

INPUT PINS (CD, PSEL)

V_IL

Input low threshold

0.4

V

V_IH

Input high threshold

1.4

3.2

R_PULLDOWN

CD pulldown resistance

Deglitch for CD and PSEL

CD Only

100

kΩ

µs

CD or PSEL rising/falling

PROTECTION

V_UVLO

IC active threshold voltage

IC active hysteresis

V_INrising

3.3

3.4

V

V_{UVLO_HYS}

V_INfalling from above V_UVLO

300

mV

Battery Undervoltage Lockout

threshold

V_BATUVLO

V_SLP

V_BATfalling, 100-mV Hysteresis

2.0 V < V_BAT< V_BATREG, V_INfalling

2.4

40

2.6

V

Sleep-mode entry threshold,

V_IN-V_BAT

0

120

mV

Deglitch time, BAT above

V_BATUVLObefore SYS starts to

rise

t_DGL(BAT)

1.2

ms

V_{SLP_HYS}

t_DGL(VSLP)

Sleep-mode exit hysteresis

V_INrising above V_SLP

40

100

30

190

mV

ms

Deglitch time for supply rising

above V_SLP+V_{SLP_HYS}

Rising voltage, 2-mV over drive, t_RISE=100 ns

bq24260

10.1

13.6

6.25

10.5

14

10.9

14.4

6.75

Input supply OVP threshold

voltage

V_OVP

IN rising, 100-mV hysteresis

bq24261/1M

bq24262

V

6.5

Good Battery Monitor

Threshold (BQ24260/1 only)

V_BATGD

V_INRising

3.51

3.7

3.89

V

ms

V

Deglitch time, VIN OVP in

Buck Mode

t_{DGL(BUCK_OVP)}

V_BOVP

IN falling below V_OVP

30

1.03 ×

V_BATREG

1.05 ×

V_BATREGV_BATREG

1.07 ×

Battery OVP threshold voltage V_BATthreshold over V_OREGto turn off charger during charge

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Electrical Characteristics (continued)

Circuit of Figure 7, V_UVLO< V_IN< V_OVPAND V_IN> V_BAT+ V_SLP, T_J= –40°C to 125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

% of

V_BATREG

V_{BOVP_HYS}

V_BOVPhysteresis

Lower limit for V_BATfalling from above V_BOVP

1

t_DGL(BOVP)

I_CbCLIMIT

T_SHTDWN

BOVP Deglitch

Battery entering/exiting BOVP

V_SYSshorted

8

4.5

150

10

ms

A

Cycle-by-cycle current limit

Thermal trip

4.1

4.9

°C

Thermal hysteresis

Thermal regulation threshold

Safety Timer Accuracy

T_REG

Input current begins to cut off

125

–20%

20%

PWM

YFF Package: Measured from IN to SW

RGE Package: Measured from IN to SW

YFF Package: Measured from SW to PGND

RGE Package: Measured from SW to PGND

75

80

120

135

115

135

1.65

mΩ

MHz

Internal top MOSFET ON-

resistance

R_{DSON_Q1}

75

Internal bottom N-channel

MOSFET ON-resistance

R_{DSON_Q2}

80

f_OSC

Oscillator frequency

Maximum duty cycle

Minimum duty cycle

1.35

0%

1.5

95%

D_MAX

D_MIN

—

BATTERY-PACK NTC MONITOR (1)

V_HOT

High temperature threshold

V_TSfalling, 2% V_DRVHysteresis

V_TSrising, 2% V_DRVHysteresis

V_TSrising, 4% V_DRVHysteresis

Applies to V_HOT, V_WARM, V_COOLand V_COLD

27.3

36.0

54.7

58.2

80

30

38.3

56.4

60

32.6 %V_DRV

41.2 %V_DRV

58.1 %V_DRV

61.8 %V_DRV

85 %V_DRV

ms

V_WARM

V_COOL

V_COLD

TSOFF

t_DGL(TS)

Warm temperature threshold

Cool temperature threshold

Low temperature threshold

TS Disable threshold

Deglitch time on TS change

50

I²C-COMPATIBLE INTERFACE

V_IH

Input low threshold level

V_PULL-UP=1.8 V, SDA and SCL

IL=5 mA, sink current

1.3

30

V

V_IL

Input low threshold level

Output low threshold level

High-Level leakage current

0.4

1

V

V_OL

I_BIAS

V_PULL-UP=1.8 V, SDA and SCL

μA

s

t_WATCHDOG

t_I2CRESET

OTG BOOST SUPPLY

50

700

ms

Quiescent current during

boost mode (BAT pin)

I_{QBAT_ BOOST}

3.3 V < V_BAT< 4.5 V, no switching

VBAT falling

100

4.5

5.2

µA

V

Battery voltage range for

specified boost operation

3.3

Boost output voltage (to pin

VBUS)

V_{IN_BOOST}

3.3 V < V_BAT< 4.5 V over line and load

4.95

5.05

V

BOOST_ILIM = 1

BOOST_ILIM = 0

BOOST_ILIM = 1

1000

500

Maximum output current for

boost

I_BO

3.3 V < V_BAT< 4.5 V

mA

A

Cycle by cycle current limit for

boost (measured at low-side

FET)

4

2

I_BLIMIT

3.3 V < V_BAT< 4.5 V

BOOST_ILIM = 0

Overvoltage protection

threshold for boost (IN pin)

V_BOOSTOVP

Signals fault and exits boost mode

5.8

6

6.2

V

Deglitch Time, VIN OVP in

Boost Mode

t_{DGL(BOOST_OVP)}

170

µs

Upper V_INvoltage threshold to

enter burst mode (stop

switching)

V_BURST(ENT)

5.1

4.9

5.2

5

5.3

5.1

V

Lower V_BUSvoltage threshold

to exit burst mode (start

switching)

V_BURST(EXIT)

10

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8.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Oscillator frequency

Maximum duty cycle

Minimum duty cycle

TEST CONDITIONS

MIN

TYP

1.5

MAX

UNIT

f_OSC

1.35

1.65

MHz

D_MAX

D_MIN

95%

0%

8.7 Typical Characteristics

10

8

95

90

85

6

4

2

0

-2

-4

-6

-8

-10

80

75

70

VIN=5V

TA=25ºC

TA=0ºC

VIN=7V

VIN=10V

VIN=12V

TA=85ºC

TA=60ºC

0

0.5

1

1.5

Load Current (A)

Figure 2. Efficiency vs Output Current

2

2.5

3

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

VBAT (V)

Figure 1. Charge Current vs Battery Voltage

100

0.0

90

80

70

60

50

40

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

TA=25ºC

TA=60ºC

TA=0ºC

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

VBAT (V)

IBAT (A)

Figure 3. Efficiency vs Battery Voltage

Figure 4. VBAT Accuracy vs IBAT – 4.2-V Setting

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Typical Characteristics (continued)

700

600

500

400

300

200

100

0

16

14

12

10

8

6

4

Input Current (μA)

2

0

-100

-2

3

5

7

9

11

13

15

0

2

4

6

8

10

Input Voltage - V

Figure 5. Input IQ - No Battery, No System

12

14

16

Input Voltage (V)

Figure 6. Input IQ With Hi-Z Enabled

12

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9 Detailed Description

9.1 Overview

The bq24260/1/1M/2 is a highly integrated single-cell Li-Ion battery charger and system power-path management

device targeted for space-limited, portable applications with high capacity batteries. The single-cell charger has a

single input that supports operation from either a USB port or wall adapter supply for a versatile solution.

The power-path management feature allows the bq24260/1/1M/2 to power the system from a high efficiency DC-

DC converter while simultaneously and independently charging the battery. The charger monitors the battery

current at all times and reduces the charge current when the system load requires current above the input

current limit or the adapter cannot support the required load, causing the adapter voltage to fall (V_{IN_DPM}). This

allows for proper charge termination and timer operation. The system voltage is regulated to the battery voltage

but will not drop below 3.5 V (V_MINSYS). This minimum system voltage support enables the system to run with a

defective or absent battery pack and enables instant system turnon even with a totally discharged battery or no

battery. The power-path management architecture also permits the battery to supplement the system current

requirements when the adapter cannot deliver the peak system currents. The power-path feature coupled with

V_IN-DPM, enables the use of many adapters with no hardware change. The charge parameters are

programmable using the I²C interface. To support USB OTG applications, the bq24260/1/1M/2 is configurable to

boost the battery voltage to 5 V at the input. In this mode, the bq24260/1/1M/2 supplies up to 1 A and operates

with battery voltages down to 3.3 V.

The battery is charged using a standard Li-Ion charge profile with three phases: precharge, constant current, and

constant voltage. In all charge phases, an internal control loop monitors the IC junction temperature and reduces

the input current to prevent the junction temperature from rising above 125°C. Additionally, a voltage-based,

JEITA-compatible battery pack thermistor monitoring input (TS) is included that monitors battery temperature and

automatically changes charge parameters to prevent the battery from charging outside of its safe temperature

range.

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9.2 Functional Block Diagram

PMID

ꢀ.8V

Reference

DRV

IN

I_CbCLimit

BOOT

I_INLIM

Q1

DC-DC CONVERTER PWM LOGIC,

COMPENSATION AND BATTERY

FET CONTROL

V_INDPM

V_SYS(REG)

I_BAT(REG)

V_BAT(REG)

SW

DIE Temp

Regulation

Qꢁ

PGND

V_SUPPLY

References

SYS

OVP

Comparator

Termination

Reference

V_IN

+

Q3

V_INOVP

+

I_BAT

Termination

Comparator

Sleep

Comparator

BAT

V_IN

+

Recharge Comparator

+

V_BAT+V_SLP

Start Recharge

Cycle

V_BATREG0.1ꢁV

V_BAT

Hi-Impedance Mode

BGATE

V_SYSREGComparator

Hi-Z

Mode

+

V_SYS

Enable Linear

Charge

CD

V_MINSYS

+

Enable HiZ in

DEFAULT mode

SDA

SCL

V_BATGD

IꢁC

Interface

V_BATSCComparator

+

Enable

I_BATSHRT

V_BAT

V_BATSHRT

Supplement COMPARATOR

+

V_SYS

V_BSUP

V_BAT

bqꢁꢀꢁ60

D+

VDRV

V_BOVPComparator

USB

Adapter

Detection

Circuitry

+

V_BAT

1.5A /

USB100

V_BATOVP

D-

+

DISABLE

bqꢁꢀꢁ61/ꢁ

PSEL

TS COLD

+

1C/

0.5C

TS COOL

V_BATREG

0.1ꢀV

STAT

INT

TS WARM

TS HOT

+

DISABLE

TS

CHARGE

CONTROLLER

w/ Timers

Figure 7. Block Diagram in Charging Mode

14

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Functional Block Diagram (continued)

PMID

4.8-V

DRV

Reference

IN

BOOT

V

Amp

BOOST

+

Q1

V

IN_BOOST

DC-DC

CONVERTER

PWM LOGIC

AND

Low Side Current

Limit Comparator

+

SW

V

BURST_ENT

Burst Mode Enter

Comparator

I

COMPENSATION

BLIMITI

V

DRV

+

Q2

BURST_EXT

Burst Mode Exit

Comparator

PGND

Boost Short Circuit

Comparator

+

V

BOOSTSHRT

+

V

BOOSTOVP

V

BOOST

OVP Comparator

SYS

Battery SC Comparator

V

BIAS

V

Q3

+

BAT

Battery Short

Circuit

I

LIM(DISCH)

BAT

CD

Hi-Z

Mode

SDA

SCL

2

I C

interface

BGATE

Digital Control

STAT

INT

TS

Figure 8. Block Diagram in Boost Mode

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9.3 Feature Description

The bq24260/1/1M/2 is a highly integrated single-cell Li-Ion battery charger and system power path management

device that supports operation from either a USB port or wall adapter supply. The power path feature allows the

bq24260/1/1M/2 to power the system from a high efficiency DC-DC converter while simultaneously and

independently charging the battery. The power path also permits the battery to supplement the system current

requirements when the adapter cannot. Many features are programmable using the I²C interface. To support

USB OTG applications, the bq24260/1/1M/2 is configurable to boost the battery voltage to 5 V and supply up to 1

A at the input. The battery is charged with three phases: precharge, constant current and constant voltage.

Thermal regulation prevents the die temperature from exceeding 125°C. Additionally, a JEITA compatible battery

pack thermistor monitoring input (TS) is included to prevent the battery from charging outside of its safe

temperature range.

Device Functional Modes explains these features in detail.

9.4 Device Functional Modes

9.4.1 High Impedance Mode

High Impedance mode (Hi-Z mode) is the low quiescent current state for the bq24260/1/1M/2. During Hi-Z mode,

the buck converter is off, and the battery FET and BGATE are on. SYS is powered by BAT. The bq24260/1/1M/2

is in Hi-Z mode when V_IN< V_UVLO, the HZ_MODE bit in the I²C is '1' or the CD terminal is driven high. Hi-Z mode

resets the safety timer.

The bq24260/1/1M/2 contains a CD input that is used to disable the IC and place the bq24260/1/1M/2 into high-

impedance mode. Drive CD low to enable the bq24260/1/1M/2 and enter normal operation. Drive CD high to

disable charge and place the bq24260/1/1M/2 into high-impedance mode. CD is internally pulled down to PGND

with a 100-kΩ resistor. When exiting Hi-Z mode, charging resumes in approximately 110 ms.

9.4.2 Battery Only Connected

When the battery is connected with no input source, the battery FET is turned on. After the battery rises above

V_BATUVLOand the deglitch time, t_DGL(BAT), the SYS output starts to rise. In this mode, the current is not regulated;

however, there is a short-circuit current limit. If the short-circuit limit (I_LIM(DISCHG)) is reached for the deglitch time

(t_DGL(SC)), the battery FET is turned off for the recovery time (t_REC(SC)). After the recovery time, the battery FET is

turned on to test and see if the short has been removed. If it has not, the FET turns off and the process repeats

until the short is removed. This process protects the internal FET from overcurrent. If an external FET is used

for discharge, the body diode prevents the load on SYS from being disconnected from the battery and t_DGL(BAT)is

not applicable.

9.4.3 Input Connected

9.4.3.1 Input Voltage Protection in Charge Mode

9.4.3.1.1 Sleep Mode

The bq24260/1/1M/2 enters the low-power sleep mode if the voltage on V_INfalls below sleep-mode entry

threshold, V_BAT+V_SLP, and V_INis higher than the undervoltage lockout threshold, V_UVLO. In sleep mode, the input

is isolated from the battery. This feature prevents draining the battery during the absence of V_IN. When V_IN

<

V_BAT+ V_SLP, the bq24260/1/1M/2 turns off the PWM converter, turns the battery FET and BGATE on, sends a

single 128-μs pulse on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers are

updated in the I²C. Once V_IN> V_BAT+ V_SLP, the STATx bits are cleared and the device initiates a new charge

cycle. The FAULT_x bits are not cleared until they are read in the I²C and the sleep condition no longer exists.

16

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Device Functional Modes (continued)

9.4.3.1.2 Input Voltage Based Dynamic Power Management (V_IN-DPM)

During normal charging process, if the input power source is not able to support the programmed or default

charging current, the supply voltage deceases. Once the supply drops to V_{IN_DPM}(default 4.2 V), the charge

current limit is reduced to prevent the further drop of the supply. When the IC enters this mode, the charge

current is lower than the set value and the DPM_STATUS bit is set. This feature ensures IC compatibility with

adapters with different current capabilities without a hardware change. Figure 9 shows the V_IN-DPM behavior to a

current limited source. In this figure the input source has a 2-A current limit and the device is charging at 1 A. A

2.5-A load transient then occurs on V_SYScausing the adapter to hit its current limit and collapse, while V_SYSgoes

from V_SYSREG(LO)to V_MINSYS. If the 2X timer is set, the safety timer is extended while V_IN-DPM is active.

Additionally, termination is disabled.

Input voltage regulated to V_{IN_DPM}

V_IN

1V/div

2A/div

(5V Offset)

Input current limit reduced to avoid crashing adapter

I_IN

500mV/div

2A/div

V_SYS

(3.6V Offset)

SYS enters supplement mode to ensure SYS load is supported

Normal Charging (1A)

SYS load removed,

normal charging

resumes

I_BAT

2A/div

I_SYS

800us/div

Figure 9. bq24260/1/1M/2 V_IN-DPM

9.4.3.1.3 Input Overvoltage Protection

The built-in input overvoltage protection protects the bq24260/1/1M/2 and downstream components connected to

SYS and/or BAT against damage from overvoltage on the input supply (Voltage from V_INto PGND). When V_IN

>

V_OVP, the bq24260/1/1M/2 turns off the PWM converter immediately. After the deglitch time t_{DGL(BUCK_OVP)}, an

OVP fault is determined to exist. During the OVP fault, the bq24260/1/1M/2 turns the battery FET and BGATE

on, sends a single 128-μs pulse on the STAT and INT outputs, and the STATx and FAULT_x bits are updated in

the I²C. Once the OVP fault is removed, the STATx bits are cleared and the device returns to normal operation.

The FAULT_x bits are not cleared until they are read in the I²C after the OVP condition no longer exists.

The OVP threshold for the bq24260 is 10.5 V for operation from standard adapters while the bq24261/1M is set

to 14 V to enable operation from 12-V sources. The bq24262 OVP is set to 6.5 V to operate from standard USB

sources.

9.4.3.2 Charge Profile

When a valid input source is connected (V_IN> V_UVLOand V_BAT+ V_SLP< V_IN< V_OVP), the CE bit in the control

register determines whether a charge cycle is initiated. By default, the bq24260 and bq24262 enable the charge

cycle when a valid input source is connected while the bq24261/1M do not (CE = 1 by default). When the CE bit

is 1 and a valid input source is connected, the battery FET is turned off and the SYS output is regulated to

VSYSREG(HI). A charge cycle is initiated when the CE bit is written to a 0.

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Device Functional Modes (continued)

The bq24260/1/1M/2 supports a precision Li-Ion or Li-Polymer charging system for single-cell applications.

Charging is done through the internal battery MOSFET. There are 6 loops that influence the charge current;

constant current loop (CC), constant voltage loop (CV), thermal regulation loop, minimum system voltage loop

(MINSYS), input current limit and V_IN-DPM. During the charging process, all six loops are enabled and the one

that is dominant takes control. The minimum system output feature regulates the system voltage to V_SYSREG(LO)

,

so that startup is enabled even for a missing or deeply discharged battery. Figure 10 shows a typical charge

profile including the minimum system output voltage feature.

Voltage Regulation

Phase

Precharge

Phase

Current Regulation

Phase

Regulation

Voltage

Regulation

Current

System Voltage

V_SYS

(3.6V)

V_BATSHORT

(2.0V)

Battery

Voltage

Charge Current

Termination

I_BATSHORT

Linear Charge

50mA Linear Charge

to Close Pack

Protector

to Maintain

Minimum

System

Battery

FET

is OFF

Battery FET (Q3) is

ON

Voltage

Figure 10. Typical Charging Profile of bq24260/1/1M/2 With Termination Enabled

9.4.4 Battery Charging Process

When the battery is deeply discharged or shorted, the bq24260/1/1M/2 applies a I_BATSHRTcurrent to close the

battery protector switch and bring the battery voltage up to acceptable charging levels. During this time, the

battery FET is off and the system output is regulated to V_SYSREG(LO). Once the battery rises above V_BATSHRT, the

charge current is regulated to the value set in the I²C register. The battery FET is linearly regulated to maintain

the system voltage at V_SYSREG(LO). Under normal conditions, the time spent in this region is a very short

percentage of the total charging time, so the linear regulation of the charge current does not affect the overall

charging efficiency for very long. If the die temperature does heat up, the thermal regulation loop reduces the

input current to maintain a die temperature at 125°C. If the current limit for the SYS output is reached (limited by

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Device Functional Modes (continued)

the input current limit, V_IN-DPM, or 100% duty cycle), the SYS output drops to the V_MINSYSoutput voltage. When

this happens, the charge current is reduced to ensure the system is supplied with all the current that is needed

while maintaining the minimum system voltage. If the charge current is reduced to 0 mA, pulling further current

from SYS causes the output to fall to the battery voltage and enter supplement mode (see Dynamic Power-Path

Management for more details).

Once the battery is charged enough that the system voltage rises above V_SYSREG(LO)(approximately 3.5 V), the

battery FET is turned on fully and the battery is charged with the full programmed charge current set by the I²C

interface, I_CHARGE. The charge current is regulated to I_CHARGEuntil the voltage between BAT and PGND reaches

the regulation voltage. The voltage between BAT and PGND is regulated to V_BATREG(CV mode) while the charge

current naturally tapers down as shown in Figure 10. During CV mode, the SYS output remains connected to the

battery. The impedance of the battery FET is increased to 4x of the fully on value when IBAT falls below

approximately 350 mA to provide increased accuracy during termination. This will show a small rise in the SYS

voltage when the R_DSONincreases below approximately 350 mA.

When termination is enabled (TE bit is '1'), the bq24260/1/1M/2 monitors the charging current during the CV

mode. Once the charge current tapers down to the termination threshold, I_TERM, and the battery voltage is above

the recharge threshold, the bq24260/1/1M/2 terminates charge, turns off the battery charging FET and enters

battery detection (see Battery Detection section for more details). The system output is regulated to the

V_SYSREG(HI)and supports the full current available from the input. The battery supplement mode is available to

supply any SYS load that cannot be supported by the input source (see Dynamic Power-Path Management for

more details). The termination current level is programmable. To disable the charge current termination, the host

sets the charge termination bit (TE) of charge control register to 0. Refer to I²C section for details. When

termination is disabled, V_BATis continuously regulated to V_BATREG. Termination is also disabled when any loop is

active other than CC or CV. This includes V_INDPM, input current limit, or thermal regulation. Termination is also

disabled during TS warm/cool conditions and when the LOW_CHG bit is set to '1'.

A charge cycle is initiated when one of the following conditions is detected:

1. The battery voltage falls below the V_BATREG-V_RCHthreshold.

2. IN Power-on reset (POR)

3. CE bit toggle or RESET bit is set (Host controlled)

4. CD terminal is toggled

9.4.5 Charge Time Optimizer

The CC to CV transition is enhanced in the bq24260/1/1M/2 architecture. The "knee" between CC and CV is

sharp. This enables the charger to remain in CC mode as long as possible before beginning to taper the charge

current (CV mode). This provides a decrease in charge time as compared to older topologies.

9.4.6 Battery Detection

When termination conditions are met, a battery detection cycle is started. During battery detection, I_DETECTis

pulled from V_BATfor t_DETECT(SNK)to verify there is a battery. If the battery voltage remains above V_DET(SINK)for the

full duration of t_DETECT(SNK), a battery is determined to present and the IC enters “Charge Done”. If V_BATfalls

below V_DET(SINK), a “Battery Not Present” fault is signaled, the charge parameters are reset (V_BATREG, I_CHARGEand

I_TERM) and battery detection continues. The next cycle of battery detection, the bq24260/1/1M/2 turns on I_BATSHRT

for t_DETECT(SRC). If V_BATrises to V_DET(SRC1), the current source is turned off and a “No Battery” condition is

registered. In order to keep VBAT high enough to close the battery protector, the current source turns on if V_BAT

falls to V_DET(SRC2). The source cycle continues for t_DETECT(SRC). After t_DETECT(SRC), the battery detection continues

through another current sink cycle. Battery detection continues until charge is disabled, the

bq24260/1/1M/2enters hi-z mode or a battery is detected. Once a battery is detected, the fault status clears and

a new charge cycle begins. With no battery connected, the BAT output will transition from VRCH to PGND with a

high period of t_DETECT(SRC)and a low period of t_DETECT(SNK). See Figure 30 in Application Curves. Battery detection

is not performed when termination is disabled.

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Device Functional Modes (continued)

9.4.7 Battery Overvoltage Protection (BOVP)

If the battery is ever above the battery OVP threshold (V_BOVP), the battery OVP circuit shuts the PWM converter

off and the battery FET is turned on to discharge the battery to safe operating levels. A battery OVP most

commonly occurs when the bq24260/1/1M/2 returns to DEFAULT mode after a watchdog timer expiration or

RESET bit written to '1'. In this condition, the V_BATREGis reset and may be below the battery voltage. Other

conditions may be when the input is initially plugged in before I²C communication is established or TS WARM

conditions or when writing the V_BATREGto less than the battery voltage. The battery OVP condition is cleared

when the battery voltage falls below the hysteresis of V_BOVPeither by the battery discharging or writing the

V_BATREGto a higher value. When a battery OVP event exists for t_DGL(BOVP), the bq24260/1/1M/2 turns the battery

FET and BGATE on, sends a single 128μs pulse on the STAT / INT outputs and the STATx and FAULT_x bits

are updated in the I²C. Once the BOVP fault is removed, the STATx bits are cleared and the device returns to

normal operation. The FAULT_x bits are not cleared until they are read in the I²C after the BOVP condition no

longer exists.

9.4.8 Dynamic Power-Path Management

The bq24260/1/1M/2 features a SYS output that powers the external system load connected to the battery. This

output is active whenever a valid source is connected to IN or BAT. When V_SYS> V_SYSREG(LO), the SYS output is

connected to V_BAT. If the battery voltage falls to V_MINSYS, V_SYSis regulated to the V_SYSREG(LO)threshold to

maintain the system output even with a deeply discharged or absent battery. In this mode, the SYS output

voltage is regulated by the buck converter and the battery FET is linearly regulated to regulate the charge current

into the battery. The current from the supply is shared between charging the battery and powering the system

load at SYS. The dynamic power-path management (DPPM) circuitry of the bq24260/1/1M/2 monitors the current

limits continuously and if the SYS voltage falls to the V_MINSYSthreshold, it adjusts charge current to maintain the

minimum system voltage and supply the load on SYS. If the charge current is reduced to zero and the load

increases further, the bq24260/1/1M/2 enters battery supplement mode. During supplement mode, the battery

FET is turned on and V_BAT= V_SYSwhile the battery supplements the system load.

2000mA

1800mA

I_SYS

800mA

0mA

1500mA

I_IN

~850mA

0mA

1A

0mA

I_BAT

–200mA

3.6V

3.5V

DPPM loop active

V_SYS

~3.1V

Supplement

Mode

Figure 11. Example DPPM Response (V_Supply=5V, V_BAT= 3.1V, 1.5A Input Current Limit)

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Device Functional Modes (continued)

9.4.9 Battery Discharge FET (BGATE)

The bq24260/1/1M/2 contains a MOSFET driver to drive an external discharge FET between the battery and the

system output. This external FET provides a low impedance path for supplying the system from the battery.

Connect BGATE to the gate of the external discharge P-channel MOSFET. BGATE is on (low) under the

following conditions:

1. No input supply connected.

2. HZ_MODE = 1

3. CD terminal = 1

9.4.10 DEFAULT Mode

DEFAULT mode is used when I²C communication is not available. DEFAULT mode is entered in the following

situations:

1. When the charger is enabled and V_BAT<V_BATGDbefore I²C communication is established

2. When the watchdog timer expires without a reset from the I²C interface

3. The RESET bit is written in the I²C register

In DEFAULT mode, the I²C registers are reset to the default values. The 2-minute safety timer is reset and starts

when DEFAULT mode is entered if a charge cycle is underway. The default value for V_BATREGis 3.6 V for the

bq24260/1/1M and 4.2 V for the bq24262. The default value for I_CHARGEis 1 A. For the bq24260, the input current

limit is determined by the D+/D– detection (See D+/D– Based Adapter Detection section). For the bq24261,

bq24261M and bq24262, the input current limit in DEFAULT mode is set by PSEL. (See Power Source Selector

Input section) DEFAULT mode is exited by writing to the I²C interface. Note that if termination is enabled and

charging has terminated, a new charge cycle is NOT initiated when entering DEFAULT mode.

9.4.11 Good Battery Monitor

The bq2426x contains a good battery monitor circuit that places the bq2426x into hi-z mode if the battery voltage

is above the V_BATGDthreshold while in DEFAULT mode. This function is used to enable compliance to the

battery charging standard that prevents charging from an un-enumerated USB host while the battery is above the

good battery threshold. If the bq24260/1/1M/2 is in HOST mode, it is assumed that USB host has been

enumerated and the good battery circuit has no effect on charging. Any write to the I²C places the

bq24260/1/1M/2 in HOST mode and clears the high-impedance mode condition. The HZ_MODE bit is not

updated during this condition.

9.4.12 D+/D– Based Adapter Detection (D+/D–, bq24260 only)

The bq24260 contains a D+/D- based adapter detection circuit that is used to program the input current limit for

the input during DEFAULT mode. D+/D- is only performed in DEFAULT mode unless forced by the D+/D-_EN

bit in host mode.

By default the input current limit is set to 100 mA. During DEFAULT mode, when the input source is connected,

the bq24260 performs an adapter detection to determine if it is connected to a USB port or dedicated charger.

The adapter detection starts with a connection detection as described in the USB Battery Charging Specification

ver 1.2 (BC1.2). Once a connection is detected, the adapter detection is performed. If a connection is not

detected within 500ms, the adapter detection begins. The adapter detection runs as described in BC1.2. If a

CDP/DCP is detected, the input current limit is increased to 1.5 A. If an SDP is detected, the current limit

remains at 100 mA, until changed in the I²C.

D+/D- is initiated at any time by the host by setting the D+/D- EN bit in the I²C to 1. After detection is complete

the D+/D- EN bit is automatically reset to 0 and the detection circuitry is disconnected from the D+ D- terminals

to avoid interference with USB data transfer. When a command is written to change the input current limit in the

I²C, this overrides the current limit selected by D+/D- detection.

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Device Functional Modes (continued)

9.4.13 Power Source Selector Input (PSEL, bq24261/2 only)

The bq24261/2 contains a PSEL input that is used to program the input current limit during DEFAULT mode.

Drive PSEL high to indicate a USB source is connected to the input and program the 100 mA (bq24261/1M) or

500mA (bq24262) current limit for IN. Drive PSEL low to indicate that an AC Adapter is connected to the input.

When PSEL is low, the IC starts up with a 1.5-A input current limit. Once an I²C write is done and the device is in

HOST mode, the PSEL has no effect on the input current limit until the watchdog timer expires and returns

thebq24260/1/1M/2 to DEFAULT mode.

9.4.14 Safety Timer and Watchdog Timer in Charge Mode (bq24260/1/1M only)

At the beginning of charging process, the bq24260/1/1M starts the safety timer. This timer is active during the

entire charging process. If charging has not terminated before the safety timer expires, the IC enters suspend

mode where charging is disabled. When a safety timer fault occurs, a single 128μs pulse is sent on the STAT

and INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I²C. The CE bit, Hi-Z

mode, or power must be toggled in order to clear the safety timer fault. The safety timer duration is selectable

using the TMR_X bits in the Safety Timer Register/ NTC Monitor register. When the safety timer is active,

changing the safety timer duration resets the safety timer. The bq24260/1/1M also contains a 2X_TIMER bit that

enables the 2x timer function to prevent premature safety timer expiration when the charge current is reduced by

a load on SYS or a NTC condition. When 2X_TIMER is enabled, the timer runs at half speed when any loop is

active other than CC or CV. This includes V_INDPM, input current limit, or thermal regulation. The timer also runs at

half speed during TS warm/cool conditions and when the LOW_CHG bit is set to 1.

In addition to the safety timer, the bq24260/1/1M contains a 30-second (t_WATCHDOG) watchdog timer that monitors

the host through the I²C interface. Once a write is performed on the I²C interface, a watchdog timer is started.

The watchdog timer is reset by the host using the I²C interface. This is done by writing a 1 to the reset bit

(TMR_RST) in the control register. The TMR_RST bit is automatically set to 0 when the watchdog timer is reset.

This process must continue as long as the input is connected in order to maintain the register contents. If the

watchdog timer expires, the IC enters DEFAULT mode where the default register values are loaded, the safety

timer restarts at 2 minutes once charging continues. The I²C may be accessed again to reinitialize the desired

values and restart the watchdog timer. The watchdog timer flow chart is shown in Figure 12.

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Device Functional Modes (continued)

Start Safety Timer

Yes

Safety timer

fault

Safety timer expired?

No

Charging suspended

Enter suspended

mode

Fault indicated in

STAT registers

STAT = Hi

Update STAT

bits

Yes

Charge Done?

< I

TERM

I

CHG

No

I²C Write

performed?

No

Yes

Start watchdog timer

Reset watchdog timer

STAT = Hi

Update STAT

bits

Yes

Charge Done?

< I

I

CHG

TERM

No

Yes

Safety timer expired?

No

Safety timer

fault

Charging suspended

Enter suspended

mode

Fault indicated in

STAT registers

No

Yes

Received

software watchdog

RESET?

No

WD timer expired?

Yes

Reset to default

values in I²C

register

Restart 2 min

safety timer

Figure 12. Watchdog Timer Flow Chart for bq24260/1/1M

9.4.15 LDO Output (DRV)

The bq24260/1/1M/2 contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and

other circuitry. Additionally, DRV supplies up to 10mA external loads to power the STAT LED or the USB

transceiver circuitry. The maximum value of the DRV output is 5.3 V so it ideal to protect voltage sensitive USB

circuits. The LDO is on whenever a supply is connected to the input of the bq24260/1/1M/2. The DRV is disabled

under the following conditions:

•

V_SUPPLY< UVLO

V_SUPPLY< V_BAT+ V_SLP

Thermal Shutdown

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Device Functional Modes (continued)

9.4.16 External NTC Monitoring (TS)

The I²C interface allows the user to easily implement the JEITA standard for systems where the battery pack

thermistor is monitored by the host. Additionally, the bq24260/1/1M/2 provides a flexible, voltage based TS input

for monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at

a safe temperature during charging. The JEITA specification is shown in Figure 13.

1.0 C

Charging Current

0.5 C

Portion of spec not covered by TS

Implementation on bq2426x

4.25 V

4.15 V

V_BAT

4.1 V

T1

(0°C)

T2

(10°C)

T3 T4

(45°C) (50°C)

T5

(60°C)

Cold

Cool

Warm

Hot

Figure 13. Charge Current During TS Conditions

To satisfy the JEITA requirements, four temperature thresholds are monitored; the cold battery threshold (T_NTC

<

0°C), the cool battery threshold (0°C < T_NTC< 10°C), the warm battery threshold (45°C < T_NTC< 60°C) and the

hot battery threshold (T_NTC> 60°C). These temperatures correspond to the V_COLD, V_COOL, V_WARM, and V_HOT

thresholds in the EC table. Charging is suspended and timers are suspended when V_TS< V_HOTor V_TS> V_COLD

.

When V_COOL< V_TS< V_COLD, the charging current is reduced to half of the programmed charge current. When

V_HOT< V_TS< V_WARM, the battery regulation voltage is reduced by 140mV from the programmed regulation

threshold. The TS function is disabled by connecting TS directly to DRV (V_TS> V_TSOFF).

The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TS

connected to the center tap to set the threshold. The connections are shown in Figure 14. The resistor values are

calculated using the following equations:

é

ê

ë

ù

ú

û

1

V_DRV´RCOLD´RHOT ´

-

V_COLDV_HOT

RLO =

é

ê

ë

ù

é

ê

ù

V

V_DRV

V_HOT

DRV

RHOT ´

-1 - RCOLD´

-1

ú

V_COLD

û

ë

û

(1)

V_DRV

-1

V_COLD

RHI =

1

+

RLO RCOLD

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Device Functional Modes (continued)

where

•

V_COLD= 0.60 × V_DRV

V_HOT= 0.30 × V_DRV

(2)

(3)

RLO´RHI´ 0.564

RLO - RLO´0.564 -RHI´0.564

RLO´RHI´ 0.383

RCOOL =

RWARM =

RLO - RLO´ 0.383 -RHI´0.383

where

•

RHOT is the NTC resistance at the hot temperature

RCOLD is the NTC resistance at cold temperature

(4)

The WARM and COOL thresholds are not independently programmable. The COOL and WARM NTC

resistances for a selected resistor divider are calculated using Equation 3 and Equation 4.

V_BATREG

1 x Charge/

0.5 x Charge

V_DRV

– 140 mV

DISABLE

TS COLD

+

TS COOL

TS WARM

+

V_DRV

TS HOT

RHI

+

TS

PACK+

TEMP

bq2426x

RLO

PACK–

Figure 14. TS Circuit

9.4.17 Thermal Regulation and Protection

During the charging process, to prevent overheating in the chip, bq24260/1/1M/2 monitors the junction

temperature, T_J, of the die and reduces the input current once T_Jreaches the thermal regulation threshold, T_REG

.

The input current is reduced to zero when the junction temperature increases about 10°C above T_REG. Once the

input current is reduced to 0, the system current is reduced while the battery supplements the load to supply the

system. When the input current is completely reduced to 0 and T_J> 125°C, this is may cause a thermal

shutdown of the bq24260/1/1M/2 if the die temperature rises too high. At any state, if T_Jexceeds T_SHTDWN

,

bq24260/1/1M/2 stops charging and disables the buck converter. During thermal shutdown mode, PWM is turned

off, all timers are suspended, a single 128-μs pulse is sent on the STAT and INT outputs, and the STATx and

FAULT_x bits of the status registers are updated in the I²C. The charge cycle resumes when T_Jfalls below

T_SHTDWNby approximately 10°C.

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Device Functional Modes (continued)

9.4.18 Charge Status Outputs (STAT, INT)

The STAT/INT output is used to indicate operation conditions for bq24260/1/1M/2. STAT/INT is pulled low during

charging when EN_STAT bit in the control register is set to 1. When charge is complete or disabled, STAT/INT is

high impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of

STAT/INT during different operation conditions is summarized in Table 1. STAT/INT drives an LED for visual

indication or can be connected to the logic rail for host communication. The EN_STAT bit in the control register is

used to enable/disable the charge status for STAT/INT. The interrupt pulses are unaffected by EN_STAT and will

always be shown.

Table 1. STAT Terminal Summary

CHARGE STATE

Charge in progress and EN_STAT=1

STAT and INT BEHAVIOR

Low

Other normal conditions

High-Impedance

Charge mode faults: Timer faults, sleep mode, VIN overvoltage, VIN < UVLO or Sleep

mode, BOVP, thermal shutdown, No Battery and Battery Temperature faults

128-µs pulse, then High Impedance

9.4.19 Boost Mode Operation

In HOST mode, when the operation mode bit (BOOST_EN) in the control register is set to 1, bq24260/1/1M/2

operates in boost mode and delivers 5 V to IN to supply USB OTG devices connected to the USB connector.

Boost operation can start with VBAT between 3.45 V to 4.5 V, and will maintain boost output until VBAT falls to

3.3 V. IN supplies up to 1 A to power these devices. It is not recommended to operate boost mode when the

battery voltage is less than 3.3 V. Proper operation is not ensured.

9.4.19.1 Chip Disable Input During Boost Mode (CD)

The bq24260/1/1M/2 contains a CD input that is used to disable the IC and place the bq24260/1/1M/2 into high-

impedance mode. CD must be low to enter boost mode. Driving CD high during boost mode places the

bq24260/1/1M/2 into hi-z mode and resets the BOOST_EN bit in the I²C. When CD is high, the buck converter is

off, and the battery FET and BGATE are turned on. CD is internally pulled down to GND with a 100-kΩ resistor.

9.4.19.2 PWM Controller in Boost Mode

Similar to charge mode operation, in boost mode the IC switches at 1.5MHz to regulate the voltage at IN to 5 V.

The voltage control loop is internally compensated to provide enough phase margin for stable operation with the

full battery voltage range and up to 1 A.

In boost mode, the cycle-by-cycle current limit is set to 4 A or 2 A (depending on the I²C setting) to provide

protection against short-circuit conditions. If the cycle-by-cycle current limit is active for 8 ms, an overload

condition is detected and the device exits boost mode, and signals an overcurrent fault. Additionally, discharge

current limit (I_LIM(DISCHG)) is active to protect the battery from overload. Synchronous operation and burst mode

are used to maximize efficiency over the full load range.

The bq24260/1/1M/2 will not enter boost mode unless the IN voltage is less than the UVLO. When the boost

function is enabled, the bq24260/1/1M/2 enters a linear mode to bring IN up to the battery voltage. Once V_IN

>

(V_BAT– 1 V), the bq24260/1/1M/2 begins switching and regulates IN up to 5 V. If V_INdoes not rise to within 1 V of

V_BATwithin 8 ms, an overcurrent event is detected and boost mode is exited and a boost mode overcurrent event

is announced, the BOOST_EN bit is reset to 0 and the STAT_x and FAULT_x bits in the Status/ Control register

are updated.

9.4.19.3 Burst Mode During Light Load

In boost mode, the IC operates using burst mode to improve light load efficiency and reduce power loss. During

boost mode, the PWM converter is turned off when the device reaches minimum duty cycle and the output

voltage rises to V_BURST(ENT)threshold. This corresponds to approximately a 75-mA inductor current. The

converter then restarts when V_INfalls to V_BURST(EXT). See Figure 38 in the Application Curves for an example

waveform.

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9.4.19.4 Watchdog Timer in Boost Mode

During boost mode, the watchdog timer is active. The watchdog timer works the same as in charge mode. Write

a 1 to the TMR_RST reset bit in the control register. If the watchdog timer expires, the IC resets the EN_BOOST

bit to 0, signals the fault pulse on the STAT and INT terminals. The FAULT_x bits read "Low Supply Fault" as

this is a higher priority fault than the WD timer.

9.4.19.5 STAT/ INT During Boost Mode

During boost mode, the STAT and INT outputs are high impedance. Under fault conditions, a 128-µs pulse is

sent out to notify the host of the error condition.

9.4.19.6 Protection in Boost Mode

9.4.19.6.1 Output Overvoltage Protection

The bq24260/1/1M/2 contains integrated overvoltage protection on the IN terminal. During boost mode, if an

overvoltage condition is detected (V_IN> V_BOOSTOVP), after deglitch t_{DGL(BOOST_OVP)}, the IC turns off the PWM

converter, resets EN_BOOST bit to 0, sets fault status bits and sends out a fault pulse on STAT and INT. The

converter does not restart when VIN drops to the normal level until the EN_BOOST bit is reset to 1.

9.4.19.6.2 Output Overcurrent Protection

The bq24260/1/1M/2 contains overcurrent protection to prevent the device and battery damage when IN is

overloaded. When an overcurrent condition occurs, the cycle-by-cycle current limit limits the current from the

battery to the load. If the overload condition lasts for 8 ms, the overload fault is detected. When an overload

condition is detected, the bq24260/1/1M/2 turns off the PWM converter, resets EN_BOOST bit to 0, sets the fault

status bits and sends out the fault pulse on STAT and INT. The boost operation starts only after the fault is

cleared and the EN_BOOST bit is reset to 1 using the I²C.

9.4.19.6.3 Battery Voltage Protection

During boost mode, when the battery voltage is below the minimum battery voltage threshold, V_BATUVLO, the IC

turns off the PWM converter, resets EN_BOOST bit to 0, sets fault status bits and sends out a fault pulse on

STAT and INT. Once the battery voltage returns to the acceptable level, the boost starts only after the

EN_BOOST bit is set to 1. Proper operation below 3.3 V down to the V_BATUVLOis not specified.

9.5 Programming

9.5.1 Serial Interface Description

The bq24260 uses an I²C compatible interface to program charge parameters. I²C is a 2-wire serial interface

developed by NXP (formerly Philips Semiconductor, see I²C-Bus Specification, Version 5, October 2012). The

bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA

and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open-drain I/O

terminals, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the

bus. The master is responsible for generating the SCL signal and device addresses. The master also generates

specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits

data on the bus under control of the master device.

The bq24260/1/1M/2 device works as a slave and supports the following data transfer modes, as defined in the

I²C Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to

the battery charge solution, enabling most functions to be programmed to new values depending on the

instantaneous application requirements. The I²C circuitry is powered from IN when a supply is connected. If the

IN supply is not connected, the I²C circuitry is powered from the battery through BAT. The battery voltage must

stay above V_BATUVLOwith no input connected in order to maintain proper operation.

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the

F/S-mode in this document. The bq24260/1/1M/2 device only supports 7-bit addressing. The device 7-bit address

is defined as ‘1101011’ (0x6Bh).

To avoid I²C hang-ups, a timer (t_I2CRESET) runs during I²C transactions. If the transaction takes longer than

t_I2CRESET, any additional commands are ignored and the I²C engine is reset. The timeout is reset with START and

repeated START conditions and stops when a valid STOP condition is sent.

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Programming (continued)

9.5.2 F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in Figure 15. All I²C -compatible devices should

recognize a start condition.

DATA

CLK

S

P

START Condition

STOP Condition

Figure 15. START and STOP Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W

on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires

the SDA line to be stable during the entire high period of the clock pulse (see Figure 16). All devices recognize

the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a

matching address generates an acknowledge (see Figure 17) by pulling the SDA line low during the entire high

period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a

slave has been established.

DATA

CLK

Data Line

Stable;

Data Valid

Change

of Data

Allowed

Figure 16. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the

slave (R/W bit 1. In either case, the receiver needs to acknowledge the data sent by the transmitter. So an

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line

from low to high while the SCL line is high (see Figure 15). This releases the bus and stops the communication

link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of

a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching

address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the

slave I²C logic from remaining in a incorrect state. Attempting to read data from register addresses not listed in

this section will result in 0xFFh being read out.

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Programming (continued)

Data Output

by Transmitter

Not Acknowledge

Acknowledge

Data Output

by Receiver

SCL From

Master

9

8

1

2

Clock Pulse for

Acknowledgement

START

Condition

Figure 17. Acknowledge on the I²C Bus

Recognize START or

REPEATED START

Condition

Recognize STOP or

REPEATED START

Condition

Generate ACKNOWLEDGE

Signal

P

SDA

Acknowledgement

Signal From Slave

MSB

Sr

Address

R/W

SCL

Sr

or

P

S

or

Sr

ACK

Figure 18. Bus Protocol

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9.6 Register Maps

9.6.1 Status/Control Register (READ/WRITE)

Memory location: 00, Reset state: 00xx 0xxx

Figure 19. Status/Control Register

B7(MSB)

B6

0

B5

X

B4

X

B3

0

B2

X

B1

X

B0(LSB)

0

X

R

R/W

R

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2. Status/Control Register Field Descriptions

BIT

FIELD^{(1) (2)}

TYPE

DESCRIPTION

B7(MSB)

TMR_RST

R/W

Write: TMR_RST function, write 1 to reset the watchdog timer (auto clear)

Read: Always 0

(bq24260/1/1M only)

B6

EN_BOOST

R/W

0-Charger Mode

1-Boost Mode (default 0)

B5

B4

STAT_1

STAT_0

R

00-Ready

01-Charge in progress

10-Charge done

11-Fault

B3

EN_SHIPMODE

R/W

0-Normal Operation

1-Ship Mode Enabled (default 0)

B2

B1

FAULT_2

FAULT_1

FAULT_0

R

000-Normal

001-VIN > VOVP or Boost Mode OVP

010- Low Supply connected (VIN<VUVLO or VIN<VSLP) or Boost Mode Overcurrent

011- Thermal Shutdown

B0(LSB)

100-Battery Temperature Fault

101- Timer Fault (watchdog or safety timer)

110-Battery OVP

111-No Battery connected

(1) STAT_x bits show current status. These bits change based on the current condition. When a status change occurs, a single 128-µs

pulse on the STAT and INT outputs occur and the STATx and FAULT_x bits of the status registers are updated in the I²C. Once the

fault is removed, the STATx bits are updated to show the current status.

(2) FAULT_x bits show faults. If a fault occurs, these bits announce the fault and do not clear until read. If more than one fault occurs only

the highest priority fault is shown, ranked from 1 to 8 in the order shown in the table. When a fault occurs, a single 128-µs pulse on the

STAT and INT outputs occur and the STATx and FAULT_x bits of the status registers are updated in the I²C. The FAULT_x bits are not

cleared until they are read in the I²C and the fault condition no longer exists.

EN_BOOST Bit (Operation Mode)

The EN_BOOST bit selects the operation mode for the bq24260/1/1M/2. Write a 1 to enable boost mode

and regulate IN to 5V to supply OTG peripherals. See Boost Mode Operation for more details.

EN_SHIPMODE Bit

Writing the EN_SHIPMODE bit to a 1 latches off the IC, battery FET and BGATE until a high to low

transition on UVLO occurs. This means that if EN_SHIPMODE is written to a 1 while the input is

connected, it must first be removed and then replaced before the battery FET turns on. This allows the

end product with no load on the battery and the end user will enable the device by plugging it into the

adapter. The EN_SHIPMODE bit can be cleared using the I²C interface as well.

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9.6.2 Control Register (READ/WRITE)

Memory location: 01, Reset state: 1xxx 1100 (bq24260/2), 1xxx 1110 (bq24261/1M)

Figure 20. bq24260/2 Control Register

B7(MSB)

B6

X

B5

X

B4

X

B3

1

B2

1

B1

0

B0(LSB)

.0

1

W

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 21. bq24261/1M Control Register

B7(MSB)

B6

X

B5

X

B4

X

B3

1

B2

1

B1

1

B0(LSB)

0

1

W

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3. Control Register Field Descriptions

BIT

FIELD

TYPE

DESCRIPTION

B7(MSB)

RESET

W

Write: 1-Reset all registers to default values

0-No effect

Read: always get 1

B6

B5

B4

IN_LIMIT_2

IN_LIMIT_1

IN_LIMIT _0

R/W

000-USB2.0 host with 100-mA current limit

001-USB3.0 host with 150-mA current limit

010 – USB2.0 host with 500-mA current limit

011 – USB3.0 host/charger with 900-mA current limit

100 – Charger with 1500-mA current limit

101—Charger with 1950-mA current limit

110 – Charger with 2500-mA current limit

111- Charger with 2000-mA current limit (default 000⁽¹⁾

)

B3

B2

EN_STAT

TE

R/W

0-Disable STAT function (STAT only shows faults)

1-Enable STAT function (default 1)

0-Disable charge current termination

1-Enable charge current termination (default 1)

B1

CE

0-Charger enabled

1-Charger is disabled (default 0-bq24260 / 2, 1-bq24261/1M)

B0(LSB)

HZ_MODE

0-Not high impedance mode

1-High impedance mode (default 0)

(1) When in DEFAULT mode, PSEL (bq24261/1M/2) determines the default input current limit.

RESET Bit

The RESET bit in the control register (0x01h) is used to reset all the charge parameters. Write 1 to

RESET bit to reset all the registers to default values and place the bq24260/1/1M/2 into DEFAULT mode

and turn off the watchdog timer. The RESET bit is automatically cleared to zero once the bq24260/1/1M/2

enters DEFAULT mode.

CE Bit (Charge Enable)

The CE bit is used to disable or enable the charge process. A low logic level (0) on this bit enables the

charge and a high logic level (1) disables the charge. When charge is disabled, the SYS output regulates

to V_SYS(REG)and battery is disconnected from the SYS. Supplement mode is available if the system load

demands cannot be met by the supply.

HZ_MODE Bit (High Impedance Mode Enable)

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The HZ_MODE bit is used to disable or enable the high impedance mode. A low logic level (0) on this bit

enables the IC and a high logic level (1) puts the IC in a low quiescent current state called high

impedance mode. When in high impedance mode, the converter is off and the battery FET and BGATE

are on. The load on SYS is supplied by the battery. BGATE is low (external FET turned on) while in high

impedance mode.

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9.6.3 Control/Battery Voltage Register (READ/WRITE)

Memory location: 02, Reset state: 0001 0100 (BQ24260/1/1M), 1000 1100 (bq24262)

Figure 22. bq24260/1/1M Control/Battery Voltage Register

B7(MSB)

B6

0

B5

0

B4

0

B3

1

B2

1

B1

0

B0(LSB)

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 23. bq24262 Control/Battery Voltage Register

B7(MSB)

B6

0

B5

0

B4

1

B3

0

B2

1

B1

0

B0(LSB)

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4. Control/Battery Voltage Register Field Descriptions

BIT

B7(MSB)

B6

FIELD

V_BREG5

TYPE

R/W

DESCRIPTION

Battery Regulation Voltage: 640 mV (default 0)

V_BREG4

Battery Regulation Voltage: 320 mV (default 0)

Battery Regulation Voltage: 160 mV (default 0)

Battery Regulation Voltage: 80 mV (default 1)

Battery Regulation Voltage: 40 mV (default 0)

Battery Regulation Voltage: 20 mV (default 1)

B5

V_BREG3

B4

V_BREG2

B3

V_BREG1

B2

V_BREG0

B1

MOD_FREQ1

MOD_FREQ0

Modify Switching Frequency Target –

00 – No Change to Nominal Frequency Target

01 – +10% Change to Nominal Frequency

10 – -10% Change to Nominal Frequency

11 – NA (default 00)

B0(LSB)

V_BREGBits (Battery Regulation Threshold setting)

Use V_BREGbits to set the battery regulation threshold. The VBATREG is calculated using the following

equation:

indent V_BATREG= 3.5 V + V_BREGCODE × 20 mV

The charge voltage range is 3.5 V to 4.44 V with the offset of 3.5 V and step of 20 mV. The default setting

is 3.6 V for the bq24260 and bq24261 and bq24261M. The default setting is 4.2 V for the bq24262. If a

value greater than 4.44 V is written, the setting goes to 4.44 V. It is recommended to set V_BATREGabove

V_MINSYS

.

MOD_FREQx Bits (Frequency Modification)

The MOD_FREQx bits are used to change the switching frequency by ±10%. This is used for applications

where the 1.5MHz switching frequency noise interferes with other device operation. The frequency may

be modified by ±10% of the nominal frequency.

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9.6.4 Vender/Part/Revision Register (READ only)

Memory location: 03, Reset state: 0100 0110

Figure 24. Vender/Part/Revision Register

B7(MSB)

B6

1

B5

0

B4

0

B3

0

B2

1

B1

1

B0(LSB)

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5. Vender/Part/Revision Register Field Descriptions

BIT

B7(MSB)

B6

FIELD

Vendor2

Vendor1

Vendor0

PN1

TYPE

R

DESCRIPTION

Vender Code: bit 2 (default 0)

Vender Code: bit 1 (default 1)

Vender Code: bit 0 (default 0)

R

B5

R

B4

R

For I²C Address 6Bh: 00 – bq24260/1/1M/2

B3

PN0

R

B2

NA

R

NA

B1

NA

R

B0(LSB)

NA

R

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9.6.5 Battery Termination/Fast Charge Current Register (READ/WRITE)

Memory location: 04, Reset state: 0010 1010

Figure 25. Battery Termination/Fast Charge Current Register

B7(MSB)

B6

0

B5

1

B4

0

B3

1

B2

0

B1

1

B0(LSB)

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. Battery Termination/Fast Charge Current Register Field Descriptions

BIT

B7(MSB)

B6

FIELD

I_CHRG4

I_CHRG3

I_CHRG2

I_CHRG1

I_CHRG0

I_TERM2

I_TERM1

I_TERM0

TYPE

R/W

DESCRIPTION

Charge current 1600 mA – (default 0)

Charge current: 800 mA — (default 0)

B5

Charge current: 400 mA —(default 1)

B4

Charge current: 200 mA — (default 0)

B3

Charge current: 100 mA (default 1)

B2

Termination current sense: 200 mA (default 0)

Termination current sense voltage: 100 mA (default 1)

Termination current sense voltage: 50 mA (default 0)

B1

B0(LSB)

I_CHRGBits (Charge Current Regulation Threshold setting)

Use I_CHRGbits to set the charge current regulation threshold. The charge current is programmable from

500 mA to 3 A in 100 mA steps. The default is 1 A. The I_CHARGEis calculated using the following equation:

indentI_CHARGE= 500 mA + I_CHRGCODE × 100 mA

Any setting programmed above 3 A selects the 3-A setting.

I_TERMBits (Charge Current Termination Threshold setting)

Use I_TERMbits to set the charge current termination threshold. The termination threshold is programmable

from 50 mA to 300 mA in 50-mA steps. The default is 150 mA. The I_TERMis calculated using the following

equation:

indentI_TERM= 50 mA + I_TERMCODE × 50 mA

Any setting programmed above 300 mA selects the 300-mA setting.

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9.6.6 V_IN-DPMVoltage/ MINSYS Status Register

Memory location: 05, Reset state: xx00 x000

Figure 26. V_IN-DPMVoltage/ MINSYS Status Register

B7(MSB)

B6

X

B5

0

B4

0

B3

X

B2

0

B1

0

B0(LSB)

0

X

R

R/W

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. V_IN-DPMVoltage/ MINSYS Status Register Field Descriptions

BIT

FIELD

TYPE

DESCRIPTION

B7(MSB)

MINSYS_STATUS

R

0 – Minimum System Voltage mode is not active

1 – Minimum System Voltage mode is active (low battery

B6

B5

B4

B3

VINDPM_STATUS

LOW_CHG

R

0 – VIN-DPM mode is not active

1 – VIN-DPM mode is active

R/W

R

0 – Normal charge current set by 04h

1 – Low charge current setting 300 mA (default 0)

FORCE_D+D-

CD_STATUS

0 - Detection complete

1 - Force D+/D- detection (bq24260 only)

0 – CD low, IC enabled

1 – CD high, IC disabled

B2

B1

V_INDPM2

V_INDPM1

V_INDPM0

R/W

Input V_IN-DPMvoltage: V_DPMOFF+ 8% (default 0)

Input V_IN-DPMvoltage: V_DPMOFF+ 4% (default 0)

Input V_IN-DPMvoltage: V_DPMOFF+ 2% (default 0)

B0(LSB)

•

V_IN-DPMvoltage offset is programmable using the VINDPM_OFF bit (bit 0 of register 0x06) and default V_IN-DPM

threshold is 4.2 V.

LOW_CHG Bit (Low Charge Mode Enable)

The LOW_CHG bit is used to reduce the charge current to a minimum current. This feature is used by

systems where battery NTC is monitored by the host and requires a reduced charge current setting or by

systems that need a “preconditioning” current for low battery voltages. Write a 1 to this bit to charge at

300 mA. Write a 0 to this bit to charge at the programmed charge current.

V_INDPMBits (V_INDPMThreshold setting)

Use V_INDPMbits to set the V_INDPMregulation threshold. The V_INDPMthreshold is calculated using the

following equation:

indentV_INDPM= V_{INDPM_OFF}+ V_INDPMCODE × 2% × V_{INDPM_OFF}

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9.6.7 Safety Timer/ NTC Monitor Register (READ/WRITE)

Memory location: 06, Reset state: 1001 1xx0

Figure 27. Safety Timer/ NTC Monitor Register

B7(MSB)

B6

0

B5

0

B4

1

B3

1

B2

X

B1

X

B0(LSB)

0

1

R/W

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. Safety Timer/ NTC Monitor Register Field Descriptions

BIT

FIELD

TYPE

DESCRIPTION

B7(MSB)

2XTMR_EN

R/W

0 – Timer not slowed at any time

1 – Timer slowed by 2× when in thermal regulation, V_{IN_DPM}or input current limit

(default 1)

B6

B5

TMR_1

TMR_2

R/W

Safety Timer Time Limit –

00 – 1.25 minute fast charge

01 – 6 hour fast charge

10 – 9 hour fast charge

11 – Disable safety timers (default 00)

(bq24260/1/1M only)

B4

B3

BOOST_ILIM

TS_EN

R/W

0 – 500 mA

1 – 1 A (Default 1)

0 – TS function disabled

1 – TS function enabled (default 1)

B2

B1

TS_FAULT1

TS_FAULT0

R

TS Fault Mode:

00 – Normal, No TS fault

01 – TS temp < T_COLDor TS temp > T_HOT(Charging suspended)

10 – T_COOL> TS temp > T_COLD(Charge current reduced by half)

11 – T_WARM< TS temp < T_HOT(Charge voltage reduced by 100mV)

B0(LSB)

VINDPM_OFF

R/W

0 – 4.2 V

1 – 10.1 V

(Default 0)

BOOST_ILIM Bit (Boost current limit setting)

The BOOST_ILIM bit programs the cycle by cycle current limit threshold for boost operation. The 1-A

setting sets the low side cycle by cycle current limit to 4 A (typical). This ensures that at least 1 A can be

supplied from the boost converter over the entire battery range. The 500-mA setting sets the current limit

to 2 A (typ) to ensure at least 500 mA available from the boost converter. See Output Overcurrent

Protection for more details.

VINDPM_OFF Bit (V_INDPMoffset setting)

The VINDPM_OFF bit programs the offset for the VINDPM function. The 4.2-V setting is intended to work

with a standard 5-V output adapter. The 10.1-V setting supports 12-V adapters and the 12-V output for

the new USB Power Delivery specification (USB PD).

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The bq24260EVM-079 evaluation module (EVM) is a complete charger module for evaluating the bq24260. The

application curves were taken using the bq24260EVM-079. See Related Documentation for details.

The EVM supports both typical application circuits shown below through board options. Figure 28 shows the

bq24261 using PSEL for the input current limit selection. Figure 28 shows the bq24260 using D+/D– for the input

current limit selection. Figure 28 also shows the addition of an external battery FET. This external FET can be

used with the bq24260/1/1M/2 to provide lower loss discharge path from the battery, and is controlled by the

BGATE pin.

10.2 Typical Application

1.5 µH

PMID

SW

10 µF

1 µF

System

Load

0.033 µF

BOOT

SYS

VBUS

D+

IN

D-

10 µF

GND

Optional FET

4.7 µF

BGATE

BAT

DRV

5.62 k

2.2 µF

DRV

1 µF

PGND

TS

PACK+

STAT

TEMP

1.5 k

V_I/O

(1.8 V)

12.4 k

PSEL(bq24261)

USB PHY

PACK-

1.5 k

HOST

INT

SDA

SCL

GPIO

D+

(bq24260)

SDA

SCL

D-

GPIO

CD

Figure 28. bq24260/1 Typical Application Circuit

38

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SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

Typical Application (continued)

10.2.1 Design Requirements

For this example, use the parameters listed in Table 9.

Table 9. Design Requirements

DESIGN PARAMATER

Input Voltage Range

Input Current Limit

EXAMPLE VALUE

4.75 V to 5.25 V nominal, withstand 28 V

2500 mA

4.25 V

Input DPM Threshold

Fast Charge Current

Battery Charge Voltage

Termination Current

3000 mA

4.2 V

50 mA

10.2.2 Detailed Design Procedure

Following the guidance in the next section, the capacitors on IN, PMID, SYS, BAT and BOOT are the minimum

recommended values of 4.7 µF, 1 µF, 10 µF, 1 µF, and 0.033 µF, respectively. It is assumed that at least 10 µF

of additional capacitance is on the SYS rail. To minimize footprint, a 1.5-µH inductor with at least 3.5-A saturation

current is selected. The optional FET, with gate connected at BGATE, only turns on in high-impedance mode (for

example, no input power/battery only) to reduce the losses across the internal battery FET of the IC . See the

bq24261EVM for exact part numbers. Pullup resistors for STAT and INT of 1.5 kΩ were selected per the current

requirements of the LED. The values for the resistor divider on TS were found using Equation 1 and Equation 2,

where RHOT is the resistance of the NTC thermistor at the hot temperature, RCOLD is the resistance of the

thermistor at cold temperature, VDRV = 5 V, VHOT = 0.3 × VDRV and V_COLD= 0.6 x V_DRV

.

Many parameters configurable by the I²C registers can be changed by using the EVM software.

10.2.2.1 Output Inductor and Capacitor Selection Guidelines

When selecting an inductor, several attributes must be examined to find the right part for the application. First,

the inductance value should be selected. The bq2426x is designed to work with 1.5-µH to 2.2-µH inductors. The

chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some

efficiency gain is reached using the 2.2-µH inductor. However, due to the physical size of the inductor, this option

may not be viable. The 1.5-µH inductor provides a good tradeoff between size and efficiency.

Once the inductance has been selected, the peak current must be calculated in order to choose the current

rating of the inductor. Use Equation 5 to calculate the peak current.

%

æ

ö

RIPPPLE

I_PEAK= I_LOAD(MAX)´ 1+

ç

÷

2

è

ø

(5)

The inductor selected must have a saturation current rating greater than or equal to the calculated I_PEAK. Due to

the high currents possible with the bq24260/1/1M/2, a thermal analysis must also be done for the inductor. Many

inductors have 40°C temperature rise rating. This is the DC current that will cause a 40°C temperature rise

above the ambient temperature in the inductor. For this analysis, the typical load current may be used adjusted

for the duty cycle of the load transients. For example, if the application requires a 1.5-A DC load with peaks at

2.5 A 20% of the time, a Δ40°C temperature rise current must be greater than 1.7 A:

I_TEMPRISE= I_LOAD+ D × (I_PEAK– I_LOAD) = 1.5 A + 0.2 × (2.5 A – 1.5 A) = 1.7 A

(6)

The internal loop compensation of the bq24260/1/1M/2 is designed to be stable with 10 µF to 150 µF of local

capacitance but requires at least 20 µF total capacitance on the SYS rail (10 µF local + ≥ 10 µF distributed). The

capacitance on the SYS rail can be higher than 150 µF if distributed amongst the rail. To reduce the output

voltage ripple, a ceramic capacitor with the capacitance between 10 µF and 47 µF is recommended for local

bypass to SYS. If greater than 100 µF effective capacitance is on the SYS rail, place at least 10-µF bypass on

the BAT terminal. Pay special attention to the DC bias characteristics of ceramic capacitors. For small case

sizes, the capacitance can be derated as high as 70% at workable voltages. All capacitances specified in this

data sheet are effective capacitance, not capacitor value.

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SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

www.ti.com

10.2.3 Application Curves

Figure 29. Start-up With No Battery

Figure 30. Battery Detection

Figure 31. Battery Removal

Figure 32. Default Start-up - bq24260

(D+/D– Shorted)

Figure 33. Default Start-up - bq24260

(D+/D– Not Shorted)

Figure 34. VSYS Transient Without Supplement Mode

40

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SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

Figure 36. VSYS Transient With Supplement Mode

Figure 35. VSYS Transient With Supplement Mode

Figure 38. Boost Burst Mode During Light Load

Figure 37. Boost Start-up No Load

Figure 39. Boost Start-up 1-A Load

Figure 40. Boost Transient Response

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SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

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Figure 42. Start-up, 4.2 V

Figure 41. Input OVP Event With INT

42

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SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

11 Power Supply Recommendations

11.1 Requirements for SYS Output

In order to provide an output voltage on SYS, the bq2426x requires either a power supply between 4.2 V and 6 V

input on all versions, 4.2 V and 6.5 V for IN input on bq24262, 4.2 V and 10.5 V on bq24260, and 4.2 and 14 V

on bq24261/M with at least 100 mA current rating connected to IN; or, a single-cell Li-Ion battery with voltage >

VBATUVLO connected to BAT. The source current rating must be at least 2.5 A for the buck converter of the

charger to provide maximum output power to SYS.

11.2 Requirements for Charging

In order for charging to occur the source voltage measured at the IN terminals of the IC, factoring in cable/trace

losses from the source, must be greater than the VINDPM threshold, but less than the maximum values shown

above. The current rating of the source must be higher than the buck converter needs to provide the load on

SYS. For charging at a desired charge current of I_CHRG, V_IN× I_IN× η > V_SYS× (_ISYS+ I_CHRG) where η is the

efficiency estimate from Figure 2 or Figure 3 and VSYS = VBAT when VBAT charges above VMINSYS. The

charger limits I_INto the current limit setting of that input. With ISYS = 0 A, the charger consumes maximum

power at the end of CC mode, when the voltage at the BAT terminal is near VBATREG but ICHRG has not

started to taper off toward ITERM.

12 Layout

12.1 Layout Guidelines

The following provides some guidelines:

•

Place 1-µF input capacitor as close to PMID terminal and PGND terminal as possible to make high-frequency

current loop area as small as possible.

•

Connect the GND of the PMID and IN capacitors as close as possible.

Place 4.7-µF input capacitor as close to IN terminal and PGND terminal as possible to make high-frequency

current loop area as small as possible.

•

The local bypass capacitor from SYS to GND should be connected between the SYS terminal and PGND of

the IC. The intent is to minimize the current path loop area from the SW terminal through the LC filter and

back to the PGND terminal.

Place all decoupling capacitors close to their respective IC terminal and as close as to PGND as possible. Do

not place components such that routing interrupts power stage currents. All small control signals should be

routed away from the high current paths.

The PCB should have a ground plane (return) connected directly to the return of all components through vias.

Two vias per capacitor for power-stage capacitors and one via per capacitor for small-signal components. TI

also recommends putting vias inside the PGND pads for the IC, if possible. A star ground design approach is

typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-

coupling and ground-bounce issues. A single ground plane for this design gives good results.

•

The high-current charge paths into IN, BAT, SYS and from the SW terminals must be sized appropriately for

the maximum charge current in order to avoid voltage drops in these traces. The PGND terminals should be

connected to the ground plane to return current through the internal low-side FET.

For high-current applications, the balls for the power paths should be connected to as much copper in the

board as possible. This allows better thermal performance as the board pulls heat away from the IC.

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SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

www.ti.com

12.2 Layout Example

It is important to pay special attention to the PCB layout. Figure 43 provides a sample layout for the high current

paths of the bq2426xYFF. Figure 44 provides a sample layout for the high current paths of the bq2426xRGE.

PMID and IN

Cap Gnds

close together

PMID

PGND

SW

IN cap close

to IN pin

BOOT

Thermal vias

connect to

PGND

SYS cap

close to

SYS pins

BAT cap close

to BAT pins

Figure 43. Recommended bq2426x PCB Layout for WCSP Package

sp

PGND

SW

PMID

BOOT

PMID and IN

Cap Gnds

Close together

SYS Cap

Close to

SYS Pins

IN Cap

Close to

IN Pin

BAT Cap

Close to

BAT Pins

Thermal

Vias connect

To GND

Figure 44. Recommended bq2426x PCB Layout for QFN Package

44

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www.ti.com

SLUSBU4D –DECEMBER 2013–REVISED APRIL 2015

13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

User's Guide for WCSP Packaged bq24260, bq24261 and bq24262A 3-A Battery Charger Evaluation Module,

SLUUAB0.

User's Guide for QFN Packaged bq24260, bq24261, and bq24262 3-A Battery Charger Evaluation Module,

SLUUAV8.

3A, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger Evaluation Module,

http://www.ti.com/tool/bq24261evm-611.

Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger Evaluation Module,

http://www.ti.com/tool/bq24261evm-079.

EVM Software, SLUC519

13.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 10. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

bq24260

bq24261

bq24262

bq24261M

Click here

13.3 Trademarks

All trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

17-Jun-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ24260RGER

BQ24260RGET

BQ24260YFFR

BQ24260YFFT

BQ24261MRGER

BQ24261MRGET

BQ24261MYFFR

BQ24261MYFFT

BQ24261RGER

BQ24261RGET

BQ24261YFFR

BQ24261YFFT

BQ24262RGER

BQ24262RGET

BQ24262YFFR

BQ24262YFFT

VQFN

RGE

YFF

RGE

YFF

RGE

YFF

RGE

YFF

24

36

24

36

24

36

24

36

3000

250

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

12.4

8.4

4.25

2.54

4.25

2.54

4.25

2.54

4.25

2.54

4.25

2.54

4.25

2.54

4.25

2.54

4.25

2.54

1.15

0.76

1.15

0.76

1.15

0.76

1.15

0.76

8.0

4.0

8.0

4.0

8.0

4.0

8.0

4.0

12.0

8.0

Q2

Q1

Q2

Q1

Q2

Q1

Q2

Q1

DSBGA

VQFN

3000

250

8.4

8.0

3000

250

12.4

8.4

12.0

8.0

VQFN

DSBGA

VQFN

3000

250

8.4

8.0

3000

250

12.4

8.4

12.0

8.0

VQFN

DSBGA

VQFN

3000

250

8.4

8.0

3000

250

12.4

8.4

12.0

8.0

VQFN

DSBGA

3000

250

8.4

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Jun-2015

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ24260RGER

BQ24260RGET

BQ24260YFFR

BQ24260YFFT

BQ24261MRGER

BQ24261MRGET

BQ24261MYFFR

BQ24261MYFFT

BQ24261RGER

BQ24261RGET

BQ24261YFFR

BQ24261YFFT

BQ24262RGER

BQ24262RGET

BQ24262YFFR

BQ24262YFFT

VQFN

RGE

YFF

RGE

YFF

RGE

YFF

RGE

YFF

24

36

24

36

24

36

24

36

3000

250

367.0

210.0

182.0

367.0

210.0

182.0

367.0

210.0

182.0

367.0

210.0

182.0

367.0

185.0

182.0

367.0

185.0

182.0

367.0

185.0

182.0

367.0

185.0

182.0

35.0

20.0

35.0

20.0

35.0

20.0

35.0

20.0

DSBGA

VQFN

3000

250

3000

250

VQFN

DSBGA

VQFN

3000

250

3000

250

VQFN

DSBGA

VQFN

3000

250

3000

250

VQFN

DSBGA

3000

250

Pack Materials-Page 2

PACKAGE OUTLINE

YFF0036

DSBGA - 0.625 mm max height

S

C

A

L

E

4

.

5

0

DIE SIZE BALL GRID ARRAY

B

E

A

BUMP A1

CORNER

D

C

0.625 MAX

SEATING PLANE

0.05 C

BALL TYP

0.30

0.12

2 TYP

SYMM

F

E

D: Max = 2.485 mm, Min =2.425 mm

E: Max = 2.485 mm, Min =2.425 mm

D

C

SYMM

2

TYP

B

A

0.3

0.2

36X

0.015

C A

B

0.4 TYP

1

2

4

5

6

3

0.4 TYP

4222008/A 03/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YFF0036

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

3

36X ( 0.23)

(0.4) TYP

1

2

4

5

6

A

B

C

SYMM

D

E

F

SYMM

LAND PATTERN EXAMPLE

SCALE:25X

0.05 MAX

0.05 MIN

(

0.23)

(

0.23)

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4222008/A 03/2015

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YFF0036

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

36X ( 0.25)

(R0.05) TYP

1

3

4

5

2

6

A

B

(0.4)

TYP

METAL

TYP

C

D

E

F

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

4222008/A 03/2015

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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型号：	BQ24262_15
厂家：	TEXAS INSTRUMENTS
描述：	bq2426x 3-A, 30-V, Host-Controlled Single-Input, Single-Cell Switched-Mode Li-Ion Battery Charger With Power-Path Management and USB-OTG Support 电池
文件：	总56页 (文件大小：6897K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ24262_15 [TI]

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BQ24270YFFT

BQ24271

BQ24271RGER

BQ24271RGET