BQ24259RGET [TI]
具有可调电压 USB OTG 的 I2C 控制型 2A 单节电池 USB NVDC-1 充电器 | RGE | 24 | -40 to 85;
| 型号： | BQ24259RGET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可调电压 USB OTG 的 I2C 控制型 2A 单节电池 USB NVDC-1 充电器 | RGE | 24 | -40 to 85 电池 PC |
| 文件： | 总50页 (文件大小：2506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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bq24259
ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
bq24259 具有窄范围 VDC 电源路径管理和可调节电压 USB OTG 的
I2C 控制的2A 单节 USB 充电器
1
1 特性
•
90% 高效开关模式 2A 充电器
•
•
•
•
针对 LED 或主机处理器的充电状态输出
通过输入电压稳压实现的最大功率跟踪功能
20µA 低电池泄漏电流，支持运输模式
•
3.9V 至 6.2V 单输入 USB 标准充电器，提供 6.4V
过压保护
–
–
输入电压和电流限制支持 USB 2.0 和 USB 3.0
4mm x 4mm 紧凑型超薄四方扁平无引线 (VQFN)-
24 封装
输入电流限值：100mA、150mA、500mA、
900mA、1A、1.5A 和 2A
2 应用
•
•
USB OTG 在电流为 1A 或 1.5A 时的可调输出电压
范围为 4.55V 至 5.5V
•
•
平板电脑，智能手机，网络设备
便携式音频扬声器
–
–
–
快速 OTG 启动（典型值为 22ms）
5V 升压模式效率为 90%
3 说明
精确的 ±15% 断续模式过流保护
bq24259 是一款高度集成的开关模式电池充电管理和
系统电源路径管理器件，适用于各种智能手机和平板电
脑应用中的 单节锂离子和锂聚合物电池的续航。它的
低阻抗电源路径对开关模式运行效率进行了优化、减少
了电池充电时间并延长了放电阶段的电池寿命。具有充
电和系统设置的 I2C 串行接口使得此器件成为一个真正
地灵活解决方案。
窄范围 VDC (NVDC) 电源路径管理
–
–
在无电池或深度电池放电时的即时系统启动
电池充电模式中的理想二极管运行
•
•
•
薄型 1.2mm 电感 1.5MHz 开关频率
I2C 端口用于实现最优系统性能和状态报告
具有或不具有主机管理的自主电池充电
–
–
–
电池充电启用
电池充电预调节
充电终止和再充电
器件信息(1)
器件型号
bq24259
封装
封装尺寸（标称值）
•
•
高精度
VQFN (24)
4.00mm x 4.00mm
–
–
–
–
±0.5% 充电电压调节
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
充电电流调节范围为 ±7%
PSEL 连接 PHY，通过 SDP/DCP 充电并带有可选
BATFET 使能接口
输入电流调节范围为 ±7.5%
USB OTG 升压模式下 ±3% 输出电压调节范围
bq24259
1μH
SYS: 3.5V-4.35V
5V USB
SDP/DCP
高集成
SW
VBUS
10μF
10μF
1μF
PMID
47nF
μF
8.2
–
–
–
–
–
电源路径管理
BTST
REGN
317W (1.5A max)
同步开关 MOSFET
集成电流感测
4.7μF
ILIM
SYS
PGND
2.2kW
阴极负载二极管
内部环路补偿
SYS
BAT
PG
STAT
VREF
10μF
10kW
10kW 10kW
4.2V
•
安全性
Optional
QON
SDA
SCL
INT
Host
PHY
REGN
5.25kW
–
–
–
–
–
针对 OTG 模式中充电和放电的电池温度感测
OTG
CE
电池充电安全定时器
热调节和热关断
TS
31.23kW
10kW
Charge Enable (0°C - 45°C)
PSEL
Thermal Pad
输入和系统过压保护
MOSFET 过流保护
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCF0
bq24259
ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 25
8.5 Programming........................................................... 26
8.6 Register Map........................................................... 29
Application and Implementation ........................ 36
9.1 Application Information............................................ 36
9.2 Typical Application .................................................. 36
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements.............................................. 10
7.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
9
10 Power Supply Recommendations ..................... 40
11 Layout................................................................... 40
11.1 Layout Guidelines ................................................. 40
11.2 Layout Example .................................................... 41
12 器件和文档支持 ..................................................... 42
12.1 器件支持 ............................................................... 42
12.2 社区资源................................................................ 42
12.3 商标....................................................................... 42
12.4 静电放电警告......................................................... 42
12.5 Glossary................................................................ 42
13 机械、封装和可订购信息....................................... 42
8
4 修订历史记录
Changes from Original (November 2015) to Revision A
Page
•
•
已将电路原理图中的引脚“BOOT”更改为“BTST” ..................................................................................................................... 1
Changed pin "BOOT" To: "BTST" in 图 39........................................................................................................................... 36
2
版权 © 2015–2016, Texas Instruments Incorporated
bq24259
www.ti.com.cn
ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
5 说明 （续）
该器件支持 3.9V 至 6.2V USB 输入电源，包括具有 6.4V 过压保护功能的标准 USB 主机端口和 USB 充电端口。
该器件支持 USB 2.0 和 USB 3.0 电源规范，具有输入电流和电压调节功能。为了设定默认输入电流限
值，bq24259 获取系统检测电路（如 USB PHY 器件）中的结果。该器件还具有快速启动功能和高达 1.5A 的精确
限流能力，能够为 VBUS 提供 4.55V 至 5.5V（默认为 5V）的可调电压，支持 USB On-the-Go 运行。
电源路径管理将系统电压调节至稍高于电池电压的水平，但是不会下降至 3.5V 最小系统电压（可编程）以下。借
助于这个特性，即使在电池电量完全耗尽或者电池被拆除时，系统也能保持运行。当达到输入源电流或电压限值
时，电源路径管理自动将充电电流减少为零，然后开始对电池放电，直到满足系统的电源需求。这个充电模式操作
可保证输入源不会过载。
此器件在主机控制不可用时开始且完成一个充电周期。它分三个阶段对电池进行自动充电：预调节、恒定电流和恒
定电压。在充电周期的末尾，当充电电流低于在恒定电压阶段中预设定的限值时，充电器自动终止。之后，当电池
电压下降到低于再充电阈值时，充电器将自动启动另外一个充电周期。
该充电器件针对电池充电和系统运行提供多种安全 功能， 其中包括负温度系数热敏电阻监控、充电安全定时器和
过压/过流保护。当结温超过 120°C（可设定）时，热调节减少充电电流。
STAT 输出报告充电状态和任何故障条件。当故障发生时，INT 立即通知主机。
bq24259 采用 24 引脚 4 x 4mm2 超薄 VQFN 封装。
Copyright © 2015–2016, Texas Instruments Incorporated
3
bq24259
ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
6 Pin Configuration and Functions
RGE Package
24-Pin VQFN With Exposed Thermal Pad
(Top View)
24
23
22
21
20
19
1
2
3
4
5
6
18
17
16
15
14
13
VBUS
PSEL
PG
PGND
PGND
SYS
STAT
SCL
SYS
BAT
SDA
BAT
7
8
9
10
11
12
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
VBUS
PSEL
PG
NUMBER
Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and
PMID with VBUS on source. Place a 1-µF ceramic capacitor from VBUS to PGND and place it as close as possible
to IC.
1, 24
P
I
2
3
Power source selection input. High indicates a USB host source and Low indicates an adapter source.
Open drain active low power good indicator. Connect to the pull up rail via 10-kΩ resistor. LOW indicates a good
input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current limit is
above 30 mA.
O
Open drain charge status output to indicate various charger operation. Connect to the pull up rail via 10-kΩ resistor.
LOW indicates charge in progress. HIGH indicates charge complete or charge disabled. When any fault condition
occurs, STAT pin in the charge blinks at 1 Hz.
STAT
4
O
I2C Interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
I2C Interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
SCL
SDA
5
6
I
I/O
Open-drain Interrupt Output. Connect the INT to a logic rail via 10-kΩ resistor. The INT pin sends active low, 256-µs
pulse to host to report charger device status and fault.
INT
7
O
USB current limit selection pin during buck mode, and active high enable pin during boost mode.
For bq24259, when in buck mode with USB host (PSEL = High), when OTG = High, IIN limit = 500 mA and when
OTG = Low, IIN limit = 100 mA.
I
OTG
8
Digital
The boost mode is activated when the REG01[5] = 1 and OTG pin is High.
Active low Charge Enable pin. Battery charging is enabled when REG01[5:4] = 01 and CE pin = Low. CE pin must
be pulled high or low.
CE
9
I
I
ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 1 V. A resistor is connected from
ILIM pin to ground to set the maximum limit as IINMAX = (1V/RILIM) × KILIM. The actual input current limit is the lower
one set by ILIM and by I2C REG00[2:0]. The minimum input current programmed on ILIM pin is 500 mA.
ILIM
10
Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program
temperature window with a resistor divider from REGN to TS to GND. Charge suspends or Boost disable when TS
pin is out of range. A 103AT-2 thermistor is recommended.
I
TS
11
Analog
BATFET enable control in shipping mode. A logic low to high transition on this pin with minimum 2ms high level
turns on BATFET to exit shipping mode. It has internal 1MΩ (Typ) pull down. For backward compatibility, when
BATFET enable control function is not used, the pin can be a no connect or tied to TS pin (10k NTC thermistor
only). (Refer to Shipping Mode for detail description).
QON
BAT
12
I
Battery connection point to the positive pin of the battery pack. The internal BATFET is connected between BAT
and SYS. Connect a 10 µF closely to the BAT pin.
13,14
P
4
Copyright © 2015–2016, Texas Instruments Incorporated
bq24259
www.ti.com.cn
ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NUMBER
System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls below
the minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage.
SYS
15,16
I
Power ground connection for high-current power converter node. Internally, PGND is connected to the source of the
n-channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the
charger. A single point connection is recommended between power PGND and the analog GND near the IC PGND
pin.
PGND
17,18
P
Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and
the drain of the n-channel LSFET. Connect the 0.047-µF bootstrap capacitor from SW to BTST.
SW
19,20
21
O
P
PWM high side driver positive supply. Internally, the BTST is connected to the anode of the boost-strap diode.
Connect the 0.047-µF bootstrap capacitor from SW to BTST.
BTST
PWM low side driver positive supply output. Internally, REGN is connected to the cathode of the boost-strap diode.
Connect a 4.7-µF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close
to the IC. REGN also serves as bias rail of TS pin.
REGN
PMID
22
23
P
Connected to the drain of the reverse blocking MOSFET and the drain of HSFET. Given the total input capacitance,
connect a 1-µF capacitor on VBUS to PGND, and the recommended 8.2 µF or more on PMID to PGND.
O
P
Exposed pad beneath the IC for heat dissipation. Always solder thermal pad to the board, and have vias on the
thermal pad plane star-connecting to PGND and ground plane for high-current power converter.
Thermal Pad
7 Specifications
7.1 Absolute Maximum Ratings(1)
MIN
–2
MAX
15(2)
15(2)
12
UNIT
VBUS (converter not switching)
V
V
V
V
PMID (converter not switching)
–0.3
–0.3
–0.3
STAT
BTST
12
7
Voltage
(with respect to GND)
SW
–2 8 (Peak for 20ns
duration)
V
BAT, SYS (converter not switching)
–0.3
6
7
V
V
SDA, SCL, INT, OTG, ILIM, REGN, TS, QON,
CE PSEL
–0.3
BTST TO SW
PGND to GND
INT, STAT, PG
–0.3
–0.3
7
0.3
6
V
V
Output sink current
mA
°C
°C
Junction temperature
–40
–65
150
150
Storage temperature range, Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground pin unless otherwise noted.
(2) VBUS is specified up to 16 V for a maximum of 24 hours under no load conditions.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
V
V(ESD)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
±250
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2015–2016, Texas Instruments Incorporated
5
bq24259
ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
7.3 Recommended Operating Conditions
MIN
MAX
UNIT
V
VIN
Input voltage
3.9
6.2(1)
3.5
4.4
2
ISYS
VBAT
Output current (SYS)
A
Battery voltage
V
Fast charging current
A
IBAT
TA
Discharging current with internal MOSFET
Operating free-air temperature range
5.5
85
A
–40
°C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight
layout minimizes switching noise.
7.4 Thermal Information
bq24259
THERMAL METRIC(1)
RGE (VQFN)
24 PIN
32.2
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
29.8
9.1
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
9.1
RθJCbot
2.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
7.5 Electrical Characteristics
V(VBUS_UVLOZ) < V(VBUS) < V(ACOV) and V(VBUS) > V(BAT) + V(SLEEP), TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
QUIESCENT CURRENTS
V(VBUS) < V(UVLO), V(BAT) = 4.2 V, leakage between BAT
and VBUS
5
µA
High-Z Mode, or no VBUS, BATFET disabled
(REG07[5] = 1), –40°C – 85°C
I(BAT)
Battery discharge current (BAT, SW, SYS)
16
20
µA
High-Z Mode, or no VBUS, BATFET enabled
(REG07[5] = 0), –40°C – 85°C
32
15
55
30
3
µA
µA
V(VBUS) = 5 V, High-Z mode, No battery
V(VBUS) > V(UVLO), V(VBUS) > V(BAT), converter not
switching
1.5
mA
I(VBUS)
Input supply current (VBUS)
V(VBUS) > V(UVLO), V(VBUS) > V(BAT), converter switching,
V(BAT) = 3.2 V, ISYS = 0 A
4
3.5
3.5
mA
mA
mA
V(VBUS) > V(UVLO), V(VBUS) > V(BAT), converter switching,
charge disable, V(BAT) = 3.8 V, ISYS = 100 µA
V(BAT) = 4.2 V, Boost mode, I(VBUS) = 0 A, converter
switching
I(BOOST)
Battery discharge current in boost mode
VBUS/BAT POWER UP
V(VBUS_OP)
V(VBUS_UVLOZ)
V(SLEEP)
VBUS operating voltage
3.9
3.6
35
6.2
V
V
VBUS for active I2C, no battery
Sleep mode falling threshold
V(VBUS) rising
V(VBUS) falling, V(VBUS-VBAT)
V(VBUS) rising, V(VBUS-VBAT)
V(VBUS) rising
80
120 mV
350 mV
V(SLEEPZ)
Sleep mode rising threshold
170
6.2
250
V(ACOV)
VBUS over-voltage rising threshold
VBUS over-voltage falling hysteresis
Battery for active I2C, no VBUS
Battery depletion threshold
6.6
V
mV
V
V(ACOV_HYST)
V(BAT_UVLOZ)
V(BAT_DPL)
V(BAT_DPL_HY)
V(VBUS) falling
250
V(BAT) rising
2.3
V(BAT) falling
2.4
2.6
V
Battery depletion rising hysteresis
V(BAT) rising
200
mV
6
版权 © 2015–2016, Texas Instruments Incorporated
bq24259
www.ti.com.cn
ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
Electrical Characteristics (接下页)
V(VBUS_UVLOZ) < V(VBUS) < V(ACOV) and V(VBUS) > V(BAT) + V(SLEEP), TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
3.8
30
MAX UNIT
V(VBUSMIN)
I(BADSRC)
Bad adapter detection threshold
Bad adapter detection current source
V(VBUS) falling
V
mA
POWER PATH MANAGEMENT
V(SYS_MAX) Maximum DC system voltage output
V(SYS_MIN)
BATFET (Q4) off, V(BAT) up to 4.35 V
REG01[3:1] = 101, V(SYS_MIN) = 3.5 V
4.43
V
V
Minimum DC system voltage output
3.5
3.65
35
Top reverse blocking MOSFET on-
resistance between VBUS and PMIID
RON(RBFET)
48 mΩ
TJ = –40°C – 85°C
TJ = -40°C – 125°C
TJ = –40°C – 85°C
TJ = -40°C – 125°C
45
45
67
67
57
Internal top switching MOSFET on-
resistance between PMID and SW
RON(HSFET)
mΩ
65
88
mΩ
98
Internal bottom switching MOSFET on-
resistance between SW and PGND
RON(LSFET)
BATFET forward voltage in supplement
mode
V(FWD)
BAT discharge current 10 mA
30
mV
V(BAT) < V(SYS_MIN) , V(SYS) falling
V(BAT) > V(SYS_MIN) , V(SYS) falling
V(BAT) rising
80
180
3.55
100
mV
mV
V
V(SYS_BAT)
SYS/BAT comparator
V(BATGD)
Battery good comparator rising threshold
Battery good comparator falling threshold
V(BATGD_HYST)
V(BAT) falling
mV
BATTERY CHARGER
V(BAT_REG_ACC) Charge voltage regulation accuracy
V(BAT) = 4.112 V and 4.208 V
–0.5%
-4%
0.5%
V(BAT) = 3.8 V, I(CHG) = 1024 mA, TJ = 25°C
V(BAT) = 3.8 V, I(CHG) = 1024 mA, TJ = -20°C – 125°C
V(BAT) = 3.8 V, ICHG = 1792 mA, TJ = -20°C – 125°C
4%
7%
I(ICHG_REG_ACC)
Fast charge current regulation accuracy
-7%
–10%
10%
V(BAT) = 3.1 V, I(CHG) = 104 mA, REG02 = 03 and
REG02[0] = 1
I(CHG)
Charge current with 20% option on
Battery LOWV falling threshold
Battery LOWV rising threshold
75
2.6
175 mA
V(BATLOWV)
V(BATLOWV_HYST)
Fast charge to precharge, REG04[1] = 1
2.8
3
2.9
3.1
V
V
Precharge to fast charge, REG04[1] = 1
(Typical 200-mV hysteresis)
2.8
I(PRECHG_ACC)
I(TYP_TERM_ACC)
I(TERM_ACC)
V(SHORT)
Precharge current regulation accuracy
Typical termination current
Termination current accuracy
Battery short voltage
V(BAT) = 2.6 V, I(CHG) = 256 mA
I(TERM) = 256 mA, I(CHG) = 2048 mA
I(TERM) = 256 mA, I(CHG) = 2048 mA
V(BAT) falling
–20%
20%
265
mA
–22.5%
22.5%
2.0
200
100
100
20
V
V(SHORT_HYST)
I(SHORT)
Battery Short Voltage hysteresis
Battery short current
V(BAT) rising
mV
mA
mV
ms
V(BAT) < 2.2 V
V(RECHG)
Recharge threshold below VBAT_REG
Recharge deglitch time
V(BAT) falling, REG04[0] = 0
V(BAT) falling, REG04[0] = 0
TJ = 25°C
t(RECHG)
24
28
35
RON(BATFET)
SYS-BAT MOSFET on-resistance
mΩ
TJ = –40°C – 125°C
24
INPUT VOLTAGE/CURRENT REGULATION
V(INDPM_REG_ACC) Input voltage regulation accuracy
-2%
85
2%
USB100
100 mA
150 mA
500 mA
900 mA
USB150
125
440
750
1.3
USB Input current regulation limit, V(BUS)
I(USB_DPM)
=
5 V, current pulled from SW
USB500
USB900
I(ADPT_DPM)
IIN(START)
KILIM
Input current regulation accuracy
Input current limit during system start up
IIN = KILIM/RILIM
I(ADP) = 1.5 A, REG00[2:0] = 101
V(SYS) < 2.2 V
IIN(DPM) = 1.5 A
1.5
A
100
435
mA
395
475 A x Ω
BAT OVERVOLTAGE PROTECTION
V(BATOVP)
Battery overvoltage threshold
V(BAT) rising, as percentage of V(BAT_REG)
V(BAT) falling, as percentage of V(BAT_REG)
104%
2%
V(BATOVP_HYST)
Battery overvoltage hysteresis
Battery overvoltage deglitch time to
disable charge
tBATOVP
1
µs
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Electrical Characteristics (接下页)
V(VBUS_UVLOZ) < V(VBUS) < V(ACOV) and V(VBUS) > V(BAT) + V(SLEEP), TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
THERMAL REGULATION AND THERMAL SHUTDOWN
TJ
Junction temperature regulation accuracy
Thermal shutdown rising temperature
Thermal shutdown hysteresis
REG06[1:0] = 11
120
160
30
1
°C
°C
°C
ms
ms
T(SHUT)
T(SHUT_HYS)
Temperature increasing
Thermal shutdown rising deglitch
Thermal shutdown falling deglitch
Temperature increasing delay
Temperature decreasing delay
1
COLD/HOT THERMISTER COMPARATOR
Cold temperature threshold, TS pin
voltage rising threshold
V(LTF)
Charger suspends charge. as percentage to V(REGN)
As percentage to V(REGN)
73% 73.5%
0.4%
74%
Cold temperature hysteresis, TS pin
voltage falling
V(LTF_HYS)
V(HTF)
Hot temperature TS pin voltage rising
threshold
As percentage to V(REGN)
46.6% 47.2% 48.8%
44.2% 44.7% 45.2%
10
Cut-off temperature TS pin voltage falling
threshold
V(TCO)
As percentage to V(REGN)
Deglitch time for temperature out of range
detection
V(TS) > V(LTF), or V(TS) < V(TCO), or V(TS) < V(HTF)
ms
Cold temperature threshold, TS pin
voltage rising threshold
As percentage to V(REGN) REG02[1] = 0
(Approx. -10°C w/ 103AT)
V(BCOLD0)
75.5%
78.5%
35.5%
32.5%
29.5%
76% 76.5%
1%
As percentage to V(REGN) REG02[1] = 0
(Approx. 1°C w/ 103AT)
V(BCOLD0_HYS)
V(BCOLD1)
V(BCOLD1_HYS)
V(BHOT0)
V(BHOT0_HYS)
V(BHOT1)
V(BHOT1_HYS)
V(BHOT2)
Cold temperature threshold 1, TS pin
voltage rising threshold
As percentage to V(REGN) REG02[1] = 1
(Approx. -20°C w/ 103AT)
79% 79.5%
1%
As percentage to V(REGN) REG02[1] = 1
(Approx. 1°C w/ 103AT)
Hot temperature threshold, TS pin voltage As percentage to V(REGN) REG06[3:2] = 01
falling threshold
36% 36.5%
3%
(Approx. 55°C w/ 103AT)
As percentage to V(REGN) REG06[3:2] = 01
(Approx. 3°C w/ 103AT)
Hot temperature threshold 1, TS pin
voltage falling threshold
As percentage to V(REGN) REG06[3:2] = 00
(Approx. 60°C w/ 103AT)
33% 33.5%
3%
As percentage to V(REGN) REG06[3:2] = 00
(Approx. 3°C w/ 103AT)
Hot temperature threshold 2, TS pin
voltage falling threshold
As percentage to V(REGN) REG06[3:2] = 10
(Approx. 65°C w/ 103AT)
30% 30.5%
3%
As percentage to V(REGN) REG06[3:2] = 10
(Approx. 3°C w/ 103AT)
V(BHOT2_HYS)
CHARGE OVERCURRENT COMPARATOR
HSFET cycle by cycle over-current
I(HSFET_OCP)
4
7.5
A
threshold
LSFET charge under-current falling
threshold
V(LSFET_UCP)
From sync mode to non-sync mode
100
mA
PWM Switching frequency, and digital
clock
FSW
1300
1500
97%
3.6
1700 kHz
D(MAX)
Maximum PWM duty cycle
V(BTST) - V(SW) when LSFET refresh pulse is requested,
V(BUS) = 5 V
V(BTST_REFRESH)
Bootstrap refresh comparator threshold
V
BOOST MODE OPERATION
OTG output voltage
I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V)
I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V)
BAT falling, REG04[1] = 1
REG01[0] = 0
5
V
V(OTG_REG_ACC)
V(OTG_BAT)
I(OTG)
OTG output voltage accuracy
-3%
2.9
1
3%
V
Battery voltage exiting OTG mode
A
OTG mode output current
REG01[0] = 1
1.5
5.8
A
V(OTG_OVP)
OTG over-voltage threshold
Rising threshold
6
V
V(OTG_OVP_HYS)
OTG over-voltage threshold hysteresis
Falling threshold
300
mV
8
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Electrical Characteristics (接下页)
V(VBUS_UVLOZ) < V(VBUS) < V(ACOV) and V(VBUS) > V(BAT) + V(SLEEP), TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
I(OTG_LSOCP)
I(OTG_HSZCP)
LSFET cycle by cycle current limit
HSFET under current falling threshold
5
A
100
1.15
1.70
mA
REG01[0] = 0
REG01[0] = 1
1.00
1.50
1.30
A
I(RBFET_OCP)
REGN LDO
V(REGN)
RBFET overcurrent threshold
1.90
V(VBUS) = 6 V, I(REGN) = 40 mA
V(VBUS) = 5 V, I(REGN) = 20 mA
V(VBUS) = 5 V, V(REGN) = 3.8 V
4.8
4.7
50
5
5.5
V
V
REGN LDO output voltage
REGN LDO current limit
4.8
I(REGN)
mA
LOGIC I/O PIN CHARACTERISTICS (OTG, CE, STAT, QON, PSEL, PG)
VI(LO)
VIH
Input low threshold
0.4
V
V
Input high threshold (CE, STAT, QON,
PSEL, PG)
1.3
1.1
VIH(OTG)
VOUT(LO)
Input high threshold (OTG)
Output low saturation voltage
V
V
Sink current = 5 mA
Pull-up rail 1.8 V
Pull-up rail 3.6 V
0.4
1
High level leakage current (OTG, CE,
STAT , PSEL, PG)
I(BIAS)
I(BIAS)
µA
µA
High level leakage current (QON)
8
I2C INTERFACE (SDA, SCL, INT)
VIH
Input high threshold level
VPULL-UP = 1.8 V, SDA and SCL
VPULL-UP = 1.8 V, SDA and SCL
Sink current = 5 mA
1.3
V
V
VIL
Input low threshold level
Output low threshold level
High-level leakage current
SCL clock frequency
0.4
0.4
1
VOL
I(BIAS)
f(SCL)
V
VPULL-UP = 1.8 V, SDA and SCL
µA
400 kHz
DIGITAL CLOCK AND WATCHDOG TIMER
f(HIZ)
f(DIG)
Digital crude clock
Digital clock
REGN LDO disabled
REGN LDO enabled
15
35
50 kHz
1300
1500
1700 kHz
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7.6 Timing Requirements
MIN
TYP
MAX UNIT
VBUS/BAT POWER UP
tBADSRC
Bad source detection duration
30
ms
BOOST MODE OPERATION
tOTG_OCP_OFF
tOTG_OCP_ON
QON TIMING
tQON
OTG mode over-current protection off cycle time
32
ms
µs
OTG mode over-current protection on cycle time
260
QON pin high time to turn on BATFET
2
ms
s
DIGITAL CLOCK AND WATCHDOG TIMER
REGN LDO disabled
REGN LDO enabled
112
136
160
160
tWDT REG05[5:4] = 11
图 1. I2C-Compatible Interface Timing Diagram
表 1. Table of Figures
7.7 Typical Characteristics
FIGURE
Charging Efficiency vs Charging Current (DCR = 10 mΩ)
System Efficiency vs System Load Current (DCR = 10 mΩ)
Boost Mode Efficiency vs V(BUS) Load Current (DCR = 10 mΩ)
SYS Voltage Regulation vs System Load Current
Boost Mode VBUS Voltage Regulation (Typical Output = 4.998 V, REG06[7:4] = 0111) vs VBUS Load Current
SYS Voltage vs Temperature
图 2
图 3
图 4
图 5
图 6
图 7
图 8
图 9
图 10
BAT Voltage vs Temperature
Input Current Limit vs Temperature
Charge Current vs Package Temperature
10
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0.95
0.95
0.90
0.85
0.80
0.75
0.70
0.90
0.85
0.80
0.75
0.70
0.65
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
3
Charge Current (A)
Load Current (A)
D001
D002
VBUS = 5 V
VBUS = 5 V
图 2. Charge Efficiency vs Charge Current
图 3. System Efficiency
vs System Load Current
100
95
90
85
80
75
70
65
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
SYSMIN = 3.5
SYSMIN = 3.2
SYSMIN = 3.7
VBAT = 3.2V
VBAT = 3.5V
VBAT = 3.8V
60
0
0.5
1
1.5
0
0.5
1
1.5
2
2.5
3
3.5
VBUS Load Current (A)
System Load Current (A)
图 4. Boost Mode Efficiency
图 5. SYS Voltage Regulation
vs VBUS Load Current
vs System Load Current
5.1
5
3.7
3.65
3.6
4.9
4.8
4.7
4.6
3.55
3.5
VBAT = 3.2V
VBAT = 3.5V
VBAT = 3.8V
SYSMIN = 3.5V
100 125 150
4.5
0
0.5
1
1.5
-50
-25
0
25
50
75
VBUS Load Current (A)
Temperature (oC)
Typical Output = 4.998 V, REG06[7:4] = 0111
图 6. Boost Mode VBUS Voltage Regulation
图 7. SYS Voltage vs Temperature
vs VBUS Load Current
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4.4
4.35
4.3
2.5
2
1.5
1
4.25
4.2
IIN = 500mA
IIN = 1.5A
IIN = 2A
0.5
0
VREG = 4.208V
VREG = 4.35V
100 125
4.15
4.1
-50
-25
0
25
50
75
150
-50
-25
0
25
50
75
100
125
150
Temperature (oC)
Temperature (oC)
图 8. BAT Voltage vs Temperature
图 9. Input Current Limit vs Temperature
2.5
TREG = 120C
TREG = 80C
2
1.5
1
0.5
0
60
80
100
120
140
160
Package Temperature (oC)
图 10. Charge Current vs Package Temperature
12
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8 Detailed Description
8.1 Overview
The bq24259 is an I2C controlled power path management device and a single cell Li-Ion battery charger. It
integrates the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side
switching FET (LSFET, Q3), and battery FET (BATFET, Q4) between system and battery. The device also
integrates the bootstrap diode for the high-side gate drive.
8.2 Functional Block Diagram
VBUS
PMID
RBFET (Q1)
VVBUS_UVLOZ
UVLO
Q1 Gate
Control
VBATZ+VSLEEP
SLEEP
ACOV
REGN
BTST
REGN
LDO
EN_HIZ
VACOV
FBO
VBUS
VBUS_OVP_BOOST
Q2_UCP_BOOST
VOTG_OVP
I(Q2)
VINDPM
IOTG_HSZCP
SW
I(Q3)
IOTG_LSOCP
Q3_OCP_BOOST
HSFET (Q2)
CONVERTER
CONTROL
IINDPM
BAT
REGN
BATOVP
IC TJ
TREG
104%xVBAT_REG
BAT
LSFET (Q3)
I(Q2)
ILSFET_UCP
VBAT_REG
PGND
UCP
Q2_OCP
I(Q3)
SYS
IHSFET_OCP
VSYSMIN
EN_HIZ
EN_CHARGE
EN_BOOST
VBTST-SW
ICHG_REG
REFRESH
VBTST_REFRESH
SYS
ICHG
VBAT_REG
ICHG_REG
Q4 Gate
Control
REF
DAC
BATFET (Q4)
IBADSRC
BAD_SRC
IDC
CONVERTER
CONTROL
STATE
BAT
ILIM
IC TJ
TSHUT
TSHUT
USB Host
Adapter
Detection
MACHINE
PSEL
BAT
QON
BAT_GD
USB
Adapter
VBATGD
VBAT_REG - VRECHG
BAT
OTG
INT
RECHRG
ICHG
TERMINATION
CHARGE
CONTROL
STATE
ITERM
BATTERY
THERMISTER
SENSING
SUSPEND
BATLOWV
STAT
PG
TS
VBATLOWV
BAT
MACHINE
I2C
Interface
VSHORT
BAT
BATSHORT
CE
SCL SDA
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8.3 Feature Description
8.3.1 Device Power Up
8.3.1.1 Power-On-Reset (POR)
The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS or VBAT rises
above UVLOZ, the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface
is ready for communication and all the registers are reset to default value. The host can access all the registers
after POR.
8.3.1.2 Power Up from Battery without DC Source
If only battery is present and the voltage is above depletion threshold (VBAT_DEPL), the BATFET turns on and
connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDS(ON) in
BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
8.3.1.2.1 BATFET Turn Off
The BATFET can be forced off by the host through I2C REG07[5]. This bit allows the user to independently turn
off the BATFET when the battery condition becomes abnormal during charging. When BATFET is off, there is no
path to charge or discharge the battery. When battery is not attached, the BATFET should be turned off by
setting REG07[5] to 1 to disable charging and supplement mode.
8.3.1.2.2 Shipping Mode
To extend battery life and minimize power when system is powered off during system idle, shipping, or storage,
the device can turn off BATFET so that the system voltage is zero to minimize the leakage. The BATFET can be
turned off by setting REG07[5] (BATFET_DISABLE) bit.
In order to keep BATFET off during shipping mode, the host has to disable the watchdog timer (REG05[5:4] =
00) and disable BATFET (REG07[5] = 1) at the same time. Once the BATFET is disabled, one of the following
events can turn on BATFET and clear REG07[5] (BATFET_DISABLE) bit.
1. Plug in adapter
2. Write REG07[5] = 0
3. watchdog timer expiration
4. Register reset (REG01[7] = 1)
5. A logic low to high transition on QON pin (refer to 图 11 for detail timing)
Min. 2ms
QON
BATFET Status
Turn off by i2c command
Turn on by QON
REG07[5]=0
REG07[5]=1
图 11. QON Timing
8.3.1.3 Power Up from DC Source
When the DC source plugs in, the charger device checks the input source voltage to turn on REGN LDO and all
the bias circuits. It also checks the input current limit before starts the buck converter.
14
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Feature Description (接下页)
8.3.1.3.1 REGN LDO
The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also
provides bias rail to TS external resistors. The pull-up rail of STAT and PG (bq24259) can be connected to
REGN as well.
The REGN is enabled when all the conditions are valid.
1. VBUS above VVBUS_UVLOZ
2. VBUS above VBAT + VSLEEPZ in buck mode or VBUS below VBAT + VSLEEP in boost mode
3. After typical 220-ms delay (100 ms minimum) is complete
If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The
device draws less than I(VBUS) (15 µA typical) from VBUS during HIZ state. The battery powers up the system
when the device is in HIZ.
8.3.1.3.2 Input Source Qualification
After REGN LDO powers up, the device checks the current capability of the input source. The input source has
to meet the following requirements to start the buck converter.
1. VBUS voltage below V(ACOV) (not in VBUS overvoltage)
2. VBUS voltage above V(BADSRC) (3.8 V typical) when pulling I(BADSRC) (30 mA typical) (poor source detection)
Once the input source passes all the conditions above, the status register REG08[2] goes high and the PG pin
(bq24259) goes low. An INT is asserted to the host.
If the device fails the poor source detection, it will repeat the detection every 2 seconds.
8.3.1.3.3 Input Current Limit Detection
After the PG is LOW (bq24259) or REG08[2] goes HIGH, the charger device always runs input current limit
detection when a DC source plugs in unless the charger is in HIZ during host mode.
The bq24259 sets input current limit through PSEL and OTG pins. After the input current limit detection is done,
the detection result is reported in VBUS_STAT registers (REG08[7:6]) and input current limit is updated in IINLIM
register (REG00[2:0]). In addition, host can write to REG00[2:0] to change the input current limit.
8.3.1.3.4 PSEL/OTG Pins Set Input Current Limit
The bq24259 has PSEL pin which directly takes the USB PHY device output to decide whether the input is USB
host or charging port.
表 2. Input Current Limit Detection
PSEL
HIGH
HIGH
LOW
OTG
LOW
HIGH
—
INPUT CURRENT LIMIT
REG08[7:6]
100 mA
500 mA
3 A
01
01
10
8.3.1.3.5 HIZ State with 100 mA USB Host
In battery charging spec, the good battery threshold is the minimum charge level of a battery to power up the
portable device successfully. When the input source is 100-mA USB host, and the battery is above bat-good
threshold (VBATGD), the device follows battery charging spec and enters high impedance state (HIZ). In HIZ state,
the device is in the lowest quiescent state with REGN LDO and the bias circuits off. The charger device sets
REG00[7] to 1, and the VBUS current during HIZ state will be less than 30 µA. The system is supplied by the
battery.
Once the charger device enters HIZ state in host mode, it stays in HIZ until the host writes REG00[7] = 0. When
the processor host wakes up, it is recommended to first check if the charger is in HIZ state.
In default mode, the charger IC will reset REG00[7] back to 0 when input source is removed. When another
source plugs in, the charger IC will run detection again, and update the input current limit.
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8.3.1.3.6 Force Input Current Limit Detection
While adapter is plugged-in, the host can force the charger device to run input current limit detection by setting
REG07[7] = 1 or when watchdog timeout. During the forced detection, the input current limit is set to 100 mA.
After the detection is completed, REG07[7] will return to 0 by itself and new input current limit is set based on
PSEL/OTG (bq24259).
8.3.1.4 Converter Power-Up
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft-start when ramp up the system rail. When the system rail is below 2.2 V, the input
current limit is forced to 100mA. After the system rises above 2.2 V, the charger device sets the input current
limit set by the lower value between register and ILIM pin.
As a battery charger, the charger deploys a 1.5-MHz step-down switching regulator. The fixed frequency
oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage,
charge current and temperature, simplifying output filter design.
A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-
tooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp
height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.
In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below
minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is
set by the ratio of SYS and VBUS.
8.3.1.5 Boost Mode Operation from Battery
The device supports boost converter operation to deliver power from the battery to other portable devices
through USB port. The boost mode output current rating meets the USB On-The-Go 1-A output requirement. The
maximum output current is 1.5 A. The boost operation can be enabled if the following conditions are valid:
1. BAT above BATLOWV threshold (VBATLOWV set by REG04[1])
2. VBUS less than VBAT + VSLEEP (in sleep mode)
3. Boost mode operation is enabled (OTG pin HIGH and REG01[5:4] = 10)
4. Thermistor Temperature is within boost mode temperature monitor threshold unless BHOT[1:0] is set to 11
(REG06[1:0]) to disable this monitor function
5. After 30 ms delay from boost mode enable
In boost mode, the device employs a 1.5-MHz step-up switching regulator. Similar to buck operation, the device
switches from PWM operation to PFM operation at light load to improve efficiency.
During boost mode, the status register REG08[7:6] is set to 11, the VBUS output is 5 V and the output current
can reach up to 1 A or 1.5 A, selected via I2C (REG01[0]). In addition, the device provides adjustable boost
voltage from 4.55 V to 5.5 V by changing BOOSTV bits in REG06[7:4]
Any fault during boost operation, including VBUS over-voltage or over-current, sets the fault register REG09[6] to
1 and an INT is asserted.
8.3.2 Power Path Management
The device accommodates a wide range of input sources from USB, wall adapter, to car battery. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.
8.3.2.1 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The
minimum system voltage is set by REG01[3:1]. Even with a fully depleted battery, the system is regulated above
the minimum system voltage (default 3.5 V).
16
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When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),
and the system is 150 mV above the minimum system voltage setting. As the battery voltage rises above the
minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the
VDS of BATFET. The status register REG08[0] goes high when the system is in minimum system voltage
regulation.
When the battery charging is disabled or terminated, and the battery voltage is above the minimum system
voltage setting, the system is always regulated at 70 mV above the battery voltage.
4.5
4.3
Charge Enabled
4.1
Charge Disabled
3.9
3.7
3.5
Minimum System Voltage Setting
3.3
3.1
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
BAT (V)
图 12. V(SYS) vs V(BAT)
8.3.2.2 Dynamic Power Management
To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic
Power Management (DPM), which continuously monitors the input current and input voltage.
When input source is over-loaded, either the current exceeds the input current limit (REG00[2:0]) or the voltage
falls below the input voltage limit (REG00[6:3]). The device then reduces the charge current until the input current
falls below the input current limit and the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to
drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement
mode where the BATFET turns on and battery starts discharging so that the system is supported from both the
input source and battery.
During DPM mode (either VIN(DPM) or IIN(DPM)), the status register REG08[3] will go high.
图 13 shows the DPM response with 5-V/1.2-A adapter, 3.2-V battery, 2-A charge current and 3.4-V minimum
system voltage setting.
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Voltage
5V
VBUS
SYS
BAT
3.6V
3.4V
3.2V
3.18V
Current
ICHG
IIN
2.3A
2.0A
ISYS
1.5A
1.0A
0.5A
-0.7A
DPM
DPM
Supplement
图 13. DPM Response
8.3.2.3 Supplement Mode
When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is
regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30 mV when the current is low.
This prevents oscillation from entering and exiting the supplement mode. As the discharge current increases, the
BATFET gate is regulated with a higher voltage to reduce RDS(ON) until the BATFET is in full conduction. At this
point onwards, the BATFET VDS linearly increases with discharge current. 图 14 shows the V-I curve of the
BATFET gate regulation operation. BATFET turns off to exit supplement mode when the battery is below battery
depletion threshold.
3.0
2.5
2.0
1.5
1.0
0.5
0
0
10 20 30 40 50 60 70 80
V(BAT-SYS) (mV)
图 14. BATFET V-I Curve
18
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ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
8.3.3 Battery Charging Management
The device charges 1-cell Li-Ion battery with up to 2-A charge current for high capacity tablet battery. The 24-mΩ
BATFET improves charging efficiency and minimizes the voltage drop during discharging.
8.3.3.1 Autonomous Charging Cycle
With battery charging enabled at POR (REG01[5:4] = 01), the charger device complete a charging cycle without
host involvement. The device default charging parameters are listed in 表 3.
表 3. Charging Parameter Default Setting
DEFAULT MODE
Charging voltage
Charging current
Pre-charge current
Termination current
Temperature profile
Safety timer
bq24259
4.208 V
2.048 A
128 mA
256 mA
Hot/Cold
12 hours(1)
(1) See Charging Safety Timer for more information.
A new charge cycle starts when the following conditions are valid:
•
•
•
•
•
Converter starts
Battery charging is enabled by I2C register bit (REG01[5:4]) = 01 and CE is low
No thermistor fault on TS
No safety timer fault
BATFET is not forced to turn off (REG07[5])
The charger device automatically terminates the charging cycle when the charging current is below termination
threshold and charge voltage is above recharge threshold. When a full battery voltage is discharged below
recharge threshold (REG04[0]), the device automatically starts another charging cycle. After the charge done,
either toggle CE pin or REG01[5:4] will initiate a new charging cycle.
The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH)
or charging fault (Blinking). The status register REG08[5:4] indicates the different charging phases: 00-charging
disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a
charging cycle is complete, an INT is asserted to notify the host.
The host can always control the charging operation and optimize the charging parameters by writing to the
registers through I2C.
8.3.3.2 Battery Charging Profile
The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the
beginning of a charging cycle, the device checks the battery voltage and applies current.
表 4. Charging Current Setting
VBAT
CHARGING CURRENT
REG DEFAULT SETTING
REG08[5:4]
V(BAT) < V(SHORT)
(Typical 2 V)
100 mA
–
01
VSHORT ≤ VBAT < V(BATLOWV)
(Typical 2 V ≤ V(BAT) < 3 V)
REG03[7:4]
REG02[7:2]
128 mA
01
10
V(BAT) ≥ V(BATLOWV)
2048 mA
(Typical V(BAT) ≥ 3 V)
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If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will
be less than the programmed value. In this case, termination is temporarily disabled and the charging safety
timer is counted at half the clock rate.
Regulation Voltage
(3.5 V – 4.4 V)
Battery Voltage
Fast Charge Current
(500 mA - 2048 mA)
Charge Current
V
BAT_LOWV (2.8 V / 3 V)
V
(BAT_SHORT) (2 V)
I
(PRECHARGE) (128 mA - 2048 mA)
(TERMINATION) (128 mA - 2048 mA)
(BATSHORT) (100 mA)
I
I
Fast Charge and Voltage Regulation
Trickle Charge Pre-charge
Safety Timer
Expiration
图 15. Battery Charging Profile
8.3.3.3 Thermistor Qualification
The charger device provides a single thermistor input for battery temperature monitor.
8.3.3.3.1 Cold/Hot Temperature Window
The device continuously monitors battery temperature by measuring the voltage between the TS pin and ground,
typically determined by a negative temperature coefficient thermistor and an external voltage divider. The device
compares this voltage against its internal thresholds to determine if charge or boost is allowed.
To initiate a charge cycle, the battery temperature must be within the V(LTF) to V(HTF) thresholds. During the
charge cycle the battery temperature must be within the V(LTF) to V(TCO) thresholds, else the device suspends
charging and waits until the battery temperature is within the V(LTF) to V(HTF) range.
For battery protection during boost mode, the device monitors the battery temperature to be within the V(BCOLDx)
to VB(HOTx) thresholds unless boost mode temperature is disabled by setting BHOT bits (REG06[3:2]) to 11.
When temperature is outside of the temperature thresholds, the boost mode is suspended and REG08[7:6] bits
(VBUS_STAT) are set to 00. Once temperature returns within thresholds, the boost mode is recovered.
REGN
bq24259
RT1
TS
RTH
RT2
103AT
图 16. TS Resistor Network
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When the TS fault occurs, the fault register REG09[2:0] indicates the actual condition on each TS pin and an INT
is asserted to the host. The STAT pin indicates the fault when charging is suspended.
TEMPERATURE RANGE
TEMPERATURE RANGE TO
INITIATE CHARGE
DURING A CHARGE CYCLE
VREF
VREF
CHARGE SUSPENDED
CHARGE SUSPENDED
VLTF
VLTF
VLTFH
VLTFH
CHARGE at full C
CHARGE at full C
VHTF
VTCO
CHARGE SUSPENDED
CHARGE SUSPENDED
AGND
AGND
图 17. TS Pin Thermistor Sense Thresholds in Charge Mode
Temperature Range to
Boost
VREF
Boost Disable
V
(BCOLDx)
( -20ºC / -10ºC)
Boost Enable
V
(BHOTx)
(55ºC / 60ºC / 65ºC)
Boost Disable
AGND
图 18. TS Pin Thermistor Sense Thresholds in Boost Mode
Assuming a 103AT NTC thermistor is used on the battery pack 图 17, the value RT1 and RT2 can be determined
by using the following equation:
æ
ç
è
ö
÷
ø
1
1
VVREF ´RTHCOLD ´RTHHOT
´
-
VLTF VTCO
RT2 =
æ
ç
è
ö
æ
ç
è
ö
VVREF
VVREF
RTHHOT
´
-1 - RTH
´
-1
÷
÷
COLD
VTCO
VLTF
ø
ø
VVREF
-1
VLTF
RT1=
1
1
+
RT2 RTHCOLD
(1)
21
Select 0°C to 45°C range for Li-ion or Li-polymer battery,
RTHCOLD = 27.28 kΩ
RTHHOT = 4.911 kΩ
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RT1 = 5.25 kΩ
RT2 = 31.23 kΩ
8.3.3.4 Charging Termination
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is complete, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn back on to engage supplement mode.
When termination occurs, the status register REG08[5:4] is 11, and an INT is asserted to the host. Termination is
temporarily disabled if the charger device is in input current/voltage regulation or thermal regulation. Termination
can be disabled by writing 0 to REG05[7].
8.3.3.4.1 Termination When REG02[0] = 1
When REG02[0] is HIGH to reduce the charging current by 80%, the charging current could be less than the
termination current. The charger device termination function should be disabled. When the battery is charged to
fully capacity, the host disables charging through CE pin or REG01[5:4].
8.3.3.5 Charging Safety Timer
The device has safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety
timer is 4 hours when the battery is below batlowv threshold. The user can program fast charge safety timer
(default 12 hours) through I2C (REG05[2:1]). When safety timer expires, the fault register REG09[5:4] goes 11
and an INT is asserted to the host. The safety timer feature can be disabled via I2C (REG05[3]).
The following actions restart the safety timer after safety timer expires:
•
•
•
Toggle the CE pin HIGH to LOW to HIGH (charge enable)
Write REG01[5:4] from 00 to 01 (charge enable)
Write REG05[3] from 0 to 1 (safety timer enable)
During input voltage/current regulation, thermal regulation, or FORCE_20PCT bit (REG02[0]) is set , the safety
timer counting at half clock rate since the actual charge current is likely to be below the register setting. For
example, if the charger is in input current regulation (IINDPM) throughout the whole charging cycle, and the
safety time is set to 5 hours, the safety timer will expire in 10 hours. This feature can be disabled by writing 0 to
REG07[6].
8.3.3.5.1 Safety Timer Configuration Change
When safety timer value needs to be changed, it is recommended that the timer is disabled first before new
configuration is written to REG05[2:1]. The safety timer can be disable by writing 1 to REG05[3]. This ensures
the safety timer restart counting after new value is configured.
8.3.3.6 USB Timer When Charging from USB100 mA Source
The total charging time in default mode from USB100 mA source is limited by a 45-min max timer. At the end of
the timer, the device stops the converter and goes to HIZ.
8.3.4 Status Outputs (PG, STAT, and INT)
8.3.4.1 Power Good Indicator (PG)
In bq24259,PG goes LOW to indicate a good input source when:
1. VBUS above V(BUS_UVLO)
2. VBUS above battery (not in sleep)
3. VBUS below V(ACOV) threshold
4. VBUS above V(BUS_MIN) when IBADSRC current is applied (not a poor source)
8.3.4.2 Charging Status Indicator (STAT)
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as the application
diagram shows.
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表 5. STAT Pin State
CHARGING STATE
STAT
LOW
HIGH
HIGH
Charging in progress (including recharge)
Charging complete
Sleep mode, charge disable
8.3.4.3 Interrupt to Host (INT)
In some applications, the host does not always monitor the charger operation. The INT notifies the system on the
device operation. The following events will generate a 256-µs INT pulse.
1. USB/adapter source identified (through PSEL detection and OTG pin)
2. Good input source detected
–
–
–
not in sleep
VBUS below VACOV threshold
current limit above IBADSRC
3. Input removed or VBUS above VACOV threshold
4. Charge Complete
5. Any FAULT event in REG09
For the first four events, INT pulse is always generated. For the last event, when a fault occurs, the charger
device sends out INT and latches the fault state in REG09 until the host reads the fault register. If a prior fault
exists, the charger device would not send any INT upon new faults except NTC fault (REG09[2:0]). The NTC
fault is not latched and always reports the current thermistor conditions. In order to read the current fault status,
the host has to read REG09 two times consecutively. The 1st reads fault register status from the last read and
the 2nd reads the current fault register status.
8.3.5 Protections
8.3.5.1 Input Current Limit on ILIM
For safe operation, the device has an additional hardware pin on ILIM to limit maximum input current on ILIM pin.
The input maximum current is set by a resistor from ILIM pin to ground as:
1V
I
=
´KLIM
INMAX
RILIM
(2)
The actual input current limit is the lower value between ILIM setting and register setting (REG00[2:0]). For
example, if the register setting is 111 for 2 A, and ILIM has a 316-Ω resistor to ground for 1.5 A, the input current
limit is 1.5 A. ILIM pin can be used to set the input current limit rather than the register settings.
The device regulates ILIM pin at 1 V. If ILIM voltage exceeds 1 V, the device enters input current regulation
(Refer to the Dynamic Power Management section).
The voltage on ILIM pin is proportional to the input current. ILIM pin can be used to monitor the input current
following 公式 3:
V
ILIM
I
=
´I
INMAX
IN
1V
(3)
For example, if ILIM pin sets 2 A, and the ILIM voltage is 0.75 V, the actual input current 1.5 A. If ILIM pin is
open, the input current is limited to zero since ILIM voltage floats above 1 V. If ILIM pin is short, the input current
limit is set by the register.
8.3.5.2 Thermal Regulation and Thermal Shutdown
During charge operation, the device monitors the internal junction temperature TJ to avoid overheat the chip and
limits the IC surface temperature. When the internal junction temperature exceeds the preset limit (REG06[1:0]),
the device lowers down the charge current. The wide thermal regulation range from 60°C to 120°C allows the
user to optimize the system thermal performance.
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During thermal regulation, the actual charging current is usually below the programmed battery charging current.
Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register REG08[1]
goes high.
Additionally, the device has thermal shutdown to turn off the converter. The fault register REG09[5:4] is 10 and
an INT is asserted to the host.
8.3.5.3 Voltage and Current Monitoring in Buck Mode
The device closely monitors the input and system voltage, as well as HSFET current for safe buck mode
operation.
8.3.5.3.1 Input Over Voltage (ACOV)
The maximum input voltage for buck mode operation is V(VBUS_OP). If VBUS voltage exceeds V(ACOV), the device
stops switching immediately. During input over voltage (ACOV), the fault register REG09[5:4] will be set to 01. An
INT is asserted to the host.
8.3.5.3.2 System Over Voltage Protection (SYSOVP)
The charger device clamps the system voltage during load transient so that the components connect to system
would not be damaged due to high voltage. When SYSOVP is detected, the converter stops immediately to
clamp the overshoot.
8.3.5.4 Voltage and Current Monitoring in Boost Mode
The charger device closely monitors the VBUS voltage, as well as LSFET current to ensure safe boost mode
operation.
8.3.5.4.1 Over Current Protection
The charger device closely monitors the RBFET (Q1) and LSFET (Q3) current to ensure safe boost mode
operation. During over-current condition, the device will operate in hiccup mode for protection. While in hiccup
mode cycle, the device turns off RBFET for tOTG_OCP_OFF (32 ms typical) and turns on RBFET for tOTG_OCP_ON
(260 us typical) in an attempt to restart. If the over-current condition is removed, the boost converter will maintain
the RBFET on state and the VBUS OTG output will operate normally. When over-current condition continues to
exist, the device will repeat the hiccup cycle until overcurrent condition is removed. When overcurrent condition is
detected, the fault register bit BOOST_FAULT (REG09[6]) is set high to indicate fault in boost operation. An INT
is asserted to the host.
8.3.5.4.2 VBUS Over Voltage Protection
When an adapter plugs in during boost mode, the VBUS voltage will rise above regulation target. Once the
VBUS voltage exceeds VOTG_OVP, the device stops switching and the device exits boost mode. During the over-
voltage, the fault register bit BOOST_FAULT (REG09[6]) is set high to indicate fault in boost operation. An INT is
asserted to the host.
8.3.5.5 Battery Protection
8.3.5.5.1 Battery Over-Voltage Protection (BATOVP)
The battery over-voltage limit is clamped at V(BAT_OVP) (4% nominal) above the battery regulation voltage. When
battery over voltage occurs, the charger device immediately disables charge. The fault register REG09[3] goes
high and an INT is asserted to the host.
8.3.5.5.2 Battery Short Protection
If the battery voltage falls below V(SHORT) (2 V typical), the device immediately turns off BATFET to disable the
battery charging or supplement mode. 1 ms later, the BATFET turns on and charge the battery with 100-mA
current. The device does not turn on BATFET to discharge a battery that is below 2.5 V.
24
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8.4 Device Functional Modes
8.4.1 Host Mode and Default Mode
The device is a host controlled device, but it can operate in default mode without host management. In default
mode, the device can be used as an autonomous charger with no host or with host in sleep.
When the charger is in default mode, REG09[7] is HIGH. When the charger is in host mode, REG09[7] is LOW.
After power-on-reset, the device starts in watchdog timer expiration state, or default mode. All the registers are in
the default settings. The device keeps charging the battery by default with 12-hour fast charging safety timer. At
the end of the 12 hours, the charging is stopped and the buck converter continues to operate to supply system
load.
Any write command to device transitions the device from default mode to host mode. All the device parameters
can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by
writing 1 to REG01[6] before the watchdog timer expires (REG05[5:4]), or disable watchdog timer by setting
REG05[5:4] = 00.
When the host changes watchdog timer configuration (REG05[5:4]), it is recommended to first disable watchdog
by writing 00 to REG05[5:4] and then change the watchdog to new timer values. This ensures the watchdog
timer is restarted after new value is written.
POR
watchdog timer expired
Reset registers
I2C interface enabled
Host Mode
Start watchdog timer
Host programs registers
Y
I2C Write?
N
Default Mode
Reset watchdog timer
Reset registers
Y
N
Reset REG01
bit[6]?
N
Y
N
I2C Write?
Y
Watchdog Timer
Expired?
图 19. Watchdog Timer Flow Chart
8.4.1.1 Plug in USB100 mA Source with Good Battery
When the input source is detected as 100 mA USB host, and the battery voltage is above batgood threshold
(V(BATGD)), the charger device enters HIZ state to meet the battery charging spec requirement.
If the charger device is in host mode, it will stay in HIZ state even after the USB100 mA source is removed, and
the adapter plugs in. During the HIZ state, REG00[7] is set HIGH and the system load is supplied from battery. It
is recommended that the processor host always checks if the charger IC is in HIZ state when it wakes up. The
host can write REG00[7] to 0 to exit HIZ state.
If the charger is in default mode, when the DC source is removed, the charger device will get out of HIZ state
automatically. When the input source plugs in again, the charger IC runs detection on the input source and
update the input current limit.
8.4.1.2 USB Timer When Charging from USB100 mA Source
The total charging time in default mode from USB100 mA source is limited by a 45-min max timer. At the end of
the timer, the device stops the converter and goes to HIZ.
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8.5 Programming
8.5.1 Serial Interface
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2C is a bi-directional 2-wire serial interface. Only two bus lines are required: a serial data line
(SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data
transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to
permit that transfer. At that time, any device addressed is considered a slave.
The device operates as a slave device with address 6BH, receiving control inputs from the master device like
micro controller or a digital signal processor. The I2C interface supports both standard mode (up to 100 kbits),
and fast mode (up to 400 kbits).
Both SDA and SCL are bi-directional lines, connecting to the positive supply voltage via a current source or pull-
up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.
8.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
SDA
SCL
Change
of data
allowed
Data line stable;
Data valid
图 20. Bit Transfer on the I2C Bus
8.5.1.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
SDA
SCL
SDA
SCL
STOP (P)
START (S)
图 21. START and STOP Conditions
26
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Programming (接下页)
8.5.1.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data
transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
Acknowledgement
Acknowledgement
signal from receiver
signal from slave
MSB
SDA
S or Sr
1
2
7
8
9
1
2
8
9
P or Sr
SCL
ACK
ACK
START or
Repeated
STOP or
Repeated
START
START
图 22. Data Transfer on the I2C Bus
8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge 9th clock pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
8.5.1.5 Slave Address and Data Direction Bit
After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction
bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
SDA
S
8
9
8
9
8
9
P
SCL
1-7
1-7
1-7
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP
START
图 23. Complete Data Transfer
8.5.1.5.1 Single Read and Write
1
8
1
1
7
1
0
1
1
8
Slave Address
ACK
Reg Addr
ACK
P
S
ACK
Data Addr
图 24. Single Write
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Programming (接下页)
1
8
1
1
1
7
1
0
1
1
1
7
Slave Address
ACK
Reg Addr
ACK
S
S
ACK
Slave Address
1
1
8
P
Data
NCK
图 25. Single Read
If the register address is not defined, the charger IC send back NACK and go back to the idle state.
8.5.1.5.2 Multi-Read and Multi-Write
The charger device supports multi-read and multi-write on REG00 through REG08.
1
8
7
1
0
1
1
Slave Address
ACK
Reg Addr
ACK
S
1
8
1
8
1
8
1
Slave Address
ACK
Data to Addr+1
ACK
Data to Addr+1
ACK
P
图 26. Multi-Write
1
8
1
7
1
0
1
1
7
1
1
Slave Address
Slave Address
ACK
Reg Addr
ACK
1
ACK
S
S
8
1
8
1
8
1
1
Data @ Addr
ACK
Data @ Addr+1
ACK
Data @ Addr+1
ACK
P
图 27. Multi-Read
The fault register REG09 locks the previous fault and only clears it after the register is read. For example, if
Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the fault when it
is read the first time, but returns to normal when it is read the second time. To verify real time fault, the fault
register REG09 should be read twice to get the real condition. In addition, the fault register REG09 does not
support multi-read or multi-write.
REG09 is a fault register. It keeps all the fault information from last read until the host issues a new read. For
example, if there is a TS fault but gets recovered immediately, the host still sees TS fault during the first read. In
order to get the fault information at present, the host has to read REG09 for the second time. REG09 does not
support multi-read and multi-write.
28
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ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
8.6 Register Map
8.6.1 I2C Registers
Address: 6BH. REG00-07 support Read and Write. REG08-0A are Read only.
8.6.1.1 Input Source Control Register REG00 [reset = 00110xxx, or 3x]
图 28. Input Source Control Register REG00 Format
7
6
5
4
3
2
1
0
EN_HIZ
R/W
VINDPM[3]
R/W
VINDPM[2]
R/W
VINDPM[1]
R/W
VINDPM[0]
R/W
IINLIM[2]
R/W
IINLIM[1]
R/W
IINLIM[0]
R/W
LEGEND: R/W = Read/Write
表 6. Input Source Control Register REG00 Field Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
NOTE
Bit 7
EN_HIZ
R/W
0
0 – Disable, 1 – Enable
Default: Disable (0)
Input Voltage Limit
Bit 6
Bit 5
Bit 4
Bit 3
VINDPM[3]
VINDPM[2]
VINDPM[1]
VINDPM[0]
R/W
R/W
R/W
R/W
0
1
1
0
640 mV
320 mV
160 mV
80 mV
Offset 3.88 V, Range: 3.88 V – 5.08 V
Default: 4.36 V (0110)
Input Current Limit (Actual input current limit is the lower of I2C and ILIM)
Bit 2
Bit 1
Bit 0
IINLIM[2]
IINLIM[1]
IINLIM[0]
R/W
R/W
R/W
x
x
x
000 – 100 mA,
001 – 150 mA,
010 – 500 mA,
011 – 900 mA,
100 – 1 A,
PSEL = Lo : 3 A (111)
PSEL = Hi : 100 mA (000) (OTG pin = Lo) or
500 mA (OTG pin = Hi)
101 – 1.5 A,
110 - 2 A
111 - 3 A
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8.6.1.2 Power-On Configuration Register REG01 [reset = 00011011, or 0x1B]
图 29. Power-On Configuration Register REG01 Format
7
6
5
4
3
2
1
0
I2C Watchdog
Timer Reset
Register Reset
R/W
OTG_CONFIG CHG_CONFIG
R/W R/W
SYS_MIN[2]
R/W
SYS_MIN[1]
R/W
SYS_MIN[0]
R/W
BOOST_LIM
R/W
R/W
LEGEND: R/W = Read/Write
表 7. Power-On Configuration Register REG01 Field Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
NOTE
Bit 7
Register Reset R/W
0
0 – Keep current register setting,
1 – Reset to default
Default: Keep current register setting (0)
Note: Register Reset bit does not reset
device to default mode
Bit 6
I2C Watchdog R/W
Timer Reset
0
0 – Normal ; 1 – Reset
Default: Normal (0)
Note: Consecutive I2C watchdog timer
reset requires minimum 20-µs delay
Charger Configuration
Bit 5
OTG_CONFIG R/W
0
1
0 – OTG Disable; 1 – OTG Enable
0- Charge Disable; 1- Charge Enable
Default: OTG disable (0)
Note: OTG_CONFIG would over-ride
Charge Enable Function in
CHG_CONFIG
Bit 4
CHG_CONFIG R/W
Default: Charge Battery (1)
Minimum System Voltage Limit
Bit 3
Bit 2
Bit 1
Bit 0
SYS_MIN[2]
SYS_MIN[1]
SYS_MIN[0]
BOOST_LIM
R/W
R/W
R/W
R/W
1
0
1
1
0.4 V
Offset: 3.0 V, Range 3.0 V – 3.7 V
Default: 3.5 V (101)
0.2 V
0.1 V
0 – 1 A, 1 – 1.5 A
Default: 1.5 A (1)
30
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8.6.1.3 Charge Current Control Register REG02 [reset = 01100000, or 60]
图 30. Charge Current Control Register REG02 Format
7
6
5
4
3
2
1
0
Reserved
R/W
ICHG[4]
R/W
ICHG[3]
R/W
ICHG[2]
R/W
ICHG[1]
R/W
ICHG[0]
R/W
BCOLD
R/W
FORCE_20PCT
R/W
LEGEND: R/W = Read/Write
表 8. Charge Current Control Register REG02 Field Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
NOTE
Fast Charge Current Limit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reserved
ICHG[4]
ICHG[3]
ICHG[2]
ICHG[1]
ICHG[0]
BCOLD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
0
0
0
0
Reserved. Always read/write 0
Offset: 512 mA
Range: 512 – 2048 mA (000000 –
011000)
Default: 2048 mA (011000)
Note: ICHG higher than 2048 mA is
not supported
1024 mA
512 mA
256 mA
128 mA
64 mA
Set Boost Mode temperature monitor
threshold voltage to disable boost mode
0 – Vbcold0 (Typ. 76% of REGN or -10°C
w/ 103AT thermistor )
Default: Vbcold0 (0)
1 – Vbcold1 (Typ. 79% of REGN or -20°C
w/ 103AT thermistor)
Bit 0
FORCE_20PCT R/W
0
0 – ICHG as Fast Charge Current
(REG02[6:2]) and IPRECH as Pre-
Charge Current (REG03[7:4])
programmed
Default: ICHG as Fast Charge
Current (REG02[6:2]) and IPRECH
as Pre-Charge Current (REG03[7:4])
programmed (0)
1 – ICHG as 20% Fast Charge Current
(REG02[6:2]) and IPRECH as 50% Pre-
Charge Current (REG03[7:4])
programmed
8.6.1.4 Pre-Charge/Termination Current Control Register REG03 [reset = 00010001, or 0x11]
图 31. Pre-Charge/Termination Current Control Register REG03 Format
7
6
5
4
3
2
1
0
IPRECHG[3]
R/W
IPRECHG[2]
R/W
IPRECHG[1]
R/W
IPRECHG[0]
R/W
Reserved
R/W
ITERM[2]
R/W
ITERM[1]
R/W
ITERM[0]
R/W
LEGEND: R/W = Read/Write
表 9. Pre-Charge/Termination Current Control Register REG03 Field Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
NOTE
Pre-Charge Current Limit
Bit 7
Bit 6
Bit 5
Bit 4
IPRECHG[3]
IPRECHG[2]
IPRECHG[1]
IPRECHG[0]
R/W
R/W
R/W
R/W
0
0
0
1
0000: 128 mA; 0001: 128 mA; 0010: Offset: 128 mA,
256 mA; 0011: 384 mA
Range: 128 mA – 2048 mA
0100: 512 mA; 0101: 768 mA; 0110: Default: 128 mA (0001)
896 mA; 0111: 1024 mA
1000: 1152 mA; 1001: 1280 mA;
1010: 1408 mA; 1011: 1536 mA
1100: 1664 mA; 1101: 1792 mA;
1110: 1920 mA; 1111: 2048 mA
Bit 3
Reserved
R/W
0
0 - Reserved
Termination Current Limit
Bit 2
Bit 1
Bit 0
ITERM[2]
ITERM[1]
ITERM[0]
R/W
R/W
R/W
0
0
1
512 mA
256 mA
128 mA
Offset: 128 mA
Range: 128 mA – 1024 mA
Default: 256 mA (001)
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8.6.1.5 Charge Voltage Control Register REG04 [reset = 10110010, or 0xB2]
图 32. Charge Voltage Control Register REG04 Format
7
6
5
4
3
2
1
0
VREG[5]
R/W
VREG[4]
R/W
VREG[3]
R/W
VREG[2]
R/W
VREG[1]
R/W
VREG[0]
R/W
BATLOWV
R/W
VRECHG
R/W
LEGEND: R/W = Read/Write
表 10. Charge Voltage Control Register REG04 Field Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
NOTE
Charge Voltage Limit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
VREG[5]
VREG[4]
VREG[3]
VREG[2]
VREG[1]
VREG[0]
BATLOWV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
1
1
1
1
512 mV
Offset: 3.504 V
Range: 3.504 V – 4.400 V
Default: 4.208 V
256 mV
128 mV
64 mV
32 mV
16 mV
0 – 2.8 V, 1 – 3 V
Default: 3.0 V (1) (pre-charge to fast charge)
Default: 100 mV (0)
Battery Recharge Threshold (below battery regulation voltage)
Bit 0 VRECHG R/W 0 – 100 mV, 1 – 300 mV
0
8.6.1.6 Charge Termination/Timer Control Register REG05 [reset = 10011100, or 0x9C]
图 33. Charge Termination/Timer Control Register REG05 Format
7
6
5
4
3
2
1
0
EN_TERM
R/W
Reserved
R/W
WATCHDOG[1] WATCHDOG[0]
R/W R/W
EN_TIMER
R/W
CHG_TIMER[1] CHG_TIMER[0]
R/W R/W
Reserved
R/W
LEGEND: R/W = Read/Write
表 11. Charge Termination/Timer Control Register REG05 Field Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
NOTE
Charging Termination Enable
Bit 7
Bit 6
EN_TERM
Reserved
R/W
R/W
1
0
0 – Disable, 1 – Enable
0 - Reserved
Default: Enable termination (1)
I2C Watchdog Timer Setting
Bit 5
Bit 4
WATCHDOG[1] R/W
WATCHDOG[0] R/W
0
1
00 – Disable timer, 01 – 40 s, 10 –
80 s, 11 – 160 s
Default: 40 s (01)
Default: Enable (1)
Charging Safety Timer Enable
Bit 3 EN_TIMER R/W
Fast Charge Timer Setting
1
0 – Disable, 1 – Enable
Bit 2
Bit 1
Bit 0
CHG_TIMER[1] R/W
CHG_TIMER[0] R/W
0
1
0
00 – 5 hrs, 01 – 8 hrs, 10 – 12 hrs, Default: 12 hrs (10)
11 – 20 hrs
(See Charging Safety Timer for details)
Reserved
R/W
0 - Reserved
32
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ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
8.6.1.7 Boost Voltage/Thermal Regulation Control Register REG06 [reset = 01110011, or 0x73]
图 34. Boost Voltage/Thermal Regulation Control Register REG06 Format
7
6
5
4
3
2
1
0
BOOSTV[3]
R/W
BOOSTV[2]
R/W
BOOSTV[1]
R/W
BOOSTV[0]
R/W
BHOT[1]
R/W
BHOT[0]
R/W
TREG[1]
R/W
TREG[0]
R/W
LEGEND: R/W = Read/Write
表 12. Boost Voltage/Thermal Regulation Control Register REG06 Field Description
BIT
FIELD
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
RESET
DESCRIPTION
512 mV
NOTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
BOOSTV[3]
BOOSTV[2]
BOOSTV[1]
BOOSTV[0]
BHOT[1]
0
1
1
1
0
0
Offset: 4.55 V
Range: 4.55 V – 5.51 V
Default:4.998 V (0111) Default:4.998 V
(0111)
256 mV
128 mV
64 mV
Set Boost Mode temperature monitor Default: Vbhot1 (00)
threshold voltage to disable boost
mode
Voltage to disable boost mode
00 – Vbhot1 (33% of REGN or 55°C
w/ 103AT thermistor)
Note: For BHOT[1:0] = 11, boost mode
BHOT[0]
operates without temperature monitor
and the NTC_FAULT is generated based
on Vbhot1 threshold
01 – Vbhot0 (36% of REGN or 60°C
w/ 103AT thermistor)
10 – Vbhot2 (30% of REGN or 65°C
w/ 103AT thermistor)
11 – Disable boost mode thermal
protection.
Thermal Regulation Threshold
Bit 1
Bit 0
TREG[1]
TREG[0]
R/W
R/W
1
1
00 – 60°C, 01 – 80°C, 10 – 100°C,
11 – 120°C
Default: 120°C (11)
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8.6.1.8 Misc Operation Control Register REG07 [reset = 01001011, or 4B]
图 35. Misc Operation Control Register REG07 Format
7
6
5
4
3
2
1
0
DPDM_EN
R/W
TMR2X_EN
R/W
BATFET_Disable
R/W
Reserved
R/W
Reserved
R/W
Reserved
R/W
INT_MASK[1]
R/W
INT_MASK[0]
R/W
LEGEND: R/W = Read/Write
表 13. Misc Operation Control Register REG07 Field Description
BIT
Force DPDM detection
Bit 7 DPDM_EN
FIELD
TYPE
RESET
DESCRIPTION
NOTE
R/W
0
0 – Not in Force detection;
1 – Force detection when VBUS
power is presence
Default: Not in Force detection (0), Back to 0
after detection complete
Safety Timer Setting during Input DPM and Thermal Regulation
Bit 6
TMR2X_EN
R/W
1
0 – Safety timer not slowed by 2X
during input DPM or thermal
regulation,
Default: Safety timer slowed by 2X (1)
1 – Safety timer slowed by 2X
during input DPM or thermal
regulation
Force BATFET Off
Bit 5
BATFET_Disable R/W
0
0 – Allow BATFET (Q4) turn on,
1 – Turn off BATFET (Q4)
Default: Allow BATFET (Q4) turn on(0)
Bit 4
Bit 3
Bit 2
Bit 1
Reserved
R/W
R/W
R/W
R/W
0
1
0
1
0 - Reserved
1 - Reserved
0 - Reserved
Reserved
Reserved
INT_MASK[1]
0 – No INT during CHRG_FAULT, Default: INT on CHRG_FAULT (1)
1 – INT on CHRG_FAULT
Bit 0
INT_MASK[0]
R/W
1
0 – No INT during BAT_FAULT,
1 – INT on BAT_FAULT
Default: INT on BAT_FAULT (1)
8.6.1.9 System Status Register REG08
图 36. System Status Register REG08 Format
7
6
5
4
3
DPM_STAT
R
2
PG_STAT
R
1
0
VSYS_STAT
R
VBUS_STAT[1] VBUS_STAT[0] CHRG_STAT[1] CHRG_STAT[0]
THERM_STAT
R
R
R
R
R
LEGEND: R = Read only
表 14. System Status Register REG08 Field Description
BIT
FIELD
TYPE
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VBUS_STAT[1]
VBUS_STAT[0]
CHRG_STAT[1]
CHRG_STAT[0]
DPM_STAT
R
R
R
R
R
R
R
R
00 – Unknown (no input, or DPDM detection incomplete), 01 – USB host, 10 – Adapter port, 11 –
OTG
00 – Not Charging, 01 – Pre-charge (<VBATLOWV), 10 – Fast Charging, 11 – Charge Termination
Done
0 – Not DPM, 1 – VINDPM or IINDPM
0 – Not Power Good, 1 – Power Good
0 – Normal, 1 – In Thermal Regulation
PG_STAT
THERM_STAT
VSYS_STAT
0 – Not in VSYSMIN regulation (BAT > VSYSMIN), 1 – In VSYSMIN regulation (BAT <
VSYSMIN)
34
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ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
8.6.1.10 New Fault Register REG09
图 37. New Fault Register REG09 Format
7
6
5
4
3
2
Reserved
R
1
0
WATCHDOG
_FAULT
OTG_FAULT CHRG_FAULT[1] CHRG_FAULT[0] BAT_FAULT
NTC_FAULT[1]
R
NTC_FAULT[0]
R
R
R
R
R
R
LEGEND: R = Read only
表 15. New Fault Register REG09 Field Description(1)(2)(3)
BIT
FIELD
TYPE
DESCRIPTION
Bit 7
Bit 6
WATCHDOG_FAULT
OTG_FAULT
R
R
0 – Normal, 1- Watchdog timer expiration
0 – Normal, 1 – VBUS overloaded in OTG, or VBUS OVP, or battery is too low (any
conditions that cannot start boost function)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CHRG_FAULT[1]
CHRG_FAULT[0]
BAT_FAULT
R
R
R
R
R
00 – Normal, 01 – Input fault (OVP or bad source), 10 - Thermal shutdown,
11 – Charge Timer Expiration
0 – Normal, 1 – Battery OVP
Reserved – 0
Reserved
NTC_FAULT[1]
0-Normal 1–Cold Note: Cold temperature threshold is different based on device operates in
buck or boost mode
Bit 0
NTC_FAULT[0]
R
0-Normal 1–Hot Note: Hot temperature threshold is different based on device operates in
buck or boost mode
(1) REG09 only supports single byte I2C read.
(2) All register bits in REG09 are latched fault. First time read of REG09 clears the previous fault and second read updates fault register to
any fault that still presents.
(3) When adapter is unplugged, input fault (bad source) in CHRG_FAULT bits[5:4] is set to 01 once.
8.6.1.11 Vender / Part / Revision Status Register REG0A
图 38. Vender / Part / Revision Status Register REG0A Format
7
PN[2]
R
6
PN[1]
R
5
PN[0]
R
4
Reserved
R
3
Reserved
R
2
Rev[2]
R
1
Rev[1]
R
0
Rev[0]
R
LEGEND: R = Read only
表 16. Vender / Part / Revision Status Register REG0A Field Description
BIT
FIELD
PN[2]
TYPE
R
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
001
PN[1]
R
PN[0]
R
Reserved
Reserved
Rev[2]
Rev[1]
Rev[0]
R
0 – Reserved
0 – Reserved
000
R
R
R
R
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A typical application consists of the device configured as an I2C controlled power path management device and a
single cell Li-Ion battery charger for single cell Li-Ion and Li-polymer batteries used in a wide range of tablets and
other portable devices. It integrates an input reverse-blocking FET (RBFET, Q1), high-side switching FET
(HSFET, Q2), low-side switching FET (LSFET, Q3), and BATFET (Q4) between the system and battery. The
device also integrates a bootstrap diode for the high-side gate drive.
9.2 Typical Application
bq24259
1μH
SYS: 3.5V-4.35V
5V USB
SDP/DCP
SW
VBUS
10μF
10μF
1μF
PMID
47nF
μF
8.2
BTST
REGN
317W (1.5A max)
4.7μF
ILIM
SYS
PGND
2.2kW
SYS
BAT
PG
STAT
VREF
10μF
10kW
10kW
10kW
4.2V
Optional
QON
SDA
SCL
INT
Host
PHY
REGN
5.25kW
OTG
CE
TS
31.23kW
10kW
Charge Enable (0°C - 45°C)
PSEL
Thermal Pad
图 39. bq24259 with PSEL from PHY, Charging from SDP/DCP, and Optional BATFET Enable Interface
9.2.1 Design Requirements
表 17. Design Requirements
DESIGN PARAMATER
Input voltage range
EXAMPLE VALUE
3.9 V to 6.2 V
1500 mA
Input current limit
Fast charge current
2000 mA
Boost mode output current
1 A
36
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ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The device has 1.5-MHz switching frequency to allow the use of small inductor and capacitor values. The
Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
ISAT ³ ICHG
+ 1/ 2 I
( )
RIPPLE
(4)
The inductor ripple current depends on input voltage (VBUS), duty cycle (D = VBAT/VVBUS), switching frequency
(fs) and inductance (L):
V ´D´(1- D)
IN
IRIPPLE
=
¦s´L
(5)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in
the range of (20 – 40%) maximum charging current as a trade-off between inductor size and efficiency for a
practical design.
9.2.2.2 Input Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at
50% duty cycle, then the worst case capacitor RMS current I(CIN) occurs where the duty cycle is closest to 50%
and can be estimated by the following equation:
ICIN = ICHG ´ D´(1- D)
(6)
For best performance, VBUS should be decouple to PGND with 1-μF capacitance. The remaining input capacitor
should be place on PMID.
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. 25-V rating or higher capacitor is preferred
for 15-V input voltage. 22-μF capacitance is suggested for typical charging current.
9.2.2.3 Output Capacitor
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current ICOUT is given:
IRIPPLE
ICOUT
=
» 0.29´IRIPPLE
2´ 3
(7)
The output capacitor voltage ripple can be calculated as follows:
æ
ç
ö
÷
VOUT
VOUT
DVO
=
1-
8LC¦s2
ç
÷
V
IN
è
ø
(8)
At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The charger device has internal loop compensator. To get good loop stability, the resonant frequency of the
output inductor and output capacitor should be designed between 15 kHz and 25 kHz. The preferred ceramic
capacitor is 6 V or higher rating, X7R or X5R.
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9.2.3 Application Performance Plots
STAT
VBUS
5V/div
2V/div
CE
REGN
5V/div
2V/div
SW
SYS
5V/div
2V/div
IVBUS
100mA/div
IBAT
1A/div
100ms/div
200ms/div
V(BAT) = 3.2 V
V(BAT) = 5 V
图 40. bq24259 Power Up with Charge Enabled
图 41. Charge Enable
STAT
2V/div
CE
5V/div
IL
1A/div
SW
5V/div
SW
IBAT
2V/div
1A/div
4ms/div
400ns/div
VBUS = 5 V, No Battery, I(SYS) = 40 mA, Charge Disable
图 43. PWM Switching in Buck Mode
图 42. Charge Disable
SYS3p5
500mV/div
SYS3p7
100mV/div
ISYS
2A/div
SW
2V/div
IL
1A/div
IVBUS
2A/div
4ms/div
2ms/div
VBUS = 5 V, IIN = 3 A, No Battery, Charge Disable
VBUS = 5 V, V(BAT) = 3.6 V, I(CHG) = 2 A
图 45. Input Current DPM Response without Battery
图 44. PFM Switching in Buck Mode
38
版权 © 2015–2016, Texas Instruments Incorporated
bq24259
www.ti.com.cn
ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
SYS3p8
500mV/div
ISYS
2A/div
SW
2V/div
IBAT
2A/div
IVBUS
2A/div
IL
1A/div
20ms/div
400ns/div
VBUS = 5 V, IIN = 1.5 A, V(BAT) = 3.8 V
V(BAT) = 3.8 V, ILOAD = 1 A
图 46. Load Transient During Supplement Mode
图 47. Boost Mode Switching
VBUS
200mV/div
IBAT
1A/div
IVBUS
1A/div
4ms/div
V(BAT) = 3.8 V
图 48. Boost Mode Load Transient
版权 © 2015–2016, Texas Instruments Incorporated
39
bq24259
ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
10 Power Supply Recommendations
In order to provide an output voltage on SYS, the bq24259 require a power supply between 3.9 V and 6.2 V input
with at least 100-mA current rating connected to VBUS; or, a single-cell Li-Ion battery with voltage > V(BATUVLO)
connected to BAT. The source current rating needs to be at least 2 A in order for the buck converter of the
charger to provide maximum output power to SYS.
11 Layout
11.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see 图 49) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout PCB according to this specific order is essential.
1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper
trace connection or GND plane.
2. Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
3. Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground
with a short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using thermal pad as the single ground
connection point. Or using a 0Ω resistor to tie analog ground to power ground.
5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC.
Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
6. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
7. It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
8. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the VQFN
information, refer to SCBA017 and SLUA271.
图 49. High Frequency Current Path
40
版权 © 2015–2016, Texas Instruments Incorporated
bq24259
www.ti.com.cn
ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
11.2 Layout Example
CREGN
CBTST
RBTST
CPMID
PGND
PGND
Top layer
L
2nd layer (PGND)
PGND
VBUS
PIN1
CSYS
via
VSYS
PGND
PGND on
PGND
Top layer
VBAT
CBAT
PGND
PGND
图 50. Layout Example
版权 © 2015–2016, Texas Instruments Incorporated
41
bq24259
ZHCSEJ2A –NOVEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 相关文档ꢀ
《四方扁平无引线逻辑器件封装应用报告》(SCBA017)
《QFN/SON PCB 连接应用报告》(SLUA271)
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
42
版权 © 2015–2016, Texas Instruments Incorporated
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都遵循在订单确认时所提供的TI 销售条款与条件。
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用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ24259RGER
BQ24259RGET
ACTIVE
ACTIVE
VQFN
VQFN
RGE
RGE
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
BQ24259
BQ24259
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
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Copyright © 2020 德州仪器半导体技术（上海）有限公司
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