BQ2201SN-N [TI]
SRAM Nonvolatile Controller Unit;
| 型号： | BQ2201SN-N |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SRAM Nonvolatile Controller Unit 静态存储器 光电二极管 |
| 文件： | 总12页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq2201
SRAM Nonvolatile Controller Unit
During a power failure, the external
Features
General Description
SRAM is switched from the VCC
supply to one of two 3V backup sup-
➤ Power monitoring and switching
for 3-volt battery-backup applica-
tions
The CMOS bq2201 SRAM Nonvolatile
plies. On a subsequent power-up, the
Controller Unit provides all necessary
SRAM is write-protected until a
functions for converting a standard
power-valid condition exists.
CMOS SRAM into nonvolatile
➤ Write-protect control
read/write memory.
The bq2201 is footprint- and timing-
compatible with industry stan-
dards with the added benefit of a
chip-enable propagation delay of
less than 10ns.
➤ 3-volt primary cell inputs
A precision comparator monitors the
5V VCC input for an out-of-tolerance
condition. When out of tolerance is
detected, a conditioned chip-enable
output is forced inactive to write-
protect any standard CMOS SRAM.
➤ Less than 10ns chip-enable
propagation delay
➤ 5% or 10% supply operation
Pin Connections
Pin Names
VOUT
Supply output
BC1—BC2 3-volt primary backup cell inputs
NC
1
2
3
4
5
6
16
15
14
13
12
11
NC
THS
CE
Threshold select input
chip-enable active low input
Conditioned chip-enable output
+5-volt supply input
Ground
VOUT
NC
VCC
NC
V
1
2
3
4
8
7
6
5
V
CC
OUT
CECON
VCC
VSS
BC
2
BC
CE
CE
BC2
NC
BC1
NC
1
THS
CON
THS
NC
CECON
V
SS
7
8
10
9
NC
CE
NC
No Connect
8-Pin Narrow DIP or SOIC
V
SS
PN220101.eps
16-Pin SOIC
PN2201E.eps
Functional Description
An external CMOS static RAM can be battery-backed
using the VOUT and the conditioned chip-enable output
pin from the bq2201. As VCC slews down during a power
failure, the conditioned chip-enable output CECON is
forced inactive independent of the chip-enable input CE.
If THS is tied to VSS, power-fail detection occurs at 4.62V
typical for 5% supply operation. If THS is tied to VCC
power-fail detection occurs at 4.37V typical for 10% sup-
ply operation. The THS pin must be tied to VSS or VCC for
proper operation.
,
This activity unconditionally write-protects external If a memory access is in process during power-fail detec-
SRAM as VCC falls to an out-of-tolerance threshold VPFD
.
tion, that memory cycle continues to completion before the
memory is write-protected. If the memory cycle is not ter-
minated within time tWPT, the CECON output is uncondi-
tionally driven high, write-protecting the memory.
VPFD is selected by the threshold select input pin, THS.
Oct. 1998 D
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bq2201
As the supply continues to fall past VPFD, an internal
switching device forces VOUT to one of the two external
backup energy sources. CECON is held high by the VOUT
energy source.
A valid isolation signal requires CE low as VCC crosses
both VPFD and VSO during a power-down. See Figure 2.
Between these two points in time, CE must be brought
to the point of (0.48 to 0.52) VCC and held for at least
*
700ns. The isolation signal is invalid if CE exceeds
During power-up, VOUT is switched back to the VCC sup-
ply as VCC rises above the backup cell input voltage
0.54 VCC at any point between VCC crossing VPFD and
*
VSO
.
sourcing VOUT
. The CECON output is held inactive for
time tCER (120 ms maximum) after the supply has
reached VPFD, independent of the CE input, to allow for
processor stabilization.
The appropriate battery is connected to VOUT and CECON
immediately on subsequent application and removal of VCC
.
During power-valid operation, the CE input is fed
through to the CECON output with a propagation delay
of less than 10ns. Nonvolatility is achieved by hardware
hookup, as shown in Figure 1.
V
PFD
Energy Cell Inputs—BC , BC
1
2
Two primary backup energy source inputs are provided
on the bq2201. The BC1 and BC2 inputs accept a 3V pri-
mary battery, typically some type of lithium chemistry.
If no primary cell is to be used on either BC1 or BC2, the
V
CC
V
SO
unused input should be tied to VSS
.
If both inputs are used, during power failure the VOUT
output is fed only by BC1 as long as it is greater than
2.5V. If the voltage at BC1 falls below 2.5V, an internal
isolation switch automatically switches VOUT from BC1
to BC2.
0.5 V
CC
CE
700ns
TD220101.eps
To prevent battery drain when there is no valid data to
retain, VOUT and CECON are internally isolated from
BC1 and BC2 by either of the following:
■
Initial connection of a battery to BC1 or BC2, or
Presentation of an isolation signal on CE.
Figure 2. Battery Isolation Signal
■
5V
V
CC
V
OUT
V
CC
From Address Decoder
CE
BC
bq2201
CMOS
SRAM
1
CE
CON
CE
THS
BC
2
3V
Primary
Cell
3V
Primary
Cell
V
SS
FG220101.eps
Figure 1. Hardware Hookup (5% Supply Operation)
2
Oct. 1998 D
bq2201
Absolute Maximum Ratings
Symbol
VCC
Parameter
Value
Unit
Conditions
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
DC voltage applied on any pin excluding VCC
relative to VSS
VT
V
T ≤ VCC + 0.3
-0.3 to 7.0
V
0 to +70
-40 to +85
-55 to +125
-40 to +85
260
°C
°C
Commercial
TOPR
Operating temperature
Industrial “N”
TSTG
Storage temperature
Temperature under bias
Soldering temperature
VOUT current
°C
TBIAS
TSOLDER
IOUT
°C
°C
For 10 seconds
200
mA
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Recommended DC Operating Conditions (T = T
)
OPR
A
Symbol
Parameter
Supply voltage
Minimum Typical Maximum
Unit
V
Notes
4.75
4.50
0
5.0
5.0
0
5.5
THS = VSS
THS = VCC
VCC
5.5
0
V
VSS
VIL
VIH
Supply voltage
V
Input low voltage
Input high voltage
-0.3
2.2
-
0.8
V
-
VCC + 0.3
V
VBC1
VBC2
,
Backup cell voltage
Threshold select
2.0
-
-
4.0
V
V
THS
-0.3
VCC + 0.3
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V or VBC.
Oct. 1998 D
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bq2201
DC Electrical Characteristics (T = T
, V
OPR CC
= 5V ± 10%)
A
Symbol
ILI
Parameter
Input leakage current
Output high voltage
VOH, BC supply
Minimum
Typical
Maximum Unit
Conditions/Notes
VIN = VSS to VCC
-
-
± 1
µA
V
VOH
VOHB
VOL
ICC
2.4
-
-
-
-
IOH = -2.0mA
VBC - 0.3
V
VBC > VCC, IOH = -10µA
IOL = 4.0mA
Output low voltage
Operating supply current
-
-
-
0.4
5
V
3
mA No load on VOUT and CECON.
4.55
4.30
-
4.62
4.37
VBC
4.75
4.50
-
V
V
V
THS = VSS
THS = VCC
VPFD
VSO
Power-fail detect voltage
Supply switch-over voltage
VOUT data-retention current
to additional memory not in-
cluded.
Data-retention mode
current
ICCDR
-
-
100
nA
VCC - 0.2
-
-
V
V
V
V
V
VCC > VBC, IOUT = 100mA
VCC > VBC, IOUT = 160mA
VCC < VBC, IOUT = 100µA
VBC1 < 2.5V
VOUT1
VOUT2
VBC
VOUT voltage
VOUT voltage
V
CC - 0.3
-
-
-
VBC - 0.3
-
-
-
-
-
VBC2
VBC1
-
-
Active backup cell
voltage
-
160
-
VBC1 > 2.5V
IOUT1
IOUT2
VOUT current
VOUT current
mA VOUT > VCC - 0.3V
µA
VOUT > VBC - 0.2V
100
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V or VBC.
Oct. 1998 D
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bq2201
Capacitance (T = 25°C, F = 1MHz, V
= 5.0V)
CC
A
Symbol
CIN
Parameter
Input capacitance
Output capacitance
Minimum
Typical
Maximum
Unit
pF
Conditions
-
-
-
-
8
Input voltage = 0V
Output voltage = 0V
COUT
10
pF
Note:
This parameter is sampled and not 100% tested.
AC Test Conditions
Parameter
Test Conditions
0V to 3.0V
5ns
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
1.5V (unless otherwise specified)
See Figure 3
5V
960
CE
CON
510
100pF
FG220102.eps
Figure 3. Output Load
Oct. 1998 D
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bq2201
Power-Fail Control (TA = T
)
OPR
Symbol
tPF
Parameter
Minimum
Typical
Maximum Unit
Notes
VCC slew, 4.75V to 4.25V
VCC slew, 4.25V to VSO
VCC slew, 4.25V to 4.75V
300
10
0
-
-
-
-
-
-
µs
µs
µs
tFS
tPU
Chip-enable propagation
delay
tCED
-
7
10
ns
Time during which SRAM is
ms write-protected after VCC
passes VPFD on power-up.
tCER
Chip-enable recovery
Write-protect time
40
80
120
Delay after VCC slews down
µs
tWPT
40
100
150
past VPFD before SRAM is
write-protected.
Note:
Typical values indicate operation at TA = 25°C.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down Timing
t
PF
4.75
V
PFD
t
FS
4.25
V
CC
V
SO
CE
t
WPT
V
OHB
CE
CON
TD220102.eps
Oct. 1998 D
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bq2201
Power-Up Timing
t
PU
4.75
V
PFD
V
CC
4.25
SO
V
t
CER
CE
t
t
CED
CED
V
OHB
CE
CON
TD220103.eps
Oct. 1998 D
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bq2201
8-Pin DIP Narrow (PN)
8-Pin DIP Narrow (PN)
Dimension
Minimum
0.160
0.015
0.015
0.055
0.008
0.350
0.300
0.230
0.300
0.090
0.115
0.020
Maximum
0.180
0.040
0.022
0.065
0.013
0.380
0.325
0.280
0.370
0.110
0.150
0.040
A
A1
B
B1
C
D
E
E1
e
G
L
S
All dimensions are in inches.
8-Pin SOIC Narrow (SN)
8-Pin SOIC Narrow (SN)
Dimension
Minimum
0.060
0.004
0.013
0.007
0.185
0.150
0.045
0.225
0.015
Maximum
0.070
0.010
0.020
0.010
0.200
0.160
0.055
0.245
0.035
A
A1
B
C
D
E
e
H
L
All dimensions are in inches.
Oct. 1998 D
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bq2201
S: 16-Pin SOIC
(
)
16-Pin S SOIC
Dimension
Minimum
0.095
0.004
0.013
0.008
0.400
0.290
0.045
0.395
0.020
Maximum
0.105
0.012
0.020
0.013
0.415
0.305
0.055
0.415
0.040
A
A1
B
D
B
e
C
E
H
D
E
e
H
L
A
C
All dimensions are in inches.
.004
A1
L
Oct. 1998 D
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bq2201
Data Sheet Revision History
Change No.
Page No.
Description
Nature of Change
1
Added industrial temperature range
Was: THS tied to VOUT
Is: THS tied to VCC
2
3
1, 3, 4
10% supply operation
1, 9, 11
Added 16-pin package option
Note:
Change 1 = Sept. 1991 B changes from Sept. 1990 A.
Change 2 = Aug. 1997 C changes from Sept. 1991 B.
Change 3 = Oct. 1998 D changes from Aug. 1997 C.
Oct. 1998 D
10
bq2201
Ordering Information
bq2201
Temperature Range:
blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)
Package Option:
PN = 8-pin narrow plastic DIP
SN = 8-pin narrow SOIC
S = 16-pin SOIC
Device:
bq2201 Nonvolatile SRAM Controller
Oct. 1998 D
11
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