BQ21062YFPR_技术文档

BQ21062

ZHCSLK7A –JULY 2020 –REVISED APRIL 2023

BQ21062 具有电源路径、负载开关、10nA 运输模式和稳压系统(PMID) 电压的

I²C 控制型单节电池500mA 线性电池充电器

1 特性

2 应用

• 具有1.25mA 至500mA 快速充电电流范围的线性

电池充电器

• 耳麦、耳塞和助听器

• 智能手表和智能追踪器

• 可穿戴健身和活动监测仪

• 血糖监测仪

– 0.5% 精度I²C 可编程电池稳压电压，范围为

3.6V 至4.6V 且阶跃为10mV

– 可配置的终止电流，支持低至0.5mA

– 可耐受20V 的输入，具有3.4V 至5.5V 的典型

输入电压工作范围

– 可编程热负荷曲线，完全可配置的热、温、凉、

冷阈值

3 说明

BQ21062 是一款高度集成的电池充电管理 IC，其集成

了适用于可穿戴设备、便携式设备和小型医疗设备的常

用功能，即充电器、用于系统电源的稳定输出电压轨、

负载开关/LDO 以及按钮控制器。

• 电源路径管理，用于系统供电和电池充电

– I²C 可编程稳定系统电压(PMID) 范围为4.4V 至

4.9V，此外还具有电池电压跟踪功能和输入直通

选项

BQ21062 IC 集成了具有电源路径的线性充电器，可实

现对小型电池进行快速准确的充电，同时为系统提供稳

定电压。根据下游 IC 和系统负载的建议运行条件，稳

定系统电压 (PMID) 输出可通过 I²C 进行配置，从而实

现最佳的系统运行。

– 动态电源路径管理可以对通过弱适配器充电进行

优化

– 利用高级I²C 控制，主机可以根据需要断开电池

或适配器

器件信息⁽¹⁾

封装尺寸（标称值）

• I²C 可配置负载开关或高达150mA LDO 输出

器件型号

BQ21062

封装

DSBGA (20)

2.00mm x 1.60mm

– 可编程范围为0.6V 至3.7V，阶跃为100mV

• 超低Iddq，可延长电池寿命

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 10nA 运输模式电池Iq

– 在为系统供电时具有400nA 的Iq（PMID 和

VDD 打开）

• 通过可调节计时器实现单按钮唤醒和重置输入

– 支持系统循环通电和硬件重置

• 20 引脚2mm x 1.6mm CSP 封装

• 总解决方案尺寸为11mm²

BQ21062

System

PMID

USB

Host

IN

C₅

C₄

VINLS

<150mA

Load

LS/LDO

I2C Bus

C₃

C₁

CE

LP

VDD

INT

PG

VIO

BAT

C₂

+

NTC

TS

MR

œ

GND

简化原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSE42

BQ21062

www.ti.com.cn

ZHCSLK7A –JULY 2020 –REVISED APRIL 2023

Table of Contents

9.4 Device Functional Modes..........................................29

9.5 Register Map.............................................................32

10 Application and Implementation................................53

10.1 Application Information........................................... 53

10.2 Typical Application.................................................. 53

11 Power Supply Recommendations..............................58

12 Layout...........................................................................59

12.1 Layout Guidelines................................................... 59

12.2 Layout Example...................................................... 59

13 Device and Documentation Support..........................60

13.1 Device Support....................................................... 60

13.2 Documentation Support.......................................... 60

13.3 接收文档更新通知................................................... 60

13.4 支持资源..................................................................60

13.5 Trademarks.............................................................60

13.6 静电放电警告.......................................................... 60

13.7 术语表..................................................................... 60

14 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................3

6 Device Comparison Table...............................................4

7 Pin Configuration and Functions...................................5

8 Specifications.................................................................. 7

8.1 Absolute Maximum Ratings........................................ 7

8.2 ESD Ratings............................................................... 7

8.3 Recommended Operating Conditions.........................7

8.4 Thermal Information....................................................7

8.5 Electrical Characteristics.............................................8

8.6 Timing Requirements................................................10

8.7 Typical Characteristics..............................................12

9 Detailed Description......................................................15

9.1 Overview...................................................................15

9.2 Functional Block Diagram.........................................15

9.3 Feature Description...................................................16

Information.................................................................... 61

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (July 2020) to Revision A (April 2023)

Page

• Changed t_{HW_RESET_WD}Test Conditions and MAX value................................................................................. 10

• Changed t_{RESET_WARN}......................................................................................................................................10

• Changed t_{HW_RESET}......................................................................................................................................... 10

• Changed 图9-3 ............................................................................................................................................... 20

• Changed t_{HW_RESET_WARN}to t_{RESET_WARN}in 节9.3.7.2 ...................................................................................21

• Changed VIN presence to valid VIN presence in 节9.3.7.2 ............................................................................21

• Changed text in 节9.4.1 ..................................................................................................................................29

English Data Sheet: SLUSE42

2

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5 说明（续）

该器件支持高达 500mA 的充电电流，并且支持低至 0.5mA 的终止电流，以实现最充分的充电。该器件采用标准

锂离子充电曲线分三个阶段对电池进行充电：预充电、恒流和恒压调节。

该器件集成了高级电源路径管理和控制，使该器件可以为系统提供电源，同时甚至能够使用很差的适配器为电池

充电。主机还可以通过 I²C 控制电源路径，允许它断开输入适配器和/或电池，而无需实际移除它们。单按钮输入

无需单独的按钮控制器 IC，从而减少了整体解决方案占用空间。按钮输入可用于唤醒功能或重置系统。运行和关

断期间的低静态电流有助于延长电池寿命。可通过 I²C 接口对输入电流限制、充电电流、LDO 输出电压和其他参

数进行编程，从而使 BQ21062 成为非常灵活的充电解决方案。该器件包含一个基于电压的 JEITA 兼容（或标准

热/冷）电池组热敏电阻监控输入 (TS)，可监控电池温度并自动更改充电参数，从而防止电池在超出其安全温度范

围的温度下充电。还可以通过 I²C 对温度阈值进行编程，从而使主机能够自定义热负荷曲线。该充电器针对 5V

USB 输入进行了优化，具有20V 的绝对最大容差，可承受线路瞬变。该器件还集成了一个用于为无线电或处理器

提供静态轨的线性稳压器，可以通过I²C 独立地为其提供电源并对其进行控制。

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English Data Sheet: SLUSE42

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6 Device Comparison Table

表6-1. Device Comparison

PARAMETER

BQ21061

BQ21062

67.5mA

ICHARGE (default)

IPRECHARGE (default)

INLIM (default)

10mA

2.5mA

8.75mA

500mA

100mA

WATCHDOG TIMER (default)

VINDPM (default)

Enabled

Disabled

Enabled

Disabled

Load Switch

2.8V

Disabled

DPPM

Enabled

LS/LDO (default)

Enabled

LDO CONFIG (default)

BATUVLO (default)

MR HW RESET (default)

AUTOWAKE TIME (default)

TS THRESHOLD (default)

LDO

3V

8s

14s

1.2s

2.4s

TWARM = 45°C; THOT = 60°C

TWARM = THOT = 45°C

English Data Sheet: SLUSE42

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7 Pin Configuration and Functions

1

2

3

4

A

IN

PMID

BAT

GND

/PG

PMID

BAT

NC1

TS

B

C

/MR

/CE

NC2

VDD

/INT

SDA

/LP

LSLDO

VINLS

D

VIO

SCL

E

图7-1. YFP Package 20-Pin DSBGA Top View

表7-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with

at least 1-µF of capacitance using a ceramic capacitor.

IN

A1

I

Regulated System Output. Connect 22-µF capacitor from PMID to GND as close to the

PMID and GND pins as possible. If operating in VIN Pass-Through Mode (PMID_REG =

111) a lower capacitor value may be used (at least 3-µF of ceramic capacitance with DC bias

de-rating).

PMID

A2, B2

I/O

GND

VDD

A4

D1

PWR

O

Ground connection. Connect to the ground plane of the circuit.

Digital supply LDO. Must connect a 2.2-µF from this pin to ground, do not leave floating.

Charge Enable. Drive CE low or leave disconnected to enable charging when VIN is valid.

CE is pulled low internally with 900-kΩresistor.

CE

C2

I

I²C Interface Clock. Connect SCL to the logic rail through a 10-kΩresistor.

I²C Interface Data. Connect SDA to the logic rail through a 10-kΩresistor.

SCL

SDA

E3

E2

I/O

I

Low Power Mode Enable. Drive this pin low to set the device in low power mode when

powered by the battery. This pin must be driven high to allow I²C communication when VIN

is not present. LP is pulled low internally with 900-kΩresistor. This pin has no effect when

VIN is present.

LP

D3

I

INT is an open-drain output that signals fault interrupts. When a fault occurs, a 128-µs pulse

is sent out as an interrupt for the host.

INT

MR

D2

C1

O

I

Manual Reset Input. MR is a general purpose input used to reset the device or to wake it up

from Ship Mode. MR has in internal 125-kΩpull-up resistor to BAT. The battery voltage V_BAT

must be above V_BATUVLOin order for MR low logic level to be detected.

Load Switch or LDO output. Connect 2.2 µF of ceramic capacitance to this pin to assure

stability. Be sure to account for capacitance bias voltage derating when selecting the

capacitor. If LDO is not used, short to VINLS

LS/LDO

VINLS

D4

E4

O

I

Input to the Load Switch / LDO output. Connect at least 1 µF of ceramic capacitance from

this pin to ground.

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表7-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with

at least 1 µF of ceramic capacitance.

BAT

A3, B3

I/O

I

Battery Pack NTC Monitor. Connect TS to a 10-kΩNTC thermistor in parallel to a 10-kΩ

resistor. If TS function is not to be used connect a 5-kΩresistor from TS to ground.

TS

B4

B1

Open-drain Power Good status indication output. The PG pin can also be configured as a

general purpose open drain output or level shifter version of MR.

PG

O

System IO supply. Connect to system IO supply to allow level shifting of input signals (SDA,

SCL, LP and CE) to the device internal digital domain. Connect to VDD when external IO

supply is not available.

VIO

E1

I

No Connect. Connect to ground if possible for better thermal dissipation or leave floating. Do

not connect to a any voltage source or signal to avoid higher quiescent current.

NC1

NC2

C3

C4

I

No Connect. Connect to ground if possible for better thermal dissipation. May be shorted

to /LP for easier routing as long as Absolute Maximum Rating requirements are met..

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English Data Sheet: SLUSE42

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

0

MAX

20

UNIT

V

IN

Voltage

Current

TS,VDD, NC

All other pins

IN

1.95

5.5

V

800

1.5

mA

A

BAT, PMID

INT, PG

–0.5

0

10

mA

°C

Junction temperature, T_J

Storage temperature, T_stg

125

150

–40

–55

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

8.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.4

3.15

2.2

1.2

0

NOM

MAX

4.6

UNIT

V

V_BAT

V_IN

Battery voltage range

Input voltage range

5.25⁽¹⁾

3.6

V

V_INLS

V_IO

LDO input voltage range

IO supply voltage range

LDO output current

V

I_LDO

I_PMID

T_A

100

mA

A

PMID output current

0

1.5

Operating free-air temperature range

85

°C

–40

(1) Based on minimum V_OVPvalue. 5.5V under typical conditions

8.4 Thermal Information

BQ21062

THERMAL METRIC⁽¹⁾

YFP (DSBGA)

20-PIN

36.1

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance ⁽²⁾

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

°C/W

74.4

0.5

17.6

0.3

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UNIT

ZHCSLK7A –JULY 2020 –REVISED APRIL 2023

8.4 Thermal Information (continued)

BQ21062

YFP (DSBGA)

20-PIN

THERMAL METRIC⁽¹⁾

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

17.7

°C/W

Ψ_JB

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Measured in BQ21062EVM board.

8.5 Electrical Characteristics

V_IN= 5V, V_BAT= 3.6V, -40°C < T_J< 125°C unless otherwise noted. Typical data at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CURRENTS

PMID_MODE = 01, V_IN= 5V, V_BAT= 3.6V

V_IN= 5V, V_BAT= 3.6V Charge Disabled

V_IN= 0V , V_BAT= 3.6V

500

1.6

µA

mA

nA

µA

I_IN

Input supply current

I_{BAT_SHIP}Battery Discharge Current in Ship Mode

10

0.46

1.7

18

V_IN= 0V , V_BAT= 3.6V, LDO Disabled

V_IN= 0V , V_BAT= 3.6V, LDO Enabled

V_IN= 0V , V_BAT= 3.6V, LDO Disabled

V_IN= 0V , V_BAT= 3.6V, LDO Enabled

0.9

1.9

23

Battery Quiescent Current in Low-power

I_{BAT_LP}

Mode

I_{BAT_ACTI}

Battery Quiescent Current in Active Mode

VE

21

25

POWER PATH MANAGEMENT AND INPUT CURRENT LIMIT

V_{PMID_RE}Default System (PMID) Regulation

4.5

V

%

Voltage

G

V_IN= 5V, V_{PMID_REG}= 4.5V. I_PMID

100mA, T_J= 25°C

=

-1

1

3

V_{PMID_RE}

System Regulation Voltage Accuracy

G_ACC

V_IN= 5V, V_{PMID_REG}= 4.5V. I_PMID= 0-

500mA

%

–3

R_ON(IN-

I_ILIM= 500mA (ILIM = 110), V_IN= 5V, I_IN

150mA

=

Input FET ON resistance

280

520

mΩ

PMID)

V_PMID

<

–

40mV

V_BSUP1

Enter supplements mode threshold

V_BAT> V_BATUVLO, Charge disabled

mV

V_BAT

V_PMID

<

–

V_BSUP2

Exit supplements mode threshold

Input Current Limit

V_BAT

20mV

Programmable Range

I_ILIM= 50mA

50

600

50

mA

45

90

I_ILIM

I_ILIM= 100mA

100

150

500

I_ILIM= 150mA

135

450

I_ILIM= 500mA

Input DPM voltage threshold where

current in reduced

Programmable Range

4.2

4.9

3

V

V_{IN_DPM}

Accuracy

%

–3

BATTERY CHARGER

R_ON(BAT-

Battery Discharge FET On Resistance

V_BAT= 4.35V, I_BAT= 100mA

100

175

mΩ

PMID)

Charge Voltage

Programmable charge voltage range

3.6

0.5

4.6

0.5

V

V_BATREG

Voltage Regulation Accuracy

%

English Data Sheet: SLUSE42

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8.5 Electrical Characteristics (continued)

V_IN= 5V, V_BAT= 3.6V, -40°C < T_J< 125°C unless otherwise noted. Typical data at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Fast Charge Programmable Current

Range

V_LOWV< V_BAT< V_BATREG

1.25

mA

I_CHARGE

Fast Charge Current Accuracy

Precharge current

I_CHARGE> 5mA

5

%

mA

%

–5

1.25

–10

Precharge current programmable range

-40°C < T_J< 85°C

I_PRECHAR

GE

Precharge Current Accuracy

10

31

5⁽¹⁾

3

Termination Current Programmable

Range

Termination Charge Current

Accuracy

1

–5⁽¹⁾

2.8

%

V

I_TERM

I_TERM= 10% I_CHARGE, I_CHARGE= 100mA

VBAT rising. Programmable Range

Programmable voltage threshold for pre-

charge to fast charge transitions

V_LOWV

V_SHORT

I_SHORT

Battery voltage threshold for short

detection

VBAT falling, VIN = 5V

2.41

2.54

2.67

V

I_PRECHAR

Charge Current in Battery Short Condition V_BAT< V_SHORT

V_BATfalling, V_BATREG= 4.2V, V_RCH

mA

mV

GE

=

140

140mV setting

V_RCH

Recharge Threshold voltage

V_BATfalling, V_BATREG= 4.2V, V_RCH

200mV setting

200

25

mV

R_{PMID_PD}PMID pull-down resistance

V_PMID= 3.6V

Ω

VDD

V_DD

VDD LDO output voltage

1.8

V

LS/LDO

Input voltage range for Load switch Mode

Input voltage range for LDO Mode

0.8

5.5

V

2.2 or

V_INLS

V_LDO

+

500mV

LDO programmable output voltage range

LDO output accuracy

0.6

3.7

2

V

%

T_J= 25°C

V_LDO

–2

V_LDO= 1.8V, V_INLS=3.6V. I_LOAD= 1mA

3

–3

ΔV_OUT

ΔI_OUT

/

0°C < T_J< 85°C, 1 mA < I_OUT< 150mA,

V_LDO= 1.8V

DC Load Regulation

1.2

0.5

%

ΔV_OUT

ΔV_IN

0°C < T_J< 85°C, Over V_INLSrange, I_OUT

100mA, V_LDO= 1.8V

=

DC Line Regulation

R_{DOSN_LD}

Switch On resistance

V_INLS= 3.6V

250

450

mΩ

O

R_{DSCH_LS}

Discharge FET On-resistance for LS

V_INLS= 3.6V

40

300

0.9

Ω

mA

µA

LDO

I_{OCL_LDO}Output Current Limit

LDO VINLS quiescent current in LDO

V_LS/LDO= 0V

200

V_BAT= V_INLS=3.6V

mode

I_{IN_LDO}

OFF State Supply Current

0.25

BATTERY PACK NTC MONITOR

V_HOT

High temperature threshold

Warm temperature threshold

Cool temperature threshold

Cold temperature threshold

TS Open threshold

V_TSfalling, -10°C < T_J< 85°C

V_TSrising, -10°C < T_J< 85°C

0.256⁽¹⁾

0.510⁽¹⁾

0.581⁽¹⁾

0.265 0.268⁽¹⁾

0.514 0.523⁽¹⁾

0.585 0.594⁽¹⁾

0.9

V

V_WARM

V_COOL

V_COLD

V_OPEN

V_HYS

V

Threshold hysteresis

4.7

mV

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ZHCSLK7A –JULY 2020 –REVISED APRIL 2023

8.5 Electrical Characteristics (continued)

V_IN= 5V, V_BAT= 3.6V, -40°C < T_J< 125°C unless otherwise noted. Typical data at T_J= 25°C.

PARAMETER

I_{TS_BIAS}TS bias current

PROTECTION

TEST CONDITIONS

MIN

TYP

MAX

UNIT

-10°C < T_J< 85°C

78.4

80

81.6

µA

V_INrising

V_INfalling

3.4

V

V_UVLO

IN active threshold voltage

3.25

Battery undervoltage Lockout Threshold

Voltage

Programmable range, 150 mV Hysteresis

2.4

3

V

%

V

V_BATUVLOAccuracy

Battery undervoltage Lockout Threshold

–3

V_BATrising, V_IN= 0V, T_J= 25°C

2.0V < V_BAT< V_BATREG, V_INfalling

3.15

80

Voltage at Power Up

V_{SLP_ENT}

Sleep Entry Threshold (V_IN- V_BAT

)

mV

RY

V_{SLP_EXIT}Sleep Exit Threshold (V_IN- V_BAT

)

2.0V < V_BAT< V_BATREG

V_INrising

130

5.5

5.4

mV

V

5.35

5.8

V_OVP

Input Supply Over Voltage Threshold

V_INfalling (125mV hysteresis)

V

Battery Over Current Threshold

Programmable range

I_{BAT_OCP}increasing

1200

1600

30

mA

%

I_{BAT_OCP}

Current Limit Accuracy

–30

T_SHUTDO

Thermal shutdown trip point

Thermal shutdown trip point hysteresis

125

15

°C

WN

T_HYS

I²C INTERFACE (SCL and SDA)

I²C Frequency

100

400

kHz

V

0.25 *

V_IO

V_IL

V_IH

Input Low threshold level

Input High Threshold level

V_PULLUP= V_IO= 1.8V

0.75 *

V_IO

V

0.25 *

V_IO

V_OL

Output Low threshold level

High-level leakage Current

V_PULLUP= V_IO= 1.8V, I_LOAD= 5mA

V_PULLUP= V_IO= 1.8V

V

I_LKG

/MR INPUT

1

µA

R_PU

V_IL

Internal pull up resistance

/MR Input Low threshold level

90

125

170

0.3

kΩ

V_BAT> V_BUVLO

V

/INT, /PG OUTPUTS

V_OLOutput Low threshold level

I_LKG/INT Hi level leakage Current

0.25 *

V_IO

V_PULLUP= V_IO= 1.8V, I_LOAD= 5mA

V

High Impedance, V_PULLUP= V_IO= 1.8V

1

µA

/CE, /LP INPUTS

R_PDOWN/CE pull down resistance

900

kΩ

V

V_IL

V_IH

Input Low threshold level

V_IO= 1.8V

0.45

/CE Input High Threshold level

1.35

V

(1) Based on Characterization Data

8.6 Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BATTERY CHARGE TIMERS

t_MAXCHGCharge safety timer

Programmable range

180

720

min

English Data Sheet: SLUSE42

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8.6 Timing Requirements (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_PRECHGPrecharge safety timer

WATCHDOG TIMERS

0.25 * t_MAXCHG

t_WATCHDO

SW Watchdog timer

25

50

s

G_SW

t_{HW_RESE}

HW reset watchdog timer

HWRESET_14S_WD = 1

14

T_WD

LDO

t_{ON_LDO}Turn ON time

100mA load, to 90% V_LDO

100mA load, to 10% V_LDO

500

30

µs

t_{OFF_LDO}Turn OFF time

t_{PMID_LDO}Delay between PMID and LDO enable

Startup

20

ms

during power up

_DELAY

PUSHBUTTON TIMERS (/MR)

WAKE1 Timer. Timer for Ship Mode

t_WAKE1

wake.

MR_WAKE1_TIMER = 0

MR_WAKE2_TIMER = 1

106

1.7

125

2

144

2.3

ms

s

WAKE2 Timer. Time from /MR falling

t_WAKE2

edge to INT being asserted.

RESET_WARN Timer. Time prior to HW

t_{RESET_W}

RESET or entering shipmode with MR

MR_RESET_WARN = 01

MR_HW_RESET = 01

AUTOWAKE = 01

0.85

6.8

1

8

1.15

9.2

s

ARN

press

HW RESET Timer. Time from /MR falling

t_{HW_RESE}

edge to HW Reset or PMID falling for

shipmode entry

T

t_RESTART(

RESTART Timer. Time from /MR HW

Reset to PMID power up

1.05

1.2

1.35

AUTOWAKE

)

PROTECTION

Deglitch time for supply rising above V_SLP

+ V_{SLP_HYS}

t_{DGL_SLP}

120

µs

t_{DGL_OVP}Deglitch time for V_OVPThreshold

t_{DGL_OCP}Battery OCP deglitch time

VIN falling below V_OVP

32

30

ms

µs

Recovery time, BAT Short Circuit during

Discharge Mode

t_{REC_SC}

250

2

ms

s

Retry window for PMID or BAT short

circuit recovery

t_{RETRY_SC}

t_{DGL_SHT}

Deglitch time, Thermal shutdown

T_Jrising above T_SHUTDOWN

When enabled

10

µs

DWN

I2C INTERFACE

t_WATCHDO

I²C interface reset timer for host

50

s

G

t_I2CRESETI²C interface inactive reset timer

500

ms

INPUT PINS (/CE and /LP)

t_{LP_EXIT_I}Time for device to exit Low-power mode

V_IN= 0V.

1

ms

and allow I²C communication

2C

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8.7 Typical Characteristics

C_IN= 1 µF, C_PMID= 10 µF, C_LSLDO= 2.2 µF, C_BAT= 1 µF (unless otherwise specified)

0

-0.05

-0.1

1.25

1

0.75

0.5

-0.15

-0.2

0.25

0

-0.25

-0.3

-0.25

-0.5

-0.75

-1

T_J= 25C

T_J= 0C

T_J= -40C

T_J= 60C

T_J= 125C

T_J= -40C

T_J= 0C

T_J= 25C

T_J= 60C

T_J= 125C

-0.35

-0.4

-1.25

-1.5

-1.75

-0.45

-0.5

3.6 3.7 3.8 3.9

4

4.1 4.2 4.3 4.4 4.5 4.6

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

I_CHARGE(A)

V_BATREG(V)

D011

D014

VIN = 5 V

PMID_REG_CTRL = 111 (Pass-Through)

VIN = 5 V VBAT = 3.6 V ICHARGE_RANGE = 1

图8-1. Battery Regulation Voltage Accuracy vs. VBATREG

图8-2. Charge Current Accuracy vs. ICHARGE Setting

Setting

1.5

1

1.2

1

0.8

0.6

0.4

0.2

0

0.5

0

-0.2

T_J= 25C

T_J= 0C

T_J= -40C

T_J= 60C

T_J= 125C

T_J= 25C

T_J= 0C

T_J= -40C

T_J= 60C

T_J= 125C

-0.5

-1

-0.4

-0.6

-0.8

-1

-1.5

-1.2

0

5

10

15

20

25

I_PRECHARGE(mA)

30

35

40

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

I_PRECHARGE(A)

D012

D013

VIN = 5 V VBAT = 2.7 V ICHARGE_RANGE = 0

VBUS = 5 V VBAT = 2.7 V ICHARGE_RANGE = 1

图8-3. Pre-Charge Current Accuracy vs. IPRECHARGE setting

图8-4. Pre-Charge Current Accuracy vs. IPRECHARGE Setting

(ICHARGE_RANGE = 0)

(ICHARGE_RANGE = 1)

0.8064

1.2

T_J= -40C

T_J= 25C

T_J= 85C

T_J= -40C

T_J= 25C

T_J= 85C

0.8056

1

0.8048

0.804

0.8032

0.8024

0.8016

0.8008

0.8

0.6

0.4

0.2

0

0.7992

0.7984

0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2

I_LOAD(A)

1

1.5

2

2.5

3

V_INLS(V)

3.5

4

4.5

5

D009

D015

VIN = 0 V

VBAT = 3.6 V

VINLS = VPMID

VBUS = 5 V

图8-6. LDO Load Regulation (VLDO = 0.8 V)

图8-5. LS/LDO Switch On Resistance vs. VINLS

English Data Sheet: SLUSE42

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8.7 Typical Characteristics (continued)

C_IN= 1 µF, C_PMID= 10 µF, C_LSLDO= 2.2 µF, C_BAT= 1 µF (unless otherwise specified)

1.82

1.818

1.816

1.814

1.812

1.81

3.33

3.326

3.322

3.318

3.314

3.31

T_J= -40C

T_J= 25C

T_J= 85C

T_J= -40C

T_J= 25C

T_J= 85C

1.808

1.806

1.804

1.802

1.8

3.306

3.302

3.298

3.294

3.29

1.798

1.796

1.794

1.792

1.79

0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19

I_LOAD(A)

0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19

I_LOAD(A)

D008

D010

VIN = 0 V

VBAT = 3.6 V

VINLS = VPMID

VIN = 0 V

VBAT = 3.6 V

VINLS= VPMID

图8-7. LDO Load Regulation (VLDO = 1.8 V)

图8-8. LDO Load Regulation (VLDO = 3.3 V)

1.21

1.208

1.206

1.204

1.202

1.2

1.81

1.808

1.806

1.804

1.802

1.8

1.198

1.196

1.194

1.192

1.19

1.798

1.796

1.794

1.792

1.79

T_J= -40C

T_J= 25C

T_J= 85C

T_J= -40C

T_J= 25C

T_J= 85C

2.2 2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

V_INLS(V)

4

4.2 4.4

2.2 2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

V_INLS(V)

4

4.2 4.4

D004

D005

VBAT = 4.4 V

ILOAD = 150 mA

VBAT = 4.4 V

ILOAD = 150 mA

图8-9. LDO Line Regulation (VLDO = 1.2 V)

图8-10. LDO Line Regulation (VLDO = 1.8 V)

3.4

3.38

3.36

3.34

3.32

3.3

3.65

3.625

3.6

T_J= -40C

T_J= 25C

T_J= 85C

3.575

3.55

3.525

3.5

3.28

3.26

3.24

3.22

3.2

3.475

3.45

3.425

3.4

T_J= -40C

T_J= 25C

T_J= 85C

3.6

3.7

3.8

3.9

4

V_INLS(V)

4.1

4.2

4.3

4.4

3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9

V_INLS(V)

4

4.1 4.2 4.3 4.4

D007

D006

VBAT = 4.4 V

ILOAD = 150 mA

VBAT = 4.4 V

ILOAD = 150 mA

图8-12. LDO Line Regulation (VLDO = 3.6 V)

图8-11. LDO Line Regulation (VLDO = 3.3 V)

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8.7 Typical Characteristics (continued)

C_IN= 1 µF, C_PMID= 10 µF, C_LSLDO= 2.2 µF, C_BAT= 1 µF (unless otherwise specified)

5

4.8

4.6

4.4

4.2

4

4.52

T_J= -40°C

T_J= 25°C

T_J= 85°C

T_J= 125°C

4.5

4.48

4.46

4.44

3.8

3.6

3.4

3.2

3

PMID_REG = 0

PMID_REG = 1

PMID_REG = 2

PMID_REG = 3

PMID_REG = 4

PMID_REG = 5

PMID_REG = 6

PMID_REG = 7

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

PMID Load Current (A)

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

PMID Load (A)

D001

D003

VBAT = 0 V

VBAT = 3.6 V

VIN = 5 V

图8-13. PMID Load Regulation

图8-14. PMID Load Regulation vs. Temperature

100

90

80

70

60

50

40

30

20

10

THERM_REG = 0

THERM_REG = 1

THERM_REG = 2

THERM_REG = 3

THERM_REG = 4

THERM_REG = 5

THERM_REG = 6

THERM_REG = 7

0

50

60

70

80

90

100

110

120

130

Temperature(èC)

D004

VBAT = 3.6 V

VIN = 5 V

图8-15. Charge Current Thermal Regulation

English Data Sheet: SLUSE42

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9 Detailed Description

9.1 Overview

The IC is a highly programmable battery management device that integrates a 500-mA linear charger for single

cell Li-Ion batteries, a general purpose LDO that may be configured as a load switch, and a push-button

controller. Through it's I²C interface the host may change charging parameters such as battery regulation voltage

and charge current, and obtain detailed device status and fault information. The push-button controller allows the

user to reset the system without any intervention from the host and wake up the device from Ship Mode.

9.2 Functional Block Diagram

PMID

Q5/Q6

BAT

VIN

IN

1.045 x V_BAT

PMID_REG

GND

S

V_{IN_DPM}

LDO, and BAT FET Control

I_BATREG

G

LDO

Control

D

V_BATREG

UVLO

VDD

VINLS

VIO

/CE

S

Thermal

Shutdown

V_IN

Q7

Charge

Enable

LDO / Load Switch

Control

G

D

LDO

SCL

SDA

I2C

Interface

Charge Control

Q8

Low Power Mode

Control

/LP

BAT

Device Control

/MR

/INT

œ

+

V_BATUVLO

JEITA/Temp

Information

For Charge Control

Interrupt

TS

/PG

/Power Good

GP Output

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9.3 Feature Description

9.3.1 Linear Charger and Power Path

The BQ21062 IC integrates a linear charger that allows the battery to be charged with a programmable charge

current of up to 500 mA. In addition to the charge current, other charging parameters can be programmed

through I²C such as the battery regulation voltage, pre-charge current, termination current, and input current limit

current.

The power path allows the system to be powered from PMID, even when the battery is dead or charging, by

drawing power from IN pin. It also prioritizes the system load connected to PMID, reducing the charging current,

if necessary, in order to support the load when input power is limited. If the input supply is removed and the

battery voltage level is above V_BATUVLO, PMID will automatically and seamlessly switch to battery power.

A more detailed description of the charger functionality is presented in the following sections of this document.

9.3.1.1 Battery Charging Process

The following diagram summarizes the charging process of the BQ21062 charger.

Connect VIN

No

V_BAT< V_LOWV

Yes

Start Precharge

Icharge set by I²C

Yes

/CE toggled or VIN and

removed and

reconnected?

Yes

Precharge safety

timer expired?

Stop Charging and set

Fault bits

No

V_BAT> V_LOWV

No

Yes

Start FastCharge

Icharge set by I²C

Yes

Fast Charge safety

timer expired?

No

I_BAT< I_TERM

Yes

No

Charge Done (Set bit

and interrupt and

disconnect BATFET)

Yes

No

V_BAT< V_BAT- V_RCH

图9-1. BQ21062 Charger Flow Diagram

English Data Sheet: SLUSE42

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When a valid input source is connected (V_IN> V_UVLOand V_BAT+V_SLP< V_IN< V_OVP), the state of the CE pin

determines whether a charge cycle is initiated. When the CE input is high and a valid input source is connected,

the battery charge FET is turned off, preventing any kind of charging of the battery. A charge cycle is initiated

when the CHARGE_DISABLE bit is written to 0 and CE pin in low. 表 9-1 shows the CE pin and bit priority to

enable/disable charging.

表9-1. Charge Enable Function Through CE Pin and CE Bit

CE PIN

CHARGE _DISABLE BIT

CHARGING

Enabled

0

1

0

1

0

1

Disabled

图9-2 shows a typical charge cycle.

图9-2. BQ21062 Typical Charge Cycle

During Pre-Charge, where the battery voltage is below the V_LOWVlevel, the battery willl be charge with

I_PRECHARGEcurrent which can be programmed through I²C. During pre-charge, the safety timer is set to 25% of

the safety timer value during fast charge. Once the battery voltage reaches V_LOWV, the charger will then operate

in Fast Charge Mode, charging the battery at I_CHARGEwhich may also be programmed through I₂C. Once the

battery voltage approaches the V_BATREGlevel, the charging current starts tapering off as shown in 图 9-2. Once

the charging current reaches the termination current (I_TERM) charging is stopped. Note that to ensure that the

battery is charged to V_BATREGlevel, the regulated PMID voltage should be set to at least 200mV above V_BATREG

.

Termination is only enabled when the charger CV loop is active in fast charge operation. No termination will

occur if the charge current reaches I_TERMwhile VINDPM is active as well as the thermal regulation loop.

Termination is also disabled when operating in the TS WARM region. The charger only goes to termination when

the current drops to I_TERMdue to the battery reaching the target voltage and not due to the charge current

limitation imposed by the previously mentioned control loops

Whenever a change in the charge current setting is triggered, whether it occurs due to I²C programming by the

host, Pre-Charge/Fast Charge transition or JEITA TS control, the device will temporarily disable charging (for ~ 1

ms) before updating the charge current value.

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9.3.1.2 JEITA and Battery Temperature Dependent Charging

The charger can be configured through I²C setting to provide JEITA support, automatically reducing the charging

current and voltage depending on the battery temperature as monitored by an NTC thermistor connected to the

BQ21062 TS pin. See 节9.3.11 for details.

9.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM)

The VINDPM loop prevents the input voltage from collapsing to a point where charging would be interrupted by

reducing the current drawn by charger in order to keep V_INfrom dropping below V_{IN_DPM}. Once the IN voltage

drops to V_{IN_DPM}, the VINDPM loops will reduce the input current through the blocking FETs, to prevent the

further drop of the supply voltage. The VINDPM function is enabled by default and may be disabled through I²C

command. The V_{IN_DPM}threshold is programmable through the I²C register from 4.2 V to 4.9 V in 100-mV steps.

DPPM is disabled by default in this device and cannot be re-enabled through I²C. When the device enters this

mode, the charge current may be lower than the set value and the corresponding status bits and flags are set. If

the 2X timer is set, the safety timer is extended while the loop is active. Additionally, termination is disabled.

9.3.1.4 Battery Supplement Mode

When the PMID voltage drops below the battery voltage by V_BSUP1, the battery supplements the system load.

The battery stops supplementing the system load when the voltage on the PMID pin rises above the battery

voltage by V_BSUP2. During supplement mode, the battery supplement current is not regulated, however, the

Battery Over-Current Protection mechanism is active. Battery charge termination is disabled while in supplement

mode.

9.3.2 Protection Mechanisms

9.3.2.1 Input Over-Voltage Protection

The input over-voltage protection protects the device and downstream components connected to PMID, and BAT

against damage from over-voltage on the input supply. When V_IN> V_OVPan OVP fault is determined to exist.

During the OVP fault, the device turns the input FET off, sends a single 128-µs pulse on INT, and the

VIN_OVP_FAULT FLAG and STAT bits are updated over I²C. Once the OVP fault is removed, the STAT bit is

cleared and the device returns to normal operation. The FLAG bit is not cleared until it is read through I²C after

the OVP condition no longer exists. The OVP threshold for the device is 5.5 V to allow operation from standard

USB sources.

9.3.2.2 Safety Timer and I²C Watchdog Timer

At the beginning of the charge cycle, the device starts the safety timer. If charging has not terminated before the

programmed safety time, t_MAXCHG, expires, charging is disabled. The pre-charge safety time, t_PRECHG, is 25% of

t_MAXCHG. When a safety timer fault occurs, a single 128-µs pulse is sent on the INT pin and the

SAFETY_TMR_FAULT_FLAG bit in the FLAG3 register is updated over I²C. The CE pin or input power must be

toggled in order to reset the safety timer and exit the fault condition. Note that the flag bit will be reset when the

bit is read by the host even if the fault has not been cleared. The safety timer duration is programmable using the

SAFETY_TIMER bits. When the safety timer is active, changing the safety timer duration resets the safety timer.

The device also contains a 2X_TIMER bit that doubles the timer duration to prevent premature safety timer

expiration when the charge current is reduced by VIN DPM, thermal regulation, or a NTC (JEITA) condition.

When 2X_TIMER function is enabled, the timer is allowed to run at half speed when any loop is active other than

CC or CV.

In addition, the BQ21062 has a 50s watchdog timer which resets after every I²C transaction. This feature, which

is disabled by default, resets all charger parameters registers to their default values when the timer expires.

9.3.2.3 Thermal Protection and Thermal Charge Current Foldback

In order to protect the device from damage due to overheating, the junction temperature of the die, T_J, is

monitored. When T_Jreaches T_SHUTDOWNthe device stops operation and is turned off. The device resumes

operation when T_Jfalls below T_SHUTDOWNby T_HYS

.

English Data Sheet: SLUSE42

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During the charging process, the device will reduce the charging current at a rate of (0.04 x I_CHARGE)/°C once T_J

exceeds the thermal foldback threshold, T_REGto prevent further heating. If the charge current is reduced to 0,

the battery supplies the current needed to supply the PMID output. The thermal regulation threshold may be set

through I²C by setting the THERM_REG bits to the desired value.

The die junction temperature, T_J, can be estimated based on the expected board performance using 方程式1:

T_J= T_A+

q ì P

JA

DISS

(1)

Where P_DISSis the total power dissipation in the IC. The θ_JAis largely driven by the board layout. For more

information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics

Application Report. Under typical conditions, the time spent in this state is very short.

9.3.2.4 Battery Short and Over Current Protection

In order to protect the device from over current and prevent excessive battery discharge current, the BQ21062

detects if the current on the battery FET exceeds I_{BAT_OCP}. If the short circuit limit is reached for the deglitch time

(t_{DGL_OCP}), the battery discharge FET is turned off and start operating in hiccup mode, re-enabling the BATFET

t_{REC_SC}(250 ms) after being turned off by the over-current condition. If the over-current condition is triggered

upon retry for 3 to 7 consecutive times, the BATFET will then remain off until the part is reset or until Vin is

connected and valid. If the over-current condition and hiccup operation occurs while in supplement mode where

VIN is already present, VIN must be toggled in order for BATFET to be enabled and start another detection

cycle.

In the case where the battery is suddenly shorted while charging and VBAT drops below V_SHORT, a fast

comparator quickly reduces the charge current to I_PRECHARGEpreventing fast charge current to be momentarily

injected to the battery while shorted.

9.3.2.5 PMID Short Circuit

A short on the PMID pin is detected when the PMID voltage drops below 1.6 V (PMID short threshold). PMID

short threshold has a 200-mV hysteresis. When this occurs, the input FET temporarily disconnects IN for up to

200 µs to prevent stress on the device if a sudden short condition happens, before allowing a softstart on the

PMID output.

9.3.3 VDD LDO

The device integrates a low current always-on LDO that serves as the digital I/O supply to the device. This LDO

is supplied by VIN or by BAT. The VDD LDO will remain on through all power states with the exception of Ship

Mode.

9.3.4 Load Switch/LDO Output and Control

The device integrates a low Iq load switch which can also be used as a regulated output. The LDO/LS has a

dedicated input pin VINLS and can support up to 150 mA of load current.

The LS/LDO may be enabled/disabled through I²C. The output voltage is programmable using the LS_LDO bits

in the registers. To limit voltage drop or voltage transients, a small ceramic capacitor must be placed close to

VINLS pin.

表9-2. LDO Mode Control

I2C EN_LS_LDO

LDO_SWITCH_CONFIG

LS/LDO OUTPUT

Pulldown

0

1

0

1

0

1

Pulldown

LDO

Load Switch

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The current capability of the LDO will depend on the VINLS input voltage and the programmed output voltage.

When the LS/LDO output is disabled through the register, an internal pull-down will discharge the output. The

LDO has output current limit protection, limiting the output current in the event of a short in the output. When the

LDO output current limit trips and is active for at least 1 ms, the device will set a flag and send an interrupt to the

host. The host must take action to enable the LDO if desired. The LS/LDO may be set to operate as a LDO by

setting the LDO_SWITCH_CONFIG bit to 0. Note that in order to change the configuration, the LS/LDO must be

disabled first, then the LDO_SWITCH_CONFIG bit is set for it to take effect. This is not the case when updating

the LDO output voltage which can be done on the fly without the need of disabling the LDO first.

9.3.5 PMID Power Control

The BQ21062 offers the option to control PMID through the I²C PMID_MODE bits. These bits can force PMID to

be supplied by BAT instead of IN, even if V_IN> V_BAT+ V_SLP. They can also disconnect PMID, pulling it down or

leaving it floating. See 表9-30 for details.

9.3.6 System Voltage (PMID) Regulation

The BQ21062 has a regulated system voltage output (PMID) that is programmable through I²C. PMID regulation

is only active when the adapter is connected and V_IN> V_UVLO, V_IN> V_BAT_ V_SLPand V_IN< V_OVP. In Battery

Tracking operation (PMID_REG_CTRL = 000), the PMID voltage will be regulated to about 4.7% over battery

level (V_PMID= V_BATx 1.047) or 3.8 V, whichever is higher. Note that the PMID regulation target should be set to

be at least 200mV higher than V_BATREG

.

9.3.7 MR Wake and Reset Input

The MR input has three main functions in the BQ21062. First, it serves as a means to wake the device from Ship

Mode. Second, it serves as a short button press detector, sending an interrupt to the host when the button

driving the MR pin has been pressed for a given period of time. This allows the implementation of different

functions in the end application such as menu selection and control. And finally it serves as a means to get the

BQ21062 to reset the system by performing a power cycle (shut down PMID and automatically powering it back

on) or go to Ship Mode after detecting a long button press. In order for the MR to be functional, the battery

voltage V_BATmust be above the V_BATUVLOlevel. The timing for the short and long button press duration is

programmable through I²C for added flexibility. Note that if a specific timer duration is changed through I²C while

that timer is active and has not expired, the new programmed value will be ignored until the timer expires and/or

is reset by MR. The MR input has an internal pull-up to BAT.

9.3.7.1 MR Wake or Short Button Press Functions

There are two programmable wake or short button press timers, WAKE1 and WAKE2. When the MR pin is held

low for t_WAKE1the device sends an interrupt (128 µs active low pulse in the INT pin) and sets the

MRWAKE1_TIMEOUT flag when it expires. If the MR pin continues to be driven low after WAKE1 and the

WAKE2 timer expires, the BQ21062 sends a second interrupt and sets the MRWAKE2_TIMOUT flag. WAKE1 is

used as the timer to wake the device from ship mode. WAKE2’s only function is to send the interrupt and has

no effect on other BQ21062 functions. These flags are not cleared until they have been read by the host. Note

that interrupts are only sent when the flags are set and the flags must be cleared in order for another interrupt to

be sent upon MR press. The timer durations can be set through the MR_WAKEx_TIMER bits in the MRCTRL

Register section.

One of the main MR functions is to wake the device from Ship Mode when the MR is asserted. The device will

exit the Ship Mode when the MR pin is held low for at least t_WAKE1. Immediately after the MR is asserted, VDD

will be enabled and the digital will start the WAKE counter. If the MR signal remains low until after the WAKE1

timer expires, the device will power up PMID and LDO (If enabled) completing the exit from the ship mode. If the

MR signal goes high before the WAKE1 timer expires, the device will go back to the Ship Mode operation, never

powering up PMID or the LDO. Note that if the MR pin remains low after exiting Ship Mode the wake interrupts

will not be sent and the long button press functions like HW reset will not occur until the MR pin is toggled. In the

case where a valid V_IN(V_IN> V_UVLO) is connected prior to WAKE2 timer expiring, the device will exit the ship

mode immediately regardless of the MR or wake timer state. 图9-3 and 图9-4 show these different scenarios.

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No WAKE interrupts

are sent or reset

actions are taken

until /MR is toggled

after Ship Mode exit

/MR

128us

INT

SHIPMODE

VDD

Output Rails

(PMID, LDO if enabled)

Don’t care

Go to Ship Mode

MR_LPRESS_ACTION

图9-3. MR Wake from Ship Mode (MR_LPRESS_ACTION = Ship Mode, VIN not valid)

VIN

/MR

INT

SHIPMODE

VDD

128us

Output Rails

(PMID, LDO if enabled)

MR_LPRESS_ACTION

Don’t care

Go to Ship Mode

图9-4. MR Wake from Ship Mode –VIN Dependencies

9.3.7.2 MR Reset or Long Button Press Functions

The BQ21062 device may be configured to perform a system hardware reset (Power Cycle/Autowake), go into

Ship Mode, or simply do nothing after a long button press (for example, when the MR pin is driven low until the

MR_HW_RESET timer expires).The action taken by the device when the timer expires is configured through the

MR_LPRESS_ACTION bits in the ICCTRL1 Register section. Once the MR_HW_RESET timer expires the

device immediately performs the operation set by the MR_LPRESS_ACTION bits. The BQ21062 sends an

interrupt to the host when the device detects that MR has been pressed for a period that is within t_{RESET_WARN}

from reaching t_{HW_RESET}. This may warn the host that the button has been pressed for a period close to

t_{HW_RESET}which would trigger a HW Reset or used as another button press timer interrupt like the WAKE1 and

WAKE2 timers. This interrupt is sent before the MR_HW_RESET timer expires and sets the MRRESET_WARN

flag. The t_{RESET_WARN}may be set through I²C by the MR_RESET_WARN bits in the MRCTRL register. The host

may change the reset behavior at any time after MR going low and prior to the MR_HW_RESET timer expiring. It

may not change it however from another behavior to a HW reset (Power Cycle/Autowake) since a HW reset can

be gated by other condition requirements, such as a valid VIN presence (controlled by MR_RESET_VIN bit),

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throughout the whole duration of the button press. This flexibility allows the host to abort any reset or power

shutdown to the system by overriding a long button press command.

A HW reset may also be started by setting the HW_RESET bit. Note that during a HW reset , VDD remains on.

Once thwreset timer

expires and decision to

power cycle is done,

BQ2515x will always

complete the wake

after t_restart, no

matter change in VIN,

or bit control

t_{RESET_}

t_RESET

/MR

WARN

VIN

INT

128us

PMID

LDO

VDD

SW reset

00 - PowerCycle (AutoWake)

MR_LPRESS_ACTION

MR_RESET_VIN

Don’t care

Default

图9-5. MR Wake and Reset Timing with VIN Present or BAT Active Mode When MR_LPRESS_ACTION =

00

Shipmode enabled when both

MR has gone high and

t_{HW_RESET}has expired

MR_RESET_VIN has no effect

on this mode

/MR

VIN

INT

128us

PMID & LDO

SHIPMODE

VDD

Go to Shipmode

Don’t care

MR_LPRESS_ACTION

图9-6. MR Wake and Reset Timing Active Mode When MR_LPRESS_ACTION = 1x (Ship Mode) and Only

BAT is Present

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9.3.8 14-Second Watchdog for HW Reset

The BQ21062 integrates a 14-second watchdog timer that makes the BQ21062 perform a HW reset/power cycle

if no I²C transaction is detected within 14 seconds of a valid adapter being connected. If the adapter is

connected and the host responds with an I²C transaction before the 14-second watchdog window expires, the

part continues in normal operation. The 14-second watchdog is disabled by default and may be enabled through

I²C by setting the HWRESET_14S_WD bit. 图9-7 shows the basic functionality of this feature.

14s

VIN

SHIPMODE

VDD

R/W

I2C

HWRESET_14S_WD

PMID

No HW Reset since I2C

transaction occurred

within 14s window of

VIN detection

No HW Reset since

function was not re-

enabled after boot up

HW Reset due to no I2C

transaction after VIN

detected

图9-7. 14-Second Watchdog for HW Reset Behavior

9.3.9 Faults Conditions and Interrupts ( INT)

The device contains an open-drain output that signals an interrupt and is valid only after the device has

completed start-up into a valid state. If the part starts into a fault, interrupts will not be sent. The INT pin is

normally in high impedance and is pulled low for 128 µs when an interrupt condition occurs. When a fault or

status change occurs or any other condition that generates an interrupt such as CHARGE_DONE, a 128-µs

pulse (interrupt) is sent on INT to notify the host. All interrupts may be masked through I²C. If the interrupt

condition occurs while the interrupt is masked an interrupt pulse will not be sent. If the interrupt is unmasked

while the fault condition is still present, an interrupt pulse will not be sent until the INT trigger condition occurs

while unmasked.

9.3.9.1 Flags and Fault Condition Response

表9-3 below details the BQ21062 behavior when a fault condition occurs.

表9-3. Interrupt Triggers and Fault Condition Response

INTERRUPT

TRIGGER

BASED ON

STATUS BIT

CHANGE

CHARGER

BEHAVIOR

CHARGER SAFETY

TIMER

FAULT / FLAG

DESCRIPTION

PMID BEHAVIOR

Set when charger

enters Constant

Voltage operation

IN powered if V_INis

valid

CHRG_CV_FLAG

Rising Edge

Enabled

No effect

Reset

Paused- Charging

resumes with VIN or

CE toggle or when

V_RCHis reached

CHARGE_DONE_FLA

G

Set when charger

reaches termination

IN powered if V_INis

valid

IN powered VIN

powered unless

supplement mode

condition is met.

Set when Input Current

Limit loop is active

Enabled. Reduced

charge current.

Doubled if option is

enabled

IINLIM_ACTIVE_FLAG

Rising Edge

VIN powered unless

supplement mode

condition is met.

VINDPM_ACTIVE_FL

AG

Set when VINDPM

loop is active

Enabled. Reduced

charge current.

Doubled if option is

enabled

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表9-3. Interrupt Triggers and Fault Condition Response (continued)

INTERRUPT

TRIGGER

BASED ON

STATUS BIT

CHANGE

CHARGER

BEHAVIOR

CHARGER SAFETY

TIMER

FAULT / FLAG

THERMREG_ACTIVE

VIN_PGOOD_FLAG

DESCRIPTION

PMID BEHAVIOR

Set when Thermal

Charge Current

Foldback (Thermal

Regulation) loop is

active

VIN powered unless

supplement mode

condition is met.

Enabled. Reduced

charge current.

Doubled if option is

enabled

Rising Edge

VIN powered (if

VIN_PGOOD_STAT

=1) unless

PMID_MODE is not

00.

If VIN_PGOOD_STAT

is low, charging is

disabled.

Set when VIN changes

PGOOD status

Rising and

Falling Edge

Reset

Charging is paused

until condition

disappears

VIN_OVP_FAULT_FL

AG

Set when V_IN> V_OVP

Rising Edge

BAT powered

BAT_OCP_FAULT_FL

AG

Set when I_BAT

I_BATOCP

>

Disabled (BAT only

condition)

Rising Edge

N/A

Disconnect BAT

BAT_UVLO_FAULT_F

LAG

Set when V_BAT

V_BATUVLO

<

IN powered of V_INis

valid

Enabled

No effect

Paused

Set when V_TS

V_{TS_COLD}

>

Charging paused until

condition is cleared

IN powered of V_INis

valid

TS_COLD_FLAG

TS_COOL_FLAG

Set when V_{TS_COLD}

V_TS> V_{TS_COOL}

>

Enabled. Reduced

charge current.

Doubled if option is

enabled

IN powered of V_INis

valid

Enabled. Reduce

battery regulation

voltage.

Set when V_{TS_HOT}

V_TS< V_{TS_WARM}

<

IN powered of V_INis

valid

TS_WARM_FLAG

TS_HOT_FLAG

Rising Edge

No effect

Paused

N/A

Charging paused until

condition is cleared

IN powered of V_INis

valid

Set when V_TS< V_HOT

Charging is paused

until condition

disappears

Set when V_TS

V_{TS_OPEN}

>

TS_OPEN_FLAG

WD_FAULT_FLAG

N/A

Set when I²C

watchdog timer expires

Enabled

Set when safety Timer

expires. Cleared after

VIN or CE toggle

SAFETY_TMR_FAULT

_FLAG

Disabled until VIN or

CE toggle

Reset after flag is

cleared

IN powered of V_INis

valid

Set when LDO output

current exceeds OCP

condition

LS_LDO_OCP_FAULT

_FLAG

Rising Edge

N/A

MRWAKE1_TIMEOUT Set when MR is low for

_FLAG at least t_WAKE1

Rising Edge

N/A

MRWAKE2_TIMEOUT Set when MR is low for

_FLAG at least t_WAKE2

MRRESET_WARN_FL Set when MR is low for

AG

at least t_RESETWARN

No flag. Die

temperature exceeds

thermal shutdown

threshold is reached

TSHUT

N/A

Disabled

9.3.10 Power Good ( PG) Pin

The PG pin is an open-drain output that by default indicates when a valid IN supply is present. It may also be

configured to be a general purpose output (GPO) controlled through I²C or to be a level shifted version of the

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MR input signal. Connect PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an

LED for visual indication. See 表9-30 for details.

9.3.11 External NTC Monitoring (TS)

The I²C interface allows the user to easily implement the JEITA standard for systems where the battery pack

thermistor is monitored by the host. Additionally, the device provides a flexible voltage based TS input for

monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a

safe temperature during charging. The TS pin is not biased continuously, instead it is biased only when the

voltage at the pin is being sampled (for about 25ms in 225ms intervals when VIN is present. Note that the TS

biasing cannot be disabled when VIN is present.

The part can be configured to meet JEITA requirements or a simpler HOT/COLD function only. Additionally, the

TS charger control function can be disabled. To satisfy the JEITA requirements, four temperature thresholds are

monitored: the cold battery threshold, the cool battery threshold, the warm battery threshold, and the hot battery

threshold. These temperatures correspond to the V_COLD, V_COOL, V_WARM, and V_HOTthresholds in the Electrical

Characteristics table. Charging and safety timers are suspended when V_TS< V_HOTor V_TS> V_COLD. When V_COOL

< V_TS< V_COLD, the charging current is reduced to the value programmed in the TS_FASTCHGCTRL register.

Note that the current steps for fast charge in the COOL region, just as those in normal fast charge, are multiples

of the fast charge LSB value (1.25 mA by default). So in the case where the calculated scaled down current for

the COOL region falls in between charge current steps, the device will round down the charge current to the

nearest step. For example, if the fast charge current is set for 15 mA (ICHG = 1100) and TS_FASTCHARGE

=111 (0.125*ICHG), the charge current in the COOL region will be 1.25 mA instead of the calculated 1.85 mA.

When V_HOT< V_TS< V_WARM, the battery regulation voltage is reduced to the value programmed in the

TS_FASTCHGCTRL register.

Regardless of whether the part is configured for JEITA, HOT/COLD, or disabled, when a TS fault occurs, a 128-

µs pulse is sent on the INT output, and the FAULT bits of the register are updated over I²C. The FAULT bits are

not cleared until they are read over I²C. This allows the host processor to take action if a different behavior than

the pre-set function is needed. Alternately, the TS pin voltage can be read by the host if VIN is present or when

BAT is present, so the appropriate action can be taken by the host.

When in Battery only mode, a reading of the TS pin can be triggered to check for any TS faults. This is done by

setting the TS_FAULT_MEAS register (0x58) to 0x04 which sets the TS_FAULT_MEAS_ENABLE bit. The

interval of the /INT interrupt can be configured in TS_READ Register to either be a manual read or every second

in the INTERVAL bit. When configured to manual read, the fault read will have to be iniated by setting the

GET_FAULT_ENABLE bit which will automatically enable the I_{TS_BIAS}current on TS.

9.3.11.1 TS Thresholds

The BQ21062 monitors the TS voltage and sends an interrupt to the host whenever it crosses the V_HOT, V_WARM

,

V_COOLand V_COLDthresholds which correspond to different temperature thresholds based on the NTC resistance

and biasing. These thresholds may be adjusted through I²C by the host. The device will also disable charging if

TS pin exceeds the V_{TS_OPEN}threshold.

The TS biasing circuit is shown in 图 9-8. Note that the respective V_TSfor T_COLD(0°C), T_COOL(10°C), T_WARM

(45°C) and T_HOT(60°C) changes for every NTC, therefore the threshold values may need to be adjusted through

I²C based on the supported NTC type.

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BQ21062

VDD

TS_HOT

+

_

Disable Charge

TS I_BIAS

+

_

TS_WARM

Reduce V_{O_REG}

Reduce I_CHARGE

+

_

TS_COOL

TS_COLD

TS

+

_

Disable Charge

NTC

R_PARALLEL

R_PARALLEL= R_NTC@25C

图9-8. TS Bias Functional Diagram

The BQ21062 supports by default the following thresholds for a 10-KΩ NTC.

表9-4. TS Thresholds for 10-KΩThermistor with 3380 B-Constant

TEMPERATURE

THRESHOLD

VTS (V)

(°C)

Open

Cold

Cool

Warm

Hot

--

>0.9

0.585

0.514

0.265

0

10

45⁽¹⁾

(1) When V_HOTis set to the same or higher voltage level as V_WARM, the WARM region is overwitten by HOT region functionality (charge is

disabled).

9.3.12 I²C Interface

The BQ21062 device uses a fully compliant I²C interface to program and read control parameters, status bits,

and so on. I²C is a 2-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification,

Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures.

When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C

bus through open drain I/O pins, SDA and SCL. A master device, usually a micro-controller or a digital signal

processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The

master also generates specific conditions that indicate the START and STOP of data transfer. A slave device

receives and/or transmits data on the bus under control of the master device.

The BQ21062 works as a slave and supports the following data transfer modes, as defined in the I²C Bus

Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the battery

charge solution, enabling most functions to be programmed to new values depending on the instantaneous

application requirements.

Register contents remain intact as long as VBAT or VIN voltages remains above their respective UVLO levels.

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The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the

F/S-mode in this document. The BQ21062 device 7-bit address is 0×6B (shifted 8-bit address is 0xD6).

9.3.12.1 F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in 图 9-9. All I²C-compatible devices should

recognize a start condition.

DATA

CLK

S

P

START Condition

STOP Condition

图9-9. START and STOP Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W

on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires

the SDA line to be stable during the entire high period of the clock pulse (see 图 9-10). All devices recognize the

address sent by the master and compare it to their internal fixed addresses. Only the slave device with a

matching address generates an acknowledge (see 图 9-11) by pulling the SDA line low during the entire high

period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with

a slave has been established.

DATA

CLK

Data Line

Stable;

Data Valid

Change

of Data

Allowed

图9-10. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the

slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line

from low to high while the SCL line is high (see 图 9-9). This releases the bus and stops the communication link

with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a

stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching

address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the

slave I²C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in

this section will result in FFh being read out.

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Data Output

by Transmitter

Not Acknowledge

Data Output

by Receiver

Acknowledge

8

SCL From

Master

9

1

2

Clock Pulse for

Acknowledgement

START

Condition

图9-11. Acknowledge on the I²C Bus

Recognize START or

REPEATED START

Condition

Recognize STOP or

REPEATED START

Condition

Generate ACKNOWLEDGE

Signal

P

SDA

Acknowledgement

Signal From Slave

MSB

Sr

Address

R/W

SCL

S

or

Sr

or

P

ACK

Sr

图9-12. Bus Protocol

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9.4 Device Functional Modes

The BQ21062 has four main modes of operation: Active Battery Mode, Low Power Mode and Ship Mode which

are battery only modes and Charge/Adapter Mode when a supply is connected to IN. 表 9-5 below summarizes

the functions that are active for each operation mode. Each mode is discussed in further detail in the following

sections in addition to the device's power-up/down sequences.

表9-5. Function Availability Based on Primary Mode of Operation

CHARGE/ ADAPTER

MODE

LOW POWER

MODE

FUNCTION

SHIP MODE

ACTIVE BATTERY MODE

VOVP

VUVLO

Yes

No

Yes

No

Yes

No

Yes

No

Yes

BATOCP

BATUVLO

VINDPM

VDD

Yes

No

Yes

If enabled

No

Yes

If enabled

Yes

No

Yes

LS/LDO

Yes

If enabled

Yes

BATFET

TS Measurement

Battery Changing

ILIM

Yes

If enabled

No

If enabled

No

Yes (Register Value)

No

MR input

LP input

Yes

No

Yes

No

Yes

INT output

I²C

Yes

No

Yes

CE input

No

9.4.1 Ship Mode

Ship Mode is the lowest quiescent current state for the device. Ship Mode latches off the device and BAT FET

until V_IN> V_UVLOor the MR button is depressed for t_WAKE1and released. Ship mode can be entered regardless

of the state of CE. The device will also enter Ship Mode upon battery insertion when no valid VIN is present. If

the EN_SHIPMODE is written to a 1 while a valid input supply is connected, the device will wait until the IN

supply is removed to enter ship mode. If the MR pin is held low when the EN_SHIPMODE bit is set, the device

will wait until the MR pin goes high before entering Ship Mode. 图 9-13 shows this behavior. The battery voltage

must be above the maximum programmable V_BATUVLOthreshold in order to exit Ship Mode with MR press. The

EN_SHIPMODE bit can be cleared using the I²C interface while the VIN input is valid. The EN_SHIPMODE bit is

not cleared upon the I²C watchdog expiring, this means that if watchdog timer fault occurs while the

EN_SHIPMODE bit is set and the device is waiting to go into Ship Mode because V_INis present or MR is low,

the device will still proceed to go into Ship Mode once those conditions are cleared.

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VIN

VBAT

t_WAKE1

/MR

EN_SHIPMODE

SHIPMODE

图9-13. Ship Mode Entry Based On EN_SHIPMODE Bit

9.4.2 Low Power

Low Power mode is a low quiescent current state while operating from the battery. The device will operate in low

power mode when the LP pin is set low, V_IN< V_UVLO, MR pin is high and all I²C transactions and interrupts that

started while in the Active Battery or Charging Modes have been completed and sent. During LP mode the VDD

output is powered by BAT, the MR inputs are active and the I²C is disabled. All other circuits, such as oscillators,

are in a low power or off state. The LS/LDO outputs will remain in the state set by the EN_LS_LDO bit prior to

entering Low Power Mode. The device exits LP Mode when the LP pin is set high or V_IN> V_UVLO

.

In the case that a faulty adapter with V_IN> V_OVPis connected to the device while LP pin is low, the device will be

powered from the battery, but will operate in Active battery mode instead of Low Power mode regardless of the

LP pin state.

When MR is held low while LP is low, the device will enter Active Battery Mode, this allows for the internal clocks

of the device to be running and allow the MR long button press HW reset. I²C operation is also possible during

this condition. Note that as soon as the MR input is released and goes high, the device will go back to LP Mode

tuning off all clocks. Note that if a HW reset has occurred while LP is low, MR must remain low until the power

cycle has completed (PMID and LDO enable) to allow completion of the power up sequence.

9.4.3 Active Battery

When the device is out of Ship Mode and battery is above V_BATUVLOwith no valid input source, the battery

discharge FET is turned on connecting PMID to the battery. The current flowing from BAT to PMID is not

regulated, but it is monitored by the battery over-current protection (OCP) circuitry. If the battery discharge

current exceed the OCP threshold, the battery discharge FET will be turned off as detailed in 节9.3.2.4.

If only battery is connected and the battery voltage goes below V_BATUVLO, the battery discharge FET is turned

off. To provide designers the most flexibility in optimizing their system, an adjustable BATUVLO is provided.

Deeper discharge of the battery enables longer times between charging, but may shorten the battery life. The

BATUVLO is adjustable with a fixed 150-mV hysteresis.

9.4.4 Charger/Adapter Mode

This mode is active when V_IN> V_UVLO. If the supply at IN is valid and above the V_{IN_DPM}level, PMID will be

powered by the supply connected to IN. The device will charge the battery, if charging is enabled, until

termination has occurred.

9.4.5 Power-Up/Down Sequencing

The power-up and power-down sequences for the BQ21062 are shown below. Upon V_INinsertion, VIN> V_UVLO

,

the device wakes up, powering the VDD rail. If V_IN> V_BAT+ V_SLPand V_IN< V_OVP, PMID will be powered by VIN

and if V_IN> V_{IN_DPM}charging will start if enabled.

In the case where V_IN< V_UVLOand the battery is inserted (V_BAT> V_BATUVLO), the device will immediately enter

Ship Mode unless MR is held low. Upon battery insertion the VDD rail will come up to allow the device to check

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the MR state and if MR is high VDD will immediately be disabled and the device will enter Ship Mode. If MR is

low, the device will start the WAKE timer and power up PMID and other rails if MR is held low for longer than

t_WAKE1

.

Triggers shipmode exit. If

VBAT = VBATREG then

termination happen and no

charging occurs

VIN

VBAT

VDD

IBAT

V_BAT

<

Battery

insertion

V_BUVLO

Digital wakes up

for shipmode

entry

Battery

supplies

power

Charging

starts

VIN level

V_BATlevel

PMID

SHIPMODE

图9-14. BQ21062 Wake-Up Upon Supply Insertion

VIN

VBAT

t_WAKE1

/MR

VDD

/MR Deglitch Delay

PMID

SHIPMODE

图9-15. BQ21062 Wake-Up Upon Battery Insertion

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9.5 Register Map

The device 7-bit address I²C is 0x6B (shifted 8-bit address is 0xD6).

9.5.1 I²C Registers

表 9-6 lists the memory-mapped registers for the I²C registers. All register offset addresses not listed in 表 9-6

should be considered as reserved locations and the register contents should not be modified.

表9-6. I²C Registers

Address

0x0

Acronym

STAT0

Register Name

Section

Go

Charger Status 0

Charger Status 1

Status 2

0x1

STAT1

0x2

STAT2

0x3

FLAG0

Charger Flags 0

Charger Flags 1

Flags 2

0x4

FLAG1

0x5

FLAG2

0x6

FLAG3

Timer Flags

0x7

MASK0

Interrupt Masks 0

Interrupt Masks 1

Interrupt Masks 2

Interrupt Masks 3

Battery Voltage Control

Fast Charge Current Control

Pre-Charge Current Control

Termination Current Control

Battery UVLO and Current Limit Control

Charger Control 0

Charger Control 1

Input Corrent Limit Control

LDO Control

0x8

MASK1

0x9

MASK2

0xA

MASK3

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1D

0x30

0x35

0x36

0x37

0x40

0x58

0x61

0x62

0x63

0x64

0x65

0x6F

VBAT_CTRL

ICHG_CTRL

PCHRGCTRL

TERMCTRL

BUVLO

CHARGERCTRL0

CHARGERCTRL1

ILIMCTRL

LDOCTRL

MRCTRL

MR Control

ICCTRL0

IC Control 0

ICCTRL1

IC Control 1

ICCTRL2

IC Control 2

TS_READ

TS_FAULT_MEAS

TS_FASTCHGCTRL

TS_COLD

TS_COOL

TS_WARM

TS_HOT

TS Read

TS Fault Measurement

TS Charge Control

TS Cold Threshold

TS Cool Threshold

TS Warm Threshold

TS Hot Threshold

Device ID

DEVICE_ID

Complex bit access types are encoded to fit into small table cells. 表 9-7 shows the codes that are used for

access types in this section.

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表9-7. I²C Access Type Codes

Access Type

Code

Description

Read Type

R

Read

RC

C

R

to Clear

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

9.5.1.1 STAT0 Register (Address = 0x0) [reset = X]

STAT0 is shown in 图9-16 and described in 表9-8.

Return to Summary Table.

图9-16. STAT0 Register

7

6

5

4

3

2

1

0

RESERVED

CHRG_CV_ST CHARGE_DON IINLIM_ACTIVE RESERVED

VINDPM_ACTI THERMREG_A VIN_PGOOD_S

AT

E_STAT

_STAT

VE_STAT

CTIVE_STAT

TAT

R-X

表9-8. STAT0 Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

R

X

Reserved

6

CHRG_CV_STAT

R

Constant Voltage Charging Mode (Taper Mode) Status

1b0 = Not Active

1b1 = Active

5

4

CHARGE_DONE_STAT

IINLIM_ACTIVE_STAT

R

X

Charge Done Status

1b0 = Not Active

1b1 = Active

Input Current Limit Status

1b0 = Not Active

1b1 = Active

3

2

RESERVED

R

X

Reserved

VINDPM_ACTIVE_STAT

VINDPM Status

1b0 = Not Active

1b1 = Active

1

0

THERMREG_ACTIVE_ST R

AT

X

Thermal Regulation Status

1b0 = Not Active

1b1 = Active

VIN_PGOOD_STAT

R

VIN Power Good Status .

1b0 = Not Good

1b1 = V_IN> V_UVLOand V_IN> V_BAT+ V_SLPand V_IN< V_OVP

9.5.1.2 STAT1 Register (Address = 0x1) [reset = X]

STAT1 is shown in 图9-17 and described in 表9-9.

Return to Summary Table.

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图9-17. STAT1 Register

7

6

5

4

3

2

1

0

VIN_OVP_FAU

LT_STAT

RESERVED

BAT_OCP_FAU BAT_UVLO_FA TS_COLD_STA TS_COOL_STA TS_WARM_ST TS_HOT_STAT

LT_STAT

ULT_STAT

T

AT

R-X

表9-9. STAT1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

VIN_OVP_FAULT_STAT

R

X

VIN Overvoltage Status

1b0 = Not Active

1b1 = Active

6

5

RESERVED

R

X

Reserved

BAT_OCP_FAULT_STAT

Battery Over-Current Protection Status

1b0 = Not Active

1b1 = Active

4

3

2

BAT_UVLO_FAULT_STAT

TS_COLD_STAT

R

X

Battery voltage below BATUVLO Level Status

1b0 = V_BAT> V_BATUVLO

1b1 = V_BAT< V_BATUVLO

TS Cold Status - V_TS> V_COLD(charging suspended)

1b0 = Not Active

1b1 = Active

TS_COOL_STAT

TS Cool Status - V_COOL< V_TS< V_COLD(charging current reduced by

value set by TS_Registers)

1b0 = Not Active

1b1 = Active

1

0

TS_WARM_STAT

TS_HOT_STAT

R

X

TS Warm - V_WARM> V_TS>V_HOT(charging voltage reduced by value

set by TS_Registers)

1b0 = Not Active

1b1 = Active

TS Hot Status - V_TS< V_HOT(charging suspended)

1b0 = Not Active

1b1 = Active

9.5.1.3 STAT2 Register (Address = 0x2) [reset = X]

STAT2 is shown in 图9-18 and described in 表9-10.

Return to Summary Table.

图9-18. STAT2 Register

7

6

5

4

3

2

1

0

RESERVED

R-X

TS_OPEN_STA

T

R-X

表9-10. STAT2 Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7-4

3-1

RESERVED

R

X

R

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表9-10. STAT2 Register Field Descriptions (continued)

Bit

Field

TS_OPEN_STAT

Type

Reset

Description

0

R

X

TS Open Status

1b0 = V_TS< V_OPEN

1b1 = V_TS> V_OPEN

9.5.1.4 FLAG0 Register (Address = 0x3) [reset = 0x0]

FLAG0 is shown in 图9-19 and described in 表9-11.

Return to Summary Table.

Clear on Read

图9-19. FLAG0 Register

7

6

5

4

3

2

1

0

RESERVED

CHRG_CV_FL CHARGE_DON IINLIM_ACTIVE RESERVED

VINDPM_ACTI THERMREG_A VIN_PGOOD_F

AG

E_FLAG

_FLAG

VE_FLAG

CTIVE_FLAG

LAG

RC-1b0

表9-11. FLAG0 Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

RC

1b0

Reserved

6

CHRG_CV_FLAG

CHARGE_DONE_FLAG

IINLIM_ACTIVE_FLAG

RESERVED

RC

1b0

Constant Voltage Charging Mode (Taper Mode) Flag

1b0 = CV Mode Entry not detected

1b1 = CV Mode Entry detected

5

4

RC

1b0

Charge Done Flag

1b0 = Charge Done (Termination) not detected

1b1 = Charge Done (Termination) detected

Input Current Limit Flag

1b0 = Input Current Limit not detected

1b1 = Input Current Limit detected

3

2

1b0

Reserved

VINDPM_ACTIVE_FLAG RC

VINDPM Flag

1b0 = VINDPM operation not detected

1b1 = VIINDPM operation detected

1

0

THERMREG_ACTIVE_FL RC

AG

1b0

Thermal Regulation Flag

1b0 = Thermal Regulation not detected

1b1 = Thermal Regulation detected

VIN_PGOOD_FLAG

RC

VIN Power Good Flag . Interrupt will not be sent if device powers up

with VIN_PGOOD condition and V_BAT< V_BATUVLO

1b0 = No change in VIN Power Good Status

1b1 = Change in VIN Power Good Status detected.

9.5.1.5 FLAG1 Register (Address = 0x4) [reset = 0x0]

FLAG1 is shown in 图9-20 and described in 表9-12.

Return to Summary Table.

Clear on Read

图9-20. FLAG1 Register

7

6

5

4

3

2

1

0

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图9-20. FLAG1 Register (continued)

VIN_OVP_FAU

LT_FLAG

RESERVED

RC-1b0

BAT_OCP_FAU BAT_UVLO_FA TS_COLD_FLA TS_COOL_FLA TS_WARM_FL TS_HOT_FLAG

LT_FLAG

ULT_FLAG

G

AG

RC-1b0

表9-12. FLAG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

VIN_OVP_FAULT_FLAG RC

1b0

VIN Over Voltage Fault Flag

1b0 = No overvoltage condition detected

1b1 = VIN overvoltage condition detected

6

5

RESERVED

RC

1b0

Reserved

BAT_OCP_FAULT_FLAG RC

Battery Over Current Protection Flag

1b0 = No Battery Over Current condition detected

1b1 = Battery Over Current condition detected

4

3

2

1

0

BAT_UVLO_FAULT_FLAG RC

1b0

Battery Under Voltage Flag

1b0 = Battery below BATUVLO condition detected

1b1 = No Battery below BATUVLO condition detected

TS_COLD_FLAG

TS_COOL_FLAG

TS_WARM_FLAG

TS_HOT_FLAG

RC

TS Cold Region Entry Flag

1b0 = TS Cold Region Entry not detected

1b1 = TS Cold Region Entry detected

TS Cool Region Entry Flag

1b0 = TS Cool Region Entry not detected

1b1 = TS Co0l Region Entry detected

TS Warm Region Entry Flag

1b0 = TS Warm Region Entry not detected

1b1 = TS Warm Region Entry detected

TS Hot Region Entry Flag

1b0 = TS Hot Region Entry not detected

1b1 = TS Hot Region Entry detected

9.5.1.6 FLAG2 Register (Address = 0x5) [reset = 0x0]

FLAG2 is shown in 图9-21 and described in 表9-13.

Return to Summary Table.

Clear on Read

图9-21. FLAG2 Register

7

6

5

4

3

2

1

0

RESERVED

RC-1b0

TS_OPEN_FLA

G

RC-1b0

RC-3b000

RC-1b0

表9-13. FLAG2 Register Field Descriptions

Bit

7-4

3-1

0

Field

Type

Reset

Description

Reserved

RESERVED

R

X

RESERVED

RC

3b000

1b0

TS_OPEN_FLAG

TS Open Flag

1b0 = No TS Open fault detected

1b1 = TS Open fault detected

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9.5.1.7 FLAG3 Register (Address = 0x6) [reset = 0x0]

FLAG3 is shown in 图9-22 and described in 表9-14.

Return to Summary Table.

Clear on Read

图9-22. FLAG3 Register

7

6

5

4

3

2

1

0

RESERVED

WD_FAULT_FL SAFETY_TMR_ LDO_OCP_FA

RESERVED

MRWAKE1_TI MRWAKE2_TI MRRESET_WA

AG

FAULT_FLAG

ULT_FLAG

MEOUT_FLAG MEOUT_FLAG

RN_FLAG

RC-1b0

RC-1b0 RC-1b0

RC-1b0

表9-14. FLAG3 Register Field Descriptions

Bit

7

Field

RESERVED

WD_FAULT_FLAG

Type

Reset

Description

RC

1b0

Reserved

6

RC

1b0

Watchdog Fault Flag

1b0 = Watchdog Timer not expired

1b1 = Watchdog Timer expired

5

4

2

1

0

SAFETY_TMR_FAULT_F RC

LAG

1b0

Safety Timer Fault Flag

1b0 = Safety Timer not expired

1b1 = Safety Timer Expired

LDO_OCP_FAULT_FLAG RC

LDO Over Current Fault

1b0 = LDO Normal

1b1 = LDO Over current fault detected

MRWAKE1_TIMEOUT_FL RC

AG

MR Wake 1 Timer Flag

1b0 = MR Wake 1 timer not expired

1b1 = MR Wake 1 timer expired

MRWAKE2_TIMEOUT_FL RC

AG

MR Wake 2 Timer Flag

1b0 = MR Wake 2 timer not expired

1b1 = MR Wake 2 timer expired

MRRESET_WARN_FLAG RC

MR Reset Warn Timer Flag

1b0 = MR Reset Warn timer not expired

1b1 = MR Reset Warn timer expired

9.5.1.8 MASK0 Register (Address = 0x7) [reset = 0x0]

MASK0 is shown in 图9-23 and described in 表9-15.

Return to Summary Table.

图9-23. MASK0 Register

7

6

5

4

3

2

1

0

RESERVED

CHRG_CV_MA CHARGE_DON IINLIM_ACTIVE RESERVED

VINDPM_ACTI THERMREG_A VIN_PGOOD_

SK

E_MASK

_MASK

VE_MASK

CTIVE_MASK

MASK

R/W-1b0

表9-15. MASK0 Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

7

R/W

1b0

Reserved

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

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表9-15. MASK0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

6

CHRG_CV_MASK

R/W

1b0

Mask for CHRG_CV interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

5

4

CHARGE_DONE_MASK R/W

1b0

Mask for CHARGE_DONE interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

IINLIM_ACTIVE_MASK

R/W

Mask for IINLIM_ACTIVE interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

3

2

RESERVED

R/W

1b0

Reserved

VINDPM_ACTIVE_MASK R/W

Mask for VINDPM_ACTIVE interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

1

0

THERMREG_ACTIVE_M R/W

ASK

1b0

Mask for THERMREG_ACTIVE interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

VIN_PGOOD_MASK

R/W

Mask for VIN_PGOOD interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

9.5.1.9 MASK1 Register (Address = 0x8) [reset = 0x0]

MASK1 is shown in 图9-24 and described in 表9-16.

Return to Summary Table.

图9-24. MASK1 Register

7

6

5

4

3

2

1

0

VIN_OVP_FAU

LT_MASK

RESERVED

BAT_OCP_FAU BAT_UVLO_FA TS_COLD_MA TS_COOL_MA TS_WARM_MA TS_HOT_MAS

LT_MASK

ULT_MASK

SK

K

R/W-1b0

表9-16. MASK1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

VIN_OVP_FAULT_MASK R/W

1b0

Mask for VIN_OVP_FAULT interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

6

5

RESERVED

R/W

1b0

Reserved

BAT_OCP_FAULT_MASK R/W

Mask for BAT_OCP_FAULT interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

4

3

2

BAT_UVLO_FAULT_MAS R/W

K

1b0

Mask for BAT_UVLO_FAULT interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

TS_COLD_MASK

TS_COOL_MASK

R/W

Mask for TS_COLD interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

Mask for TS_COOL interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

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表9-16. MASK1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

TS_WARM_MASK

R/W

1b0

Mask for TS_WARM interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

0

TS_HOT_MASK

R/W

1b0

Mask for TS_HOT interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

9.5.1.10 MASK2 Register (Address = 0x9) [reset = 0x71]

MASK2 is shown in 图9-25 and described in 表9-17.

Return to Summary Table.

图9-25. MASK2 Register

7

6

5

4

3

2

1

0

RESERVED

TS_OPEN_MA

SK

R/W-1b0

R/W-1b1

R/W-3b000

R/W-1b1

表9-17. MASK2 Register Field Descriptions

Bit

7

Field

Type

Reset

Description

Reserved

RESERVED

TS_OPEN_MASK

R

X

6

R

X

5

R

X

4

R

X

3-1

0

R/W

3b000

1b1

Mask for TS_OPEN Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

9.5.1.11 MASK3 Register (Address = 0xA) [reset = 0x0]

MASK3 is shown in 图9-26 and described in 表9-18.

Return to Summary Table.

图9-26. MASK3 Register

7

6

5

4

3

2

1

0

RESERVED

WD_FAULT_M SAFETY_TMR_ LDO_OCP_FA

RESERVED

MRWAKE1_TI MRWAKE2_TI MRRESET_WA

ASK

FAULT_MASK

ULT_MASK

MEOUT_MASK MEOUT_MASK

R/W-1b0 R/W-1b0

RN_MASK

R/W-1b0

表9-18. MASK3 Register Field Descriptions

Bit

7

Field

RESERVED

WD_FAULT_MASK

Type

R/W

Reset

Description

1b0

Reserved

6

1b0

Mask for WD_FAULT Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

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表9-18. MASK3 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5

SAFETY_TMR_FAULT_M R/W

ASK

1b0

Mask for SAFETY_TIMER_FAULT Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

4

LDO_OCP_FAULT_MASK R/W

1b0

Mask for LDO_OCP_FAULT Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

3

2

RESERVED

R/W

1b0

Reserved

MRWAKE1_TIMEOUT_M R/W

ASK

Mask for MRWAKE1_TIMEOUT Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

1

0

MRWAKE2_TIMEOUT_M R/W

ASK

1b0

Mask for MRWAKE2_TIMEOUT Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

MRRESET_WARN_MASK R/W

Mask for MRRESET_WARN Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

9.5.1.12 VBAT_CTRL Register (Address = 0x12) [reset = 0x3C]

VBAT_CTRL is shown in 图9-27 and described in 表9-19.

Return to Summary Table.

图9-27. VBAT_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-1b0

VBAT_REG_6:0

R/W-7b0111100

表9-19. VBAT_CTRL Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

RESERVED

1b0

Reserved

6-0

VBAT_REG_6:0

7b0111100 Battery Regulation Voltage (4.2 V default)

VBATREG = 3.6 V + VBAT_REG code x 10 mV

If a value greater than 4.6 V is written, the setting will go to 4.6 V

9.5.1.13 ICHG_CTRL Register (Address = 0x13) [reset = 0x36]

ICHG_CTRL is shown in 图9-28 and described in 表9-20.

Return to Summary Table.

图9-28. ICHG_CTRL Register

7

6

5

4

3

2

1

0

ICHG_7:0

R/W-8b00110110

English Data Sheet: SLUSE42

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表9-20. ICHG_CTRL Register Field Descriptions

Bit

Field

ICHG_7:0

Type

Reset

8b00110110 Fast Charge Current (67.5 mA default)

Fast Charge Current = 1.25 mA x ICHG code (ICHARGE_RANGE =

Description

7-0

R/W

0)

Fast Charge Current = 2.5 mA x ICHG code (ICHARGE_RANGE =

1)

9.5.1.14 PCHRGCTRL Register (Address = 0x14) [reset = 0x7]

PCHRGCTRL is shown in 图9-29 and described in 表9-21.

Return to Summary Table.

图9-29. PCHRGCTRL Register

7

6

5

4

3

2

1

0

ICHARGE_RAN

GE

RESERVED

R/W-2b00

IPRECHG_4:0

R/W-1b0

R/W-5b00111

表9-21. PCHRGCTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ICHARGE_RANGE

R/W

1b0

Charge Current Step

1b0 = 1.25 mA step (318.75 mA max charge current)

1b1 = 2.5 mA step (500 mA max charge current)

6-5

4-0

RESERVED

R/W

2b00

Reserved

IPRECHG_4:0

5b00111

Pre-Charge Current (8.75 mA default)

Pre-Charge Current = 1.25 mA x IPRECHG code

(ICHARGE_RANGE = 0)

Pre-Charge Current = 2.5 mA x IPRECHG code (ICHARGE_RANGE

= 1)

9.5.1.15 TERMCTRL Register (Address = 0x15) [reset = 0x14]

TERMCTRL is shown in 图9-30 and described in 表9-22.

Return to Summary Table.

图9-30. TERMCTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-2b00

ITERM_4:0

TERM_DISABL

E

R/W-5b01010

R/W-1b0

表9-22. TERMCTRL Register Field Descriptions

Bit

7-6

Field

Type

Reset

Description

RESERVED

R/W

2b00

Reserved

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表9-22. TERMCTRL Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5-1

ITERM_4:0

R/W

5b01010

Termination Current (10% of ICHRG default)

Programmable Range = 1% to 31% of ICHRG

5b00000 = Do not Use

5b00001 = 1% of ICHRG

5b00010 = 2% of ICHRG

5b00100 = 4% of ICHRG

5b01000 = 8% of ICHRG

5b10000 = 16% of ICHRG

0

TERM_DISABLE

R/W

1b0

Termination Disable

1b0 = Termination Enabled

1b1 = Termination Disabled

9.5.1.16 BUVLO Register (Address = 0x16) [reset = 0x3]

BUVLO is shown in 图9-31 and described in 表9-23.

Return to Summary Table.

图9-31. BUVLO Register

7

6

5

4

3

2

1

0

RESERVED

R/W-2b00

VLOWV_SEL

R/W-1b0

IBAT_OCP_ILIM_1:0

R/W-2b00

BUVLO_2:0

R/W-3b011

表9-23. BUVLO Register Field Descriptions

Bit

Field

Type

R/W

Reset

2b00

1b0

Description

7-6

5

RESERVED

Reserved

VLOWV_SEL

Pre-charge to Fast Charge Threshold

1b0 = 3.0 V

1b1 = 2.8 V

4-3

2-0

IBAT_OCP_ILIM_1:0

R/W

2b00

Battery Over-Current Protection Threshold

2b00 = 1200 mA

2b01 = 1500 mA

2b10 = Disabled

2b11 = Disabled

BUVLO_2:0

3b011

Battery UVLO Voltage

3b000 = 3.0 V

3b001 = 3.0 V

3b010 = 3.0 V

3b011 = 2.8 V

3b100 = 2.6 V

3b101 = 2.4 V

3b110 = 2.2 V

3b111 = Disabled

9.5.1.17 CHARGERCTRL0 Register (Address = 0x17) [reset = 0x92]

CHARGERCTRL0 is shown in 图9-32 and described in 表9-24.

Return to Summary Table.

English Data Sheet: SLUSE42

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图9-32. CHARGERCTRL0 Register

7

6

5

4

3

2

1

0

TS_EN

TS_CONTROL VRH_THRESH WATCHDOG_D

2XTMR_EN

SAFETY_TIMER_LIMIT_1:0

R/W-2b01

RESERVED

_MODE

ISABLE

R/W-1b1

R/W-1b0

R/W-1b1

R/W-1b0

表9-24. CHARGERCTRL0 Register Field Descriptions

Bit

Field

TS_EN

Type

Reset

Description

7

R/W

1b1

TS Function Enable

1b0 = TS function disabled (Only charge control is disabled.

TS_OPEN detection and TS ADC monitoring remain enabled)

1b1 = TS function enabled

6

5

4

3

TS_CONTROL_MODE

VRH_THRESH

R/W

1b0

1b1

1b0

TS Function Control Mode

1b0 = Custom (JEITA)

1b1 = Disable charging on HOT/COLD Only

Recharge Voltage Threshold

1b0 = 140 mV

1b1 = 200 mV

WATCHDOG_DISABLE

2XTMR_EN

Watchdog Timer Disable

1b0 = Watchdog timer enabled

1b1 = Watchdog timer disabled

Enable 2X Safety Timer

1b0 = The timer is not slowed at any time

1b1 = The timer is slowed by 2x when in any control other than CC

or CV

2-1

SAFETY_TIMER_LIMIT_1 R/W

:0

2b01

Charger Safety Timer

2b00 = 3 Hr Fast Charge

2b01 = 6 Hr Fast Charge

2b10 = 12 Hr Fast Charge

2b11 = Disabled

0

RESERVED

R/W

1b0

Reserved

9.5.1.18 CHARGERCTRL1 Register (Address = 0x18) [reset = 0x32]

CHARGERCTRL1 is shown in 图9-33 and described in 表9-25.

Return to Summary Table.

图9-33. CHARGERCTRL1 Register

7

6

5

4

3

2

1

0

VINDPM_DIS

R/W-1b0

VINPDM_2:0

R/W-3b011

RESERVED

R/W-1b1

THERM_REG_2:0

R/W-3b010

表9-25. CHARGERCTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

VINDPM_DIS

R/W

1b0

Disable VINDPM Function

1b0 = VINDPM Enabled

1b1 = VINDPM Disabled

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表9-25. CHARGERCTRL1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

6-4

VINPDM_2:0

R/W

3b011

VINDPM Level Selection

3b000 = 4.2 V

3b001 = 4.3 V

3b010 = 4.4 V

3b011 = 4.5 V

3b100 = 4.6 V

3b101 = 4.7 V

3b110 = 4.8 V

3b111 = 4.9 V

3

RESERVED

R/W

1b1

Reserved

2-0

THERM_REG_2:0

3b010

Thermal Charge Current Foldback Threshold

3b000 = 80°C

3b001 = 85°C

3b010 = 90°C

3b011 = 95°C

3b100 = 100°C

3b101 = 105°C

3b110 = 110°C

3b111 = Disabled

English Data Sheet: SLUSE42

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9.5.1.19 ILIMCTRL Register (Address = 0x19) [reset = 0x1]

ILIMCTRL is shown in 图9-34 and described in 表9-26.

Return to Summary Table.

图9-34. ILIMCTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-5b00000

ILIM_2:0

R/W-3b001

表9-26. ILIMCTRL Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-3

2-0

RESERVED

ILIM_2:0

5b00000

3b001

Reserved

Input Current Limit Level Selection

3b000 = 50 mA

3b001 = 100 mA

3b010 = 150 mA

3b011 = 200 mA

3b100 = 300 mA

3b101 = 400 mA

3b110 = 500 mA

3b111 = 600 mA

9.5.1.20 LDOCTRL Register (Address = 0x1D) [reset = 0x32]

LDOCTRL is shown in 图9-35 and described in 表9-27.

Return to Summary Table.

图9-35. LDOCTRL Register

7

6

5

4

3

2

1

0

EN_LS_LDO

VLDO_4:0

LDO_SWITCH_ RESERVED

CONFG

R/W-1b0

R/W-5b01100

R/W-1b1

R/W-1b0

表9-27. LDOCTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

EN_LS_LDO

R/W

1b0

LS/LDO Enable

1b0 = Disable LS/LDO

1b1 = Enable LS/LDO

6-2

1

VLDO_4:0

R/W

5b01100

1b1

LDO output voltage setting (1.8 V default)

LDO Voltage = 600 mV + VLDO Code x 100 mV

LDO_SWITCH_CONFG

LDO / Load Switch Configuration Select

1b0 = LDO

1b1 = Load Switch

0

RESERVED

R/W

1b0

Reserved

9.5.1.21 MRCTRL Register (Address = 0x30) [reset = 0x2E]

MRCTRL is shown in 图9-36 and described in 表9-28.

Return to Summary Table.

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图9-36. MRCTRL Register

7

6

5

4

3

2

1

0

MR_RESET_VI MR_WAKE1_TI MR_WAKE2_TI

MR_RESET_WARN_1:0

R/W-2b01

MR_HW_RESET_1:0

RESERVED

N

MER

R/W-1b0

R/W-1b1

R/W-2b11

R/W-1b0

表9-28. MRCTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

MR_RESET_VIN

R/W

1b0

VIN Power Good gated MR Reset Enable

1b0 = Reset sent when /MR reset time is met regardless of VIN state

1b1 = Reset sent when MR reset is met and Vin is valid

6

5

MR_WAKE1_TIMER

MR_WAKE2_TIMER

MR_RESET_WARN_1:0

R/W

1b0

Wake 1 Timer setting

1b0 = 125 ms

1b1 = 500 ms

1b1

Wake 2 Timer setting

1b0 = 1 s

1b1 = 2 s

4-3

2b01

MR Reset Warn Timer setting

2b00 = MR_HW_RESET - 0.5 s

2b01 = MR_HW_RESET - 1.0 s

2b10 = MR_HW_RESET - 1.5 s

2b11 = MR_HW_RESET - 2.0 s

2-1

MR_HW_RESET_1:0

R/W

2b11

1b0

MR HW Reset Timer setting

2b00 = 4 s

2b01 = 8 s

2b10 = 10 s

2b11 = 14 s

0

RESERVED

Reserved

9.5.1.22 ICCTRL0 Register (Address = 0x35) [reset = 0x20]

ICCTRL0 is shown in 图9-37 and described in 表9-29.

Return to Summary Table.

图9-37. ICCTRL0 Register

7

6

5

4

3

2

1

0

EN_SHIP_MOD RESERVED

E

AUTOWAKE_1:0

R/W-2b10

RESERVED

GLOBAL_INT_

MASK

HW_RESET

SW_RESET

R/W-1b0

表9-29. ICCTRL0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

EN_SHIP_MODE

R/W

1b0

Ship Mode Enable

1b0 = Normal operation

1b1 = Enter Ship Mode when VIN is not valid and /MR is high

6

RESERVED

R/W

1b0

Reserved

5-4

AUTOWAKE_1:0

2b10

Auto-wakeup Timer (TRESTART) for /MR HW Reset

2b00 = 0.6 s

2b01 = 1.2 s

2b10 = 2.4 s

2b11 = 5 s

46

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表9-29. ICCTRL0 Register Field Descriptions (continued)

Bit

3

Field

Type

R/W

Reset

Description

RESERVED

1b0

Reserved

2

GLOBAL_INT_MASK

1b0

Global Interrupt Mask

1b0 = Normal Operation

1b1 = Mask all interrupts

1

0

HW_RESET

SW_RESET

R/W

1b0

HW Reset

1b0 = Normal operation

1b1 = HW Reset. Temporarily power down all power rails, except

VDD. I²C Register go to default settings.

SW_Reset

1b0 = Normal operation

1b1 = SW Reset. I²C Registers go to default settings.

9.5.1.23 ICCTRL1 Register (Address = 0x36) [reset = 0x0]

ICCTRL1 is shown in 图9-38 and described in 表9-30.

Return to Summary Table.

图9-38. ICCTRL1 Register

7

6

5

4

3

2

1

0

MR_LPRESS_ACTION_1:0

R/W-2b00

RESERVED

R/W-1b0

RESERVED

R/W-1b0

PG_MODE_1:0

R/W-2b00

PMID_MODE_1:0

R/W-2b00

表9-30. ICCTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

MR_LPRESS_ACTION_1: R/W

0

2b00

MR Long Press Action

2b00 = HW Reset (Power Cycle)

2b01 = Do nothing

2b10 = Enter Ship Mode

2b11 = Enter Ship Mode

5

4

RESERVED

PG_MODE_1:0

R/W

1b0

Reserved

1b0

Reserved

3-2

2b00

PG Pin Mode of Operation

2b00 = VIN Power Good. PG pulls to GND when V_IN> V_UVLO, V_IN

V_BAT+V_SLPand V_IN< V_{IN_OVP}

2b01 = Deglitched Level Shifted /MR. PG is high impedance when

>

.

the MR input is high, and PG pulls to GND when the MR input is low.

2b1x = General Purpose Open Drain Output. The state of the PG pin

is then controlled through the GPO_PG bit, where if GPO_PG is 0 ,

the PG pin is pulled to GND and if it is 1, the PG pin is in high

impedance.

1-0

PMID_MODE_1:0

R/W

2b00

PMID Control

Sets how PMID is powered in any state, except Ship Mode.

2b00 = PMID powered from BAT or VIN if present

2b01 = PMID powered from BAT only, even if VIN is present

2b10 = PMID disconnected and left floating

2b11 = PMID disconnected and pulled down.

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9.5.1.24 ICCTRL2 Register (Address = 0x37) [reset = 0x40]

ICCTRL2 is shown in 图9-39 and described in 表9-31.

Return to Summary Table.

图9-39. ICCTRL2 Register

7

6

5

4

3

2

1

0

PMID_REG_CTRL_2:0

GPO_PG

RESERVED

R/W-2b00

HWRESET_14 CHARGER_DIS

S_WD

ABLE

R/W-3b010

R/W-1b0

表9-31. ICCTRL2 Register Field Descriptions

Bit

7-5

Field

Type

Reset

Description

PMID_REG_CTRL_2:0

R/W

3b010

System (PMID) Regulation Voltage

3b000 = Battery Tracking

3b001 = 4.4 V

3b010 = 4.5 V

3b011 = 4.6 V

3b100 = 4.7 V

3b101 = 4.8 V

3b110 = 4.9 V

3b111 = Pass-Through (V_IN

)

4

GPO_PG

R/W

1b0

/PG General Purpose Output State Control

1b0 = Pulled Down

1b1 = High Z

3-2

1

RESERVED

R/W

2b00

1b0

Reserved

HWRESET_14S_WD

Enable for 14-second I²C watchdog timer for HW Reset after VIN

connection

1b0 = Timer disabled

1b1 = Device will perform HW reset if no I²C transaction is done

within 14 s after VIN is present

0

CHARGER_DISABLE

R/W

1b0

Charge Disable

1b0 = Charge enabled if /CE pin is low

1b1 = Charge disabled

9.5.1.25 TS_READ Register (Address = 0x40) [reset = 0x2]

TS_Read is shown in 图9-40 and described in 表9-32.

Return to Summary Table.

图9-40. TS_READ Register

7

6

5

4

3

2

1

0

INTERVAL

R/W-1b0

RESERVED

R-1b0

GET_FAULT_ENABLE

R/W-1b0

RESERVED

R/W-2b00

RESERVED

R/W-3b010

表9-32. TS_READ Register Field Descriptions

Bit

Field

Type

Reset

Description

7

INTERVAL

R/W

1b0

Interval rate for TS read in BAT Only operation

1b0 = Manual Read (TS pin checked when

GET_FAULT_ENABLE is set)

1b1 = TS pin checked every 1 second

English Data Sheet: SLUSE42

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表9-32. TS_READ Register Field Descriptions (continued)

Bit

6

Field

Type

R/W

Reset

Description

RESERVED

1b0

Reserved

5

GET_FAULT_ENABLE

1b0

TS Fault Read Trigger. Bit goes back to 0 when read is

complete

1b0 = Normal Operation

1b1 = Initiate TS Fault read

4-3

2-0

RESERVED

R/W

2b00

Reserved

3b010

9.5.1.26 TS_FAULT_MEAS Register (Address = 0x58) [reset = 0x0]

TS_FAULT_MEAS is shown in 图9-41 and described in 表9-33.

Return to Summary Table.

图9-41. TS_FAULT_MEAS Register

7

6

5

4

Reserved

R/W-1b0

3

Reserved

R/W- 1b0

2

1

Reserved

R/W-1b0

0

Reserved

R/W-1b0

Reserved

Fault_Enable

R/W-1b0

表9-33. TS_Fault_MEAS Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

1b0

Description

Reserved

RESERVED

6

RESERVED

5

RESERVED

4

RESERVED

3

RESERVED

2

TS_FAULT_MEAS_ENABLE

Enable TS Fault Measurement

1b0 = Measurement disabled

1b1 = Measurement enabled

1

0

RESERVED

R/W

1b0

Reserved

9.5.1.27 TS_FASTCHGCTRL Register (Address = 0x61) [reset = 0x34]

TS_FASTCHGCTRL is shown in 图9-42 and described in 表9-34.

Return to Summary Table.

图9-42. TS_FASTCHGCTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-1b0

TS_VBAT_REG__2:0

R/W-3b011

RESERVED

R/W-1b0

TS_ICHRG_2:0

R/W-3b100

表9-34. TS_FASTCHGCTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R/W

1b0

Reserved

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表9-34. TS_FASTCHGCTRL Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

6-4

TS_VBAT_REG__2:0

R/W

3b011

Reduced target battery voltage during Warm

3b000 = No reduction

3b001 = VBAT_REG - 50 mV

3b010 = VBAT_REG - 100 mV

3b011 = VBAT_REG - 150 mV

3b100 = VBAT_REG - 200 mV

3b101 = VBAT_REG - 250 mV

3b110 = VBAT_REG - 300 mV

3b111 = VBAT_REG - 350 mV

3

RESERVED

R/W

1b0

Reserved

2-0

TS_ICHRG_2:0

3b100

Fast charge current when decreased by TS function

3b000 = No reduction

3b001 = 0.875 x ICHG

3b010 = 0.750 x ICHG

3b011 = 0.625 x ICHG

3b100 = 0.500 x ICHG

3b101 = 0.375 x ICHG

3b110 = 0.250 x ICHG

3b111 = 0.125 x ICHG

9.5.1.28 TS_COLD Register (Address = 0x62) [reset = 0x7C]

TS_COLD is shown in 图9-43 and described in 表9-35.

Return to Summary Table.

图9-43. TS_COLD Register

7

6

5

4

3

2

1

0

TS_COLD_7:0

R/W-8b01111100

表9-35. TS_COLD Register Field Descriptions

Bit

7-0

Field

TS_COLD_7:0

Type

Reset

Description

R/W

8b01111100 TS Cold Threshold

1b = 4.688 mV

10b = 9.375 mV

100b = 18.75 mV

1000b = 37.5 mV

10000b = 75 mV

100000b = 150 mV

1000000b = 300 mV

10000000b = 600 mV

English Data Sheet: SLUSE42

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9.5.1.29 TS_COOL Register (Address = 0x63) [reset = 0x6D]

TS_COOL is shown in 图9-44 and described in 表9-36.

Return to Summary Table.

图9-44. TS_COOL Register

7

6

5

4

3

2

1

0

TS_COOL_7:0

R/W-8b01101101

表9-36. TS_COOL Register Field Descriptions

Bit

7-0

Field

TS_COOL_7:0

Type

Reset

Description

R/W

8b01101101 TS Cool Threshold

1b = 4.688 mV

10b = 9.375 mV

100b = 18.75 mV

1000b = 37.5 mV

10000b = 75 mV

100000b = 150 mV

1000000b = 300 mV

10000000b = 600 mV

9.5.1.30 TS_WARM Register (Address = 0x64) [reset = 0x38]

TS_WARM is shown in 图9-45 and described in 表9-37.

Return to Summary Table.

图9-45. TS_WARM Register

7

6

5

4

3

2

1

0

TS_WARM_7:0

R/W-8b00111000

表9-37. TS_WARM Register Field Descriptions

Bit

7-0

Field

TS_WARM_7:0

Type

Reset

Description

R/W

8b00111000 TS Warm Threshold

1b = 4.688 mV

10b = 9.375 mV

100b = 18.75 mV

1000b = 37.5 mV

10000b = 75 mV

100000b = 150 mV

1000000b = 300 mV

10000000b = 600 mV

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9.5.1.31 TS_HOT Register (Address = 0x65) [reset = 0x38]

TS_HOT is shown in 图9-46 and described in 表9-38.

Return to Summary Table.

图9-46. TS_HOT Register

7

6

5

4

3

2

1

0

TS_HOT_7:0

R/W-8b00111000

表9-38. TS_HOT Register Field Descriptions

Bit

7-0

Field

TS_HOT_7:0

Type

Reset

Description

R/W

8b00111000 TS Hot Threshold

1b = 4.688 mV

10b = 9.375 mV

100b = 18.75 mV

1000b = 37.5 mV

10000b = 75 mV

100000b = 150 mV

1000000b = 300 mV

10000000b = 600 mV

9.5.1.32 DEVICE_ID Register (Address = 0x6F) [reset = 0x3B]

DEVICE_ID is shown in 图9-47 and described in 表9-39.

Return to Summary Table.

图9-47. DEVICE_ID Register

7

6

5

4

3

2

1

0

DEVICE_ID_7:0

R-8b00111011

表9-39. DEVICE_ID Register Field Descriptions

Bit

7-0

Field

DEVICE_ID_7:0

Type

Reset

8b00111011 Device ID

00111011b = BQ21062

Description

R

English Data Sheet: SLUSE42

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10 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Application Information

A typical application of the BQ21062 consists of the device configured as an I²C controlled single cell Li-ion

battery charger and power path manager or small battery applications such as smart-watches and wireless

headsets. A battery thermistor may be connected to the TS pin to allow the device to monitor the battery

temperature and control charging as desired.

The system designer may connect the MR input to a push-button to send interrupts to the host as the button is

pressed or to allow the application's end user to reset the system. If not used this pin must be left floating or tied

to BAT.

10.2 Typical Application

PMID

IN

VBUS

System Load

22 µF

4.7 µF

VINLS

LS/LDO

<150 mA Load

2.2 µF

VIO

VDD

2.2 µF

Charging /

Power Path

Control

SDA

SCL

BAT

INT

PG

CE

LP

HHosotst

1 µF

10 kΩ

NTC

+

TS

œ

10 kΩ

BQ21062

MR

GND

图10-1. Typical Application Diagram

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10.2.1 Design Requirements

The design parameters for the following design example are shown in the table below.

表10-1. Design Parameters

PARAMETER

IN Supply Voltage

VALUE

5 V

Battery Regulation Voltage

LDO Output Voltage

4.35 V

LDO (1.8 V)

10.2.2 Detailed Design Procedure

10.2.2.1 Input (IN/PMID) Capacitors

Low ESR ceramic capacitors such as X7R or X5R is preferred for input decoupling capacitors and should be

places as close as possible to the supply and ground pins fo the IC. Due to the voltage derating of the capacitors

it is recommended at 25-V rated capacitors are used for IN and PMID pins which can normally operate at 5 V.

After derating the minimum capacitance must be higher than 1 µF.

10.2.2.2 VDD, LDO Input and Output Capacitors

A Low ESR ceramic capacitor such as X7R or X5R is recommended for the LDO decoupling capacitor. A 4.7-µF

capacitor is recommended for VDD output. For the LDO output a 2.2-µF capacitor is recommended. The

minimum supported capacitance after derating must be higher than 1 µF to ensure stability. The VINLS input

bypass capacitor value should match or exceed the LDO output capacitor value.

10.2.2.3 TS

A 10-KΩ NTC should be connected in parallel to a 10-kΩ biasing resistor connected to ground. The ground

connection of both the NTC and biasing resistor must be done as close as possible to the GND pin of the device

or kelvin connected to it to minimize any error in TS measurement due IR drops on the board ground lines.

If the system designer does not wish to use the TS function for charging control, a 5-kΩ resistor from TS to

ground must be connected.

10.2.2.4 Recommended Passive Components

表10-2. Recommended Passive Components

MIN

1⁽¹⁾

1

NOM

22

MAX

47

UNIT

µF

C_PMID

C_LDO

C_VDD

C_BAT

C_IN

Capacitance in PMID pin

LDO output capacitance

2.2

4.7

µF

VDD output capacitance

1

2.2

µF

BAT pin capacitance

1

µF

–

IN input bypass capacitance

VINLS input bypass capacitance

Capacitance from TS pin to ground

1

4.7

0

10

µF

C_INLS

C_TS

1

µF

–

0

1

nF

(1) For PMID regulation loop stability, for better transient performance a minimum capacitance (after derating) of 10 µF is recommended.

English Data Sheet: SLUSE42

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10.2.3 Application Curves

VIN = 5V

VBAT = 0V

VIN = 5V

VBAT = 3.6V

图10-2. Power Up from IN Supply Insertion with No

图10-3. Power Up from Ship Mode with IN Supply

Battery

Insertion

VIN = 0V

VBAT = 3.6V

VIN = 0V

VBAT = 3.6V

图10-4. Wake In To Ship Mode on Battery Insertion

图10-5. Power Up from Ship Mode with MR Press

with No IN Supply

VIN = 0V

VBAT = 3.6V

VIN = 0V

VBAT = 3.6V LBPRESS_ACTION= 01

图10-6. HW Reset on MR Long Button Press

图10-7. Ship Mode Entry with MR Long Button

Press

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VIN = 0V

VBAT = 3.6V

VIN = 5V

VBAT = 3.6V

SHIPMODE_EN = 1

图10-8. HW Reset Through I²C Command

图10-9. Ship Mode Entry on IN Supply Removal

VIN = 5V

VBAT = 3.6V

VIN = 5V

VBAT = 3.6V

图10-10. PG Power Good Function - IN Supply

图10-11. PG Power Good Function - IN Supply

Insertion

Removal

VBAT = 3.6V

VIN = 5V

VBAT = 3.6V

图10-13. PG MR Level Shift Function - MR Falling

图10-12. PG MR Level Shift Function - MR Rising

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VBAT = 3.6V

No load

图10-15. LDO Enable Through I²C (EN_LS_LDO)

图10-14. PG General Purpose Output Function -

GPO_PG Bit Toggle

VBAT = 3.6V

No load

图10-16. LDO Disable Through I²C (EN_LS_LDO)

VIN = 0V

VBAT = 3.6V

VINLS = VPMID

图10-17. LDO Load Transient - VLDO = 1.8V

VIN = 0V

VBAT = 2.4V

VINLS = VPMID

VIN = 0V

VBAT = 3.8V

VINLS = VPMID

图10-18. LDO Load Transient - VLDO = 1.8V

图10-19. LDO Load Transient - VLDO = 3.3V

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VIN = 0V

VBAT = 3.6V

VINLS = VPMID

图10-20. LDO Load Transient - VLDO = 1.2V

11 Power Supply Recommendations

The BQ21062 requires the adapter or IN supply to be between 3.4 V and 5.5 V with at least 600-mA rating. The

battery voltage must be higher than 2.4 V or V_BATUVLOto ensure proper operation.

English Data Sheet: SLUSE42

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12 Layout

12.1 Layout Guidelines

• Have solid ground plane that is tied to the GND bump

• Place LDO and VDD output capacitors as close as possible to the respective bumps and GND or ground

plane with short copper trace connection

• Place PMID capacitor as close to the PMID bump as possible and GND or ground plane.

12.2 Layout Example

GND

C_IN

C_PMID

C_BAT

PMID

GND

IN

PMID

BAT

GND

/PG

PMID

/CE

BAT

NC

TS

C_LDO

/MR

NC

C_VDD

VDD

VIO

/INT

SDA

/LP

SCL

LSLDO

VINLS

VDD

PMID

C_INLS

GND

图12-1. Layout Example

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13 Device and Documentation Support

13.1 Device Support

13.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation see the following: BQ21061EVM User's Guide and BQ21061 Setup Guide Tool

13.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

13.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

13.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

13.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ21062YFPR
厂家：	TEXAS INSTRUMENTS
描述：	具有 10nA 运输模式、电源路径、稳定系统电压和 LDO 的 500mA 单节电池线性充电器 \| YFP \| 20 \| -40 to 85 电池
文件：	总62页 (文件大小：1957K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ21062YFPR [TI]

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