BQ2058CSN [TI]
Lithium Ion Pack Supervisor for 3- and 4-Cell Packs; 锂离子电池组为监事3和4节包
| 型号： | BQ2058CSN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Lithium Ion Pack Supervisor for 3- and 4-Cell Packs |
| 文件： | 总14页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq2058
Lithium Ion Pack Supervisor
for 3- and 4-Cell Packs
vents overcharge of any cell within
Features
General Description
the battery pack. After an overvolt-
age condition occurs, each cell must
fall below VCE (charge enable voltage)
for the bq2058 to re-enable charging.
➤ Protects and individually moni-
tors three or four Li-Ion series
cells for overvoltage, undervolt-
age
The bq2058 Lithium Ion Pack Super-
visor is designed to control the charge
and discharge cell voltages for three or
four lithium ion (Li-Ion) series cells,
accommodating battery packs contain-
ing series/parallel configurations. The
low operating current does not over-
discharge the cells during periods of
storage and does not significantly in-
crease the system discharge load. The
bq2058 can be part of a low-cost Li-Ion
charge control system within the bat-
tery pack.
The bq2058 protects batteries from
overdischarge. If the voltage on any
cell falls below VUV (undervoltage
limit) for a user-configurable delay pe-
riod (tUVD), the DSG output is driven
high, shutting off the battery dis-
charge. This safety feature prevents
overdischarge of any cell within the
battery pack.
➤ Monitors pack for overcurrent
➤ Designed for battery pack inte-
gration
➤ Minimal external components
➤ Drives external FET switches
➤ Selectable overvoltage (VOV
)
The bq2058 also stops discharge on
detection of an overcurrent condition,
such as a short circuit. If an overcur-
rent condition occurs for a user-
configurable delay period (tOCD), the
DSG output is driven high, disconnect-
ing the load from the pack. DSG re-
mains high until removal of the short
circuit or overcurrent condition.
thresholds
The bq2058 controls two external FETs
to limit the charge and discharge poten-
tials. The bq2058 allows charging when
each individual cell voltage is below VOV
(overvoltage limit). If the voltage on any
cell exceeds VOV for a user-configurable
- Mask-programmable by
Unitrode
- Standard version–4.25V
➤ Supply current: 25µA typical
➤ Sleep current: 0.7µA typical
➤ 16-pin 150-mil narrow SOIC
delay period (tOVD), the
CHG pin is
driven high, shutting off charge to the
battery pack. This safety feature pre-
Pin Names
Pin Connections
DSG
NSEL
UVD
OVD
OCD
VCC
Discharge control output
3- or 4-cell selection
CHG
CTL
VSS
Charge control output
Pack disable input
Low potential input
CHG
CTL
1
2
3
4
5
6
16
15
14
13
12
11
DSG
NSEL
UVD
OVD
OCD
Undervoltage delay input
Overvoltage delay input
Overcurrent delay input
High potential input
V
SS
CSL
CSL
Current sense low-side
input
BAT
4N
BAT
3N
V
CC
BAT4N
BAT3N
BAT2N
BAT1N
Battery 4 negative input
Battery 3 negative input
Battery 2 negative input
Battery 1 negative input
BAT
BAT
7
8
10
9
CSH
2N
CSH
Current sense high-side
input
BAT
1P
1N
16-Pin Narrow SOIC
BAT1P
Battery 1 positive input
PN205801.eps
1/99 I
1
bq2058
This input is connected to BAT1P in a three-
cell configuration.
Pin Descriptions
CHG
Charge control output
DSG
Discharge control output
This push-pull output controls the charge
path to the battery pack. Charging is al-
lowed when low.
This push-pull output controls the discharge
path to the battery pack. Discharge is al-
lowed when low.
CTL
Pack disable input
NSEL
Number of cells input
When high, this input allows an external
source to disable the pack by making both
DSG and CHG inactive. For normal opera-
tion, the CTL pin is low.
This input selects the number of series cells
in the pack. NSEL should connect to VCC for
four cells and to VSS for three cells.
UVD
OVD
OCD
Undervoltage delay input
VSS
Low potential input
This input uses an external capacitor to VCC
to set the undervoltage delay timing.
CSL
Overcurrent sense low-side input
This input is connected between the low-side
discharge FET (or sense resistor) and BAT4N
to enable overcurrent sensing in the battery
pack’s ground path.
Overvoltage delay input
This input uses an external capacitor to VCC
to set the overvoltage delay timing.
BAT4N
BAT3N
BAT2N
BAT1N
Battery 4 negative input
Overcurrent delay input
This input is connected to the negative termi-
nal of the cell designated BAT4 in Figure 2.
This input uses an external capacitor to VCC
to set the overcurrent delay timing.
Battery 3 negative input
VCC
High potential input
This input is connected to the negative terminal
of the cell designated BAT3 in Figure 2.
CSH
Overcurrent sense high-side input
This input is connected between the
high-side discharge FET (or sense resistor)
and BAT1P to enable overcurrent sense in
the battery pack’s positive supply path.
Battery 2 negative input
This input is connected to the negative termi-
nal of the cell designated BAT2 in Figure 2.
BAT1P
Battery 1 positive input
Battery 1 negative input
This input is connected to the positive terminal
of the cell designated BAT1 in Figure 2.
This input is connected to the negative termi-
nal of the cell designated BAT1 in Figure 2.
Table 1. Pin Configuration for 3- and 4-Series Cells
Number of Cells
Configuration Pins
Battery Pins
BAT1N – Positive terminal of first cell
BAT2N – Negative terminal of first cell
BAT3N – Negative terminal of second cell
BAT4N – Negative terminal of third cell
BAT1P – Positive terminal of first cell
BAT1N – Negative terminal of first cell
BAT2N – Negative terminal of second cell
BAT3N – Negative terminal of third cell
BAT4N – Negative terminal of fourth cell
BAT1N tied to BAT1P
NSEL = VSS
3 cells
NSEL = VCC
4 cells
2
bq2058
Sel4
Sel3
Sel2
Sel1
Cell Inputs
Pin 9 B1P
Pin 8 B1N
Number of Cells Select
+
-
Pin 15
NSEL
NSEL
Clock
Sleep
Sel4 Sel4
Sel3 Sel3
Sel2 Sel2
Sel1 Sel1
Pin 7 B2N
Pin 6 B3N
Sleep
B4N
Pin 5
V
OV
Pin 3
+
Overcharge
D
CK
D
Q
Pin 1
CHG
Chip Negative
Supply
CK
Any_Above_V
OV
Sel4
Sel3
QB
Edge
Out
QB
Reset
Non-Retrigger
D
Q
Charge Control
Output
Oneshot
Reset
CK
QB
Capacitor
OVD
Pin 13
D
Q
Discharge Off Delay Capacitor Input
CK
Sel2
Sel1
All_Below_V
CE
QB
D
Q
CK
QB
Any_Below_V
UV
Sleep
D
Pin 16
CK
D
Q
QB
Edge
Out
CK
DSG
Sel4
Sel3
Reset
Non-Retrigger
QB
Discharge Control
Output
Oneshot
Reset
D
Q
Capacitor
CK
UVD
Pin 14
QB
Charge Off Delay Capacitor Input
Sense High-side Input
Pin 10 CSH
70mV
D
Q
Sel2
Sel1
CK
QB
Pin 9 B1P
+
D
Q
+
Sense Low-side Input
CK
Pin 4
Pin 5
CSL
V
70mV
CE
QB
B4N
+
D
CK
Q
Overcurrent
QB
D
Q
Edge
Out
Sel4
CK
Overcurrent Delay
Capacitor Input
Reset
Non-Retrigger
QB
Oneshot
Reset
Pin 12
OCD
D
Q
Capacitor
+
CK
Pin 10 CSH
Pin 9 B1P
Sel3
Sel2
160mV
QB
V
UV
+
D
Q
CK
CSL
B4N
Pin 4
Pin 5
160mV
+
QB
Pin 2
CTL
D
Q
CK
Sel1
QB
External Output Control
Figure 1. Block Diagram
3
bq2058
The bq2058 samples a cell every 40ms (typical). Every
sample is a fully differential measurement of each cell.
During this sample period, the bq2058 compares the
measurements with these thresholds to determine if any
Functional Description
Figure 1 is a block diagram outlining the major compo-
nents of the bq2058. Figure 2 shows a 3- or 4-cell pack
supervisor circuit. The following sections detail the vari-
ous functional aspects of the bq2058.
of the these conditions exist: VOV, VUV, and VCE
.
Overcurrent and charge detect are conditions that are
not sampled, but are continuously monitored.
Thresholds
Initialization
The bq2058 monitors the lithium ion pack for the condi-
tions listed below. Shown with these conditions are the
respective thresholds used to determine if that condition
exists:
On initial power-up, such as connecting the battery pack
for the first time to the bq2058, the bq2058 enters the
low-power sleep mode, disabling the DSG output. It is
recommended that a top to bottom cell connection
be made at pack assembly for proper initializa-
tion. A charging supply must be applied to the bq2058
circuit to enable the pack. See Low-Power Sleep Mode
and Charge Detect sections.
I
I
I
I
I
Overvoltage (VOV
Undervoltage (VUV
Overcurrent (VOCH, VOCL
Charge Enable (VCE
)
)
)
)
Charge Detect (VCD
)
C8
* See note 1.
0.1uF
C6
0.1uF
R2
6.98K
Q4
ZVP3306F
Q1
Si4435DY
Q2
Si4435DY
* See note 2.
POS
R10
0 Ohm
R11
0 Ohm
R9
1M
R6
100K
4-Cell
3-Cell
Q3
2N7002
U1
bq2058
C10
0.1uF
C9
0.1uF
R3
10K
15
13
14
12
16
10
1
NSEL
OVD
UVD
OCD
DSG
CSH
CHG
CTL
C5
0.1uF
B1P
11
9
C7
0.01uF
VCC
C1
0.001uF
R4
10K
BAT1P
BAT1N
BAT2N
BAT3N
BAT4N
VSS
8
B1N
7
C2
0.001uF
R5
10K
6
TP1
B2N
B3N
B4N
5
C3
0.001uF
3
2
R7
10K
4
CSL
C4
0.001uF
R8
10K
R1
2.7K
D1
BAT54
NEG
Notes:
1. For automatic short circuit recovery.
2. Remove R11 for 4-cell. Remove R10 and connect
B1P to B1N for 3-cells.
Figure 2. 3- or 4-Cell Li-Ion Battery Pack Supervisor
4
bq2058
Low-Power Sleep Mode
Table 2. Overvoltage Threshold Options
The bq2058 enters the low-power sleep mode in two dif-
ferent ways:
Part No.
VOV Limit
4.25V
4.325
bq2058
1. On initial power-up.
bq2058C
bq2058D
2. After the detection of an undervoltage condi-
4.30V
4.375V
4.35V
3.4V
tion–VUV
.
bq2058G*
bq2058R
bq2058W
When the bq2058 enters the low-power sleep mode, DSG
is driven high and the device consumes 0.7µA (typical).
The bq2058 only comes out of low-power sleep mode
when a valid charge-detect condition exists.
The overvoltage threshold limits are programmed
at Unitrode. The bq2058 is the standard option
that is more readily available for sampling and
prototyping purposes. Please contact Unitrode
for other voltage threshold and tolerance options.
Charge Detect
The bq2058 continuously monitors for a charge-detect con-
dition. A valid charge-detect condition exists when either
of the conditions are true:
CSL < BAT4N - 70mV (VCD
)
Charge Enable
CSH > BAT1P + 70mV (VCD
)
A valid charge enable indicates that an overvoltage
(overcharge) condition no longer exists and that the
pack is ready to accept further charge. Once overvoltage
protection is asserted, charging will not be enabled un-
til all cell voltages fall below VCE. The VCE threshold is
a function of VOV, and changes with different VOV lim-
its.
A valid charge-detect enables the DSG output, allowing
charging of the lithium ion cells. This is accomplished
by applying the charging supply to the pack.
Undervoltage
Undervoltage (or overdischarge) protection is asserted
when any cell voltage drops below the VUV threshold
and remains below the VUV threshold for a time
exceeding a user-configurable delay (tUVD). The DSG
output is driven high disabling the discharge of the
pack. The bq2058 then enters the low-power sleep
mode.
VCE = VOV - 150mV
Overcurrent
The bq2058 detects an overcurrent (or short circuit) con-
dition only in the discharge direction. Overcurrent pro-
tection is asserted when either of the conditions occurs
and remain for a time exceeding a user-configurable de-
lay (tOCD):
Overvoltage
Overvoltage (or overcharge) protection is asserted when
any cell voltage exceeds the VOV threshold and remains
above the VOV threshold for a time exceeding a user-
configurable delay (tOVD). The CHG pin is driven high,
disabling charge into the battery pack. Charging is dis-
abled until a valid charge enable exists. See Charge En-
able section.
CSL > BAT4N + VOCL
CSH < BAT1P - VOCH
where:
VOCL = 160mV (low-side detect)
V
OCH = 160mV (high-side detect)
Important note: If any battery pin floats (BAT1P
BAT1N 4N), the bq2058 assumes an overvoltage has
occurred.
,
–
When either of these conditions occurs, DSG is driven
high, disconnecting the load from the pack. DSG re-
mains high until both of the voltage conditions are false,
indicating removal of the short-circuit condition. The
user can facilitate clearing these conditions by inserting
the battery pack into a charger.
Because of different manufacturers specifications for
overvoltage thresholds, the bq2058 can be available with
different VOV options. Table 2 summarizes these differ-
ent voltage thresholds.
The low-side overcurrent sense can be disabled by con-
necting CSL to BAT4N. This ensures that CSL is never
greater than BAT4N
. If low-side detection is disabled,
high-side detection must be used with CSH.
5
bq2058
The FETs in the charge/discharge path controlled by the
CHG and DSG pins affect the overcurrent level. The
on-resistance of these FETs need to be taken into ac-
count when determining overcurrent levels.
Pack Disable Input–CTL
The CTL pin is used to electrically disconnect the bat-
tery from the pack terminals through an externally sup-
plied signal. When CTL is taken high, CHG and DSG
are driven high. Any load on the pack terminals will be
interpreted as an overcurrent condition by the bq2058
with the overcurrent delay timer held in reset. When
the CTL pin is driven low, the overcurrent delay timer is
allowed to start. If the programmed delay (tOCD) is too
short, the overcurrent recovery circuit, if implemented,
will be unable to correct the overcurrent situation prior
to the delay time-out. It is recommended that a delay
time of greater than 10ms (COCD ≥ 0.01µF) be used if
the CTL pin function is used.
Condition
Normal operation
Overvoltage
CHG pin
Low
High
Low
DSG pin
Low
Low
Undervoltage
High
Overcurrent
Low
High
Floating battery input
CTL = high
High
High
Indeterminate
High
Important note: If CTL floats, it is internally
pulled high making both DSG and CHG inactive,
thus disabling the pack. If CTL is not used, it
CHG and DSG States
should be tied to VSS
.
The CHG and DSG output truth table is shown below.
The polarity of CTL is mask programmable at Unitrode.
Please contact Unitrode for other polarity options.
The polarities of CHG and DSG are mask programmable
at Unitrode. Push-pull vs. open-drain configuration is
also mask-configurable at Unitrode. Please contact
Unitrode for availability of these variations.
Protection Delay Timers
The delay time between the detection of an overcurrent,
overvoltage, or undervoltage condition and the deactivation
of the CHG and/or DSG outputs is user-configurable by the
selection of capacitor values between VCC and OCD, OVD,
and UVD pins (respectively). See Table 3 below.
Number of Cells
The user must configure the bq2058 for three- or four-
series cell operation. For a three-cell pack, NSEL
should be tied directly to VSS
.
For a four-cell pack,
N
SEL should be connected directly to VCC
.
The fault condition must persist through the entire de-
lay period, or the bq2058 may not deactivate either FET
control output.
Number of Series Cells
NSEL
Figure 3 shows a step-by-step event cycle for the
bq2058.
3-cell
4-cell
Tied to VSS
Tied to VCC
Table 3. Protection Delay Timers
Typical
Protection
Feature
Delay
Capacitor from
CC to:
Tolerance
Capacitor
0.010µF
0.100µF
0.100µF
Time
12ms
Period
V
tOCD
Overcurrent
Overvoltage
Undervoltage
OCD
OVD
UVD
40%
40%
40%
tOVD
950ms
950ms
tUVD
Notes:
1. The delay time versus capacitance can be approximated by the following equations:.
For tOCD
:
t(s) ≈ 1.2 ∗ C(µf)
t(s) ≈ 9.5 ∗ C(µf)
,
,
where C ≥ 0.001µF
where C ≥ 0.01µF
For tOVD, tUVD
:
2. Overvoltage and undervoltage conditions are sampled by the bq2058. The delay in Table 2 is in
addition to the time required for the bq2058 to detect the violation, which may vary from 0 to
160 ms depending on where in the sampling period the violation occurs. Overcurrent is continuously
monitored and is subject to a delay of approximately 1.5ms.
6
bq2058
0
1
2
3
4
5
6
7
8
9
10
11 12
V
OV
V
CE
V
UV
Cell Voltage
BAT + 70mV (V
)
1P CD
CSH
DSG
BAT - 160mV (V
1P
)
OCH
t
t
UVD
OCD
CHG
CTL
t
OVD
TD205801.eps
Figure 3. Protector Event Diagram
Event Definition:
0:
1:
The bq2058 is in the low-power sleep mode because one or more of the cell voltages are below VUV.
A charger is applied to the pack, causing the difference between CSH and BAT1P to become greater
than 70mV. This awakens the bq2058, and the discharge pin DSG goes low.
2:
One or more cells charge to a voltage equal to VOV, initiating the overvoltage delay timer.
The overvoltage delay time expires, causing CHG to be driven high.
All cell voltages fall below VCE, causing CHG to be driven low.
Stop charging, apply a load.
3:
4:
5:
6:
An overcurrent condition is detected, initiating the overcurrent delay timer.
The overcurrent delay time expires, causing DSG to be driven high.
The overcurrent condition is no longer present; DSG is driven low.
Pin CTL is driven high; both DSG and CHG are driven high.
Pin CTL is driven low; both DSG and CHG resume their normal function.
One or more cells fall below VUV, initiating the overdischarge delay timer.
7:
8:
9:
10:
11:
12:
Once the overdischarge delay timer expires, if any of the cells is below VUV, the bq2058 drives
DSG high and enters the low-power sleep mode.
7
bq2058
Absolute Maximum Ratings
Symbol
VCC
Parameter
Value
18
Unit
V
Conditions
Relative to VSS
Supply voltage
TOPR
TSTG
TSOLDER
IIN
Operating temperature
Storage temperature
Soldering temperature
Maximum input current
-30 to +70
-55 to +125
260
°C
°C
°C
µA
For 10 seconds
All pins except VCC, VSS
100
Notes:
1
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional
operation should be limited to the Recommended DC Operating Conditions detailed in this data
sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect
device reliability.
2. Internal protection diodes are in place on every pin relative to VCC and VSS. See Figure 4.
V
CC
Any pin
V
SS
FG2058x .eps
Figure 4. Internal Protection Diodes
8
bq2058
DC Electrical Characteristics (T = T
A
OPR)
Symbol
VOH
Parameter
Output high voltage
Output low voltage
Operating voltage
Input low voltage
Input high voltage
Input low voltage
Input high voltage
Active current
Minimum
Typical
Maximum
Unit
V
Conditions/Notes
VCC - 0.5
-
-
I
I
OH = 10µA, CHG, DSG
OL = 10µA, CHG, DSG
VOL
VOP
VIL
VSS + 0.5
-
-
-
V
4
18.0
V
VCC relative to VSS
Pin CTL
-
-
VSS + 0.5
V
VIH
VIL
VSS + 2.0
-
-
V
Pin CTL
-
-
VSS + 0.5
V
Pin NSEL
VIH
ICCA
ICCS
VCC - 0.5
-
-
-
Pin NSEL
-
-
25
0.7
40
1.5
µA
µA
Sleep current
DC Thresholds (T = T
A
OPR)
Symbol
Parameter
Value
Unit
Tolerance
Conditons
4.25
V
See note 1
50mV
55mV
Overvoltage threshold
(See Figure 5)
For bq2058G only
See note 3
VOV
4.375
V
Table 2
Customer option
For bq2058W only
For bq2058W only
V
OV - 150mV
OV - 200mV
2.25
V
V
50mV
50mV
100mV
100mV
35mV
35mV
VCE
Charge enable threshold
Undervoltage threshold
V
V
VUV
2.10
V
VOCH
VOCL
VCD
Overcurrent detect high-side
Overcurrent detect low-side
Charge detect threshold
160
mV
mV
160
70
mV -60mV, +80mV
COVD = 0.100µF, TA = 30°C
See note 2
tOVD
Overvoltage delay threshold
950
ms
40%
CUVD = 0.100µF, TA = 30°C
tUVD
tOCD
Undervoltage delay threshold
Overcurrent delay threshold
950
12
ms
ms
40%
40%
See note 2
COCD = 0.01µF, TA = 30°C
Notes:
1. Standard device. Contact Unitrode for different thresholds and tolerance options.
2. Does not include cell sampling delay, which may add up to 160ms of additional delay until the
condition is detected.
3. bq2058G is designed only for 3-cell applications.
9
bq2058
Impedance
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Notes
RCELL
Pins BAT1P, BAT1N-4N, CSH, CSL
Input impedance
-
10
-
MΩ
4.280
4.270
4.260
4.250
4.240
4.230
4.220
4.210
Measurement accuracy 2mV
-30 -20 -10
0
10 20 30 40 50 60 70
T
A
– Free-Air Temperature – ˚C
Gr2058.eps
Figure 5. bq2058 4.25V Overvoltage Threshold vs.
Free-Air Temperature
10
bq2058
Data Sheet Revision History
Change No.
Page No.
Description
PACK+, PACK-
Nature of Change
1
1, 2, 5
Pins renamed to CSH and CSL respectively
Added CSH/CSL description
Pin description
Block diagram
1
1
Update Block diagram
1
1
1
3
4
4
Figure 2
Update typical application circuit
Correction to description
Configuration description
Was: VOCH = 150mV 25mV
V
OCL = 85mV 25mV
Is: VOCH = 160mV 25mV
OCL = 100mV 25mV
1, 2
1
5
7
Overcurrent limits
Figure 3
V
Update Event diagram
Was: VOCH = 150mV 25mV
V
OCL = 100mV 80mV
V
CD = 70mV -60, +50mV
1, 2
9
DC threshold
Is: VOCH = 160mV 25mV
V
V
OCL = 100mV 25mV
CD = 70mV -60, +80mV
Was: Between VCC and CSH,
Is: Between BAT1P and CSH
3
1, 3, 5
High-side overcurrent monitored
3
3
4
4
3, 5
4
Overvoltage threshold options
Overcurrent limit
Figure 2
Added bq2058R
Was: VOCL = 100mV, Is: VOCL = 150mV
Corrected schematic
Was: tOCD = 10ms 30%
t
t
OVD = 800ms 30%
UVD = 800ms 40%
4
6, 8
Protection Delay Times
Is: tOCD = 12ms 40%
t
t
OVD = 950ms 40%
UVD = 950ms 40%
Was: VOCH = 160mV 25mV
V
V
V
OCL = 150mV 25mV
OCH = 160mV 35mV
OCL = 160mV 35mV
4
5
10
Overcurrent limits
Is:
Overvoltage threshold
Charge enable threshold
Undervoltage threshold
5, 9
Added bq2058W
6
7
8
9
5, 9
4
DC electrical characteristics
Overvoltage threshold
Was: Minimum VOP = 0V, Is: Minimum VOP = 4V
Added bq2058C and bq2058G
Reference circuit amended
Moved D1 to new location
Notes:
Change 1 = Feb. 1997 B changes from Jan. 1997 A. Change 2 = April 1997 C changes from Feb. 1997 B.
Change 3 = June 1997 D changes from April 1997 C. Change 4 = July 1997 E changes from June 1997 D.
Change 5 = Feb. 1998 F changes from July 1997 E. Change 6 = May 1998 G changes from Feb. 1998 F.
Change 7 = June 1998 H changes from May 1998 G.
Change 8 = Jan. 1999 I changes from June 1998 H.
11
bq2058
(
)
SN: 16-Pin SN 0.150" SOIC
(
)
16-Pin SN 0.150" SOIC
Inches
Millimeters
Min.
Max.
Min.
Max.
Dimension
D
B
e
A
A1
B
0.060
0.004
0.013
0.007
0.385
0.150
0.045
0.225
0.015
0.070
0.010
0.020
0.010
0.400
0.160
0.055
0.245
0.035
1.52
0.10
0.33
0.18
9.78
3.81
1.14
5.72
0.38
1.78
0.25
0.51
0.25
10.16
4.06
1.40
6.22
0.89
E
C
H
D
E
A
C
e
A1
H
L
.004
L
12
bq2058
Ordering Information
bq2058
XXXX
Standard Device:
Blank = Standard device
XXXX = Customer code assigned by Benchmarq
Package Option:
SN = 16-pin narrow SOIC
Overvoltage Threshold
Blank = 4.25V (Standard device)
Contact Factory for availability of other thresholds
Device:
bq2058 Lithium Ion Pack Supervisor
Package Devices
T
V
Threshold
3.4V
16-pin Narrow SOIC (SN)
bq2058WSN
bq2058MSN
bq2058FSN
A
OV
4.15V
4.20V
4.225V
4.25V
4.325V
4.30V
4.35V
4.36V
4.375V
bq2058KSN
bq2058SN
-30°C
To
+70°C
bq2058CSN
bq2058DSN
bq2058RSN
bq2058JSN
bq2058GSN
Notes: bq2058SN is Standard Device.
Contact factory for availability of other thresholds and
tolerances.
13
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