AMC1305M05QDWQ1 [TI]
汽车类 ±50mV 输入、精密电流检测增强型隔离式调制器 | DW | 16 | -40 to 125;
| 型号： | AMC1305M05QDWQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 ±50mV 输入、精密电流检测增强型隔离式调制器 | DW | 16 | -40 to 125 光电二极管 转换器 |
| 文件： | 总43页 (文件大小：2086K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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AMC1305L25-Q1, AMC1305M05-Q1, AMC1305M25-Q1
ZHCSFZ3 –FEBRUARY 2017
AMC1305x-Q1
高精度、增强隔离式 Δ-Σ 调制器
1 特性
2 应用
1
•
•
汽车电子 应用认证
具有符合 AEC-Q100 的下列结果：
•
基于分流的电流感测或基于电阻分压器的电压感测
输入：
–
–
–
–
牵引逆变器
–
–
温度等级 1：-40°C 至 +125°C
板载充电器 (OBC)
直流-直流转换器
人体放电模式 (HBM) 静电放电 (ESD) 分类等级
2
–
组件充电模式 (CDM) ESD 分类等级 C6
电池管理系统 (BMS)
•
•
与以下器件引脚兼容的系列：
3 说明
–
–
输入电压范围为 ±50mV 或 ±250mV
AMC1305-Q1 器件是一款高精度 Δ-Σ (ΔΣ) 调制器，通
过磁场抗扰度较高的电容式双隔离栅隔离输出与输入电
路。根据 DIN V VDE V 0884-10、UL1577 和 CSA 标
准，该隔离栅经认证可提供高达 7000 V峰值 的增强型
隔离。当与隔离电源配合使用时，该器件可防止共模高
电压线路上的噪声电流进入本地系统接地，从而干扰或
损害低电压电路。
互补金属氧化物半导体 (CMOS) 或低压差分信
令 (LVDS) 数字接口选项
出色的直流性能：
–
–
–
–
偏移误差：±50µV 或 ±150µV（最大值）
偏移漂移：1.3µV/°C（最大值）
增益误差：±0.3%（最大值）
增益漂移：±40ppm/°C（最大值）
•
安全相关认证：
AMC1305-Q1 针对直接连接分流电阻器或其它低电压
等级信号源进行了优化，同时具有出色的直流和交流性
能。分流电阻通常用于感测牵引逆变器、车载充电器或
类似汽车应用 中的电流。通过使用适当的数字滤波器
（即，集成于 TMS320F2837x）来抽取位流，该器件
可在 78kSPS 数据速率下实现 85dB (13.8 ENOB) 动
态范围的 16 位分辨率。
–
–
–
7000 VPK 增强型隔离，符合 DIN V VDE V
0884-10 (VDE V 0884-10): 2006-12 标准
符合 UL 1577 标准且长达 1 分钟的 5000 VRMS
隔离
CAN/CSA No. 5A 组件验收服务通知
•
•
瞬态抗扰度：15kV/µs（最小值）
高电磁场抗扰度
（请参见应用手册 SLLA181A）
在高侧，调制器由 5V (AVDD) 标称电压供电，而隔离
数字接口则由 3.3V 或 5V 电源 (DVDD) 供电。
•
5MHz 至 20MHz 外部时钟输入
AMC1305-Q1 采用宽体小外形尺寸集成电路 (SOIC)-
16 (DW) 封装。
器件信息(1)
器件型号
封装
封装尺寸（标称值）
AMC1305x-Q1
SOIC (16)
10.30mm x 7.50mm
(1) 如需了解所有可用封装，请参见数据表末尾的可订购产品附
录。
简化电路原理图
Floating
Power Supply
HV+
AMC1305-Q1
Gate Driver
5.0 V
DVDD
AVDD
3.3 V, or 5.0 V
AGND
DGND
RSHUNT
To Load
AINN
AINP
DOUT
CLKIN
SD-Dx
SD-Cx
PWMx
Gate Driver
TMS320F2837x
Copyright © 2016, Texas Instruments Incorporated
HV-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS797
AMC1305L25-Q1, AMC1305M05-Q1, AMC1305M25-Q1
ZHCSFZ3 –FEBRUARY 2017
www.ti.com.cn
目录
8.1 Overview ................................................................. 20
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 21
8.4 Device Functional Modes........................................ 23
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Applications ................................................ 25
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Power Ratings........................................................... 4
7.6 Insulation Specifications............................................ 5
7.7 Safety-Related Certifications..................................... 6
7.8 Safety Limiting Values .............................................. 6
7.9 Electrical Characteristics: AMC1305M05-Q1............ 7
7.10 Electrical Characteristics: AMC1305x25-Q1........... 9
7.11 Switching Characteristics...................................... 11
7.12 Insulation Characteristics Curves ......................... 12
7.13 Typical Characteristics.......................................... 13
Detailed Description ............................................ 20
9
10 Power-Supply Recommendations ..................... 29
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Examples................................................... 30
12 器件和文档支持 ..................................................... 32
12.1 文档支持................................................................ 32
12.2 相关链接................................................................ 32
12.3 接收文档更新通知 ................................................. 32
12.4 社区资源................................................................ 32
12.5 商标....................................................................... 32
12.6 静电放电警告......................................................... 32
12.7 Glossary................................................................ 32
13 机械、封装和可订购信息....................................... 33
8
4 修订历史记录
日期
修订版本
注释
2017 年2 月
*
首次发布。
2
Copyright © 2017, Texas Instruments Incorporated
AMC1305L25-Q1, AMC1305M05-Q1, AMC1305M25-Q1
www.ti.com.cn
ZHCSFZ3 –FEBRUARY 2017
5 Device Comparison Table
INPUT VOLTAGE
RANGE
DIFFERENTIAL INPUT
SNR (sinc3 Filter,
78 kSPS)
PART NUMBER
AMC1305L25-Q1
AMC1305M05-Q1
AMC1305M25-Q1
RESISTANCE
OUTPUT INTERFACE
±250 mV
±50 mV
25 kΩ
82 dB
76 dB
82 dB
LVDS
CMOS
CMOS
5 kΩ
±250 mV
25 kΩ
6 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
DW Package
16-Pin SOIC
Top View
NC
AINP
AINN
AGND
NC
1
2
3
4
5
6
7
8
16 DGND
NC
AINP
AINN
AGND
NC
1
2
3
4
5
6
7
8
16 DGND
NC
NC
15
14
13
12
11
10
9
15
14
13
12
11
10
9
DVDD
CLKIN
CLKIN_N
DOUT
DOUT_N
DGND
DVDD
CLKIN
NC
NC
NC
DOUT
NC
AVDD
AGND
AVDD
AGND
DGND
LVDS Versions (AMC1305L25-Q1)
CMOS Versions (AMC1305Mx-Q1)
Pin Functions
PIN
I/O
NAME
NO.
DESCRIPTION
This pin is internally connected to pin 8 and can be left unconnected or tied to high-side
ground
4
—
AGND
8
3
2
—
High-side ground reference
Inverting analog input
AINN
AINP
I
I
Noninverting analog input
High-side power supply, 4.5 V to 5.5 V.
See the Power-Supply Recommendations section for decoupling recommendations.
AVDD
7
—
CLKIN
CLKIN_N
DGND
13
I
Modulator clock input, 5 MHz to 20.1 MHz
12
I
AMC1305L25-Q1 only: inverted modulator clock input
Controller-side ground reference
9, 16
—
O
O
—
—
—
—
—
DOUT
11
Modulator data output
DOUT_N
DVDD
10
AMC1305L25-Q1 only: inverted modulator data output
Controller-side power supply, 3.0 to 5.5 V
14
1
This pin can be connected to AVDD or can be left unconnected
This pin can be left unconnected or tied to AGND only
These pins have no internal connection (pins 10 and 12 on the AMC1305Mx-Q1 only).
This pin can be left unconnected or tied to DVDD only
5
6, 10, 12
15
NC
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7 Specifications
7.1 Absolute Maximum Ratings
over the operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
6.5
UNIT
V
Supply voltage, AVDD to AGND or DVDD to DGND
Analog input voltage at AINP, AINN
AGND – 6
DGND – 0.3
–10
AVDD + 0.5
DVDD + 0.3
10
V
Digital input voltage at CLKIN, CLKIN_N
Input current to any pin except supply pins
Maximum virtual junction temperature, TJ
Storage temperature, Tstg
V
mA
°C
°C
150
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
5.0
MAX
UNIT
AVDD
DVDD
TA
High-side (analog) supply voltage
Controller-side (digital) supply voltage
Operating ambient temperature range
5.5
5.5
V
V
3.0
3.3
–40
125
°C
7.4 Thermal Information
AMC1305x-Q1
THERMAL METRIC(1)
DW (SOIC)
16 PINS
80.2
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
40.5
45.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
11.9
ψJB
44.5
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
PARAMETER
TEST CONDITIONS
VALUE
UNIT
Maximum power dissipation
(both sides)
PD
AVDD = 5.5 V, DVDD = 5.5 V, LVDS, RLOAD = 100 Ω
89.1
mW
Maximum power dissipation
(high-side supply)
PD1
PD2
AVDD = 5.5 V
45.1
44
mW
mW
Maximum power dissipation
(low-side supply)
DVDD = 5.5 V, LVDS, RLOAD = 100 Ω
4
Copyright © 2017, Texas Instruments Incorporated
AMC1305L25-Q1, AMC1305M05-Q1, AMC1305M25-Q1
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ZHCSFZ3 –FEBRUARY 2017
7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
Minimum air gap (clearance)(1)
Shortest pin-to-pin distance through air
≥ 8
≥ 8
mm
mm
Shortest pin-to-pin distance across the package
surface
CPG
Minimum external tracking (creepage)(1)
Minimum internal gap (internal clearance) of the
double insulation (2 × 0.0135 mm)
DTI
CTI
Distance through insulation
0.027
mm
V
Comparative tracking index
Material group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
≥ 600
I
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-III
I-II
Overvoltage category per IEC 60664-1
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12(2)
Maximum repetitive peak isolation
voltage
VIORM
At ac voltage (bipolar or unipolar)
1414
VPK
At ac voltage (sine wave)
At dc voltage
1000
1500
7000
VRMS
VDC
Maximum-rated isolation working
voltage
VIOWM
VTEST = VIOTM, t = 60 s (qualification test)
VIOTM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
VPK
VTEST = 1.2 x VIOTM, t = 1 s (100% production
test)
8400
Test method per IEC 60065, 1.2/50-μs
waveform, VTEST = 1.6 x VIOSM = 10000 VPK
(qualification)
VIOSM
6250
VPK
pC
pC
pC
Method a, after input/output safety test subgroup
2 / 3, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 x VIORM
= 1697 VPK, tm = 10 s
≤ 5
≤ 5
≤ 5
Method a, after environmental tests subgroup 1,
qpd
Apparent charge(4)
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 x VIORM
2263 VPK, tm = 10 s
=
Method b1, at routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s,
Vpd(m) = 1.875 x VIORM = 2652 VPK, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance, input to output(5)
Pollution degree
VIO = 0.5 VPP at 1 MHz
1.2
> 109
2
pF
VIO = 500 V at TS = 150°C
Ω
Climatic category
40/125/21
UL1577
VTEST = VISO = 5000 VRMS or 7000 VDC, t = 60 s
(qualification test), VTEST = 1.2 x VISO = 6000
VRMS, t = 1 s (100% production test)
VISO
Withstand isolation voltage
5000
VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves or ribs on the PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.
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7.7 Safety-Related Certifications
VDE
UL
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):
2006-12, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and DIN EN
60095 (VDE 0860): 2005-11
Recognized under UL1577 component recognition and CSA
component acceptance NO 5 programs
Reinforced insulation
Single protection
File number: 40040142
File number: E181974
7.8 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A
failure of the I/O circuitry may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient
power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
θJA = 80.2°C/W, AVDD = DVDD = 5.5 V, TJ = 150°C,
TA = 25°C, see Figure 3
283
mA
mA
IS
Safety input, output, or supply current
θJA = 80.2°C/W, AVDD = DVDD = 3.6 V, TJ = 150°C,
TA = 25°C, see Figure 3
432
PS Safety input, output, or total power
TS Maximum safety temperature
θJA = 80.2°C/W, TJ = 150°C, TA = 25°C, see Figure 4
1558(1)
150
mW
°C
(1) Input, output, or the sum of input and output power must not exceed this value.
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
6
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AMC1305L25-Q1, AMC1305M05-Q1, AMC1305M25-Q1
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ZHCSFZ3 –FEBRUARY 2017
7.9 Electrical Characteristics: AMC1305M05-Q1
All minimum and maximum specifications at TA = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP =
–50 mV to 50 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C,
CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Maximum differential voltage input range
(AINP-AINN)
VClipping
FSR
±62.5
mV
mV
Specified linear full-scale range
(AINP-AINN)
–50
50
VCM
CID
IIB
Operating common-mode input range
Differential input capacitance
Input current
–0.032
AVDD – 2
V
pF
2
–72
5
Inputs shorted to AGND
–97
15
-57
μA
RID
IOS
Differential input resistance
Input offset current
kΩ
±5
nA
CMTI
Common-mode transient immunity
kV/μs
fIN = 0 Hz,
CM min ≤ VIN ≤ VCM max
–104
V
CMRR
BW
Common-mode rejection ratio
Input bandwidth
dB
fIN from 0.1 Hz to 50 kHz,
CM min ≤ VIN ≤ VCM max
–75
800
V
kHz
DC ACCURACY
DNL
INL
Differential nonlinearity
Integral nonlinearity(1)
Resolution: 16 bits
Resolution: 16 bits
Initial, at 25°C
–0.99
–5
0.99
5
LSB
LSB
µV
±1.5
±2.5
EO
Offset error
–50
50
TCEO
EG
Offset error thermal drift(2)
Gain error
Gain error thermal drift(3)
–1.3
–0.3%
–40
1.3
0.3%
40
μV/°C
Initial, at 25°C
–0.02%
±20
TCEG
PSRR
ppm/°C
dB
Power-supply rejection ratio
VAVDD from 4.5 to 5.5V, at dc
105
AC ACCURACY
SNR
Signal-to-noise ratio
fIN = 1 kHz
fIN = 1 kHz
fIN = 1 kHz
fIN = 1 kHz
76
76
81
81
dB
dB
dB
dB
SINAD
THD
Signal-to-noise + distortion
Total harmonic distortion
Spurious-free dynamic range
–90
92
–83
SFDR
83
DIGITAL INPUTS/OUTPUTS
External Clock
fCLKIN
Input clock frequency
Duty cycle
5
20
20.1
60%
MHz
DutyCLKIN
5 MHz ≤ fCLKIN ≤ 20.1 MHz
DGND ≤ VIN ≤ DVDD
40%
50%
CMOS Logic Family, CMOS with Schmitt-Trigger
IIN
Input current
–1
1
μA
pF
V
CIN
VIH
Input capacitance
5
High-level input voltage
Low-level input voltage
Output load capacitance
0.7 × DVDD
–0.3
DVDD + 0.3
0.3 × DVDD
VIL
V
CLOAD
fCLKIN = 20 MHz
IOH = –20 µA
IOH = –4 mA
IOL = 20 µA
30
pF
DVDD – 0.1
DVDD – 0.4
VOH
High-level output voltage
Low-level output voltage
V
V
0.1
0.4
VOL
IOL = 4 mA
(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
valueMAX - valueMIN
TCEO
=
TempRange
(2) Offset error drift is calculated using the box method as described by the following equation:
≈ value MAX - value MIN
’
6
∆
∆
÷
÷
TCEG ( ppm) =
ì10
value ìTempRange
«
◊
(3) Gain error drift is calculated using the box method as described by the following equation:
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Electrical Characteristics: AMC1305M05-Q1 (continued)
All minimum and maximum specifications at TA = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP =
–50 mV to 50 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C,
CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
AVDD
IAVDD
High-side supply voltage
High-side supply current
High-side power dissipation
Controller-side supply voltage
4.5
5.0
6.5
5.5
8.2
V
mA
mW
V
PAVDD
DVDD
32.5
3.3
45.1
5.5
3.0
3.0 V ≤ DVDD ≤ 3.6 V
2.7
4.0
IDVDD
Controller-side supply current
mA
4.5 V ≤ DVDD ≤ 5.5 V
3.0 V ≤ DVDD ≤ 3.6 V
4.5 V ≤ DVDD ≤ 5.5 V
3.2
5.5
8.9
14.4
30.3
PDVDD
Controller-side power dissipation
mW
16.0
8
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AMC1305L25-Q1, AMC1305M05-Q1, AMC1305M25-Q1
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ZHCSFZ3 –FEBRUARY 2017
7.10 Electrical Characteristics: AMC1305x25-Q1
All minimum and maximum specifications at TA = –40°C to 125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP =
–250 mV to 250 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C,
CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Maximum differential voltage input range
(AINP-AINN)
VClipping
FSR
±312.5
mV
mV
Specified linear full-scale range
(AINP-AINN)
–250
250
VCM
CID
IIB
Operating common-mode input range
Differential input capacitance
Input current
–0.16
AVDD – 2
V
pF
1
–60
25
Inputs shorted to AGND
–82
15
–48
μA
RID
IOS
Differential input resistance
Input offset current
kΩ
±5
nA
CMTI
Common-mode transient immunity
kV/μs
fIN = 0 Hz,
CM min ≤ VIN ≤ VCM max
–95
V
CMRR
BW
Common-mode rejection ratio
Input bandwidth
dB
fIN from 0.1 Hz to 50 kHz,
CM min ≤ VIN ≤ VCM max
–76
V
1000
kHz
DC ACCURACY
DNL
INL
Differential nonlinearity
Integral nonlinearity(1)
Resolution: 16 bits
Resolution: 16 bits
Initial, at 25°C
–0.99
–4
0.99
4
LSB
LSB
±1.5
±40
EO
Offset error
–150
–1.3
–0.3
–40
150
1.3
0.3
40
µV
TCEO
EG
Offset error thermal drift(2)
Gain error
Gain error thermal drift(3)
μV/°C
%FS
ppm/°C
dB
Initial, at 25°C
–0.02
±20
90
TCEG
PSRR
Power-supply rejection ratio
VAVDD from 4.5 V to 5.5 V, at dc
AC ACCURACY
SNR
Signal-to-noise ratio
fIN = 1 kHz
fIN = 1 kHz
fIN = 1 kHz
fIN = 1 kHz
82
80
85
84
dB
dB
dB
dB
SINAD
THD
Signal-to-noise + distortion
Total harmonic distortion
Spurious-free dynamic range
–90
92
–83
SFDR
83
DIGITAL INPUTS/OUTPUTS
External Clock
fCLKIN
Input clock frequency
Duty cycle
5
20
20.1
60%
MHz
DutyCLKIN
5 MHz ≤ fCLKIN ≤ 20.1 MHz
40%
50%
CMOS Logic Family (AMC1305M25-Q1), CMOS with Schmitt-Trigger
IIN
Input current
DGND ≤ VIN ≤ DVDD
–1
1
μA
pF
V
CIN
VIH
Input capacitance
5
High-level input voltage
Low-level input voltage
Output load capacitance
0.7 × DVDD
–0.3
DVDD + 0.3
0.3 × DVDD
VIL
V
CLOAD
fCLKIN = 20 MHz
IOH = –20 µA
IOH = –4 mA
IOL = 20 µA
30
pF
DVDD – 0.1
DVDD – 0.4
VOH
High-level output voltage
Low-level output voltage
V
V
0.1
0.4
VOL
IOL = 4 mA
(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as the number of LSBs or as a percent of the specified linear full-scale range FSR.
valueMAX - valueMIN
TCEO
=
TempRange
(2) Offset error drift is calculated using the box method as described by the following equation:
≈ value MAX - value MIN
’
6
∆
∆
÷
÷
TCEG ( ppm) =
ì10
value ìTempRange
«
◊
(3) Gain error drift is calculated using the box method as described by the following equation:
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Electrical Characteristics: AMC1305x25-Q1 (continued)
All minimum and maximum specifications at TA = –40°C to 125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP =
–250 mV to 250 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C,
CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVDS Logic Family (AMC1305L25-Q1)
VOD
VOCM
IS
Differential output voltage
Output common-mode voltage
Output short-circuit current
Input common-mode voltage
Differential input voltage
Input current
RLOAD = 100 Ω
250
350
450
1.375
24
mV
V
1.125
1.23
mA
V
VICM
VID
VID = 100 mV
0.05
100
–24
1.25
350
0
3.25
600
20
mV
µA
IIN
DGND ≤ VIN ≤ 3.3 V
POWER SUPPLY
AVDD
IAVDD
High-side supply voltage
4.5
3.0
5.0
6.5
5.5
8.2
V
mA
mW
V
High-side supply current
PAVDD
DVDD
High-side power dissipation
Controller-side supply voltage
32.5
3.3
45.1
5.5
AMC1305L25-Q1, RLOAD = 100 Ω
6.1
8.0
AMC1305M25-Q1, 3.0 ≤ DVDD ≤ 3.6 V,
CLOAD = 5 pF
2.7
4.0
IDVDD
Controller-side supply current
mA
AMC1305M25-Q1, 4.5 ≤ DVDD ≤ 5.5 V,
CLOAD = 5 pF
3.2
20.1
8.9
5.5
44.0
14.4
AMC1305L25-Q1, RLOAD = 100 Ω
AMC1305M25-Q1, 3.0 ≤ DVDD ≤ 3.6 V,
CLOAD = 5 pF
PDVDD
Controller-side power dissipation
mW
AMC1305M25-Q1, 4.5 ≤ DVDD ≤ 5.5 V,
CLOAD = 5 pF
16.0
30.3
10
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7.11 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
49.75
19.9
TYP
50
MAX
200
120
120
UNIT
ns
tCLK
tHIGH
tLOW
tD
CLKIN, CLKIN_N clock period
CLKIN, CLKIN_N clock high time
CLKIN, CLKIN_N clock low time
25
ns
19.9
25
ns
Falling edge of CLKIN, CLKIN_N to DOUT, DOUT_N valid delay,
CLOAD = 5 pF
0
15
32
ns
Interface startup time
(DVDD at 3.0 V min to DOUT, DOUT_N valid with AVDD ≥ 4.5 V)
CLKIN
cycles
tISTART
tASTART
32
Analog startup time (AVDD step up to 4.5 V with DVDD ≥ 3.0 V)
1
ms
tCLK
tHIGH
/[YLb
/[YLb_b
tLOW
tD
5hÜÇ
5hÜÇ_b
Figure 1. Digital Interface Timing
5ë55
/[YLb
5hÜÇ
...
5ata not valid
ëalid data
tISTART = 32 CLKIN cycles
Figure 2. Digital Interface Startup Timing
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7.12 Insulation Characteristics Curves
500
1600
1400
1200
1000
800
600
400
200
0
AVDD = DVDD = 3.6 V
AVDD = DVDD = 5.5 V
400
300
200
100
0
0
50
100
150
200
0
50
100
150
200
TA (°C)
TA (°C)
D043
D044
Figure 3. Thermal Derating Curve for Safety Limiting
Current per VDE
Figure 4. Thermal Derating Curve for Safety Limiting Power
per VDE
TA up to 150°C, stress voltage frequency = 60 Hz
Figure 5. Reinforced Isolation Capacitor Lifetime Projection
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7.13 Typical Characteristics
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
AMC1305x25-Q1
AMC1305M05-Q1
AMC1305x25-Q1
AMC1305M05-Q1
Figure 6. Input Current vs Input Common-Mode Voltage
Figure 7. Common-Mode Rejection Ratio vs
Input Signal Frequency
4
3
4
3.5
3
2
1
2.5
2
0
-1
-2
-3
1.5
1
0.5
0
-4
-0.25 -0.2 -0.15 -0.1 -0.05
0
0.05 0.1 0.15 0.2 0.25
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VIN (mV)
D003
D004
Figure 8. Integral Nonlinearity vs Input Signal Amplitude
Figure 9. Integral Nonlinearity vs Temperature
150
125
100
75
50
40
30
20
50
10
25
0
0
-25
-50
-75
-100
-125
-150
-10
-20
-30
-40
-50
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
AVDD (V)
AVDD (V)
D005
D006
AMC1305x25-Q1
AMC1305M05-Q1
Figure 11. Offset Error vs High-Side Supply Voltage
Figure 10. Offset Error vs High-Side Supply Voltage
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
150
125
100
75
50
40
30
20
50
10
25
0
0
-25
-50
-75
-100
-125
-150
-10
-20
-30
-40
-50
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Temperature (èC)
D007
D008
AMC1305x25-Q1
AMC1305M05-Q1
Figure 12. Offset Error vs Temperature
Figure 13. Offset Error vs Temperature
0.3
0.2
0.1
0
AMC1305x25-Q1
AMC1305M05-Q1
-0.1
-0.2
-0.3
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
AVDD (V)
D010
Figure 15. Gain Error vs High-Side Supply Voltage
Figure 14. Offset Error vs Clock Frequency
0.3
0.2
0.1
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
-40 -25 -10
5
20 35 50 65 80 95 110 125
5
10
15
20
Temperature (èC)
fCLKIN (MHz)
D011
D012
Figure 16. Gain Error vs Temperature
Figure 17. Gain Error vs Clock Frequency
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
SNR (AMC1305x25-Q1)
SINAD (AMC1305x25-Q1)
SNR (AMC1305M05-Q1)
SINAD (AMC1305M05-Q1)
AMC1305x25-Q1
AMC1503M05-Q1
Figure 18. Power-Supply Rejection Ratio vs
Ripple Frequency
Figure 19. SNR and SINAD vs High-Side Supply Voltage
SNR (AMC1305x25-Q1)
SINAD (AMC1305x25-Q1)
SNR (AMC1305M05-Q1)
SINAD (AMC1305M05-Q1)
SNR (AMC1305x25-Q1)
SINAD (AMC1305x25-Q1)
SNR (AMC1305M05-Q1)
SINAD (AMC1305M05-Q1)
Figure 20. SNR and SINAD vs Temperature
Figure 21. SNR and SINAD vs Clock Frequency
100
SNR (AMC1305x25-Q1)
SINAD (AMC1305x25-Q1)
SNR (AMC1305M05-Q1)
SINAD (AMC1305M05-Q1)
SNR
SINAD
95
90
85
80
75
70
65
60
55
50
0
50 100 150 200 250 300 350 400 450 500
VIN (mVpp)
D018
AMC1305x25-Q1
Figure 23. SNR and SINAD vs Input Signal Amplitude
Figure 22. SNR and SINAD vs Input Signal Frequency
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
100
95
90
85
80
75
70
65
60
55
50
-60
SNR
SINAD
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
0
10
20
30
40
50
60
70
80
90 100
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
VIN (mVpp)
AVDD (V)
D019
D020
AMC1305M05-Q1
Figure 24. SNR and SINAD vs Input Signal Amplitude
Figure 25. Total Harmonic Distortion vs
High-Side Supply Voltage
-60
-60
-65
-65
-70
-70
-75
-75
-80
-80
-85
-85
-90
-90
-95
-95
-100
-105
-110
-100
-105
-110
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
5
10
15
20
fCLKIN (MHz)
D021
D022
Figure 26. Total Harmonic Distortion vs Temperature
Figure 27. Total Harmonic Distortion vs Clock Frequency
-60
-60
-65
-70
-65
-70
-75
-75
-80
-80
-85
-85
-90
-90
-95
-95
-100
-105
-110
-100
-105
-110
0.1
1
10
100
0
50 100 150 200 250 300 350 400 450 500
VIN (mVpp)
fIN (kHz)
D023
D024
AMC1305x25-Q1
Figure 28. Total Harmonic Distortion vs
Input Signal Frequency
Figure 29. Total Harmonic Distortion vs
Input Signal Amplitude
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
-60
110
105
100
95
-65
-70
-75
-80
90
-85
85
-90
80
-95
75
-100
-105
-110
70
65
60
0
50
100
150
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
VIN (mVpp)
AVDD (V)
D025
D026
AMC1305M05-Q1
Figure 30. Total Harmonic Distortion vs
Input Signal Amplitude
Figure 31. Spurious-Free Dynamic Range vs
High-Side Supply Voltage
110
105
100
95
110
105
100
95
90
90
85
85
80
80
75
75
70
70
65
65
60
60
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
5
10
15
20
fCLKIN (MHz)
D027
D028
Figure 32. Spurious-Free Dynamic Range vs Temperature
Figure 33. Spurious-Free Dynamic Range vs
Clock Frequency
110
105
100
95
110
105
100
95
90
90
85
85
80
80
75
75
70
70
65
65
60
60
0.1
1
10
100
0
50 100 150 200 250 300 350 400 450 500
VIN (mVpp)
fIN (kHz)
D029
D030
AMC1305x25-Q1
Figure 34. Spurious-Free Dynamic Range vs
Input Signal Frequency
Figure 35. Spurious-Free Dynamic Range vs
Input Signal Amplitude
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
110
105
100
95
0
-20
-40
90
-60
85
-80
80
75
-100
-120
-140
70
65
60
0
50
100
150
0
5
10
15
20
25
30
35
40
VIN (mVpp)
Frequency (kHz)
D031
D032
AMC1305M05-Q1
AMC1305x25-Q1, 4096-point FFT, VIN = 500 mVPP
Figure 36. Spurious-Free Dynamic Range vs
Input Signal Amplitude
Figure 37. Frequency Spectrum with 1-kHz Input Signal
0
-20
0
-20
-40
-60
-80
-40
-60
-80
-100
-120
-140
-100
-120
-140
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Frequency (kHz)
Frequency (kHz)
D033
D034
AMC1305x25-Q1, 4096-point FFT, VIN = 500 mVPP
AMC1305M05-Q1, 4096-point FFT, VIN = 500 mVPP
Figure 38. Frequency Spectrum with 5-kHz Input Signal
Figure 39. Frequency Spectrum with 1-kHz Input Signal
0
10
-20
-40
-60
-80
9
8
7
6
5
4
3
-100
-120
-140
0
5
10
15
20
25
30
35
40
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
Frequency (kHz)
AVDD (V)
D035
D036
AMC1305M05-Q1, 4096-point FFT, VIN = 500 mVPP
Figure 40. Frequency Spectrum with 5-kHz Input Signal
Figure 41. High-Side Supply Current vs
High-Side Supply Voltage
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
5
10
15
20
fCLKIN (MHz)
D037
D038
Figure 42. High-Side Supply Current vs Temperature
Figure 43. High-Side Supply Current vs Clock Frequency
12
11
10
9
12
LVDS
CMOS
LVDS
CMOS
11
10
9
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
3
3.1
3.2
3.3
3.4
3.5
3.6
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
DVDD (V)
DVDD (V)
D039
D040
Figure 44. Controller-Side Supply Current vs
Controller-Side Supply Voltage (3.3 V, nom)
Figure 45. Controller-Side Supply Current vs
Controller-Side Supply Voltage (5 V, nom)
12
11
10
9
12
11
10
9
LVDS 5 V
LVDS 3.3 V
CMOS 5 V
LVDS 5V
LVDS 3.3V
CMOS 5 V
CMOS 3.3 V
CMOS 3.3 V
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
5
10
15
20
Clock Frequency (MHz)
D041
D042
Figure 46. Controller-Side Supply Current vs Temperature
Figure 47. Controller-Side Supply Current vs
Clock Frequency
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8 Detailed Description
8.1 Overview
The differential analog input (AINP and AINN) of the AMC1305-Q1 is a fully-differential amplifier feeding the
switched-capacitor input of a second-order delta-sigma (ΔΣ) modulator stage that digitizes the input signal into a
1-bit output stream. The isolated data output (DOUT) of the converter provides a stream of digital ones and zeros
synchronous to the externally-provided clock source at the CLKIN pin with a frequency in the range of 5 MHz to
20.1 MHz. The time average of this serial bit-stream output is proportional to the analog input voltage.
The Functional Block Diagram section shows a detailed block diagram of the AMC1305-Q1. The analog input
range is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The
SiO2-based capacitive isolation barrier supports a high level of magnetic field immunity as described in the
application report ISO72x Digital Isolator Magnetic-Field Immunity (SLLA181A), available for download at
www.ti.com. The external clock input simplifies the synchronization of multiple current-sense channels on the
system level. The extended frequency range of up to 20.1 MHz supports higher performance levels compared to
other solutions available on the market.
8.2 Functional Block Diagram
DVDD
AVDD
AINP
AINN
BUF
BUF
TX
TX
DOUT
DOUT_N
(AMC1305L25-Q1 only)
-
ûꢀ-Modulator
+
TX
CLKIN
CLKIN_N
(AMC1305L25-Q1 only)
1.25-V
Reference
BUF
TX
AMC1305-Q1
DGND
AGND
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8.3 Feature Description
8.3.1 Analog Input
The AMC1305-Q1 incorporates front-end circuitry that contains a differential amplifier and sampling stage,
followed by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of
4 for devices with a specified input voltage range of ±250 mV (for the AMC1305x25-Q1), or to a factor of 20 for
devices with a ±50-mV input voltage range (for the AMC1305M05-Q1), resulting in a differential input impedance
of 5 kΩ (for the AMC1305M05-Q1) or 25 kΩ (for the AMC1305x25-Q1).
Consider the input impedance of the AMC1305-Q1 in designs with high-impedance signal sources that can
cause degradation of gain and offset specifications. The importance of this effect, however, depends on the
desired system performance. Additionally, the input bias current caused by the internal common-mode voltage at
the output of the differential amplifier causes an offset that depends on the actual amplitude of the input signal.
See the Isolated Voltage Sensing section for more details on reducing these effects.
There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the
range of AGND – 6 V to AVDD + 0.5 V, the input current must be limited to 10 mA because the device input
electrostatic discharge (ESD) protection diodes turn on. In addition, the linearity and noise performance of the
device are ensured only when the differential analog input voltage remains within the specified linear full-scale
range (FSR), that is ±250 mV (for the AMC1305x25-Q1) or ±50 mV (for the AMC1305M05-Q1), and within the
specified input common-mode range.
8.3.2 Modulator
The modulator implemented in the AMC1305-Q1 is a second-order, switched-capacitor, feed-forward ΔΣ
modulator, such as the one conceptualized in Figure 48. The analog input voltage VIN and the output V5 of the 1-
bit digital-to-analog converter (DAC) are differentiated, providing an analog voltage V1 at the input of the first
integrator stage. The output of the first integrator feeds the input of the second integrator stage, resulting in
output voltage V3 that is differentiated with the input signal VIN and the output of the first integrator V2. Depending
on the polarity of the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC
responds on the next clock pulse by changing its analog output voltage V5, causing the integrators to progress in
the opposite direction while forcing the value of the integrator output to track the average value of the input.
f/[YLb
ë1
ë2
ë3
ë4
ëLb
Integrator 1
Integrator 2
ꢀ
ꢀ
/at
0 ë
ë5
DAC
Figure 48. Block Diagram of a Second-Order Modulator
The modulator shifts the quantization noise to high frequencies; see Figure 49. Therefore, use a low-pass digital
filter at the output of the device to increase overall performance. This filter is also used to convert from the 1-bit
data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's microcontroller
family TMS320F2837x offers a suitable programmable, hardwired filter structure termed a sigma-delta filter
module (SDFM) optimized for usage with the AMC1305-Q1 family. Alternatively, a field-programmable gate array
(FPGA) can be used to implement the digital filter.
Copyright © 2017, Texas Instruments Incorporated
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ZHCSFZ3 –FEBRUARY 2017
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Feature Description (continued)
0
-20
-40
-60
-80
-100
-120
-140
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 49. Quantization Noise Shaping
8.3.3 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A
differential input of 250 mV (for the AMC1305x25-Q1) or 50 mV (for the AMC1305M05-Q1) produces a stream of
ones and zeros that are high 90% of the time. A differential input of –250 mV (–50 mV for the AMC1305M05-Q1)
produces a stream of ones and zeros that are high 10% of the time. These input voltages are also the specified
linear ranges of the different AMC1305-Q1 versions with performance as specified in this document. If the input
voltage value exceeds these ranges, the output of the modulator shows non-linear behavior while the
quantization noise increases. The output of the modulator would clip with a stream of only zeros with an input
less than or equal to –312.5 mV (–62.5 mV for the AMC1305M05-Q1) or with a stream of only ones with an input
greater than or equal to 312.5 mV (62.5 mV for the AMC1305M05-Q1). In this case, however, the AMC1305-Q1
generates a single 1 (if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device
function (see the Fail-Safe Output section for more details). The input voltage versus the output modulator signal
is shown in Figure 50.
The density of ones in the output bit-stream for any input voltage value (with the exception of a full-scale input
signal as described in Output Behavior in Case of Full-Scale Input ) can be calculated using Equation 1:
V IN + VClipping
2 * VClipping
(1)
The AMC1305-Q1 system clock is typically 20 MHz and is provided externally at the CLKIN pin. Data are
synchronously provided at 20 MHz at the DOUT pin. Data change at the CLKIN falling edge. For more details,
see the Switching Characteristics table.
Modulator Output
+FS (Analog Input)
-FS (Analog Input)
Analog Input
Figure 50. Analog Input versus AMC1305-Q1 Modulator Output
22
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8.4 Device Functional Modes
8.4.1 Fail-Safe Output
In the case of a missing high-side supply voltage (AVDD), the output of a ΔΣ modulator is not defined and could
cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable.
Therefore, the AMC1305-Q1 implements a fail-safe output function that ensures the device maintains its output
level in case of a missing AVDD, as shown in Figure 51.
/[YLb
!ë55
5hÜÇ
5hÜÇ
!ë55 Dhh5
!ë55 C!L[
/ase 1: 5hÜÇ = Z1[ ÁZꢀv !ë55 (ꢁ]o•
/ase 2: 5hÜÇ = Z0[ ÁZꢀv !ë55 (ꢁ]o•
Figure 51. Fail-Safe Output of the AMC1305-Q1
8.4.2 Output Behavior in Case of Full-Scale Input
If a full-scale input signal is applied to the AMC1305-Q1 (that is, VIN ≥ VClipping), the device generates a single
one or zero every 128 bits at DOUT, depending on the actual polarity of the signal being sensed, as shown in
Figure 52.
In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the system level.
/[YLb
...
...
5hÜÇ
5hÜÇ
ëLb ≤ 312.5 mV (AMC1305M05: 61.5 mV)
...
...
...
...
ëLb ≥ 312.5 mV (AMC1305M05: 61.5 mV)
127 /[YLb cycles
127 /[YLb cycles
Figure 52. Overrange Output of the AMC1305-Q1
Copyright © 2017, Texas Instruments Incorporated
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Digital Filter Usage
The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort
and hardware, is a sinc3-type filter, as shown in Equation 2:
3
-OSR
≈
’
1- z
∆
∆
÷
÷
H(z) =
1- z-1
«
◊
(2)
This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-
order modulator. All the characterization in this document is also done with a sinc3 filter with an over-sampling
ratio (OSR) of 256 and an output word width of 16 bits.
(3)
16
14
12
10
8
6
4
sinc1
sinc2
sinc3
2
0
1
10
100
1000
OSR
D053
Figure 53. Measured Effective Number of Bits versus Oversampling Ratio
An example code for an implementation of a sinc3 filter in an FPGA, see the application note Combining
ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control Applications (SBAA094), available
for download at www.ti.com.
24
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9.2 Typical Applications
9.2.1 Traction Inverter Application
Because to their high ac and dc performance, isolated ΔΣ modulators are being widely used in new generation
traction inverter designs. Traction inverters are critical parts of electrical and hybrid electrical vehicles. The input
structure of the AMC1305-Q1 is optimized for use with low-impedance shunt resistors and is therefore tailored for
isolated current sensing using shunts.
DC link
Gate Driver
Gate Driver
Gate Driver
RSHUNT
RSHUNT
RSHUNT
Gate Driver
Gate Driver
Gate Driver
AMC1305-Q1
TMS320F2837x
SD-D1
AVDD
AINP
DVDD
DOUT
CLKIN
DGND
5.0 V
3.3 V
AINN
AGND
SD-C1
AMC1305-Q1
AVDD
DVDD
DOUT
CLKIN
DGND
5.0 V
3.3 V
AINP
AINN
AGND
SD-D2
SD-C3
AMC1305-Q1
AMC1305-Q1
AVDD
AINP
DVDD
5.0 V
3.3 V
AVDD
DVDD
DOUT
CLKIN
DGND
5.0 V
3.3 V
DOUT
CLKIN
DGND
SD-D4
SD-C4
AINP
AINN
AGND
AINN
AGND
PWMx
SD-D5
SD-C5
Copyright © 2016, Texas Instruments Incorporated
Figure 54. The AMC1305-Q1 in a Traction Inverter Application
9.2.1.1 Design Requirements
A typical operation of the device in a traction inverter application is shown in Figure 54. When the inverter stage
is part of a motor drive system, measurement of the motor phase current is done via the shunt resistors (RSHUNT).
Depending on the system design, either all three or only two phase currents are sensed.
In this example, an additional fourth AMC1305-Q1 is used to support isolated voltage sensing of the dc link. This
high voltage is reduced using a high-impedance resistive divider before being sensed by the device across a
smaller resistor. The value of this resistor can degrade the performance of the measurement, as described in the
Isolated Voltage Sensing section.
9.2.1.2 Detailed Design Procedure
The usually recommended RC filter in front of a ΔΣ modulator to improve signal-to-noise performance of the
signal path, is not required for the AMC1305-Q1. By design, the input bandwidth of the analog front-end of the
device is limited to 1 MHz.
For modulator output bit-stream filtering, a device from TI's TMS320F2837x family of dual-core MCUs is
recommended. This family supports up to eight channels of dedicated hardwired filter structures that significantly
simplify system level design by offering two filtering paths per channel: one providing high accuracy results for
the control loop and one fast response path for overcurrent detection.
Copyright © 2017, Texas Instruments Incorporated
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Typical Applications (continued)
9.2.1.3 Application Curve
In motor control applications, a very fast response time for overcurrent detection is required. The time for fully
settling the filter in case of a step-signal at the input of the modulator depends on its order; that is, a sinc3 filter
requires three data updates for full settling (with fDATA = fCLK / OSR). Therefore, for overcurrent protection, filter
types other than sinc3 can be a better choice; an alternative is the sinc2 filter. Figure 55 compares the settling
times of different filter orders.
16
14
12
10
8
6
4
sinc1
sinc2
sinc3
2
0
0
2
4
6
8
10
12
14
16
18
20
settling time (µs)
D054
Figure 55. Measured Effective Number of Bits versus Settling Time
The delay time of the sinc filter with a continuous signal is half of its settling time.
26
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Typical Applications (continued)
9.2.2 Isolated Voltage Sensing
The AMC1305-Q1 is optimized for usage in current-sensing applications using low-impedance shunts. However,
the device can also be used in isolated voltage-sensing applications if the impact of the (usually higher)
impedance of the resistor used in this case is considered.
High Voltage
Potential
5 V
R1
AVDD
AINP
AMC1305-Q1
R2
R3
R4
R5
IIB
-
RID
ûꢀ Modulator
+
AINN
R3'
R4'
R5'
AGND
VCM = 2 V
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 56. Using AMC1305-Q1 for Isolated Voltage Sensing
9.2.2.1 Design Requirements
Figure 56 shows a simplified circuit typically used in high-voltage sensing applications. The high impedance
resistors (R1 and R2) are used as voltage dividers and dominate the current value definition. The resistance of
the sensing resistor R3 is chosen to meet the input voltage range of the AMC1305-Q1. This resistor and the
differential input impedance of the device (the AMC1305x25-Q1 is 25 kΩ, the AMC1305M05-Q1 is 5 kΩ) also
create a voltage divider that results in an additional gain error. With the assumption of R1, R2, and RIN having a
considerably higher value than R3, the resulting total gain error can be estimated using Equation 4, with EG
being the gain error of the AMC1305-Q1.
R3
EGtot = EG
+
RIN
(4)
This gain error can be easily minimized during the initial system level gain calibration procedure.
9.2.2.2 Detailed Design Procedure
As indicated in Figure 56, the output of the integrated differential amplifier is internally biased to a common-mode
voltage of 2 V. This voltage results in a bias current IIB through the resistive network R4 and R5 (or R4' and R5')
used for setting the gain of the amplifier. The value range of this current is specified in the Electrical
Characteristics table. This bias current generates additional offset error that depends on the value of the resistor
R3. Because the value of this bias current depends on the actual common-mode amplitude of the input signal (as
shown in Figure 57), the initial system offset calibration does not minimize its effect. Therefore, in systems with
high accuracy requirements TI recommends using a series resistor at the negative input (AINN) of the AMC1305-
Q1 with a value equal to the shunt resistor R3 (that is R3' = R3 in Figure 56) to eliminate the effect of the bias
current.
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Typical Applications (continued)
This additional series resistor (R3') influences the gain error of the circuit. The effect can be calculated using
Equation 5 with R5 = R5' = 50 kΩ and R4 = R4' = 2.5 kΩ (for the AMC1305M05-Q1) or 12.5 kΩ (for the
AMC1305x25-Q1).
R4
≈
’
÷
E (%) = 1 -
*100%
∆
G
R4'+R3'
«
◊
(5)
9.2.2.3 Application Curve
Figure 57 shows the dependency of the input bias current on the common-mode voltage at the input of the
AMC1305-Q1.
AMC1305x25-Q1
AMC1305M05-Q1
Figure 57. Input Current vs Input Common-Mode Voltage
28
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ZHCSFZ3 –FEBRUARY 2017
10 Power-Supply Recommendations
In a typical traction inverter application, the high-side power supply (AVDD) for the device is derived from the
floating power supply of the upper gate driver. For lowest cost, a Zener diode can be used to limit the voltage to
5 V ±10%. Alternatively a low-cost low-drop regulator (LDO), for example the LP2951-xx-Q1, can be used to
minimize noise on the power supply. A low-ESR decoupling capacitor of 0.1 µF is recommended for filtering this
power-supply path. Place this capacitor (C2 in Figure 58) as close as possible to the AVDD pin of the AMC1305-
Q1 for best performance. If better filtering is required, an additional 10-µF capacitor can be used. The floating
ground reference (AGND) is derived from the end of the shunt resistor, which is connected to the negative input
(AINN) of the device. If a four-pin shunt is used, the device inputs are connected to the inner leads, while AGND
is connected to one of the outer leads of the shunt.
For decoupling of the digital power supply on controller side, TI recommends using a 0.1-µF capacitor assembled
as close to the DVDD pin of the AMC1305-Q1 as possible, followed by an additional capacitor in the range of
1 µF to 10 µF.
Floating
Power Supply
HV+
20 V
R1
800 ꢀ
AMC1305-Q1
Gate Driver
5.1 V
DVDD
AVDD
3.3 V, or 5.0 V
C1
10 ꢁF
C4
0.1 ꢁF
C2
0.1 ꢁF
C5
2.2 ꢁF
Z1
1N751A
AGND
AINN
DGND
DOUT
TMS320F2837x
SD-Dx
RSHUNT
To Load
SD-Cx
PWMx
AINP
CLKIN
Gate Driver
Copyright © 2016, Texas Instruments Incorporated
HV-
Figure 58. Zener-Diode-Based High-Side Power Supply
Copyright © 2017, Texas Instruments Incorporated
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ZHCSFZ3 –FEBRUARY 2017
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11 Layout
11.1 Layout Guidelines
A layout recommendation showing the critical placement of the decoupling capacitors (as close as possible to the
AMC1305-Q1) and placement of the other components required by the device is shown in Figure 59.
For the AMC1305L25-Q1 version, place the 100-Ω termination resistor as close as possible to the CLKIN,
CLKIN_N inputs of the device to achieve highest signal integrity. If not integrated, an additional termination
resistor is required as close as possible to the LVDS data inputs of the MCU or filter device; see Figure 60.
11.2 Layout Examples
Top View
Clearance area
to be kept free of any
conductive materials
1
NC
AINP
AINN
AGND
NC
DGND
NC
16
0.1 µF
SMD
0603
From shunt
resistor
DVDD
CLKIN
NC
AMC1305Mxx-Q1
to/from
MCU
(filter)
DOUT
NC
NC
LEGEND
TOP layer:
copper pour & traces
AVDD
AGND
0.1 µF
high-side area
SMD
0603
controller-side area
DGND
via to ground plane
via to supply plane
Copyright © 2016, Texas Instruments Incorporated
Figure 59. Recommended Layout of the AMC1305Mx-Q1
30
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AMC1305L25-Q1, AMC1305M05-Q1, AMC1305M25-Q1
www.ti.com.cn
ZHCSFZ3 –FEBRUARY 2017
Layout Examples (continued)
to/from
MCU
(filter)
Copyright © 2016, Texas Instruments Incorporated
Figure 60. Recommended Layout of the AMC1305L25-Q1
版权 © 2017, Texas Instruments Incorporated
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12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
相关文档请参阅以下部分：
•
•
•
•
•
隔离相关术语
《ISO72x 数字隔离器磁场抗扰度》
《使用 ADS1202 与 FPGA 数字滤波器的组合测量 测量》
《LP2951-xx-Q1 具有关断功能的可调节微功耗稳压器》
《TMS320F2837xD 双核 Delfino™ 微控制器》
12.2 相关链接
下面的表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可通过快速访问立刻订
购。
表 1. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
AMC1305L25-Q1
AMC1305M05-Q1
AMC1305M25-Q1
12.3 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017, Texas Instruments Incorporated
33
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC1305L25QDWQ1
AMC1305L25QDWRQ1
AMC1305M05QDWQ1
AMC1305M05QDWRQ1
AMC1305M25QDWQ1
AMC1305M25QDWRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
DW
16
16
16
16
16
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1305L25Q1
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
1305L25Q1
1305M05Q1
1305M05Q1
1305M25Q1
1305M25Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
R0.05 TYP
9
8
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
R0.05 TYP
8
9
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
R0.05 TYP
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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