AM62A74AUMSIAMBQ1 [TI]
2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras | AMB | 484 | -40 to 125;
| 型号： | AM62A74AUMSIAMBQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras | AMB | 484 | -40 to 125 |
| 文件： | 总218页 (文件大小：4175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
SPRSP77 – MARCH 2023
AM62Ax Sitara™ Processors
•
One Camera Serial interface (CSI-2) Receiver with
4-Lane D-PHY
1 Features
– MIPI® CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
– Support for 1,2,3 or 4 data lane mode up to 1.5
Gbps per lane
– ECC verification/correction with CRC check +
ECC on RAM
– Virtual Channel support (up to 16)
– Ability to write stream data directly to DDR via
DMA
Video Encoder/Decoder
– Support for HEVC (H.265) Main profiles at
Level 5.1 High-tier
– Support for H.264 BaseLine/Main/High Profiles
at Level 5.2
– Support for up to 4K UHD resolution
(3840 × 2160)
Processor Cores:
•
Up to Quad Arm® Cortex®-A53 microprocessor
subsystem at up to 1.4 GHz
– Quad-core Cortex-A53 cluster with 512KB L2
shared cache with SECDED ECC
– Each A53 core has 32KB L1 DCache with
SECDED ECC and 32KB L1 ICache with Parity
protection
•
•
Single-core Arm® Cortex®-R5F at up to 800 MHz,
integrated as part of MCU Channel with FFI
– 32KB ICache, 32KB L1 DCache, and 64KB
TCM with SECDED ECC on all memories
– 512KB SRAM with SECDED ECC
Single-core Arm® Cortex®-R5F at up to 800 MHz,
integrated to support Device Management
– 32KB ICache, 32KB L1 DCache, and 64KB
TCM with SECDED ECC on all memories
Deep Learning Accelerator based on Single-core
C7x
•
•
•
Clocking options supporting 240 MPixels/s,
120 MPixels/s, or 60 MPixels/s
Motion JPEG encode at 416 MPixels/s with
resolutions up to 4K UHD (3840 × 2160)
•
Memory Subsystem:
– C7x floating point, up to 40 GFLOPS, 256-bit
Vector DSP at 1.0 GHz
– Matrix Multiply Accelerator (MMA), up to 2
TOPS (8b) at 1.0 GHz
– 32KB L1 DCache with SECDED ECC and
64KB L1 ICache with Parity protection
– 1.25MB of L2 SRAM with SECDED ECC
•
Up to 2.29MB of On-chip RAM
– 64KB of On-Chip RAM (OCRAM) with
SECDED ECC, can be divided into smaller
banks in increments of 32KB for as many as
2 separate memory banks
– 256KB of On-Chip RAM with SECDED ECC in
SMS Subsystem
– 176KB of On-Chip RAM with SECDED ECC in
SMS Subsystem for TI security firmware
– 512KB of On-chip RAM with SECDED ECC in
Cortex-R5F MCU Subsystem
•
Vision Processing Accelerators (VPAC) with Image
Signal Processor (ISP) and multiple vision assist
accelerators:
– 315 MPixel/s ISP; Up to 5MP @ 60 fps
– Support for 12-bit RGB-IR
– 64KB of On-chip RAM with SECDED ECC in
Device/Power Manager Subsystem
– 1.25MB of L2 SRAM with SECDED ECC in C7x
Deep Learning Accelerator
– Support for up to 16-bit input RAW format
– Line support up to 4096
– Wide Dynamic Range (WDR), Lens Distortion
Correction (LDC), Vision Imaging Subsystem
(VISS), and Multi-Scalar (MSC) support
•
DDR Subsystem (DDRSS)
– Supports LPDDR4
•
Output color format : 8-bits, 12-bits, and
YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL
– 32-bit data bus with inline ECC
– Supports speeds up to 3733 MT/s
– Max addressable range of 8GBytes
Multimedia:
•
Display subsystem
– Single display support
– Up to 2048x1080 @ 60fps
– Up to 165-MHz pixel clock support with
independent PLL
– DPI 24-bit RGB parallel interface
– Supports safety features such as freeze frame
detection and MISR data check
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
SPRSP77 – MARCH 2023
www.ti.com
Functional Safety:
High-Speed Interfaces:
• Integrated Ethernet switch supporting (total 2
•
•
•
Functional Safety-Compliant targeted [Industrial]
– Developed for functional safety applications
– Documentation will be available to aid IEC
61508 functional safety system design
– Systematic capability up to SIL 3 targeted
– Hardware Integrity up to SIL 2 targeted
– Safety-related certification
external ports)
– RMII(10/100) or RGMII (10/100/1000)
– IEEE1588 (Annex D, Annex E, Annex F with
802.1AS PTP)
– Clause 45 MDIO PHY management
– Packet Classifier based on ALE engine with
512 classifiers
•
IEC 61508 by TÜV SÜD planned
– Priority based flow control
Functional Safety-Compliant targeted [Automotive]
– Developed for functional safety applications
– Documentation will be available to aid ISO
26262 functional safety system design
– Systematic capability up to ASIL D targeted
– Hardware integrity up to ASIL B targeted
– Safety-related certification
– Time Sensitive Networking (TSN) support
– Four CPU H/W interrupt Pacing
– IP/UDP/TCP checksum offload in hardware
Two USB2.0 Ports
•
– Port configurable as USB host, USB peripheral,
or USB Dual-Role Device (DRD mode)
– Integrated USB VBUS detection
•
ISO 26262 by TÜV SÜD planned
AEC-Q100 qualified [Automotive]
General Connectivity:
Security:
•
9x Universal Asynchronous Receiver-Transmitters
(UART)
5x Serial Peripheral Interface (SPI) controllers
6x Inter-Integrated Circuit (I2C) ports
3x Multichannel Audio Serial Ports (McASP)
•
Secure boot supported
•
•
•
– Hardware-enforced Root-of-Trust (RoT)
– Support to switch RoT via backup key
– Support for takeover protection, IP protection,
and anti-roll back protection
– Transmit and Receive Clocks up to 50 MHz
– Up to 16/10/6 Serial Data Pins across 3x
McASP with Independent TX and RX Clocks
– Supports Time Division Multiplexing (TDM),
Inter-IC Sound (I2S), and Similar Formats
– Supports Digital Audio Interface Transmission
(SPDIF, IEC60958-1, and AES-3 Formats)
– FIFO Buffers for Transmit and Receive (256
Bytes)
– Support for audio reference output clock
3x enhanced PWM modules (ePWM)
3x enhanced Quadrature Encoder Pulse modules
(eQEP)
3x enhanced Capture modules (eCAP)
General-Purpose I/O (GPIO), All LVCMOS I/O can
be configured as GPIO
3x Controller Area Network (CAN) modules with
CAN-FD support
– Conforms w/ CAN Protocol 2.0 A, B and ISO
11898-1
– Full CAN FD support (up to 64 data bytes)
– Parity/ECC check for Message RAM
– Speed up to 8 Mbps
•
Trusted Execution Environment (TEE) supported
– Arm TrustZone® based TEE
– Extensive firewall support for isolation
– Secure watchdog/timer/IPC
– Secure storage support
– Replay Protected Memory Block (RPMB)
support
•
•
Dedicated Security Controller with user
programmable HSM core and dedicated security
DMA & IPC subsystem for isolated processing
Cryptographic acceleration supported
•
•
– Session-aware cryptographic engine with ability
to auto-switch key-material based on incoming
data stream
•
•
•
Supports cryptographic cores
•
– AES – 128-/192-/256-Bit key sizes
– SHA2 – 224-/256-/384-/512-Bit key sizes
– DRBG with true random number generator
– PKA (Public Key Accelerator) to Assist in
RSA/ECC processing for secure boot
Debugging security
•
– Secure software controlled debug access
– Security aware debugging
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SPRSP77 – MARCH 2023
Media and Data Storage:
Power Management:
•
3x Secure Digital® (SD®) (4b+4b+8b) interface
– 1x 8-bit eMMC interface up to HS200 speed
– 2x 4-bit SD/SDIO interface up to UHS-I
– Compliant with eMMC 5.1, SD 3.0, and SDIO
Version 3.0
•
Low-power modes supported by Device/Power
Manager
– Partial IO support for CAN/GPIO/UART wakeup
– DeepSleep : I/O + DDR (suspend to RAM)
– DeepSleep
•
1× General-Purpose Memory Controller (GPMC)
up to 133 MHz
– MCU Only
– Standby
– Dynamic frequency scaling for Cortex-A53
– Flexible 8- and 16-bit Asynchronous Memory
Interface with up to four Chip (22-bit address)
Selects (NAND, NOR, Muxed-NOR, and
SRAM)
– Uses BCH code to support 4-, 8-, or 16-bit ECC
– Uses Hamming code to support 1-bit ECC
– Error Locator Module (ELM)
Boot Options:
•
•
•
•
•
•
•
•
•
UART
I2C EEPROM
OSPI/QSPI Flash
GPMC NOR/NAND Flash
SD Card
eMMC
USB (host) Mass storage
USB (device) boot from external host (DFU mode)
Ethernet
•
Used with the GPMC to locate addresses
of data errors from syndrome polynomials
generated using a BCH algorithm
Supports 4-, 8-, and 16-bit per 512-
Byte block error location based on BCH
algorithms
•
Technology / Package:
•
OSPI/QSPI with DDR / SDR support
– Support for Serial NAND and Serial NOR Flash
devices
– 4GBytes memory address support
– XIP mode with optional on-the-fly encryption
•
•
16-nm FinFET technology
18 mm x 18 mm, 0.8-mm pitch full-array, 484-pin
FCBGA (AMB)
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SPRSP77 – MARCH 2023
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2 Applications
•
•
•
•
•
•
•
Driver Monitoring System (DMS) / Occupancy Monitoring System (OMS)
eMirror/Camera Mirror System (CMS)
Machine Vision Camera
Barcode scanner
Front camera system
Stick up camera / Video doorbell
Autonomous Mobile Robots (AMR)
3 Description
AM62Ax is an extension of the Sitara™ automotive-grade family of heterogeneous Arm® processors with
embedded Deep Learning (DL), Video and Vision Processing acceleration, display interface and extensive
automotive peripheral and networking options. AM62Ax is built for a set of cost-sensitive automotive applications
including driver and in-cabin monitoring systems, next generation of eMirror system, as well as a broad set
of industrial applications in Factory Automation, Building Automation, and other markets. The cost optimized
AM62Ax provides high-performance compute for both traditional and deep learning algorithms at industry
leading power/performance ratios with a high level of system integration to enable scalability and lower costs
for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units
(ECUs).
AM62Ax contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator
(VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL) and video
accelerators, a Cortex®-R5F MCU Channel core and a Cortex®-R5F Device Management core. The Cortex-
A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of
traditional vision computing based-algorithms such as driver monitoring. Building on the existing world-class ISP,
TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR),
support for higher bit depth, and features targeting analytics applications. Key cores include the next generation
C7000™ DSP from Texas Instruments (“C7x”) with scalar and vector cores, dedicated “MMA” deep learning
accelerator enabling performance up to 2 TOPS within the lowest power envelope in the industry when operating
at the typical automotive worst case junction temperature of 125°C.
The 3-port Gigabit Ethernet switch has one internal port and two external ports with TSN support and can be
used to enable industrial networking options. In addition, an extensive peripherals set is included in AM62Ax
to enable system level connectivity such as USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for
parallel host interface to an external ASIC/FPGA. AM62Ax supports secure boot for IP protection with the built-in
HSM (Hardware Security Module) and also employs advanced power management support for portable and
power-sensitive applications.
Package Information
PART NUMBER
XAM62A7x...AMB
XAM62A3x...AMB
PACKAGE(1)
BODY SIZE
18 mm x 18 mm
18 mm x 18 mm
FCBGA (484-pin) 0.8mm full array
FCBGA (484-pin) 0.8mm full array
(1) For more information, see Section 11, Mechanical, Packaging, and Orderable Information.
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SPRSP77 – MARCH 2023
3.1 Functional Block Diagram
Figure 3-1 is functional block diagram for the device.
AM62Ax
Application Cores
MCU Channel
with FFI
Device Management
Arm®
Arm®
®
64KB TCM
Cortex®-R5F
with ECC
Arm
Cortex -A53
Arm®
Cortex®-A53
®
Cortex®-R5F
Arm®
®
64KB TCM
with ECC
Arm
Cortex -A53
Deep Learning Accelerator (2 TOPS)
C7x256v and MMA
Cortex®-A53
®
1.25MB Dedicated L2 SRAM
with ECC
512KB SRAM
with ECC
512KB Shared L2 with ECC
System Memory
Safety DTK
64KB SRAM
with ECC
(Shared)
GPMC
General Connectivity and IO
General Connectivity
(MCUSS)
2-port Gb Ethernet w/ 1588
DDR4/LPDDR4
with inline ECC
(32b)
3x MMCSD
GPIO
GPIO
2x SPI
UART
3x SPI
8x UART
CAN-FD
5x I2C
3x ePWM
3x eCAP
3x eQEP
2x USB 2.0
Multimedia
3x McASP
JPEG Encode
RGB-IR VPAC
CSI2 -Rx 4L
2x CAN-FD
I2C
1x Display
with DPI
H.264/H.265
Video Codec
OSPI
Security
HSM
(Secure Boot)
SHA
MD5
PKA
DRBG
TRNG
SMS
AES
432KB SRAM with ECC
System Services
DMA
Firewall
DCC
ESM
ECC
Device/Power
Manager
System
Monitor
Secure
Boot
Debug
Timers
IPC
Figure 3-1. Functional Block Diagram
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SPRSP77 – MARCH 2023
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................4
3 Description.......................................................................4
3.1 Functional Block Diagram...........................................5
4 Revision History.............................................................. 6
5 Device Comparison.........................................................7
5.1 Related Products........................................................ 8
6 Terminal Configuration and Functions..........................9
6.1 Pin Diagrams.............................................................. 9
6.2 Pin Attributes.............................................................10
6.3 Signal Descriptions................................................... 44
6.4 Pin Connectivity Requirements.................................70
7 Specifications................................................................ 74
7.1 Absolute Maximum Ratings...................................... 74
7.2 ESD Ratings............................................................. 76
7.3 Power-On Hours (POH)............................................76
7.4 Recommended Operating Conditions.......................77
7.5 Operating Performance Points..................................79
7.6 Electrical Characteristics...........................................81
7.7 VPP Specifications for One-Time Programmable
7.8 Thermal Resistance Characteristics......................... 87
7.9 Timing and Switching Characteristics....................... 88
8 Detailed Description....................................................198
8.1 Overview.................................................................198
9 Applications, Implementation, and Layout............... 199
9.1 Device Connection and Layout Fundamentals....... 199
9.2 Peripheral- and Interface-Specific Design
Information................................................................ 200
10 Device and Documentation Support........................207
10.1 Device Nomenclature............................................207
10.2 Tools and Software............................................... 210
10.3 Documentation Support........................................ 210
10.4 Support Resources............................................... 210
10.5 Trademarks...........................................................210
10.6 Electrostatic Discharge Caution............................211
10.7 Glossary................................................................211
11 Mechanical, Packaging, and Orderable
Information.................................................................. 212
11.1 Packaging Information.......................................... 212
(OTP) eFuses..............................................................86
4 Revision History
DATE
REVISION
NOTES
March 2023
*
Initial Release.
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SPRSP77 – MARCH 2023
5 Device Comparison
Table 5-1 shows a comparison between devices, highlighting the differences.
Note
Availability of features listed in this table are a function of shared IO pins, where IO signals associated
with many of the features are multiplexed to a limited number of pins. The SysConfig tool should
be used to assign signal functions to pins. This will provide a better understanding of limitations
associated with pin multiplexing.
Note
To understand what device features are currently supported by TI Software Development Kits (SDKs),
see the AM62Ax Software Build Sheet.
Table 5-1. Device Comparison
AM62A7
AM62A3
REFERENCE
NAME
FEATURES
AM62A74 AM62A72
AM62A34
TBD
AM62A32
AM62A31
TBD
CTRLMMR_WKUP_JTAG_DEVICE_ID[31:13]
DEVICE_ID register bit field value(1)
TBD
TBD
TBD
PROCESSORS AND ACCELERATORS
Speed Grades
See Table 7-1, Device Speed Grades
Arm Cortex-A53
Microprocessor Subsystem
Arm A53
Quad Core
Dual Core
Quad Core
Dual Core
Single Core
Single Core
Arm Cortex-R5F in MCU domain
MCU_R5F
Functional Safety Optional(4)
C7xV-256 Deep Learning Accelerator
Vision Processing Accelerators
Video Encoder / Decoder
C7x MMA
VPAC
Up to 2 TOPS
Up to 1 TOPS
Up to 5MP @ 60 fps
VENC/VDEC
MJPEG
Yes
Yes
Motion JPEG Encoder
Device Management Subsystem
Hardware Security Module
Crypto Accelerators
WKUP_R5F
HSM
Single Core
Yes
Security
Yes
PROGRAM AND DATA STORAGE
On-Chip Shared Memory (RAM) in MAIN
Domain
OCSRAM
64KB
On-Chip Shared Memory (RAM) in MCU
Domain
MCU_MSRAM
512KB
LPDDR4 DDR Subsystem
General-Purpose Memory Controller
PERIPHERALS
DDRSS
GPMC
32-bit data with inline ECC up to 8GB
Up to 1GB with ECC
Display Subsystem(2)
DSS
1x DPI (Optional)
Modular Controller Area Network Interface
Full CAN-FD Support
MCAN
CAN-FD
GPIO
2
TBD
General-Purpose I/O
Up to 168
Inter-Integrated Circuit Interface
Multichannel Audio Serial Port
Multichannel Serial Peripheral Interface
I2C
6
MCASP
MCSPI
3
5
1x eMMC (8-bits)
Multi-Media Card/ Secure Digital Interface
MM/CSD
2x SD/SDIO (4-bits)
OSPI/QSPI/SPI(3) Flash Subsystem
Gigabit Ethernet Interface
OSPI
Yes
CPSW3G
TIMER
EPWM
ECAP
Yes
General-Purpose Timers
12 (4 in MCU Channel)
Enhanced Pulse-Width Modulator Module
Enhanced Capture Module
3
3
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AM62A31
SPRSP77 – MARCH 2023
Table 5-1. Device Comparison (continued)
AM62A7
AM62A3
REFERENCE
NAME
FEATURES
AM62A74 AM62A72
AM62A34
AM62A32
Enhanced Quadrature Encoder Pulse
Module
EQEP
3
Universal Asynchronous Receiver and
Transmitter
UART
9
CSI2-RX Controller with DPHY
USB2.0 Controller with PHY
CSI-RX
USB 2.0
1
2
(1) For more details about the CTRLMMR_WKUP_JTAG_DEVICE_ID register and DEVICE_ID bit field, see the device TRM.
(2) Display Subsystem is available when selecting an orderable part number that includes a feature code of M. Refer to Device Naming
Convention for definition of feature codes.
(3) A single instance of an OSPI flash host configured to operate with OSPI/QSPI/SPI devices.
(4) Functional Safety is available when selecting an orderable part number that includes a feature code of S to Z. Refer to Device Naming
Convention for definition of feature codes.
5.1 Related Products
Sitara™ processors Broad family of scalable processors based on Arm® Cortex®-A cores with flexible
accelerators, peripherals, connectivity and unified software support – perfect for sensors to servers. Sitara
processors have the reliability needed for use in industrial applications.
TBD
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SPRSP77 – MARCH 2023
6 Terminal Configuration and Functions
6.1 Pin Diagrams
Note
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt
is made to use "ball" only when referring to the physical package.
Figure 6-1 shows the ball locations for the 484-ball flip chip ball grid array (FCBGA) package to quickly locate
signal names and ball grid numbering. This figure is used in conjunction with Section 6.2.1 through Section 6.4
(Pin Attributes table and all Signal Descriptions tables, including the Pin Connectivity Requirements table).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CSI0
_RXCLKP
CSI0
_RXCLKN
RGMII1
_RD0
RGMII1
_TXC
RGMII2
_TXC
RGMII2
_RD3
RGMII2
_RD2
AB
AA
Y
VSS
VDDS_DDR
VSS
DDR0_DQ31
VSS
MMC0_DAT1 MMC0_CLK MMC0_DAT7
VSS
CSI0_RXP3
CSI0_RXN3
VSS
VSS
VSS
VSS
RGMII1_RX
_CTL
RGMII1
_RXC
RGMII1
_TD3
RGMII2
_TD2
RGMII2
_TD0
RGMII2
_RXC
RGMII2
_RD0
VOUT0
_PCLK
VDDS_DDR
VSS
DDR0_DQ24
VSS
DDR0_DQ29
VSS
DDR0_DQ28
VSS
DDR0_DQ30 MMC0_DAT0 MMC0_DAT3
VSS
USB0_DP
USB0_DM
USB1_DP
VSS
USB1_DM
VSS
CSI0_RXP2
CSI0_RXN2
CSI0_RXN1
CSI0_RXP0
VSS
CSI0_RXP1
VSS
DDR0_DQS3
_n
RGMII1
_TD2
RGMII1
_TD0
RGMII2
_TD1
RGMII2_TX
_CTL
RGMII2
_RD1
VOUT0
_DATA14
VOUT0
_DATA15
VSS
VSS
MMC0_CMD MMC0_DAT2 MMC0_DAT4
VSS
VSS
VSS
USB0
_RCALIB
RGMII1
_RD2
RGMII1_TX
_CTL
RGMII2
_TD3
RGMII2_RX
_CTL
VOUT0
_DATA13
VOUT0
_DATA12
VOUT0
_DATA11
VOUT0
_DATA10
W
V
DDR0_DQS3
DDR0_DM3
DDR0_DQ27
VSS
USB1_VBUS
VSS
MMC0_DAT5
VSS
MMC0_DAT6
CSI0_RXN0
MDIO0_MDC
VSS
CSI0
_RXRCALIB
MDIO0
_MDIO
RGMII1
_RD3
RGMII1
_RD1
RGMII1
_TD1
VOUT0
_VSYNC
VOUT0
_DATA9
VOUT0
_DATA8
VOUT0
_DATA7
VOUT0
_DATA6
VSS
DDR0_DQ25
VSS
DDR0_DQ26
VSS
VSS
USB0_VBUS
VDDSHV4
VDDSHV4
VSS
RSVD7
RSVD6
VSS
USB1
_RCALIB
VDDA_3P3
_USB
VOUT0
_DATA5
VOUT0
_DATA3
VOUT0
_DATA2
VOUT0
_DATA1
VOUT0
_DATA0
U
T
DDR0_DM2
VSS
DDR0_DQ23
VSS
DDR0_DQ18
VSS
VDDSHV2
VDDSHV2
VDDSHV2
VSS
VSS
CAP_VDDS2
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VOUT0_DE
VDDA_CORE VDDA_1P8 VDDA_CORE VDDA_1P8
_USB
VOUT0
_HSYNC
VOUT0
_DATA4
GPMC0
_AD14
GPMC0
_AD15
GPMC0
_AD12
VSS
DDR0_DQ22
VSS
DDR0_DQ17
VSS
DDR0_DQ16
VSS
VSS
VSS
_USB
_CSIRX0
_CSIRX0
GPMC0
_WAIT1
GPMC0
_WAIT0
GPMC0
_AD10
GPMC0
_AD13
GPMC0
_AD11
R
P
DDR0_DQS2
VSS
DDR0_DQ21
VSS
DDR0_DQ19
DDR0_CKE1
VSS
DDR0_BG1 CAP_VDDS4 VDD_CORE
VSS
VDDA_PLL1
VSS
VDD_CORE
GPMC0_AD9
DDR0_DQS2
_n
DDR0
_RESET0_n
VDDA
_TEMP0
DDR0_DQ20 DDR0_CKE0
DDR0_BG0
VSS
VDDS_DDR VDDR_CORE VDD_CORE
VSS
VDD_CORE
VSS
VDDR_CORE
VDD_CORE
VSS
VSS
GPMC0_AD5 GPMC0_AD6
VSS
GPMC0_AD7 GPMC0_AD8
DDR0_CS1
_n
DDR0_ACT
_n
N
M
L
VSS
DDR0_PAR
DDR0_A13
DDR0_A9
DDR0_A10
DDR0_A1
DDR0_A7
DDR0_ODT1
DDR0_A12
VSS
DDR0_WE_n VDDS_DDR
VSS
VDDA_PLL0
VSS
VSS
VDD_CORE
VSS
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV1
VSS
GPMC0_AD4 GPMC0_AD3 GPMC0_AD2 GPMC0_AD1 GPMC0_AD0 GPMC0_CLK
DDR0_CAS
_n
DDR0_RAS
VSS
VDDA_DDR
_PLL0
GPMC0
_BE1n
GPMC0
_CSn0
GPMC0
_CSn3
GPMC0
_CSn1
GPMC0
_CSn2
DDR0_CK0
VSS
DDR0_A3
VSS
VDDS_DDR
VDDR_CORE
VDD_CORE VDDA_PLL2 VDDR_CORE
CAP_VDDS3
VDDSHV1
VSS
_n
DDR0_CK0
_n
VDDS_DDR
_C
VDDA
_TEMP2
GPMC0_OEn
_REn
GPMC0
_ADVn_ALE
GPMC0
_BE0n_CLE
DDR0_A11
DDR0_A5
DDR0_A0
DDR0_A8
VDDS_DDR
VDD_CORE
VDD_CORE
VSS
VDD_CORE
VSS
VSS
OSPI0_DQS
OSPI0_D4
OSPI0_D0
OSPI0_CLK
OSPI0
_CSn2
OSPI0
_LBCLKO
K
VSS
DDR0_A4
VSS
DDR0_A6
DDR0_BA0
VSS
VDDS_DDR
VSS
VDDA_PLL4
VDDA_MCU
VSS
VDDR_CORE VDDA_PLL3 VDD_CORE
CAP_VDDS1 GPMC0_WPn GPMC0_DIR GPMC0_WEn
DDR0_CS0
_n
J
VSS
DDR0_A2
VDDS_DDR VDDS_OSC0 VDD_CORE
VDD_CORE
VSS
VMON_VSYS
VSS
VDD_CORE VDDR_CORE VDD_CORE CAP_VDDS6
VSS
OSPI0_D1
OSPI0_D3
OSPI0_D2
OSPI0_D5
OSPI0_D6
OSPI0_D7
DDR0
_ALERT_n
VDDSHV
_CANUART
VDD
_CANUART
VDDSHV
_MCU
OSPI0
_CSn0
H
G
F
DDR0_BA1
VSS
DDR0_ODT0 DDR0_CAL0
VSS
VDDSHV0
CAP_VDDS0
VSS
VSS
VDDSHV5
CAP_VDDS5
TRSTn
VDDSHV6
VDDSHV5
VSS
VDDSHV6
VSS
MMC2_CLK
CAP_VDDS
_CANUART
CAP_VDDS
_MCU
VDDSHV
_MCU
VDDA
_TEMP1
OSPI0
_CSn1
OSPI0
_CSn3
DDR0_DQS1 DDR0_DQ11
VSS
DDR0_DQ13
VSS
DDR0_DQ12
RSVD3
RSVD5
VPP
VSS
VDDSHV0
VSS
MMC2_DAT3 MMC2_CMD
DDR0_DQS1
MCU_UART0 VMON_3P3
_TXD
VMON_1P8
_SOC
UART0
_CTSn
RESETSTA
Tz
VSS
_n
DDR0_DM1
VSS
DDR0_DQ9
RSVD4
EMU1
VSS
EXTINTn
I2C1_SDA
I2C0_SCL
I2C1_SCL
MCAN0_TX
SPI0_CLK
PORz_OUT
MMC1_SDCD
MMC1_SDWP
MCAN0_RX
MMC2_DAT2 MMC2_DAT1 MMC2_SDCD
MMC2_DAT0 MMC2_SDWP MMC1_CLK
_SOC
WKUP
_UART0
_TXD
MCU_MCAN0
_RX
MCU_SPI0
_CS0
MCU_I2C0
_SCL
WKUP_I2C0
_SDA
RESET
_REQz
E
VSS
DDR0_DQ8
VSS
DDR0_DQ14
VSS
DDR0_DQ10
RSVD1
RSVD2
UART0_RXD
SPI0_D1
I2C0_SDA
SPI0_CS0
SPI0_CS1
MCU_MCAN1 MCU_UART0
MCU_I2C0
_SDA
MCU_UART0
_RTSn
PMIC_LPM
_EN0
WKUP_I2C0 MCU_RESETS
_SCL
USB1
_DRVVBUS
D
C
B
DDR0_DQS0
VSS
DDR0_DQ15
DDR0_DQ5
VSS
VSS
DDR0_DQ3
DDR0_DQ4
VSS
VSS
UART0_TXD
VSS
MMC1_DAT1 MMC1_DAT3
MMC1_CMD MMC1_DAT2
_TX
_RXD
TATz
WKUP
_UART0
_RTSn
WKUP
_UART0
_RXD
WKUP
_UART0
_CTSn
DDR0_DQS0
_n
MCU_MCAN0
_TX
MCU_SPI0
_CS1
MCU
_RESETz
UART0
_RTSn
MCASP0
_AXR3
USB0
_DRVVBUS
DDR0_DM0
DDR0_DQ6
VDDS_DDR
VSS
RSVD0
EMU0
TDO
MCU
_ERRORn
MCU_MCAN1
_RX
WKUP
_CLKOUT0
MCU_UART0
_CTSn
MCU_SPI0
_D1
MCU_SPI0
_CLK
EXT
_REFCLK1
MCASP0
_AXR1
MCASP0
_AXR2
MCASP0
_AXR0
MCASP0
MMC1_DAT0
_AFSR
VDDS_DDR
DDR0_DQ1
DDR0_DQ2
VSS
TMS
TCK
SPI0_D0
WKUP
_LFOSC0
_XI
WKUP
_LFOSC0
_XO
MCU_OSC0
_XO
MCU_OSC0
_XI
MCU_SPI0
_D0
MCASP0
_ACLKX
MCASP0
_AFSX
MCASP0
VSS
A
VSS
DDR0_DQ7
VSS
DDR0_DQ0
VSS
MCU_PORz
VSS
VSS
TDI
VSS
_ACLKR
Not to scale
Figure 6-1. AMB FCBGA-N484 Pin Diagram (Bottom View)
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6.2 Pin Attributes
The following list describes the contents of each column in the Table 6-1, Pin Attributes (AMB Package) table:
1. BALL NUMBER: Ball numbers assigned to each terminal of the Ball Grid Array package.
ꢀ
2. BALL NAME: Ball name assigned to each terminal of the Ball Grid Array package (this name is typically
taken from the primary MUXMODE 0 signal function).
ꢀ
3. SIGNAL NAME: Signal name(s) of all dedicated and pin multiplexed signal functions associated with a ball.
Note
Many device pins support multiple signal functions. Some signal functions are selected via a
single layer of multiplexers associated with pins. Other signal functions are selected via two or
more layers of multiplexers, where one layer is associated with the pins and other layers are
associated with peripheral logic functions.
The Table 6-1, Pin Attributes (AMB Package) table only defines signal multiplexing at the pins.
For more information, related to signal multiplexing at the pins, see Pad Configuration Registers
section in Device Configuration chapter of the device TRM. Refer to the respective peripheral
chapter in the device TRM for information associated with peripheral signal multiplexing.
4. MUX MODE: The MUXMODE value associated with each pin multiplexed signal function:
a. MUXMODE 0 is the primary pin multiplexed signal function. However, the primary pin multiplexed signal
function is not necessarily the default pin multiplexed signal function.
Note
The value found in the MUX MODE AFTER RESET column defines the default pin
multiplexed signal function selected when MCU_PORz is deasserted.
a. MUXMODE values 1 through 15 are possible for pin multiplexed signal functions. However, not all
MUXMODE values have been implemented. The only valid MUXMODE values are those defined as pin
multiplexed signal functions within the Pin Attributes table. Only valid values of MUXMODE should be
used.
b. Bootstrap defines SOC configuration pins, where the logic state applied to each pin is latched on the
rising edge of PORz_OUT. These input signal functions are fixed to their respective pins and are not
programable via MUXMODE.
c. An empty box means Not Applicable.
Note
The following configurations of MUXMODE must be avoided for proper device operation.
•
Configuring multiple pins operating as inputs to the same pin multiplexed signal function is not
supported as it can yield unexpected results.
•
Configuring a pin to an undefined pin multiplexing mode will cause the pin behavior to be
undefined.
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5. TYPE: Signal type and direction:
•
•
•
•
•
•
•
•
•
•
•
I = Input
O = Output
OD = Output, with open-drain output function
IO = Input, Output, or simultaneously Input and Output
IOD = Input, Output, or simultaneously Input and Output, with open-drain output function
IOZ = Input, Output, or simultaneously Input and Output, with three-state output function
OZ = Output with three-state output function
A = Analog
PWR = Power
GND = Ground
CAP = LDO Capacitor.
6. DSIS: The deselected input state (DSIS) indicates the state driven to the subsystem input (logic "0", logic
"1", or "pad" level) when the pin multiplexed signal function is not selected by MUXMODE.
•
•
•
•
0: Logic 0 driven to the subsystem input.
1: Logic 1 driven to the subsystem input.
pad: Logic state of the pad is driven to the subsystem input.
An empty box means Not Applicable.
7. BALL STATE DURING RESET RX/TX/PULL: State of the terminal while MCU_PORz is asserted, where RX
defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state of
internal pull resistors:
•
•
•
RX (Input buffer)
– Off: The input buffer is disabled.
– On: The input buffer is enabled.
TX (Output buffer)
– Off: The output buffer is disabled.
– Low: The output buffer is enabled and drives VOL
PULL (Internal pull resistors)
.
– Off: Internal pull resistors are turned off.
– Up: Internal pull-up resistor is turned on.
– Down: Internal pull-down resistor is turned on.
– NA: Not Applicable.
•
An empty box means Not Applicable.
8. BALL STATE AFTER RESET RX/TX/PULL: State of the terminal after MCU_PORz is deasserted, where
RX defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state
of internal pull resistors:
•
•
•
RX (Input buffer)
– Off: The input buffer is disabled.
– On: The input buffer is enabled.
TX (Output buffer)
– Off: The output buffer is disabled.
– SS: The subsystem selected with MUXMODE determines the output buffer state.
PULL (Internal pull resistors)
– Off: Internal pull resistors are turned off.
– Up: Internal pull-up resistor is turned on.
– Down: Internal pull-down resistor is turned on.
– NA: Not Applicable.
•
An empty box means Not Applicable.
9. MUX MODE AFTER RESET: The value found in this column defines the default pin multiplexed signal
function after MCU_PORz is deasserted.
An empty box means Not Applicable.
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10. I/O VOLTAGE VALUE: This column describes I/O operating voltage options of the respective power supply,
when applicable.
An empty box means Not Applicable.
For more information, see valid operating voltage range(s) defined for each power supply in Section 7.4,
Recommended Operating Conditions.
11. POWER: The power supply of the associated I/O, when applicable.
An empty box means Not Applicable.
12. HYS: Indicates if the input buffer associated with this I/O has hysteresis:
•
•
•
Yes: With hysteresis
No: Without hysteresis
An empty box means Not Applicable.
For more information, see the hysteresis values in Section 7.6, Electrical Characteristics.
13. BUFFER TYPE: This column defines the buffer type associated with a terminal. This information can be
used to determine which Electrical Characteristics table is applicable.
An empty box means Not Applicable.
For electrical characteristics, refer to the appropriate buffer type table in Section 7.6, Electrical
Characteristics.
14. PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and
pulldown resistors can be enabled or disabled via software.
•
•
•
•
PU: Internal pull-up
PD: Internal pull-down
PU/PD: Internal pull-up and pull-down
An empty box means No internal pull.
15. PADCONFIG Register:Name of the IO pad configuration register associated with Ball.
ꢀ
16. PADCONFIG Address:Physical address of the IO pad configuration register associated with Ball.
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Table 6-1. Pin Attributes (AMB Package)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
G13
K16
CAP_VDDS0
CAP_VDDS1
CAP_VDDS2
CAP_VDDS3
CAP_VDDS4
CAP_VDDS5
CAP_VDDS6
CAP_VDDS_CANUART
CAP_VDDS_MCU
CSI0_RXCLKN
CSI0_RXCLKP
CSI0_RXRCALIB
CSI0_RXN0
CAP_VDDS0
CAP
CAP_VDDS1
CAP_VDDS2
CAP_VDDS3
CAP_VDDS4
CAP_VDDS5
CAP_VDDS6
CAP_VDDS_CANUART
CAP_VDDS_MCU
CSI0_RXCLKN
CSI0_RXCLKP
CSI0_RXRCALIB
CSI0_RXN0
CAP
T14
CAP
M16
R8
CAP
CAP
G15
J16
CAP
CAP
G8
CAP
G10
AB14
AB13
V10
CAP
I
I
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
A
I
W12
Y13
CSI0_RXN1
CSI0_RXN1
I
AA13
AB11
W13
Y14
CSI0_RXN2
CSI0_RXN2
I
CSI0_RXN3
CSI0_RXN3
I
CSI0_RXP0
CSI0_RXP0
I
CSI0_RXP1
CSI0_RXP1
I
AA12
AB10
CSI0_RXP2
CSI0_RXP2
I
CSI0_RXP3
CSI0_RXP3
I
VDDS_DDR,
VDDS_DDR_C
N5
H7
M5
N2
M6
N6
J5
DDR0_ACT_n
DDR0_ALERT_n
DDR0_CAS_n
DDR0_PAR
DDR0_RAS_n
DDR0_WE_n
DDR0_A0
DDR0_ACT_n
DDR0_ALERT_n
DDR0_CAS_n
DDR0_PAR
DDR0_RAS_n
DDR0_WE_n
DDR0_A0
O
IO
O
O
O
O
O
O
O
O
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
J2
DDR0_A1
DDR0_A1
VDDS_DDR,
VDDS_DDR_C
J4
DDR0_A2
DDR0_A2
VDDS_DDR,
VDDS_DDR_C
L4
DDR0_A3
DDR0_A3
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Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
VDDS_DDR,
VDDS_DDR_C
J1
K5
K3
H2
L6
DDR0_A4
DDR0_A4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
A
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
VDDS_DDR,
VDDS_DDR_C
DDR0_A5
DDR0_A5
VDDS_DDR,
VDDS_DDR_C
DDR0_A6
DDR0_A6
VDDS_DDR,
VDDS_DDR_C
DDR0_A7
DDR0_A7
VDDS_DDR,
VDDS_DDR_C
DDR0_A8
DDR0_A8
VDDS_DDR,
VDDS_DDR_C
L2
DDR0_A9
DDR0_A9
VDDS_DDR,
VDDS_DDR_C
K2
L5
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
DDR0_CAL0
DDR0_CK0
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n
DDR0_CS1_n
DDR0_DM0
DDR0_DM1
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
DDR0_CAL0
DDR0_CK0
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n
DDR0_CS1_n
DDR0_DM0
DDR0_DM1
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
M3
M2
K6
H3
P4
R7
H6
M1
L1
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
O
O
O
O
O
O
IO
IO
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
P3
P5
J6
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
N4
C2
F3
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
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Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
VDDS_DDR,
VDDS_DDR_C
U1
W3
A5
B4
B6
D5
C5
C3
B2
A3
E2
F5
E6
G2
G6
G4
E4
D3
T6
T4
U5
R5
P2
DDR0_DM2
DDR0_DM3
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DM2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
VDDS_DDR,
VDDS_DDR_C
DDR0_DM3
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
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SPRSP77 – MARCH 2023
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Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
VDDS_DDR,
VDDS_DDR_C
R3
T2
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
DDR0_DQS0
DDR0_DQS0_n
DDR0_DQS1
DDR0_DQS1_n
DDR0_DQS2
DDR0_DQS2_n
DDR0_DQS3
DDR0_DQS3_n
DDR0_ODT0
DDR0_ODT1
DDR0_RESET0_n
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
DDR0_DQS0
DDR0_DQS0_n
DDR0_DQS1
DDR0_DQS1_n
DDR0_DQS2
DDR0_DQS2_n
DDR0_DQS3
DDR0_DQS3_n
DDR0_ODT0
DDR0_ODT1
DDR0_RESET0_n
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
U3
Y2
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
V2
VDDS_DDR,
VDDS_DDR_C
V4
VDDS_DDR,
VDDS_DDR_C
W5
Y4
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
AA3
AA5
AB4
D1
C1
G1
F1
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
R1
P1
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
W1
Y1
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
H5
N3
P6
VDDS_DDR,
VDDS_DDR_C
O
VDDS_DDR,
VDDS_DDR_C
O
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SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
EMU0
PADCONFIG:
MCU_PADCONFIG30
0x04084078
C13
E10
F17
EMU0
EMU1
0
0
IO
IO
0
0
On / Off / Up
On / Off / Up
Off / Off / NA
On / Off / Up
On / Off / Up
Off / Off / NA
0
0
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_MCU
VDDSHV_MCU
VDDSHV0
Yes
Yes
Yes
LVCMOS
LVCMOS
I2C OD FS
PU/PD
PU/PD
EMU1
PADCONFIG:
MCU_PADCONFIG31
0x0408407C
EXTINTn
EXTINTn
0
7
I
1
pad
0
PADCONFIG:
PADCONFIG125
0x000F41F4
GPIO1_31
IOD
EXT_REFCLK1
SYNC1_OUT
0
1
2
3
4
5
6
7
8
0
2
6
7
0
2
3
6
7
0
3
6
7
8
0
2
6
7
I
O
SPI2_CS3
IO
O
1
0
EXT_REFCLK1
SYSCLKOUT0
TIMER_IO4
PADCONFIG:
PADCONFIG124
0x000F41F0
B16
IO
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
CLKOUT0
CP_GEMAC_CPTS0_RFT_CLK
GPIO1_30
I
0
pad
0
IO
IO
O
ECAP0_IN_APWM_OUT
GPMC0_ADVn_ALE
MCASP1_AXR2
TRC_DATA7
GPMC0_ADVn_ALE
IO
O
0
pad
0
PADCONFIG:
PADCONFIG33
0x000F4084
L18
N22
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
VDDSHV3
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
GPIO0_32
IO
O
GPMC0_CLK
GPMC0_CLK
MCASP1_AXR3
GPMC0_FCLK_MUX
TRC_DATA6
IO
O
PADCONFIG:
PADCONFIG31
0x000F407C
Off / Off / Off
Off / Off / Off
O
GPIO0_31
IO
O
pad
0
GPMC0_DIR
GPMC0_DIR
MCASP2_AXR13
TRC_DATA14
GPIO0_40
IO
O
PADCONFIG:
PADCONFIG41
0x000F40A4
K18
L17
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
VDDSHV3
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
IO
IO
O
pad
0
EQEP2_S
GPMC0_OEn_REn
MCASP1_AXR1
TRC_DATA8
GPMC0_OEn_REn
IO
O
0
PADCONFIG:
PADCONFIG34
0x000F4088
Off / Off / Off
Off / Off / Off
GPIO0_33
IO
pad
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SPRSP77 – MARCH 2023
www.ti.com
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
GPMC0_WEn
MCASP1_AXR0
TRC_DATA9
GPIO0_34
0
O
IO
O
GPMC0_WEn
2
0
pad
0
PADCONFIG:
PADCONFIG35
0x000F408C
K19
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
VDDSHV3
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
6
7
IO
O
GPMC0_WPn
AUDIO_EXT_REFCLK1
GPMC0_A22
UART6_TXD
TRC_DATA13
GPIO0_39
0
1
IO
OZ
O
GPMC0_WPn
2
PADCONFIG:
PADCONFIG40
0x000F40A0
K17
Off / Off / Off
Off / Off / Off
1.8 V/3.3 V
VDDSHV3
3
6
O
7
IO
IO
IO
O
pad
0
GPMC0_AD0
MCASP2_AXR4
TRC_CLK
0
GPMC0_AD0
3
0
PADCONFIG:
PADCONFIG15
0x000F403C
N21
N20
N19
N18
N17
6
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
7
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV3
Yes
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
GPIO0_15
7
IO
I
pad
BOOTMODE00
GPMC0_AD1
MCASP2_AXR5
TRC_CTL
Bootstrap
0
IO
IO
O
0
0
GPMC0_AD1
3
PADCONFIG:
PADCONFIG16
0x000F4040
6
GPIO0_16
7
IO
I
pad
BOOTMODE01
GPMC0_AD2
MCASP2_AXR6
TRC_DATA0
GPIO0_17
Bootstrap
0
IO
IO
O
0
0
GPMC0_AD2
3
PADCONFIG:
PADCONFIG17
0x000F4044
6
7
IO
I
pad
BOOTMODE02
GPMC0_AD3
MCASP2_AXR7
TRC_DATA1
GPIO0_18
Bootstrap
0
IO
IO
O
0
0
GPMC0_AD3
3
PADCONFIG:
PADCONFIG18
0x000F4048
6
7
IO
I
pad
BOOTMODE03
GPMC0_AD4
MCASP2_AXR8
TRC_DATA2
GPIO0_19
Bootstrap
0
IO
IO
O
0
0
GPMC0_AD4
3
PADCONFIG:
PADCONFIG19
0x000F404C
6
7
IO
I
pad
BOOTMODE04
Bootstrap
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www.ti.com
SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
GPMC0_AD5
0
IO
IO
O
IO
I
0
0
GPMC0_AD5
MCASP2_AXR9
TRC_DATA3
3
PADCONFIG:
PADCONFIG20
0x000F4050
P18
P19
P21
6
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
GPIO0_20
7
pad
BOOTMODE05
GPMC0_AD6
MCASP2_AXR10
TRC_DATA4
Bootstrap
0
IO
IO
O
IO
I
0
0
GPMC0_AD6
3
PADCONFIG:
PADCONFIG21
0x000F4054
6
VDDSHV3
VDDSHV3
GPIO0_21
7
pad
BOOTMODE06
GPMC0_AD7
MCASP2_AXR11
TRC_DATA5
Bootstrap
0
IO
IO
O
IO
I
0
0
GPMC0_AD7
3
PADCONFIG:
PADCONFIG22
0x000F4058
6
GPIO0_22
7
pad
0
BOOTMODE07
GPMC0_AD8
VOUT0_DATA16
UART2_RXD
MCASP2_AXR0
GPIO0_23
Bootstrap
0
IO
O
I
1
GPMC0_AD8
2
1
0
PADCONFIG:
PADCONFIG23
0x000F405C
P22
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
3
IO
IO
I
7
pad
BOOTMODE08
GPMC0_AD9
VOUT0_DATA17
UART2_TXD
MCASP2_AXR1
GPIO0_24
Bootstrap
0
IO
O
O
IO
IO
I
0
1
GPMC0_AD9
2
PADCONFIG:
PADCONFIG24
0x000F4060
R19
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
3
0
7
pad
BOOTMODE09
GPMC0_AD10
VOUT0_DATA18
UART3_RXD
MCASP2_AXR2
GPIO0_25
Bootstrap
0
IO
O
I
0
1
GPMC0_AD10
2
1
0
PADCONFIG:
PADCONFIG25
0x000F4064
R20
3
IO
IO
O
I
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
7
8
pad
OBSCLK0
BOOTMODE10
Bootstrap
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SPRSP77 – MARCH 2023
www.ti.com
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
GPMC0_AD11
VOUT0_DATA19
UART3_TXD
0
IO
O
O
IO
O
IO
I
0
1
GPMC0_AD11
2
PADCONFIG:
PADCONFIG26
0x000F4068
R22
MCASP2_AXR3
TRC_DATA23
GPIO0_26
3
0
pad
0
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
6
7
BOOTMODE11
GPMC0_AD12
VOUT0_DATA20
UART4_RXD
MCASP2_AFSX
TRC_DATA22
GPIO0_27
Bootstrap
0
IO
O
I
1
GPMC0_AD12
2
1
0
PADCONFIG:
PADCONFIG27
0x000F406C
T22
3
IO
O
IO
I
VDDSHV3
6
7
pad
0
BOOTMODE12
GPMC0_AD13
VOUT0_DATA21
UART4_TXD
Bootstrap
0
IO
O
O
IO
O
IO
I
1
GPMC0_AD13
2
PADCONFIG:
PADCONFIG28
0x000F4070
R21
MCASP2_ACLKX
TRC_DATA21
GPIO0_28
3
0
pad
0
VDDSHV3
6
7
BOOTMODE13
GPMC0_AD14
VOUT0_DATA22
UART5_RXD
MCASP2_AFSR
TRC_DATA20
GPIO0_29
Bootstrap
0
IO
O
I
1
2
1
0
GPMC0_AD14
3
IO
O
IO
I
PADCONFIG:
PADCONFIG29
0x000F4074
T20
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
6
7
pad
1
UART2_CTSn
BOOTMODE14
GPMC0_AD15
VOUT0_DATA23
UART5_TXD
8
Bootstrap
I
0
IO
O
O
IO
O
IO
O
I
0
1
2
GPMC0_AD15
MCASP2_ACLKR
TRC_DATA19
GPIO0_30
3
0
PADCONFIG:
PADCONFIG30
0x000F4078
T21
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
6
7
8
pad
UART2_RTSn
BOOTMODE15
Bootstrap
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www.ti.com
SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
GPMC0_BE0n_CLE
0
2
6
7
0
3
6
7
0
3
6
7
0
3
6
7
0
1
2
3
6
7
8
0
1
2
3
4
6
7
8
0
2
6
7
O
IO
O
GPMC0_BE0n_CLE
MCASP1_ACLKX
TRC_DATA10
GPIO0_35
0
pad
0
PADCONFIG:
PADCONFIG36
0x000F4090
L19
M18
M19
M21
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
IO
O
GPMC0_BE1n
MCASP2_AXR12
TRC_DATA11
GPIO0_36
GPMC0_BE1n
IO
O
PADCONFIG:
PADCONFIG37
0x000F4094
VDDSHV3
VDDSHV3
VDDSHV3
IO
O
pad
0
GPMC0_CSn0
MCASP2_AXR14
TRC_DATA15
GPIO0_41
GPMC0_CSn0
IO
O
PADCONFIG:
PADCONFIG42
0x000F40A8
IO
O
pad
0
GPMC0_CSn1
MCASP2_AXR15
TRC_DATA16
GPIO0_42
GPMC0_CSn1
IO
O
PADCONFIG:
PADCONFIG43
0x000F40AC
IO
O
pad
GPMC0_CSn2
I2C2_SCL
IOD
IO
I
1
0
1
GPMC0_CSn2
MCASP1_AXR4
UART4_RXD
TRC_DATA17
GPIO0_43
PADCONFIG:
PADCONFIG44
0x000F40B0
M22
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
O
IO
IO
O
pad
0
MCASP1_AFSR
GPMC0_CSn3
I2C2_SDA
IOD
OZ
O
1
0
GPMC0_A20
UART4_TXD
MCASP1_AXR5
TRC_DATA18
GPIO0_44
GPMC0_CSn3
PADCONFIG:
PADCONFIG45
0x000F40B4
M20
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
IO
O
IO
IO
I
pad
0
MCASP1_ACLKR
GPMC0_WAIT0
MCASP1_AFSX
TRC_DATA12
GPIO0_37
1
GPMC0_WAIT0
IO
O
0
PADCONFIG:
PADCONFIG38
0x000F4098
R18
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
IO
pad
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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
SPRSP77 – MARCH 2023
www.ti.com
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
GPMC0_WAIT1
VOUT0_EXTPCLKIN
GPMC0_A21
UART6_RXD
GPIO0_38
0
1
2
3
7
8
0
2
3
4
5
6
7
8
9
0
2
3
4
5
6
7
8
0
1
2
3
4
7
8
9
I
I
1
0
GPMC0_WAIT1
OZ
I
PADCONFIG:
PADCONFIG39
0x000F409C
R17
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
1
pad
0
IO
IO
IOD
O
EQEP2_I
I2C0_SCL
1
SYNC0_OUT
OBSCLK1
O
I2C0_SCL
UART1_DCDn
EQEP2_A
I
1
0
PADCONFIG:
PADCONFIG120
0x000F41E0
D17
I
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
EHRPWM_SOCA
GPIO1_26
O
IO
IO
IO
IOD
IO
IO
I
pad
0
ECAP1_IN_APWM_OUT
SPI2_CS0
1
I2C0_SDA
1
SPI2_CS2
1
TIMER_IO5
0
I2C0_SDA
UART1_DSRn
EQEP2_B
1
PADCONFIG:
PADCONFIG121
0x000F41E4
E16
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
I
0
EHRPWM_SOCB
GPIO1_27
O
IO
IO
IOD
I
pad
0
ECAP2_IN_APWM_OUT
I2C1_SCL
1
UART1_RXD
TIMER_IO0
1
IO
IO
I
0
I2C1_SCL
SPI2_CS1
1
PADCONFIG:
PADCONFIG122
0x000F41E8
C17
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
EHRPWM0_SYNCI
GPIO1_28
0
IO
IO
I
pad
0
EHRPWM2_A
MMC2_SDCD
0
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SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
I2C1_SDA
0
1
2
3
4
7
8
9
0
1
2
3
4
5
7
8
9
0
1
2
3
4
5
7
8
9
0
1
2
6
7
8
0
1
2
7
8
IOD
O
1
UART1_TXD
TIMER_IO1
IO
IO
O
0
0
I2C1_SDA
SPI2_CLK
PADCONFIG:
PADCONFIG123
0x000F41EC
E17
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
EHRPWM0_SYNCO
GPIO1_29
IO
IO
I
pad
0
EHRPWM2_B
MMC2_SDWP
MCAN0_RX
0
I
1
UART5_TXD
TIMER_IO3
O
IO
O
0
MCAN0_RX
SYNC3_OUT
UART1_RIn
PADCONFIG:
PADCONFIG119
0x000F41DC
C18
I
1
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
EQEP2_S
IO
IO
IO
I
GPIO1_25
pad
0
MCASP2_AXR1
EHRPWM_TZn_IN4
MCAN0_TX
0
O
UART5_RXD
TIMER_IO2
I
1
0
IO
O
MCAN0_TX
SYNC2_OUT
UART1_DTRn
EQEP2_I
PADCONFIG:
PADCONFIG118
0x000F41D8
B17
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
IO
IO
IO
I
0
pad
0
GPIO1_24
MCASP2_AXR0
EHRPWM_TZn_IN3
MCASP0_ACLKR
SPI2_CLK
0
IO
IO
O
0
0
MCASP0_ACLKR
UART1_TXD
EHRPWM0_B
GPIO1_14
PADCONFIG:
PADCONFIG108
0x000F41B0
A21
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
Yes
LVCMOS
PU/PD
IO
IO
IO
IO
IO
IO
IO
I
0
pad
0
EQEP1_I
MCASP0_ACLKX
SPI2_CS1
0
MCASP0_ACLKX
1
PADCONFIG:
PADCONFIG105
0x000F41A4
A19
ECAP2_IN_APWM_OUT
GPIO1_11
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
LVCMOS
PU/PD
pad
0
EQEP1_A
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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
SPRSP77 – MARCH 2023
www.ti.com
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
MCASP0_AFSR
SPI2_CS0
0
1
2
6
7
8
0
1
2
7
8
0
2
6
7
8
0
1
2
6
7
8
0
1
2
3
5
7
8
0
1
2
3
5
7
8
IO
IO
I
0
1
MCASP0_AFSR
UART1_RXD
EHRPWM0_A
GPIO1_13
1
PADCONFIG:
PADCONFIG107
0x000F41AC
B21
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
IO
IO
IO
IO
IO
IO
IO
I
0
pad
0
EQEP1_S
MCASP0_AFSX
SPI2_CS3
0
MCASP0_AFSX
1
PADCONFIG:
PADCONFIG106
0x000F41A8
A20
B20
AUDIO_EXT_REFCLK1
GPIO1_12
0
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
VDDSHV0
VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
pad
0
EQEP1_B
MCASP0_AXR0
AUDIO_EXT_REFCLK0
EHRPWM1_B
GPIO1_10
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
0
MCASP0_AXR0
0
PADCONFIG:
PADCONFIG104
0x000F41A0
0
Off / Off / Off
Off / Off / Off
1.8 V/3.3 V
pad
0
EQEP0_I
MCASP0_AXR1
SPI2_CS2
0
1
MCASP0_AXR1
ECAP1_IN_APWM_OUT
EHRPWM1_A
GPIO1_9
0
PADCONFIG:
PADCONFIG103
0x000F419C
B18
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
0
pad
0
EQEP0_S
MCASP0_AXR2
SPI2_D1
0
0
MCASP0_AXR2
UART1_RTSn
UART6_TXD
ECAP2_IN_APWM_OUT
GPIO1_8
PADCONFIG:
PADCONFIG102
0x000F4198
B19
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
IO
IO
I
0
pad
0
EQEP0_B
MCASP0_AXR3
SPI2_D0
IO
IO
I
0
0
MCASP0_AXR3
UART1_CTSn
UART6_RXD
ECAP1_IN_APWM_OUT
GPIO1_7
1
PADCONFIG:
PADCONFIG101
0x000F4194
C19
I
1
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
IO
IO
I
0
pad
0
EQEP0_A
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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
www.ti.com
SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
MCU_ERRORn
PADCONFIG:
MCU_PADCONFIG24
0x04084060
B8
E12
D9
MCU_ERRORn
0
IO
Off / Off / Down
Off / Off / NA
Off / Off / NA
On / SS / Down
On / SS / NA
On / SS / NA
0
7
7
1.8 V
VDDS_OSC0
VDDSHV_MCU
VDDSHV_MCU
Yes
Yes
Yes
LVCMOS
I2C OD FS
I2C OD FS
PU/PD
MCU_I2C0_SCL
MCU_I2C0_SCL
MCU_GPIO0_17
MCU_I2C0_SDA
MCU_GPIO0_18
0
7
0
7
IOD
IOD
IOD
IOD
1
PADCONFIG:
MCU_PADCONFIG17
0x04084044
1.8 V/3.3 V
1.8 V/3.3 V
pad
1
MCU_I2C0_SDA
PADCONFIG:
MCU_PADCONFIG18
0x04084048
pad
MCU_MCAN0_RX
MCU_TIMER_IO0
MCU_SPI1_CS3
MCU_GPIO0_14
MCU_MCAN0_TX
WKUP_TIMER_IO0
MCU_SPI0_CS3
MCU_GPIO0_13
MCU_MCAN1_RX
MCU_TIMER_IO3
MCU_SPI0_CS2
MCU_SPI1_CS2
MCU_SPI1_CLK
MCU_GPIO0_16
MCU_MCAN1_TX
MCU_TIMER_IO2
MCU_SPI1_CS1
MCU_EXT_REFCLK0
MCU_GPIO0_15
MCU_OSC0_XI
0
1
2
7
0
1
2
7
0
1
2
3
4
7
0
1
3
4
7
I
1
0
MCU_MCAN0_RX
IO
IO
IO
O
PADCONFIG:
MCU_PADCONFIG14
0x04084038
E8
C7
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_CANUART
VDDSHV_CANUART
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
1
pad
MCU_MCAN0_TX
IO
IO
IO
I
0
1
PADCONFIG:
MCU_PADCONFIG13
0x04084034
pad
1
IO
IO
IO
IO
IO
O
0
MCU_MCAN1_RX
1
PADCONFIG:
MCU_PADCONFIG16
0x04084040
B9
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_CANUART
Yes
Yes
LVCMOS
PU/PD
1
0
pad
MCU_MCAN1_TX
IO
IO
I
0
1
PADCONFIG:
MCU_PADCONFIG15
0x0408403C
D7
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_CANUART
LVCMOS
PU/PD
0
IO
I
pad
A12
A11
MCU_OSC0_XI
MCU_OSC0_XO
MCU_PORz
1.8 V
1.8 V
VDDS_OSC0
VDDS_OSC0
HFOSC
HFOSC
MCU_OSC0_XO
O
PADCONFIG:
MCU_PADCONFIG22
0x04084058
A7
MCU_PORz
0
I
0
0
1.8 V
VDDS_OSC0
Yes
Yes
FS RESET
LVCMOS
MCU_RESETSTATz
MCU_RESETSTATz
MCU_GPIO0_21
0
7
O
PADCONFIG:
MCU_PADCONFIG23
0x0408405C
D14
Off / Low / Off
Off / SS / Off
1.8 V/3.3 V
VDDSHV_MCU
PU/PD
IO
pad
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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
SPRSP77 – MARCH 2023
www.ti.com
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
MCU_RESETz
PADCONFIG:
MCU_PADCONFIG21
0x04084054
C12
MCU_RESETz
0
I
On / Off / Up
Off / Off / Off
Off / Off / Off
On / Off / Up
Off / Off / Off
Off / Off / Off
0
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_MCU
VDDSHV_MCU
VDDSHV_MCU
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
MCU_SPI0_CLK
MCU_SPI0_CLK
MCU_GPIO0_2
0
7
IO
IO
0
PADCONFIG:
MCU_PADCONFIG2
0x04084008
B13
E11
pad
MCU_SPI0_CS0
MCU_SPI0_CS0
0
4
IO
IO
1
0
PADCONFIG:
MCU_PADCONFIG0
0x04084000
WKUP_TIMER_IO1
MCU_GPIO0_0
7
IO
pad
1
MCU_SPI0_CS1
MCU_OBSCLK0
MCU_SYSCLKOUT0
MCU_EXT_REFCLK0
MCU_TIMER_IO1
MCU_GPIO0_1
0
1
2
3
4
7
0
IO
O
MCU_SPI0_CS1
O
PADCONFIG:
MCU_PADCONFIG1
0x04084004
C11
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
I
0
0
IO
IO
IO
pad
0
MCU_SPI0_D0
MCU_SPI0_D0
PADCONFIG:
MCU_PADCONFIG3
0x0408400C
A15
B12
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_MCU
VDDSHV_MCU
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
MCU_GPIO0_3
MCU_SPI0_D1
MCU_GPIO0_4
7
0
7
IO
IO
IO
pad
0
MCU_SPI0_D1
PADCONFIG:
MCU_PADCONFIG4
0x04084010
pad
MCU_UART0_CTSn
MCU_TIMER_IO0
MCU_SPI1_D0
0
1
3
7
0
1
3
7
0
I
1
0
MCU_UART0_CTSn
IO
IO
IO
O
PADCONFIG:
MCU_PADCONFIG7
0x0408401C
B11
D10
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_CANUART
VDDSHV_CANUART
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
0
MCU_GPIO0_7
pad
MCU_UART0_RTSn
MCU_TIMER_IO1
MCU_SPI1_D1
MCU_UART0_RTSn
IO
IO
IO
I
0
0
PADCONFIG:
MCU_PADCONFIG8
0x04084020
MCU_GPIO0_8
pad
1
MCU_UART0_RXD
MCU_UART0_RXD
PADCONFIG:
MCU_PADCONFIG5
0x04084014
D8
F8
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_CANUART
VDDSHV_CANUART
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
MCU_GPIO0_5
MCU_UART0_TXD
MCU_GPIO0_6
7
0
7
IO
O
pad
MCU_UART0_TXD
PADCONFIG:
MCU_PADCONFIG6
0x04084018
IO
pad
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SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
MDIO0_MDC
MDIO0_MDC
0
7
0
7
O
PADCONFIG:
PADCONFIG88
0x000F4160
V12
V13
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
VDDSHV2
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
GPIO0_86
IO
IO
IO
pad
0
MDIO0_MDIO
MDIO0_MDIO
GPIO0_85
PADCONFIG:
PADCONFIG87
0x000F415C
pad
MMC0_CLK
I2C3_SCL
0
1
2
5
6
7
0
1
2
5
6
7
0
2
3
7
0
2
3
7
0
1
2
3
7
0
1
2
3
7
IO
IOD
IO
IO
IO
IO
IO
IOD
IO
IO
IO
IO
IO
IO
I
0
1
MMC0_CLK
EHRPWM2_A
SPI1_CS1
0
PADCONFIG:
PADCONFIG134
0x000F4218
AB7
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
1
TIMER_IO4
GPIO1_40
0
pad
1
MMC0_CMD
I2C3_SDA
1
MMC0_CMD
EHRPWM2_B
SPI1_CS2
0
PADCONFIG:
PADCONFIG136
0x000F4220
Y6
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
1
TIMER_IO5
GPIO1_41
0
pad
0
MMC1_CLK
TIMER_IO4
UART3_RXD
GPIO1_46
MMC1_CLK
0
PADCONFIG:
PADCONFIG141
0x000F4234
E22
C21
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV5
VDDSHV5
Yes
Yes
SDIO
SDIO
PU/PD
PU/PD
1
IO
IO
IO
O
pad
1
MMC1_CMD
TIMER_IO5
UART3_TXD
GPIO1_47
MMC1_CMD
0
PADCONFIG:
PADCONFIG143
0x000F423C
IO
I
pad
0
MMC1_SDCD
UART6_RXD
TIMER_IO6
UART3_RTSn
GPIO1_48
MMC1_SDCD
I
1
PADCONFIG:
PADCONFIG144
0x000F4240
E18
D18
IO
O
0
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
VDDSHV0
VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
IO
I
pad
0
MMC1_SDWP
UART6_TXD
TIMER_IO7
UART3_CTSn
GPIO1_49
MMC1_SDWP
O
PADCONFIG:
PADCONFIG145
0x000F4244
IO
I
0
1
Off / Off / Off
Off / Off / Off
1.8 V/3.3 V
IO
pad
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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
SPRSP77 – MARCH 2023
www.ti.com
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
MMC2_CLK
MCASP1_ACLKR
MCASP1_AXR5
UART6_RXD
GPIO0_69
0
1
2
3
7
0
1
2
3
7
0
1
3
7
0
1
3
7
0
1
2
6
7
0
1
2
5
6
7
0
1
2
5
6
7
IO
IO
IO
I
0
0
MMC2_CLK
PADCONFIG:
PADCONFIG70
0x000F4118
H22
0
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
VDDSHV6
Yes
Yes
SDIO
SDIO
PU/PD
PU/PD
1
IO
IO
IO
IO
O
pad
1
MMC2_CMD
MCASP1_AFSR
MCASP1_AXR4
UART6_TXD
GPIO0_70
MMC2_CMD
0
PADCONFIG:
PADCONFIG72
0x000F4120
G22
0
Off / Off / Off
Off / Off / Off
1.8 V/3.3 V
VDDSHV6
IO
I
pad
0
MMC2_SDCD
MCASP1_ACLKX
UART4_RXD
GPIO0_71
MMC2_SDCD
IO
I
0
PADCONFIG:
PADCONFIG73
0x000F4124
F22
E21
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV6
VDDSHV6
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
1
IO
I
pad
0
MMC2_SDWP
MCASP1_AFSX
UART4_TXD
GPIO0_72
MMC2_SDWP
IO
O
0
PADCONFIG:
PADCONFIG74
0x000F4128
IO
IO
I
pad
1
MMC0_DAT0
UART3_CTSn
EHRPWM_TZn_IN1
SPI2_CLK
MMC0_DAT0
1
PADCONFIG:
PADCONFIG133
0x000F4214
AA6
I
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
Yes
SDIO
PU/PD
IO
IO
IO
O
0
GPIO1_39
pad
1
MMC0_DAT1
UART3_RTSn
EHRPWM1_B
SPI1_CS3
MMC0_DAT1
IO
IO
IO
IO
IO
O
0
1
PADCONFIG:
PADCONFIG132
0x000F4210
AB6
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
SDIO
PU/PD
SPI2_CS0
1
GPIO1_38
pad
1
MMC0_DAT2
UART3_TXD
EHRPWM1_A
SPI1_CLK
MMC0_DAT2
IO
IO
IO
IO
0
0
PADCONFIG:
PADCONFIG131
0x000F420C
Y7
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
TIMER_IO0
0
GPIO1_37
pad
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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
www.ti.com
SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
MMC0_DAT3
0
1
2
5
6
7
0
1
2
6
7
0
1
2
6
7
0
1
2
5
6
7
0
1
2
5
6
7
0
1
2
3
4
7
IO
I
1
1
UART3_RXD
EHRPWM0_B
SPI1_CS0
MMC0_DAT3
IO
IO
IO
IO
IO
I
0
PADCONFIG:
PADCONFIG130
0x000F4208
AA7
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
1
SPI2_CS2
1
GPIO1_36
pad
1
MMC0_DAT4
UART2_CTSn
EHRPWM0_A
SPI2_D1
MMC0_DAT4
1
PADCONFIG:
PADCONFIG129
0x000F4204
Y8
IO
IO
IO
IO
O
0
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
VDDSHV4
VDDSHV4
Yes
Yes
SDIO
SDIO
PU/PD
PU/PD
0
GPIO1_35
pad
1
MMC0_DAT5
UART2_RTSn
EHRPWM_TZn_IN2
SPI2_D0
MMC0_DAT5
PADCONFIG:
PADCONFIG128
0x000F4200
W7
I
0
0
Off / Off / Off
Off / Off / Off
1.8 V/3.3 V
IO
IO
IO
O
GPIO1_34
pad
1
MMC0_DAT6
UART2_TXD
EHRPWM0_SYNCO
SPI1_D1
MMC0_DAT6
O
PADCONFIG:
PADCONFIG127
0x000F41FC
W9
AB8
B22
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV4
VDDSHV4
VDDSHV5
Yes
Yes
Yes
SDIO
SDIO
SDIO
PU/PD
PU/PD
PU/PD
IO
IO
IO
IO
I
0
1
SPI2_CS3
GPIO1_33
pad
1
MMC0_DAT7
UART2_RXD
EHRPWM0_SYNCI
SPI1_D0
1
MMC0_DAT7
I
0
PADCONFIG:
PADCONFIG126
0x000F41F8
IO
IO
IO
IO
I
0
SPI2_CS1
1
GPIO1_32
pad
1
MMC1_DAT0
CP_GEMAC_CPTS0_HW2TSPUSH
TIMER_IO3
0
MMC1_DAT0
IO
I
0
PADCONFIG:
PADCONFIG140
0x000F4230
UART2_CTSn
ECAP2_IN_APWM_OUT
GPIO1_45
1
IO
IO
0
pad
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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
SPRSP77 – MARCH 2023
www.ti.com
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
MMC1_DAT1
0
1
2
3
4
7
0
1
2
3
7
0
1
2
3
7
0
1
IO
I
1
0
0
CP_GEMAC_CPTS0_HW1TSPUSH
TIMER_IO2
MMC1_DAT1
IO
O
PADCONFIG:
PADCONFIG139
0x000F422C
D21
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV5
Yes
SDIO
PU/PD
UART2_RTSn
ECAP1_IN_APWM_OUT
GPIO1_44
IO
IO
IO
O
0
pad
1
MMC1_DAT2
MMC1_DAT2
CP_GEMAC_CPTS0_TS_SYNC
TIMER_IO1
PADCONFIG:
PADCONFIG138
0x000F4228
C22
D22
IO
O
0
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
VDDSHV5
VDDSHV5
Yes
Yes
SDIO
SDIO
PU/PD
PU/PD
UART2_TXD
GPIO1_43
IO
IO
O
pad
1
MMC1_DAT3
MMC1_DAT3
CP_GEMAC_CPTS0_TS_COMP
TIMER_IO0
PADCONFIG:
PADCONFIG137
0x000F4224
IO
I
0
1
Off / Off / Off
Off / Off / Off
1.8 V/3.3 V
UART2_RXD
GPIO1_42
IO
IO
IO
pad
1
MMC2_DAT0
MMC2_DAT0
PADCONFIG:
PADCONFIG69
0x000F4114
MCASP1_AXR0
0
E20
F21
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV6
VDDSHV6
Yes
Yes
SDIO
SDIO
PU/PD
PU/PD
GPIO0_68
7
IO
pad
MMC2_DAT1
MMC2_DAT1
0
1
IO
IO
1
0
PADCONFIG:
PADCONFIG68
0x000F4110
MCASP1_AXR1
GPIO0_67
7
IO
pad
MMC2_DAT2
MCASP1_AXR2
UART5_TXD
GPIO0_66
0
1
3
7
0
1
3
7
0
IO
IO
O
1
0
MMC2_DAT2
PADCONFIG:
PADCONFIG67
0x000F410C
F20
G21
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV6
VDDSHV6
Yes
Yes
SDIO
SDIO
PU/PD
PU/PD
IO
IO
IO
I
pad
1
MMC2_DAT3
MCASP1_AXR3
UART5_RXD
GPIO0_65
MMC2_DAT3
0
PADCONFIG:
PADCONFIG66
0x000F4108
1
IO
O
pad
OSPI0_CLK
OSPI0_CLK
PADCONFIG:
PADCONFIG0
0x000F4000
L22
L21
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV1
VDDSHV1
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
GPIO0_0
7
IO
pad
OSPI0_DQS
OSPI0_DQS
0
5
I
I
0
1
PADCONFIG:
PADCONFIG2
0x000F4008
UART5_CTSn
GPIO0_2
7
IO
pad
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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
www.ti.com
SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
OSPI0_LBCLKO
OSPI0_LBCLKO
0
5
IO
O
0
PADCONFIG:
PADCONFIG1
0x000F4004
UART5_RTSn
GPIO0_1
K22
H21
G19
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV1
VDDSHV1
VDDSHV1
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
7
0
IO
O
pad
OSPI0_CSn0
OSPI0_CSn0
PADCONFIG:
PADCONFIG11
0x000F402C
GPIO0_11
7
0
7
IO
O
pad
OSPI0_CSn1
OSPI0_CSn1
GPIO0_12
PADCONFIG:
PADCONFIG12
0x000F4030
IO
pad
1
OSPI0_CSn2
0
1
2
3
4
5
7
0
1
2
3
4
5
7
0
O
IO
O
SPI1_CS1
OSPI0_CSn2
OSPI0_RESET_OUT1
MCASP1_AFSR
MCASP1_AXR2
UART5_RXD
PADCONFIG:
PADCONFIG13
0x000F4034
K20
IO
IO
I
0
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
1
GPIO0_13
IO
O
pad
OSPI0_CSn3
OSPI0_RESET_OUT0
OSPI0_ECC_FAIL
MCASP1_ACLKR
MCASP1_AXR3
UART5_TXD
O
OSPI0_CSn3
I
1
0
0
PADCONFIG:
PADCONFIG14
0x000F4038
G20
IO
IO
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
GPIO0_14
IO
IO
pad
0
OSPI0_D0
OSPI0_D0
PADCONFIG:
PADCONFIG3
0x000F400C
J21
J18
J19
H18
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV1
VDDSHV1
VDDSHV1
VDDSHV1
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
GPIO0_3
OSPI0_D1
GPIO0_4
OSPI0_D2
GPIO0_5
OSPI0_D3
GPIO0_6
7
0
7
0
7
0
7
IO
IO
IO
IO
IO
IO
IO
pad
0
OSPI0_D1
PADCONFIG:
PADCONFIG4
0x000F4010
pad
0
OSPI0_D2
PADCONFIG:
PADCONFIG5
0x000F4014
pad
0
OSPI0_D3
PADCONFIG:
PADCONFIG6
0x000F4018
pad
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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
SPRSP77 – MARCH 2023
www.ti.com
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
OSPI0_D4
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
IO
IO
IO
I
0
1
OSPI0_D4
SPI1_CS0
PADCONFIG:
PADCONFIG7
0x000F401C
K21
MCASP1_AXR1
UART6_RXD
GPIO0_7
0
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV1
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
1
IO
IO
IO
IO
O
pad
0
OSPI0_D5
OSPI0_D5
SPI1_CLK
0
PADCONFIG:
PADCONFIG8
0x000F4020
H19
J20
J22
MCASP1_AXR0
UART6_TXD
GPIO0_8
0
VDDSHV1
VDDSHV1
VDDSHV1
IO
IO
IO
IO
O
pad
0
OSPI0_D6
OSPI0_D6
SPI1_D0
0
PADCONFIG:
PADCONFIG9
0x000F4024
MCASP1_ACLKX
UART6_RTSn
GPIO0_9
0
IO
IO
IO
IO
I
pad
0
OSPI0_D7
OSPI0_D7
SPI1_D1
0
PADCONFIG:
PADCONFIG10
0x000F4028
MCASP1_AFSX
UART6_CTSn
GPIO0_10
0
1
IO
O
pad
PMIC_LPM_EN0
PMIC_LPM_EN0
PADCONFIG:
MCU_PADCONFIG32
0x04084080
D12
F18
Off / Off / Off
Off / Low / Off
Off / Low / Off
On / Off / Up
Off / Off / Off
Off / SS / Off
Off / SS / Off
Off / SS / Off
On / Off / Up
Off / Off / Off
0
0
0
0
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_CANUART
VDDSHV0
Yes
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
MCU_GPIO0_22
PORz_OUT
7
IO
pad
PORz_OUT
PADCONFIG:
PADCONFIG148
0x000F4250
0
O
RESETSTATz
PADCONFIG:
PADCONFIG147
0x000F424C
F19
RESETSTATz
RESET_REQz
0
0
O
I
VDDSHV0
RESET_REQz
PADCONFIG:
PADCONFIG146
0x000F4248
E19
VDDSHV0
RGMII1_RXC
RGMII1_RXC
0
1
I
I
0
0
PADCONFIG:
PADCONFIG82
0x000F4148
RMII1_REF_CLK
AA16
VDDSHV2
GPIO0_80
7
IO
pad
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SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
RGMII1_RX_CTL
RGMII1_RX_CTL
0
1
I
I
0
0
PADCONFIG:
PADCONFIG81
0x000F4144
RMII1_RX_ER
GPIO0_79
AA15
AB17
W16
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
VDDSHV2
VDDSHV2
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
7
IO
pad
RGMII1_TXC
RGMII1_TXC
0
1
IO
I
0
0
PADCONFIG:
PADCONFIG76
0x000F4130
RMII1_CRS_DV
GPIO0_74
7
IO
pad
RGMII1_TX_CTL
RGMII1_TX_CTL
RMII1_TX_EN
0
1
O
O
PADCONFIG:
PADCONFIG75
0x000F412C
GPIO0_73
7
IO
pad
RGMII2_RXC
RMII2_REF_CLK
MCASP2_AXR1
GPIO1_2
0
1
2
7
0
1
2
7
0
1
2
7
0
1
2
7
0
1
I
0
0
RGMII2_RXC
I
PADCONFIG:
PADCONFIG96
0x000F4180
AA20
W18
AB19
Y19
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
VDDSHV2
VDDSHV2
VDDSHV2
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
IO
IO
I
0
pad
0
RGMII2_RX_CTL
RMII2_RX_ER
MCASP2_AXR3
GPIO1_1
RGMII2_RX_CTL
I
0
PADCONFIG:
PADCONFIG95
0x000F417C
IO
IO
IO
I
0
pad
0
RGMII2_TXC
RMII2_CRS_DV
MCASP2_AXR5
GPIO0_88
RGMII2_TXC
0
PADCONFIG:
PADCONFIG90
0x000F4168
IO
IO
O
O
IO
IO
I
0
pad
RGMII2_TX_CTL
RMII2_TX_EN
MCASP2_AXR4
GPIO0_87
RGMII2_TX_CTL
PADCONFIG:
PADCONFIG89
0x000F4164
0
pad
0
RGMII1_RD0
RGMII1_RD0
RMII1_RXD0
PADCONFIG:
PADCONFIG83
0x000F414C
I
0
AB16
V15
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
VDDSHV2
VDDSHV2
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
GPIO0_81
7
IO
pad
RGMII1_RD1
RGMII1_RD1
RMII1_RXD1
0
1
I
I
0
0
PADCONFIG:
PADCONFIG84
0x000F4150
GPIO0_82
7
0
IO
I
pad
0
RGMII1_RD2
RGMII1_RD2
PADCONFIG:
PADCONFIG85
0x000F4154
W15
GPIO0_83
7
IO
pad
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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
SPRSP77 – MARCH 2023
www.ti.com
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
RGMII1_RD3
RGMII1_RD3
GPIO0_84
0
7
I
0
PADCONFIG:
PADCONFIG86
0x000F4158
V14
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
VDDSHV2
VDDSHV2
VDDSHV2
VDDSHV2
Yes
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
IO
pad
RGMII1_TD0
RGMII1_TD0
RMII1_TXD0
0
1
O
O
PADCONFIG:
PADCONFIG77
0x000F4134
Y17
V16
GPIO0_75
7
IO
pad
RGMII1_TD1
RGMII1_TD1
RMII1_TXD1
0
1
O
O
PADCONFIG:
PADCONFIG78
0x000F4138
GPIO0_76
7
0
IO
O
pad
pad
RGMII1_TD2
RGMII1_TD2
PADCONFIG:
PADCONFIG79
0x000F413C
Y16
GPIO0_77
7
IO
RGMII1_TD3
RGMII1_TD3
CLKOUT0
0
1
O
O
PADCONFIG:
PADCONFIG80
0x000F4140
AA17
GPIO0_78
7
IO
pad
RGMII2_RD0
RMII2_RXD0
MCASP2_AXR2
GPIO1_3
0
1
2
7
0
1
2
5
7
0
2
7
8
0
2
7
8
0
1
2
7
I
0
0
RGMII2_RD0
I
PADCONFIG:
PADCONFIG97
0x000F4184
AA21
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
VDDSHV2
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
IO
IO
I
0
pad
0
RGMII2_RD1
RMII2_RXD1
MCASP2_AFSR
MCASP2_AXR7
GPIO1_4
RGMII2_RD1
I
0
PADCONFIG:
PADCONFIG98
0x000F4188
Y20
IO
IO
IO
I
0
Off / Off / Off
Off / Off / Off
0
pad
0
RGMII2_RD2
MCASP2_AXR0
GPIO1_5
RGMII2_RD2
IO
IO
I
0
PADCONFIG:
PADCONFIG99
0x000F418C
AB21
AB20
AA19
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
VDDSHV2
VDDSHV2
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
pad
0
EQEP2_A
RGMII2_RD3
AUDIO_EXT_REFCLK0
GPIO1_6
I
0
RGMII2_RD3
IO
IO
I
0
PADCONFIG:
PADCONFIG100
0x000F4190
pad
0
EQEP2_B
RGMII2_TD0
RMII2_TXD0
MCASP2_AXR6
GPIO0_89
O
O
IO
IO
RGMII2_TD0
PADCONFIG:
PADCONFIG91
0x000F416C
0
pad
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www.ti.com
SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
RGMII2_TD1
0
1
2
5
7
0
2
7
8
0
1
2
7
8
O
O
RGMII2_TD1
RMII2_TXD1
MCASP2_ACLKR
MCASP2_AXR8
GPIO0_90
PADCONFIG:
PADCONFIG92
0x000F4170
Y18
AA18
W17
IO
0
0
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
IO
IO
pad
RGMII2_TD2
MCASP2_AFSX
GPIO0_91
O
RGMII2_TD2
IO
0
pad
0
PADCONFIG:
PADCONFIG93
0x000F4174
VDDSHV2
VDDSHV2
IO
EQEP2_I
IO
RGMII2_TD3
CLKOUT0
O
RGMII2_TD3
O
PADCONFIG:
PADCONFIG94
0x000F4178
MCASP2_ACLKX
GPIO1_0
IO
0
pad
0
IO
EQEP2_S
IO
C6
D6
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
IO
RSVD1
E7
RSVD2
F6
RSVD3
F10
G7
U11
V11
RSVD4
RSVD5
RSVD6
RSVD7
SPI0_CLK
0
1
2
7
0
2
0
SPI0_CLK
CP_GEMAC_CPTS0_TS_SYNC
EHRPWM1_A
GPIO1_17
O
PADCONFIG:
PADCONFIG111
0x000F41BC
A17
D16
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0
VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
IO
0
pad
1
IO
SPI0_CS0
SPI0_CS0
IO
PADCONFIG:
PADCONFIG109
0x000F41B4
EHRPWM0_A
IO
0
GPIO1_15
7
IO
pad
1
SPI0_CS1
0
1
2
3
7
9
IO
O
CP_GEMAC_CPTS0_TS_COMP
EHRPWM0_B
SPI0_CS1
IO
IO
IO
I
0
0
PADCONFIG:
PADCONFIG110
0x000F41B8
C16
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
ECAP0_IN_APWM_OUT
GPIO1_16
pad
0
EHRPWM_TZn_IN5
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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
SPRSP77 – MARCH 2023
www.ti.com
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
SPI0_D0
0
1
2
7
0
1
2
7
IO
I
0
0
SPI0_D0
CP_GEMAC_CPTS0_HW1TSPUSH
EHRPWM1_B
PADCONFIG:
PADCONFIG112
0x000F41C0
B15
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
IO
IO
IO
I
0
GPIO1_18
pad
0
SPI0_D1
SPI0_D1
CP_GEMAC_CPTS0_HW2TSPUSH
EHRPWM_TZn_IN0
GPIO1_19
0
PADCONFIG:
PADCONFIG113
0x000F41C4
E15
VDDSHV0
I
0
IO
pad
TCK
PADCONFIG:
MCU_PADCONFIG25
0x04084064
A14
A16
C14
B14
F15
TCK
TDI
0
0
0
0
0
I
On / Off / Up
On / Off / Up
Off / Off / Up
On / Off / Up
On / Off / Down
On / Off / Up
On / Off / Up
Off / SS / Up
On / Off / Up
On / Off / Down
0
0
0
0
0
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_MCU
VDDSHV_MCU
VDDSHV_MCU
VDDSHV_MCU
VDDSHV_MCU
Yes
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
TDI
PADCONFIG:
MCU_PADCONFIG27
0x0408406C
I
TDO
PADCONFIG:
MCU_PADCONFIG28
0x04084070
TDO
TMS
TRSTn
OZ
TMS
PADCONFIG:
MCU_PADCONFIG29
0x04084074
I
I
TRSTn
PADCONFIG:
MCU_PADCONFIG26
0x04084068
UART0_CTSn
SPI0_CS2
0
1
2
3
4
5
7
8
9
I
IO
IOD
I
1
1
I2C3_SCL
1
UART0_CTSn
UART2_RXD
TIMER_IO6
1
PADCONFIG:
PADCONFIG116
0x000F41D0
F14
IO
IO
IO
IO
I
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
AUDIO_EXT_REFCLK0
GPIO1_22
0
pad
0
MCASP2_AFSX
MMC2_SDCD
0
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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
www.ti.com
SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
UART0_RTSn
0
1
2
3
4
5
7
8
9
0
1
2
3
7
0
1
2
3
7
O
IO
IOD
O
SPI0_CS3
1
1
I2C3_SDA
UART0_RTSn
UART2_TXD
TIMER_IO7
PADCONFIG:
PADCONFIG117
0x000F41D4
C15
IO
IO
IO
IO
I
0
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
AUDIO_EXT_REFCLK1
GPIO1_23
pad
0
MCASP2_ACLKX
MMC2_SDWP
UART0_RXD
ECAP1_IN_APWM_OUT
SPI2_D0
0
I
1
UART0_RXD
IO
IO
IO
IO
O
0
PADCONFIG:
PADCONFIG114
0x000F41C8
E14
D15
0
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
VDDSHV0
VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
EHRPWM2_A
GPIO1_20
0
pad
UART0_TXD
ECAP2_IN_APWM_OUT
SPI2_D1
UART0_TXD
IO
IO
IO
IO
0
0
PADCONFIG:
PADCONFIG115
0x000F41CC
Off / Off / Off
Off / Off / Off
1.8 V/3.3 V
EHRPWM2_B
GPIO1_21
0
pad
VDDA_1P8_USB,
VDDA_3P3_USB
AA10
AA9
USB0_DM
USB0_DM
IO
1.8 V/3.3 V
1.8 V/3.3 V
USB2PHY
USB2PHY
VDDA_1P8_USB,
VDDA_3P3_USB
USB0_DP
USB0_DP
IO
O
USB0_DRVVBUS
USB0_DRVVBUS
0
7
PADCONFIG:
PADCONFIG149
0x000F4268
C20
Off / Off / Down
Off / Off / Down
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
GPIO1_50
IO
pad
VDDA_1P8_USB,
VDDA_3P3_USB
W10
V8
USB0_RCALIB
USB0_VBUS
USB1_DM
USB0_RCALIB
USB0_VBUS
USB1_DM
A
A
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
USB2PHY
USB2PHY
USB2PHY
USB2PHY
VDDA_1P8_USB,
VDDA_3P3_USB
VDDA_1P8_USB,
VDDA_3P3_USB
Y11
Y10
IO
VDDA_1P8_USB,
VDDA_3P3_USB
USB1_DP
USB1_DP
IO
O
USB1_DRVVBUS
USB1_DRVVBUS
0
7
PADCONFIG:
PADCONFIG150
0x000F4280
D19
U7
Off / Off / Down
Off / Off / Down
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
GPIO1_51
IO
A
pad
VDDA_1P8_USB,
VDDA_3P3_USB
USB1_RCALIB
USB1_RCALIB
USB2PHY
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SPRSP77 – MARCH 2023
www.ti.com
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
VDDA_1P8_USB,
VDDA_3P3_USB
V6
USB1_VBUS
USB1_VBUS
A
1.8 V/3.3 V
USB2PHY
T10
T12
VDDA_1P8_USB
VDDA_1P8_CSIRX0
VDDA_3P3_USB
VDDA_CORE_CSIRX0
VDDA_CORE_USB
VDDA_DDR_PLL0
VDDA_MCU
VDDA_1P8_USB
VDDA_1P8_CSIRX0
VDDA_3P3_USB
VDDA_CORE_CSIRX0
VDDA_CORE_USB
VDDA_DDR_PLL0
VDDA_MCU
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
U10
T11
T9
M9
J10
N9
VDDA_PLL0
VDDA_PLL0
R11
M13
K13
K10
P16
G18
L10
VDDA_PLL1
VDDA_PLL1
VDDA_PLL2
VDDA_PLL2
VDDA_PLL3
VDDA_PLL3
VDDA_PLL4
VDDA_PLL4
VDDA_TEMP0
VDDA_TEMP1
VDDA_TEMP2
VDDA_TEMP0
VDDA_TEMP1
VDDA_TEMP2
J14, K12,
M10, M14, VDDR_CORE
P12, P9
VDDR_CORE
PWR
G14, H13
K15, L16
VDDSHV0
VDDSHV1
VDDSHV0
VDDSHV1
PWR
PWR
R13, T13,
U13
VDDSHV2
VDDSHV3
VDDSHV2
VDDSHV3
PWR
PWR
L15, M15,
N15
T8, U8
G16, H15
H16, H17
H8
VDDSHV4
VDDSHV4
PWR
PWR
PWR
PWR
PWR
VDDSHV5
VDDSHV5
VDDSHV6
VDDSHV6
VDDSHV_CANUART
VDDSHV_MCU
VDDSHV_CANUART
VDDSHV_MCU
G11, H10
A2, AA1,
AB2, B1, J7,
K8, L7, M8,
N7, P8
VDDS_DDR
VDDS_DDR
PWR
L8
J8
VDDS_DDR_C
VDDS_OSC0
VDDS_DDR_C
VDDS_OSC0
PWR
PWR
PWR
H9
VDD_CANUART
VDD_CANUART
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SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
J11, J13, J15,
J9, K14, L11,
L13, L9, M12,
N11, N13,
VDD_CORE
VDD_CORE
PWR
P10, P14,
R15, R9, T16,
U15
F12
F9
VMON_1P8_SOC
VMON_3P3_SOC
VMON_VSYS
VMON_1P8_SOC
VMON_3P3_SOC
VMON_VSYS
VOUT0_DE
A
A
H12
A
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
O
VOUT0_DE
GPMC0_A17
UART3_CTSn
GPIO0_62
OZ
I
PADCONFIG:
PADCONFIG63
0x000F40FC
U17
T18
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
1
IO
O
pad
VOUT0_HSYNC
GPMC0_A16
UART3_RTSn
GPIO0_61
VOUT0_HSYNC
OZ
O
PADCONFIG:
PADCONFIG62
0x000F40F8
IO
O
pad
VOUT0_PCLK
GPMC0_A19
UART2_CTSn
GPIO0_64
VOUT0_PCLK
OZ
I
PADCONFIG:
PADCONFIG65
0x000F4104
AA22
V17
U22
U21
U20
1
IO
O
pad
VOUT0_VSYNC
GPMC0_A18
UART2_RTSn
GPIO0_63
VOUT0_VSYNC
OZ
O
PADCONFIG:
PADCONFIG64
0x000F4100
IO
O
pad
VOUT0_DATA0
GPMC0_A0
VOUT0_DATA0
OZ
I
PADCONFIG:
PADCONFIG46
0x000F40B8
UART2_RXD
GPIO0_45
1
IO
O
pad
VOUT0_DATA1
GPMC0_A1
VOUT0_DATA1
OZ
O
PADCONFIG:
PADCONFIG47
0x000F40BC
UART2_TXD
GPIO0_46
IO
O
pad
VOUT0_DATA2
GPMC0_A2
VOUT0_DATA2
OZ
I
PADCONFIG:
PADCONFIG48
0x000F40C0
UART3_RXD
GPIO0_47
1
IO
pad
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SPRSP77 – MARCH 2023
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Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
VOUT0_DATA3
GPMC0_A3
UART3_TXD
GPIO0_48
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
O
OZ
O
VOUT0_DATA3
PADCONFIG:
PADCONFIG49
0x000F40C4
U19
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
IO
O
pad
VOUT0_DATA4
GPMC0_A4
UART4_RXD
GPIO0_49
VOUT0_DATA4
OZ
I
PADCONFIG:
PADCONFIG50
0x000F40C8
T19
U18
V22
V21
V19
V18
W22
W21
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV3
1
IO
O
pad
VOUT0_DATA5
GPMC0_A5
UART4_TXD
GPIO0_50
VOUT0_DATA5
OZ
O
PADCONFIG:
PADCONFIG51
0x000F40CC
IO
O
pad
VOUT0_DATA6
GPMC0_A6
UART5_RXD
GPIO0_51
VOUT0_DATA6
OZ
I
PADCONFIG:
PADCONFIG52
0x000F40D0
1
IO
O
pad
VOUT0_DATA7
GPMC0_A7
UART5_TXD
GPIO0_52
VOUT0_DATA7
OZ
O
PADCONFIG:
PADCONFIG53
0x000F40D4
IO
O
pad
VOUT0_DATA8
GPMC0_A8
UART6_RXD
GPIO0_53
VOUT0_DATA8
OZ
I
PADCONFIG:
PADCONFIG54
0x000F40D8
1
IO
O
pad
VOUT0_DATA9
GPMC0_A9
UART6_TXD
GPIO0_54
VOUT0_DATA9
OZ
O
PADCONFIG:
PADCONFIG55
0x000F40DC
IO
O
pad
pad
VOUT0_DATA10
GPMC0_A10
UART6_RTSn
GPIO0_55
VOUT0_DATA10
OZ
O
PADCONFIG:
PADCONFIG56
0x000F40E0
IO
O
VOUT0_DATA11
GPMC0_A11
UART6_CTSn
GPIO0_56
VOUT0_DATA11
OZ
I
PADCONFIG:
PADCONFIG57
0x000F40E4
1
IO
pad
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SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
VOUT0_DATA12
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
O
OZ
O
VOUT0_DATA12
GPMC0_A12
UART5_RTSn
GPIO0_57
PADCONFIG:
PADCONFIG58
0x000F40E8
W20
W19
Y21
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
IO
O
pad
VOUT0_DATA13
GPMC0_A13
UART5_CTSn
GPIO0_58
VOUT0_DATA13
OZ
I
PADCONFIG:
PADCONFIG59
0x000F40EC
VDDSHV3
VDDSHV3
VDDSHV3
1
IO
O
pad
VOUT0_DATA14
GPMC0_A14
UART4_RTSn
GPIO0_59
VOUT0_DATA14
OZ
O
PADCONFIG:
PADCONFIG60
0x000F40F0
IO
O
pad
VOUT0_DATA15
GPMC0_A15
UART4_CTSn
GPIO0_60
VOUT0_DATA15
OZ
I
PADCONFIG:
PADCONFIG61
0x000F40F4
Y22
F7
1
IO
PWR
pad
VPP
VPP
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SPRSP77 – MARCH 2023
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Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
A1, A10, A13,
A18, A22, A4,
A6, AA11,
AA14, AA2,
AA4, AA8,
AB1, AB12,
AB15, AB18,
AB22, AB3,
AB5, AB9,
B3, B5, B7,
C4, D11, D2,
D20, D4, E1,
E3, E5, F11,
F13, F16, F2,
F4, G12,
G17, G3, G5,
G9, H1, H11,
H14, H20,
H4, J12, J17,
J3, K1, K11,
K4, K7, K9,
L12, L14,
VSS
VSS
PWR
L20, L3, M11,
M17, M4, M7,
N1, N10,
N12, N14,
N16, N8, P11,
P13, P15,
P17, P20, P7,
R10, R12,
R14, R16,
R2, R4, R6,
T1, T15, T17,
T3, T5, T7,
U12, U14,
U16, U2, U4,
U6, U9, V1,
V20, V3, V5,
V7, V9, W11,
W14, W2,
W4, W6, W8,
Y12, Y15, Y3,
Y5, Y9
WKUP_CLKOUT0
WKUP_CLKOUT0
MCU_GPIO0_23
WKUP_I2C0_SCL
MCU_GPIO0_19
WKUP_I2C0_SDA
MCU_GPIO0_20
0
7
0
7
0
7
O
PADCONFIG:
MCU_PADCONFIG33
0x04084084
B10
D13
E13
Off / Off / Off
Off / Off / NA
Off / Off / NA
Off / SS / Off
On / SS / NA
On / SS / NA
0
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_MCU
VDDSHV_MCU
VDDSHV_MCU
Yes
Yes
Yes
LVCMOS
I2C OD FS
I2C OD FS
PU/PD
IO
pad
1
WKUP_I2C0_SCL
IOD
IOD
IOD
IOD
PADCONFIG:
MCU_PADCONFIG19
0x0408404C
pad
1
WKUP_I2C0_SDA
PADCONFIG:
MCU_PADCONFIG20
0x04084050
pad
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SPRSP77 – MARCH 2023
Table 6-1. Pin Attributes (AMB Package) (continued)
BALL
STATE
DURING
RESET
BALL
STATE
AFTER
RESET
MUX
MODE
AFTER
RESET
[9]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER [1]
TYPE
[5]
DSIS
[6]
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
OPERATING
VOLTAGE [10]
POWER [11]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
A8
A9
WKUP_LFOSC0_XI
WKUP_LFOSC0_XO
WKUP_LFOSC0_XI
I
1.8 V
1.8 V
VDDS_OSC0
VDDS_OSC0
LFXOSC
LFXOSC
WKUP_LFOSC0_XO
WKUP_UART0_CTSn
WKUP_TIMER_IO0
MCU_SPI1_CS0
O
I
0
1
3
7
0
1
3
7
0
2
1
0
WKUP_UART0_CTSn
IO
IO
IO
O
IO
IO
IO
I
PADCONFIG:
MCU_PADCONFIG11
0x0408402C
C10
C8
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_CANUART
VDDSHV_CANUART
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
1
MCU_GPIO0_11
pad
WKUP_UART0_RTSn
WKUP_TIMER_IO1
MCU_SPI1_CLK
WKUP_UART0_RTSn
0
0
PADCONFIG:
MCU_PADCONFIG12
0x04084030
MCU_GPIO0_12
pad
1
WKUP_UART0_RXD
WKUP_UART0_RXD
MCU_SPI0_CS2
PADCONFIG:
MCU_PADCONFIG9
0x04084024
IO
1
C9
E9
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_CANUART
VDDSHV_CANUART
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
MCU_GPIO0_9
7
IO
pad
WKUP_UART0_TXD
WKUP_UART0_TXD
MCU_SPI1_CS2
0
2
O
PADCONFIG:
MCU_PADCONFIG10
0x04084028
IO
1
MCU_GPIO0_10
7
IO
pad
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6.3 Signal Descriptions
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing
options.
The following list describes the column headers:
1. SIGNAL NAME: The name of the signal passing through the pin.
Note
Signal names and descriptions provided in each Signal Descriptions table, represent the pin
multiplexed signal function which is implemented at the pin and selected via PADCONFIG
registers. Device subsystems may provide secondary multiplexing of signal functions, which are
not described in these tables. For more information on secondary multiplexed signal functions,
see the respective peripheral chapter of the device TRM.
2. PIN TYPE: Signal direction and type:
•
•
•
•
•
•
•
•
•
•
•
I = Input
O = Output
OD = Output, with open-drain output function
IO = Input, Output, or simultaneously Input and Output
IOD = Input, Output, or simultaneously Input and Output with open-drain output function
IOZ = Input, Output, or simultaneously Input and Output with three-state output function
OZ = Output with three-state output function
A = Analog
PWR = Power
GND = Ground
CAP = LDO Capacitor
3. DESCRIPTION: Description of the signal
ꢀ
4. BALL: Ball number(s) associated with signal
6.3.1 CPSW3G
6.3.1.1 MAIN Domain
Table 6-2. CPSW3G0 RGMII1 Signal Descriptions
SIGNAL NAME [1]
RGMII1_RXC
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
AA16
AA15
AB17
W16
I
I
RGMII Receive Clock
RGMII1_RX_CTL
RGMII1_TXC
RGMII1_TX_CTL
RGMII1_RD0
RGMII1_RD1
RGMII1_RD2
RGMII1_RD3
RGMII1_TD0
RGMII1_TD1
RGMII1_TD2
RGMII1_TD3
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
IO
O
I
AB16
V15
I
I
W15
I
V14
O
O
O
O
Y17
V16
Y16
AA17
Table 6-3. CPSW3G0 RGMII2 Signal Descriptions
SIGNAL NAME [1]
RGMII2_RXC
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
I
RGMII Receive Clock
AA20
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SPRSP77 – MARCH 2023
Table 6-3. CPSW3G0 RGMII2 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
W18
RGMII2_RX_CTL
RGMII2_TXC
RGMII2_TX_CTL
RGMII2_RD0
RGMII2_RD1
RGMII2_RD2
RGMII2_RD3
RGMII2_TD0
RGMII2_TD1
RGMII2_TD2
RGMII2_TD3
I
IO
O
I
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
AB19
Y19
AA21
Y20
I
I
AB21
AB20
AA19
Y18
I
O
O
O
O
AA18
W17
Table 6-4. CPSW3G0 RMII1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
AB17
AA16
AA15
W16
RMII1_CRS_DV
RMII1_REF_CLK
RMII1_RX_ER
RMII1_TX_EN
RMII1_RXD0
RMII1_RXD1
RMII1_TXD0
I
I
RMII Carrier Sense / Data Valid
RMII Reference Clock
RMII Receive Data Error
RMII Transmit Enable
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
I
O
I
AB16
V15
I
O
O
Y17
RMII1_TXD1
V16
Table 6-5. CPSW3G0 RMII2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
AB19
AA20
W18
RMII2_CRS_DV
RMII2_REF_CLK
RMII2_RX_ER
RMII2_TX_EN
RMII2_RXD0
RMII2_RXD1
RMII2_TXD0
I
I
RMII Carrier Sense / Data Valid
RMII Reference Clock
RMII Receive Data Error
RMII Transmit Enable
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
I
O
I
Y19
AA21
Y20
I
O
O
AA19
Y18
RMII2_TXD1
6.3.2 CPTS
Note
Some CPTS signals are connected directly to CPTS modules within the device. Other CPTS signals
are connected to the Time Sync Router and fanned out to peripherals linked to the router. Input
signals are sent to the peripherals while output signals are sourced from the peripherals. For more
information, see the Time Sync and Compare Events section in the Time Sync chapter in the device
TRM.
6.3.2.1 MAIN Domain
Table 6-6. CPTS Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
CP_GEMAC_CPTS0_RFT_CLK
I
CPTS Reference Clock Input
B16
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Table 6-6. CPTS Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
CPTS Time Stamp Counter Compare Output from
CPSW3G0 CPTS
CP_GEMAC_CPTS0_TS_COMP
O
C16, D22
A17, C22
B15, D21
B22, E15
D17
CPTS Time Stamp Counter Bit Output from CPSW3G0
CPTS
CP_GEMAC_CPTS0_TS_SYNC
CP_GEMAC_CPTS0_HW1TSPUSH
CP_GEMAC_CPTS0_HW2TSPUSH
SYNC0_OUT
O
I
CPTS Hardware Time Stamp Push Input to Time Sync
Router
CPTS Hardware Time Stamp Push Input to Time Sync
Router
I
CPTS Time Stamp Generator Bit 0 Output from Time
Sync Router
O
O
O
O
CPTS Time Stamp Generator Bit 1 Output from Time
Sync Router
SYNC1_OUT
B16
CPTS Time Stamp Generator Bit 2 Output from Time
Sync Router
SYNC2_OUT
B17
CPTS Time Stamp Generator Bit 3 Output from Time
Sync Router
SYNC3_OUT
C18
6.3.3 CSI-2
6.3.3.1 MAIN Domain
Table 6-7. CSIRX0 Signal Descriptions
SIGNAL NAME [1]
CSI0_RXCLKN
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
AB14
I
I
CSI Differential Receive Clock Input (negative)
CSI Differential Receive Clock Input (positive)
CSI0_RXCLKP
AB13
CSI pin connected to external resistor for on-chip
resistor calibration
CSI0_RXRCALIB (1)
A
V10
CSI0_RXN0
CSI0_RXN1
CSI0_RXN2
CSI0_RXN3
CSI0_RXP0
CSI0_RXP1
CSI0_RXP2
CSI0_RXP3
I
I
I
I
I
I
I
I
CSI Differential Receive Input (negative)
CSI Differential Receive Input (negative)
CSI Differential Receive Input (negative)
CSI Differential Receive Input (negative)
CSI Differential Receive Input (positive)
CSI Differential Receive Input (positive)
CSI Differential Receive Input (positive)
CSI Differential Receive Input (positive)
W12
Y13
AA13
AB11
W13
Y14
AA12
AB10
(1) An external 499 Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is
7.2mW. No external voltage should be applied to this pin.
6.3.4 DDRSS
6.3.4.1 MAIN Domain
Table 6-8. DDRSS0 Signal Descriptions
SIGNAL NAME [1]
DDR0_ACT_n
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
O
DDRSS Activation Command
N5
H7
DDR0_ALERT_n
DDR0_CAS_n (1)
IO
DDRSS Alert
DDR4 Column Address Strobe / LPDDR4 Chip Select
1B
O
M5
DDR0_PAR
DDR0_RAS_n (1)
DDR0_WE_n
DDR0_A0
O
O
O
O
O
DDRSS Command and Address Parity
DDR4 Row Address Strobe / LPDDR4 Chip Select 0B
DDRSS Write Enable
N2
M6
N6
J5
DDRSS Address Bus
DDR0_A1
DDRSS Address Bus
J2
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Table 6-8. DDRSS0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
J4
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
O
O
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Bank Address
DDRSS Bank Address
DDRSS Bank Group
DDRSS Bank Group
IO Pad Calibration Resistor
DDRSS Clock
L4
O
J1
O
K5
K3
H2
L6
O
O
O
O
L2
O
K2
L5
O
O
M3
M2
K6
H3
P4
R7
H6
M1
L1
O
O
O
O
O
DDR0_CAL0 (2)
A
DDR0_CK0
O
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n (1)
DDR0_CS1_n (1)
DDR0_DM0
DDR0_DM1
DDR0_DM2
DDR0_DM3
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
O
DDRSS Negative Clock
DDRSS Clock Enable
DDRSS Clock Enable
DDR4 Chip Select 0 / LPDDR4 Chip Select 0A
DDR4 Chip Select 1 / LPDDR4 Chip Select 1A
DDRSS Data Mask
DDRSS Data Mask
DDRSS Data Mask
DDRSS Data Mask
DDRSS Data
O
P3
P5
J6
O
O
O
N4
C2
F3
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
U1
W3
A5
B4
B6
D5
C5
C3
B2
A3
E2
F5
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
E6
G2
G6
G4
E4
D3
T6
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
T4
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Table 6-8. DDRSS0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
DDR0_DQS0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
U5
R5
P2
R3
T2
U3
Y2
V2
V4
W5
Y4
AA3
AA5
AB4
D1
C1
G1
F1
DDRSS Data Strobe
DDR0_DQS0_n
DDR0_DQS1
DDRSS Complimentary Data Strobe
DDRSS Data Strobe
DDR0_DQS1_n
DDR0_DQS2
DDRSS Complimentary Data Strobe
DDRSS Data Strobe
R1
P1
DDR0_DQS2_n
DDR0_DQS3
DDRSS Complimentary Data Strobe
DDRSS Data Strobe
W1
Y1
DDR0_DQS3_n
DDR0_ODT0
DDRSS Complimentary Data Strobe
DDRSS On-Die Termination for Chip Select 0
DDRSS On-Die Termination for Chip Select 1
DDRSS Reset
H5
N3
P6
DDR0_ODT1
O
DDR0_RESET0_n
O
(1) DDRSS implements different signal functions on these signals based on the attached memory device type. The signals function as
Column Address Strobe, Row Address Strobe, Chip Select 0, and Chip Select 1 when DDRSS is configured to operate with DDR4
memory devices. The signals function as Chip Select 1B, Chip Select 0B, Chip Select 0A, and Chip Select 1A respectively when
DDRSS is configured to operate with LPDDR4 memory devices. For more information, refer to Section 9.2.1, DDR Board Design and
Layout Guidelines.
(2) An external 240 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
6.3.5 DSS
6.3.5.1 MAIN Domain
Table 6-9. DSS0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
U17
VOUT0_DE
O
I
Video Output Data Enable
VOUT0_EXTPCLKIN
VOUT0_HSYNC
VOUT0_PCLK
Video Output External Pixel Clock Input
Video Output Horizontal Sync
Video Output Pixel Clock Output
Video Output Vertical Sync
Video Output Data 0
R17
O
O
O
O
O
O
O
O
O
T18
AA22
V17
VOUT0_VSYNC
VOUT0_DATA0
VOUT0_DATA1
VOUT0_DATA2
VOUT0_DATA3
VOUT0_DATA4
VOUT0_DATA5
U22
Video Output Data 1
U21
Video Output Data 2
U20
Video Output Data 3
U19
Video Output Data 4
T19
Video Output Data 5
U18
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Table 6-9. DSS0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
V22
VOUT0_DATA6
VOUT0_DATA7
VOUT0_DATA8
VOUT0_DATA9
VOUT0_DATA10
VOUT0_DATA11
VOUT0_DATA12
VOUT0_DATA13
VOUT0_DATA14
VOUT0_DATA15
VOUT0_DATA16
VOUT0_DATA17
VOUT0_DATA18
VOUT0_DATA19
VOUT0_DATA20
VOUT0_DATA21
VOUT0_DATA22
VOUT0_DATA23
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Video Output Data 6
Video Output Data 7
Video Output Data 8
Video Output Data 9
Video Output Data 10
Video Output Data 11
Video Output Data 12
Video Output Data 13
Video Output Data 14
Video Output Data 15
Video Output Data 16
Video Output Data 17
Video Output Data 18
Video Output Data 19
Video Output Data 20
Video Output Data 21
Video Output Data 22
Video Output Data 23
V21
V19
V18
W22
W21
W20
W19
Y21
Y22
P22
R19
R20
R22
T22
R21
T20
T21
6.3.6 ECAP
6.3.6.1 MAIN Domain
Table 6-10. ECAP0 Signal Descriptions
SIGNAL NAME [1]
ECAP0_IN_APWM_OUT
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Ouput
IO
B16, C16
Table 6-11. ECAP1 Signal Descriptions
SIGNAL NAME [1]
ECAP1_IN_APWM_OUT
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Ouput
B18, C19, D17,
D21, E14
IO
Table 6-12. ECAP2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Ouput
A19, B19, B22,
D15, E16
ECAP2_IN_APWM_OUT
IO
6.3.7 Emulation and Debug
6.3.7.1 MAIN Domain
Table 6-13. Trace Signal Descriptions
SIGNAL NAME [1]
TRC_CLK
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
N21
O
O
O
O
O
O
Trace Clock
Trace Control
Trace Data 0
Trace Data 1
Trace Data 2
Trace Data 3
TRC_CTL
N20
TRC_DATA0
N19
TRC_DATA1
N18
TRC_DATA2
N17
TRC_DATA3
P18
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Table 6-13. Trace Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
TRC_DATA4
TRC_DATA5
TRC_DATA6
TRC_DATA7
TRC_DATA8
TRC_DATA9
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Trace Data 4
Trace Data 5
Trace Data 6
Trace Data 7
Trace Data 8
Trace Data 9
Trace Data 10
Trace Data 11
Trace Data 12
Trace Data 13
Trace Data 14
Trace Data 15
Trace Data 16
Trace Data 17
Trace Data 18
Trace Data 19
Trace Data 20
Trace Data 21
Trace Data 22
Trace Data 23
P19
P21
N22
L18
L17
K19
L19
M18
R18
K17
K18
M19
M21
M22
M20
T21
T20
R21
T22
R22
TRC_DATA10
TRC_DATA11
TRC_DATA12
TRC_DATA13
TRC_DATA14
TRC_DATA15
TRC_DATA16
TRC_DATA17
TRC_DATA18
TRC_DATA19
TRC_DATA20
TRC_DATA21
TRC_DATA22
TRC_DATA23
6.3.7.2 MCU Domain
Table 6-14. JTAG Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
C13
EMU0
EMU1
TCK
IO
Emulation Control 0
Emulation Control 1
JTAG Test Clock Input
JTAG Test Data Input
JTAG Test Data Output
JTAG Test Mode Select Input
JTAG Reset
IO
E10
I
A14
TDI
I
A16
TDO
OZ
C14
TMS
I
I
B14
TRSTn
F15
6.3.8 EPWM
6.3.8.1 MAIN Domain
Table 6-15. EPWM Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
D17
EHRPWM_SOCA
EHRPWM_SOCB
EHRPWM_TZn_IN0
EHRPWM_TZn_IN1
EHRPWM_TZn_IN2
EHRPWM_TZn_IN3
EHRPWM_TZn_IN4
EHRPWM_TZn_IN5
O
O
I
EHRPWM Start of Conversion A
EHRPWM Start of Conversion B
E16
EHRPWM Trip Zone Input 0 (active low)
EHRPWM Trip Zone Input 1 (active low)
EHRPWM Trip Zone Input 2 (active low)
EHRPWM Trip Zone Input 3 (active low)
EHRPWM Trip Zone Input 4 (active low)
EHRPWM Trip Zone Input 5 (active low)
E15
I
AA6
I
W7
I
B17
I
C18
I
C16
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Table 6-16. EPWM0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
B21, D16, Y8
A21, AA7, C16
AB8, C17
EHRPWM0_A
IO
IO
I
EHRPWM Output A
EHRPWM0_B
EHRPWM Output B
EHRPWM0_SYNCI
EHRPWM0_SYNCO
Sync Input to EHRPWM module from an external pin
Sync Input to EHRPWM module from an external pin
O
E17, W9
Table 6-17. EPWM1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
A17, B18, Y7
AB6, B15, B20
EHRPWM1_A
EHRPWM1_B
IO
IO
EHRPWM Output A
EHRPWM Output B
Table 6-18. EPWM2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
AB7, C17, E14
D15, E17, Y6
EHRPWM2_A
EHRPWM2_B
IO
IO
EHRPWM Output A
EHRPWM Output B
6.3.9 EQEP
6.3.9.1 MAIN Domain
Table 6-19. EQEP0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
C19
EQEP0_A (1)
EQEP0_B (1)
EQEP0_I (1)
EQEP0_S (1)
I
EQEP Quadrature Input A
EQEP Quadrature Input B
EQEP Index
I
B19
IO
IO
B20
EQEP Strobe
B18
(1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
Table 6-20. EQEP1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
A19
EQEP1_A (1)
EQEP1_B (1)
EQEP1_I (1)
EQEP1_S (1)
I
EQEP Quadrature Input A
I
EQEP Quadrature Input B
EQEP Index
A20
IO
IO
A21
EQEP Strobe
B21
(1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
Table 6-21. EQEP2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
AB21, D17
EQEP2_A (1)
EQEP2_B (1)
EQEP2_I (1)
EQEP2_S (1)
I
EQEP Quadrature Input A
I
EQEP Quadrature Input B
EQEP Index
AB20, E16
IO
IO
AA18, B17, R17
C18, K18, W17
EQEP Strobe
(1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
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6.3.10 GPIO
6.3.10.1 MAIN Domain
Table 6-22. GPIO0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
GPIO0_0
IO
General Purpose Input/Output
L22
K22
L21
J21
GPIO0_1
IO
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
GPIO0_2
IO
GPIO0_3
IO
GPIO0_4
IO
J18
GPIO0_5
IO
J19
GPIO0_6
IO
H18
K21
H19
J20
GPIO0_7
IO
GPIO0_8
IO
GPIO0_9
IO
GPIO0_10
GPIO0_11
GPIO0_12
GPIO0_13 (1)
GPIO0_14 (1)
GPIO0_15
GPIO0_16
GPIO0_17
GPIO0_18
GPIO0_19
GPIO0_20
GPIO0_21
GPIO0_22
GPIO0_23
GPIO0_24
GPIO0_25
GPIO0_26
GPIO0_27
GPIO0_28
GPIO0_29
GPIO0_30
GPIO0_31
GPIO0_32
GPIO0_33
GPIO0_34
GPIO0_35
GPIO0_36
GPIO0_37
GPIO0_38
GPIO0_39
GPIO0_40
GPIO0_41
GPIO0_42
IO
J22
IO
H21
G19
K20
G20
N21
N20
N19
N18
N17
P18
P19
P21
P22
R19
R20
R22
T22
R21
T20
T21
N22
L18
L17
K19
L19
M18
R18
R17
K17
K18
M19
M21
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
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Table 6-22. GPIO0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
M22
M20
U22
U21
U20
U19
T19
GPIO0_43 (1)
GPIO0_44 (1)
GPIO0_45
GPIO0_46
GPIO0_47
GPIO0_48
GPIO0_49
GPIO0_50
GPIO0_51
GPIO0_52
GPIO0_53
GPIO0_54
GPIO0_55
GPIO0_56
GPIO0_57
GPIO0_58
GPIO0_59
GPIO0_60
GPIO0_61
GPIO0_62
GPIO0_63
GPIO0_64
GPIO0_65 (1)
GPIO0_66 (1)
GPIO0_67 (1)
GPIO0_68 (1)
GPIO0_69 (1)
GPIO0_70 (1)
GPIO0_71 (1)
GPIO0_72 (1)
GPIO0_73
GPIO0_74
GPIO0_75
GPIO0_76
GPIO0_77
GPIO0_78
GPIO0_79
GPIO0_80
GPIO0_81
GPIO0_82
GPIO0_83
GPIO0_84
GPIO0_85
GPIO0_86
GPIO0_87
IO
General Purpose Input/Output
IO
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
IO
IO
IO
IO
IO
IO
U18
V22
IO
IO
V21
IO
V19
IO
V18
IO
W22
W21
W20
W19
Y21
IO
IO
IO
IO
IO
Y22
IO
T18
IO
U17
V17
IO
IO
AA22
G21
F20
IO
IO
IO
F21
IO
E20
IO
H22
G22
F22
IO
IO
IO
E21
IO
W16
AB17
Y17
IO
IO
IO
V16
IO
Y16
IO
AA17
AA15
AA16
AB16
V15
IO
IO
IO
IO
IO
W15
V14
IO
IO
V13
IO
V12
IO
Y19
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Table 6-22. GPIO0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
GPIO0_88
GPIO0_89
GPIO0_90
GPIO0_91
IO
IO
IO
IO
General Purpose Input/Output
AB19
AA19
Y18
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
AA18
(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
Table 6-23. GPIO1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
W17
W18
AA20
AA21
Y20
AB21
AB20
C19
B19
B18
B20
A19
A20
B21
A21
D16
C16
A17
B15
E15
E14
D15
F14
GPIO1_0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IOD
IO
IO
IO
IO
IO
General Purpose Input/Output
GPIO1_1
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
GPIO1_2
GPIO1_3
GPIO1_4
GPIO1_5
GPIO1_6
GPIO1_7
GPIO1_8
GPIO1_9
GPIO1_10
GPIO1_11
GPIO1_12
GPIO1_13
GPIO1_14
GPIO1_15
GPIO1_16 (1)
GPIO1_17
GPIO1_18
GPIO1_19
GPIO1_20
GPIO1_21
GPIO1_22
GPIO1_23
GPIO1_24
GPIO1_25
GPIO1_26
GPIO1_27
GPIO1_28
GPIO1_29
GPIO1_30
GPIO1_31 (1)
GPIO1_32 (1)
GPIO1_33 (1)
GPIO1_34 (1)
GPIO1_35 (1)
GPIO1_36 (1)
C15
B17
C18
D17
E16
C17
E17
B16
F17
AB8
W9
W7
Y8
AA7
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SPRSP77 – MARCH 2023
Table 6-23. GPIO1 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
Y7
GPIO1_37 (1)
GPIO1_38 (1)
GPIO1_39 (1)
GPIO1_40 (1)
GPIO1_41 (1)
GPIO1_42 (1)
GPIO1_43 (1)
GPIO1_44 (1)
GPIO1_45 (1)
GPIO1_46 (1)
GPIO1_47 (1)
GPIO1_48 (1)
GPIO1_49 (1)
GPIO1_50
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
AB6
AA6
AB7
Y6
D22
C22
D21
B22
E22
C21
E18
D18
C20
D19
GPIO1_51
(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
6.3.10.2 MCU Domain
Table 6-24. MCU_GPIO0 Signal Descriptions
SIGNAL NAME [1]
MCU_GPIO0_0 (1)
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
E11
C11
B13
A15
B12
D8
IO
IO
General Purpose Input/Output
MCU_GPIO0_1 (1)
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
MCU_GPIO0_2
IO
MCU_GPIO0_3
IO
MCU_GPIO0_4
IO
MCU_GPIO0_5
IO
MCU_GPIO0_6
IO
F8
MCU_GPIO0_7 (1)
MCU_GPIO0_8 (1)
MCU_GPIO0_9
IO
B11
D10
C9
IO
IO
MCU_GPIO0_10
MCU_GPIO0_11 (1)
MCU_GPIO0_12 (1)
MCU_GPIO0_13
MCU_GPIO0_14
MCU_GPIO0_15 (1)
MCU_GPIO0_16 (1)
MCU_GPIO0_17
MCU_GPIO0_18
MCU_GPIO0_19
MCU_GPIO0_20
MCU_GPIO0_21
MCU_GPIO0_22
IO
E9
IO
C10
C8
IO
IO
C7
IO
E8
IO
D7
IO
B9
IOD
IOD
IOD
IOD
IO
E12
D9
D13
E13
D14
D12
IO
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Table 6-24. MCU_GPIO0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
B10
MCU_GPIO0_23
IO
General Purpose Input/Output
(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
6.3.11 GPMC
6.3.11.1 MAIN Domain
Table 6-25. GPMC0 Signal Descriptions
SIGNAL NAME [1]
GPMC0_ADVn_ALE
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
GPMC Address Valid (active low) or Address Latch
Enable
O
L18
GPMC0_CLK
O
O
O
GPMC clock
N22
K18
N22
GPMC0_DIR
GPMC Data Bus Signal Direction Control
GPMC functional clock output
GPMC0_FCLK_MUX
GPMC Output Enable (active low) or Read Enable
(active low)
GPMC0_OEn_REn
O
L17
GPMC0_WEn
GPMC0_WPn
O
O
GPMC Write Enable (active low)
K19
K17
GPMC Flash Write Protect (active low)
GPMC Address 0 Output. Only used to effectively
address 8-bit data non-multiplexed memories
GPMC0_A0
GPMC0_A1
GPMC0_A2
GPMC0_A3
GPMC0_A4
GPMC0_A5
GPMC0_A6
GPMC0_A7
GPMC0_A8
GPMC0_A9
GPMC0_A10
GPMC0_A11
GPMC0_A12
GPMC0_A13
GPMC0_A14
GPMC0_A15
GPMC0_A16
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
U22
U21
U20
U19
T19
U18
V22
V21
V19
V18
W22
W21
W20
W19
Y21
Y22
T18
GPMC address 1 Output in A/D non-multiplexed mode
and Address 17 in A/D multiplexed mode
GPMC address 2 Output in A/D non-multiplexed mode
and Address 18 in A/D multiplexed mode
GPMC address 3 Output in A/D non-multiplexed mode
and Address 19 in A/D multiplexed mode
GPMC address 4 Output in A/D non-multiplexed mode
and Address 20 in A/D multiplexed mode
GPMC address 5 Output in A/D non-multiplexed mode
and Address 21 in A/D multiplexed mode
GPMC address 6 Output in A/D non-multiplexed mode
and Address 22 in A/D multiplexed mode
GPMC address 7 Output in A/D non-multiplexed mode
and Address 23 in A/D multiplexed mode
GPMC address 8 Output in A/D non-multiplexed mode
and Address 24 in A/D multiplexed mode
GPMC address 9 Output in A/D non-multiplexed mode
and Address 25 in A/D multiplexed mode
GPMC address 10 Output in A/D non-multiplexed
mode and Address 26 in A/D multiplexed mode
GPMC address 11 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
GPMC address 12 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
GPMC address 13 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
GPMC address 14 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
GPMC address 15 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
GPMC address 16 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
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Table 6-25. GPMC0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
GPMC address 17 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
GPMC0_A17
GPMC0_A18
GPMC0_A19
GPMC0_A20
GPMC0_A21
GPMC0_A22
OZ
U17
GPMC address 18 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
OZ
OZ
OZ
OZ
OZ
V17
AA22
M20
R17
GPMC address 19 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
GPMC address 20 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
GPMC address 21 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
GPMC address 22 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
K17
GPMC Data 0 Input/Output in A/D non-multiplexed
mode and additionally Address 1 Output in A/D
multiplexed mode
GPMC0_AD0
GPMC0_AD1
GPMC0_AD2
GPMC0_AD3
GPMC0_AD4
GPMC0_AD5
GPMC0_AD6
GPMC0_AD7
GPMC0_AD8
GPMC0_AD9
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
N21
N20
N19
N18
N17
P18
P19
P21
P22
R19
R20
R22
T22
R21
T20
GPMC Data 1 Input/Output in A/D non-multiplexed
mode and additionally Address 2 Output in A/D
multiplexed mode
GPMC Data 2 Input/Output in A/D non-multiplexed
mode and additionally Address 3 Output in A/D
multiplexed mode
GPMC Data 3 Input/Output in A/D non-multiplexed
mode and additionally Address 3 Output in A/D
multiplexed mode
GPMC Data 4 Input/Output in A/D non-multiplexed
mode and additionally Address 3 Output in A/D
multiplexed mode
GPMC Data 5 Input/Output in A/D non-multiplexed
mode and additionally Address 3 Output in A/D
multiplexed mode
GPMC Data 6 Input/Output in A/D non-multiplexed
mode and additionally Address 3 Output in A/D
multiplexed mode
GPMC Data 7 Input/Output in A/D non-multiplexed
mode and additionally Address 3 Output in A/D
multiplexed mode
GPMC Data 8 Input/Output in A/D non-multiplexed
mode and additionally Address 3 Output in A/D
multiplexed mode
GPMC Data 9 Input/Output in A/D non-multiplexed
mode and additionally Address 3 Output in A/D
multiplexed mode
GPMC Data 10 Input/Output in A/D non-multiplexed
mode and additionally Address 11 Output in A/D
multiplexed mode
GPMC0_AD10
GPMC0_AD11
GPMC0_AD12
GPMC0_AD13
GPMC Data 11 Input/Output in A/D non-multiplexed
mode and additionally Address 12 Output in A/D
multiplexed mode
GPMC Data 12 Input/Output in A/D non-multiplexed
mode and additionally Address 13 Output in A/D
multiplexed mode
GPMC Data 13 Input/Output in A/D non-multiplexed
mode and additionally Address 14 Output in A/D
multiplexed mode
GPMC Data 14 Input/Output in A/D non-multiplexed
mode and additionally Address 15 Output in A/D
multiplexed mode
GPMC0_AD14
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Table 6-25. GPMC0 Signal Descriptions (continued)
SIGNAL NAME [1]
GPMC0_AD15
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
GPMC Data 15 Input/Output in A/D non-multiplexed
mode and additionally Address 16 Output in A/D
multiplexed mode
IO
T21
L19
GPMC Lower-Byte Enable (active low) or Command
Latch Enable
GPMC0_BE0n_CLE
O
GPMC0_BE1n
GPMC0_CSn0
GPMC0_CSn1
GPMC0_CSn2
GPMC0_CSn3
GPMC0_WAIT0
GPMC0_WAIT1
O
O
O
O
O
I
GPMC Upper-Byte Enable (active low)
GPMC Chip Select 0 (active low)
GPMC Chip Select 1 (active low)
GPMC Chip Select 2 (active low)
GPMC Chip Select 3 (active low)
GPMC External Indication of Wait
GPMC External Indication of Wait
M18
M19
M21
M22
M20
R18
R17
I
6.3.12 I2C
6.3.12.1 MAIN Domain
Table 6-26. I2C0 Signal Descriptions
SIGNAL NAME [1]
I2C0_SCL
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
D17
IOD
I2C Clock
I2C Data
I2C0_SDA
IOD
E16
Table 6-27. I2C1 Signal Descriptions
SIGNAL NAME [1]
I2C1_SCL
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
C17
IOD
I2C Clock
I2C Data
I2C1_SDA
IOD
E17
Table 6-28. I2C2 Signal Descriptions
SIGNAL NAME [1]
I2C2_SCL
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
M22
IOD
I2C Clock
I2C Data
I2C2_SDA
IOD
M20
Table 6-29. I2C3 Signal Descriptions
SIGNAL NAME [1]
I2C3_SCL
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
AB7, F14
C15, Y6
IOD
I2C Clock
I2C Data
I2C3_SDA
IOD
6.3.12.2 MCU Domain
Table 6-30. MCU_I2C0 Signal Descriptions
SIGNAL NAME [1]
MCU_I2C0_SCL
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
IOD
I2C Clock
I2C Data
E12
D9
MCU_I2C0_SDA
IOD
6.3.12.3 WKUP Domain
Table 6-31. WKUP_I2C0 Signal Descriptions
SIGNAL NAME [1]
WKUP_I2C0_SCL
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
D13
IOD
I2C Clock
I2C Data
WKUP_I2C0_SDA
IOD
E13
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6.3.13 MCAN
6.3.13.1 MAIN Domain
Table 6-32. MCAN0 Signal Descriptions
SIGNAL NAME [1]
MCAN0_RX
PIN TYPE [2]
DESCRIPTION [3]
MCAN Receive Data
MCAN Transmit Data
AMB PIN [4]
C18
I
MCAN0_TX
O
B17
6.3.13.2 MCU Domain
Table 6-33. MCU_MCAN0 Signal Descriptions
SIGNAL NAME [1]
MCU_MCAN0_RX
PIN TYPE [2]
DESCRIPTION [3]
MCAN Receive Data
MCAN Transmit Data
AMB PIN [4]
I
E8
C7
MCU_MCAN0_TX
O
Table 6-34. MCU_MCAN1 Signal Descriptions
SIGNAL NAME [1]
MCU_MCAN1_RX
PIN TYPE [2]
DESCRIPTION [3]
MCAN Receive Data
MCAN Transmit Data
AMB PIN [4]
I
B9
D7
MCU_MCAN1_TX
O
6.3.14 MCASP
6.3.14.1 MAIN Domain
Table 6-35. MCASP0 Signal Descriptions
SIGNAL NAME [1]
MCASP0_ACLKR
MCASP0_ACLKX
MCASP0_AFSR
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
A21
IO
IO
IO
IO
IO
IO
IO
IO
MCASP Receive Bit Clock
MCASP Transmit Bit Clock
A19
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
B21
MCASP0_AFSX
A20
MCASP0_AXR0
B20
MCASP0_AXR1
B18
MCASP0_AXR2
B19
MCASP0_AXR3
C19
Table 6-36. MCASP1 Signal Descriptions
SIGNAL NAME [1]
MCASP1_ACLKR
MCASP1_ACLKX
MCASP1_AFSR
MCASP1_AFSX
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
G20, H22, M20
F22, J20, L19
G22, K20, M22
E21, J22, R18
E20, H19, K19
F21, K21, L17
F20, K20, L18
G20, G21, N22
G22, M22
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MCASP Receive Bit Clock
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP1_AXR0
MCASP1_AXR1
MCASP1_AXR2
MCASP1_AXR3
MCASP1_AXR4
MCASP1_AXR5
H22, M20
Table 6-37. MCASP2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
MCASP2_ACLKR
IO
MCASP Receive Bit Clock
T21, Y18
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Table 6-37. MCASP2 Signal Descriptions (continued)
SIGNAL NAME [1]
MCASP2_ACLKX
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MCASP Transmit Bit Clock
C15, R21, W17
T20, Y20
AA18, F14, T22
AB21, B17, P22
AA20, C18, R19
AA21, R20
R22, W18
N21, Y19
AB19, N20
AA19, N19
N18, Y20
N17, Y18
P18
MCASP2_AFSR
MCASP2_AFSX
MCASP2_AXR0
MCASP2_AXR1
MCASP2_AXR2
MCASP2_AXR3
MCASP2_AXR4
MCASP2_AXR5
MCASP2_AXR6
MCASP2_AXR7
MCASP2_AXR8
MCASP2_AXR9
MCASP2_AXR10
MCASP2_AXR11
MCASP2_AXR12
MCASP2_AXR13
MCASP2_AXR14
MCASP2_AXR15
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
P19
P21
M18
K18
M19
M21
6.3.15 MCSPI
6.3.15.1 MAIN Domain
Table 6-38. MCSPI0 Signal Descriptions
SIGNAL NAME [1]
SPI0_CLK
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
A17
IO
IO
IO
IO
IO
IO
IO
SPI Clock
SPI0_CS0
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
D16
SPI0_CS1
C16
SPI0_CS2
F14
SPI0_CS3
C15
SPI0_D0
B15
SPI0_D1
SPI Data 1
E15
Table 6-39. MCSPI1 Signal Descriptions
SIGNAL NAME [1]
SPI1_CLK
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
H19, Y7
AA7, K21
AB7, K20
Y6
IO
IO
IO
IO
IO
IO
IO
SPI Clock
SPI1_CS0
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI1_CS1
SPI1_CS2
SPI1_CS3
AB6
SPI1_D0
AB8, J20
J22, W9
SPI1_D1
SPI Data 1
Table 6-40. MCSPI2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
SPI2_CLK
IO
SPI Clock
A21, AA6, E17
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Table 6-40. MCSPI2 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
AB6, B21, D17
A19, AB8, C17
AA7, B18, E16
A20, B16, W9
C19, E14, W7
B19, D15, Y8
SPI2_CS0
SPI2_CS1
SPI2_CS2
SPI2_CS3
SPI2_D0
IO
IO
IO
IO
IO
IO
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI2_D1
SPI Data 1
6.3.15.2 MCU Domain
Table 6-41. MCU_MCSPI0 Signal Descriptions
SIGNAL NAME [1]
MCU_SPI0_CLK
MCU_SPI0_CS0
MCU_SPI0_CS1
MCU_SPI0_CS2
MCU_SPI0_CS3
MCU_SPI0_D0
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
B13
IO
IO
IO
IO
IO
IO
IO
SPI Clock
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
E11
C11
B9, C9
C7
A15
MCU_SPI0_D1
SPI Data 1
B12
Table 6-42. MCU_MCSPI1 Signal Descriptions
SIGNAL NAME [1]
MCU_SPI1_CLK
MCU_SPI1_CS0
MCU_SPI1_CS1
MCU_SPI1_CS2
MCU_SPI1_CS3
MCU_SPI1_D0
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
B9, C8
C10
IO
IO
IO
IO
IO
IO
IO
SPI Clock
SPI Chip Select 0
SPI Chip Select 2
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
D7
B9, E9
E8
B11
MCU_SPI1_D1
SPI Data 1
D10
6.3.16 MDIO
6.3.16.1 MAIN Domain
Table 6-43. MDIO0 Signal Descriptions
SIGNAL NAME [1]
MDIO0_MDC
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
V12
O
MDIO Clock
MDIO Data
MDIO0_MDIO
IO
V13
6.3.17 MMC
6.3.17.1 MAIN Domain
Table 6-44. MMC0 Signal Descriptions
SIGNAL NAME [1]
MMC0_CLK (1)
MMC0_CMD
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
AB7
IO
IO
IO
IO
IO
IO
MMC/SD/SDIO Clock
MMC/SD/SDIO Command
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
Y6
MMC0_DAT0
AA6
MMC0_DAT1
AB6
MMC0_DAT2
Y7
MMC0_DAT3
AA7
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Table 6-44. MMC0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
MMC0_DAT4
MMC0_DAT5
MMC0_DAT6
MMC0_DAT7
IO
IO
IO
IO
MMC/SD/SDIO Data
Y8
W7
W9
AB8
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
(1) For MMC0_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG135 register must remain in its default state
of 0x1 because of retiming purposes.
Table 6-45. MMC1 Signal Descriptions
SIGNAL NAME [1]
MMC1_CLK (1)
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
E22
IO
IO
I
MMC/SD/SDIO Clock
MMC1_CMD
MMC1_SDCD
MMC1_SDWP
MMC1_DAT0
MMC1_DAT1
MMC1_DAT2
MMC1_DAT3
MMC/SD/SDIO Command
SD Card Detect
C21
E18
I
SD Write Protect
D18
IO
IO
IO
IO
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
B22
D21
C22
D22
(1) For MMC1_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG142 register must remain in its default state
of 0x1 because of retiming purposes.
Table 6-46. MMC2 Signal Descriptions
SIGNAL NAME [1]
MMC2_CLK (1)
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
H22
IO
IO
I
MMC/SD/SDIO Clock
MMC2_CMD
MMC2_SDCD
MMC2_SDWP
MMC2_DAT0
MMC2_DAT1
MMC2_DAT2
MMC2_DAT3
MMC/SD/SDIO Command
SD Card Detect
G22
C17, F14, F22
C15, E17, E21
E20
I
SD Write Protect
IO
IO
IO
IO
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
F21
F20
G21
(1) For MMC2_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG71 register must remain in its default state
of 0x1 because of retiming purposes.
6.3.18 OSPI
6.3.18.1 MAIN Domain
Table 6-47. OSPI0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
L22
OSPI0_CLK
OSPI0_DQS
O
I
OSPI Clock
OSPI Data Strobe (DQS) or Loopback Clock Input
OSPI ECC Status
L21
OSPI0_ECC_FAIL
OSPI0_LBCLKO
OSPI0_CSn0
OSPI0_CSn1
OSPI0_CSn2
OSPI0_CSn3
OSPI0_D0
I
G20
IO
O
O
O
O
IO
IO
OSPI Loopback Clock Output
OSPI Chip Select 0 (active low)
OSPI Chip Select 1 (active low)
OSPI Chip Select 2 (active low)
OSPI Chip Select 3 (active low)
OSPI Data 0
K22
H21
G19
K20
G20
J21
OSPI0_D1
OSPI Data 1
J18
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Table 6-47. OSPI0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
J19
OSPI0_D2
OSPI0_D3
OSPI0_D4
OSPI0_D5
OSPI0_D6
OSPI0_D7
IO
IO
IO
IO
IO
IO
O
OSPI Data 2
OSPI Data 3
OSPI Data 4
OSPI Data 5
OSPI Data 6
OSPI Data 7
OSPI Reset
OSPI Reset
H18
K21
H19
J20
J22
OSPI0_RESET_OUT0
OSPI0_RESET_OUT1
G20
O
K20
6.3.19 Power Supply
Table 6-48. Power Supply Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
External capacitor connection for IO group 0
External capacitor connection for IO group 1
External capacitor connection for IO group 2
External capacitor connection for IO group 3
External capacitor connection for IO group 4
External capacitor connection for IO group 5
External capacitor connection for IO group 6
External capacitor connection for IO CANUART
External capacitor connection for IO MCU
USB 1.8 V analog supply
AMB PIN [4]
G13
K16
T14
M16
R8
CAP_VDDS0 (1)
CAP_VDDS1 (1)
CAP_VDDS2 (1)
CAP_VDDS3 (1)
CAP_VDDS4 (1)
CAP_VDDS5 (1)
CAP_VDDS6 (1)
CAP_VDDS_CANUART (1)
CAP_VDDS_MCU (1)
VDDA_1P8_USB
VDDA_1P8_CSIRX0
VDDA_3P3_USB
VDDA_CORE_CSIRX0
VDDA_CORE_USB
VDDA_DDR_PLL0
VDDA_MCU
CAP
CAP
CAP
CAP
CAP
CAP
G15
J16
CAP
CAP
G8
CAP
G10
T10
T12
U10
T11
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
CSIRX analog supply high
USB 3.3 V analog supply
CSIRX analog supply low
USB Core Supply
T9
DDR Deskew PLL analog supply
POR and MCU PLL analog supply
MAIN PLL analog supply
M9
J10
VDDA_PLL0
N9
VDDA_PLL1
PER0 PLL and PER1 PLL analog supply
VIDEO PLL analog supply
R11
M13
K13
K10
P16
G18
L10
VDDA_PLL2
VDDA_PLL3
C7x PLL and DSS PLL analog supply
ARM0 PLL and SMS PLL analog supply
TEMP0 analog supply
VDDA_PLL4
VDDA_TEMP0
VDDA_TEMP1
TEMP1 analog supply
VDDA_TEMP2
TEMP2 analog supply
J14, K12, M10,
M14, P12, P9
VDDR_CORE
PWR
Core Supply
VDDSHV0
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
IO supply for IO group 0
IO supply for IO group 1
IO supply for IO group 2
IO supply for IO group 3
IO supply for IO group 4
IO supply for IO group 5
IO supply for IO group 6
IO supply for IO CANUART
G14, H13
K15, L16
VDDSHV1
VDDSHV2
R13, T13, U13
L15, M15, N15
T8, U8
VDDSHV3
VDDSHV4
VDDSHV5
G16, H15
H16, H17
H8
VDDSHV6
VDDSHV_CANUART
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Table 6-48. Power Supply Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
VDDSHV_MCU
PWR
IO supply for IO MCU
G11, H10
A2, AA1, AB2,
B1, J7, K8, L7,
M8, N7, P8
VDDS_DDR
PWR
DDR PHY IO supply
VDDS_DDR_C
VDDS_OSC0
PWR
PWR
PWR
DDR clock IO supply
MCU_OSC0 supply
CANUART Core Supply
L8
J8
VDD_CANUART
H9
J11, J13, J15, J9,
K14, L11, L13,
L9, M12, N11,
N13, P10, P14,
R15, R9, T16,
U15
VDD_CORE
VPP
PWR
PWR
Core supply
eFuse ROM programming supply
F7
A1, A10, A13,
A18, A22, A4,
A6, AA11, AA14,
AA2, AA4, AA8,
AB1, AB12,
AB15, AB18,
AB22, AB3, AB5,
AB9, B3, B5, B7,
C4, D11, D2,
D20, D4, E1, E3,
E5, F11, F13,
F16, F2, F4,
G12, G17, G3,
G5, G9, H1, H11,
H14, H20, H4,
J12, J17, J3, K1,
K11, K4, K7, K9,
L12, L14, L20,
L3, M11, M17,
M4, M7, N1,
VSS
PWR
Ground
N10, N12, N14,
N16, N8, P11,
P13, P15, P17,
P20, P7, R10,
R12, R14, R16,
R2, R4, R6, T1,
T15, T17, T3, T5,
T7, U12, U14,
U16, U2, U4, U6,
U9, V1, V20, V3,
V5, V7, V9, W11,
W14, W2, W4,
W6, W8, Y12,
Y15, Y3, Y5, Y9
(1) This pin must always be connected via a 1-μF capacitor to VSS.
6.3.20 Reserved
Table 6-49. Reserved Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
N/A
Reserved, must be left unconnected
C6
D6
E7
N/A
N/A
N/A
N/A
Reserved, must be left unconnected
Reserved, must be left unconnected
Reserved, must be left unconnected
Reserved, must be left unconnected
F6
F10
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Table 6-49. Reserved Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
Reserved, must be left unconnected
Reserved, must be left unconnected
Reserved, must be left unconnected
AMB PIN [4]
RSVD5
RSVD6
RSVD7
N/A
N/A
N/A
G7
U11
V11
6.3.21 System and Miscellaneous
6.3.21.1 Boot Mode Configuration
6.3.21.1.1 MAIN Domain
Table 6-50. Sysboot Signal Descriptions
SIGNAL NAME [1]
BOOTMODE00
BOOTMODE01
BOOTMODE02
BOOTMODE03
BOOTMODE04
BOOTMODE05
BOOTMODE06
BOOTMODE07
BOOTMODE08
BOOTMODE09
BOOTMODE10
BOOTMODE11
BOOTMODE12
BOOTMODE13
BOOTMODE14
BOOTMODE15
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
N21
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Bootmode pin 0
Bootmode pin 1
Bootmode pin 2
Bootmode pin 3
Bootmode pin 4
Bootmode pin 5
Bootmode pin 6
Bootmode pin 7
Bootmode pin 8
Bootmode pin 9
Bootmode pin 10
Bootmode pin 11
Bootmode pin 12
Bootmode pin 13
Bootmode pin 14
Bootmode pin 15
N20
N19
N18
N17
P18
P19
P21
P22
R19
R20
R22
T22
R21
T20
T21
6.3.21.2 Clock
6.3.21.2.1 MCU Domain
Table 6-51. MCU Clock Signal Descriptions
SIGNAL NAME [1]
MCU_OSC0_XI
PIN TYPE [2]
DESCRIPTION [3]
High frequency oscillator input
High frequency oscillator output
AMB PIN [4]
A12
I
MCU_OSC0_XO
O
A11
6.3.21.2.2 WKUP Domain
Table 6-52. WKUP Clock Signal Descriptions
SIGNAL NAME [1]
WKUP_LFOSC0_XI
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
I
Low frequency (32.768 KHz) oscillator input
Low frequency (32.768 KHz) oscillator output
A8
A9
WKUP_LFOSC0_XO
O
6.3.21.3 System
6.3.21.3.1 MAIN Domain
Table 6-53. System Signal Descriptions
SIGNAL NAME [1]
AUDIO_EXT_REFCLK0
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
AB20, B20, F14
A20, C15, K17
IO
IO
External clock input to McASP or output from McASP
External clock input to McASP or output from McASP
AUDIO_EXT_REFCLK1
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Table 6-53. System Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
RMII Clock Output (50 MHz). This pin is used for clock
source to the external RMII PHY and must also be
routed back to the respective RMII[x]_REF_CLK pin
for proper device operation.
CLKOUT0
EXTINTn
O
AA17, B16, W17
I
I
External Interrupt
F17
B16
EXT_REFCLK1
OBSCLK0
External clock input to Main Domain
Main Domain Observation clock output for test and
debug purposes only
O
O
R20
D17
Main Domain Observation clock output for test and
debug purposes only
OBSCLK1
PORz_OUT
O
O
I
Main Domain POR status output
F18
F19
E19
RESETSTATz
RESET_REQz
Main Domain warm reset status output
Main Domain external warm reset request input
Main Domain system clock output (divided by 4) for
test and debug purposes only
SYSCLKOUT0
O
B16
6.3.21.3.2 MCU Domain
Table 6-54. MCU System Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
Error signal output from MCU Domain ESM
External input to MCU Domain
AMB PIN [4]
B8
MCU_ERRORn
IO
I
MCU_EXT_REFCLK0
C11, D7
MCU Domain Observation clock output for test and
debug purposes only
MCU_OBSCLK0
O
C11
MCU_PORz
I
O
I
MCU and Main Domain cold reset
MCU Domain warm reset status output
MCU and Main Domain warm reset
A7
MCU_RESETSTATz
MCU_RESETz
D14
C12
MCU Domain system clock output (divided by 4) for
test and debug purposes only
MCU_SYSCLKOUT0
O
C11
6.3.21.3.3 WKUP Domain
Table 6-55. WKUP System Signal Descriptions
SIGNAL NAME [1]
PMIC_LPM_EN0
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
D12
Dual-function PMIC control output, Low Power Mode
(active low) or PMIC Enable (active high)
O
O
WKUP_CLKOUT0
WKUP Domain CLKOUT0 output
B10
6.3.21.4 VMON
Table 6-56. VMON Signal Descriptions
SIGNAL NAME [1]
VMON_1P8_SOC
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
A
A
Voltage monitor input for 1.8 V SoC power supply
Voltage monitor input for 3.3 V SoC power supply
F12
F9
VMON_3P3_SOC
Voltage monitor input, fixed 0.45 V (+/-3%) threshold.
Use with external precision voltage divider to monitor a
higher voltage rail such as the PMIC input supply.
VMON_VSYS
A
H12
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6.3.22 TIMER
6.3.22.1 MAIN Domain
Table 6-57. TIMER Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO0
IO
C17, D22, Y7
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO1
TIMER_IO2
TIMER_IO3
TIMER_IO4
TIMER_IO5
TIMER_IO6
TIMER_IO7
IO
IO
IO
IO
IO
IO
IO
C22, E17
B17, D21
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
B22, C18
Timer Inputs and Outputs (not tied to single timer
instance)
AB7, B16, E22
C21, E16, Y6
E18, F14
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
C15, D18
6.3.22.2 MCU Domain
Table 6-58. MCU_TIMER Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
Timer Inputs and Outputs (not tied to single timer
instance)
MCU_TIMER_IO0
IO
B11, E8
Timer Inputs and Outputs (not tied to single timer
instance)
MCU_TIMER_IO1
MCU_TIMER_IO2
MCU_TIMER_IO3
IO
IO
IO
C11, D10
D7
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
B9
6.3.22.3 WKUP Domain
Table 6-59. WKUP_TIMER Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
Timer Inputs and Outputs (not tied to single timer
instance)
WKUP_TIMER_IO0
IO
C10, C7
Timer Inputs and Outputs (not tied to single timer
instance)
WKUP_TIMER_IO1
IO
C8, E11
6.3.23 UART
6.3.23.1 MAIN Domain
Table 6-60. UART0 Signal Descriptions
SIGNAL NAME [1]
UART0_CTSn
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
F14
I
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
UART0_RTSn
O
I
C15
UART0_RXD
E14
UART0_TXD
O
UART Transmit Data
D15
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Table 6-61. UART1 Signal Descriptions
SIGNAL NAME [1]
UART1_CTSn
PIN TYPE [2]
DESCRIPTION [3]
UART Clear to Send (active low)
UART Clear to Send (active low)
UART Data Set Ready (active low)
UART Data Terminal Ready (active low)
UART Ring Indicator
AMB PIN [4]
I
I
C19
D17
UART1_DCDn
UART1_DSRn
UART1_DTRn
UART1_RIn
I
E16
O
I
B17
C18
UART1_RTSn
UART1_RXD
UART1_TXD
O
I
UART Request to Send (active low)
UART Receive Data
B19
B21, C17
A21, E17
O
UART Transmit Data
Table 6-62. UART2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
AA22, B22, T20,
Y8
UART2_CTSn
UART2_RTSn
UART2_RXD
UART2_TXD
I
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
D21, T21, V17,
W7
O
I
AB8, D22, F14,
P22, U22
C15, C22, R19,
U21, W9
O
UART Transmit Data
Table 6-63. UART3 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
AA6, D18, U17
AB6, E18, T18
UART3_CTSn
UART3_RTSn
I
UART Clear to Send (active low)
UART Request to Send (active low)
O
AA7, E22, R20,
U20
UART3_RXD
UART3_TXD
I
UART Receive Data
UART Transmit Data
C21, R22, U19,
Y7
O
Table 6-64. UART4 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
Y22
UART4_CTSn
UART4_RTSn
I
UART Clear to Send (active low)
UART Request to Send (active low)
O
Y21
F22, M22, T19,
T22
UART4_RXD
UART4_TXD
I
UART Receive Data
UART Transmit Data
E21, M20, R21,
U18
O
Table 6-65. UART5 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
L21, W19
UART5_CTSn
UART5_RTSn
I
UART Clear to Send (active low)
UART Request to Send (active low)
O
K22, W20
B17, G21, K20,
T20, V22
UART5_RXD
UART5_TXD
I
UART Receive Data
UART Transmit Data
C18, F20, G20,
T21, V21
O
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Table 6-66. UART6 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
UART Clear to Send (active low)
UART Request to Send (active low)
AMB PIN [4]
J22, W21
UART6_CTSn
UART6_RTSn
I
O
J20, W22
C19, E18, H22,
K21, R17, V19
UART6_RXD
UART6_TXD
I
UART Receive Data
UART Transmit Data
B19, D18, G22,
H19, K17, V18
O
6.3.23.2 MCU Domain
Table 6-67. MCU_UART0 Signal Descriptions
SIGNAL NAME [1]
MCU_UART0_CTSn
MCU_UART0_RTSn
MCU_UART0_RXD
PIN TYPE [2]
DESCRIPTION [3]
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
AMB PIN [4]
I
B11
D10
D8
O
I
MCU_UART0_TXD
O
UART Transmit Data
F8
6.3.23.3 WKUP Domain
Table 6-68. WKUP_UART0 Signal Descriptions
SIGNAL NAME [1]
WKUP_UART0_CTSn
WKUP_UART0_RTSn
WKUP_UART0_RXD
PIN TYPE [2]
DESCRIPTION [3]
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
AMB PIN [4]
I
C10
C8
C9
E9
O
I
WKUP_UART0_TXD
O
UART Transmit Data
6.3.24 USB
6.3.24.1 MAIN Domain
Table 6-69. USB0 Signal Descriptions
SIGNAL NAME [1]
USB0_DM
PIN TYPE [2]
DESCRIPTION [3]
AMB PIN [4]
AA10
AA9
IO
IO
O
A
USB 2.0 Differential Data (negative)
USB 2.0 Differential Data (positive)
USB VBUS control output (active high)
Pin to connect to calibration resistor
USB Level-shifted VBUS Input
USB0_DP
USB0_DRVVBUS
USB0_RCALIB (1)
USB0_VBUS (2)
C20
W10
A
V8
(1) An external 499 Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is
7.2mW. No external voltage should be applied to this pin.
(2) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 9.2.3, USB
VBUS Design Guidelines.
Table 6-70. USB1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
USB 2.0 Differential Data (negative)
USB 2.0 Differential Data (positive)
USB VBUS control output (active high)
Pin to connect to calibration resistor
USB Level-shifted VBUS Input
AMB PIN [4]
USB1_DM
USB1_DP
IO
IO
O
A
Y11
Y10
D19
U7
USB1_DRVVBUS
USB1_RCALIB (1)
USB1_VBUS (2)
A
V6
(1) An external 499 Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is
7.2mW. No external voltage should be applied to this pin.
(2) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 9.2.3, USB
VBUS Design Guidelines.
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6.4 Pin Connectivity Requirements
This section describes connectivity requirements for package balls that have specific connectivity requirements
and package balls that may be unused.
Note
All power pins must be supplied with the voltages specified in Section 7.4, Recommended Operating
Conditions, unless otherwise specified.
Note
For additional clarification, "leave unconnected" means no signal traces connected to these ball
numbers.
Table 6-71. Connectivity Requirements
AMB
BALL
BALL NAME
CONNECTION REQUIREMENTS
NUMBER
Each of these balls must be connected to VSS through separate external pull
resistors to ensure they are held to a valid logic low level if a PCB signal
trace is connected and not actively driven by an attached device. The internal
pull-down may be used to hold a valid logic low level if no PCB signal trace is
connected to the ball.
B8
F15
MCU_ERRORn
TRSTn
C13
E10
C12
E19
A14
A16
B14
EMU0
EMU1
MCU_RESETz
RESET_REQz
TCK
Each of these balls must be connected to the corresponding power supply(1)
through separate external pull resistors to ensure these balls are held to a valid
logic high level if a PCB signal trace is connected and not actively driven by
an attached device. The internal pull-up may be used to hold a valid logic high
level if no PCB signal trace is connected to the ball.
TDI
TMS
E12
D9
D13
E13
MCU_I2C0_SCL
MCU_I2C0_SDA
WKUP_I2C0_SCL
WKUP_I2C0_SDA
Each of these balls must be connected to the corresponding power supply(1)
through separate external pull resistors to ensure these balls are held to a valid
logic high level.
N21
N20
N19
N18
N17
P18
P19
P21
P22
R19
R20
R22
T22
R21
T20
T21
GPMC0_AD0
GPMC0_AD1
GPMC0_AD2
GPMC0_AD3
GPMC0_AD4
GPMC0_AD5
GPMC0_AD6
GPMC0_AD7
GPMC0_AD8
GPMC0_AD9
GPMC0_AD10
GPMC0_AD11
GPMC0_AD12
GPMC0_AD13
GPMC0_AD14
GPMC0_AD15
Each of these balls must be connected to the corresponding power supply(1) or
VSS through separate external pull resistors to ensure these balls are held to
a valid logic high or low level as appropriate to select the desired device boot
mode.
A2
AA1
AB2
B1
J7
K8
L7
M8
N7
P8
L8
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR_C
If DDRSS is not used, each of these balls must be connected directly to VSS.
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Table 6-71. Connectivity Requirements (continued)
AMB
BALL
BALL NAME
CONNECTION REQUIREMENTS
NUMBER
N5
H7
M5
N2
M6
N6
J5
DDR0_ACT_n
DDR0_ALERT_n
DDR0_CAS_n
DDR0_PAR
DDR0_RAS_n
DDR0_WE_n
DDR0_A0
J2
DDR0_A1
J4
DDR0_A2
L4
DDR0_A3
J1
DDR0_A4
K5
K3
H2
L6
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
L2
DDR0_A9
K2
L5
DDR0_A10
DDR0_A11
M3
M2
K6
H3
P4
R7
H6
M1
L1
DDR0_A12
DDR0_A13
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
DDR0_CAL0
DDR0_CK0
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n
DDR0_CS1_n
DDR0_DM0
DDR0_DM1
DDR0_DM2
DDR0_DM3
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
P3
P5
J6
If DDRSS is not used, leave unconnected.
N4
C2
F3
U1
W3
A5
B4
B6
D5
C5
C3
B2
A3
E2
F5
E6
G2
G6
G4
E4
D3
T6
T4
U5
R5
P2
R3
T2
U3
Y2
V2
V4
W5
Y4
Note: The DDR0 pins in this list can only be left unconnected when
VDDS_DDR and VDDS_DDR_C are connected to VSS. The DDR0 pins must
be connected as defined in the DDR Board Design and Layout Guidelines,
when VDDS_DDR and VDDS_DDR_C are connected to a power source.
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Table 6-71. Connectivity Requirements (continued)
AMB
BALL
BALL NAME
CONNECTION REQUIREMENTS
NUMBER
AA3
AA5
AB4
D1
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
DDR0_DQS0
C1
G1
F1
DDR0_DQS0_n
DDR0_DQS1
DDR0_DQS1_n
DDR0_DQS2
R1
P1
W1
Y1
DDR0_DQS2_n
DDR0_DQS2
DDR0_DQS2_n
DDR0_ODT0
H5
N3
DDR0_ODT1
P6
DDR0_RESET0_n
USB0 and USB1 share these power rails, so each of these balls must be
connected to valid power sources when either USB0 or USB1 is used.
T9
T10
U10
VDDA_CORE_USB
VDDA_1P8_USB
VDDA_3P3_USB
If USB0 and USB1 are not used, each of these balls must be connected
directly to VSS.
If USB0 or USB1 is not used, leave the respective DM, DP, and VBUS balls
unconnected.
AA10
AA9
W10
V8
Y11
Y10
U7
USB0_DM
USB0_DP
USB0_RCALIB
USB0_VBUS
USB1_DM
USB1_DP
USB1_RCALIB
USB1_VBUS
Note: The USB0_RCALIB and USB1_RCALIB pins can only be
left unconnected when VDDA_CORE_USB, VDDA_1P8_USB, and
VDDA_3P3_USB are connected to VSS. The USB0_RCALIB and
USB1_RCALIB pins must be connected to VSS through separate
appropriate external resistors when VDDA_CORE_USB, VDDA_1P8_USB,
and VDDA_3P3_USB are connected to power sources.
V6
If CSIRX0 is not used and the device boundary scan function is required, each
of these balls must be connected to valid power sources.
T11
T12
VDDA_CORE_CSIRX0
VDDA_1P8_CSIRX0
If CSIRX0 is not used and the device boundary scan function is not required,
each of these balls may alternatively be connected directly to VSS.
AB14
AB13
W12
W13
Y13
CSI0_RXCLKN
CSI0_RXCLKP
CSI0_RXN0
CSI0_RXP0
CSI0_RXN1
CSI0_RXP1
CSI0_RXN2
CSI0_RXP2
CSI0_RXN3
CSI0_RXP3
CSI0_RXRCALIB
Y14
If CSIRX0 is not used, leave unconnected.
AA13
AA12
AB11
AB10
V10
H12
VMON_VSYS
If VMON_VSYS is not used, this ball must be connected directly to VSS.
If VMON_1P8_SOC and VMON_3P3_SOC are not used to monitor the SOC
power rails, these balls must still be connected to their respective 1.8V and
3.3V power rails.
F12
F9
VMON_1P8_SOC
VMON_3P3_SOC
(1) To determine which power supply is associated with any IO, see POWER column of the Pin Attributes table.
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Note
Internal pull resistors are weak and may not source enough current to maintain a valid logic level for
some operating conditions. This may be the case when connected to components with leakage to the
opposite logic level, or when external noise sources couple to signal traces attached to balls which
are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be
required to hold a valid logic level on balls with external connections.
If balls are allowed to float between valid logic levels, the input buffer may enter a high-current state
which could damage the IO cell.
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7 Specifications
Note
All specifications listed are preliminary and may change during device characterization.
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1) (2)
PARAMETER
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
MAX UNIT
VDD_CORE
Core supply
1.05
1.05
1.05
1.05
1.05
1.05
1.57
1.57
1.98
1.98
1.98
1.98
2.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDDR_CORE
VDD_CANUART
VDDA_CORE_CSIRX0
VDDA_CORE_USB
VDDA_DDR_PLL0
VDDS_DDR
RAM supply
CANUART core supply
CSIRX0 core supply
USB0 and USB1 core supply
DDR Deskew PLL supply
DDR PHY IO supply
VDDS_DDR_C
VDDS_OSC0
VDDA_MCU
DDR clock IO supply
MCU_OSC0 supply
RCOSC, POR, POK, and MCU PLL analog supply
MAIN PLL and VIDEO PLL analog supply
PER0 PLL and PER1 PLL analog supply
C7x PLL and DSS PLL analog supply
ARM0 PLL and SMS PLL analog supply
DDR PLL analog supply
VDDA_PLL0
VDDA_PLL1
VDDA_PLL2
VDDA_PLL3
1.98
1.98
1.98
1.98
1.98
2.2
VDDA_PLL4
VDDA_1P8_CSIRX0
VDDA_1P8_USB
VDDA_TEMP0
VDDA_TEMP1
VDDA_TEMP2
VPP
CSIRX0 1.8 V analog supply
USB0 and USB1 1.8 V analog supply
TEMP0 analog supply
TEMP1 analog supply
TEMP2 analog supply
1.98
1.98
3.63
3.63
3.63
3.63
3.63
3.63
3.63
3.63
3.63
3.63
eFuse ROM programming supply
IO supply for IO MCU
VDDSHV_MCU
VDDSHV_CANUART
VDDSHV0
IO supply for IO CANUART
IO supply for IO group 0
VDDSHV1
IO supply for IO group 1
VDDSHV2
IO supply for IO group 2
VDDSHV3
IO supply for IO group 3
VDDSHV4
IO supply for IO group 4
VDDSHV5
IO supply for IO group 5
VDDSHV6
IO supply for IO group 6
VDDA_3P3_USB
USB0 and USB1 3.3 V analog supply
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over operating junction temperature range (unless otherwise noted)(1) (2)
PARAMETER
MIN
MAX UNIT
MCU_PORz
-0.3
3.63
V
MCU_I2C0_SCL, MCU_I2C0_SDA,
WKUP_I2C0_SCL, WKUP_I2C0_SDA,
EXTINTn
When operating at 1.8V
-0.3
-0.3
1.98(3)
V
MCU_I2C0_SCL, MCU_I2C0_SDA,
WKUP_I2C0_SCL, WKUP_I2C0_SDA,
EXTINTn
Steady-state max voltage at all fail-safe IO pins
3.63(3)
When operating at 3.3V
VMON_1P8_SOC
-0.3
-0.3
-0.3
-0.3
1.98
3.63
1.98
3.6
V
V
V
V
VMON_3P3_SOC
VMON_VSYS(4)
USB0_VBUS, USB1_VBUS(6)
Steady-state max voltage at all other IO pins(5)
IO supply
voltage + 0.3
All other IO pins
-0.3
V
V
20% of IO supply voltage for up to 20%
of the signal period (see Figure 7-1, IO
Transient Voltage Ranges)
Transient overshoot and undershoot at IO pin
Latch-up performance(8)
0.2 × VDD(7)
I-Test
-100
-55
100
1.5 x VDD(7)
+150
mA
V
Over-Voltage (OV) Test
TSTG
Storage temperature
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Section 7.4, Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be
fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) The absolute maximum ratings for these fail-safe pins depends on their IO supply operating voltage. Therefore, this value is also
defined by the maximum VIH value found in the I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics section, where
the electrical characteristics table has separate parameter values for 1.8-V mode and 3.3-V mode.
(4) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see Section 9.2.4, System Power
Supply Monitor Design Guidelines.
(5) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be
–0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used
to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range,
including power supply ramp-up and ramp-down sequences.
(6) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.2.3, USB
Design Guidelines.
(7) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(8) For current pulse injection (I-Test):
•
Pins stressed per JEDEC JESD78 (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times
maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.
For over-voltage performance (Over-Voltage (OV) Test):
Supplies stressed per JEDEC JESD78 (Class II) and passed specified voltage injection.
•
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply
voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO
power supplies are turned off. The MCU_I2C0_SCL, MCU_I2C0_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA,
EXTINTn, VMON_1P8_SOC, VMON_3P3_SOC, and MCU_PORz are the only fail-safe IO terminals. All other IO
terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the Steady
State Max. Voltage at all IO pins parameter in Section 7.1.
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Overshoot = 20% of nominal
IO supply voltage
Tovershoot
Tperiod
Tundershoot
Undershoot = 20% of nominal
IO supply voltage
A. Tovershoot + Tundershoot < 20% of Tperiod
Figure 7-1. IO Transient Voltage Ranges
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
±1000
Corner pins
V(ESD)
Electrostatic discharge
(A1, A22, AB1, and
AB22)
±750
±250
V
Charged-device model (CDM), per AEC Q100-011
All other pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Power-On Hours (POH)
POWER ON HOURS (POH)(1) (2) (3)
JUNCTION TEMPERATURE RANGE
LIFETIME (POH)
100000
Commercial
0°C to 95°C
-40°C to 105°C
-40°C to 125°C
Extended Industrial
Automotive
100000
20000(4)
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard
terms and conditions for TI semiconductor products.
(2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted
temperatures.
(3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH.
(4) Automotive profile is defined as 20000 power on hours with a junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,
and 10%@125°C.
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7.4 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
MIN(1)
NOM MAX(1) UNIT
VDD_CORE(2)
Core supply
CSIRX0 core supply
USB0 and USB1 core supply
DDR Deskew PLL supply
0.75-V operation
0.85-V operation
0.715
0.75
0.79
V
VDDA_CORE_CSIRX0(2)
VDDA_CORE_USB(2)
VDDA_DDR_PLL0(2)
0.81
0.85
0.895
V
0.75-V operation
0.85-V operation
0.715
0.81
0.81
1.06
1.14
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
see(7)
1.71
3.135
3.135
0
0.75
0.85
0.85
1.1
0.79
0.895
0.895
1.17
1.26
1.89
1.89
1.89
1.89
1.89
1.89
1.89
1.89
1.89
1.89
1.89
1.89
see(7)
1.89
3.465
3.465
1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD_CANUART(3)
CANUART core supply
RAM supply
VDDR_CORE
VDDS_DDR(4)
DDR PHY IO supply
DDR clock IO supply
1.1-V operation
1.2-V operation
VDDS_DDR_C(4)
1.2
VDDS_OSC0
VDDA_MCU
MCU_OSC0 supply
1.8
RCOSC, POR, POK, and MCU PLL analog supply
MAIN PLL and VIDEO PLL analog supply
PER0 PLL and PER1 PLL analog supply
C7x PLL and DSS PLL analog supply
ARM0 PLL and SMS PLL analog supply
DDR PLL analog supply
1.8
VDDA_PLL0
1.8
VDDA_PLL1
1.8
VDDA_PLL2
1.8
VDDA_PLL3
1.8
VDDA_PLL4
1.8
VDDA_1P8_CSIRX0
VDDA_1P8_USB
VDDA_TEMP0
VDDA_TEMP1
VDDA_TEMP2
VPP
CSIRX0 1.8 V analog supply
1.8
USB0 and USB1 1.8 V analog supply
TEMP0 analog supply
1.8
1.8
TEMP1 analog supply
1.8
TEMP2 analog supply
1.8
eFuse ROM programming supply
Voltage monitor for 1.8 V SoC power supply
USB0 and USB1 3.3 V analog supply
Voltage monitor for 3.3 V SoC power supply
Voltage monitor pin
see(7)
VMON_1P8_SOC
VDDA_3P3_USB
VMON_3P3_SOC
VMON_VSYS
USB0_VBUS
USB1_VBUS
1.8
3.3
3.3
see(5)
see(6)
see(6)
1.8
USB0 Level-shifted VBUS Input
USB1 Level-shifted VBUS Input
0
3.465
3.465
1.89
3.465
1.89
3.465
1.89
3.465
1.89
3.465
1.89
3.465
1.89
3.465
1.89
3.465
1.89
3.465
0
1.8-V operation
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
VDDSHV_CANUART(3)
VDDSHV_MCU
VDDSHV0
Dual-voltage IO supply
Dual-voltage IO supply
Dual-voltage IO supply
Dual-voltage IO supply
Dual-voltage IO supply
Dual-voltage IO supply
Dual-voltage IO supply
Dual-voltage IO supply
3.3-V operation
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
3.3
1.8
3.3
1.8
3.3
1.8
VDDSHV1
3.3
1.8
VDDSHV2
3.3
1.8
VDDSHV3
3.3
1.8
VDDSHV4
3.3
1.8
VDDSHV5
3.3
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over operating junction temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
MIN(1)
1.71
3.135
-40
NOM MAX(1) UNIT
1.8-V operation
3.3-V operation
Automotive
1.8
3.3
1.89
3.465
125
V
V
VDDSHV6
Dual-voltage IO supply
°C
°C
TJ
Operating junction temperature range
Extended Industrial
-40
105
(1) The voltage at the device ball must never drop below the MIN voltage or rise above the MAX voltage for any amount of time during
normal device operation.
(2) VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 shall be sourced from the same power source.
Care should be taken to ensure that voltage differential between VDD_CORE and VDDA_CORE_USB is within +/- 1%.
(3) VDD_CANUART and VDDSHV_CANUART shall be connected to always on power sources when using Partial IO low power mode.
VDD_CANUART shall be connected to the same power source as VDD_CORE and VDDSHV_CANUART shall be connected to any
valid IO power source when not using Partial IO low power mode.
(4) VDDS_DDR and VDDS_DDR_C shall be sourced from the same power source.
(5) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see Section 9.2.4, System Power
Supply Monitor Design Guidelines.
(6) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.2.3, USB
Design Guidelines.
(7) Refer to the Recommended Operating Conditions for OTP eFuse Programming table for VPP supply voltages based on eFuse usage.
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7.5 Operating Performance Points
Table 7-1 defines the maximum operating frequency of the clocks for each device speed grade and Table 7-2
defines the only valid Operating Performance Points (OPPs) for the device subsystem and core clocks.
Table 7-1. Device Speed Grades
MAXIMUM
TRANSITION
MAXIMUM OPERATING FREQUENCY (MHz)
RATE (MT/s)
(2)
Speed
Grade
VDD_CORE
(V)(1)
DEVICE
MANAGER
R5F
MCU
R5F
/
A53SS
(Cortex-
A53x)
VENC
/
VDEC
MAIN
SYSCLK
C7x
HSM
VPAC
MJPEG
LPDDR4
/
SYSCLK
CLK
800
/
400
800
/
400
M
N
O
P
Q
R
S
T
0.75/0.85
800
800
500
500
500
500
500
500
500
500
500
500
500
400
400
400
400
400
400
400
400
400
400
375
375
375
375
375
375
375
375
375
375
400
400
400
400
400
400
400
400
400
400
250
250
250
250
250
250
250
250
250
250
3200
3200
3200
3733
3200
3733
3200
3733
3200
3733
0.75
0.85
850
800
/
400
800
/
400
1000
800
/
400
800
/
400
0.75/0.85
0.75/0.85
1000
1000
1000
1000
500
500
800
/
400
800
/
400
0.75
0.85
0.75
0.85
0.75
0.85
0.75
0.85
0.75
0.85
0.75
0.85
850
1000
850
800
/
400
800
/
400
800
/
400
800
/
400
1000
1250
1400
1250
1400
1250
1400
1250
1400
800
/
400
800
/
400
500
500
800
/
400
800
/
400
850
1000
850
800
/
400
800
/
400
U
V
800
/
400
800
/
400
1000
(1) Nominal operating voltage, see Recommended Operating Conditions.
(2) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.
Refer to DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency.
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Table 7-2. Device Operating Performance Points
FIXED OPERATING FREQUENCY OPTIONS (MHz)(2)
MT/s(3)
DEVICE
MANAGER
MCU
R5F
/
A53SS(1)
C7x
VENC
/
VDEC
OPP
MAIN
SYSCLK
R5F
/
CLK
HSM
VPAC
MJPEG
LPDDR4
SYSCLK
ꢀ
From
ARM0
PLL
Bypass
to
Speed
Grade
Maximum
From
C7x
PLL
Bypass
to
Speed
Grade
Maximum
800
/
400
800
/
400
From
DDR
High
ꢀ
500
250
400
133
400,
200,
or
PLL
187.5,
or
375
Bypass(4)
to
250
400
/
200
400
/
133
100
Speed
Grade
Maximum
Low
(1) Default operating frequency, set by software at boot. Supports Dynamic Frequency Scaling after boot.
(2) Fixed operating frequency, set by software at boot.
(3) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.
Refer to DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency.
(4) The DDR PLL output, which sources DDR0_CK0 and DDR0_CK0_n, is typically defined in units of frequency. So the "DDR PLL
Bypass" transaction rate is equal to 2x the DDR PLL output frequency when operating in bypass mode.
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SPRSP77 – MARCH 2023
7.6 Electrical Characteristics
Note
The interfaces or signals described in Section 7.6 correspond to the interfaces or signals available in
multiplexing mode 0 (Primary Signal Function).
All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical
characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC
electrical characteristics are specified for the different multiplexing modes (Functions).
7.6.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.8 V MODE
VIL
Input Low Voltage
0.3 × VDD(1)
0.3 × VDD(1)
V
V
VILSS
Input Low Voltage Steady State
Input High Voltage
VIH
0.7 × VDD(1)
0.7 × VDD(1)
0.1 × VDD(1)
1.98(2)
V
VIHSS
VHYS
Input High Voltage Steady State
Input Hysteresis Voltage
V
mV
VI = 1.8 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0 V
VOL
Output Low Voltage
0.2 × VDD(1)
V
(3)
IOL
Low Level Output Current
VOL(MAX)
10
mA
18f(4)
or
(5)
SRI
Input Slew Rate
V/s
1.8E+6
3.3 V MODE (6)
VIL
Input Low Voltage
0.3 × VDD(1)
0.25 × VDD(1)
3.63(2)
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.7 × VDD(1)
0.7 × VDD(1)
0.05 × VDD(1)
V
VIHSS
VHYS
Input High Voltage Steady State
Input Hysteresis Voltage
V
mV
VI = 3.3 V
or
VI = 0 V
IIN
Input Leakage Current.
±10
0.4
µA
VOL
Output Low Voltage
V
(3)
IOL
Low Level Output Current
VOL(MAX)
10
mA
33f(4)
or
(5)
SRI
Input Slew Rate
8E+7
V/s
3.3E+6
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
(2) This value also defines the Absolute Maximum Ratings value the IO.
(3) The IOL parameter defines the minimum Low Level Output Current for which the device is able to maintain the specified VOL value.
The value defined by this parameter should be considered the maximum current available to a system implementation which needs to
maintain the specified VOL value for attached components.
(4) f = toggle frequency of the input signal in Hz.
(5) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
(6) I2C Hs-mode is not supported when operating the IO in 3.3 V mode.
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7.6.2 Fail-Safe Reset (FS RESET) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.3 ×
VDDS_OSC0
VIL
Input Low Voltage
V
0.3 ×
VDDS_OSC0
VILSS
VIH
VIHSS
VHYS
Input Low Voltage Steady State
Input High Voltage
V
V
0.7 ×
VDDS_OSC0
0.7 ×
VDDS_OSC0
Input High Voltage Steady State
Input Hysteresis Voltage
V
200
mV
VI = 1.8 V
or
VI = 0 V
IIN
Input Leakage Current.
Input Slew Rate
±10
µA
18f(1)
or
(2)
SRI
V/s
1.8E+6
(1) f = toggle frequency of the input signal in Hz.
(2) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
7.6.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.35 ×
VDDS_OSC0
VIL
Input Low Voltage
V
0.65 ×
VDDS_OSC0
VIH
Input High Voltage
V
VHYS
Input Hysteresis Voltage
49
mV
VI = 1.8 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0.0 V
7.6.4 Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.30 ×
VDDS_OSC0
VIL
VIH
Input Low Voltage
V
0.70 ×
VDDS_OSC0
Input High Voltage
V
Active Mode
85
mV
mV
VHYS
Input Hysteresis Voltage
Bypass Mode
324
VI = 1.8 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0.0 V
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SPRSP77 – MARCH 2023
7.6.5 SDIO Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.8 V MODE
VIL
Input Low Voltage
0.58
0.58
V
V
VILSS
Input Low Voltage Steady State
Input High Voltage
VIH
1.27
1.7
V
VIHSS
VHYS
Input High Voltage Steady State
Input Hysteresis Voltage
V
150
mV
VI = 1.8 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0 V
RPU
RPD
VOL
Pull-up Resistor
40
40
50
50
60
60
kΩ
kΩ
V
Pull-down Resistor
Output Low Voltage
0.45
VDDSHV5 -
0.45
VOH
Output High Voltage
V
(1)
IOL
Low Level Output Current
High Level Output Current
VOL(MAX)
VOH(MIN)
4
4
mA
mA
(1)
IOH
18f(2)
or
(3)
SRI
Input Slew Rate
V/s
1.8E+6
3.3 V MODE
0.25 ×
VDDSHV5
VIL
Input Low Voltage
V
V
V
0.15 ×
VDDSHV5
VILSS
VIH
VIHSS
VHYS
Input Low Voltage Steady State
Input High Voltage
0.625 ×
VDDSHV5
0.625 ×
VDDSHV5
Input High Voltage Steady State
Input Hysteresis Voltage
V
150
mV
VI = 3.3 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0 V
RPU
RPD
Pull-up Resistor
40
40
50
50
60
60
kΩ
kΩ
Pull-down Resistor
0.125 ×
VDDSHV5
VOL
VOH
Output Low Voltage
Output High Voltage
V
V
0.75 ×
VDDSHV5
(1)
IOL
Low Level Output Current
High Level Output Current
VOL(MAX)
VOH(MIN)
6
mA
mA
(1)
IOH
10
33f(2)
or
(3)
SRI
Input Slew Rate
V/s
3.3E+6
(1) The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is
able to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current
available to a system implementation which needs to maintain the specified VOL and VOH values for attached components.
(2) f = toggle frequency of the input signal in Hz.
(3) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
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SPRSP77 – MARCH 2023
7.6.6 LVCMOS Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.8-V MODE
VIL
Input Low Voltage
0.35 × VDD(1)
0.3 × VDD(1)
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.65 × VDD(1)
0.85 × VDD(1)
150
V
VIHSS
VHYS
Input High Voltage Steady State
Input Hysteresis Voltage
V
mV
VI = 1.8 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0.0 V
RPU
RPD
VOL
VOH
Pull-up Resistor
15
15
22
22
30
30
kΩ
kΩ
V
Pull-down Resistor
Output Low Voltage
Output High Voltage
Low Level Output Current
High Level Output Current
0.45
VDD(1) - 0.45
V
(2)
IOL
VOL(MAX)
VOH(MIN)
3
3
mA
mA
(2)
IOH
18f(3)
or
(4)
SRI
Input Slew Rate
V/s
1.8E+6
3.3-V MODE
VIL
Input Low Voltage
0.8
0.6
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
2.0
2.0
V
VIHSS
VHYS
Input High Voltage Steady State
Input Hysteresis Voltage
V
150
mV
VI = 3.3 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0.0 V
RPU
RPD
VOL
VOH
Pull-up Resistor
15
15
22
22
30
30
kΩ
kΩ
V
Pull-down Resistor
Output Low Voltage
Output High Voltage
Low Level Output Current
High Level Output Current
0.4
2.4
5
V
(2)
IOL
VOL(MAX)
VOH(MIN)
mA
mA
(2)
IOH
9
33f(3)
or
(4)
SRI
Input Slew Rate
V/s
3.3E+6
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
(2) The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is
able to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current
available to a system implementation which needs to maintain the specified VOL and VOH values for attached components.
(3) f = toggle frequency of the input signal in Hz.
(4) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
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7.6.7 CSI-2 (D-PHY) Electrical Characteristics
Note
CSIRX0 is compliant with MIPI DPHY v1.2 dated August 1, 2014 including ECNs and Errata as
applicable
7.6.8 USB2PHY Electrical Characteristics
Note
The USB0 and USB1 interfaces are compliant with Universal Serial Bus Revision 2.0 Specification
dated April 27, 2000 including ECNs and Errata as applicable.
7.6.9 DDR Electrical Characteristics
Note
The DDR interface is compatible with LPDDR4 devices
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7.7 VPP Specifications for One-Time Programmable (OTP) eFuses
This section specifies the operating conditions required for programming the OTP eFuses .
7.7.1 Recommended Operating Conditions for OTP eFuse Programming
over operating junction temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN
NOM
MAX
UNIT
VDD_CORE
Supply voltage range for the core domain during OTP
operation; OPP NOM (BOOT)
See Section 7.4
V
VPP
Supply voltage range for the eFuse ROM domain during
normal operation without hardware support to program
eFuse ROM
NC(1)
V
V
V
Supply voltage range for the eFuse ROM domain during
normal operation with hardware support to program eFuse
ROM
0
Supply voltage range for the eFuse ROM domain during
OTP programming(2)
1.71
1.8
1.89
I(VPP)
SR(VPP)
Tj
VPP current
400
6E + 4
85
mA
V/s
°C
VPP Slew Rate
Operating junction temperature range while programming
eFuse ROM.
0
25
(1) NC indicates No Connect.
(2) Supply voltage range includes DC errors and peak-to-peak noise.
7.7.2 Hardware Requirements
The following hardware requirements must be met when programming keys in the OTP eFuses:
•
•
The VPP power supply must be disabled when not programming OTP registers.
The VPP power supply must be ramped up after the proper device power-up sequence (for more details, see
Section 7.9.2.2, Power Supply Sequencing).
7.7.3 Programming Sequence
Programming sequence for OTP eFuses:
•
Power on the board per the power-up sequencing. No voltage should be applied on the VPP terminal during
power up and normal operation.
•
Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP
software package).
•
•
•
Apply the voltage on the VPP terminal according to the specification in Section 7.7.1.
Run the software that programs the OTP registers.
After validating the content of the OTP registers, remove the voltage from the VPP terminal.
7.7.4 Impact to Your Hardware Warranty
You accept that e-Fusing the TI Devices with security keys permanently alters them. You acknowledge that
the e-Fuse can fail, for example, due to incorrect or aborted program sequence or if you omit a sequence
step. Further the TI Device may fail to secure boot if the error code correction check fails for the Production
Keys or if the image is not signed and optionally encrypted with the current active Production Keys. These
types of situations will render the TI Device inoperable and TI will be unable to confirm whether the TI Devices
conformed to their specifications prior to the attempted e-Fuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY
(WARRANTY OR OTHERWISE) FOR ANY TI DEVICES THAT HAVE BEEN e-FUSED WITH SECURITY KEYS.
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7.8 Thermal Resistance Characteristics
This section provides the thermal resistance characteristics used on this device.
For reliability and operability concerns, the maximum junction temperature of the device has to be at or below
the TJ value identified in Section 7.4, Recommended Operating Conditions.
7.8.1 Thermal Resistance Characteristics for AMB Package
It is recommended to perform thermal simulations at the system level with the worst case device power consumption.
AMB PACKAGE
NO.
PARAMETER
DESCRIPTION
AIR FLOW
(m/s)(2)
°C/W(1) (3)
T1
RΘJC
Junction-to-case
Junction-to-board
Junction-to-free air
0.77
3.3
N/A
N/A
0
T2
RΘJB
T3
12.5
8.6
T4
1
RΘJA
T5
Junction-to-moving air
7.6
2
T6
7.0
3
T7
0.39
0.41
0.42
0.43
3.1
0
T8
1
ΨJT
Junction-to-package top
T9
2
T10
T11
T12
T13
T14
3
0
2.8
1
ΨJB
Junction-to-board
2.7
2
2.6
3
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second.
(3) °C/W = degrees Celsius per watt.
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7.9 Timing and Switching Characteristics
Note
The Timing Requirements and Switching Characteristics values may change following the silicon
characterization result.
Note
The default SLEWRATE settings in each pad configuration register must be used to ensure timings,
unless specific instructions are given otherwise.
7.9.1 Timing Parameters and Information
The timing parameter symbols used in Section 7.9 are created in accordance with JEDEC Standard 100. To
shorten the symbols, some pin names and other related terminologies have been abbreviated in Table 7-3:
Table 7-3. Timing Parameters Subscripts
SYMBOL
PARAMETER
Cycle time (period)
Delay time
c
d
dis
en
h
Disable time
Enable time
Hold time
su
START
t
Setup time
Start bit
Transition time
Valid time
v
w
Pulse duration (width)
Unknown, changing, or don't care level
Fall time
X
F
H
High
L
Low
R
Rise time
V
Valid
IV
AE
FE
LE
Z
Invalid
Active Edge
First Edge
Last Edge
High impedance
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7.9.2 Power Supply Requirements
This section describes the power supply requirements to ensure proper device operation.
Note
All power balls must be supplied with the voltages specified in the Recommended Operating
Conditions section, unless otherwise specified in Signal Descriptions and Pin Connectivity
Requirements.
7.9.2.1 Power Supply Slew Rate Requirement
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the
maximum slew rate of supplies to be less than 18 mV/µs. For instance, as shown in Figure 7-2, TI recommends
having the supply ramp slew for a 1.8-V supply of more than 100 µs.
Figure 7-2 describes the Power Supply Slew Rate Requirement in the device.
Supply value
t
slew rate < 18 mV/μs
slew > (supply value) / (18 mV/μs)
or
supply value × 55.6 μs/V
SPRT740_ELCH_06
Figure 7-2. Power Supply Slew and Slew Rate
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7.9.2.2 Power Supply Sequencing
This section describes power sequence requirements using power sequence diagrams and associated notes.
Each power sequence diagram demonstrates the sequential order expected for each device power rail. This
is done by assigning each device power rail to one or more waveform. A dual-voltage power rail may be
associated with more than one waveform and the associated note will describe which waveform is applicable.
Each waveform defines a transition region for the associated power rails and shows its sequential relationship
to the transition regions of other power rails. The notes associated with the power sequence diagram provides
further detail of these requirements. See the Power-up Sequence section for details on power-up requirements,
and the Power-down Sequence section for details on power-down requirements.
Two types of power supply transition regions are used to simplify the power supply sequencing diagrams. The
legends shown in Figure 7-3 and Figure 7-4 along with their descriptions are provided to clarify what each
transition regions represents.
Figure 7-3 defines a transition region with multiple power rails which may be sourced from multiple power
supplies or a single power supply. Transitions shown within the transition region represent a use case where
multiple power supplies are used to source power rails associated with this waveform, and these power
supplies are allowed to ramp at different times within the region since they do not have any specific sequence
requirement relative to each other.
Figure 7-3. Multiple Power Supply Transition Legend
Figure 7-4 defines a transition region with one or more power rails which must be sourced from a single common
power supply. No transitions are shown within the region to represent a single ramp within the transition region.
Figure 7-4. Single Common Power Supply Transition Legend
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7.9.2.2.1 Power-Up Sequencing
Figure 7-5 describes the device power-up sequencing.
VSYS
Note 1
Note 2
VSYS, VMON_VSYS
VMON_VSYS
(3)
(3)
(3)
(3)
VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3
(3)
,
(3)
VDDSHV_CANUART , VDDA_3P3_USB,
(4)
VMON_3P3_SOC
(5)
(5)
(5)
(5)
(5)
(5)
VDDS_OSC0, VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3
,
VDDSHV_CANUART , VDDA_MCU,
VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_PLL3, VDDA_PLL4, VDDA_PLL5, VDDA_1P8_CSIRX0,
(6)
VDDA_1P8_USB, VMON_1P8_SOC , VDDA_TEMP0, VDDA_TEMP1, VDDA_TEMP2
(12) (12)
VDDSHV4 , VDDSHV5 , VDDSHV6
(12)
(7)
VDDS_DDR , VDDS_DDR_C
(7)
(8)(10)
(8)
(8)
, VDD_CANUART , VDDA_CORE_CSIRX0 , VDDA_CORE_USB
(8)
VDD_CORE
,
(12)
VDDA_DDR_PLL0
(9)(10)
(10) (9)
, VDDR_CORE , VDDA_CANUART ,VDDA_CORE_CSIRX0
(9)
VDD_CORE
,
(12)
(9)
VDDA_CORE_USB0 ,VDDA_DDR_PLL0
Hi-Z
(11)
VPP
MCU_PORz
MCU_OSC0_XI, MCU_OSC0_XO
AM62Ax_ELCH_01
Figure 7-5. Power-Up Sequencing
1. VSYS represents the name of a supply which sources power to the entire system. This supply is expected to
be a pre-regulated supply that sources power management devices which source all other supplies.
2. VMON_VSYS input is used to monitor VSYS via an external resistor divider circuit. For more information,
see the System Power Supply Monitor Design Guidelines.
3. VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-6] are dual voltage IO supplies which can
be operated at 1.8V or 3.3V depending on the application requirements. VDDSHV_CANUART shall be
connected to an always-on power source when using Partial IO low power mode, or connected to any valid
IO power source when not using Partial IO low power mode. When VDDSHV_CANUART is not connected to
an always-on power source and is operating at 3.3V, it shall be ramped up with other 3.3V supplies during
the 3.3V ramp period defined by this waveform.
When any of the VDDSHV_MCU and VDDSHVx [x=0-6] IO supplies are operating at 3.3V, they shall be
ramped up with other 3.3V supplies during the 3.3V ramp period defined by this waveform.
4. The VMON_3P3_SOC input is used to monitor supply voltage and shall be connected to the respective 3.3V
supply source.
5. VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-6] are dual voltage IO supplies which can
be operated at 1.8V or 3.3V depending on the application requirements. VDDSHV_CANUART shall be
connected to an always-on power source when using Partial IO low power mode, or connected to any valid
IO power source when not using Partial IO low power mode. When VDDSHV_CANUART is not connected to
an always-on power source and is operating at 1.8V, it shall be ramped up with other 1.8V supplies during
the 1.8V ramp period defined by this waveform.
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When any of the VDDSHV_MCU and VDDSHVx [x=0-6] IO supplies are operating at 1.8V, they shall be
ramped up with other 1.8V supplies during the 1.8V ramp period defined by this waveform.
6. The VMON_1P8_SOC input is used to monitor supply voltage and shall be connected to the respective 1.8V
supply source.
7. VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp
together.
8. VDD_CANUART shall be connected to an always-on power source when using Partial IO or IO Only + DDR
Self-refresh low power modes, or connected to the same power source as VDD_CORE when not using
these low power modes.
VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 shall always be sourced
from the same power source and can be operated at 0.75V or 0.85V. When these supplies are operating at
0.75V, they shall be ramped up prior to all 0.85V supplies as shown in this waveform.
The potential applied to VDD_CORE must never be greater than the potential applied to VDD_CANUART
+ 0.18V during power-up or power-down. This requires VDD_CANUART to ramp up before and ramp down
after VDD_CORE. VDD_CANUART does not have any ramp requirements beyond the one defined for
VDD_CORE.
9. VDD_CANUART shall be connected to an always-on power source when using Partial IO or IO Only + DDR
Self-refresh low power modes, or connected to the same power source as VDD_CORE when not using
these low power modes.
VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 shall be sourced from
the same power source and can be operated at 0.75V or 0.85V. When these supplies are operating at 0.85V,
they shall be ramped up with other 0.85V supplies during the 0.85V ramp period defined by this waveform.
The potential applied to VDD_CORE must never be greater than the potential applied to VDD_CANUART
+ 0.18V during power-up or power-down. This requires VDD_CANUART to ramp up before and ramp down
after VDD_CORE. VDD_CANUART does not have any ramp requirements beyond the one defined for
VDD_CORE.
10. The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE +
0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after
VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements
beyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered by
the same source so they ramp together when VDD_CORE is operating at 0.85V.
The potential applied to VDD_CORE must never be greater than the potential applied to VDD_CANUART
+ 0.18V during power-up or power-down. This requires VDD_CANUART to ramp up before and ramp down
after VDD_CORE. VDD_CANUART does not have any ramp requirements beyond the one defined for
VDD_CORE.
11. VPP is the 1.8V eFuse programming supply, which shall be left floating (HiZ) or grounded during power-up/
down sequences and during normal device operation. This supply shall only be sourced while programming
eFuse.
12. VDDSHV4, VDDSHV5, and VDDSHV6 were designed to support power-up, power-down, or dynamic
voltage change without any dependency on other power rails. This capability is required to support UHS-I
SD Cards.
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7.9.2.2.2 Power-Down Sequencing
Figure 7-6 describes the device power-down sequencing.
VSYS
VSYS, VMON_VSYS
VMON_VSYS
(1)
(1)
(1)
(1)
VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3
(1)
,
(1)
VDDSHV_CANUART , VDDA_3P3_USB,
VMON_3P3_SOC
(2)
(2)
(2)
(2)
VDDS_OSC0, VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3
(2)
,
(2)
VDDSHV_CANUART , VDDA_MCU,
VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_PLL3, VDDA_PLL4, VDDA_PLL5, VDDA_1P8_CSIRX0,
VDDA_1P8_USB, VMON_1P8_SOC, VDDA_TEMP0, VDDA_TEMP1, VDDA_TEMP2
(6) (6)
VDDSHV4 , VDDSHV5 , VDDSHV6
(6)
VDDS_DDR, VDDS_DDR_C
(3)(5)
(3)
(3)
, VDD_CANUART , VDDA_CORE_CSIRX0 , VDDA_CORE_USB
(3)
VDD_CORE
,
(6)
VDDA_DDR_PLL0
(4)(5)
(5)
(4)
, VDDR_CORE , VDDA_CANUART , VDDA_CORE_CSIRX0 ,
(4)
VDD_CORE
(4)
VDDA_CORE_USB ,VDDA_DDR_PLL0
(6)
VPP
Hi-Z
MCU_PORz
MCU_OSC0_XI, MCU_OSC0_XO
AM62Ax_ELCH_02
Figure 7-6. Power-Down Sequencing
1. VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-6] when operating at 3.3V.
2. VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-6] when operating at 1.8V.
3. VDD_CORE, VDD_CANUART, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 when
operating at 0.75V.
4. VDD_CORE, VDD_CANUART, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 when
operating at 0.85V.
5. The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE +
0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after
VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements
beyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered by
the same source so they ramp together when VDD_CORE is operating at 0.85V.
The potential applied to VDD_CORE must never be greater than the potential applied to VDD_CANUART
+ 0.18V during power-up or power-down. This requires VDD_CANUART to ramp up before and ramp down
after VDD_CORE. VDD_CANUART does not have any ramp requirements beyond the one defined for
VDD_CORE.
6. VDDSHV4, VDDSHV5, and VDDSHV6 were designed to support power-up, power-down, or dynamic
voltage change without any dependency on other power rails. This capability is required to support UHS-I
SD Cards.
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7.9.3 System Timing
For more details about features and additional description information on the subsystem multiplexing signals,
see the corresponding subsections within Signal Descriptions and Detailed Description sections.
7.9.3.1 Reset Timing
Tables and figures provided in this section define timing conditions, timing requirements, and switching
characteristics for reset related signals.
Table 7-4. Reset Timing Conditions
PARAMETER
MIN
MAX UNIT
INPUT CONDITIONS
VDD(1) = 1.8V
VDD(1) = 3.3V
0.0033
0.0018
V/ns
V/ns
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
30 pF
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
Table 7-5. MCU_PORz Timing Requirements
see Figure 7-7
NO.
PARAMETER
MIN
MAX UNIT
Hold time, MCU_PORz active (low) at Power-up
after supplies valid (using external crystal circuit)
RST1
9500000
ns
th(SUPPLIES_VALID - MCU_PORz)
Hold time, MCU_PORz active (low) at Power-up
after supplies valid and external clock stable (using
external LVCMOS clock source)
RST2
1200
1200
ns
ns
Pulse Width, MCU_PORz low after Power-up
(without removal of Power or system reference
clock MCU_OSC0_XI/XO)
RST3 tw(MCU_PORzL)
Figure 7-7. MCU_PORz Timing Requirements
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Table 7-6. MCU_RESETSTATz, and RESETSTATz Switching Characteristics
see Figure 7-8
NO.
PARAMETER
MIN
MAX UNIT
Delay time, MCU_PORz active (low) to
MCU_RESETSTATz active (low)
RST4 td(MCU_PORzL-MCU_RESETSTATzL)
RST5 td(MCU_PORzH-MCU_RESETSTATzH)
RST6 td(MCU_PORzL-RESETSTATzL)
RST7 td(MCU_PORzH-RESETSTATzH)
RST8 tw(MCU_RESETSTATzL)
0
ns
Delay time, MCU_PORz inactive (high) to
MCU_RESETSTATz inactive (high)
6120*S(1)
0
ns
ns
ns
ns
Delay time, MCU_PORz active (low) to
RESETSTATz active (low)
Delay time, MCU_PORz inactive (high) to
RESETSTATz inactive (high)
9195*S(1)
966*S(1)
Pulse Width, MCU_RESETSTATz low
(SW_MCU_WARMRST)
Pulse Width, RESETSTATz low
(SW_MCU_WARMRST, SW_MAIN_PORz, or
SW_MAIN_WARMRST)
RST9 tw(RESETSTATzL)
4040*S
ns
(1) S = MCU_OSC0_XI/XO clock period in ns.
Figure 7-8. MCU_RESETSTATz, and RESETSTATz Switching Characteristics
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Table 7-7. MCU_RESETz Timing Requirements
see Figure 7-9
NO.
PARAMETER
MIN
MAX UNIT
(1)
RST10 tw(MCU_RESETzL)
Pulse Width, MCU_RESETz active (low)
1200
ns
(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 7-8. MCU_RESETSTATz, and RESETSTATz Switching Characteristics
see Figure 7-9
NO.
PARAMETER
MIN
MAX UNIT
Delay time, MCU_RESETz active (low) to
MCU_RESETSTATz active (low)
RST11 td(MCU_RESETzL-MCU_RESETSTATzL)
0
ns
Delay time, MCU_RESETz inactive (high) to
MCU_RESETSTATz inactive (high)
RST12 td(MCU_RESETzH-MCU_RESETSTATzH)
RST13 td(MCU_RESETzL-RESETSTATzL)
966*S(1)
0
ns
ns
ns
Delay time, MCU_RESETz active (low) to
RESETSTATz active (low)
RST14 td(MCU_RESETzH-RESETSTATzH)
Delay time, MCU_RESETz inactive (high) to
RESETSTATz inactive (high)
4040*S(1)
(1) S = MCU_OSC0_XI/XO clock period in ns.
Figure 7-9. MCU_RESETz, MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching
Characteristics
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Table 7-9. RESET_REQz Timing Requirements
see Figure 7-10
NO.
PARAMETER
MIN
MAX UNIT
(1)
RST15 tw(RESET_REQzL)
Pulse Width, RESET_REQz active (low)
1200
ns
(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 7-10. RESETSTATz Switching Characteristics
see Figure 7-10
NO.
PARAMETER
MIN
MAX UNIT
Delay time, RESET_REQz active (low) to
RESETSTATz active (low)
RST16 td(RESET_REQzL-RESETSTATzL)
900*T(1)
ns
Delay time, RESET_REQz inactive (high) to
RESETSTATz inactive (high)
RST17 td(RESET_REQzH-RESETSTATzH)
4040*S(2)
ns
(1) T = Reset Isolation Time (Software Dependent)
(2) S = MCU_OSC0_XI/XO clock period in ns.
Figure 7-10. RESET_REQz and RESETSTATz Timing Requirements and Switching Characteristics
Table 7-11. EMUx Timing Requirements
see Figure 7-11
NO.
PARAMETER
MIN
MAX UNIT
Setup time, EMU[1:0] before MCU_PORz inactive
(high)
RST18 tsu(EMUx-MCU_PORz)
3*S(1)
ns
Hold time, EMU[1:0] after MCU_PORz inactive
(high)
RST19 th(MCU_PORz - EMUx)
10
ns
(1) S = MCU_OSC0_XI/XO clock period in ns.
Figure 7-11. EMUx Timing Requirements
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Table 7-12. BOOTMODE Timing Requirements
see Figure 7-12
NO.
PARAMETER
MIN
MAX UNIT
Setup time, BOOTMODE[15:00] before
PORz_OUT high (External MCU PORz event or
Software SW_MAIN_PORz)
RST23 tsu(BOOTMODE-PORz_OUT)
3*S(1)
ns
Hold time, BOOTMODE[15:00] after PORz_OUT
high (External MCU PORz event, or Software
SW_MAIN_PORz)
RST24 th(PORz_OUT - BOOTMODE)
0
ns
(1) S = MCU_OSC0_XI/XO clock period in ns.
Table 7-13. PORz_OUT Switching Characteristics
see Figure 7-12
NO.
PARAMETER
MIN
MAX UNIT
Delay time, MCU_PORz active (low) to
PORz_OUT active (low)
RST25 td(MCU_PORzL-PORz_OUT)
RST26 td(MCU_PORzH-PORz_OUT)
RST27 tw(PORz_OUTL)
0
ns
Delay time, MCU_PORz inactive (high) to
PORz_OUT inactive (high)
1840
1200
ns
ns
Pulse Width, PORz_OUT low (MCU_PORz or
SW_MAIN_PORz)
Figure 7-12. BOOTMODE Timing Requirements and PORz_OUT Switching Characteristics
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7.9.3.2 Error Signal Timing
Tables and figures provided in this section define timing conditions and switching characteristics for
MCU_ERRORn.
Table 7-14. Error Signal Timing Conditions
PARAMETER
MIN
MAX UNIT
OUTPUT CONDITIONS
CL
Output load capacitance
30 pF
Table 7-15. MCU_ERRORn Switching Characteristics
see Figure 7-13
NO.
PARAMETER
MIN
MAX UNIT
Cycle time minimum, MCU_ERRORn (PWM
mode enabled)
ERR1 tc(MCU_ERRORn)
ERR2 tw(MCU_ERRORn)
td (ERROR_CONDITION-
(P*H)+(P*L)(1) (3) (4)
P*R(1) (2)
ns
Pulse width minimum, MCU_ERRORn active
(PWM mode disabled)(5)
ns
ns
Delay time, ERROR CONDITION to
MCU_ERRORn active(5)
ERR3
50*P(1)
MCU_ERRORnL)
(1) P = ESM functional clock period in ns.
(2) R = Error Pin Counter Pre-Load Register count value.
(3) H = Error Pin PWM High Pre-Load Register count value.
(4) L = Error Pin PWM Low Pre-Load Register count value.
(5) When PWM mode is enabled, MCU_ERRORn stops toggling after ERR3 and will maintain its value (either high or low) until the error is
cleared. When PWM mode is disabled, MCU_ERRORn is active low.
Internal Error Condition
(Active High)
ERR1
MCU_ERRORn
(PWM Mode Enabled)
ERR2
ERR3
MCU_ERRORn
(PWM Mode Disabled)
Figure 7-13. MCU_ERRORn Timing Requirements and Switching Characteristics
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7.9.3.3 Clock Timing
Tables and figures provided in this section define timing conditions, timing requirements, and switching
characteristics for clock signals.
Table 7-16. Clock Timing Conditions
PARAMETER
MIN
MAX UNIT
INPUT CONDITIONS
SRI
Input slew rate
0.5
V/ns
OUTPUT CONDITIONS
5 ns ≤ tc < 8 ns
8 ns ≤ tc < 20 ns
20 ns ≤ tc
5 pF
10 pF
30 pF
CL
Output load capacitance
Table 7-17. Clock Timing Requirements
see Figure 7-14
NO.
MIN
MAX UNIT
CLK1 tc(EXT_REFCLK1)
Cycle time minimum, EXT_REFCLK1
10
E*0.45(1)
E*0.45(1)
10
ns
CLK2 tw(EXT_REFCLK1H)
Pulse Duration, EXT_REFCLK1 high
E*0.55(1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK3 tw(EXT_REFCLK1L)
Pulse Duration, EXT_REFCLK1 low
E*0.55(1)
CLK1 tc(MCU_EXT_REFCLK0)
CLK2 tw(MCU_EXT_REFCLK0H)
CLK3 tw(MCU_EXT_REFCLK0L)
CLK1 tc(AUDIO_EXT_REFCLK0)
CLK2 tw(AUDIO_EXT_REFCLK0H)
CLK3 tw(AUDIO_EXT_REFCLK0L)
CLK1 tc(AUDIO_EXT_REFCLK1)
CLK2 tw(AUDIO_EXT_REFCLK1H)
CLK3 tw(AUDIO_EXT_REFCLK1L)
Cycle time minimum, MCU_EXT_REFCLK0
Pulse Duration, MCU_EXT_REFCLK0 high
Pulse Duration, MCU_EXT_REFCLK0 low
Cycle time minimum, AUDIO_EXT_REFCLK0
Pulse Duration, AUDIO_EXT_REFCLK0 high
Pulse Duration, AUDIO_EXT_REFCLK0 low
Cycle time minimum, AUDIO_EXT_REFCLK1
Pulse Duration, AUDIO_EXT_REFCLK1 high
Pulse Duration, AUDIO_EXT_REFCLK1 low
F*0.45(2)
F*0.45(2)
20
F*0.55(2)
F*0.55(2)
G*0.45(3)
G*0.45(3)
20
G*0.55(3)
G*0.55(3)
H*0.45(4)
H*0.45(4)
H*0.55(4)
H*0.55(4)
(1) E = EXT_REFCLK1 cycle time in ns.
(2) F = MCU_EXT_REFCLK0 cycle time in ns.
(3) G = AUDIO_EXT_REFCLK0 cycle time in ns.
(4) H = AUDIO_EXT_REFCLK1 cycle time in ns.
CLK1
CLK2
CLK3
Input Clock
Figure 7-14. Clock Timing Requirements
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Table 7-18. Clock Switching Characteristics
see Figure 7-15
NO.
PARAMETER
MIN
8
MAX UNIT
CLK4 tc(SYSCLKOUT0)
CLK5 tw(SYSCLKOUT0H)
CLK6 tw(SYSCLKOUT0L)
CLK4 tc(OBSCLK0)
Cycle time minimum,SYSCLKOUT0
Pulse Duration, SYSCLKOUT0 high
Pulse Duration, SYSCLKOUT0 low
Cycle time minimum, OBSCLK0
Pulse Duration, OBSCLK0 high
ns
A*0.4(1)
A*0.4(1)
5
A*0.6(1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A*0.6(1)
CLK5 tw(OBSCLK0H)
B*0.45(2)
B*0.45(2)
5
B*0.55(2)
B*0.55(2)
CLK6 tw(OBSCLK0L)
Pulse Duration, OBSCLK0 low
CLK4 tc(OBSCLK1)
Cycle time minimum, OBSCLK1
Pulse Duration, OBSCLK1 high
CLK5 tw(OBSCLK1H)
TBD*0.45
TBD*0.45
20
TBD*0.55
TBD*0.55
CLK6 tw(OBSCLK1L)
Pulse Duration, OBSCLK1 low
CLK4 tc(CLKOUT0)
Cycle time minimum, CLKOUT0
Pulse Duration, CLKOUT0 high
CLK5 tw(CLKOUT0H)
C*0.4(3)
C*0.4(3)
10
C*0.6(3)
C*0.6(3)
CLK6 tw(CLKOUT0L)
Pulse Duration, CLKOUT0 low
CLK4 tc(MCU_SYSCLKOUT0)
CLK5 tw(MCU_SYSCLKOUT0H)
CLK6 tw(MCU_SYSCLKOUT0L)
CLK4 tc(MCU_OBSCLK0)
CLK5 tw(MCU_OBSCLK0H)
CLK6 tw(MCU_OBSCLK0L)
CLK4 tc(WKUP_CLKOUT0)
CLK5 tw(WKUP_CLKOUT0H)
CLK6 tw(WKUP_CLKOUT0L)
Cycle time minimum, MCU_SYSCLKOUT0
Pulse Duration, MCU_SYSCLKOUT0 high
Pulse Duration, MCU_SYSCLKOUT0 low
Cycle time minimum, MCU_OBSCLK0
Pulse Duration, MCU_OBSCLK0 high
Pulse Duration, MCU_OBSCLK0 low
Cycle time minimum, WKUP_CLKOUT0
Pulse Duration, WKUP_CLKOUT0 high
Pulse Duration, WKUP_CLKOUT0 low
E*0.4(4)
E*0.4(4)
5
E*0.6(4)
E*0.6(4)
D*0.45(5)
D*0.45(5)
5
D*0.55(5)
D*0.55(5)
W*0.4(6)
W*0.4(6)
W*0.6(6)
W*0.6(6)
Cycle time minimum, AUDIO_EXT_REFCLK0
(McASP Clock Source)
20
ns
ns
CLK4 tc(AUDIO_EXT_REFCLK0 )
Cycle time minimum, AUDIO_EXT_REFCLK0
(PLL Clock Source)
10
CLK5 tw(AUDIO_EXT_REFCLK0 H)
CLK6 tw(AUDIO_EXT_REFCLK0 L)
Pulse Duration, AUDIO_EXT_REFCLK0 high
Pulse Duration, AUDIO_EXT_REFCLK0 low
G*0.4(7)
G*0.4(7)
G*0.6(7)
G*0.6(7)
ns
ns
Cycle time minimum, AUDIO_EXT_REFCLK1
(McASP Clock Source)
20
ns
ns
CLK4 tc(AUDIO_EXT_REFCLK1 )
Cycle time minimum, AUDIO_EXT_REFCLK1
(PLL Clock Source)
10
CLK5 tw(AUDIO_EXT_REFCLK1 H)
CLK6 tw(AUDIO_EXT_REFCLK1 L)
Pulse Duration, AUDIO_EXT_REFCLK1 high
Pulse Duration, AUDIO_EXT_REFCLK1 low
J*0.4(8)
J*0.4(8)
J*0.6(8)
J*0.6(8)
ns
ns
(1) A = SYSCLKOUT0 cycle time in ns.
(2) B = OBSCLK0 cycle time in ns.
(3) C = CLKOUT0 cycle time in ns.
(4) E = MCU_SYSCLKOUT0 cycle time in ns.
(5) D = MCU_OBSCLK0 cycle time in ns.
(6) W = WKUP_CLKOUT0 cycle time in ns.
(7) G = AUDIO_EXT_REFCLK0 cycle time in ns.
(8) J = AUDIO_EXT_REFCLK1 cycle time in ns.
CLK4
CLK5
CLK6
Output Clock
Figure 7-15. Clock Switching Characteristics
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7.9.4 Clock Specifications
7.9.4.1 Input Clocks / Oscillators
Various external clock inputs/outputs are needed to drive the device. Summary of these input clock signals is as
follows:
•
MCU_OSC0_XO/MCU_OSC0_XI — external main crystal interface pins connected to the internal high-
frequency oscillator (MCU_HFOSC0), which is the default clock source for internal reference clock
HFOSC0_CLKOUT.
•
•
WKUP_LFOSC0_XO/WKUP_LFOSC0_XI — external crystal interface pins connected to internal low-
frequency oscillator (WKUP_LFOSC0), which sources optional 32768 Hz reference clock.
General purpose clock inputs
– MCU_EXT_REFCLK0 — optional external system clock.
– EXT_REFCLK1 — optional external system clock.
•
•
External CPTS reference clock inputs
– CP_GEMAC_CPTS0_RFT_CLK — optional reference clock input for CPTS_RFT_CLK.
External audio reference clock inputs/outputs
– AUDIO_EXT_REFCLK[1:0] — optional McASP high-frequency input clocks when configured to operate as
an input.
For more information about Input clock interfaces, see Clocking section in Device Configuration chapter in the
device TRM.
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7.9.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
Figure 7-16 shows the recommended crystal circuit. All discrete components used to implement the oscillator
circuit should be placed as close as possible to the MCU_OSC0_XI and MCU_OSC0_XO pins.
Device
MCU_OSC0_XO
MCU_OSC0_XI
Crystal
CL2
CL1
PCB Ground
AM65x_MCU_OSC_INT_01
Figure 7-16. MCU_OSC0 Crystal Implementation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 7-19 summarizes the
required electrical constraints.
Table 7-19. MCU_OSC0 Crystal Circuit Requirements
PARAMETER
MIN
TYP
MAX
UNIT
MHz
ppm
Fxtal
Fxtal
Crystal Parallel Resonance Frequency
25
Crystal Frequency Stability and Tolerance
Ethernet RGMII and RMII
not used
±100
Ethernet RGMII and RMII
using derived clock
±50
CL1+PCBXI
CL2+PCBXO
CL
Capacitance of CL1 + CPCBXI
Capacitance of CL2 + CPCBXO
Crystal Load Capacitance
12
12
6
24
24
12
7
pF
pF
pF
pF
pF
pF
Ω
Cshunt
Crystal Circuit Shunt Capacitance
ESRxtal = 30 Ω
25 MHz
25 MHz
25 MHz
ESRxtal = 40 Ω
ESRxtal = 50 Ω
5
5
(1)
ESRxtal
Crystal Effective Series Resistance
(1) The maximum ESR of the crystal is a function of the crystal frequency and shunt capacitance. See the Cshunt parameter.
When selecting a crystal, the system design must consider temperature and aging characteristics of the crystal
based on worst case environment and expected life expectancy of the system.
Table 7-20 details the switching characteristics of the oscillator.
Table 7-20. MCU_OSC0 Switching Characteristics - Crystal Mode
PARAMETER
MIN
TYP
MAX
UNIT
pF
CXI
XI Capacitance
XO Capacitance
TBD
TBD
TBD
CXO
CXIXO
pF
XI to XO Mutual Capacitance
pF
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Table 7-20. MCU_OSC0 Switching Characteristics - Crystal Mode (continued)
PARAMETER
MIN
TYP
MAX
UNIT
ts
Start-up Time
4
ms
VDD_CORE (min.)
VSS
VDD_CORE
VDDS_OSC0
VDDS_OSC0 (min.)
MCU_OSC0_XO
tsX
VSS
Time
AM65x_MCU_OSC_STARTUP_02
Figure 7-17. MCU_OSC0 Start-up Time
7.9.4.1.1.1 Load Capacitance
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors
CL1, CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to
MCU_OSC0_XI and MCU_OSC0_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the
PCB designer should be able to extract parasitic capacitance for each signal trace. The MCU_OSC0 circuits
and device package have combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic
capacitance values are defined in Table 7-20.
Device
Crystal Circuit
Components
PCB
Signal Traces
MCU_OSC0_XI
CL1
CPCBXI
CXI
CL2
CPCBXO
CXO
MCU_OSC0_XO
AM65x_MCU_OSC_CC_05
Figure 7-18. Load Capacitance
Load capacitors, CL1 and CL2 in Figure 7-16, should be chosen such that the below equation is satisfied. CL in
the equation is the load specified by the crystal manufacturer.
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to
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determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO
=
0.5 pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -
(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF
7.9.4.1.1.2 Shunt Capacitance
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for
MCU_OSC0 operating conditions defined in Table 7-19. Shunt capacitance, Cshunt, of the crystal circuit is a
combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal
circuit components to MCU_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB
designer should be able to extract mutual parasitic capacitance between these signal traces. The device
package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined
in Table 7-20.
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can
also be minimized by placing a ground trace between these signals when the layout requires them to be routed
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as
possible when selecting a crystal.
Device
Crystal Circuit
Components
PCB
Signal Traces
MCU_OSC0_XI
CPCBXIXO
CXIXO
CO
MCU_OSC0_XO
AM65x_MCU_OSC_SC_06
Figure 7-19. Shunt Capacitance
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt
capacitance specified by the crystal manufacturer.
Cshunt ≥ CO + CPCBXIXO + CXIXO
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,
CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.
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7.9.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
Figure 7-20 shows the recommended oscillator connections when MCU_OSC0_XI is connected to a 1.8-V
LVCMOS square-wave digital clock source.
Note
A DC steady-state condition is not allowed on MCU_OSC0_XI when the oscillator is powered up. This
is not allowed because MCU_OSC0_XI is internally AC coupled to a comparator that can enter an
unknown state when DC is applied to the input. Therefore, application software must power down
MCU_OSC0 any time MCU_OSC0_XI is not toggling between logic states.
Device
MCU_OSC0_XO
MCU_OSC0_XI
PCB Ground
AM65x_MCU_OSC_EXT_CLK_03
Figure 7-20. 1.8-V LVCMOS-Compatible Clock Input
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7.9.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
Figure 7-21 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit board
(PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator
operation when combined with production crystal circuit components. In most cases, Rbias is not required and
Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator
performance with production crystal circuit components installed on preproduction PCBs.
Device
WKUP_LFOSC0_XO
WKUP_LFOSC0_XI
Rd
Crystal
(Optional)
(Optional)
Rbias
Cf2
Cf1
PCB Ground
J7ES_LF_OSC_INT_12
Figure 7-21. WKUP_LFOSC0 Crystal Implementation
Table 7-21 presents LFXOSC modes of operation.
Table 7-21. LFXOSC Modes of Operation
CLK_O
UT
MODE
BP_C PD_C
XI
XO
DESCRIPTION
ACTIVE
0
0
XTAL
XTAL CLK_OU
T
Active oscillator mode providing 32kHz
PWRDN
BYPASS
0
1
1
X
PD
PD
LOW Output will be pulled down to LOW. PAD to be tri-stated. Active mode disabled
X
CLK
CLK
XI is driven by external clock source. XO is pulled down to LOW. Due to ESD
diode to supply, XI should not be driven unless oscillator supply is present.
Note
User should set CTRLMMR_WKUP_LFXOSC_TRIM[18:16] i_mult = 3b’001 for CL in the range 6pf to
9.5pf. CTRLMMR_WKUP_LFXOSC_TRIM [18:16] i_mult = 3b’010 for CL in the range 8.5pf to 12pf.
Default setting is 3b’010.
Note
The load capacitors, Cf1 and Cf2 in Figure 7-22, should be chosen such that the below equation is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components
used to implement the oscillator circuit should be placed as close as possible to the associated
oscillator WKUP_LFOSC0_XI, WKUP_LFOSC0_XO, and VSS pins.
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Cf1Cf2
= (Cf1+Cf2)
C
L
J7ES_CL_MATH_03
Figure 7-22. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 7-22 summarizes the
required electrical constraints.
Table 7-22. WKUP_LFOSC0 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
MIN
TYP
MAX UNIT
Parallel resonance crystal frequency
32768
Hz
Cf1
Cf2
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
12
24
24
4
pF
pF
pF
pF
pF
pF
Ω
ESRxtal – 40 kΩ
ESRxtal – 60 kΩ
ESRxtal – 80 kΩ
ESRxtal – 100 kΩ
3
Cshunt Shunt capacitance
2
1
(1)
ESR
Crystal effective series resistance
(1) The maximum ESR of the crystal is a function of the crystal frequency and shunt capacitance. See the Cshunt parameter.
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based
on the worst case environment and expected life expectancy of the system.
Table 7-23 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 7-23. WKUP_LFOSC0 Switching Characteristics – Crystal Mode
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Hz
fxtal
tsX
Oscillation frequency
Start-up time
32768
96.5
ms
VDD_CORE (min.)
VSS
VDD_CORE
VDDS_OSC0
VDDS_OSC0 (min.)
WKUP_LFOSC0_XO
tsX
VSS
Time
LFXOSC_STARTUP_02
Figure 7-23. WKUP_LFOSC0 Start-up Time
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7.9.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
Figure 7-24 shows the recommended oscillator connections when WKUP_LFOSC0_XI is connected to a 1.8-V
LVCMOS square-wave digital clock source.
Device
WKUP_LFOSC0_XI
WKUP_LFOSC0_XO
PCB Ground
AM62x_MCU_OSC_EXT_CLK_03
Figure 7-24. 1.8-V LVCMOS-Compatible Clock Input
7.9.4.1.5 WKUP_LFOSC0 Not Used
Figure 7-25 shows the recommended oscillator connections when WKUP_LFOSC0 is not used.
Device
WKUP_LFOSC0_XO
WKUP_LFOSC0_XI
NC
PCB Ground
Figure 7-25. WKUP_LFOSC0 Not Used
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7.9.4.2 Output Clocks
The device provides several system clock outputs. Summary of these output clocks are as follows:
•
MCU_SYSCLKOUT0
– MCU_PLL0_HSDIV0_CLKOUT (MCU_SYSCLKOUT0) divided by 4 and sent out of the device as
MCU_SYSCLKOUT0. This clock output is provided for test and debug purposes only.
•
•
•
MCU_OBSCLK0
– Observation clock output for test and debug purposes only.
WKUP_CLKOUT0
– WKUP domain CLKOUT0 output.
SYSCLKOUT0
– MAIN_PLL0_HSDIV0_CLKOUT (SYSCLKOUT0) divided by 4 and then sent out of the device as
SYSCLKOUT0. This clock output is provided for test and debug purposes only.
CLKOUT0
•
– CLKOUT0 is the Ethernet subsystem clock (MAIN_PLL2_HSDIV1_CLKOUT) divided-by-5 or divided-
by-10. This clock output was provided as an optional source to the external PHY. When configured
to operate as the RMII Clock source (50 MHz) the signal must also be routed back to the respective
RMII[x]_REF_CLK pin for proper device operation.
•
•
OBSCLK[1:0]
– Observation clock outputs for test and debug purposes only.
AUDIO_EXT_REFCLK[1:0]
– Option of sourcing one of six McASP high-frequency audio reference clocks,
MAIN_PLL1_HSDIV6_CLKOUT, or MAIN_PLL2_HSDIV8_CLKOUT when configured to operate as an
output.
7.9.4.3 PLLs
Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from
off-chip power-sources.
There is one PLL in the MCU domain:
•
MCU PLL
There are nine PLLs in the MAIN domain:
•
•
•
•
•
•
•
•
•
MAIN PLL
PER0 PLL
PER1 PLL
VIDEO PLL
C7x PLL
ARM0 PLL
DDR PLL
SMS PLL
DSS PLL
The system designer should consider the reference clock source start-up time and the PLL lock requirements
before configuring and using any of the PLL outputs as clock sources. The device reference clock input
requirements are defined in Section 7.9.4.1, Input Clocks / Oscillators. PLL configuration details are described in
the device TRM.
For more information on PLLs, see the PLL subsection in the Clocking subsection of the Device Configuration
section in the device TRM.
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7.9.4.4 Recommended System Precautions for Clock and Control Signal Transitions
All clock and strobe signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
Monotonic transitions are more likely to occur with fast signal transitions. It is easy for noise to create non-
monotonic events on a signal with slow transitions. Therefore, avoid slow signal transitions on all clock and
control signals since they are more likely to generate glitches inside the device.
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7.9.5 Peripherals
7.9.5.1 CPSW3G
For more details about features and additional description information on the device Gigabit Ethernet MAC, see
the corresponding subsections within Signal Descriptions and Detailed Description sections.
7.9.5.1.1 CPSW3G MDIO Timing
Table 7-24, Table 7-25, Table 7-26, and Figure 7-26 present timing conditions, requirements, and switching
characteristics for CPSW3G MDIO.
Table 7-24. CPSW3G MDIO Timing Conditions
PARAMETER
MIN
0.9
10
MAX
3.6
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
470
Table 7-25. CPSW3G MDIO Timing Requirements
see Figure 7-26
NO.
PARAMETER
MIN
90
0
MAX
UNIT
ns
MDIO1 tsu(MDIO_MDC)
MDIO2 th(MDC_MDIO)
Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high
Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high
ns
Table 7-26. CPSW3G MDIO Switching Characteristics
see Figure 7-26
NO.
PARAMETER
MIN
400
160
160
-150
MAX
UNIT
ns
MDIO3 tc(MDC)
Cycle time, MDIO[x]_MDC
MDIO4 tw(MDCH)
MDIO5 tw(MDCL)
MDIO7 td(MDC_MDIO)
Pulse Duration, MDIO[x]_MDC high
Pulse Duration, MDIO[x]_MDC low
Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid
ns
ns
150
ns
MDIO3
MDIO4
MDIO5
MDIO[x]_MDC
MDIO1
MDIO2
MDIO[x]_MDIO
(input)
MDIO7
MDIO[x]_MDIO
(output)
CPSW2G_MDIO_TIMING_01
Figure 7-26. CPSW3G MDIO Timing Requirements and Switching Characteristics
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7.9.5.1.2 CPSW3G RMII Timing
Table 7-27, Table 7-28, Figure 7-27, Table 7-29, Figure 7-28, Table 7-30, and Figure 7-29 present timing
conditions, requirements, and switching characteristics for CPSW3G RMII.
Table 7-27. CPSW3G RMII Timing Conditions
PARAMETER
MIN
MAX UNIT
INPUT CONDITIONS
VDD(1) = 1.8V
VDD(1) = 3.3V
0.18
0.4
0.54 V/ns
1.2 V/ns
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
3
25
pF
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
Table 7-28. RMII[x]_REF_CLK Timing Requirements – RMII Mode
see Figure 7-27
NO.
PARAMETER
tc(REF_CLK)
tw(REF_CLKH)
tw(REF_CLKL)
DESCRIPTION
Cycle time, RMII[x]_REF_CLK
MIN
MAX
20.001
13
UNIT
ns
RMII1
RMII2
RMII3
19.999
Pulse Duration, RMII[x]_REF_CLK High
Pulse Duration, RMII[x]_REF_CLK Low
7
7
ns
13
ns
RMII1
RMII2
RMII[x]_REF_CLK
RMII3
Figure 7-27. CPSW3G RMII[x]_REF_CLK Timing Requirements – RMII Mode
Table 7-29. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
see Figure 7-28
NO.
PARAMETER
DESCRIPTION
MIN
4
MAX
UNIT
ns
RMII4
tsu(RXD-REF_CLK)
Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK
Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK
Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK
Hold time RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK
Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK
Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
th(REF_CLK-RXD)
4
ns
4
ns
RMII5
2
ns
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
2
ns
2
ns
RMII4
RMII5
RMII[x]_REF_CLK
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RX_ER
Figure 7-28. CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements – RMII
Mode
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Table 7-30. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
see Figure 7-29
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
RMII6 td(REF_CLK-TXD)
Delay time, RMII[x]_REF_CLK High to RMII[x]_
TXD[1:0] valid
2
10
ns
td(REF_CLK-TX_EN)
Delay time, RMII[x]_REF_CLK to RMII[x]_TX_EN
valid
2
10
ns
RMII6
RMII[x]_REF_CLK
RMII[x]_TXD[1:0], RMII[x]_TX_EN
Figure 7-29. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
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7.9.5.1.3 CPSW3G RGMII Timing
Table 7-31, Table 7-32, Table 7-33, Figure 7-30, Table 7-34, Table 7-35, and Figure 7-31 present timing
conditions, requirements, and switching characteristics for CPSW3G RGMII.
Table 7-31. CPSW3G RGMII Timing Conditions
PARAMETER
MIN
2.64
2
MAX UNIT
INPUT CONDITIONS
SRI
Input slew rate
5
V/ns
pF
OUTPUT CONDITIONS
CL
Output load capacitance
20
PCB CONNECTIVITY REQUIREMENTS
RGMII[x]_RXC,
RGMII[x]_RD[3:0],
RGMII[x]_RX_CTL
50
50
ps
ps
td(Trace Mismatch
Propagation delay mismatch across all traces
Delay)
RGMII[x]_TXC,
RGMII[x]_TD[3:0],
RGMII[x]_TX_CTL
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Table 7-32. RGMII[x]_RXC Timing Requirements – RGMII Mode
see Figure 7-30
NO.
PARAMETER
DESCRIPTION
Cycle time, RGMII[x]_RXC
MODE
10Mbps
MIN
360
36
MAX UNIT
RGMII1 tc(RXC)
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
240
24
RGMII2 tw(RXCH)
Pulse duration, RGMII[x]_RXC high
Pulse duration, RGMII[x]_RXC low
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
RGMII3 tw(RXCL)
100Mbps
1000Mbps
3.6
4.4
Table 7-33. RGMII[x]_RD[3:0], and RGMII[x]_RX_CTL Timing Requirements – RGMII Mode
see Figure 7-30
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
1
MAX UNIT
RGMII4 tsu(RD-RXC)
Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC
high/low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
1
1
tsu(RX_CTL-RXC)
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC
high/low
1
100Mbps
1000Mbps
10Mbps
1
1
RGMII5 th(RXC-RD)
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC
high/low
1
100Mbps
1000Mbps
10Mbps
1
1
th(RXC-RX_CTL)
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC
high/low
1
100Mbps
1000Mbps
1
1
RGMII1
RGMII2
RGMII3
RGMII[x]_RXC(A)
RGMII4
RGMII5
RGMII[x]_RD[3:0](B)
RGMII[x]_RX_CTL(B)
1st Half-byte
RXDV
2nd Half-byte
RXERR
A. RGMII[x]_RXC must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of
RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.
Figure 7-30. CPSW3G RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII
Mode
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Table 7-34. RGMII[x]_TXC Switching Characteristics – RGMII Mode
see Figure 7-31
NO.
PARAMETER
DESCRIPTION
Cycle time, RGMII[x]_TXC
MODE
10Mbps
MIN
360
36
MAX UNIT
RGMII6 tc(TXC)
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
240
24
RGMII7 tw(TXCH)
Pulse duration, RGMII[x]_TXC high
Pulse duration, RGMII[x]_TXC low
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
RGMII8 tw(TXCL)
100Mbps
1000Mbps
3.6
4.4
Table 7-35. RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
see Figure 7-31
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
MAX UNIT
RGMII9 tosu(TD-TXC)
Output setup time(1), RGMII[x]_TD[3:0] valid to
RGMII[x]_TXC high/low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
tosu(TX_CTL-TXC)
Output setup time(1), RGMII[x]_TX_CTL valid to
RGMII[x]_TXC high/low
100Mbps
1000Mbps
10Mbps
RGMII10 toh(TXC-TD)
Output hold time(1), RGMII[x]_TD[3:0] valid after
RGMII[x]_TXC high/low
100Mbps
1000Mbps
10Mbps
toh(TXC-TX_CTL)
Output hold time(1), RGMII[x]_TX_CTL valid after
RGMII[x]_TXC high/low
100Mbps
1000Mbps
(1) Output setup/hold times are defining a delay relationship of the transmit data and control outputs relative to the transmit clock output,
but this output relationship is being presented as the minimum setup/hold times provided to the attached receiver. This approach
matches how the output timing relationships are defined in the RGMII specification.
RGMII6
RGMII7
RGMII8
RGMII[x]_TXC(A)
RGMII9
RGMII[x]_TD[3:0](B)
RGMII[x]_TX_CTL(B)
1st Half-byte
TXEN
2nd Half-byte
TXERR
RGMII10
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of
RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.
Figure 7-31. CPSW3G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics
- RGMII Mode
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7.9.5.2 CPTS
Table 7-36, Table 7-37, Figure 7-32, Table 7-38, and Figure 7-33 present timing conditions, requirements, and
switching characteristics for CPTS.
Table 7-36. CPTS Timing Conditions
PARAMETER
MIN
0.5
2
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
10
Table 7-37. CPTS Timing Requirements
see Figure 7-32
NO.
T1
T2
T3
T4
T5
PARAMETER
DESCRIPTION
Pulse duration, HWnTSPUSH high
MIN
12P(1) + 2
12P(1) + 2
5
MAX
UNIT
ns
tw(HWTSPUSHH)
tw(HWTSPUSHL)
tc(RFT_CLK)
Pulse duration, HWnTSPUSH low
Cycle time, RFT_CLK
ns
8
ns
tw(RFT_CLKH)
tw(RFT_CLKL)
Pulse duration, RFT_CLK high
Pulse duration, RFT_CLK low
0.45T(2)
0.45T(2)
ns
ns
(1) P = functional clock period in ns.
(2) T = RFT_CLK cycle time in ns.
T1
T2
HWn_TSPUSH
RFT_CLK
T3
T4
T5
Figure 7-32. CPTS Timing Requirements
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Table 7-38. CPTS Switching Characteristics
see Figure 7-33
NO.
PARAMETER
DESCRIPTION
Pulse duration, TS_COMP high
SOURCE
MIN
36P(1) - 2
36P(1) - 2
36P(1) - 2
36P(1) - 2
36P(1) - 2
5P(1) - 2
MAX UNIT
T6
tw(TS_COMPH)
tw(TS_COMPL)
tw(TS_SYNCH)
tw(TS_SYNCL)
tw(SYNC_OUTH)
ns
ns
ns
ns
ns
ns
ns
ns
T7
Pulse duration, TS_COMP low
Pulse duration, TS_SYNC high
Pulse duration, TS_SYNC low
Pulse duration, SYNCn_OUT high
T8
T9
T10
TS_SYNC
GENF
T11
tw(SYNC_OUTL)
Pulse duration, SYNCn_OUT low
TS_SYNC
GENF
36P(1) - 2
5P(1) - 2
(1) P = functional clock period in ns.
T6
T7
TS_COMP
T8
T9
TS_SYNC
T10
T11
SYNCn_OUT
Figure 7-33. CPTS Switching Characteristics
For more information, see Data Movement Architecture (DMA) chapter in the device TRM.
7.9.5.3 CSI-2
Note
For more information, see the Camera Streaming Interface Receiver (CSI_RX_IF) section in the
device TRM.
The CSI_RX_IF deals with the processing of the pixel data coming from an external image sensor. It is a key
component for the following multimedia applications: camera viewfinder, video record, and still image capture.
The CSI_RX_IF has a primary serial interface CSI-2 port (CSIRX0) compliant with the MIPI D-PHY RX
specification v1.2 and the MIPI CSI-2 specification v1.3, with 4 differential data lanes plus 1 differential clock
lane in synchronous mode, double data rate. Refer to the MIPI specifications for timing details.
•
Support for 1,2,3 or 4 data lane mode up to 1.5Gbps
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7.9.5.4 DDRSS
For more details about features and additional description information on the device LPDDR4 Memory Interface,
see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 7-39 and Figure 7-34 present switching characteristics for DDRSS.
Table 7-39. DDRSS Switching Characteristics
see Figure 7-34
NO.
PARAMETER
DDR TYPE
MIN
MAX UNIT
20 ns
tc(DDR_CKP/
1
Cycle time, DDR_CKP and DDR_CKN
LPDDR4
0.5358(1)
DDR_CKN)
(1) Minimum DDR clock Cycle time will be limited based on the specific memory type (vendor) used in a system and by PCB
implementation. Refer to AM62Ax DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum
DDR frequency.
1
DDR0_CKP
DDR0_CKN
Figure 7-34. DDRSS Switching Characteristics
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.
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7.9.5.5 DSS
Table 7-40, Table 7-41, Figure 7-35, Table 7-42 and Figure 7-36 present timing conditions, requirements, and
switching characteristics for DSS.
Table 7-40. DSS Timing Conditions
PARAMETER
MIN
1.44
1.5
MAX
26.4
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch Delay)
Propagation delay mismatch across all traces
100
ps
Table 7-41. DSS External Pixel Clock Timing Requirements
see Figure 7-35
NO.
MIN
MAX
UNIT
D6
D7
D8
tc(extpclkin)
Cycle time, VOUT(x)_EXTPCLKIN(2)
6.06
ns
ns
ns
tw(extpclkinL)
tw(extpclkinH)
Pulse duration, VOUT(x)_EXTPCLKIN(2) low
Pulse duration, VOUT(x)_EXTPCLKIN(2) high
0.475P(1)
0.475P(1)
(1) P = VOUT(x)_EXTPCLKIN cycle time in ns
(2) x in VOUT(x) = 0
D7
D8
D6
Falling-edge Clock Reference
Rising-edge Clock Reference
VOUT(x)_EXTPCLKIN
VOUT(x)_EXTPCLKIN
DPI_TIMING_02
Figure 7-35. DSS External Pixel Clock Timing Requirements
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Table 7-42. DSS Switching Characteristics
see Figure 7-36
NO.
PARAMETER
MIN
6.06
MAX UNIT
D1
D2
D3
tc(pclk)
Cycle time, VOUT(x)_PCLK(2)
ns
ns
ns
tw(pclkL)
tw(pclkH)
Pulse duration, VOUT(x)_PCLK(2) low
Pulse duration, VOUT(x)_PCLK(2) high
0.475P(1)
0.475P(1)
Delay time, VOUT(x)_PCLK(2) transition to VOUT(x)_DATA[23:0](2)
transition
D4
D5
td(pclkV-dataV)
-0.68
-0.68
1.78
1.78
ns
ns
Delay time, VOUT(x)_PCLK(2) transition to control signals
VOUT(x)_VSYNC(2), VOUT(x)_HSYNC(2), VOUT(x)_DE(2) falling
edge
td(pclkV-ctrlL)
(1) P = VOUT(x)_PCLK cycle time in ns
(2) x in VOUT(x) = 0
D2
D3
D1
Falling-edge Clock Reference
Rising-edge Clock Reference
VOUT(x)_PCLK
VOUT(x)_PCLK
D5
VOUT(x)_VSYNC
D5
VOUT(x)_HSYNC
D4
VOUT(x)_DATA[23:0]
VOUT(x)_DE
data_1 data_2
D5
data_n
DPI_TIMING_01
A. The assertion of data can be programmed to occur on the falling or rising edge of the pixel clock. Refer to Display Subsystem (DSS)
section in Peripherals chapter in the device TRM.
B. The polarity and pulse width of VOUT(x)_HSYNC and VOUT(x)_VSYNC are programmable, refer to Display Subsystem (DSS) section
in Peripherals chapter in the device TRM.
C. The VOUT(x)_PCLK frequency is configurable, refer to Display Subsystem section in Peripherals chapter in the device TRM.
Figure 7-36. DSS Switching Characteristics
For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter of the
device TRM.
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7.9.5.6 ECAP
Table 7-43, Table 7-44, Figure 7-37, Table 7-45, and Figure 7-38 present timing conditions, requirements, and
switching characteristics for ECAP.
Table 7-43. ECAP Timing Conditions
PARAMETER
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
Table 7-44. ECAP Timing Requirements
see Figure 7-37
NO.
PARAMETER
DESCRIPTION
Pulse duration, CAP (asynchronous)
MIN
MAX
UNIT
CAP1 tw(CAP)
2P(1) + 2
ns
(1) P = sysclk period in ns.
CAP1
CAP
EPERIPHERALS_TIMNG_01
Figure 7-37. ECAP Timings Requirements
Table 7-45. ECAP Switching Characteristics
see Figure 7-38
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
CAP2 tw(APWM)
Pulse duration, APWMx high/low
2P(1) - 2
ns
(1) P = sysclk period in ns.
CAP2
APWM
EPERIPHERALS_TIMNG_02
Figure 7-38. ECAP Switching Characteristics
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.
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7.9.5.7 Emulation and Debug
For more details about features and additional description information on the device Trace and JTAG interfaces,
see the corresponding subsections within Signal Descriptions and Detailed Description sections.
7.9.5.7.1 Trace
Table 7-46. Trace Timing Conditions
PARAMETER
MIN
MAX UNIT
OUTPUT CONDITIONS
CL Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
2
5
pF
ps
td(Trace Mismatch)
Propagation delay mismatch across all traces
200
Table 7-47. Trace Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
1.8V Mode
DBTR1 tc(TRC_CLK)
DBTR2 tw(TRC_CLKH)
DBTR3 tw(TRC_CLKL)
Cycle time, TRC_CLK
6.83
2.66
2.66
ns
ns
ns
Pulse width, TRC_CLK high
Pulse width, TRC_CLK low
tosu(TRC_DATAV-
DBTR4
Output setup time, TRC_DATA valid to TRC_CLK edge
0.85
ns
TRC_CLK)
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge
0.85
0.85
0.85
ns
ns
ns
DBTR7 toh(TRC_CLK-TRC_CTLI)
Output hold time, TRC_CLK edge to TRC_CTL invalid
3.3V Mode
DBTR1 tc(TRC_CLK)
DBTR2 tw(TRC_CLKH)
DBTR3 tw(TRC_CLKL)
Cycle time, TRC_CLK
8.78
3.64
3.64
ns
ns
ns
Pulse width, TRC_CLK high
Pulse width, TRC_CLK low
tosu(TRC_DATAV-
DBTR4
Output setup time, TRC_DATA valid to TRC_CLK edge
1.10
ns
TRC_CLK)
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge
1.10
1.10
1.10
ns
ns
ns
DBTR7 toh(TRC_CLK-TRC_CTLI)
Output hold time, TRC_CLK edge to TRC_CTL invalid
DBTR1
DBTR2
DBTR3
TRC_CLK
(Worst Case 1)
(Ideal)
(Worst Case 2)
DBTR4
DBTR6
DBTR5
DBTR7
DBTR4
DBTR6
DBTR5
DBTR7
TRC_DATA
TRC_CTL
SPRSP08_Debug_01
Figure 7-39. Trace Switching Characteristics
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7.9.5.7.2 JTAG
Table 7-48. JTAG Timing Conditions
PARAMETER
MIN
0.5
5
MAX
2.0
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
15
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
Propagation delay of each trace
Propagation delay mismatch across all traces
83.5
1000(1)
100
ps
ps
td(Trace Mismatch Delay)
(1) Maximum propagation delay associated with the JTAG signal traces has a significant impact on maximum TCK operating frequency. It
may be possible to increase the trace delay beyond this value, but the operating frequency of TCK must be reduced to account for the
additional trace delay.
Table 7-49. JTAG Timing Requirements
see Figure 7-40
NO.
MIN
MAX
UNIT
ns
J1
tc(TCK)
Cycle time minimum, TCK
40(1)
J2
tw(TCKH)
Pulse width minimum, TCK high
0.4P(2)
ns
J3
tw(TCKL)
Pulse width minimum, TCK low
0.4P(2)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
Input setup time minimum, TDI valid to TCK high
Input setup time minimum, TMS valid to TCK high
Input hold time minimum, TDI valid from TCK high
Input hold time minimum, TMS valid from TCK high
2
2
3
3
ns
J4
J5
ns
ns
ns
(1) The maximum TCK operating frequency assumes the following timing requirements and switching characteristis for the attached
debugger. The operating frequency of TCK must be reduced to provide appropriate timing margin if the debugger exceeds any of these
assumptions.
•
•
Minimum TDO setup time of 2 ns relative to the rising edge of TCK
TDI and TMS output delay in the range of -12.9 ns to 13.9 ns relative to the falling edge of TCK
(2) P = TCK cycle time in ns
Table 7-50. JTAG Switching Characteristics
see Figure 7-40
NO.
PARAMETER
MIN
MAX
UNIT
ns
J6
J7
td(TCKL-TDOI)
td(TCKL-TDOV)
Delay time minimum, TCK low to TDO invalid
Delay time maximum, TCK low to TDO valid
0
12
ns
J1
J2
J3
TCK
TDI / TMS
TDO
J4
J5
J4
J5
J7
J6
Figure 7-40. JTAG Timing Requirements and Switching Characteristics
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7.9.5.8 EPWM
Table 7-51, Table 7-52, Figure 7-41, Table 7-53, Figure 7-42, Figure 7-43, and Figure 7-44 present timing
conditions, requirements, and switching characteristics for EPWM.
Table 7-51. EPWM Timing Conditions
PARAMETER
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
Table 7-52. EPWM Timing Requirements
see Figure 7-41
NO.
PARAMETER
DESCRIPTION
Pulse duration, EHRPWM_SYNCI
MIN
2P(1) + 2
3P(1) + 2
MAX
UNIT
ns
PWM6 tw(SYNCIN)
PWM7 tw(TZ)
Pulse duration, EHRPWM_TZn_IN low
ns
(1) P = sysclk period in ns.
PWM6
EHRPWM_SYNCI
PWM7
EHRPWM_TZn_IN
EPERIPHERALS_TIMNG_07
Figure 7-41. EPWM Timing Requirements
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Table 7-53. EPWM Switching Characteristics
see Figure 7-42, Figure 7-43, and Figure 7-44
NO.
PARAMETER
DESCRIPTION
Pulse duration, EHRPWM_A/B high/low
Pulse duration, EHRPWM_SYNCO
MIN
P(1) - 3
P(1) - 3
MAX
UNIT
ns
PWM1 tw(PWM)
PWM2 tw(SYNCOUT)
PWM3 td(TZ-PWM)
ns
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B forced
high/low
11
11
ns
PWM4 td(TZ-PWMZ)
PWM5 tw(SOC)
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B Hi-Z
Pulse duration, EHRPWM_SOCA/B output
ns
ns
P(1) - 3
(1) P = sysclk period in ns.
PWM1
EHRPWM_A/B
PWM1
PWM2
EHRPWM_SYNCO
EHRPWM_SOCA/B
PWM5
EPERIPHERALS_TIMNG_04
Figure 7-42. EHRPWM Switching Characteristics
PWM3
EHRPWM_A/B
EHRPWM_TZn_IN
EPERIPHERALS_TIMING_05
Figure 7-43. EHRPWM_TZn_IN to EHRPWM_A/B Forced Switching Characteristics
PWM4
EHRPWM_A/B
EHRPWM_TZn_IN
Figure 7-44. EHRPWM_TZn_IN to EHRPWM_A/B Hi-Z Switching Characteristics
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in
the device TRM.
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7.9.5.9 EQEP
Table 7-54, Table 7-55, Figure 7-45, and Table 7-56 present timing conditions, requirements, and switching
characteristics for EQEP.
Table 7-54. EQEP Timing Conditions
PARAMETER
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
Table 7-55. EQEP Timing Requirements
see Figure 7-45
NO.
PARAMETER
DESCRIPTION
MIN
2P(1) + 2
2P(1) + 2
2P(1) + 2
2P(1) + 2
2P(1) + 2
MAX
UNIT
ns
QEP1
QEP2
QEP3
QEP4
QEP5
tw(QEP)
Pulse duration, QEP_A/B
Pulse duration, QEP_I high
Pulse duration, QEP_I low
tw(QEPIH)
tw(QEPIL)
tw(QEPSH)
tw(QEPSL)
ns
ns
Pulse duration, QEP_S high
Pulse duration, QEP_S low
ns
ns
(1) P = sysclk period in ns
QEP1
QEP_A/B
QEP2
QEP_I
QEP3
QEP4
QEP_S
QEP5
EPERIPHERALS_TIMNG_03
Figure 7-45. EQEP Timing Requirements
Table 7-56. EQEP Switching Characteristics
NO.
PARAMETER
td(QEP-CNTR)
DESCRIPTION
MIN
MAX
UNIT
QEP6
Delay time, external clock to counter increment
24
ns
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter
in the device TRM.
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7.9.5.10 GPIO
Table 7-57, Table 7-58, and Table 7-59 present timing conditions, requirements, and switching characteristics for
GPIO.
The device has three instances of the GPIO module.
•
•
•
MCU_GPIO0
GPIO0
GPIO1
Note
GPIOn_x is generic name used to describe a GPIO signal, where n represents the specific GPIO
module and x represents one of the input/output signals associated with the module.
For additional description information on the device GPIO, see the corresponding subsections within
Signal Descriptions and Detailed Description sections.
Table 7-57. GPIO Timing Conditions
PARAMETER
BUFFER TYPE
MIN
MAX UNIT
INPUT CONDITIONS
SRI Input slew rate
OUTPUT CONDITIONS
CL Output load capacitance
LVCMOS
0.2
0.2
6.6 V/ns
0.8 V/ns
I2C OD FS
LVCMOS
3
3
10
pF
pF
I2C OD FS
100
Table 7-58. GPIO Timing Requirements
NO.
PARAMETER
DESCRIPTION
MODE
1.8 V
3.3 V
MIN
MAX UNIT
2P + 2.6(1)
2P + 3.5(1)
ns
ns
GPIO1 tw(GPIO_IN)
Pulse width, GPIOn_x
(1) P = functional clock period in ns.
Table 7-59. GPIO Switching Characteristics
NO.
PARAMETER
DESCRIPTION
BUFFER TYPE
MIN
MAX UNIT
0.975P(1)
-
LVCMOS
ns
ns
3.6
GPIO2 tw(GPIO_OUT)
Pulse width, GPIOn_x
I2C OD FS
160
(1) P = functional clock period in ns.
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.
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7.9.5.11 GPMC
For more details about features and additional description information on the device General-Purpose Memory
Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 7-60 presents timing conditions for GPMC.
Table 7-60. GPMC Timing Conditions
PARAMETER
MIN
1.65
2
MAX UNIT
INPUT CONDITIONS
SRI
Input slew rate
4
V/ns
pF
OUTPUT CONDITIONS
CL
Output load capacitance
20
PCB CONNECTIVITY REQUIREMENTS
133 MHz Synchronous Mode
All other modes
140
140
360
720
ps
ps
td(Trace Delay)
Propagation delay of each trace
td(Trace Mismatch
Propagation delay mismatch across all traces
200
ps
Delay)
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the
device TRM.
7.9.5.11.1 GPMC and NOR Flash — Synchronous Mode
Table 7-61 and Table 7-62 present timing requirements and switching characteristics for GPMC and NOR Flash -
Synchronous Mode.
Table 7-61. GPMC and NOR Flash Timing Requirements — Synchronous Mode
see Figure 7-46, Figure 7-47, and Figure 7-50
MIN
MAX
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(4)
UNIT
GPMC_FCLK = GPMC_FCLK =
100 MHz(1)
133 MHz(1)
F12 tsu(dV-clkH)
F13 th(clkH-dV)
F21 tsu(waitV-clkH)
F22 th(clkH-waitV)
Setup time, input data
GPMC_AD[15:0] valid before output
clock GPMC_CLK high
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.61
0.92
ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
0.86
2.09
2.09
1.61
0.86
2.09
2.09
3.41
2.09
2.09
0.92
3.41
2.09
2.09
ns
ns
ns
ns
ns
ns
ns
Hold time, input data
GPMC_AD[15:0] valid after output
clock GPMC_CLK high
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Setup time, input wait
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GPMC_WAIT[j](2) (3) valid before
output clock GPMC_CLK high
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Hold time, input wait
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GPMC_WAIT[j](2) (3) valid after
output clock GPMC_CLK high
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
(1) GPMC_FCLK select
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•
•
gpmc_fclk_sel[1:0] = 2b01 to select the 100MHz GPMC_FCLK
gpmc_fclk_sel[1:0] = 2b00 to select the 133MHz GPMC_FCLK
(2) In GPMC_WAIT[j], j is equal to 0 or 1.
(3) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-
Purpose Memory Controller (GPMC) section in the device TRM.
(4) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
For not_div_by_1_mode:
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz
For TIMEPARAGRANULARITY_X1:
–
•
–
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
Table 7-62. GPMC and NOR Flash Switching Characteristics – Synchronous Mode
see Figure 7-46, Figure 7-47, Figure 7-48, Figure 7-49, and Figure 7-50
MIN
100 MHz
10.00
MAX
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(16)
UNIT
(2)
133 MHz
F0 1 / tc(clk)
F1 tw(clkH)
Period, output clock GPMC_CLK(15)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
7.52
ns
Typical pulse duration, output clock
GPMC_CLK high
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
0.475P
- 0.3(14)
0.475P
ns
ns
- 0.3(14)
F1 tw(clkL)
Typical pulse duration, output clock
GPMC_CLK low
div_by_1_mode;
GPMC_FCLK_MUX;
0.475P
- 0.3(14)
0.475P
- 0.3(14)
TIMEPARAGRANULARITY_X1
F2 td(clkH-csnV)
Delay time, output clock GPMC_CLK
rising edge to output chip select
GPMC_CSn[i] transition(13)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
F - 2.2
F + F - 2.2
3.75
F + ns
3.75
(5)
(5)
F3 td(clkH-CSn[i]V) Delay time, output clock GPMC_CLK
rising edge to output chip select
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
E - 2.2
E + E - 2.2 E + 4.5 ns
3.18
(4)
(4)
GPMC_CSn[i] invalid(13)
F4 td(aV-clk)
Delay time, output address
GPMC_A[27:1] valid to output clock
GPMC_CLK first edge
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
B - 2.3 B + 4.5 B - 2.3 B + 4.5 ns
(2)
(2)
F5 td(clkH-aIV)
Delay time, output clock GPMC_CLK
rising edge to output address
GPMC_A[27:1] invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3
4.5
-2.3
4.5 ns
F6 td(be[x]nV-clk)
Delay time, output lower byte
enable and command latch enable
div_by_1_mode;
GPMC_FCLK_MUX;
B - 2.3 B + 1.9 B - 2.3 B + 1.9 ns
(2)
(2)
GPMC_BE0n_CLE, output upper byte TIMEPARAGRANULARITY_X1
enable GPMC_BE1n valid to output
clock GPMC_CLK first edge
F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK
rising edge to output lower byte
div_by_1_mode;
GPMC_FCLK_MUX;
D - D + 1.9 D - 2.3 D + 1.9 ns
2.3(3)
(3)
enable and command latch enable
TIMEPARAGRANULARITY_X1
GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n invalid(10)
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Table 7-62. GPMC and NOR Flash Switching Characteristics – Synchronous Mode (continued)
see Figure 7-46, Figure 7-47, Figure 7-48, Figure 7-49, and Figure 7-50
MIN
100 MHz
D - 2.3 D + 1.9 D - 2.3 D + 1.9 ns
MAX
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(16)
UNIT
(2)
133 MHz
F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
invalid(11)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
(3)
(3)
F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
invalid(12)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
D - 2.3 D + 1.9 D - 2.3 D + 1.9 ns
(3)
(3)
F8 td(clkH-advn)
F9 td(clkH-advnIV)
F10 td(clkH-oen)
F11 td(clkH-oenIV)
F14 td(clkH-wen)
Delay time, output clock GPMC_CLK
rising edge to output address
valid and address latch enable
GPMC_ADVn_ALE transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
G - G + 4.5 G - 2.3 G + 4.5 ns
2.3(6)
(6)
Delay time, output clock GPMC_CLK
rising edge to output address
valid and address latch enable
GPMC_ADVn_ALE invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
D - 2.3 D + 4.5 D - 2.3 D + 4.5 ns
(3)
(3)
Delay time, output clock GPMC_CLK
rising edge to output enable
GPMC_OEn_REn transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
H - 2.3 H + 3.5 H - 2.3 H + 3.5 ns
(7)
(7)
Delay time, output clock GPMC_CLK
rising edge to output enable
GPMC_OEn_REn invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
H - 2.3 H + 3.5 H - 2.3 H + 3.5 ns
(7)
(7)
Delay time, output clock GPMC_CLK
rising edge to output write enable
GPMC_WEn transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
I - 2.3 I + 4.5 I - 2.3 I + 4.5 ns
(8)
(8)
F15 td(clkH-do)
F15 td(clkL-do)
F15 td(clkL-do).
F17 td(clkH-be[x]n)
Delay time, output clock GPMC_CLK
rising edge to output data
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns
(9)
(9)
GPMC_AD[15:0] transition(10)
Delay time, GPMC_CLK falling
edge to GPMC_AD[15:0] data bus
transition(11)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns
(9)
(9)
Delay time, GPMC_CLK falling
edge to GPMC_AD[15:0] data bus
transition(12)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns
(9)
(9)
Delay time, output clock GPMC_CLK
rising edge to output lower byte
enable and command latch enable
GPMC_BE0n_CLE transition(10)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns
(9)
(9)
F17 td(clkL-be[x]n)
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
transition(11)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns
(9)
(9)
F17 td(clkL-be[x]n).
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
transition(12)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns
(9)
(9)
F18 tw(csnV)
Pulse duration, output chip select
GPMC_CSn[i](13) low
Read
Write
Read
Write
A
A
C
C
A
A
C
C
ns
ns
ns
ns
F19 tw(be[x]nV)
Pulse duration, output lower byte
enable and command latch enable
GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n low
F20 tw(advnV)
Pulse duration, output address
valid and address latch enable
GPMC_ADVn_ALE low
Read
Write
K
K
K
K
ns
ns
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
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For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
With n being the page burst access number.
(2) B = ClkActivationTime × GPMC_FCLK(14)
(3) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(4) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(5) For csn falling edge (CS activated):
•
Case GPMCFCLKDIVIDER = 0:
F = 0.5 × CSExtraDelay × GPMC_FCLK(14)
Case GPMCFCLKDIVIDER = 1:
–
•
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and
CSOnTime are even)
–
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
(6) For ADV falling edge (ADV activated):
•
Case GPMCFCLKDIVIDER = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
Case GPMCFCLKDIVIDER = 1:
–
•
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
•
Case GPMCFCLKDIVIDER = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
Case GPMCFCLKDIVIDER = 1:
–
•
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
•
Case GPMCFCLKDIVIDER = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
Case GPMCFCLKDIVIDER = 1:
–
•
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
(7) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
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•
•
Case GPMCFCLKDIVIDER = 0:
H = 0.5 × OEExtraDelay × GPMC_FCLK(14)
Case GPMCFCLKDIVIDER = 1:
–
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and
OEOnTime are even)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
For OE rising edge (OE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
H = 0.5 × OEExtraDelay × GPMC_FCLK(14)
Case GPMCFCLKDIVIDER = 1:
–
•
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and
OEOffTime are even)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
(8) For WE falling edge (WE activated):
•
Case GPMCFCLKDIVIDER = 0:
I = 0.5 × WEExtraDelay × GPMC_FCLK(14)
Case GPMCFCLKDIVIDER = 1:
–
•
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and
WEOnTime are even)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
For WE rising edge (WE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
I = 0.5 × WEExtraDelay × GPMC_FCLK (14)
Case GPMCFCLKDIVIDER = 1:
–
•
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and
WEOffTime are even)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(9) J = GPMC_FCLK(14)
(10) First transfer only for CLK DIV 1 mode.
(11) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(12) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
(14) P = GPMC_CLK period in ns
(15) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
(16) For div_by_1_mode:
•
GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
–
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For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz
SPRSP77 – MARCH 2023
•
For TIMEPARAGRANULARITY_X1:
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
•
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
For no extra_delay:
•
•
•
•
GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed
F1
F0
F1
GPMC_CLK
F2
F3
F18
GPMC_CSn[i]
F4
F6
GPMC_A[MSB:1]
Valid Address
F7
F19
F19
GPMC_BE0n_CLE
GPMC_BE1n
F6
F8
F8
F20
F9
GPMC_ADVn_ALE
GPMC_OEn_REn
F10
F11
F13
F12
D 0
GPMC_AD[15:0]
GPMC_WAIT[j]
GPMC_01
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-46. GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)
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F1
F0
F1
GPMC_CLK
F2
F3
GPMC_CSn[i]
F4
GPMCA[MSB:1]
Valid Address
F6
F7
GPMC_BE0n_CLE
GPMC_BE1n
F7
F9
F6
F8
F8
GPMC_ADVn_ALE
GPMC_OEn_REn
F10
F11
F13
F13
F12
D 0
F22
F12
D 3
GPMC_AD[15:0]
GPMC_WAIT[j]
D 1
D 2
F21
GPMC_02
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-47. GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)
F1
F1
F0
GPMC_CLK
GPMC_CSn[i]
F2
F3
F4
F6
Valid Address
GPMC_A[MSB:1]
F17
F17
F17
F17
F17
F17
GPMC_BE0n_CLE
GPMC_BE1n
F6
F8
F8
F9
GPMC_ADVn_ALE
GPMC_WEn
F14
F14
F15
D 1
F15
D 2
F15
GPMC_AD[15:0]
GPMC_WAIT[j]
D 0
D 3
GPMC_03
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
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B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-48. GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
F1
F0
F1
GPMC_CLK
F2
F3
GPMC_CSn[i]
F6
F6
F4
F7
GMPC_BE0n_CLE
Valid
F7
Valid
GPMC_BE1n
GPMC_A[27:17]
Address (MSB)
F5
F12
F13
F4
F12
GPMC_AD[15:0]
Address (LSB)
D0
D1
D2
D3
F8
F8
F9
GPMC_ADVn_ALE
F10
F11
GPMC_OEn_REn
GPMC_WAIT[j]
GPMC_04
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-49. GPMC and Multiplexed NOR Flash — Synchronous Burst Read
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F1
F1
F0
GPMC_CLK
F2
F3
F18
GPMC_CSn[i]
F4
GPMC_A[27:17]
Address (MSB)
F17
F17
F6
F17
F17
F17
F17
GPMC_BE1n
F6
BPMC_BE0n_CLE
F8
F8
F20
F9
GPMC_ADVn_ALE
F14
F14
GPMC_WEn
F15
D 1
F15
D 2
F15
GPMC_AD[15:0]
Address (LSB)
D 0
D 3
F22
F21
GPMC_WAIT[j]
GPMC_05
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-50. GPMC and Multiplexed NOR Flash — Synchronous Burst Write
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SPRSP77 – MARCH 2023
7.9.5.11.2 GPMC and NOR Flash — Asynchronous Mode
Table 7-63 and Table 7-64 present timing requirements and switching characteristics for GPMC and NOR Flash
— Asynchronous Mode.
Table 7-63. GPMC and NOR Flash Timing Requirements – Asynchronous Mode
see Figure 7-51, Figure 7-52, Figure 7-53, and Figure 7-55
NO. PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
FA5(1) tacc(d)
Data access time
div_by_1_mode;
GPMC_FCLK_MUX;
H(4) ns
TIMEPARAGRANULARITY_X1
FA2 tacc1-pgmode(d)
0(2)
Page mode successive data access time
Page mode first data access time
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
P(3) ns
FA2 tacc2-pgmode(d)
1(1)
div_by_1_mode;
GPMC_FCLK_MUX;
H(4) ns
TIMEPARAGRANULARITY_X1
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active
functional clock edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)
(4) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)
(5) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
Table 7-64. GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
see Figure 7-51, Figure 7-52, Figure 7-53, Figure 7-54, Figure 7-55, and Figure 7-56
MIN
MAX
NO. PARAMETER
DESCRIPTION
MODE(15)
UNIT
N (12) ns
N (12)
133 MHz
FA0 tw(be[x]nV)
Pulse duration, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid time
Read
Write
FA1 tw(csnV)
Pulse duration, output chip select GPMC_CSn[i](13)
low
Read
Write
Read
Write
A (1) ns
A (1)
FA3 td(csnV-advnIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
B - 2 (2) B + 2(2) ns
B - 2(2) B + 2(2)
FA4 td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn invalid
(Single read)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
C - 2(3) C + 2(3) ns
FA9 td(aV-csnV)
Delay time, output address GPMC_A[27:1] valid to
output chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
J - 2(9)
J + 2(9) ns
TIMEPARAGRANULARITY_X1
FA10 td(be[x]nV-csnV)
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid to output
chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2(9)
J + 2(9) ns
FA12 td(csnV-advnV)
FA13 td(csnV-oenV)
FA16 tw(aIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
K - 2(10) K + 2(10) ns
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
L - 2(11) L + 2(11) ns
Pulse duration output address GPMC_A[26:1]
invalid between 2 successive read and write
accesses
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
G (7)
ns
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Table 7-64. GPMC and NOR Flash Switching Characteristics – Asynchronous Mode (continued)
see Figure 7-51, Figure 7-52, Figure 7-53, Figure 7-54, Figure 7-55, and Figure 7-56
MIN
MAX
NO. PARAMETER
DESCRIPTION
MODE(15)
UNIT
133 MHz
FA18 td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn invalid
(Burst read)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
I - 2(8)
I + 2(8) ns
FA20 tw(aV)
Pulse duration, output address GPMC_A[27:1]
valid - 2nd, 3rd, and 4th accesses
div_by_1_mode;
GPMC_FCLK_MUX;
D (4)
ns
TIMEPARAGRANULARITY_X1
FA25 td(csnV-wenV)
FA27 td(csnV-wenIV)
FA28 td(wenV-dV)
FA29 td(dV-csnV)
FA37 td(oenV-aIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
E - 2(5) E + 2(5) ns
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F - 2(6) F + 2(6) ns
Delay time, output write enable GPMC_WEn valid
to output data GPMC_AD[15:0] valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2
ns
Delay time, output data GPMC_AD[15:0] valid to
output chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2(9)
J + 2(9) ns
Delay time, output enable GPMC_OEn_REn valid
to output address GPMC_AD[15:0] phase end
div_by_1_mode;
GPMC_FCLK_MUX;
2
ns
TIMEPARAGRANULARITY_X1
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
with n being the page burst access number
(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(7) G = Cycle2CycleDelay × GPMC_FCLK(14)
(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay))
× GPMC_FCLK(14)
(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)
(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
–
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
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OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
GPMC_FCLK
GPMC_CLK
FA5
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1]
Valid Address
FA0
FA10
Valid
FA0
GPMC_BE0n_CLE
GPMC_BE1n
Valid
FA10
FA3
FA12
GPMC_ADVn_ALE
FA4
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
Data IN 0
Data IN 0
GPMC_WAIT[j]
GPMC_06
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], jis equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-51. GPMC and NOR Flash — Asynchronous Read — Single Word
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GPMC_FCLK
GPMC_CLK
FA5
FA5
FA1
FA1
GPMC_CSn[i]
FA16
FA9
FA9
Address 0
FA0
Address 1
FA0
GPMC_A[MSB:1]
FA10
FA10
Valid
FA0
Valid
FA0
GPMC_BE0n_CLE
GPMC_BE1n
Valid
Valid
FA10
FA10
FA3
FA3
FA12
FA12
GPMC_ADCn_ALE
FA4
FA4
FA13
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
Data Upper
GPMC_WAIT[j]
GPMC_07
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-52. GPMC and NOR Flash — Asynchronous Read — 32–Bit
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GPMC_FCLK
GPMC_CLK
FA20
Add3
FA20
Add1
FA21
FA20
Add2
FA1
GPMC_CSn[i]
FA9
Add0
Add4
GPMC_A[MSB:1]
FA0
FA10
FA10
GPMC_BE0n_CLE
FA0
GPMC_BE1n
FA12
GPMC_ADVn_ALE
FA18
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
D3
D0
D1
D2
D3
GPMC_WAIT[j]
GPMC_08
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by
active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC
functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first
input page data). FA20 value must be stored in PageBurstAccessTime register bits field.
D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-53. GPMC and NOR Flash — Asynchronous Read — Page Mode 4x16–Bit
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GPMC_FCLK
GPMC_CLK
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1]
Valid Address
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
FA29
GPMC_AD[15:0]
GPMC_WAIT[j]
Data OUT
GPMC_09
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-54. GPMC and NOR Flash — Asynchronous Write — Single Word
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GPMC_FCLK
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GPMC_CLK
FA1
FA5
GPMC_CSn[i]
FA9
Address (MSB)
FA0
GPMC_A[27:17]
FA10
FA10
GPMC_BE0n_CLE
GPMC_BE1n
Valid
FA0
Valid
FA3
FA12
GPMC_ADVn_ALE
GPMC_OEn_REn
FA4
FA13
FA29
FA37
Data IN
Data IN
Address (LSB)
GPMC_AD[15:0]
GPMC_WAIT[j]
GPMC_10
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-55. GPMC and Multiplexed NOR Flash — Asynchronous Read — Single Word
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GPMC_FCLK
GPMC_CLK
FA1
GPMC_CSn[i]
FA9
GPMC_A[27:17]
Address (MSB)
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
FA29
FA28
GPMC_AD[15:0]
Valid Address (LSB)
Data OUT
GPMC_WAIT[j]
GPMC_11
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-56. GPMC and Multiplexed NOR Flash — Asynchronous Write — Single Word
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7.9.5.11.3 GPMC and NAND Flash — Asynchronous Mode
Table 7-65 and Table 7-66 present timing requirements and switching characteristics for GPMC and NAND Flash
— Asynchronous Mode.
Table 7-65. GPMC and NAND Flash Timing Requirements – Asynchronous Mode
see Figure 7-59
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(4)
UNIT
133 MHz
GNF12(1) tacc(d)
Access time, input data GPMC_AD[15:0](3)
div_by_1_mode;
GPMC_FCLK_MUX;
J(2) ns
TIMEPARAGRANULARITY_X1
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(4) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
–
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
Table 7-66. GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
see Figure 7-57, Figure 7-58, Figure 7-59 and Figure 7-60
NO.
PARAMETER
MODE(4)
MIN
MAX UNIT
GNF0 tw(wenV)
Pulse duration, output write enable GPMC_WEn
valid
div_by_1_mode;
GPMC_FCLK_MUX;
A
ns
TIMEPARAGRANULARITY_X1
GNF1 td(csnV-wenV)
GNF2 tw(cleH-wenV)
GNF3 tw(wenV-dV)
GNF4 tw(wenIV-dIV)
GNF5 tw(wenIV-cleIV)
Delay time, output chip select GPMC_CSn[i](2)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
B - 2
C - 2
D - 2
E - 2
F - 2
G - 2
C - 2
B + 2 ns
C + 2 ns
D + 2 ns
E + 2 ns
F + 2 ns
G + 2 ns
C + 2 ns
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE high to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output data GPMC_AD[15:0] valid to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output write enable GPMC_WEn
invalid to output data GPMC_AD[15:0] invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output write enable GPMC_WEn
invalid to output lower-byte enable and command
latch enable GPMC_BE0n_CLE invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn
invalid to output chip select GPMC_CSn[i](2)
invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF7 tw(aleH-wenV)
Delay time, output address valid and address latch
enable GPMC_ADVn_ALE high to output write
enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
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Table 7-66. GPMC and NAND Flash Switching Characteristics – Asynchronous Mode (continued)
see Figure 7-57, Figure 7-58, Figure 7-59 and Figure 7-60
NO.
PARAMETER
MODE(4)
MIN
MAX UNIT
GNF8 tw(wenIV-aleIV)
Delay time, output write enable GPMC_WEn
invalid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F - 2
F + 2 ns
GNF9 tc(wen)
Cycle time, write
div_by_1_mode;
GPMC_FCLK_MUX;
H
ns
TIMEPARAGRANULARITY_X1
GNF10 td(csnV-oenV)
GNF13 tw(oenV)
GNF14 tc(oen)
Delay time, output chip select GPMC_CSn[i](2)
valid to output enable GPMC_OEn_REn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
I - 2
I + 2 ns
Pulse duration, output enable GPMC_OEn_REn
valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
K
ns
ns
Cycle time, read
div_by_1_mode;
GPMC_FCLK_MUX;
L
TIMEPARAGRANULARITY_X1
GNF15 tw(oenIV-CSn[i]V) Delay time, output enable GPMC_OEn_REn
invalid to output chip select GPMC_CSn[i](2)
invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
M - 2
M + 2 ns
(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(3)
(2) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(4) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
–
•
•
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
GPMC_FCLK
GPMC_CSn[i]
GNF1
GNF2
GNF6
GNF5
GPMC_BE0n_CLE
GPMC_ADCn_ALE
GPMC_OEn_REn
GPMC_WEn
GNF0
GNF3
GNF4
GPMC_AD[15:0]
Command
GPMC_12
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
Figure 7-57. GPMC and NAND Flash — Command Latch Cycle
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GPMC_FCLK
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GNF1
GNF7
GNF6
GNF8
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GPMC_WEn
GNF9
GNF0
GNF3
GNF4
Address
GPMC_AD[15:0]
GPMC_13
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
Figure 7-58. GPMC and NAND Flash — Address Latch Cycle
GPMC_FCLK
GPMC_CSn[i]
GNF12
GNF10
GNF15
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GNF14
GNF13
GPMC_OEn_REn
GPMC_AD[15:0]
GPMC_WAIT[j]
DATA
GPMC_14
A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-59. GPMC and NAND Flash — Data Read Cycle
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GPMC_FCLK
GPMC_CSn[i]
GNF1
GNF6
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GNF9
GNF0
GPMC_WEn
GNF3
GNF4
GPMC_AD[15:0]
DATA
GPMC_15
A. `In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
Figure 7-60. GPMC and NAND Flash — Data Write Cycle
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7.9.5.12 I2C
The device contains six multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was
designed to be compliant to the Philips I2C-bus™ specification version 2.1. However, the device IOs are not
fully compliant to the I2C electrical specification. The speeds supported and exceptions are described per port
below:
•
I2C0, I2C1, I2C2, and I2C3
– Speeds:
•
Standard-mode (up to 100 Kbits/s)
– 1.8 V
– 3.3 V
•
Fast-mode (up to 400 Kbits/s)
– 1.8 V
– 3.3 V
– Exceptions:
•
The IOs associated with these ports are not compliant to the fall time requirements defined in the I2C
specification because they are implemented with higher performance LVCMOS push-pull IOs that were
designed to support other signal functions that could not be implemented with I2C compatible IOs. The
LVCMOS IOs being used on these ports are connected such they emulate open-drain outputs. This
emulation is achieved by forcing a constant low output and disabling the output buffer to enter the Hi-Z
state.
•
The I2C specification defines a maximum input voltage VIH of (VDD + 0.5 V), which exceeds the
absolute maximum ratings for the device IOs. The system must bemdaex signed to ensure the I2C signals
never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.
•
MCU_I2C0 and WKUP_I2C0
– Speeds:
•
•
•
Standard-mode (up to 100 Kbits/s)
– 1.8 V
– 3.3 V
Fast-mode (up to 400 Kbits/s)
– 1.8 V
– 3.3 V
Hs-mode (up to 3.4 Mbits/s)
– 1.8 V
– Exceptions:
•
The IOs associated with these ports were not design to support Hs-mode while operating at 3.3 V. So
Hs-mode is limited to 1.8-V operation.
•
The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of 0.8
V/ns (or 8E+7 V/s). This limit is more restrictive than the minimum fall time limits defined in the I2C
specification. Therefore, it may be necessary to add additional capacitance to the I2C signals to slow
the rise and fall times such that they do not exceed a slew rate of 0.8 V/ns.
•
The I2C specification defines a maximum input voltage VIH of (VDD + 0.5 V), which exceeds the
absolute maximum ratings for the device IOs. The system must bemdaex signed to ensure the I2C signals
never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.
Note
I2C3 has one or more signals which can be multiplexed to more than one pin. Timing is only valid for
specific pin combinations known as IOSETs. Valid pin combinations or IOSETs for this interface are
defined in the SysConfig-PinMux Tool.
Refer to the Philips I2C-bus specification version 2.1 for timing details.
For more details about features and additional description information on the device Inter-Integrated Circuit, see
the corresponding subsections within Signal Descriptions and Detailed Description sections.
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7.9.5.13 MCAN
Table 7-67 and Table 7-68 presents timing conditions and switching characteristics for MCAN.
For more details about features and additional description information on the device Controller Area Network
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Note
The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names,
where n represents the specific MCAN module.
Table 7-67. MCAN Timing Conditions
PARAMETER
MIN
2
MAX
15
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
5
20
Table 7-68. MCAN Switching Characteristics
NO.
PARAMETER
DESCRIPTION
Delay time, transmit shift register to MCANn_TX
Delay time, MCANn_RX to receive shift register
MIN
MAX
10
UNIT
ns
MCAN1 td(MCAN_TX)
MCAN2 td(MCAN_RX)
10
ns
For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM.
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7.9.5.14 MCASP
Note
McASP has one or more signals which can be multiplexed to more than one pin. Timing requirements
and switching characteristics defined in this section are only valid for specific pin combinations known
as IOSETs. Valid pin combinations or IOSETs for this interface are defined in the SysConfig-PinMux
Tool.
Table 7-69, Table 7-70, Figure 7-61, Table 7-71, and Figure 7-62 present timing conditions, requirements, and
switching characteristics for MCASP.
Table 7-69. MCASP Timing Conditions
PARAMETER
MIN
0.7
1
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
10
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
Propagation delay of each trace
100
1100
100
ps
ps
td(Trace Mismatch Delay)
Propagation delay mismatch across all traces
Table 7-70. MCASP Timing Requirements
see Figure 7-61
NO.
MODE(1)
MIN
20
MAX UNIT
ASP1 tc(AHCLKRX)
ASP2 tw(AHCLKRX)
ASP3 tc(ACLKRX)
ASP4 tw(ACLKRX)
Cycle time, MCASP[x]_AHCLKR/X(4)
ns
ns
0.5P(2)
-
Pulse duration, MCASP[x]_AHCLKR/X(4) high or low
Cycle time, MCASP[x]_ACLKR/X(4)
1.53
20
ns
ns
0.5R(3)
-
Pulse duration, MCASP[x]_ACLKR/X(4) high or low
1.53
Setup time, MCASP[x]_AFSR/X(4) input valid before
MCASP[x]_ACLKR/X(4)
ACLKR/X int
9.29
4
ns
ns
ns
ns
ASP5 tsu(AFSRX-ACLKRX)
ASP6 th(ACLKRX-AFSRX)
ASP7 tsu(AXR-ACLKRX)
ASP8 th(ACLKRX-AXR)
ACLKR/X ext in/out
ACLKR/X int
Hold time, MCASP[x]_AFSR/X(4) input valid after
MCASP[x]_ACLKR/X(4)
-1
ACLKR/X ext in/out
ACLKR/X int
1.6
9.29
4
Setup time, MCASP[x]_AXR(4) input valid before
MCASP[x]_ACLKR/X(4)
ACLKR/X ext in/out
ACLKR/X int
Hold time, MCASP[x]_AXR(4) input valid after
MCASP[x]_ACLKR/X(4)
-1
ACLKR/X ext in/out
1.6
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
(4) x in MCASP[x]_* is 0, 1 or 2
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ASP2
ASP2
ASP1
MCASP[x]_ACLKR/X (Falling Edge Polarity)
MCASP[x]_AHCLKR/X (Rising Edge Polarity)
ASP4
ASP4
ASP3
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(B)
ASP6
ASP5
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
ASP8
ASP7
MCASP[x]_AXR[x] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured
for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured
for rising edge (to shift data in).
Figure 7-61. MCASP Timing Requirements
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Table 7-71. MCASP Switching Characteristics
see Figure 7-62
NO.
PARAMETER
DESCRIPTION
MODE(1)
MIN
20
MAX UNIT
ASP9 tc(AHCLKRX)
ASP10 tw(AHCLKRX)
ASP11 tc(ACLKRX)
ASP12 tw(ACLKRX)
Cycle time, MCASP[x]_AHCLKR/X(4)
ns
ns
ns
ns
Pulse duration, MCASP[x]_AHCLKR/X(4) high or low
Cycle time, MCASP[x]_ACLKR/X(4)
0.5P(2) - 2
20
Pulse duration, MCASP[x]_ACLKR/X(4) high or low
0.5R(3) - 2
-1
Delay time, MCASP[x]_ACLKR/X(4) transmit edge to
MCASP[x]_AFSR/X(4) output valid
ACLKR/X int
7.25
ns
12.84
ASP13 td(ACLKRX-AFSRX)
ASP14 td(ACLKX-AXR)
ASP15 tdis(ACLKX-AXR)
ACLKR/X ext in/out
ACLKR/X int
-15.29
-1
Delay time, MCASP[x]_ACLKX(4) transmit edge to
MCASP[x]_AXR(4) output valid
7.25
ns
12.84
ACLKR/X ext in/out
ACLKR/X int
-15.29
-1
Disable time, MCASP[x]_ACLKX(4) transmit edge to
MCASP[x]_AXR(4) output high impedance
7.25
ns
14
ACLKR/X ext in/out
-14.9
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
(4) x in MCASP[x]_* is 0, 1 or 2
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ASP10
ASP10
ASP9
MCASP[x]_ACLKR/X (Falling Edge Polarity)
MCASP[x]_AHCLKR/X (Rising Edge Polarity)
ASP12
ASP12
ASP11
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(B)
ASP13
ASP13
ASP13
ASP13
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
MCASP[x]_AXR[x] (Data Out/Transmit)
ASP13
ASP13
ASP13
ASP14
ASP15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured
for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured
for falling edge (to shift data in).
Figure 7-62. MCASP Switching Characteristics
For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device
TRM.
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7.9.5.15 MCSPI
Note
McSPI has one or more signals which can be multiplexed to more than one pin. Timing requirements
and switching characteristics defined in this section are only valid for specific pin combinations known
as IOSETs. Valid pin combinations or IOSETs for this interface are defined in the SysConfig-PinMux
Tool.
For more details about features and additional description information on the device Serial Port Interface, see
the corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 7-72 presents timing conditions for MCSPI.
Table 7-72. MCSPI Timing Conditions
PARAMETER
MIN
2
MAX
8.5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
6
12
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
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7.9.5.15.1 MCSPI — Controller Mode
Table 7-73, Figure 7-63, Table 7-74, and Figure 7-64 present timing requirements and switching characteristics
for SPI – Controller Mode.
Table 7-73. MCSPI Timing Requirements – Controller Mode
see Figure 7-63
NO.
SM4
SM5
PARAMETER
DESCRIPTION
MIN
2.8
3
MAX
UNIT
ns
tsu(POCI-SPICLK)
Setup time, SPIn_D[x] valid before SPIn_CLK active edge
Hold time, SPIn_D[x] valid after SPIn_CLK active edge
th(SPICLK-POCI)
ns
PHA=0
EPOL=1
SPI_CS[i] (OUT)
SPI_SCLK (OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
POL=1
SM1
SM3
SM2
SPI_SCLK (OUT)
SM5
SM5
SM4
SM4
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
SPI_D[x] (IN)
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SPI_SCLK (OUT)
SM2
SM1
SM8
SM3
SM2
SM9
POL=0
POL=1
SM1
SM3
SPI_SCLK (OUT)
SM5
SM4
SM5
Bit n-2
SM4
Bit n-1
Bit n-3
Bit 1
Bit 0
SPI_D[x] (IN)
SPRSP08_TIMING_McSPI_02
Figure 7-63. SPI Controller Mode Receive Timing
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Table 7-74. MCSPI Switching Characteristics - Controller Mode
see Figure 7-64
NO.
PARAMETER
MIN
20
0.5P - 1(1)
0.5P - 1(1)
-3
MAX UNIT
SM1
SM2
SM3
SM6
SM7
SM8
tc(SPICLK)
Cycle time, SPIn_CLK
ns
ns
ns
tw(SPICLKL)
tw(SPICLKH)
td(SPICLK-PICO)
td(CS-PICO)
td(CS-SPICLK)
Pulse duration, SPIn_CLK low
Pulse duration, SPIn_CLK high
Delay time, SPIn_CLK active edge to SPIn_D[x]
Delay time, SPIn_CSi active edge to SPIn_D[x]
Delay time, SPIn_CSi active to SPIn_CLK first edge
2.5
ns
ns
ns
ns
ns
ns
5
PHA = 0
PHA = 1
PHA = 0
PHA = 1
B - 4 (3)
A - 4 (2)
A - 4(2)
B - 4(3)
SM9
td(SPICLK-CS)
Delay time, SPIn_CLK last edge to SPIn_CSi inactive
(1) P = SPI_CLK period in ns.
(2) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A =
(TCS + 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
(3) B = (TCS + .5) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2.
PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
POL=1
SPI_SCLK (OUT)
SM1
SM3
SM2
SPI_SCLK (OUT)
SPI_D[x] (OUT)
SM7
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SPI_SCLK (OUT)
SM1
SM2
SM8
SM3
SM2
SM9
POL=0
POL=1
SM1
SM3
SPI_SCLK (OUT)
SPI_D[x] (OUT)
SM6
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
SM6
Bit 1
Bit0
SPRSP08_TIMING_McSPI_01
Figure 7-64. SPI Controller Mode Transmit Timing
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7.9.5.15.2 MCSPI — Peripheral Mode
Table 7-75, Figure 7-65, Table 7-76, and Figure 7-66 present timing requirements and switching characteristics
for SPI – Peripheral Mode.
Table 7-75. MCSPI Timing Requirements – Peripheral Mode
see Figure 7-65
NO.
SS1
SS2
SS3
SS4
SS5
SS8
SS9
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
ns
tc(SPICLK)
Cycle time, SPIn_CLK
20
0.45P(1)
0.45P(1)
tw(SPICLKL)
Pulse duration, SPIn_CLK low
ns
tw(SPICLKH)
Pulse duration, SPIn_CLK high
ns
tsu(PICO-SPICLK)
th(SPICLK-PICO)
tsu(CS-SPICLK)
th(SPICLK-CS)
Setup time, SPIn_D[x] valid before SPIn_CLK active edge
Hold time, SPIn_D[x] valid after SPIn_CLK active edge
Setup time, SPIn_CSi valid before SPIn_CLK first edge
Hold time, SPIn_CSi valid after SPIn_CLK last edge
5
5
5
5
ns
ns
ns
ns
(1) P = SPIn_CLK period in ns.
PHA=0
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
SPI_SCLK (IN)
SS1
SS2
POL=1
SPI_SCLK (IN)
SS5
SS4
SS5
Bit n-2
SS4
Bit n-1
Bit n-3
Bit n-4
Bit 0
SPI_D[x] (IN)
PHA=1
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
SPI_SCLK (IN)
SS1
SS3
POL=1
SPI_SCLK (IN)
SS4
SS5
SS4
SS5
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
SPI_D[x] (IN)
SPRSP08_TIMING_McSPI_04
Figure 7-65. SPI Peripheral Mode Receive Timing
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Table 7-76. MCSPI Switching Characteristics – Peripheral Mode
see Figure 7-66
NO.
SS6
SS7
PARAMETER
td(SPICLK-POCI)
tsk(CS-POCI)
DESCRIPTION
Delay time, SPIn_CLK active edge to SPIn_D[x]
Delay time, SPIn_CSi active edge to SPIn_D[x]
MIN
2
MAX
UNIT
ns
17.12
20.95
ns
PHA=0
EPOL=1
SPI_CS[i] (IN)
SPI_SCLK (IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
POL=1
SS1
SS2
SPI_SCLK (IN)
SPI_D[x] (OUT)
SS7
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (IN)
SPI_SCLK (IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
SS1
SS3
SPI_SCLK (IN)
SPI_D[x] (OUT)
SS6
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
SS6
Bit 1
Bit 0
SPRSP08_TIMING_McSPI_03
Figure 7-66. SPI Peripheral Mode Transmit Timing
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7.9.5.16 MMCSD
The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD),
and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at
transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking
for syntactical correctness.
For more details about MMCSD interfaces, see the corresponding MMC0, MMC1, and MMC2 subsections within
Signal Descriptions and Detailed Description sections.
Note
Some operating modes require software configuration of the MMC DLL delay settings, as shown in
Table 7-77 and Table 7-95.
The modes which show a value of "Tuning" in the ITAPDLYSEL column of Table 7-77 and Table 7-95
require a tuning algorithm to be used for optimizing input timing. Refer to the MMCSD Programming
Guide in the device TRM for more information on the tuning algorithm and configuration of input
delays required to optimize input timing.
For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in
the device TRM.
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7.9.5.16.1 MMC0 - eMMC/SD/SDIO Interface
MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and it supports the
following eMMC applications:
•
•
•
Legacy SDR
High Speed SDR
HS200
MMC0 interface is also compliant with the SD Host Controller Standard Specification 4.10 and SD Physical
Layer Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:
•
•
•
•
•
•
•
Default Speed
High Speed
UHS–I SDR12
UHS–I SDR25
UHS–I SDR50
UHS–I DDR50
UHS–I SDR104
Table 7-77 presents the required DLL software configuration settings for MMC0 timing modes.
Table 7-77. MMC0 DLL Delay Mapping for all Timing Modes
REGISTER NAME
BIT FIELD
MMCSD0_SS_PHY_CTRL_4_REG
[15:12] [8]
OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL
MMCSD0_SS_PHY_CTRL_5_REG
[20]
[4:0]
[2:0]
BIT FIELD NAME
CLKBUFSEL
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DELAY
BUFFER
DURATION
DELAY
ENABLE
DELAY
VALUE
MODE
DESCRIPTION
8-bit PHY operating
1.8 V, 25 MHz
0x0
0x0
0x0
0x0
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
NA(1)
NA(1)
NA(1)
NA(1)
0x6
0x0
0x0
0x0
0x0
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
NA(1)
NA(1)
0x7
0x7
0x7
0x7
0x7
0x7
0x7
0x7
0x7
0x7
0x7
0x7
Legacy
SDR
8-bit PHY operating
3.3 V, 25 MHz
8-bit PHY operating
1.8 V, 50 MHz
NA(1)
High
Speed
SDR
8-bit PHY operating
3.3 V, 50 MHz
NA(1)
8-bit PHY operating
1.8 V, 200 MHz
HS200
Tuning(2)
0x0
Default
Speed
4-bit PHY operating
3.3 V, 25 MHz
0x0
High
Speed
4-bit PHY operating
3.3 V, 50 MHz
0x0
0x0
UHS-I
SDR12
4-bit PHY operating
1.8 V, 25 MHz
0xF
0x0
UHS-I
SDR25
4-bit PHY operating
1.8 V, 50 MHz
0xF
0x0
UHS-I
SDR50
4-bit PHY operating
1.8 V, 100 MHz
0xC
0x9
Tuning(2)
Tuning(2)
Tuning(2)
UHS-I
DDR50
4-bit PHY operating
1.8 V, 50 MHz
UHS-I
SDR104
4-bit PHY operating
1.8, V 200 MHz
0x6
(1) NA means Not Applicable
(2) Tuning means this mode requires a tuning algorithm to be used for optimal input timing
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Table 7-78 presents timing conditions for MMC0.
Table 7-78. MMC0 Timing Conditions
PARAMETER
MIN
MAX UNIT
INPUT CONDITIONS
Legacy SDR @ 3.3 V
High Speed SDR@ 3.3V
Default Speed
0.69
0.14
2.06 V/ns
High Speed
Legacy SDR @ 1.8 V
UHS-I SDR12
SRI
Input slew rate
1.44 V/ns
1.34 V/ns
High Speed SDR @ 1.8 V
UHS-I SDR25
0.3
1
UHS-I DDR50
2
V/ns
OUTPUT CONDITIONS
HS200
UHS-I SDR104
1
1
10
12
pF
pF
CL
Output load capacitance
All other modes
PCB CONNECTIVITY REQUIREMENTS
Legacy SDR
High Speed SDR
HS200
126
756
ps
ps
Default Speed
High Speed
UHS-I SDR12
UHS-I SDR25
UHS-I SDR50
UHS-I SDR104
td(Trace Delay)
Propagation delay of each trace
126
239
1386
UHS-I DDR50
1134
8
ps
ps
High Speed SDR
HS200
High Speed
UHS-I SDR104
td(Trace Mismatch
Propagation delay mismatch across all
traces
Delay)
UHS-I DDR50
20
ps
ps
All other modes
100
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SPRSP77 – MARCH 2023
7.9.5.16.1.1 Legacy SDR Mode
Table 7-79, Figure 7-67, Table 7-80, and Figure 7-68 present timing requirements and switching characteristics
for MMC0 – Legacy SDR Mode.
Table 7-79. MMC0 Timing Requirements – Legacy SDR Mode
see Figure 7-67
IO
NO.
Operating
Voltage
MIN
MAX
UNIT
1.8 V
3.3 V
1.8 V
3.3 V
1.8 V
3.3 V
1.8 V
3.3 V
4.2
2.15
0.87
1.67
4.2
ns
ns
ns
ns
ns
ns
ns
ns
LSDR1
LSDR2
LSDR3
LSDR4
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
2.15
0.87
1.67
Figure 7-67. MMC0 – Legacy SDR – Receive Mode
Table 7-80. MMC0 Switching Characteristics – Legacy SDR Mode
see Figure 7-68
IO
NO.
PARAMETER
Operating
Voltage
MIN
MAX UNIT
fop(clk)
Operating frequency, MMC0_CLK
Cycle time, MMC0_CLK
25
MHz
ns
LSDR5
LSDR6
LSDR7
tc(clk)
40
18.7
18.7
-2.1
-1.8
-2.1
-1.8
tw(clkH)
tw(clkL)
Pulse duration, MMC0_CLK high
Pulse duration, MMC0_CLK low
ns
ns
1.8 V
3.3 V
1.8 V
3.3 V
2.1
2.2
2.1
2.2
ns
LSDR8
LSDR9
td(clkL-cmdV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
ns
ns
td(clkL-dV)
ns
Figure 7-68. MMC0 – Legacy SDR – Transmit Mode
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7.9.5.16.1.2 High Speed SDR Mode
Table 7-81, Figure 7-69, Table 7-82, and Figure 7-70 present timing requirements and switching characteristics
for MMC0 – High Speed SDR Mode.
Table 7-81. MMC0 Timing Requirements – High Speed SDR Mode
see Figure 7-69
IO
NO.
Operating
Voltage
MIN
MAX UNIT
1.8 V
3.3 V
1.8 V
3.3 V
1.8 V
3.3 V
1.8 V
3.3 V
2.15
2.24
1.27
1.66
2.15
2.24
1.27
1.66
ns
ns
ns
ns
ns
ns
ns
ns
HSSDR1
HSSDR2
HSSDR3
HSSDR4
tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
Figure 7-69. MMC0 – High Speed SDR Mode – Receive Mode
Table 7-82. MMC0 Switching Characteristics – High Speed SDR Mode
see Figure 7-70
IO
NO.
PARAMETER
Operating
Voltage
MIN
MAX UNIT
fop(clk)
Operating frequency, MMC0_CLK
Cycle time, MMC0_CLK
50
MHz
ns
HSSDR5
HSSDR6
HSSDR7
tc(clk)
20
9.2
tw(clkH)
tw(clkL)
Pulse duration, MMC0_CLK high
Pulse duration, MMC0_CLK low
ns
9.2
ns
1.8 V
3.3 V
1.8 V
3.3 V
-1.55
-1.8
-1.55
-1.8
3.05
2.2
ns
HSSDR8
HSSDR9
td(clkL-cmdV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
ns
3.05
2.2
ns
td(clkL-dV)
ns
Figure 7-70. MMC0 – High Speed SDR Mode – Transmit Mode
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SPRSP77 – MARCH 2023
7.9.5.16.1.3 HS200 Mode
Table 7-83 and Figure 7-71 present switching characteristics for MMC0 – HS200 Mode.
Table 7-83. MMC0 Switching Characteristics – HS200 Mode
see Figure 7-71
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
200
HS2005
HS2006
HS2007
HS2008
HS2009
tc(clk)
Cycle time, MMC0_CLK
5
2.12
2.12
1.07
1.07
tw(clkH)
Pulse duration, MMC0_CLK high
ns
tw(clkL)
Pulse duration, MMC0_CLK low
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition
3.21
3.21
ns
ns
Figure 7-71. MMC0 – HS200 Mode – Transmit Mode
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7.9.5.16.1.4 Default Speed Mode
Table 7-84, Figure 7-72, Table 7-85, and Figure 7-73 present timing requirements and switching characteristics
for MMC0 – Default Speed Mode.
Table 7-84. Timing Requirements for MMC0 – Default Speed Mode
see Figure 7-72
NO.
DS1
DS2
DS3
DS4
MIN
2.15
1.67
2.15
1.67
MAX
UNIT
ns
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge
ns
ns
ns
MMC[x]_CLK
DS2
DS4
DS1
DS3
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-72. MMC0 – Default Speed – Receive Mode
Table 7-85. Switching Characteristics for MMC0 – Default Speed Mode
see Figure 7-73
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
25
DS5
DS6
DS7
DS8
DS9
tc(clk)
Cycle time, MMC0_CLK
40
18.7
18.7
- 1.8
- 1.8
tw(clkH)
Pulse duration, MMC0_CLK high
ns
tw(clkL)
Pulse duration, MMC0_CLK low
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[3:0] transition
2.2
2.2
ns
ns
DS5
DS6
DS7
MMC[x]_CLK
MMC[x]_CMD
DS8
DS9
MMC[x]_DAT[3:0]
Figure 7-73. MMC0 – Default Speed – Transmit Mode
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SPRSP77 – MARCH 2023
7.9.5.16.1.5 High Speed Mode
Table 7-86, Figure 7-74, Table 7-87, and Figure 7-75 present timing requirements and switching characteristics
for MMC0 – High Speed Mode.
Table 7-86. Timing Requirements for MMC0 – High Speed Mode
see Figure 7-74
NO.
HS1
HS2
HS3
HS4
MIN
2.24
1.66
2.24
1.66
MAX
UNIT
ns
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge
ns
ns
ns
MMC[x]_CLK
HS1
HS3
HS2
HS4
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-74. MMC0 – High Speed – Receive Mode
Table 7-87. Switching Characteristics for MMC0 – High Speed Mode
see Figure 7-75
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
50
HS5
HS6
HS7
HS8
HS9
tc(clk)
Cycle time. MMC0_CLK
20
9.2
tw(clkH)
Pulse duration, MMC0_CLK high
ns
tw(clkL)
Pulse duration, MMC0_CLK low
9.2
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[3:0] transition
-1.8
-1.8
2.2
2.2
ns
ns
HS5
HS6
HS7
MMC[x]_CLK
HS8
HS9
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-75. MMC0 – High Speed – Transmit Mode
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7.9.5.16.1.6 UHS–I SDR12 Mode
Table 7-88, Figure 7-76, Table 7-89, and Figure 7-77 present timing requirements and switching characteristics
for MMC0 – UHS-I SDR12 Mode.
Table 7-88. Timing Requirements for MMC0 – UHS-I SDR12 Mode
see Figure 7-76
NO.
MIN
4.2
MAX
UNIT
ns
SDR121 tsu(cmdV-clkH)
SDR122 th(clkH-cmdV)
SDR123 tsu(dV-clkH)
SDR124 th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge
0.87
4.2
ns
ns
0.87
ns
MMC[x]_CLK
SDR122
SDR124
SDR121
SDR123
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-76. MMC0 – UHS-I SDR12 – Receive Mode
Table 7-89. Switching Characteristics for MMC0 – UHS-I SDR12 Mode
see Figure 7-77
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
25
SDR125 tc(clk)
Cycle time, MMC0_CLK
40
18.7
18.7
1.5
SDR126 tw(clkH)
SDR127 tw(clkL)
SDR128 td(clkL-cmdV)
SDR129 td(clkL-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
ns
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition
8.6
8.6
ns
1.5
ns
SDR125
SDR126
SDR127
MMC[x]_CLK
SDR128
SDR128
MMC[x]_CMD
SDR129
SDR129
MMC[x]_DAT[3:0]
Figure 7-77. MMC0 – UHS-I SDR12 – Transmit Mode
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SPRSP77 – MARCH 2023
7.9.5.16.1.7 UHS–I SDR25 Mode
Table 7-90, Figure 7-78, Table 7-91, and Figure 7-79 present timing requirements and switching characteristics
for MMC0 – UHS-I SDR25 Mode.
Table 7-90. Timing Requirements for MMC0 – UHS-I SDR25 Mode
see Figure 7-78
NO.
MIN
2.15
1.27
2.15
1.27
MAX
UNIT
ns
SDR251 tsu(cmdV-clkH)
SDR252 th(clkH-cmdV)
SDR253 tsu(dV-clkH)
SDR254 th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge
ns
ns
ns
MMC[x]_CLK
SDR252
SDR254
SDR251
SDR253
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-78. MMC0 – UHS-I SDR25 – Receive Mode
Table 7-91. Switching Characteristics for MMC0 – UHS-I SDR25 Mode
see Figure 7-79
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
50
SDR255 tc(clk)
Cycle time, MMC0_CLK
20
9.2
9.2
2.4
2.4
SDR256 tw(clkH)
SDR257 tw(clkL)
SDR258 td(clkL-cmdV)
SDR259 td(clkL-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
ns
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition
8.1
8.1
ns
ns
SDR255
SDR256
SDR257
MMC[x]_CLK
SDR258
SDR258
MMC[x]_CMD
SDR259
SDR259
MMC[x]_DAT[3:0]
Figure 7-79. MMC0 – UHS-I SDR25 – Transmit Mode
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7.9.5.16.1.8 UHS–I SDR50 Mode
Table 7-92 and Figure 7-80 presents switching characteristics for MMC0 – UHS-I SDR50 Mode.
Table 7-92. Switching Characteristics for MMC0 – UHS-I SDR50 Mode
see Figure 7-80
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
100
SDR505 tc(clk)
Cycle time, MMC0_CLK
10
4.45
4.45
1.2
SDR506 tw(clkH)
SDR507 tw(clkL)
SDR508 td(clkL-cmdV)
SDR509 td(clkL-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
ns
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition
6.35
6.35
ns
1.2
ns
SDR505
SDR506
SDR507
MMC[x]_CLK
SDR508
SDR508
MMC[x]_CMD
SDR509
SDR509
MMC[x]_DAT[3:0]
Figure 7-80. MMC0 – UHS-I SDR50 – Transmit Mode
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SPRSP77 – MARCH 2023
7.9.5.16.1.9 UHS–I DDR50 Mode
Table 7-93 and Figure 7-81 present switching characteristics for MMC0 – UHS-I DDR50 Mode.
Table 7-93. Switching Characteristics for MMC0 – UHS-I DDR50 Mode
see Figure 7-81
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
50
DDR505
DDR506
DDR507
DDR508
DDR509
tc(clk)
Cycle time, MMC0_CLK
20
9.2
tw(clkH)
tw(clkL)
td(clk-cmdV)
td(clk-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
9.2
ns
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK transition to MMC0_DAT[3:0] transition
1.12
1.12
6.43
6.43
ns
ns
DDR505
DDR506
DDR507
MMC[x]_CLK
MMC[x]_CMD
DDR508
DDR509
DDR509
MMC[x]_DAT[3:0]
Figure 7-81. MMC0 – UHS-I DDR50 – Transmit Mode
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7.9.5.16.1.10 UHS–I SDR104 Mode
Table 7-94 and Figure 7-82 present switching characteristics for MMC0 – UHS-I SDR104 Mode.
Table 7-94. Switching Characteristics for MMC0 – UHS-I SDR104 Mode
see Figure 7-82
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
200
SDR1045 tc(clk)
Cycle time, MMC0_CLK
5
2.12
2.12
1.07
1.07
SDR1046 tw(clkH)
SDR1047 tw(clkL)
SDR1048 td(clkL-cmdV)
SDR1049 td(clkL-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
ns
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition
3.21
3.21
ns
ns
SDR1045
SDR1046
SDR1047
MMC[x]_CLK
SDR1048
SDR1048
MMC[x]_CMD
SDR1049
SDR1049
MMC[x]_DAT[3:0]
Figure 7-82. MMC0 – UHS-I SDR104 – Transmit Mode
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SPRSP77 – MARCH 2023
7.9.5.16.2 MMC1/MMC2 - SD/SDIO Interface
MMC1/MMC2 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical
Layer Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:
•
•
•
•
•
•
•
Default speed
High speed
UHS–I SDR12
UHS–I SDR25
UHS–I SDR50
UHS–I DDR50
UHS–I SDR104
Table 7-95 presents the required DLL software configuration settings for MMC1/2 timing modes.
Table 7-95. MMC1/MMC2 DLL Delay Mapping for all Timing Modes
MMCSD1_SS_PHY_CTRL_4_REG/
MMCSD2_SS_PHY_CTRL_4_REG
MMCSD1_SS_PHY_CTRL_5_REG/
MMCSD2_SS_PHY_CTRL_5_REG
REGISTER NAME
BIT FIELD
[20]
[15:12]
[8]
[4:0]
[2:0]
BIT FIELD NAME
OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL
CLKBUFSEL
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DELAY
BUFFER
DURATION
DELAY
ENABLE
DELAY
VALUE
MODE
DESCRIPTION
Default
Speed
4-bit PHY operating
3.3 V, 25 MHz
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x0
0x0
0xF
0xF
0xC
0x9
0x6
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x0
0x0
0x7
0x7
0x7
0x7
0x7
0x7
0x7
High
Speed
4-bit PHY operating
3.3 V, 50 MHz
UHS-I
SDR12
4-bit PHY operating
1.8 V, 25 MHz
0x0
UHS-I
SDR25
4-bit PHY operating
1.8 V, 50 MHz
0x0
UHS-I
SDR50
4-bit PHY operating
1.8 V, 100 MHz
Tuning(1)
Tuning(1)
Tuning(1)
UHS-I
DR50
4-bit PHY operating
1.8 V, 50 MHz
UHS-I
SDR104
4-bit PHY operating
1.8, V 200 MHz
(1) Tuning means this mode requires a tuning algorithm to be used for optimal input timing
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MAX UNIT
SPRSP77 – MARCH 2023
Table 7-96 presents timing conditions for MMC1.
Table 7-96. MMC1/MMC2 Timing Conditions
PARAMETER
MIN
Input Conditions
Default Speed
High Speed
0.69
2.06 V/ns
1.34 V/ns
SRI
Input slew rate
UHS–I SDR12
UHS–I SDR25
0.34
1
UHS–I DDR50
2
V/ns
pF
Output Conditions
CL
Output load capacitance
All modes
1
10
PCB Connectivity Requirements
UHS–I DDR50
All other modes
239
126
1134
1386
ps
ps
td(Trace Delay)
Propagation delay of each trace
High Speed
UHS–I SDR104
8
ps
td(Trace Mismatch
Propagation delay mismatch across all
traces
UHS–I DDR50
All other modes
20
ps
ps
Delay)
100
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7.9.5.16.2.1 Default Speed Mode
Table 7-97, Figure 7-83, Table 7-98, and Figure 7-84 present timing requirements and switching characteristics
for MMC1/MMC2 – Default Speed Mode.
Table 7-97. Timing Requirements for MMC1/MMC2 – Default Speed Mode
see Figure 7-83
NO.
DS1
DS2
DS3
DS4
MIN
2.15
1.67
2.15
1.67
MAX
UNIT
ns
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Setup time, MMCx_CMD valid before MMCx_CLK rising edge
Hold time, MMCx_CMD valid after MMCx_CLK rising edge
Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge
Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge
ns
ns
ns
MMC[x]_CLK
DS2
DS4
DS1
DS3
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-83. MMC1/MMC2 – Default Speed – Receive Mode
Table 7-98. Switching Characteristics for MMC1/MMC2 – Default Speed Mode
see Figure 7-84
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
25
DS5
DS6
DS7
DS8
DS9
tc(clk)
Cycle time, MMCx_CLK
40
18.7
18.7
- 1.8
- 1.8
tw(clkH)
Pulse duration, MMCx_CLK high
ns
tw(clkL)
Pulse duration, MMCx_CLK low
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMCx_CLK falling edge to MMCx_CMD transition
Delay time, MMCx_CLK falling edge to MMCx_DAT[3:0] transition
2.2
2.2
ns
ns
DS5
DS6
DS7
MMC[x]_CLK
MMC[x]_CMD
DS8
DS9
MMC[x]_DAT[3:0]
Figure 7-84. MMC1/MMC2 – Default Speed – Transmit Mode
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7.9.5.16.2.2 High Speed Mode
Table 7-99, Figure 7-85, Table 7-100, and Figure 7-86 present timing requirements and switching characteristics
for MMC1/MMC2 – High Speed Mode.
Table 7-99. Timing Requirements for MMC1/MMC2 – High Speed Mode
see Figure 7-85
NO.
HS1
HS2
HS3
HS4
MIN
2.24
1.66
2.24
1.66
MAX
UNIT
ns
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Setup time, MMCx_CMD valid before MMCx_CLK rising edge
Hold time, MMCx_CMD valid after MMCx_CLK rising edge
Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge
Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge
ns
ns
ns
MMC[x]_CLK
HS1
HS3
HS2
HS4
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-85. MMC1/MMC2 – High Speed – Receive Mode
Table 7-100. Switching Characteristics for MMC1/MMC2 – High Speed Mode
see Figure 7-86
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
50
HS5
HS6
HS7
HS8
HS9
tc(clk)
Cycle time. MMCx_CLK
20
9.2
tw(clkH)
Pulse duration, MMCx_CLK high
ns
tw(clkL)
Pulse duration, MMCx_CLK low
9.2
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMCx_CLK falling edge to MMCx_CMD transition
Delay time, MMCx_CLK falling edge to MMCx_DAT[3:0] transition
- 1.8
- 1.8
2.2
2.2
ns
ns
HS5
HS6
HS7
MMC[x]_CLK
HS8
HS9
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-86. MMC1/MMC2 – High Speed – Transmit Mode
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7.9.5.16.2.3 UHS–I SDR12 Mode
Table 7-101, Figure 7-87, Table 7-102, and Figure 7-88 present timing requirements and switching
characteristics for MMC1/MMC2 – UHS-I SDR12 Mode.
Table 7-101. Timing Requirements for MMC1/MMC2 – UHS-I SDR12 Mode
see Figure 7-87
NO.
MIN
4.2
MAX
UNIT
ns
SDR121 tsu(cmdV-clkH)
SDR122 th(clkH-cmdV)
SDR123 tsu(dV-clkH)
SDR124 th(clkH-dV)
Setup time, MMCx_CMD valid before MMCx_CLK rising edge
Hold time, MMCx_CMD valid after MMCx_CLK rising edge
Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge
Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge
0.87
4.2
ns
ns
0.87
ns
MMC[x]_CLK
SDR122
SDR124
SDR121
SDR123
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-87. MMC1/MMC2 – UHS-I SDR12 – Receive Mode
Table 7-102. Switching Characteristics for MMC1/MMC2 – UHS-I SDR12 Mode
see Figure 7-88
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
25
SDR125 tc(clk)
Cycle time, MMCx_CLK
40
18.7
18.7
1.5
SDR126 tw(clkH)
SDR127 tw(clkL)
SDR128 td(clkL-cmdV)
SDR129 td(clkL-dV)
Pulse duration, MMCx_CLK high
ns
Pulse duration, MMCx_CLK low
ns
Delay time, MMCx_CLK rising edge to MMCx_CMD transition
Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition
8.6
8.6
ns
1.5
ns
SDR125
SDR126
SDR127
MMC[x]_CLK
SDR128
SDR128
MMC[x]_CMD
SDR129
SDR129
MMC[x]_DAT[3:0]
Figure 7-88. MMC1/MMC2 – UHS-I SDR12 – Transmit Mode
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7.9.5.16.2.4 UHS–I SDR25 Mode
Table 7-103, Figure 7-89, Table 7-104, and Figure 7-90 present timing requirements and switching
characteristics for MMC1/MMC2 – UHS-I SDR25 Mode.
Table 7-103. Timing Requirements for MMC1/MMC2 – UHS-I SDR25 Mode
see Figure 7-89
NO.
MIN
2.15
1.27
2.15
1.27
MAX
UNIT
ns
SDR251 tsu(cmdV-clkH)
SDR252 th(clkH-cmdV)
SDR253 tsu(dV-clkH)
SDR254 th(clkH-dV)
Setup time, MMCx_CMD valid before MMCx_CLK rising edge
Hold time, MMCx_CMD valid after MMCx_CLK rising edge
Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge
Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge
ns
ns
ns
MMC[x]_CLK
SDR252
SDR254
SDR251
SDR253
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-89. MMC1/MMC2 – UHS-I SDR25 – Receive Mode
Table 7-104. Switching Characteristics for MMC1/MMC2 – UHS-I SDR25 Mode
see Figure 7-90
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
50
SDR255 tc(clk)
Cycle time, MMCx_CLK
20
9.2
9.2
2.4
2.4
SDR256 tw(clkH)
SDR257 tw(clkL)
SDR258 td(clkL-cmdV)
SDR259 td(clkL-dV)
Pulse duration, MMCx_CLK high
ns
Pulse duration, MMCx_CLK low
ns
Delay time, MMCx_CLK rising edge to MMCx_CMD transition
Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition
8.1
8.1
ns
ns
SDR255
SDR256
SDR257
MMC[x]_CLK
SDR258
SDR258
MMC[x]_CMD
SDR259
SDR259
MMC[x]_DAT[3:0]
Figure 7-90. MMC1/MMC2 – UHS-I SDR25 – Transmit Mode
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7.9.5.16.2.5 UHS–I SDR50 Mode
Table 7-105 and Figure 7-91 presents switching characteristics for MMC1/MMC2 – UHS-I SDR50 Mode.
Table 7-105. Switching Characteristics for MMC1/MMC2 – UHS-I SDR50 Mode
see Figure 7-91
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
100
SDR505 tc(clk)
Cycle time, MMCx_CLK
10
4.45
4.45
1.2
SDR506 tw(clkH)
SDR507 tw(clkL)
SDR508 td(clkL-cmdV)
SDR509 td(clkL-dV)
Pulse duration, MMCx_CLK high
ns
Pulse duration, MMCx_CLK low
ns
Delay time, MMCx_CLK rising edge to MMCx_CMD transition
Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition
6.35
6.35
ns
1.2
ns
SDR505
SDR506
SDR507
MMC[x]_CLK
SDR508
SDR508
MMC[x]_CMD
SDR509
SDR509
MMC[x]_DAT[3:0]
Figure 7-91. MMC1/MMC2 – UHS-I SDR50 – Transmit Mode
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7.9.5.16.2.6 UHS–I DDR50 Mode
Table 7-106 and Figure 7-92 present switching characteristics for MMC1/MMC2 – UHS-I DDR50 Mode.
Table 7-106. Switching Characteristics for MMC1/MMC2 – UHS-I DDR50 Mode
see Figure 7-92
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
50
DDR505
DDR506
DDR507
DDR508
DDR509
tc(clk)
Cycle time, MMCx_CLK
20
9.2
tw(clkH)
tw(clkL)
td(clk-cmdV)
td(clk-dV)
Pulse duration, MMCx_CLK high
ns
Pulse duration, MMCx_CLK low
9.2
ns
Delay time, MMCx_CLK rising edge to MMCx_CMD transition
Delay time, MMCx_CLK transition to MMCx_DAT[3:0] transition
1.12
1.12
6.43
6.43
ns
ns
DDR505
DDR506
DDR507
MMC[x]_CLK
MMC[x]_CMD
DDR508
DDR509
DDR509
MMC[x]_DAT[3:0]
Figure 7-92. MMC1/MMC2 – UHS-I DDR50 – Transmit Mode
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7.9.5.16.2.7 UHS–I SDR104 Mode
Table 7-107 and Figure 7-93 present switching characteristics for MMC1/MMC2 – UHS-I SDR104 Mode.
Table 7-107. Switching Characteristics for MMC1/MMC2 – UHS-I SDR104 Mode
see Figure 7-93
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
200
SDR1045 tc(clk)
Cycle time, MMCx_CLK
5
2.12
2.12
1.07
1.07
SDR1046 tw(clkH)
SDR1047 tw(clkL)
SDR1048 td(clkL-cmdV)
SDR1049 td(clkL-dV)
Pulse duration, MMCx_CLK high
ns
Pulse duration, MMCx_CLK low
ns
Delay time, MMCx_CLK rising edge to MMCx_CMD transition
Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition
3.21
3.21
ns
ns
SDR1045
SDR1046
SDR1047
MMC[x]_CLK
SDR1048
SDR1048
MMC[x]_CMD
SDR1049
SDR1049
MMC[x]_DAT[3:0]
Figure 7-93. MMC1/MMC2 – UHS-I SDR104 – Transmit Mode
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7.9.5.17 OSPI
OSPI0 offers two data capture modes, PHY mode and Tap mode.
PHY mode uses an internal reference clock to transmit and receive data via a DLL based PHY, where each
reference clock cycle produces a single cycle of OSPI0_CLK for Single Data Rate (SDR) transfers or a half
cycle of OSPI0_CLK for Double Data Rate (DDR) transfers. PHY mode supports four clocking topologies
for the receive data capture clock. Internal PHY Loopback - uses the internal reference clock as the PHY
receive data capture clock. Internal Pad Loopback - uses OSPI0_LBCLKO looped back into the PHY from the
OSPI0_LBCLKO pin as the PHY receive data capture clock. External Board Loopback - uses OSPI0_LBCLKO
looped back into the PHY from the OSPI0_DQS pin as the PHY receive data capture clock. DQS - uses the DQS
output from the attached device as the PHY receive data capture clock. SDR transfers are not supported when
using the Internal Pad Loopback and DQS clocking topologies. DDR transfers are not supported when using the
Internal PHY Loopback or Internal Pad Loopback clocking topologies.
Tap mode uses an internal reference clock with selectable taps to adjusted data transmit and receive capture
delays relative to OSPI0_CLK, which is a divide by 4 of the internal reference clock for SDR transfers or a divide
by 8 of the internal reference clock for DDR transfers. Tap mode only supports one clocking topology for the
receive data capture clock. No Loopback - uses the internal reference clock as the Tap receive data capture
clock. This clocking topology supports a maximum internal reference clock rate of 200 MHz, which produces an
OSPI0_CLK rate up to 50 MHz for SDR mode or 25 MHz for DDR mode.
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device
TRM.
For more details about features and additional description information on the device Octal Serial Peripheral
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Section 7.9.5.17.1 defines timing requirements and switching characteristics associated with PHY mode and
Section 7.9.5.17.2 defines timing requirements and switching characteristics associated with Tap mode.
Table 7-108 presents timing conditions for OSPI0.
Table 7-108. OSPI0 Timing Conditions
PARAMETER
MODE
MIN
1
MAX UNIT
INPUT CONDITIONS
SRI Input slew rate
OUTPUT CONDITIONS
6
V/ns
pF
CL
Output load capacitance
3
10
PCB CONNECTIVITY REQUIREMENTS
No Loopback
Propagation delay of OSPI0_CLK trace
Internal PHY Loopback
Internal Pad Loopback
450
ps
td(Trace Delay)
Propagation delay of OSPI0_LBCLKO
trace
External Board Loopback
DQS
2L(1) - 30
L(1) - 30
2L(1) + 30
L(1) + 30
ps
ps
Propagation delay of OSPI0_DQS trace
Propagation delay mismatch of
OSPI0_D[7:0] and OSPI0_CSn[3:0]
relative to OSPI0_CLK
td(Trace Mismatch
All modes
60
ps
Delay)
(1) L = Propagation delay of OSPI0_CLK trace
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SPRSP77 – MARCH 2023
7.9.5.17.1 OSPI0 PHY Mode
7.9.5.17.1.1 OSPI0 With PHY Data Training
Read and write data valid windows will shift due to variation in process, voltage, temperature, and operating
frequency. A data training method may be implemented to dynamically configure optimal read and write timing.
Implementing data training enables proper operation across temperature with a specific process, voltage, and
frequency operating condition, while achieving a higher operating frequency.
Data transmit and receive timing parameters are not defined for the data training use case since they are
dynamically adjusted based on the operating condition.
Table 7-109 defines DLL delays required for OSPI0 with Data Training. Table 7-110, Figure 7-94, Table 7-111,
and Figure 7-95 present timing requirements and switching characteristics for OSPI0 with Data Training.
Table 7-109. OSPI0 DLL Delay Mapping for PHY Data Training
MODE
OSPI_PHY_CONFIGURATION_REG BIT FIELD
DELAY VALUE
Transmit
All modes
Receive
(1)
PHY_CONFIG_TX_DLL_DELAY_FLD,
(2)
All modes
PHY_CONFIG_RX_DLL_DELAY_FLD
(1) Transmit DLL delay value determined by training software
(2) Receive DLL delay value determined by training software
Table 7-110. OSPI0 Timing Requirements – PHY Data Training
see Figure 7-94
NO.
MODE
MIN
MAX UNIT
Setup time, OSPI0_D[7:0] valid before
active OSPI0_DQS edge
(1)
O15 tsu(D-LBCLK)
O16 th(LBCLK-D)
DDR with DQS
ns
Hold time, OSPI0_D[7:0] valid after active
OSPI0_DQS edge
(1)
DDR with DQS
ns
(1) Minimum setup and hold time requirements for OSPI0_D[7:0] inputs are not defined when Data Training is used to find the optimum
data valid window.
OSPI_DQS
O15 O16 O15 O16
OSPI_D[i:0]
OSPI_TIMING_04
Figure 7-94. OSPI0 Timing Requirements – PHY Data Training, DDR with DQS
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Table 7-111. OSPI Switching Characteristics – PHY Data Training
See Figure 7-95
NO.
PARAMETER
MODE
1.8V, DDR
3.3V, DDR
DDR
MIN
6.02
MAX UNIT
ns
ns
ns
ns
O1
tc(CLK)
Cycle time, OSPI0_CLK
7.52
O2
O3
tw(CLKL)
tw(CLKH)
Pulse duration, OSPI0_CLK low
Pulse duration, OSPI0_CLK high
((0.475P(1)) - 0.3)
((0.475P(1)) - 0.3)
DDR
((0.475P(1)) +
(0.975M(2)R(4)) +
(0.04TD(5)) - 1)
((0.525P(1)) +
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
O4
td(CSn-CLK)
DDR
(1.025M(2)R(4)) +
(0.11TD(5)) + 1)
ns
((0.475P(1)) +
(0.975N(3)R(4)) -
(0.04TD(5)) - 1)
((0.525P(1)) +
(1.025N(3)R(4)) -
(0.11TD(5)) + 1)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
O5
O6
td(CLK-CSn)
DDR
DDR
ns
ns
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
(6)
(6)
td(CLK-D)
(1) P = OSPI0_CLK cycle time = SCLK period in ns
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) R = refclk cycle time in ns
(5) TD = PHY_CONFIG_TX_DLL_DELAY_FLD
(6) Minimum and maximum delay times for OSPI0_D[7:0] outputs are not defined when Data Training is used to find the optimum data
valid window.
OSPI_CSn
O4
O3
O5
OSPI_CLK
OSPI_D[i:0]
O2
O6
O6
O1
OSPI_TIMING_01
Figure 7-95. OSPI0 Switching Characteristics – PHY DDR Data Training
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SPRSP77 – MARCH 2023
7.9.5.17.1.2 OSPI0 Without Data Training
Note
Timing parameters defined in this section are only applicable when data training is not implemented
and DLL delays are configured as described in Table 7-112 and Table 7-115.
7.9.5.17.1.2.1 OSPI0 PHY SDR Timing
Table 7-112 defines DLL delays required for OSPI0 PHY SDR Mode. Table 7-113, Figure 7-96, Figure 7-97,
Table 7-114, and Figure 7-98 present timing requirements and switching characteristics for OSPI0 PHY SDR
Mode.
Table 7-112. OSPI0 DLL Delay Mapping for PHY SDR Timing Modes
MODE
OSPI_PHY_CONFIGURATION_REG BIT FIELD
DELAY VALUE
Transmit
All modes
Receive
PHY_CONFIG_TX_DLL_DELAY_FLD,
0x0
0x0
All modes
PHY_CONFIG_RX_DLL_DELAY_FLD
Table 7-113. OSPI0 Timing Requirements – PHY SDR Mode
see Figure 7-96 and Figure 7-97
NO.
MODE
MIN
4.8
MAX UNIT
1.8V, SDR with Internal PHY Loopback
3.3V, SDR with Internal PHY Loopback
1.8V, SDR with Internal PHY Loopback
3.3V, SDR with Internal PHY Loopback
1.8V, SDR with External Board Loopback
3.3V, SDR with External Board Loopback
1.8V, SDR with External Board Loopback
3.3V, SDR with External Board Loopback
ns
ns
ns
ns
ns
ns
ns
ns
Setup time, OSPI0_D[7:0] valid before
active OSPI0_CLK edge
O19 tsu(D-CLK)
O20 th(CLK-D)
O21 tsu(D-LBCLK)
O22 th(LBCLK-D)
5.19
-0.5
-0.5
0.6
Hold time, OSPI0_D[7:0] valid after active
OSPI0_CLK edge
Setup time, OSPI0_D[7:0] valid before
active OSPI0_DQS edge
0.9
1.7
Hold time, OSPI0_D[7:0] valid after active
OSPI0_DQS edge
2.0
OSPI_CLK
O19
O20
OSPI_D[i:0]
OSPI_TIMING_05
Figure 7-96. OSPI0 Timing Requirements – PHY SDR with Internal PHY Loopback
OSPI_DQS
O21
O22
OSPI_D[i:0]
OSPI_TIMING_06
Figure 7-97. OSPI0 Timing Requirements – PHY SDR with External Board Loopback
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Table 7-114. OSPI0 Switching Characteristics – PHY SDR Mode
see Figure 7-98
NO.
PARAMETER
MODE
1.8V
MIN
7
MAX UNIT
ns
ns
ns
ns
O7
tc(CLK)
Cycle time, OSPI0_CLK
3.3V
6.03
O8
O9
tw(CLKL)
tw(CLKH)
Pulse duration, OSPI0_CLK low
Pulse duration, OSPI0_CLK high
((0.475P(1)) - 0.3)
((0.475P(1)) - 0.3)
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
((0.475P(1)) +
((0.525P(1)) +
O10 td(CSn-CLK)
O11 td(CLK-CSn)
ns
ns
(0.975M(2)R(4)) - 1) (1.025M(2)R(4)) + 1)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
((0.475P(1)) +
((0.525P(1)) +
(0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)
1.8V
3.3V
-1.16
-1.33
1.25
1.51
ns
ns
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
O12 td(CLK-D)
(1) P = CLK cycle time = SCLK period in ns
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) R = refclk cycle time in ns
OSPI_CSn
O11
O10
O7
O9
O8
OSPI_CLK
OSPI_D[i:0]
O12
OSPI_TIMING_02
Figure 7-98. OSPI0 Switching Characteristics – PHY SDR
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7.9.5.17.1.2.2 OSPI0 PHY DDR Timing
Table 7-115 defines DLL delays required for OSPI0 PHY DDR Mode. Table 7-116, Figure 7-99, Table 7-117, and
Figure 7-100 present timing requirements and switching characteristics for OSPI0 PHY DDR Mode.
Table 7-115. OSPI0 DLL Delay Mapping for PHY DDR Timing Modes
MODE
OSPI_PHY_CONFIGURATION_REG BIT FIELD
DELAY VALUE
Transmit
1.8V
PHY_CONFIG_TX_DLL_DELAY_FLD
PHY_CONFIG_TX_DLL_DELAY_FLD
0x46
0x43
3.3V
Receive
1.8V, DQS
3.3V, DQS
PHY_CONFIG_RX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
0x15
0x3A
0x0
All other modes
Table 7-116. OSPI0 Timing Requirements – PHY DDR Mode
see Figure 7-99
NO.
MODE
MIN
0.53
MAX UNIT
1.8V, DDR with External Board Loopback
ns
ns
ns
ns
ns
ns
ns
ns
1.8V, DDR with DQS
3.3V, DDR with External Board Loopback
3.3V, DDR with DQS
-0.46
1.23
Setup time, OSPI0_D[7:0] valid before
active OSPI0_DQS edge
O15 tsu(D-LBCLK)
-0.66
1.24(1)
3.59
1.8V, DDR with External Board Loopback
1.8V, DDR with DQS
Hold time, OSPI0_D[7:0] valid after active
OSPI0_DQS edge
O16 th(LBCLK-D)
3.3V, DDR with External Board Loopback
3.3V, DDR with DQS
1.44(1)
7.92
(1) This Hold time requirement is larger than the Hold time provided by a typical OSPI/QSPI/SPI device. Therefore, the trace length
between the SoC and attached OSPI/QSPI/SPI device must be sufficiently long enough to ensure that the Hold time is met at the SoC.
The length of the SoC's external loopback clock (OSPI0_LBCLKO to OSPI0_DQS) may need to be shortened to compensate.
OSPI_DQS
O15 O16 O15 O16
OSPI_D[i:0]
OSPI_TIMING_04
Figure 7-99. OSPI0 Timing Requirements – PHY DDR with External Board Loopback or DQS
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Table 7-117. OSPI0 Switching Characteristics – PHY DDR Mode
see Figure 7-100
NO.
PARAMETER
MODE
MIN
19
MAX UNIT
O1
O2
O3
tc(CLK)
Cycle time, OSPI0_CLK
ns
ns
ns
tw(CLKL)
tw(CLKH)
Pulse duration, OSPI0_CLK low
Pulse duration, OSPI0_CLK high
((0.475P(1)) - 0.3)
((0.475P(1)) - 0.3)
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
((0.475P(1)) -
((0.525P(1)) -
O4
O5
td(CSn-CLK)
td(CLK-CSn)
ns
ns
(0.975M(2)R(4))) (1.025M(2)R(4)) + 7)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
((0.475P(1)) +
((0.525P(1)) +
(0.975N(3)R(4)) - 7)
(1.025N(3)R(4)))
1.8V
3.3V
-7.71
-7.71
-1.56
-1.56
ns
ns
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
O6
td(CLK-D)
(1) P = OSPI0_CLK cycle time = SCLK period in ns
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) R = refclk cycle time in ns
OSPI_CSn
O4
O3
O5
OSPI_CLK
O2
O6
O6
O1
OSPI_D[i:0]
OSPI_TIMING_01
Figure 7-100. OSPI0 Switching Characteristics – PHY DDR
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7.9.5.17.2 OSPI0 Tap Mode
7.9.5.17.2.1 OSPI0 Tap SDR Timing
Table 7-118, Figure 7-101, Table 7-119, and Figure 7-102 present timing requirements and switching
characteristics for OSPI0 Tap SDR Mode.
Table 7-118. OSPI0 Timing Requirements – Tap SDR Mode
see Figure 7-101
NO.
MODE
MIN
MAX UNIT
Setup time, OSPI0_D[7:0] valid before
active OSPI0_CLK edge
(10.4 -
O19 tsu(D-CLK)
No Loopback
ns
(0.975T(1)R(2)))
Hold time, OSPI0_D[7:0] valid after active
OSPI0_CLK edge
(0.7 +
O20 th(CLK-D)
No Loopback
ns
(0.975T(1)R(2)))
(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]
(2) R = refclk cycle time in ns
OSPI_CLK
O19
O20
OSPI_D[i:0]
OSPI_TIMING_05
Figure 7-101. OSPI0 Timing Requirements – Tap SDR, No Loopback
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Table 7-119. OSPI0 Switching Characteristics – Tap SDR Mode
see Figure 7-102
NO.
PARAMETER
MODE
MIN
20
MAX UNIT
O7
O8
O9
tc(CLK)
Cycle time, OSPI0_CLK
ns
ns
ns
tw(CLKL)
tw(CLKH)
Pulse duration, OSPI0_CLK low
Pulse duration, OSPI0_CLK high
((0.475P(1)) - 0.3)
((0.475P(1)) - 0.3)
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
((0.475P(1)) +
((0.525P(1)) +
O10 td(CSn-CLK)
O11 td(CLK-CSn)
O12 td(CLK-D)
ns
ns
ns
(0.975M(2)R(4)) - 1) (1.025M(2)R(4)) + 1)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
((0.475P(1)) +
((0.525P(1)) +
(0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
- 4.25
7.25
(1) P = CLK cycle time = SCLK period in ns
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) R = refclk cycle time in ns
OSPI_CSn
O11
O10
O7
O9
O8
OSPI_CLK
OSPI_D[i:0]
O12
OSPI_TIMING_02
Figure 7-102. OSPI0 Switching Characteristics – Tap SDR, No Loopback
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7.9.5.17.2.2 OSPI0 Tap DDR Timing
Table 7-120, Figure 7-103, Table 7-121, and Figure 7-104 present timing requirements and switching
characteristics for OSPI0 Tap DDR Mode.
Table 7-120. OSPI0 Timing Requirements – Tap DDR Mode
see Figure 7-103
NO.
MODE
MIN
MAX UNIT
Setup time, OSPI0_D[7:0] valid before
active OSPI0_CLK edge
(12.04 -
O13 tsu(D-CLK)
No Loopback
ns
(0.975T(1)R(2)))
Hold time, OSPI0_D[7:0] valid after active
OSPI0_CLK edge
(1.84 +
O14 th(CLK-D)
No Loopback
ns
(0.975T(1)R(2)))
(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]
(2) R = refclk cycle time in ns
OSPI_CLK
O13 O14 O13 O14
OSPI_D[i:0]
OSPI_TIMING_03
Figure 7-103. OSPI0 Timing Requirements – Tap DDR, No Loopback
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Table 7-121. OSPI0 Switching Characteristics – Tap DDR Mode
see Figure 7-104
NO.
PARAMETER
MODE
MIN
40
MAX UNIT
O1
O2
O3
tc(CLK)
Cycle time, OSPI0_CLK
ns
ns
ns
tw(CLKL)
tw(CLKH)
Pulse duration, OSPI0_CLK low
Pulse duration, OSPI0_CLK high
((0.475P(1)) - 0.3)
((0.475P(1)) - 0.3)
((0.525P(1)) +
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
((0.475P(1)) +
O4
td(CSn-CLK)
( 1.025M(2)R(4)) +
1)
ns
((0.975M(2)R(4)) - 1)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
((0.475P(1)) +
((0.525P(1)) +
O5
O6
td(CLK-CSn)
td(CLK-D)
ns
ns
(0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
(- 17.94 +
(- 1.56 +
(0.975T(5)R(4)))
(1.025T(5)R(4)))
(1) P = CLK cycle time = SCLK period in ns
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) R = refclk cycle time in ns
(5) T = OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD]
OSPI_CSn
O4
O3
O5
OSPI_CLK
O2
O6
O6
O1
OSPI_D[i:0]
OSPI_TIMING_01
Figure 7-104. OSPI0 Switching Characteristics – Tap DDR, No Loopback
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7.9.5.18 Timers
For more details about features and additional description information on the device Timers, see the
corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 7-122. Timer Timing Conditions
PARAMETER
MIN
0.5
2
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
10
Table 7-123. Timer Input Timing Requirements
see Figure 7-105
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
T1
tw(TINPH)
Pulse duration, high
Pulse duration, low
CAPTURE
4P(1)
+
ns
2.5
T2
tw(TINPL)
CAPTURE
4P(1)
+
ns
2.5
(1) P = functional clock period in ns.
Table 7-124. Timer Output Switching Characteristics
see Figure 7-105
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
T3
tw(TOUTH)
Pulse duration, high
Pulse duration, low
PWM
4P(1)
-
ns
2.5
T4
tw(TOUTL)
PWM
4P(1)
-
ns
2.5
(1) P = functional clock period in ns.
T1
T2
TIMER_IOx (inputs)
T3
T4
TIMER_IOx (outputs)
TIMER_01
Figure 7-105. Timer Timing Requirements and Switching Characteristics
For more information, see Timers section in Peripherals chapter in the device TRM.
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7.9.5.19 UART
For more details about features and additional description information on the device Universal Asynchronous
Receiver Transmitter, see the corresponding subsections within Signal Descriptions and Detailed Description
sections.
Table 7-125. UART Timing Conditions
PARAMETER
MIN
0.5
1
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
30(1)
(1) This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the
load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall
times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore,
it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the
device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point
where the minimum data valid time of the attached device is violated.
Table 7-126. UART Timing Requirements
see Figure 7-106
NO.
PARAMETER
tw(RXD)
tw(RXDS)
DESCRIPTION
MIN
MAX
UNIT
0.95U(1)
1.05U(1)
1
Pulse width, receive data bit high or low
ns
(2)
(2)
0.95U(1)
2
Pulse width, receive start bit low
ns
(2)
(1) U = UART baud time in ns = 1/programmed baud rate.
(2) This value defines the data valid time, where the input voltage is required to be above VIH or below VIL.
Table 7-127. UART Switching Characteristics
see Figure 7-106
NO.
PARAMETER
DESCRIPTION
Programmable baud rate for Main Domain UARTs
Programmable baud rate for MCU and WKUP Domain UARTs
Pulse width, transmit data bit high or low
MIN
MAX
12
UNIT
Mbps
Mbps
ns
f(baud)
3.7
3
4
tw(TXD)
U(1) - 2
U(1) - 2
U(1) + 2
tw(TXDS)
Pulse width, transmit start bit low
ns
(1) U = UART baud time in ns = 1/actual baud rate, where the actual baud rate is defined in the UART Baud Rate Settings table of the
device TRM.
2
1
Start
VIH
Bit
UARTi_RXD
VIL
Data Bits
4
3
Start
Bit
UARTi_TXD
Data Bits
UART_TIMING_01_RCVRVIHVIL
Figure 7-106. UART Timing Requirements and Switching Characteristics
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For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter
in the device TRM.
7.9.5.20 USB
The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the
specification for timing details.
For more details about features and additional description information on the device Universal Serial Bus
Subsystem (USB), see the corresponding subsections within Signal Descriptions and Detailed Description
sections.
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8 Detailed Description
8.1 Overview
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9 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Device Connection and Layout Fundamentals
9.1.1 Power Supply
9.1.1.1 Power Distribution Network Implementation Guidance
The Sitara Processor Power Distribution Networks: Implementation and Analysis provides guidance for
successful implementation of the power distribution network. This includes PCB stackup guidance as well as
guidance for optimizing the selection and placement of the decoupling capacitors. TI only supports designs that
follow the board design guidelines contained in the application report.
9.1.2 External Oscillator
For more information about External Oscillators, see the Clock Specifications section.
9.1.3 JTAG, EMU, and TRACE
Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various
debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target
Connection Guide.
For recommendations on JTAG, EMU, and TRACE routing, see the Emulation and Trace Headers Technical
Reference Manual
9.1.4 Unused Pins
For more information about Unused Pins, see Section 6.4, Pin Connectivity Requirements
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9.2 Peripheral- and Interface-Specific Design Information
9.2.1 DDR Board Design and Layout Guidelines
The goal of the AM62Ax DDR Board Design and Layout Guidelines is to make the DDR system
implementation straightforward for all designers. Requirements have been distilled down to a set of layout and
routing rules that allow designers to successfully implement a robust design for the topologies that TI supports.
TI only supports board designs using LPDDR4 memories that follow the guidelines in this document.
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9.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
The following section details the PCB routing guidelines that must be observed when connecting OSPI, QSPI, or
SPI devices.
9.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
•
•
The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
The signal propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to
B) must be ≤ 450 ps (~7cm as stripline or ~8cm as microstrip)
•
The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-1
Propagation delays and matching:
•
•
– (A to B) ≤ 450 ps
– (E to F, or F to E) = ((A to B) ± 60 ps)
A
B
R1
0 Ω*
OSPI/QSPI/SPI
Device Clock Input
OSPI[x]_CLK
OSPI[x]_LBCLKO
OSPI Device DQS
OSPI[x]_DQS
E
F
OSPI[x]_D[y],
OSPI[x]_CSn[z]
OSPI/QSPI/SPI
Device IO[y], CS#
OSPI_Board_01
* 0 Ω resistor (R1), located as close as possible to the OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.
Figure 9-1. OSPI Connectivity Schematic for No Loopback, Internal PHY Loopback, and Internal Pad
Loopback
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9.2.2.2 External Board Loopback
•
•
•
The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
The OSPI[x]_LBCLKO output pin must be looped back to the OSPI[x]_DQS input pin
The signal propagation delay of the OSPI[x]_LBCLKO pin to the OSPI[x]_DQS pin (C to D) must be
approximately twice the propagation delay of the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device
CLK pin (A to B)
•
The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-2
Propagation delays and matching:
•
•
– (C to D) = 2 x ((A to B) ± 30 ps), see the exception note below.
– (E to F, or F to E) = ((A to B) ± 60 ps)
Note
The External Board Loopback hold time requirement (defined by parameter number O16 in Table
7-116, OSPI0 Timing Requirements - PHY DDR Mode) may be larger than the hold time provided by
a typical OSPI/QSPI/SPI device. In this case, the propagation delay of OPSI[x]_LBCLKO pin to the
OSPI[x]_DQS pin (C to D) can be reduced to provide additional hold time.
A
B
R1
0 Ω*
OSPI/QSPI/SPI
Device Clock Input
OSPI[x]_CLK
C
R1
0 Ω*
OSPI[x]_LBCLKO
D
OSPI Device DQS
OSPI[x]_DQS
E
F
OSPI[x]_D[y],
OSPI[x]_CSn[z]
OSPI/QSPI/SPI
Device IO[y], CS#
OSPI_Board_02
* 0 Ω resistor (R1), located as close as possible to the OSPI[x]_CLK and OSPI[x]_LBCLKO pins, is a placeholder for fine tuning, if
needed.
Figure 9-2. OSPI Connectivity Schematic for External Board Loopback
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9.2.2.3 DQS (only available in Octal SPI devices)
•
•
•
The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
The DQS pin of the attached OSPI/QSPI/SPI device must be connected to OSPI[x]_DQS pin
The signal propagation delay from the attached OSPI/QSPI/SPI device DQS pin to the OSPI[x]_DQS pin (D
to C) must be approximately equal to the signal propagation delay from the OSPI[x]_CLK pin to the attached
OSPI/QSPI/SPI device CLK pin (A to B)
•
The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-3
Propagation delays and matching:
•
•
– (D to C) = ((A to B) ± 30 ps)
– (E to F, or F to E) = ((A to B) ± 60 ps)
A
B
R1
0 Ω*
OSPI/QSPI/SPI
Device Clock Input
OSPI[x]_CLK
OSPI[x]_LBCLKO
C
D
OSPI Device DQS
OSPI[x]_DQS
E
F
OSPI[x]_D[y],
OSPI[x]_CSn[z]
OSPI/QSPI/SPI
Device IO[y], CS#
OSPI_Board_03
* 0 Ω resistor (R1), located as close as possible to the OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed.
Figure 9-3. OSPI Connectivity Schematic for DQS
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9.2.3 USB VBUS Design Guidelines
The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as
20 V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to
be 30 V.
The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in
the Figure 9-4), which limits the voltage applied to the actual device pin (USB0_VBUS). The tolerance of these
external resistors should be equal to or less than 1%, and the leakage current of Zener diode at 5 V should be
less than 100 nA.
Device
USBn_VBUS
16.5 kΩ
1%
3.5 kΩ
1%
VBUS signal
10 kΩ
1%
6.8V
(BZX84C6V8 or equivalent)
VSS
VSS
J7ES_USB_VBUS_01
Figure 9-4. USB VBUS Detect Voltage Divider / Clamp Circuit
The USB0_VBUS pin can be considered to be fail-safe because the external circuit in Figure 9-4 limits the input
current to the actual device pin in a case where VBUS is applied while the device is powered off.
9.2.4 System Power Supply Monitor Design Guidelines
The VMON_VSYS pin provides a way to monitor a system power supply. This system power supply is typically
a single pre-regulated power source for the entire system and can be connected to the VMON_VSYS pin via
and external resistor divider circuit. This system supply is monitored by comparing the external voltage divider
output voltage to an internal voltage reference, where a power fail event is triggered when the voltage applied
to VMON_VSYS drops below the internal reference voltage. The actual system power supply voltage trip point
is determined by the system designer when selecting component values used to implement the external resistor
voltage divider circuit.
When designing the resistor divider circuit the designer must understand various factors which contribute to
variability in the system power supply monitor trip point. The first thing to consider is the initial accuracy of
the VMON_VSYS input threshold which has a nominal value of 0.45 V, with a variation of ±3%. Precision
1% resistors with similar thermal coefficient are recommended for implementing the resistor voltage divider.
This minimizes variability contributed by resistor value tolerances. Input leakage current associated with
VMON_VSYS must also be considered since any current flowing into the pin creates a loading error on the
voltage divider output. The VMON_VSYS input leakage current can be in the range of 10 nA to 2.5 µA when
applying 0.45 V.
Note
The resistor voltage divider shall be designed such that the output voltage never exceeds the
maximum value defined in the Recommended Operating Conditions section, during normal operating
conditions.
Figure 9-5 presents an example, where the system power supply is nominally 5 V and the maximum trigger
threshold is 5 V - 10%, or 4.5 V.
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For this example, the designer must understand which variables effect the maximum trigger threshold when
selecting resistor values. A device which has a VMON_VSYS input threshold of 0.45 V + 3% needs to be
considered when trying to design a voltage divider that doesn’t trip until the system supply drops 10%. The effect
of resistor tolerance and input leakage also needs to be considered, but the contribution to the maximum trigger
point is not obvious. When selecting component values which produce a maximum trigger voltage, the system
designer must consider a condition where the value of R1 is 1% low and the value of R2 is 1% high combined
with a condition where input leakage current for the VMON_VSYS pin is 2.5 µA. When implementing a resistor
divider where R1 = 4.81 KΩ and R2 = 40.2 KΩ, the result is a maximum trigger threshold of 4.517 V.
Once component values have been selected to satisfy the maximum trigger voltage as described above, the
system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an
output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input
leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result
is a minimum trigger threshold of 4.013 V.
This example demonstrates a system power supply voltage trip point that ranges from 4.013 V to 4.517
V. Approximately 250 mV of this range is introduced by VMON_VSYS input threshold accuracy of ±3%,
approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV
of this range is introduced by loading error when VMON_VSYS input leakage current is 2.5 µA.
The resistor values selected in this example produces approximately 100 µA of bias current through the resistor
divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above can be reduced to about
10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor divider bias
current vs loading error is something the system designer needs to consider when selecting component values.
The system designer must also consider implementing a noise filter on the voltage divider output since
VMON_VSYS has minimum hysteresis and a high-bandwidth response to transients. This can be done by
installing a capacitor across R1 as shown in Figure 9-5. However, the system designer must determine the
response time of this filter based on system supply noise and expected response to transient events.
Device
VMON_VSYS
R2
VSYS
40.2 kΩ 1%
C1
Value = Determined by system designer
(System Power Supply)
4.81 kΩ
1%
R1
VSS
SPRSP56_VMON_ER_MON_01
Figure 9-5. System Supply Monitor Voltage Divider Circuit
VMON_1P8_SOC pin provides a way to monitor external 1.8 V power supplies. This pin must be connected
directly to their respective power source. An internal resistor divider with software control is implemented inside
the SoC for each of these pins. Software can program each internal resistor divider to create appropriate under
voltage and over voltage interrupts.
VMON_3P3_SOC pin provides a way to monitor external 3.3 V power supplies. This pin must be connected
directly to their respective power source. An internal resistor divider with software control is implemented inside
the SoC for each of these pins. Software can program each internal resistor divider to create appropriate under
voltage and over voltage interrupts.
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9.2.5 High Speed Differential Signal Routing Guidance
The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed
differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and
spacing limits. TI supports only designs that follow the board design guidelines contained in the application note.
9.2.6 Thermal Solution Guidance
The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful
implementation of a thermal solution for system designs containing this device. This document provides
background information on common terms and methods related to thermal solutions. TI only supports designs
that follow system design guidelines contained in the application note.
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10 Device and Documentation Support
10.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for
example, AM62AxAMB). Texas Instruments recommends two of three possible prefix designators for its support
tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
For orderable part numbers of AM62Ax devices in the AMB package type, see the Package Option Addendum of
this document, the TI website (ti.com), or contact your TI sales representative.
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10.1.1 Standard Package Symbolization
Note
Some devices may have a cosmetic circular marking visible on the top of the device package which
results from the production test process. In addition, some devices may also show a color variation in
the package substrate which results from the substrate manufacturer. These differences are cosmetic
only with no reliability impact.
SITARA
aBBBBBBr
ZfYytPPPQ1
XXXXXXX
A1 (PIN ONE INDICATOR)
G1
YYY
O
Figure 10-1. Printed Device Reference
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10.1.2 Device Naming Convention
FIELD PARAMETER FIELD DESCRIPTION
VALUE
DESCRIPTION
X(1)
Prototype
a
Device evolution stage
P
Preproduction (production test flow, no reliability data)
Production
BLANK(2)
AM62A74
AM62A72
Base production part
number
BBBBBBB
AM62A34
see Device Comparison
SR1.0
AM62A32
AM62A31
r
Device revision
A
M
N
O
P
Q
Z
Device Speed Grade
See Device Speed Grades
R
S
T
U
V
G
Base
Features
f
(see Device
Comparison)
L
Features supported by G, plus Multimedia JPEG Encoder
Features supported by L, plus Display Subsystem
Secure with Dummy Key / No Functional Safety
Secure with Production Key / No Functional Safety
Secure with Production Key / Functional Safety
M
1 to 9
H to R
S to Z
Security / Functional
Safety
Y
t
–40°C to 105°C - Extended Industrial (see Recommended Operation
Conditions)
A
Temperature(3)
I
–40°C to 125°C - Automotive (see Recommended Operation Conditions)
FC/CSP BGA (484)
ppp
Q
Package Designator
AMB
Q1
Auto Qualified (Q100)
Automotive Designator
BLANK
Standard
xxxxxxx
YYY
ZZZ
O
Lot Trace Code (LTC)
Production Code, For TI use only
Production Code, For TI use only
Pin one designator
G1
ECAT - Green package designator
(1) Device symbolization was changed after prototype devices began to ship. The prototype devices were symbolized
XAM62A74ATMGHIAMB, which does not match the naming convention defined by this table. The prototype device symbolization
corresponds to device XAM62A74AUMHIAMB.
(2) BLANK in the symbol or part number is collapsed so there are no gaps between characters.
(3) Applies to device max junction temperature.
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10.2 Tools and Software
The following Development Tools support development for TI's Embedded Processing platforms:
Development Tools
Code Composer Studio™ Integrated Development Environment Code Composer Studio (CCS) Integrated
Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded
Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded
applications. The tool includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through
each step of the application development flow. Familiar tools and interfaces allow users to get started faster
than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with
advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment
for embedded developers.
SysConfig-PinMux Tool The SysConfig-PinMux Tool is a software tool which provides a Graphical User
Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI
Embedded Processor devices. The tool can be used to automatically calculate the optimal pinmux configuration
to satisfy entered system requirements. The tool generates output C header/code files that can be imported
into software development kits (SDKs) and used to configure customer's software to meet custom hardware
requirements. The Cloud-based SysConfig-PinMux Tool is also available.
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized
distributor.
10.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
The following documents describe the AM62Ax devices.
Technical Reference Manual
AM62x Sitara Processors Technical Reference Manual: Details the integration, the environment, the
functional description, and the programming models for each peripheral and subsystem in the AM62Ax family of
devices.
Errata
AM62Ax Sitara Processors Silicon Errata: Describes the known exceptions to the functional specifications for
the device.
10.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.5 Trademarks
Sitara™, C7000™, Code Composer Studio™, and TI E2E™ are trademarks of Texas Instruments.
Arm®, Cortex®, and TrustZone® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or
elsewhere.
MIPI® is a registered trademark of MIPI Alliance.
Secure Digital® and SD® are registered trademarks of SD Card Association.
All trademarks are the property of their respective owners.
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10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AM62A31AMLHAAMB
AM62A32AMLHAAMB
AM62A32AMLSIAMBQ1
AM62A34ASMHAAMB
PREVIEW
PREVIEW
PREVIEW
PREVIEW
FCBGA
FCBGA
FCBGA
FCBGA
AMB
AMB
AMB
AMB
484
484
484
484
84
84
84
84
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 105
-40 to 105
-40 to 125
-40 to 105
TBD
Call TI
RoHS & Green
Level-3-250C-168 HR
AM62A34A
SMHAAMB
498
AM62A34ASMSIAMBQ1
AM62A74AUMHAAMB
AM62A74AUMHAAMBR
AM62A74AUMSIAMBQ1
AM62A74AUMSIAMBRQ1
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
AMB
AMB
AMB
AMB
AMB
484
484
484
484
484
84
84
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Call TI
Call TI
Call TI
Call TI
Level-3-250C-168 HR
Level-3-250C-168 HR
Level-3-250C-168 HR
Level-3-250C-168 HR
Level-3-250C-168 HR
-40 to 125
-40 to 105
-40 to 105
-40 to 125
-40 to 125
AM62A34A
SMSIAMBQ1
498
AM62A74A
UMHAAMB
498
500
84
AM62A74A
UMHAAMB
498
AM62A74A
UMSIAMBQ1
498
500
AM62A74A
UMSIAMBQ1
498
AM62A74AVMSIAMBQ1
XAM62A34ASMHAAMB
PREVIEW
ACTIVE
FCBGA
FCBGA
AMB
AMB
484
484
84
84
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 105
Samples
Samples
Samples
Samples
XAM62A34ASMHIAMB
XAM62A74AUMHAAMB
XAM62A74AUMHIAMB
ACTIVE
ACTIVE
ACTIVE
FCBGA
FCBGA
FCBGA
AMB
AMB
AMB
484
484
484
84
84
84
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 105
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2023
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF AM62A7, AM62A7-Q1 :
Catalog : AM62A7
•
Automotive : AM62A7-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE OUTLINE
AMB0484A
FCBGA - 2.556 mm max height
SCALE 0.900
BALL GRID ARRAY
18.1
17.9
A
B
BALL A1 CORNER
PIN 1 ID
(OPTIONAL)
18.1
17.9
(
13.6)
(
0.1 C
17.6)
(
11.6)
2.144
1.940
0.2 C
2.556
2.328
C
SEATING PLANE
0.2 C
0.5
0.3
TYP
16.8 TYP
SYMM
(0.6) TYP
(0.6) TYP
0.8 TYP
AB
AA
Y
W
V
U
T
R
P
N
M
L
SYMM
16.8
TYP
K
J
H
G
F
E
D
C
B
A
1
2 3
6 7
8
9 10 12 14 16 18 20 22
11 13 15 17 19 21
0.55
0.45
4
5
484X
NOTE 3
0.8 TYP
0.25
0.1
C A B
C
4228703/A 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Ball diameter after reflow. Dimension is measured at the maximum solder ball diameter parallel to primary datum C.
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EXAMPLE BOARD LAYOUT
AMB0484A
FCBGA - 2.556 mm max height
BALL GRID ARRAY
(0.8) TYP
484X ( 0.45)
1
2
3
5
8
9
10 11 12
15
4
6
7
13 14
16 17 18 19 20 21 22
A
(0.8) TYP
B
C
D
E
F
G
H
J
K
SYMM
L
M
N
P
R
T
U
V
W
Y
AA
AB
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SNOWN
SCALE:6X
0.07 MAX
0.07 MIN
METAL UNDER
SOLDER MASK
(
0.45)
METAL
EXPOSED METAL
(
0.45)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4228703/A 04/2022
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
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EXAMPLE STENCIL DESIGN
AMB0484A
FCBGA - 2.556 mm max height
BALL GRID ARRAY
(0.8) TYP
484X ( 0.45)
1
2
3
5
8
9
10 11 12
15
4
6
7
13 14
16 17 18 19 20 21 22
A
(0.8) TYP
B
C
D
E
F
G
H
J
K
SYMM
L
M
N
P
R
T
U
V
W
Y
AA
AB
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE: 6X
4228703/A 04/2022
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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