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AM3517AZERC [TI]

AM3517/05 Sitara™ ARM Microprocessors; AM3517 / 05 Sitaraa ？ ¢ ARM微处理器
AM3517AZERC
型号： AM3517AZERC
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

AM3517/05 Sitara™ ARM Microprocessors
AM3517 / 05 Sitaraa ？ ¢ ARM微处理器

微处理器
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AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
AM3517/05 Sitara™ ARM Microprocessors  
Check for Samples: AM3517, AM3505  
1 Device Summary  
1.1 Features  
123456  
–
SIDETONE Core Support (McBSP2 and  
3 Only) For Filter, Gain, and Mix  
Operations  
128-Channel Transmit/Receive Mode  
Direct Interface to I2S and PCM Device  
and TDM Buses  
• AM3517/05 Sitara™ ARM Microprocessor:  
– MPU Subsystem  
•
•
600-MHz Sitara™ ARM® Cortex™-A8 Core  
–
–
NEONTM SIMD Coprocessor and Vector  
floating point (FP) co-processor  
– Memory Interfaces:  
•
•
HDQ/1-Wire Interface  
•
166 MHz 16/32- bit mDDR/DDR2 Interface  
with 1 GByte total addressable space  
4 UARTs (One with Infrared Data  
Association [IrDA] and Consumer Infrared  
[CIR] Modes)  
3 Master/Slave High-Speed Inter-  
Integrated Circuit (I2C) Controllers  
12 32-bit General Purpose Timers  
1 32-bit Watchdog Timer  
1 32-bit 32-kHz Sync Timer  
•
Up to 83 MHz General Purpose Memory  
Interface supporting 16-bit Wide  
Multiplexed Address/Data bus  
•
•
•
64 K-Byte SRAM  
3 Removable Media Interfaces  
[MMC/SD/SDIO]  
•
•
•
•
– IO Voltage:  
Up to 186 General-Purpose I/O (GPIO)  
Pins  
•
•
mDDR/DDR2 IOs: 1.8V  
Other IOs: 1.8V and 3.3V  
• Display subsystem  
– Core Voltage: 1.2V  
– Commercial and Extended Temperature  
Grade  
– Parallel Digital Output  
– Up to 24-Bit RGB  
– Supports Up to 2 LCD Panels  
(operating restrictions apply)  
– Support for Remote Frame Buffer Interface  
(RFBI) LCD Panels  
– 16-bit Video Input Port capable of capturing  
HD video  
– Two 10-bit Digital-to-Analog Converters  
(DACs) Supporting  
– HD resolution Display Subsystem  
– Serial Communication  
•
•
Composite NTSC/PAL Video  
Luma/Chroma Separate Video (S-Video)  
•
•
•
High-End CAN Controller  
10/100 Mbit Ethernet MAC  
USB OTG subsystem with standard  
DP/DM interface [HS/FS/LS]  
– Rotation 90, 180, and 270 degrees  
– Resize Images From 1/4x to 8x  
– Color Space Converter  
•
Multiport USB Host Subsystem  
[HS/FS/LS]  
– 8-bit Alpha Blending  
–
12-pin ULPI or 6/4/3-pin Serial  
Interface  
• Video Processing Front End (VPFE) 16-bit  
Video Input Port  
•
•
Four Master/Slave Multichannel Serial  
Port Interface (McSPI) Ports  
Five Multichannel Buffered Serial Ports  
– RAW Data Interface  
– 75-MHz Maximum Pixel Clock  
– Supports REC656/CCIR656 Standard  
–
512-Byte Transmit/Receive Buffer  
(McBSP1/3/4/5)  
5K-Byte Transmit/Receive Buffer  
(McBSP2)  
– Supports YCbCr422 Format (8-bit or 16-bit  
With Discrete Horizontal and Vertical Sync  
Signals)  
–
– Generates Optical Black Clamping Signals  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
4
5
6
PowerVR SGX is a trademark of Imagination Technologies Ltd.  
Sitara is a trademark of Texas Instruments.  
Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.  
ARM, Jazelle are registered trademarks of ARM Ltd or its subsidiaries.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date. Products conform to  
specifications per the terms of the Texas Instruments standard warranty. Production  
processing does not necessarily include testing of all parameters.  
Copyright © 2009–2012, Texas Instruments Incorporated  
 
 
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
– Built-in Digital Clamping and Black Level  
Compensation  
– 10-bit to 8-bit A-law Compression Hardware  
1.1 and 2.0, OpenVG1.0  
– Fine Grained Task Switching, Load  
Balancing, and Power Management  
– Supports up to 16K Pixels (Image Size) in  
Horizontal and Vertical Directions  
– Programmable, High-Quality Image Anti-  
Aliasing  
• System Direct Memory Access (sDMA)  
Controller (32 Logical Channels With  
Configurable Priority)  
• Comprehensive Power, Reset and Clock  
Management  
• ARM Cortex™-A8 Memory Architecture  
– ARMv7 Architecture  
• Endianess  
– ARM Instructions - Little Endian  
– ARM Data – Configurable  
• SDRC Memory Controller  
– 16/32-bit Memory Controller With 1G-Byte  
Total Address Space  
– Double Data Rate (DDR2) SDRAM, mobile  
Double Data Rate (mDDR)SDRAM  
– SDRAM Memory Scheduler (SMS) and  
Rotation Engine  
– In-Order, Dual-Issue, Superscalar  
Microprocessor Core  
– ARM NEON™ Multimedia Architecture  
– Over 2x Performance of ARMv6 SIMD  
– Supports Both Integer and Floating Point  
SIMD  
– Jazelle® RCT Execution Environment  
Architecture  
– Dynamic Branch Prediction with Branch  
Target Address Cache, Global history buffer  
and 8 entry return stack  
– Embedded Trace Macrocell [ETM] support  
for Non_invasive Debug  
• General Purpose Memory Controller (GPMC)  
– 16-bit Wide Multiplexed Address/Data Bus  
– Up to 8 Chip Select Pins With 128M-Byte  
Address Space per Chip Select Pin  
– Glueless Interface to NOR Flash, NAND  
Flash (With ECC Hamming Code  
Calculation), SRAM and Pseudo-SRAM  
– Flexible Asynchronous Protocol Control for  
Interface to Custom Logic (FPGA, CPLD,  
ASICs, etc.)  
– 16K-Byte instruction Cache (4-Way set-  
associative)  
– Nonmultiplexed Address/Data Mode (Limited  
2K-Byte Address Space)  
– 16K-Byte Data Cache (4-Way Set-  
Associative)  
– 256K-Byte L2 Cache  
• Test Interfaces  
– IEEE-1149.1 (JTAG) Boundary-Scan  
Compatible  
• PowerVR SGX™ Graphics Accelerator (AM3517  
only)  
– Embedded Trace Macro Interface (ETM)  
• 65-nm CMOS technology  
• Packages:  
– Tile Based Architecture Delivering up to 10  
MPoly/sec  
– Universal Scalable Shader Engine: Multi-  
threaded Engine Incorporating Pixel and  
Vertex Shader Functionality  
– 491-pin BGA (17x17, 0.65mm pitch)  
[ZCN suffix]  
with via channel array technology  
– 484-pin PBGA (23x23, 1-mm pitch)  
[ZER suffix]  
– Industry Standard API Support: OpenGLES  
1.2 Applications  
•
•
•
•
•
•
Single Board Computers  
Industrial and Home Automation  
Digital Signage  
•
•
•
•
•
•
Transportation  
Navigation  
Smart White Goods  
Digital TV  
Point of Service  
Portable Media Player  
Portable Industrial  
Digital Video Camera  
Gaming  
2
Device Summary  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
 
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
1.3 Description  
AM3517/05 is a high-performance ARM Cortex-A8 microprocessor with speeds up to 600 MHz. The  
device offers 3D graphics acceleration while also supporting numerous peripherals, including DDR2, CAN,  
EMAC, and USB OTG PHY that are well suited for industrial apllications.  
The processor can support other applications, including:  
•
•
•
Single Board Computers  
Home and Industrial automation  
Human Machine Interface  
The device supports high-level operating systems (OSs), such as:  
•
•
•
Linux®  
Windows® CE  
Android™  
The following subsystems are part of the device:  
•
•
Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor.  
PowerVR SGX™ Graphics Accelerator (AM3517 device only) Subsystem for 3D graphics acceleration  
to support display and gaming effects.  
•
•
Display subsystem with several features for multiple concurrent image manipulation, and a  
programmable interface supporting a wide variety of displays. The display subsystem also supports  
NTSC/PAL video out.  
High performance interconnects provide high-bandwidth data transfers for multiple initiators to the  
internal and external memory controllers and to on-chip peripherals. The device also offers a  
comprehensive clock-management scheme.  
AM3517/05 devices are available in a 491-pin BGA package and a 484-pin PBGA package.  
This AM3517/05 data manual presents the electrical and mechanical specifications for the AM3517/05  
Sitara ARM Microprocessor.  
Copyright © 2009–2012, Texas Instruments Incorporated  
Device Summary  
3
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AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
1.4 Functional Block Diagram  
Figure 1-1 shows the functional block diagram of the AM3517/05 Sitara ARM Microprocessor.  
CVBS  
or  
S-Video  
LCD Panel  
Parallel  
USB transceivers /  
device ports [3]  
MPU  
Subsystem  
Analog  
DAC  
ARM Cortex-  
A8TM Core  
16K/16K L1$  
HS/FS/  
LS  
USB  
Host  
Dual Output 3-Layer  
Display Processor  
(1xGraphics, 2xVideo)  
Temporal Dithering  
SDTV → QCIF Support  
POWERVR  
SGXTM  
Graphics  
Accelerator  
(AM3517 only)  
32  
USB PHY  
USB OTG  
Controller  
Channel  
System  
DMA  
L2$  
256K  
64  
64  
64  
32  
32  
32 32  
32  
32  
Async  
VPFE  
HECC  
EMAC  
64  
L3 Interconnect Network-Hierarchial, Performance, and Power Driven  
64 32 32  
SMS:  
32  
32  
L4 Interconnect  
SDRAM  
Memory  
Scheduler/  
Rotation  
132K  
On-Chip  
BOOT  
ROM  
64K  
On-Chip  
RAM  
GPMC:  
Peripherals:  
4xUART, 3xHigh-Speed I2C,  
5xMcBSP  
(2x with Sidetone/Audio Buffer)  
4xMcSPI, 186xGPIO,  
3xHigh-Speed MMC/SDIO,  
HDQ/1 Wire,  
General  
Purpose  
Memory  
Controller  
System  
Controls  
PRCM  
EMIF  
Controller  
DDR PHY  
12xGPTimers, 1xWDT,  
32K Sync Timer  
External  
Peripherals  
Interfaces  
Emulation  
Debug: ETM, JTAG  
External  
DDR2/  
mDDR  
NAND/NOR/  
FLASH,  
SRAM  
SPRS550-006  
Figure 1-1. AM3517/05 Functional Block Diagram  
4
Device Summary  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
 
 
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
1.5 ZCN and ZER Package Differences  
Table 1-1 shows the ZER and ZCN package differences on the device.  
Table 1-1. ZCN and ZER Package Differences  
FEATURE  
ZCN PACKAGE  
ZER PACKAGE  
Pin Assignments  
For ZCN package pin assignments, see  
For ZER package pin assignments, see  
Section 2, Terminal Description  
Section 2, Terminal Description  
Video Interfaces  
TV Out available  
TV Out not available  
Copyright © 2009–2012, Texas Instruments Incorporated  
Device Summary  
5
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Product Folder Link(s): AM3517 AM3505  
 
 
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
1
Device Summary ........................................ 1  
1.1 Features ............................................. 1  
1.2 Applications .......................................... 2  
1.3 Description ........................................... 3  
1.4 Functional Block Diagram ........................... 4  
1.5 ZCN and ZER Package Differences ................. 5  
4.3 Output Clock Specifications ........................ 95  
4.4 DPLL Specifications ................................ 97  
Video DAC Specifications .......................... 100  
5.1 Interface Description .............................. 101  
5
6
5.2  
Electrical Specifications Over Recommended  
Operating Conditions .............................. 102  
5.3  
Analog Supply (vdda_dac) Noise Requirements . 104  
Revision History .............................................. 7  
2
5.4 External Component Value Choice ............... 105  
Timing Requirements and Switching  
Terminal Description ................................... 8  
2.1 Pin Assignments ..................................... 8  
2.2 Ball Characteristics ................................. 17  
2.3 Multiplexing Characteristics ........................ 51  
2.4 Signal Description .................................. 57  
Electrical Characteristics ............................ 80  
3.1 Absolute Maximum Ratings ........................ 80  
3.2 Recommended Operating Conditions .............. 82  
3.3 DC Electrical Characteristics ....................... 84  
3.4 Core Voltage Decoupling ........................... 86  
3.5 Power-up and Power-down ......................... 88  
Clock Specifications .................................. 91  
4.1 Oscillator ........................................... 92  
4.2 Input Clock Specifications .......................... 93  
Characteristics ....................................... 106  
6.1 Timing Test Conditions ........................... 106  
6.2 Interface Clock Specifications ..................... 106  
6.3 Timing Parameters ................................ 107  
6.4 External Memory Interfaces ....................... 108  
6.5 Video Interfaces ................................... 150  
6.6 Serial Communications Interfaces ................ 155  
6.7 Removable Media Interfaces ...................... 197  
6.8 Test Interfaces .................................... 211  
Package Characteristics ............................ 215  
7.1 Package Thermal Resistance ..................... 215  
7.2 Device Support .................................... 215  
7.3 Mechanical Data .................................. 217  
3
7
4
6
Contents  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
This data manual revision history table highlights the technical changes made from the previous to the  
current revision.  
SEE  
ADDITIONS/MODIFICATIONS/DELETIONS  
Section 2.2  
Ball Characteristics:  
Corrected USB0_VBUS signal voltage to 3.3V in Table 2-1, Ball Characteristics (ZCN Pkg.)  
General-Purpose IOs:  
Section 2.4.7  
Corrected ZCN/ZER ball numbers for GPIO_125, GPIO_126, GPIO_130, GPIO_131 signals in Table 2-25,  
General-Purpose IOs Signals Description  
Section 4.1  
Oscillator:  
Deleted paragraph and added notes to Figure 4-3, AM3517/05 Oscillator Connections  
Management Data Input/Output (MDIO) Electrical Data/Timing:  
Modified Parameter 5 MIN value in Table 6-115, Timing Requirements for MDIO Input  
Section 6.6.8.1  
Copyright © 2009–2012, Texas Instruments Incorporated  
Contents  
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AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
2 Terminal Description  
2.1 Pin Assignments  
2.1.1 Pin Map (Top View)  
The following illustrations show the top views of the 484-pin [ZER] and 491-pin [ZCN] package pin  
assignments in four quadrants (A, B, C, and D).  
Note: A pin with an "NC" designator indicates No Connection. For proper device operation, these pins  
must be left unconnected.  
8
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
DSS_ACBIAS DSS_PCLK  
ETK_D15  
ETK_D12  
ETK_D8  
ETK_D5  
ETK_CTL  
MCSPI2_  
CS1  
MCSPI1_  
CS3  
MCSPI1_  
CS2  
MCSPI1_  
CLK  
AE  
AD  
VSS  
AE  
AD  
DSS_DATA1  
DSS_DATA0 DSS_VSYNC DSS_HSYNC  
ETK_D13  
ETK_D14  
ETK_D9  
ETK_D10  
ETK_D11  
ETK_D6  
ETK_D0  
ETK_D1  
ETK_CLK  
MCSPI2_  
CLK  
MCSPI1_  
SIMO  
MCSPI1_  
CS1  
AC  
DSS_DATA4  
DSS_DATA3 DSS_DATA2  
MCSPI2_  
SIMO  
MCSPI1_  
SOMI  
AC  
DSS_DATA6 DSS_DATA5  
DSS_DATA9 DSS_DATA8  
ETK_D7  
ETK_D2  
ETK_D3  
MCSPI2_  
SOMI  
MCSPI1_CS0  
AB  
AA  
AB  
AA  
VDDS_  
DPLL_MPU  
_USBHOST  
DSS_DATA7  
DSS_DATA11  
UART1_TX  
MCSPI2_  
CS0  
DSS_DATA13 DSS_DATA12  
DSS_DATA10  
UART1_CTS UART1_RTS  
ETK_D4  
VDDS  
Y
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
Y
DSS_DATA18 DSS_DATA17 DSS_DATA16  
UART1_RX  
W
DSS_DATA15 DSS_DATA14  
W
DSS_DATA20 DSS_DATA19  
VDD_CORE VDD_CORE  
V
U
T
VSS  
VSS  
VSS  
VSS  
VSS  
V
U
T
DSS_  
DATA21  
JTAG_TCK JTAG_NTRST  
JTAG_EMU0 JTAG_TDO  
DSS_  
DATA23  
DSS_  
DATA22  
VDD_CORE  
VDD_CORE  
VDDS  
VDDSHV  
VDDSHV  
VSS  
VSS  
JTAG_TDI  
JTAG_RTCK  
VDD_CORE  
VDD_CORE  
VDDSHV  
JTAG_TMS  
_TMSC  
JTAG_  
EMU1  
MCBSP1_  
CLKR  
VDD_CORE VDD_CORE  
R
P
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
R
P
MCBSP_  
CLKS  
MCBSP1_  
FSX  
MCBSP1_  
DR  
MCBSP1_  
DX  
MCBSP1_  
FSR  
VDDSHV  
VDDSHV  
VDDSHV  
VSS  
VSS  
VSS  
VDDS_DPLL_  
PER_CORE  
SYS_  
CLKOUT1  
MCBSP1_  
CLKX  
N
VSS  
VSS  
VSS  
N
NC  
NC  
SYS_  
CLKOUT2  
SYS_  
CLKREQ  
M
VDD_CORE  
VSS  
17  
VSS  
14  
M
VSS  
16  
VSS  
15  
25  
24  
23  
22  
21  
20  
19  
18  
Figure 2-1. ZCN Pin Map [Quadrant A]  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
9
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
MMC1_  
DAT7  
MMC1_  
DAT2  
MMC2_  
CMD  
RMII_50MHZ  
_CLK  
RMII_MDIO  
_DATA  
CCDC_  
DATA4  
MMC2_  
DAT3  
CCDC_  
WEN  
MMC2_  
DAT7  
CCDC_  
DATA1  
CCDC_  
HD  
RMII_TXD1  
AE  
VSS  
AE  
MMC2_  
DAT6  
MMC2_  
DAT2  
RMII_MDIO  
_CLK  
MMC1_  
DAT6  
MMC1_  
DAT1  
CCDC_  
DATA3  
CCDC_  
DATA0  
CCDC_  
PCLK  
CCDC_  
VD  
CCDC_  
FIELD  
MMC2_CLK  
RMII_TXEN RMII_TXD0  
AD  
AC  
AD  
AC  
MMC1_  
DAT0  
SYS_  
BOOT6  
CCDC_  
DATA2  
SYS_  
BOOT7  
MMC1_  
DAT5  
CCDC_  
DATA7  
SYS_  
BOOT8  
MMC2_  
DAT1  
RMII_RXER  
MMC2_  
DAT5  
MMC2_  
DAT0  
MMC1_  
DAT4  
MMC1_  
CMD  
SYS_  
BOOT4  
SYS_  
BOOT5  
MMC2_  
DAT4  
RMII_CRS_  
DV  
CCDC_  
DATA6  
AB  
AB  
AA  
Y
VDDS_SRAM CAP_VDD_  
SRAM_MPU  
MMC1_  
DAT3  
SYS_  
BOOT1  
SYS_  
BOOT2  
MMC1_CLK  
RMII_RXD1  
RMII_RXD0  
SYS_  
BOOT3  
AA  
_MPU  
SYS  
_NRES  
WARM  
SYS  
_NRES  
PWRON  
CCDC_  
DATA5  
SYS_  
BOOT0  
Y
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDS  
SYS_NIRQ  
I2C2_SCL  
VDDSHV  
I2C2_SDA  
VDDSHV  
VDDSHV  
I2C3_SDA  
I2C1_SDA  
I2C3_SCL  
I2C1_SCL  
W
V
VDDSHV  
W
V
VDDSHV  
HECC1_  
RXD  
VDD_CORE VDD_CORE  
HECC1_  
TXD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDDSHV  
RESERVED  
VDD_CORE  
VDD_CORE  
GPMC_  
WAIT3  
RESERVED  
U
T
VSS  
VSS  
U
GPMC_  
NWP  
VDD_CORE  
GPMC_  
WAIT2  
GPMC_  
WAIT1  
GPMC_  
WAIT0  
GPMC_  
NBE1  
VSS  
VSS  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
T
VDD_CORE  
VDD_CORE  
VSS  
GPMC_NBE0  
_CLE  
GPMC_NADV  
_ALE  
GPMC_  
NWE  
GPMC_  
NOE  
R
P
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD_CORE  
VDDS  
R
UART3_RX  
_IRRX  
UART3_TX  
_IRTX  
VSS  
VSS  
VSS  
P
GPMC_  
NCS6  
GPMC_  
NCS7  
UART3_RTS  
_SD  
UART3_CTS  
_RCTX  
N
M
VSS  
VSS  
VSS  
VSS  
VDDSHV  
VDDSHV  
N
GPMC_CLK  
GPMC_  
NCS3  
GPMC_  
NCS2  
GPMC_  
NCS4  
GPMC_  
NCS5  
VSS  
VSS  
VSS  
VSS  
10  
VSS  
9
VSS  
8
VDDSHV  
VDDSHV  
VDDSHV  
M
13  
12  
11  
7
6
5
4
3
2
1
Figure 2-2. ZCN Pin Map [Quadrant B]  
10  
Terminal Description  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
25  
24  
23  
22  
21  
20  
19  
18  
17  
15  
14  
16  
HDQ_  
SIO  
VDD_CORE  
L
K
J
NC  
NC  
VDDSHV  
VSS  
VSS  
VSS  
L
NC  
NC  
VDDSOSC  
VSS  
SYS_  
XTALIN  
SYS_32K  
VDD_CORE VDD_CORE  
TV_  
OUT1  
VDDSHV  
VSS  
VSS  
K
J
TV_VFB1  
NC  
NC  
VSSOSC  
VSS  
VSS  
VDDSHV  
VDDS  
VDD_CORE  
VDD_CORE  
VDD_CORE  
SYS_  
XTALOUT  
VDDSHV  
H
G
F
TV_  
OUT2  
VSS  
H
G
F
E
D
C
B
A
NC  
TV_VREF  
VSSA_DAC  
VDDA_DAC  
VDDS  
TV_VFB2  
VDDA1P8V  
_USBPHY  
USB0_  
VBUS  
USB0_ID  
USB0_DP  
VDDS  
VDDS  
VSS  
VSS  
CAP_  
VDDA1P2LDO  
_USBPHY  
VDDA3P3V  
_USBPHY  
USB0_DM  
VREFSSTL  
UART2_CTS UART2_RTS  
VDDS  
NC  
VDDS_SRAM CAP_VDD_  
_CORE_BG SRAM_CORE  
USB0_  
DRVVBUS  
UART2  
_TX  
E
D
C
B
A
UART2_RX  
SDRC_D4  
SDRC_NCAS  
MCBSP2_  
FSX  
MCBSP2_  
DX  
SDRC_D2  
SDRC_D3  
SDRC_D5  
SDRC_D6  
SDRC_D9  
SDRC_D11  
SDRC_D12  
SDRC_CKE0  
SDRC_NRAS  
MCBSP2_  
CLKX  
MCBSP3_  
DR  
MCBSP3_  
FSX  
SDRC_D10  
SDRC_DM0  
SDRC_  
D0  
MCBSP4_  
CLKX  
MCBSP4_  
DX  
SDRC_  
DQS0P  
SDRC_  
D7  
SDRC_  
D8  
SDRC_  
DQS1P  
SDRC_  
D13  
SDRC_  
DM1  
MCBSP3_DX  
SDRC_  
NWE  
MCBSP2_DR  
SDRC_  
STRBEN  
_DLY0  
SDRC_  
DQS1N  
SDRC_  
D14  
SDRC_  
D15  
MCBSP3_  
CLKX  
MCBSP4_  
DR  
MCBSP4_  
FSX  
SDRC_  
DQS0N  
SDRC_  
STRBEN0  
SDRC_  
D1  
SDRC_  
NCS1  
VSS  
25  
24  
23  
22  
21  
20  
19  
18  
17  
15  
14  
16  
Figure 2-3. ZCN Pin Map [Quadrant C]  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
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13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
GPMC_  
NCS0  
GPMC_  
NCS1  
VDD_CORE VDD_CORE  
VDD_CORE VDD_CORE  
L
VSS  
VSS  
VSS  
VSS  
L
VSS  
VSS  
VSS  
GPMC_D15  
K
VSS  
VSS  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
GPMC_D13 GPMC_D14  
K
J
GPMC_D12  
VDD_CORE VDD_CORE  
VDD_CORE VDD_CORE  
GPMC_D7 GPMC_D8  
GPMC_D9  
J
H
G
F
VSS  
VSS  
VSS  
VDDS  
GPMC_D10 GPMC_D11  
GPMC_D5 GPMC_D6  
VSS  
H
G
F
E
D
C
B
A
GPMC_D0 GPMC_D1  
GPMC_D2  
GPMC_A7  
GPMC_A1  
GPMC_D3  
GPMC_A8  
GPMC_A2  
GPMC_D4  
GPMC_A9  
GPMC_A3  
SDRC_DM3  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
GPMC_A10  
GPMC_A5  
VDDS  
GPMC_A4  
SDRC_D19  
GPMC_A6  
SDRC_  
NCS0  
SDRC_  
A4  
SDRC_  
A9  
E
D
C
B
A
SDRC_DM2  
SDRC_A14  
SDRC_BA2  
SDRC_BA1  
SDRC_D18 SDRC_D21  
SCRC_D29  
SDRC_A3  
SDRC_A2  
SDRC_A1  
SDRC_A8  
SDRC_A7  
SDRC_A6  
SDRC_  
ODT  
SDRC_D20 SDRC_D23  
SDRC_D27 SDRC_D28 SDRC_D31  
SDRC_  
NCLK  
DDR_  
PADREF  
SDRC_  
A13  
SDRC_  
D17  
SDRC_  
DQS2N  
SDRC_  
DQS3N  
SDRC_D30  
SDRC_D26  
SDRC_A11  
SDRC_D22  
SDRC_24  
SDRC_  
STRBEN  
_DLY1  
SDRC_  
DQS3P  
SDRC_  
DQS2P  
SDRC_  
STRBEN1  
SDRC_  
A12  
SDRC_  
A10  
SDRC_  
D16  
SDRC_D25  
VSS  
SDRC_CLK  
SDRC_A0  
SDRC_A5  
SDRC_BA0  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
Figure 2-4. ZCN Pin Map [Quadrant D]  
12  
Terminal Description  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
A
B
C
D
E
F
G
H
K
L
J
MCSPI2_  
SOMI  
DSS_PCLK  
UART1_TX  
ETK_D8  
ETK_D10  
ETK_D1  
ETK_CLK  
MCSPI2_CLK MCSPI1_CLK  
22  
21  
VSS  
VDDSHV  
22  
21  
DSS_HSYNC UART1_RTS  
ETK_D9  
ETK_D7  
ETK_D5  
ETK_D2  
ETK_CTL  
ETK_D0  
MCSPI2_CS0 MCSPI1_CS3 MMC2_DAT3 MMC2_DAT6  
VDDSHV  
MCSPI2_  
SIMO  
DSS_DATA0 DSS_VSYNC UART1_RX  
ETK_D13  
ETK_D11  
MCSPI1_CS1 MMC2_DAT0 MMC2_DAT5  
20  
20  
DSS_DATA1 DSS_ACBIAS UART1_CTS ETK_D14  
ETK_D4  
ETK_D6  
ETK_D3  
MCSPI2_CS1 MCSPI1_CS2 MCSPI1_SIMO MMC2_DAT1  
19  
18  
19  
18  
MCSPI1_  
SOMI  
DSS_DATA2 DSS_DATA3  
DSS_DATA5  
ETK_D15  
ETK_D12  
MCSPI1_CS0 MMC2_DAT4  
VDDSHV  
VSS  
VDDSHV  
VDDS_DPLL_  
VDDS_  
DSS_DATA4 DSS_DATA8 DSS_DATA9 DSS_DATA6  
DSS_DATA13 DSS_DATA7 DSS_DATA10 DSS_DATA11  
17  
VDDSHV  
VSS  
VDDSHV  
VSS  
VSS  
VDDSHV  
MPU_  
USBHOST  
17  
SRAM_MPU  
VDD_CORE  
16  
VSS  
VDDS  
VSS  
VSS  
VDDS  
16  
DSS_DATA16 DSS_DATA15 DSS_DATA19 DSS_DATA14  
VDD_CORE  
15  
14  
13  
VDDSHV  
VSS  
VDDS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD_CORE  
VSS  
VSS  
VDD_CORE  
VSS  
15  
14  
13  
DSS_DATA17 DSS_DATA23 DSS_DATA22 DSS_DATA12 JTAG_TCK  
DSS_DATA20 DSS_DATA21 DSS_DATA18 JTAG_NTRST JTAG_EMU0  
JTAG_TMS_  
VDDSHV  
VSS  
VDD_CORE  
VSS  
VDDSHV  
JTAG_TDI  
JTAG_RTCK JTAG_TDO  
JTAG_EMU1  
VDD_CORE  
VDD_CORE  
12  
VDDSHV  
VDDSHV  
VSS  
H
VSS  
K
12  
TMSC  
A
B
C
D
E
F
G
L
J
Figure 2-5. ZER Pin Map [Quadrant A]  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
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M
N
P
R
T
U
V
W
Y
AA  
AB  
RMII_  
MDIO_CLK  
CCDC_  
DATA4  
CCDC_  
DATA0  
MMC1_DAT4 MMC1_CLK RMII_RXER RMII_TXD0  
CCDC_VD  
22  
VSS  
VDDSHV  
VSS  
22  
RMII_  
50MHZ_CLK  
RMII_  
CRS_DV  
RMII_  
MDIO_DATA  
CCDC_  
DATA2  
CCDC_  
PCLK  
MMC2_CLK MMC1_CMD MMC1_DAT0  
CCDC_WEN CCDC_HD CCDC_FIELD  
21  
20  
21  
20  
CCDC_  
DATA5  
CCDC_  
DATA6  
CCDC_  
DATA1  
MMC2_CMD MMC1_DAT1 MMC1_DAT3 RMII_TXD1 RMII_RXD1  
MMC2_DAT7 MMC1_DAT5 MMC1_DAT2 RMII_TXEN RMII_RXD0  
SYS_BOOT8 SYS_BOOT7 SYS_BOOT1  
CCDC_  
DATA7  
CCDC_  
DATA3  
SYS_BOOT6 SYS_BOOT5 SYS_BOOT3 SYS_BOOT0  
19  
18  
17  
16  
15  
14  
19  
SYS_NRE  
SWARM  
SYS_NRES  
PWRON  
MMC2_DAT2 MMC1_DAT6  
SYS_BOOT4 SYS_BOOT2  
SYS_NIRQ  
I2C1_SDA  
MMC1_DAT7  
VDDSHV  
VSS  
VDDSHV  
VSS  
VDDSHV  
VSS  
VDDSHV  
18  
CAP_VDD  
_SRAM_MPU  
I2C3_SDA  
I2C3_SCL  
I2C2_SCL  
I2C2_SDA  
I2C1_SCL  
VSS  
VSS  
VSS  
VDDSHV  
17  
16  
15  
14  
13  
12  
GPMC_  
WAIT1  
HECC1_RXD  
VSS  
VDDSHV  
VDDSHV  
VDDSHV  
RESERVED  
RESERVED  
VDD_CORE  
VDD_CORE  
GPMC_NBE1 GPMC_NWE HECC1_TXD  
UART3_CTS  
_RCTX  
VSS  
VSS  
VDDS  
VSS  
GPMC_  
GPMC_  
WAIT3  
GPMC_  
WAIT2  
VDD_CORE  
VDD_CORE  
GPMC_NWP  
GPMC_NOE  
NADV_ALE  
VSS  
VSS  
VSS  
VDDSHV  
GPMC_  
WAIT0  
VDD_CORE  
UART3_RTS UART3_TX UART3_RX GPMC_CLK  
_SD _IRTX _IRRX  
13 VDD_CORE  
VSS  
VSS  
VDDSHV  
VSS  
VDD_CORE  
VDD_CORE  
GPMC_NCS3 GPMC_NCS5 GPMC_NCS2 GPMC_NCS6  
12  
VSS  
M
VSS  
P
VSS  
T
VDDSHV  
VSS  
AB  
N
R
U
V
W
Y
AA  
Figure 2-6. ZER Pin Map [Quadrant B]  
14  
Terminal Description  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
A
C
F
G
H
L
B
D
E
J
K
VDDS_  
DPLL_PER  
_CORE  
MCBSP1  
_CLKR  
MCBSP1_FSX MCBSP1_FSR MCBSP_CLKS  
VDD_CORE  
11  
10  
9
VSS  
VSS  
VSS  
VSS  
VSS  
11  
10  
9
SYS_  
CLKOUT2  
SYS_XTALIN  
MCBSP1_DX  
MCBSP1_DR  
VDD_CORE  
VDD_CORE  
VSSOSC  
NC  
NC  
VDDSHV  
VSS  
VSS  
VSS  
SYS_  
XTALOUT  
SYS_  
CLKOUT1  
VDD_CORE  
VSS  
VSS  
HDQ_SIO  
NC  
VDDSOSC  
VDDSHV  
NC  
NC  
MCBSP1  
_CLKX  
SYS_32K  
SYS_CLKREQ  
VDD_CORE  
VDD_CORE  
8
NC  
NC  
VSS  
VSS  
8
CAP_VDDA1  
P2LDO_  
USBPHY  
VDDA1P8V  
_USBPHY  
VDDA3P3V  
_USBPHY  
USB0_  
DRVVBUS  
USB0_ID  
USB0_VBUS  
UART2_RX  
7
VSS  
NC  
VDDS  
VSS  
7
VSS  
VDDS_SRAM CAP_VDD_  
_CORE_BG SRAM_CORE  
USB0_DP  
USB0_DM  
UART2_TX  
VSS  
6
VSS  
VSS  
VDDS  
6
NC  
VSS  
MCBSP2  
_CLKX  
SDRC_BA1  
SDRC_BA2  
VREFSSTL  
UART2_RTS MCBSP2_DR  
VDDS  
UART2_CTS  
MCBSP2_FSX  
5
5
VDDS  
MCBSP3  
_CLKX  
MCBSP3_FSX MCBSP3_DR MCBSP3_DX  
MCBSP2_DX SDRC_DM0  
SDRC_D11  
SDRC_D12 SDRC_NCS0 SDRC_NCS1  
SDRC_BA0  
4
4
MCBSP4  
_CLKX  
MCBSP4_DR  
SDRC_D2  
SDRC_D1  
SDRC_D0  
SDRC_D4  
SDRC_D9  
SDRC_D10  
SDRC_D14  
SDRC_CKE0 SDRC_NCAS  
SDRC_NWE SDRC_NCLK  
SDRC_NRAS SDRC_CLK  
3
3
SDRC_  
STRBEN0  
MCBSP4_DX MCBSP4_FSX SDRC_D3  
SDRC_D5 SDRC_DQS0P  
SDRC_D7 SDRC_DQS0N  
SDRC_D8 SDRC_DQS1P SDRC_DM1  
SDRC_D13 SDRC_DQS1N SDRC_D15  
2
2
SDRC_  
STRBEN  
_DLY0  
SDRC_D6  
1
VSS  
A
VDDSHV  
1
B
C
D
E
F
G
H
J
L
K
Figure 2-7. ZER Pin Map [Quadrant C]  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
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M
N
P
R
T
U
V
W
Y
AA  
AB  
GPMC_  
NBE0_CLE  
VDD_CORE  
VDDSHV  
11  
10  
9
VSS  
VDD_CORE  
VSS  
VSS  
GPMC_NCS7  
11  
10  
9
GPMC_NCS1 GPMC_NCS4  
VDDSHV  
VDD_CORE  
GPMC_D12  
GPMC_D14 GPMC_D8 GPMC_NCS0  
VDD_CORE  
VSS  
VDDSHV  
VSS  
VDDSHV  
GPMC_D10  
GPMC_D9  
GPMC_D6  
GPMC_A9  
GPMC_A6  
GPMC_A5  
VSS  
VSS  
VDD_CORE  
VSS  
GPMC_D13 GPMC_D3  
VDD_CORE  
VSS  
VDD_CORE  
VSS  
VSS  
GPMC_D15 GPMC_D11  
GPMC_D4 GPMC_D5  
VSS  
VDD_CORE  
8
VSS  
VDDSHV  
VDDSHV  
VDDSHV  
VSS  
GPMC_D7  
8
VDD_CORE  
VDD_CORE  
GPMC_D2 GPMC_D1 GPMC_D0  
7
VSS  
VDDS  
VSS  
VSS  
7
GPMC_A8  
GPMC_A10  
GPMC_A7  
GPMC_A4  
6
VSS  
VDDS  
VSS  
VDDS  
VDDS  
VSS  
6
SDRC_A2  
SDRC_A1  
SDRC_A0  
SDRC_D22  
GPMC_A1 GPMC_A2  
5
VDDS  
VDDS  
VSS  
VDDS  
5
SDRC_A5  
SDRC_A3  
SDRC_A4  
SDRC_A9  
SDRC_A6  
SDRC_A7  
SDRC_A13 SDRC_DM2 SDRC_D18 SDRC_D19 SDRC_D25 SDRC_D27 SDRC_D30 GPMC_A3  
4
4
SDRC_A12  
SDRC_A11  
SDRC_D24 SDRC_D26  
SDRC_D29 SDRC_DM3  
SDRC_D28 SDRC_D31  
SDRC_D16  
SDRC_A14  
SDRC_D17  
SDRC_D23  
SDRC_D21  
3
3
SDRC_  
STRBEN  
_DLY1  
DDR_  
PADREF  
SDRC_  
DQS2N  
SDRC_  
DQS3N  
2
2
SDRC_  
STRBEN1  
SDRC_A8  
SDRC_A10  
SDRC_  
ODT  
SDRC_  
DQS2P  
SDRC_  
D20  
SDRC_  
DQS3P  
1
VSS  
M
VDDS  
VDDS  
AA  
VSS  
1
N
P
R
T
U
V
W
Y
AB  
Figure 2-8. ZER Pin Map [Quadrant D]  
16  
Terminal Description  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
2.2 Ball Characteristics  
Table 2-1 and Table 2-2 describe the terminal characteristics and the signals multiplexed on each pin for  
the ZCN/ZER packages. The following list describes the table column headers.  
1. BALL LOCATION: Ball number(s) on the bottom side associated with each signal(s) on the bottom.  
2. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the  
signal name in mode 0).  
Note: The Ball Characteristics table does not take into account subsystem pin multiplexing options.  
Subsystem pin multiplexing options are described in Section 2.4, Signal Description.  
3. MODE: Multiplexing mode number.  
(a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin  
corresponds to the name of the pin. There is always a function mapped on the primary mode.  
Notice that primary mode is not necessarily the default mode.  
Note: The default mode is the mode which is automatically configured on release of the internal  
GLOBAL_PWRON reset; also see the RESET REL. MODE column.  
(b) Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectively  
used for alternate functions, while some modes are not used and do not correspond to a functional  
configuration.  
4. TYPE: Signal direction  
–
–
–
–
–
–
I = Input  
O = Output  
I/O = Input/Output  
D = Open drain  
DS = Differential  
A = Analog  
Note: In the safe_mode, the buffer is configured in high-impedance.  
5. BALL RESET STATE: The state of the terminal at reset (power up).  
–
0: The buffer drives VOL (pulldown/pullup resistor not activated)  
0(PD): The buffer drives VOL with an active pulldown resistor.  
1: The buffer drives VOH (pulldown/pullup resistor not activated)  
1(PU): The buffer drives VOH with an active pullup resistor.  
Z: High-impedance  
–
–
–
–
L: High-impedance with an active pulldown resistor  
H: High-impedance with an active pullup resistor  
6. BALL RESET REL. STATE: The state of the terminal at reset release.  
–
0: The buffer drives VOL (pulldown/pullup resistor not activated)  
0(PD): The buffer drives VOL with an active pulldown resistor.  
1: The buffer drives VOH (pulldown/pullup resistor not activated)  
1(PU): The buffer drives VOH with an active pullup resistor.  
Z: High-impedance  
–
–
–
–
L: High-impedance with an active pulldown resistor  
H : High-impedance with an active pullup resistor  
7. RESET REL. MODE: This mode is automatically configured on release of the internal  
GLOBAL_PWRON reset.  
8. POWER: The voltage supply that powers the terminal’s I/O buffers.  
9. VOLTAGE: Supply voltage for associated pin.  
10. HYS: Indicates if the input buffer is with hysteresis.  
11. LOAD: Load capacitance of the associated output buffer.  
12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and  
pulldown resistors can be enabled or disabled via software.  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
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13. IO CELL: IO cell information.  
Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results.  
This can be easily prevented with the proper software configuration.  
Table 2-1. Ball Characteristics (ZCN Pkg.)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
IO CELL [13]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
B21  
A21  
D20  
C20  
E19  
D19  
C19  
B19  
B18  
D17  
C17  
D16  
C16  
B16  
A16  
A15  
A7  
sdrc_d0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
sdrc_d1  
sdrc_d2  
sdrc_d3  
sdrc_d4  
sdrc_d5  
sdrc_d6  
sdrc_d7  
sdrc_d8  
sdrc_d9  
sdrc_d10  
sdrc_d11  
sdrc_d12  
sdrc_d13  
sdrc_d14  
sdrc_d15  
sdrc_d16  
sdrc_d17  
sdrc_d18  
sdrc_d19  
sdrc_d20  
sdrc_d21  
sdrc_d22  
sdrc_d23  
sdrc_d24  
sdrc_d25  
sdrc_d26  
sdrc_d27  
sdrc_d28  
sdrc_d29  
sdrc_d30  
sdrc_d31  
sdrc_ba0  
sdrc_ba1  
sdrc_ba2  
sdrc_a0  
sdrc_a1  
sdrc_a2  
sdrc_a3  
sdrc_a4  
sdrc_a5  
sdrc_a6  
sdrc_a7  
sdrc_a8  
sdrc_a9  
sdrc_a10  
sdrc_a11  
sdrc_a12  
sdrc_a13  
B7  
D7  
E7  
C6  
D6  
B5  
C5  
B4  
A3  
B3  
C3  
C2  
D2  
B1  
C1  
A12  
C13  
D13  
A11  
B11  
C11  
D11  
E11  
A10  
B10  
C10  
D10  
E10  
A9  
O
No  
O
No  
O
No  
O
No  
O
No  
O
No  
O
No  
O
No  
O
No  
O
No  
O
No  
O
No  
O
No  
B9  
O
No  
A8  
O
No  
B8  
O
No  
18  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
 
 
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
IO CELL [13]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
D8  
sdrc_a14  
0
0
0
0
0
0
7
O
O
O
O
O
O
L
L
L
L
L
L
L
Z
0
0
0
0
0
7
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
No  
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
E13  
A14  
A13  
B13  
D14  
sdrc_ncs0  
sdrc_ncs1  
sdrc_clk  
Z
No  
Z
No  
Z
Yes  
No  
sdrc_nclk  
sdrc_cke0  
Z
PD  
Yes  
sdrc_cke0_s  
afe  
C14  
E14  
B14  
C21  
B15  
E8  
sdrc_nras  
sdrc_ncas  
sdrc_nwe  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
No  
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
O
No  
O
No  
sdrc_dm0  
sdrc_dm1  
sdrc_dm2  
sdrc_dm3  
sdrc_dqs0p  
sdrc_dqs1p  
sdrc_dqs2p  
sdrc_dqs3p  
sdrc_dqs0n  
sdrc_dqs1n  
sdrc_dqs2n  
sdrc_dqs3n  
sdrc_odt  
O
No  
O
No  
O
No  
D1  
O
No  
B20  
B17  
A6  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
Yes  
Yes  
Yes  
Yes  
A2  
A20  
A17  
B6  
B2  
C8  
A19  
A18  
sdrc_strben0  
sdrc_strben_  
dly0  
A5  
A4  
sdrc_strben1  
0
0
L
L
Z
Z
0
0
VDDS  
VDDS  
1.8V  
1.8V  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
sdrc_strben_  
dly1  
B12  
E3  
ddr_padref  
gpmc_a1  
gpio_34  
0
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
A
VDDS  
1.8V  
O
IO  
L
PD  
PD  
PD  
PD  
PD  
PU  
PU  
PU  
PU  
7
7
7
7
7
7
7
7
7
VDDSHV  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
30  
30  
30  
30  
30  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
gpmc_a2  
gpio_35  
E2  
E1  
F7  
F6  
F4  
F3  
F2  
F1  
O
L
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
IO  
safe_mode  
gpmc_a3  
gpio_36  
O
L
IO  
safe_mode  
gpmc_a4  
gpio_37  
O
L
IO  
safe_mode  
gpmc_a5  
gpio_38  
O
L
IO  
safe_mode  
gpmc_a6  
gpio_39  
O
H
H
H
H
IO  
safe_mode  
gpmc_a7  
gpio_40  
O
IO  
safe_mode  
gpmc_a8  
gpio_41  
O
IO  
safe_mode  
gpmc_a9  
O
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
19  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
LOAD (pF) PULL U/D IO CELL [13]  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
sys_  
1
I
ndmareq2  
gpio_42  
4
7
0
1
IO  
safe_mode  
gpmc_a10  
G6  
O
I
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
sys_  
ndmareq3  
gpio_43  
4
7
0
0
0
0
0
0
0
0
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
0
4
0
2
IO  
safe_mode  
gpmc_d0  
gpmc_d1  
gpmc_d2  
gpmc_d3  
gpmc_d4  
gpmc_d5  
gpmc_d6  
gpmc_d7  
gpmc_d8  
gpio_44  
G5  
G4  
G3  
G2  
G1  
H2  
H1  
J5  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
H
H
H
H
H
H
H
H
H
PU  
PU  
PU  
PU  
PU  
PU  
PU  
PU  
PU  
0
0
0
0
0
0
0
0
0
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
30  
30  
30  
30  
30  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
J4  
J3  
J2  
J1  
K4  
K3  
K2  
K1  
gpmc_d9  
gpio_45  
H
H
H
H
H
H
H
PU  
PU  
PU  
PU  
PU  
PU  
PU  
0
0
0
0
0
0
0
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
30  
30  
30  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
gpmc_d10  
gpio_46  
gpmc_d11  
gpio_47  
gpmc_d12  
gpio_48  
gpmc_d13  
gpio_49  
gpmc_d14  
gpio_50  
gpmc_d15  
gpio_51  
L2  
L1  
gpmc_ncs0  
gpmc_ncs1  
gpio_52  
H
H
Z
Z
0
0
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
No  
30  
30  
NA  
LVCMOS  
LVCMOS  
O
Yes  
PU/ PD  
IO  
O
M4  
gpmc_ncs2  
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
gpt9_pwm_e  
vt  
IO  
gpio_53  
4
7
0
1
IO  
safe_mode  
gpmc_ncs3  
M3  
O
I
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
sys_  
ndmareq0  
gpt10_pwm_  
evt  
2
IO  
IO  
gpio_54  
4
7
0
1
safe_mode  
gpmc_ncs4  
M2  
O
I
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
sys_  
ndmareq1  
gpt9_pwm_e  
vt  
3
IO  
IO  
gpio_55  
4
7
safe_mode  
20  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
IO CELL [13]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
M1  
N5  
N4  
gpmc_ncs5  
0
1
O
I
H
H
H
PU  
PU  
PU  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
sys_  
ndmareq2  
gpt10_pwm_  
evt  
3
IO  
IO  
gpio_56  
4
7
0
1
safe_mode  
gpmc_ncs6  
O
I
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
sys_  
ndmareq3  
gpt11_pwm_  
evt  
3
IO  
IO  
gpio_57  
4
7
0
1
3
safe_mode  
gpmc_ncs7  
gpmc_io_dir  
O
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
O
gpt8_pwm_e  
vt  
IO  
gpio_58  
4
7
0
4
0
IO  
safe_mode  
gpmc_clk  
gpio_59  
N1  
R1  
O
L
L
Z
Z
0
0
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
No  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
O
gpmc_nadv_  
ale  
R2  
R3  
R4  
gpmc_noe  
gpmc_nwe  
0
0
0
O
O
O
H
H
L
Z
Z
Z
0
0
0
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
No  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
No  
gpmc_nbe0_  
cle  
Yes  
gpio_60  
4
0
4
7
0
4
0
0
1
4
7
0
1
4
7
0
1
IO  
O
T1  
T2  
gpmc_nbe1  
gpio_61  
L
L
PD  
Z
7
0
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
safe_mode  
gpmc_nwp  
gpio_62  
O
IO  
I
T3  
T4  
gpmc_wait0  
gpmc_wait1  
uart4_tx  
H
H
PU  
PU  
0
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
I
O
IO  
gpio_63  
safe_mode  
gpmc_wait2  
uart4_rx  
T5  
U1  
I
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
I
gpio_64  
IO  
safe_mode  
gpmc_wait3  
I
I
sys_  
ndmareq1  
uart3_cts_rct  
x
2
I
gpio_65  
4
7
0
4
5
7
0
4
5
7
IO  
safe_mode  
dss_pclk  
AE23  
AD22  
O
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
20  
20  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
gpio_66  
IO  
O
hw_dbg12  
safe_mode  
dss_hsync  
gpio_67  
O
IO  
O
hw_dbg13  
safe_mode  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
21  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
IO CELL [13]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
AD23  
AE24  
AD24  
dss_vsync  
0
4
7
0
4
7
0
2
4
7
0
2
4
7
0
4
7
0
4
7
0
2
4
7
0
2
4
7
0
2
4
5
7
0
2
4
5
7
0
4
5
7
0
4
5
7
0
4
7
0
4
7
0
4
7
O
H
L
L
PU  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
Yes  
20  
PU/ PD  
LVCMOS  
gpio_68  
IO  
safe_mode  
dss_acbias  
gpio_69  
O
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
20  
20  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
safe_mode  
dss_data0  
uart1_cts  
gpio_70  
O
I
IO  
safe_mode  
dss_data1  
uart1_rts  
AD25  
O
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
20  
PU/ PD  
LVCMOS  
O
gpio_71  
IO  
safe_mode  
dss_data2  
gpio_72  
AC23  
AC24  
AC25  
O
L
L
L
PD  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
20  
20  
20  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
safe_mode  
dss_data3  
gpio_73  
O
IO  
safe_mode  
dss_data4  
uart3_rx_ irrx  
gpio_74  
O
I
IO  
safe_mode  
dss_data5  
uart3_tx_ irtx  
gpio_75  
AB24  
AB25  
O
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
20  
20  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
O
IO  
safe_mode  
dss_data6  
uart1_tx  
O
O
IO  
O
gpio_76  
hw_dbg14  
safe_mode  
dss_data7  
uart1_rx  
AA23  
O
I
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
20  
PU/ PD  
LVCMOS  
gpio_77  
IO  
O
hw_dbg15  
safe_mode  
dss_data8  
gpio_78  
AA24  
AA25  
O
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
20  
20  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
O
hw_dbg16  
safe_mode  
dss_data9  
gpio_79  
O
IO  
O
hw_dbg17  
safe_mode  
dss_data10  
gpio_80  
Y22  
Y23  
Y24  
O
L
L
L
PD  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
20  
20  
20  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
safe_mode  
dss_data11  
gpio_81  
O
IO  
safe_mode  
dss_data12  
gpio_82  
O
IO  
safe_mode  
22  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
IO CELL [13]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
Y25  
dss_data13  
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
2
3
4
7
0
2
O
L
L
L
L
L
L
PD  
PD  
PD  
PD  
PD  
PD  
7
7
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
Yes  
20  
PU/ PD  
LVCMOS  
gpio_83  
IO  
safe_mode  
dss_data14  
gpio_84  
W21  
W22  
W23  
W24  
W25  
O
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
Yes  
20  
20  
20  
20  
20  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
safe_mode  
dss_data15  
gpio_85  
O
IO  
safe_mode  
dss_data16  
gpio_86  
O
IO  
safe_mode  
dss_data17  
gpio_87  
O
IO  
safe_mode  
dss_data18  
mcspi3_clk  
dss_data4  
gpio_88  
O
IO  
O
IO  
safe_mode  
dss_data19  
V24  
O
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
20  
PU/ PD  
LVCMOS  
mcspi3_  
simo  
IO  
dss_data3  
gpio_89  
3
4
7
0
2
O
IO  
safe_mode  
dss_data20  
V25  
O
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
20  
PU/ PD  
LVCMOS  
mcspi3_  
somi  
IO  
dss_data2  
gpio_90  
3
4
7
0
2
3
4
7
0
2
3
4
7
0
3
4
7
0
0
0
0
0
0
4
5
7
O
IO  
safe_mode  
dss_data21  
mcspi3_cs0  
dss_data1  
gpio_91  
U21  
U22  
U23  
O
L
L
L
PD  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
20  
20  
20  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
O
IO  
safe_mode  
dss_data22  
mcspi3_cs1  
dss_data0  
gpio_92  
O
O
O
IO  
safe_mode  
dss_data23  
dss_data5  
gpio_93  
O
O
IO  
safe_mode  
tv_out2  
H24  
K21  
K20  
H23  
H20  
AD2  
O
O
O
O
I
0
0
0
0
0
7
VDDA_DAC 1.8V  
VDDA_DAC 1.8V  
VDDA_DAC 1.8V  
VDDA_DAC 1.8V  
VDDA_DAC 1.8V  
NA  
10-bit DAC  
10-bit DAC  
10-bit DAC  
10-bit DAC  
10-bit DAC  
LVCMOS  
tv_out1  
NA  
tv_vfb1  
Z
Z
Z
L
NA  
NA  
NA  
PD  
NA  
tv_vfb2  
NA  
tv_vref  
NA  
ccdc_pclk  
gpio_94  
IO  
IO  
O
VDDSHV  
1.8V/3.3V  
Yes  
15  
PU/ PD  
hw_dbg0  
safe_mode  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
23  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
IO CELL [13]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
AD1  
ccdc_field  
0
1
2
3
4
5
7
0
2
4
7
0
2
4
5
7
0
1
2
4
5
7
0
3
4
7
0
4
7
0
4
5
7
0
4
5
7
0
4
5
7
0
4
5
7
0
4
7
0
4
7
IO  
I
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
15  
PU/ PD  
LVCMOS  
ccdc_data8  
uart4_tx  
O
i2c3_scl  
IOD  
IO  
O
gpio_95  
hw_dbg1  
safe_mode  
ccdc_ hd  
uart4_rts  
AE2  
AD3  
IO  
O
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
15  
15  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
gpio_96  
IO  
safe_mode  
ccdc_vd  
IO  
I
uart4_cts  
gpio_97  
IO  
O
hw_dbg2  
safe_mode  
ccdc_wen  
ccdc_data9  
uart4_rx  
AE3  
IO  
I
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
15  
PU/PD  
LVCMOS  
I
gpio_98  
IO  
O
hw_dbg3  
safe_mode  
ccdc_data0  
i2c3_sda  
AD4  
I
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
15  
PU/PD  
LVCMOS  
IOD  
I
gpio_99  
safe_mode  
ccdc_data1  
gpio_100  
safe_mode  
ccdc_data2  
gpio_101  
hw_dbg4  
safe_mode  
ccdc_data3  
gpio_102  
hw_dbg5  
safe_mode  
ccdc_data4  
gpio_103  
hw_dbg6  
safe_mode  
ccdc_data5  
gpio_104  
hw_dbg7  
safe_mode  
ccdc_data6  
gpio_105  
safe_mode  
ccdc_data7  
gpio_106  
safe_mode  
AE4  
AC5  
I
I
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
15  
15  
PU/PD  
PU/ PD  
LVCMOS  
LVCMOS  
I
IO  
O
AD5  
AE5  
Y6  
I
L
L
L
PD  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
15  
15  
15  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
O
I
IO  
O
I
IO  
O
AB6  
AC6  
AE6  
I
L
L
H
PD  
PD  
PU  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
15  
15  
25  
PU/PD  
PU/PD  
PU/PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
I
IO  
rmii_mdio_da 0  
ta  
IO  
ccdc_data8  
gpio_107  
1
4
I
IO  
24  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
IO CELL [13]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
safe_mode  
7
0
AD6  
rmii_mdio_cl  
k
O
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
Yes  
25  
PU/PD  
LVCMOS  
ccdc_data9  
gpio_108  
1
4
7
0
1
4
5
7
0
1
4
5
7
0
1
4
7
0
1
4
5
7
0
I
IO  
safe_mode  
rmii_rxd0  
Y7  
I
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
25  
25  
PU/ PD  
LVCMOS  
LVCMOS  
ccdc_data10  
gpio_109  
I
IO  
O
hw_dbg8  
safe_mode  
rmii_rxd1  
AA7  
I
H
PU  
7
VDDSHV  
PU/ PD  
ccdc_data11  
gpio_110  
I
IO  
O
hw_dbg9  
safe_mode  
rmii_crs_dv  
ccdc_data12  
gpio_111  
AB7  
AC7  
I
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
25  
25  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
I
IO  
safe_mode  
rmii_rxer  
I
ccdc_data13  
gpio_167  
I
IO  
O
hw_dbg10  
safe_mode  
rmii_txd0  
AD7  
AE7  
O
I
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
NA  
25  
25  
PU/ PD  
LVCMOS  
LVCMOS  
ccdc_ data14 1  
gpio_126  
4
5
7
0
1
4
7
0
4
7
0
IO  
O
hw_dbg11  
safe_mode  
rmii_txd1  
O
I
PU/PD  
ccdc_data15  
gpio_112  
I
safe_mode  
rmii_txen  
AD8  
AE8  
O
I
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
25  
25  
PU/PD  
PU/ PD  
LVCMOS  
LVCMOS  
gpio_113  
safe_mode  
rmii_50mhz_  
clk  
I
I
gpio_114  
4
7
0
4
7
0
NA  
safe_mode  
mcbsp2_fsx  
gpio_116  
D25  
C25  
IO  
IO  
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mcbsp2_  
clkx  
IO  
IO  
Yes  
gpio_117  
4
7
0
4
7
0
4
7
0
4
safe_mode  
mcbsp2_dr  
gpio_118  
B25  
D24  
AA9  
I
L
L
L
PD  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
safe_mode  
mcbsp2_dx  
gpio_119  
IO  
IO  
safe_mode  
mmc1_clk  
gpio_120  
O
IO  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
25  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
LOAD (pF) PULL U/D IO CELL [13]  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
safe_mode  
7
0
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
1
2
4
7
0
1
AB9  
AC9  
mmc1_cmd  
gpio_121  
IO  
IO  
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
Yes  
Yes  
30  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mmc1_dat0  
mcspi2_clk  
gpio_122  
IO  
IO  
IO  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
safe_mode  
mmc1_dat1  
mcspi2_simo  
gpio_123  
AD9  
AE9  
IO  
IO  
IO  
L
L
L
PD  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
mmc1_dat2  
mcspi2_somi  
gpio_124  
IO  
IO  
IO  
safe_mode  
mmc1_dat3  
mcspi2_cs0  
gpio_125  
AA10  
IO  
O
IO  
safe_mode  
mmc1_dat4  
gpio_126  
AB10  
AC10  
AD10  
AE10  
AD11  
IO  
IO  
L
L
L
L
L
PD  
PD  
PD  
PD  
PD  
7
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
No  
No  
No  
No  
Yes  
30  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
mmc1_dat5  
gpio_127  
IO  
IO  
safe_mode  
mmc1_dat6  
gpio_128  
IO  
IO  
safe_mode  
mmc1_dat7  
gpio_129  
IO  
IO  
safe_mode  
mmc2_clk  
mcspi3_clk  
uart4_cts  
O
IO  
I
gpio_130  
IO  
safe_mode  
mmc2_ cmd  
AE11  
AB12  
AC12  
IO  
IO  
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
mcspi3_  
simo  
uart4_rts  
2
4
7
0
1
O
gpio_131  
IO  
safe_mode  
mmc2_ dat0  
IO  
IO  
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
mcspi3_  
somi  
uart4_tx  
2
4
7
0
2
4
7
0
1
O
gpio_132  
IO  
safe_mode  
mmc2_ dat1  
uart4_rx  
IO  
I
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
gpio_133  
IO  
safe_mode  
mmc2_ dat2  
mcspi3_cs1  
AD12  
IO  
O
26  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
IO CELL [13]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
gpio_134  
4
7
0
1
4
7
0
IO  
safe_mode  
mmc2_ dat3  
mcspi3_cs0  
gpio_135  
AE12  
AB13  
IO  
IO  
IO  
H
L
PU  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
Yes  
Yes  
30  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mmc2_ dat4  
IO  
O
1.8V/3.3V  
30  
PU/ PD  
mmc2_dir_da 1  
t0  
mmc3_dat0  
gpio_136  
3
4
7
0
IO  
IO  
safe_mode  
mmc2_ dat5  
AC13  
IO  
O
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
mmc2_dir_da 1  
t1  
mmc3_dat1  
gpio_137  
3
4
IO  
IO  
IO  
mm_fsusb3_r 6  
xdp  
safe_mode  
7
0
1
AD13  
mmc2_ dat6  
IO  
O
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
mmc2_dir_  
cmd  
mmc3_dat2  
gpio_138  
3
4
7
0
1
3
4
IO  
IO  
safe_mode  
mmc2_ dat7  
mmc2_ clkin  
mmc3_dat3  
gpio_139  
AE13  
IO  
I
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
IO  
IO  
IO  
mm_fsusb3_r 6  
xdm  
safe_mode  
mcbsp3_dx  
uart2_cts  
7
0
1
4
7
0
1
4
7
0
B24  
C24  
A24  
IO  
I
L
L
L
PD  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_140  
IO  
safe_mode  
mcbsp3_dr  
uart2_rts  
I
O
IO  
gpio_141  
safe_mode  
mcbsp3_  
clkx  
IO  
uart2_tx  
1
4
7
0
1
4
7
0
1
2
O
gpio_142  
safe_mode  
mcbsp3_fsx  
uart2_rx  
IO  
C23  
F20  
IO  
I
L
PD  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
gpio_143  
safe_mode  
uart2_cts  
mcbsp3_dx  
IO  
I
H
IO  
IO  
gpt9_pwm_e  
vt  
gpio_144  
safe_mode  
uart2_rts  
4
7
0
IO  
O
F19  
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
27  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
IO CELL [13]  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
[11] TYPE [12]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
mcbsp3_dr  
1
2
I
gpt10_pwm_  
evt  
IO  
gpio_145  
safe_mode  
uart2_tx  
4
7
0
1
IO  
E24  
O
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
mcbsp3_  
clkx  
IO  
gpt11_pwm  
_evt  
2
IO  
IO  
gpio_146  
safe_mode  
uart2_rx  
4
7
0
1
2
E23  
I
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
mcbsp3_fsx  
IO  
IO  
gpt8_pwm_e  
vt  
gpio_147  
safe_mode  
uart1_tx  
4
7
0
4
7
0
4
7
0
4
7
0
2
3
4
7
0
IO  
AA19  
Y19  
O
L
L
L
L
PD  
PD  
PD  
PD  
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_148  
safe_mode  
uart1_rts  
IO  
O
gpio_149  
safe_mode  
uart1_cts  
gpio_150  
safe_mode  
uart1_rx  
IO  
Y20  
I
IO  
W20  
I
mcbsp1_ clkr  
mcspi4_clk  
gpio_151  
safe_mode  
I
IO  
IO  
B23  
mcbsp4_  
clkx  
IO  
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
gpio_152  
4
IO  
IO  
mm_fsusb3_t 6  
xse0  
safe_mode  
mcbsp4_dr  
gpio_153  
7
0
4
A23  
B22  
A22  
R25  
I
L
L
L
PD  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
IO  
mm_fsusb3_r 6  
xrcv  
safe_mode  
mcbsp4_dx  
gpio_154  
7
0
4
IO  
IO  
IO  
mm_fsusb3_t 6  
xdat  
safe_mode  
mcbsp4_fsx  
gpio_155  
7
0
4
IO  
IO  
IO  
mm_fsusb3_t 6  
xen_ n  
safe_mode  
mcbsp1_ clkr  
mcspi4_clk  
gpio_156  
7
0
1
4
7
0
IO  
IO  
IO  
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mcbsp1_fsr  
P21  
IO  
28  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
IO CELL [13]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
gpio_157  
4
7
0
1
IO  
safe_mode  
mcbsp1_dx  
P22  
IO  
IO  
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
mcspi4_  
simo  
mcbsp3_dx  
gpio_158  
2
4
7
0
1
IO  
IO  
safe_mode  
mcbsp1_dr  
P23  
I
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
mcspi4_  
somi  
IO  
mcbsp3_dr  
gpio_159  
2
4
7
0
4
5
7
0
1
2
4
7
0
I
IO  
safe_mode  
mcbsp_clks  
gpio_160  
P25  
P24  
I
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
I
uart1_cts  
safe_mode  
mcbsp1_fsx  
mcspi4_cs0  
mcbsp3_fsx  
gpio_161  
IO  
IO  
IO  
IO  
safe_mode  
N24  
mcbsp1_  
clkx  
IO  
IO  
IO  
L
PD  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
LVCMOS  
LVCMOS  
mcbsp3_  
clkx  
2
gpio_162  
4
7
0
safe_mode  
N2  
uart3_cts_  
rctx  
IO  
IO  
H
PU/ PD  
gpio_163  
4
7
0
4
7
0
4
7
0
4
7
0
1
0
1
0
safe_mode  
uart3_rts_ sd  
gpio_164  
N3  
P1  
P2  
O
H
H
H
PU  
PU  
PU  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
safe_mode  
uart3_rx_ irrx  
gpio_165  
I
IO  
safe_mode  
uart3_tx_ irtx  
gpio_166  
O
IO  
safe_mode  
usb0_dp  
F25  
F24  
IO  
O
IO  
I
5.0V  
5.0V  
Yes  
Yes  
PU/ PD  
PU/ PD  
USB_PHY  
USB_PHY  
uart3_tx_ irtx  
usb0_dm  
uart3_rx_ irrx  
usb0_vbus  
G24  
G25  
E25  
A
VDDA3P3V_ 3.3V  
USBPHY  
Yes  
Yes  
PU/ PD  
PU/ PD  
USB_PHY  
USB_PHY  
LVCMOS  
usb0_id  
0
0
A
VDDA3P3V_ 3.3V  
USBPHY  
usb0_drvvbu  
s
O
L
PD  
PU  
7
7
VDDSHV  
1.8V/3.3V  
30  
24  
uart3_tx_ irtx  
gpio_125  
2
4
7
0
2
4
O
IO  
safe_mode  
hecc1_ txd  
uart3_rx_ irrx  
gpio_130  
V2  
O
I
H
VDDSHV  
1.8V/3.3V  
Yes  
PU/ PD  
LVCMOS  
IO  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
29  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
IO CELL [13]  
LVCMOS  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
safe_mode  
7
0
2
4
7
0
0
0
4
7
0
4
7
0
4
7
0
4
7
0
1
2
3
4
7
0
1
4
7
0
V3  
hecc1_ rxd  
uart3_rts_ sd  
gpio_131  
safe_mode  
i2c1_scl  
I
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
24  
PU/ PD  
O
IO  
V4  
V5  
W1  
IOD  
IOD  
IOD  
IO  
H
H
H
PU  
PU  
PU  
0
0
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
40  
40  
40  
PU/ PD  
PU/ PD  
PU/ PD  
Open Drain  
Open Drain  
Open Drain  
i2c1_ sda  
i2c2_scl  
gpio_168  
safe_mode  
i2c2_sda  
W2  
W4  
W5  
L25  
IOD  
IO  
H
H
H
H
PU  
PU  
PU  
PU  
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
40  
40  
40  
40  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
Open Drain  
Open Drain  
Open Drain  
LVCMOS  
gpio_183  
safe_mode  
i2c3_scl  
IOD  
IO  
gpio_184  
safe_mode  
i2c3_sda  
IOD  
IO  
gpio_185  
safe_mode  
hdq_sio  
IO  
I
sys_altclk  
i2c2_sccbe  
i2c3_sccbe  
gpio_170  
safe_mode  
mcspi1_clk  
mmc2_dat4  
gpio_171  
safe_mode  
O
O
IO  
AE14  
AD15  
IO  
IO  
IO  
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
mcspi1_  
simo  
IO  
mmc2_dat5  
gpio_172  
1
4
7
0
IO  
IO  
safe_mode  
AC15  
mcspi1_  
somi  
IO  
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
mmc2_dat6  
gpio_173  
1
4
7
0
1
4
7
0
3
4
7
0
3
4
7
0
3
IO  
IO  
safe_mode  
mcspi1_cs0  
mmc2_dat7  
gpio_174  
AB15  
AD14  
AE15  
AE16  
IO  
IO  
IO  
H
H
H
H
PU  
PU  
PU  
PU  
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
mcspi1_cs1  
mmc3_cmd  
gpio_175  
O
IO  
IO  
safe_mode  
mcspi1_cs2  
mmc3_clk  
gpio_176  
O
O
IO  
safe_mode  
mcspi1_cs3  
O
hsusb2_  
data2  
IO  
gpio_177  
4
IO  
30  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
IO CELL [13]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
mm_fsusb2_t 5  
IO  
xdat  
safe_mode  
mcspi2_clk  
7
0
3
AD16  
AC16  
IO  
IO  
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
Yes  
Yes  
30  
PU/ PD  
LVCMOS  
LVCMOS  
hsusb2_  
data7  
gpio_178  
4
7
0
IO  
safe_mode  
mcspi2_  
simo  
IO  
IO  
IO  
IO  
1.8V/3.3V  
30  
PU/ PD  
gpt9_pwm_e  
vt  
1
3
hsusb2_  
data4  
gpio_179  
4
7
0
safe_mode  
AB16  
mcspi2_  
somi  
IO  
IO  
IO  
IO  
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
gpt10_pwm_  
evt  
1
3
hsusb2_  
data5  
gpio_180  
4
7
0
1
safe_mode  
mcspi2_cs0  
AA16  
IO  
IO  
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
gpt11_pwm_  
evt  
hsusb2_  
data6  
3
IO  
IO  
gpio_181  
4
7
0
1
safe_mode  
mcspi2_cs1  
AE17  
O
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
gpt8_pwm_e  
vt  
IO  
hsusb2_  
data3  
3
IO  
gpio_182  
4
IO  
IO  
mm_fsusb2_t 5  
xen_ n  
safe_mode  
sys_32k  
7
0
0
0
0
4
0
4
7
0
K24  
K25  
H25  
M24  
I
Z
Z
Z
L
Z
Z
Z
Z
0
0
0
0
VDDSHV  
VDDSOSC  
VDDSOSC  
VDDSHV  
1.8V/3.3V  
1.8V  
Yes  
NA  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
sys_xtalin  
sys_xtalout  
sys_clkreq  
gpio_1  
I
O
IO  
IO  
I
1.8V  
NA  
1.8V/3.3V  
Yes  
30  
30  
Y1  
sys_nirq  
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
PU/ PD  
LVCMOS  
gpio_0  
IO  
safe_mode  
Y2  
Y3  
sys_  
nrespwron  
I
Z
L
Z
0
0
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
sys_  
0
IO  
PD  
nreswarm  
gpio_30  
sys_boot0  
gpio_2  
4
0
4
0
4
0
4
IO  
I
Open Drain  
LVCMOS  
Y4  
Z
Z
Z
Z
Z
Z
0
0
0
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
IO  
I
AA1  
AA2  
sys_boot1  
gpio_3  
LVCMOS  
LVCMOS  
IO  
I
sys_boot2  
gpio_4  
IO  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
31  
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Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
LOAD (pF) PULL U/D IO CELL [13]  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
AA3  
sys_boot3  
0
4
0
I
Z
Z
0
VDDSHV  
VDDSHV  
1.8V/3.3V  
Yes  
Yes  
30  
PU/ PD  
LVCMOS  
LVCMOS  
gpio_5  
IO  
I
AB1  
sys_boot4  
Z
Z
0
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
mmc2_dir_da 1  
t2  
O
gpio_6  
4
0
IO  
I
AB2  
AC1  
sys_boot5  
Z
Z
Z
Z
0
0
VDDSHV  
Yes  
LVCMOS  
mmc2_dir_da 1  
t3  
O
gpio_7  
4
0
4
0
0
0
4
7
0
4
7
0
0
0
IO  
I
sys_boot6  
gpio_8  
VDDSHV  
Yes  
LVCMOS  
IO  
I
AC2  
AC3  
N25  
sys_boot7  
sys_boot8  
sys_clkout1  
gpio_10  
Z
Z
H
Z
0
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
30  
30  
30  
PU/PD  
PU/PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
I
Z
0
O
IO  
PD  
0/7(1)  
safe_mode  
sys_clkout2  
gpio_186  
safe_mode  
jtag_ntrst  
jtag_tck  
M25  
O
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
10  
PU/ PD  
LVCMOS  
IO  
U24  
U25  
T21  
T22  
I
L
L
L
H
PD  
PD  
Z
0
0
0
0
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
20  
20  
20  
20  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
I
jtag_rtck  
O
IO  
jtag_tms_tms 0  
c
PU  
T23  
T24  
T25  
jtag_tdi  
0
0
0
4
0
4
0
1
I
H
L
PU  
Z
0
0
0
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
20  
20  
20  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
jtag_tdo  
jtag_emu0  
gpio_11  
jtag_emu1  
gpio_31  
etk_clk  
O
IO  
IO  
IO  
IO  
O
H
PU  
R24  
H
H
PU  
PU  
0
4
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
20  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
AD17  
9, 25  
mcbsp5_  
clkx  
IO  
mmc3_clk  
hsusb1_stp  
gpio_12  
2
3
4
0
2
3
4
O
O
IO  
O
AE18  
etk_ctl  
H
PU  
4
VDDSHV  
1.8V/3.3V  
Yes  
9, 25  
PU/ PD  
LVCMOS  
mmc3_cmd  
hsusb1_clk  
gpio_13  
IO  
O
IO  
IO  
mm_fsusb1_r 5  
xdp  
AD18  
etk_d0  
0
1
O
H
PU  
4
VDDSHV  
1.8V/3.3V  
Yes  
9, 25  
PU/ PD  
LVCMOS  
mcspi3_  
simo  
IO  
mmc3_dat4  
2
3
IO  
IO  
hsusb1_  
data0  
gpio_14  
4
IO  
IO  
mm_fsusb1_r 5  
xrcv  
AC18  
etk_d1  
0
1
O
H
PU  
4
VDDSHV  
1.8V/3.3V  
Yes  
9, 25  
PU/ PD  
LVCMOS  
mcspi3_  
somi  
IO  
hsusb1_  
data1  
3
IO  
(1) Mux0 if sys_boot6 is pulled down (clock master).  
32 Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
IO CELL [13]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
gpio_15  
4
IO  
IO  
mm_fsusb1_t 5  
xse0  
AB18  
etk_d2  
0
1
3
O
H
PU  
4
VDDSHV  
1.8V/3.3V  
Yes  
9, 25  
PU/ PD  
LVCMOS  
mcspi3_cs0  
IO  
IO  
hsusb1_  
data2  
gpio_16  
4
IO  
IO  
mm_fsusb1_t 5  
xdat  
AA18  
etk_d3  
0
1
2
3
O
L
L
L
L
L
PU  
PD  
PD  
PD  
PD  
4
4
4
4
4
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
Yes  
9, 25  
9, 25  
9, 25  
9, 25  
9, 25  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
mcspi3_clk  
mmc3_dat3  
IO  
IO  
IO  
hsusb1_  
data7  
gpio_17  
4
0
1
2
3
IO  
O
I
Y18  
etk_d4  
mcbsp5_dr  
mmc3_dat0  
IO  
IO  
hsusb1_  
data4  
gpio_18  
4
0
1
2
3
IO  
O
AE19  
AD19  
AB19  
etk_d5  
mcbsp5_fsx  
mmc3_dat1  
IO  
IO  
IO  
hsusb1_  
data5  
gpio_19  
4
0
1
2
3
IO  
O
etk_d6  
mcbsp5_dx  
mmc3_dat2  
IO  
IO  
IO  
hsusb1_  
data6  
gpio_20  
4
0
1
2
3
IO  
O
etk_d7  
mcspi3_cs1  
mmc3_dat7  
O
IO  
IO  
hsusb1_  
data3  
gpio_21  
4
IO  
IO  
mm_fsusb1_t 5  
xen_n  
AE20  
AD20  
etk_d8  
0
2
3
4
0
2
3
4
O
IO  
I
L
L
PD  
PD  
4
4
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
9, 25  
9, 25  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
mmc3_dat6  
hsusb1_dir  
gpio_22  
IO  
O
IO  
I
etk_d9  
mmc3_dat5  
hsusb1_nxt  
gpio_23  
IO  
IO  
mm_fsusb1_r 5  
xdm  
AC20  
AB20  
etk_d10  
0
2
3
4
0
1
O
I
L
L
PD  
PD  
4
4
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
9, 25  
9, 25  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
uart1_rx  
hsusb2_clk  
gpio_24  
O
IO  
O
IO  
etk_d11  
mcspi3_clk  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
33  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
LOAD (pF) PULL U/D IO CELL [13]  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
[11]  
TYPE [12]  
hsusb2_stp  
gpio_25  
3
4
O
IO  
IO  
mm_fsusb2_r 5  
xdp  
AE21  
AD21  
etk_d12  
0
3
4
0
3
4
O
I
L
L
PD  
PD  
4
4
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
9, 25  
9, 25  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
hsusb2_dir  
gpio_26  
IO  
O
I
etk_d13  
hsusb2_nxt  
gpio_27  
IO  
IO  
mm_fsusb2_r 5  
xdm  
AC21  
AE22  
etk_d14  
0
3
O
L
L
PD  
PD  
4
4
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.2V  
Yes  
Yes  
9, 25  
PU/ PD  
LVCMOS  
LVCMOS  
hsusb2_  
data0  
IO  
gpio_28  
4
IO  
IO  
mm_fsusb2_r 5  
xrcv  
etk_d15  
0
3
O
9, 25  
PU/ PD  
hsusb2_  
data1  
IO  
gpio_29  
4
IO  
IO  
mm_fsusb2_t 5  
xse0  
V16, V15,  
V11, V10,  
U16, U15,  
U11, U10,  
T18, T17, T9,  
T8, R18,  
VDD_CORE  
0
PWR  
R17, R9, R8,  
M18, L18,  
L9, L8, K18,  
K17, K9, K8,  
J16, J15,  
J11, J10,  
H15, H11,  
H10  
AA13  
VDDS_SRA  
M_MPU  
0
0
PWR  
PWR  
1.8V  
1.8V  
E17  
VDDS_SRA  
M_CORE_B  
G
AA12  
E16  
CAP_VDD_S 0  
RAM_MPU  
PWR  
PWR  
PWR  
1.2V  
1.2V  
1.8V  
CAP_VDD_S 0  
RAM_CORE  
AA15  
VDDS_DPLL  
_MPU_USB  
HOST  
0
N20  
VDDS_DPLL  
_PER_CORE  
0
PWR  
1.8V  
H21  
F23  
VDDA_DAC  
0
0
PWR  
PWR  
1.8V  
3.3V  
VDDA3P3V_  
USBPHY  
G22  
F22  
VDDA1P8V_  
USBPHY  
0
PWR  
PWR  
1.8V  
1.2V  
CAP_VDDA1 0  
P2LDO_USB  
PHY  
34  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)  
BALL  
LOCATION [2]  
[1]  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
RESET  
STATE [5]  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF) PULL U/D  
[11] TYPE [12]  
IO CELL [13]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
Y16, Y15,  
VDDSHV  
0
PWR  
1.8V/3.3V  
Y13, Y12,  
Y10, W16,  
W15, W13,  
W12,W10,  
W9, W6, V7,  
V6, U19,  
T20, T19, T7,  
T6, R7, R6,  
P20, P19,  
N19, N7, N6,  
M7, M6, M5,  
L19, K19,  
K7, K6, K5,  
J7, H18, H17  
Y9, W18,  
U20, R5,  
H16, H8,  
G17, G16,  
G14, G13,  
G11, G10,  
G8, F16,  
F13, F11,  
F10, F8  
VDDS  
0
PWR  
1.8V  
F14  
L20  
J25  
VREFSSTL  
VDDSOSC  
VSSOSC  
0
0
O
0
I
PWR  
GND  
GND  
1.8V  
1.8V  
AE25, AE1, VSS  
V18, V17,  
V14, V13,  
V12, V9, V8,  
U18, U17,  
U14, U13,  
U12, U9, U8,  
T14, T13,  
T12, R16,  
R15, R14,  
R13, R12,  
R11, R10,  
P18, P17,  
P16, P15,  
P14, P13,  
P12, P11,  
P10, P9, P8,  
N18, N17,  
N14, N13,  
N12, N9, N8,  
M17, M16,  
M15, M14,  
M13,M12,  
M11, M10,  
M9, M8, L17,  
L16, L15,  
L14, L13,  
L12, L11,  
L10, K14,  
K13, K12,  
J18, J17,  
J14, J13,  
J12, J9, J8,  
H14, H13,  
H12, H9,  
A25, A1,  
N23, G20,  
G21  
H22  
VSSA_DAC  
0
GND  
L24, L23,  
L22, L21,  
K23, K22,  
H19,  
NC(2)  
N22,N21,F17  
U2(3)  
V1(3)  
Reserved  
Reserved  
(2) "NC" indicates "No Connect". For proper device operation, these pins must be left unconnected.  
(3) For proper device operation, this pin must be pulled up to VDDSHV via a 10k-Ω resistor.  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Terminal Description  
35  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
IO CELL [13]  
Table 2-2. Ball Characteristics (ZER Pkg.)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
E3  
D3  
C3  
C2  
F3  
sdrc_d0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
sdrc_d1  
sdrc_d2  
sdrc_d3  
sdrc_d4  
D2  
C1  
D1  
G2  
G3  
H3  
G4  
H4  
G1  
J3  
sdrc_d5  
sdrc_d6  
sdrc_d7  
sdrc_d8  
sdrc_d9  
sdrc_d10  
sdrc_d11  
sdrc_d12  
sdrc_d13  
sdrc_d14  
sdrc_d15  
sdrc_d16  
sdrc_d17  
sdrc_d18  
sdrc_d19  
sdrc_d20  
sdrc_d21  
sdrc_d22  
sdrc_d23  
sdrc_d24  
sdrc_d25  
sdrc_d26  
sdrc_d27  
sdrc_d28  
sdrc_d29  
sdrc_d30  
sdrc_d31  
sdrc_ba0  
sdrc_ba1  
sdrc_ba2  
sdrc_a0  
J1  
T3  
U3  
U4  
V4  
V1  
V2  
V5  
V3  
W3  
W4  
Y3  
Y4  
AA2  
AA3  
AA4  
AB2  
L4  
K5  
J5  
O
No  
O
No  
M3  
M4  
M5  
N3  
N2  
N4  
P3  
P2  
P1  
P4  
R1  
R2  
R3  
R4  
T2  
O
No  
sdrc_a1  
O
No  
sdrc_a2  
O
No  
sdrc_a3  
O
No  
sdrc_a4  
O
No  
sdrc_a5  
O
No  
sdrc_a6  
O
No  
sdrc_a7  
O
No  
sdrc_a8  
O
No  
sdrc_a9  
O
No  
sdrc_a10  
sdrc_a11  
sdrc_a12  
sdrc_a13  
sdrc_a14  
sdrc_ncs0  
sdrc_ncs1  
sdrc_clk  
sdrc_nclk  
O
No  
O
No  
O
No  
O
No  
O
No  
J4  
O
No  
K4  
L1  
O
No  
O
Yes  
No  
L2  
O
36  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
 
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
LOCATION [2]  
[1]  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
RESET  
STATE [5]  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
IO CELL [13]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
K3  
sdrc_cke0  
0
7
O
I
L
PD  
7
VDDS  
1.8V  
Yes  
8
PU/ PD  
LVCMOS  
sdrc_cke0_s  
afe  
K1  
L3  
sdrc_nras  
sdrc_ncas  
sdrc_nwe  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
VDDS  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
1.8V  
No  
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
O
No  
K2  
F4  
J2  
O
No  
sdrc_dm0  
sdrc_dm1  
sdrc_dm2  
sdrc_dm3  
sdrc_dqs0p  
sdrc_dqs1p  
sdrc_dqs2p  
sdrc_dqs3p  
sdrc_dqs0n  
sdrc_dqs1n  
sdrc_dqs2n  
sdrc_dqs3n  
sdrc_odt  
O
No  
O
No  
T4  
AB3  
E2  
H2  
U1  
Y1  
E1  
H1  
U2  
Y2  
T1  
F2  
F1  
O
No  
O
No  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
Yes  
Yes  
Yes  
Yes  
sdrc_strben0  
sdrc_strben_  
dly0  
W1  
W2  
sdrc_strben1  
0
0
L
L
Z
Z
0
0
VDDS  
VDDS  
1.8V  
1.8V  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
sdrc_strben_  
dly1  
W5  
gpmc_a1  
gpio_34  
gpmc_a2  
gpio_35  
gpmc_a3  
gpio_36  
gpmc_a4  
gpio_37  
gpmc_a5  
gpio_38  
gpmc_a6  
gpio_39  
gpmc_a7  
gpio_40  
gpmc_a8  
gpio_41  
gpmc_a9  
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
1
O
L
PD  
PD  
PD  
PD  
PD  
PU  
PU  
PU  
PU  
7
7
7
7
7
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
30  
30  
30  
30  
30  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
O
Y5  
L
IO  
O
AB4  
AA5  
AB5  
AB6  
AA6  
W6  
L
IO  
O
L
IO  
O
L
IO  
O
H
H
H
H
IO  
O
IO  
O
IO  
O
AB7  
sys_  
I
ndmareq2  
gpio_42  
4
0
1
IO  
O
I
Y6  
gpmc_a10  
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
sys_  
ndmareq3  
gpio_43  
4
0
0
0
0
0
0
0
0
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AA7  
Y7  
gpmc_d0  
gpmc_d1  
gpmc_d2  
gpmc_d3  
gpmc_d4  
gpmc_d5  
gpmc_d6  
gpmc_d7  
H
H
H
H
H
H
H
H
PU  
PU  
PU  
PU  
PU  
PU  
PU  
PU  
0
0
0
0
0
0
0
0
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
30  
30  
30  
30  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
W7  
AA9  
Y8  
AA8  
AB8  
W8  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
37  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
IO CELL [13]  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
W10  
AB9  
AB10  
W9  
gpmc_d8  
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
0
4
0
2
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
H
H
H
H
H
H
H
H
PU  
PU  
PU  
PU  
PU  
PU  
PU  
PU  
0
0
0
0
0
0
0
0
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
30  
30  
30  
30  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_44  
gpmc_d9  
gpio_45  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
gpmc_d10  
gpio_46  
gpmc_d11  
gpio_47  
AA10  
Y9  
gpmc_d12  
gpio_48  
gpmc_d13  
gpio_49  
V10  
V9  
gpmc_d14  
gpio_50  
gpmc_d15  
gpio_51  
Y10  
Y11  
gpmc_ncs0  
gpmc_ncs1  
gpio_52  
H
H
Z
Z
0
0
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
No  
30  
30  
NA  
LVCMOS  
LVCMOS  
O
Yes  
PU/ PD  
IO  
O
Y12  
gpmc_ncs2  
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
Yes  
30  
PU/ PD  
PU/ PD  
LVCMOS  
gpt9_pwm_e  
vt  
IO  
gpio_53  
4
0
1
IO  
O
I
V12  
gpmc_ncs3  
H
PU  
7
VDDSHV  
1.8V/3.3V  
30  
LVCMOS  
sys_  
ndmareq0  
gpt10_pwm_  
evt  
2
IO  
gpio_54  
4
0
1
IO  
O
I
AA11  
W12  
AA12  
V11  
gpmc_ncs4  
H
H
H
H
PU  
PU  
PU  
PU  
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
sys_  
ndmareq1  
gpt9_pwm_e  
vt  
3
IO  
gpio_55  
4
0
1
IO  
O
I
gpmc_ncs5  
sys_  
ndmareq2  
gpt10_pwm_  
evt  
3
IO  
gpio_56  
4
0
1
IO  
O
I
gpmc_ncs6  
sys_  
ndmareq3  
gpt11_pwm_  
evt  
3
IO  
gpio_57  
4
0
1
3
IO  
O
gpmc_ncs7  
gpmc_io_dir  
O
gpt8_pwm_e  
vt  
IO  
gpio_58  
gpmc_clk  
gpio_59  
4
0
4
0
IO  
O
AB13  
AA14  
L
L
Z
Z
0
0
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
No  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
O
gpmc_nadv_  
ale  
AB14  
AA15  
gpmc_noe  
gpmc_nwe  
0
0
O
O
H
H
Z
Z
0
0
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
No  
No  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
38  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
LOCATION [2]  
[1]  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
RESET  
STATE [5]  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
IO CELL [13]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
W11  
gpmc_nbe0_  
0
O
L
Z
0
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
cle  
gpio_60  
4
0
4
0
4
0
0
1
4
0
1
4
0
1
IO  
O
IO  
O
IO  
I
Y15  
gpmc_nbe1  
gpio_61  
L
L
PD  
Z
7
0
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
W14  
gpmc_nwp  
gpio_62  
V13  
gpmc_wait0  
gpmc_wait1  
uart4_tx  
H
H
PU  
PU  
0
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
AA16  
I
O
IO  
I
gpio_63  
Y14  
V14  
gpmc_wait2  
uart4_rx  
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
I
gpio_64  
IO  
I
gpmc_wait3  
sys_  
I
ndmareq1  
uart3_cts_rct  
x
2
I
gpio_65  
4
0
4
5
0
4
5
0
4
0
4
0
2
4
0
2
4
0
4
0
4
0
2
4
0
2
4
0
2
4
5
0
2
4
5
0
4
IO  
O
IO  
O
O
IO  
O
O
IO  
O
IO  
O
I
B22  
B21  
dss_pclk  
gpio_66  
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
20  
20  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
hw_dbg12  
dss_hsync  
gpio_67  
hw_dbg13  
dss_vsync  
gpio_68  
B20  
B19  
A20  
H
L
L
PU  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
20  
20  
20  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
dss_acbias  
gpio_69  
dss_data0  
uart1_cts  
gpio_70  
IO  
O
O
IO  
O
IO  
O
IO  
O
I
A19  
dss_data1  
uart1_rts  
gpio_71  
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
20  
PU/ PD  
LVCMOS  
A18  
B18  
A17  
dss_data2  
gpio_72  
L
L
L
PD  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
20  
20  
20  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
dss_data3  
gpio_73  
dss_data4  
uart3_rx_irrx  
gpio_74  
IO  
O
O
IO  
O
O
IO  
O
O
I
C18  
D17  
dss_data5  
uart3_tx_irtx  
gpio_75  
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
20  
20  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
dss_data6  
uart1_tx  
gpio_76  
hw_dbg14  
dss_data7  
uart1_rx  
B16  
B17  
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
20  
20  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
gpio_77  
IO  
O
O
IO  
hw_dbg15  
dss_data8  
gpio_78  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
39  
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Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
IO CELL [13]  
LVCMOS  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
hw_dbg16  
5
0
4
5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
2
3
4
0
2
O
C17  
dss_data9  
gpio_79  
O
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
20  
PU/ PD  
IO  
O
hw_dbg17  
dss_data10  
gpio_80  
C16  
D16  
D14  
A16  
D15  
B15  
A15  
A14  
C13  
O
L
L
L
L
L
L
L
L
L
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
7
7
7
7
7
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
20  
20  
20  
20  
20  
20  
20  
20  
20  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
O
dss_data11  
gpio_81  
IO  
O
dss_data12  
gpio_82  
IO  
O
dss_data13  
gpio_83  
IO  
O
dss_data14  
gpio_84  
IO  
O
dss_data15  
gpio_85  
IO  
O
dss_data16  
gpio_86  
IO  
O
dss_data17  
gpio_87  
IO  
O
dss_data18  
mcspi3_clk  
dss_data4  
gpio_88  
IO  
O
IO  
O
C15  
A13  
B13  
dss_data19  
L
L
L
PD  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
20  
20  
20  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
mcspi3_  
simo  
IO  
dss_data3  
gpio_89  
3
4
0
2
O
IO  
O
dss_data20  
mcspi3_  
somi  
IO  
dss_data2  
gpio_90  
3
4
0
2
3
4
0
2
4
0
3
4
0
4
5
0
1
2
3
4
5
0
2
O
IO  
O
dss_data21  
mcspi3_cs0  
dss_data1  
gpio_91  
IO  
O
IO  
O
C14  
dss_data22  
mcspi3_cs1  
gpio_92  
L
L
L
L
PD  
PD  
PD  
PD  
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
20  
20  
15  
15  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
O
IO  
O
B14  
dss_data23  
dss_data5  
gpio_93  
O
IO  
IO  
IO  
O
AB21  
AA21  
ccdc_pclk  
gpio_94  
hw_dbg0  
ccdc_field  
ccdc_data8  
uart4_tx  
IO  
I
O
i2c3_scl  
IO  
IO  
O
gpio_95  
hw_dbg1  
ccdc_ hd  
uart4_rts  
Y21  
IO  
O
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
15  
PU/ PD  
LVCMOS  
40  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
LOCATION [2]  
[1]  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
RESET  
STATE [5]  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
IO CELL [13]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
gpio_96  
4
0
2
4
5
0
1
2
4
5
0
3
4
0
4
0
4
5
0
4
5
0
4
5
0
4
5
0
4
0
4
IO  
IO  
I
Y22  
ccdc_vd  
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
Yes  
15  
15  
PU/ PD  
PU/PD  
LVCMOS  
uart4_cts  
gpio_97  
IO  
O
IO  
I
hw_dbg2  
ccdc_wen  
ccdc_data9  
uart4_rx  
W21  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
LVCMOS  
LVCMOS  
I
gpio_98  
IO  
O
I
hw_dbg3  
ccdc_data0  
i2c3_sda  
gpio_99  
W22  
L
PD  
7
VDDSHV  
15  
PU/PD  
IO  
I
W20  
V21  
ccdc_data1  
gpio_100  
ccdc_data2  
gpio_101  
hw_dbg4  
ccdc_data3  
gpio_102  
hw_dbg5  
ccdc_data4  
gpio_103  
hw_dbg6  
ccdc_data5  
gpio_104  
hw_dbg7  
ccdc_data6  
gpio_105  
ccdc_data7  
gpio_106  
I
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
15  
15  
PU/PD  
PU/ PD  
LVCMOS  
LVCMOS  
I
I
IO  
O
I
V19  
V22  
U20  
L
L
L
PD  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
15  
15  
15  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
O
I
IO  
O
I
IO  
O
I
V20  
U19  
U21  
L
L
H
PD  
PD  
PU  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
15  
15  
25  
PU/PD  
PU/PD  
PU/PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
I
IO  
IO  
rmii_mdio_da 0  
ta  
ccdc_data8  
gpio_107  
1
4
I
IO  
O
I
8
U22  
T19  
rmii_mdio_clk 0  
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
8
25  
25  
PU/PD  
PU/ PD  
LVCMOS  
LVCMOS  
ccdc_data9  
gpio_108  
1
4
0
1
4
5
0
1
4
5
0
1
4
0
1
4
5
IO  
I
rmii_rxd0  
Yes  
ccdc_data10  
gpio_109  
I
IO  
O
I
hw_dbg8  
T20  
rmii_rxd1  
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
25  
PU/ PD  
LVCMOS  
ccdc_data11  
gpio_110  
I
IO  
O
I
hw_dbg9  
T21  
R22  
rmii_crs_dv  
ccdc_data12  
gpio_111  
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
25  
25  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
I
IO  
I
rmii_rxer  
ccdc_data13  
gpio_167  
I
IO  
O
hw_dbg10  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
41  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
LOCATION [2]  
[1]  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
RESET  
STATE [5]  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
IO CELL [13]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
T22  
rmii_txd0  
0
1
4
5
0
1
4
0
4
0
O
I
H
PU  
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
Yes  
25  
PU/ PD  
LVCMOS  
ccdc_ data14  
gpio_126  
IO  
O
O
I
hw_dbg11  
rmii_txd1  
R20  
H
PU  
7
1.8V/3.3V  
Yes  
NA  
25  
PU/PD  
LVCMOS  
ccdc_data15  
gpio_112  
I
R19  
R21  
rmii_txen  
O
I
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
25  
25  
PU/PD  
PU/ PD  
LVCMOS  
LVCMOS  
gpio_113  
rmii_50mhz_  
clk  
I
gpio_114  
mcbsp2_fsx  
gpio_116  
4
0
4
I
NA  
E5  
IO  
IO  
IO  
IO  
I
L
L
L
L
L
L
L
PD  
PD  
PD  
PD  
PD  
PD  
PD  
7
7
7
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
30  
30  
30  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
D5  
mcbsp2_ clkx 0  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
gpio_117  
4
0
4
0
4
0
4
0
4
0
1
4
0
1
4
0
1
4
0
1
4
0
4
0
4
0
4
0
4
0
1
2
4
0
1
C5  
mcbsp2_dr  
gpio_118  
IO  
IO  
IO  
O
E4  
mcbsp2_dx  
gpio_119  
P22  
N21  
P21  
mmc1_clk  
gpio_120  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
mmc1_cmd  
gpio_121  
mmc1_dat0  
mcspi2_clk  
gpio_122  
N20  
P19  
P20  
mmc1_dat1  
mcspi2_simo  
gpio_123  
L
L
L
PD  
PD  
PD  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
mmc1_dat2  
mcspi2_somi  
gpio_124  
mmc1_dat3  
mcspi2_cs0  
gpio_125  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
N22  
N19  
N18  
P18  
M21  
mmc1_dat4  
gpio_126  
L
L
L
L
L
PD  
PD  
PD  
PD  
PD  
7
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
No  
No  
No  
No  
Yes  
30  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
mmc1_dat5  
gpio_127  
mmc1_dat6  
gpio_128  
mmc1_dat7  
gpio_129  
mmc2_clk  
mcspi3_clk  
uart4_cts  
IO  
I
gpio_130  
IO  
IO  
IO  
M20  
mmc2_ cmd  
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
mcspi3_  
simo  
uart4_rts  
2
4
0
1
O
gpio_131  
IO  
IO  
IO  
K20  
mmc2_ dat0  
mcspi3_  
somi  
42  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
LOCATION [2]  
[1]  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
RESET  
STATE [5]  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
IO CELL [13]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
uart4_tx  
2
4
0
2
4
0
1
4
0
1
4
0
O
gpio_132  
IO  
IO  
I
L19  
M18  
K21  
L18  
mmc2_ dat1  
uart4_rx  
H
H
H
L
PU  
PU  
PU  
PD  
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_133  
IO  
IO  
O
mmc2_ dat2  
mcspi3_cs1  
gpio_134  
IO  
IO  
IO  
IO  
IO  
O
mmc2_ dat3  
mcspi3_cs0  
gpio_135  
mmc2_ dat4  
mmc2_dir_da 1  
t0  
mmc3_dat0  
gpio_136  
3
4
0
IO  
IO  
IO  
O
L20  
mmc2_ dat5  
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
mmc2_dir_da 1  
t1  
mmc3_dat1  
gpio_137  
3
4
IO  
IO  
IO  
mm_fsusb3_r 6  
xdp  
L21  
mmc2_ dat6  
0
1
IO  
O
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
mmc2_dir_c  
md  
mmc3_dat2  
gpio_138  
3
4
0
1
3
4
IO  
IO  
IO  
I
M19  
mmc2_ dat7  
mmc2_clkin  
mmc3_dat3  
gpio_139  
IO  
IO  
IO  
mm_fsusb3_r 6  
xdm  
C4  
B4  
D4  
A4  
A5  
mcbsp3_dx  
uart2_cts  
gpio_140  
mcbsp3_dr  
uart2_rts  
0
1
4
0
1
4
IO  
I
L
L
L
L
H
PD  
PD  
PD  
PD  
PU  
7
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
Yes  
30  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
I
O
IO  
IO  
O
IO  
IO  
I
gpio_141  
mcbsp3_ clkx 0  
uart2_tx  
1
4
0
1
4
0
1
2
gpio_142  
mcbsp3_fsx  
uart2_rx  
gpio_143  
uart2_cts  
mcbsp3_dx  
IO  
I
IO  
IO  
gpt9_pwm_e  
vt  
gpio_144  
uart2_rts  
mcbsp3_dr  
4
0
1
2
IO  
O
I
B5  
D6  
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
gpt10_pwm_  
evt  
IO  
gpio_145  
uart2_tx  
4
0
IO  
O
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
43  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
IO CELL [13]  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
mcbsp3_clkx  
1
2
IO  
IO  
gpt11_pwm  
_evt  
gpio_146  
uart2_rx  
4
0
1
2
IO  
I
C6  
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
mcbsp3_fsx  
IO  
IO  
gpt8_pwm_e  
vt  
gpio_147  
uart1_tx  
4
0
4
0
4
0
4
0
2
3
4
IO  
O
IO  
O
IO  
I
C22  
C21  
C19  
C20  
L
L
L
L
PD  
PD  
PD  
PD  
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_148  
uart1_rts  
gpio_149  
uart1_cts  
gpio_150  
uart1_rx  
IO  
I
mcbsp1_ clkr  
mcspi4_clk  
gpio_151  
I
IO  
IO  
IO  
IO  
IO  
A3  
B3  
A2  
B2  
B11  
mcbsp4_ clkx 0  
gpio_152  
L
L
L
L
L
PD  
PD  
PD  
PD  
PD  
7
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
Yes  
30  
30  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
4
mm_fsusb3_t 6  
xse0  
mcbsp4_dr  
gpio_153  
0
4
I
IO  
IO  
mm_fsusb3_r 6  
xrcv  
mcbsp4_dx  
gpio_154  
0
4
IO  
IO  
IO  
mm_fsusb3_t 6  
xdat  
mcbsp4_fsx  
gpio_155  
0
4
IO  
IO  
IO  
mm_fsusb3_t 6  
xen_n  
mcbsp1_ clkr  
mcspi4_clk  
gpio_156  
0
1
4
0
4
0
1
IO  
IO  
IO  
IO  
IO  
IO  
IO  
D11  
C10  
mcbsp1_fsr  
gpio_157  
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
mcbsp1_dx  
mcspi4_  
simo  
mcbsp3_dx  
gpio_158  
2
4
0
1
I
IO  
I
C9  
mcbsp1_dr  
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
mcspi4_  
somi  
IO  
mcbsp3_dr  
gpio_159  
2
4
0
4
5
0
1
2
4
I
IO  
I
E11  
C11  
mcbsp_clks  
gpio_160  
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
I
uart1_cts  
mcbsp1_fsx  
mcspi4_cs0  
mcbsp3_fsx  
gpio_161  
IO  
IO  
IO  
IO  
IO  
C8  
mcbsp1_ clkx 0  
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
44  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
LOCATION [2]  
[1]  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
RESET  
STATE [5]  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
IO CELL [13]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
mcbsp3_clkx  
2
4
0
IO  
IO  
IO  
gpio_162  
W15  
uart3_cts_rct  
x
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
gpio_163  
4
0
4
0
4
0
4
0
0
0
IO  
O
W13  
AA13  
Y13  
uart3_rts_sd  
gpio_164  
H
H
H
PU  
PU  
PU  
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
I
uart3_rx_irrx  
gpio_165  
IO  
O
uart3_tx_irtx  
gpio_166  
IO  
IO  
IO  
A
A6  
B6  
C7  
usb0_dp  
5.0V  
5.0V  
Yes  
Yes  
Yes  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
usb0_dm  
usb0_vbus  
VDDA3P3V_ 3.3V  
USBPHY  
B7  
A7  
usb0_id  
0
0
A
VDDA3P3V_ 3.3V  
USBPHY  
Yes  
PU/ PD  
LVCMOS  
usb0_drvvbu  
s
O
L
PD  
7
VDDSHV  
1.8V/3.3V  
30  
uart3_tx_irtx  
gpio_125  
hecc1_ txd  
uart3_rx_irrx  
gpio_130  
hecc1_ rxd  
uart3_rts_sd  
gpio_131  
i2c1_scl  
2
4
0
2
4
0
2
4
0
0
0
4
0
4
0
4
0
4
0
1
2
3
4
0
1
4
0
O
IO  
O
AB15  
AB16  
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
24  
24  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
I
IO  
I
O
IO  
IOD  
IOD  
IOD  
IO  
IOD  
IO  
IOD  
IO  
IOD  
IO  
IO  
I
AA17  
AB17  
Y17  
H
H
H
PU  
PU  
PU  
0
0
7
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
40  
40  
40  
PU/ PD  
PU/ PD  
PU/ PD  
Open Drain  
Open Drain  
Open Drain  
i2c1_ sda  
i2c2_scl  
gpio_168  
i2c2_sda  
Y16  
W16  
W17  
B9  
H
H
H
H
PU  
PU  
PU  
PU  
7
7
7
7
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
40  
40  
40  
40  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
Open Drain  
Open Drain  
Open Drain  
LVCMOS  
gpio_183  
i2c3_scl  
gpio_184  
i2c3_sda  
gpio_185  
hdq_sio  
sys_altclk  
i2c2_sccbe  
i2c3_sccbe  
gpio_170  
mcspi1_clk  
mmc2_dat4  
gpio_171  
O
O
IO  
IO  
IO  
IO  
IO  
K22  
K19  
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
mcspi1_  
simo  
mmc2_dat5  
gpio_172  
1
4
0
IO  
IO  
IO  
J18  
mcspi1_  
somi  
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
mmc2_dat6  
gpio_173  
1
4
0
1
4
0
IO  
IO  
IO  
IO  
IO  
O
K18  
J20  
mcspi1_cs0  
mmc2_dat7  
gpio_174  
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
mcspi1_cs1  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
45  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
IO CELL [13]  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
mmc3_cmd  
3
4
0
3
4
0
3
IO  
IO  
O
gpio_175  
J19  
J21  
mcspi1_cs2  
mmc3_clk  
gpio_176  
H
H
PU  
PU  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
O
IO  
O
mcspi1_cs3  
hsusb2_  
data2  
IO  
gpio_177  
4
IO  
IO  
mm_fsusb2_t 5  
xdat  
J22  
mcspi2_clk  
0
3
IO  
IO  
L
L
PD  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
hsusb2_  
data7  
gpio_178  
4
0
IO  
IO  
H20  
mcspi2_  
simo  
gpt9_pwm_e  
vt  
1
3
IO  
IO  
hsusb2_  
data4  
gpio_179  
4
0
IO  
IO  
H22  
mcspi2_  
somi  
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
30  
PU/ PD  
LVCMOS  
gpt10_pwm_  
evt  
1
3
IO  
IO  
hsusb2_  
data5  
gpio_180  
4
0
1
IO  
IO  
IO  
H21  
H19  
mcspi2_cs0  
H
PU  
PD  
7
7
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
LVCMOS  
LVCMOS  
gpt11_pwm_  
evt  
hsusb2_  
data6  
3
IO  
gpio_181  
4
0
1
IO  
O
mcspi2_cs1  
L
PU/ PD  
gpt8_pwm_e  
vt  
IO  
hsusb2_  
data3  
3
4
IO  
gpio_182  
IO  
IO  
mm_fsusb2_t 5  
xen_n  
A8  
sys_32k  
sys_xtalin  
sys_xtalout  
sys_clkreq  
gpio_1  
0
0
0
0
4
0
4
0
I
Z
Z
Z
L
Z
Z
Z
Z
0
0
0
0
VDDSHV  
VDDSOSC  
VDDSOSC  
VDDSHV  
1.8V/3.3V  
1.8V  
Yes  
NA  
30  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
A10  
A9  
I
O
IO  
IO  
I
1.8V  
NA  
B8  
1.8V/3.3V  
Yes  
30  
30  
AB18  
sys_nirq  
gpio_0  
H
PU  
7
VDDSHV  
1.8V/3.3V  
Yes  
PU/ PD  
LVCMOS  
IO  
I
AA18  
Y18  
sys_  
nrespwron  
Z
L
Z
0
0
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
sys_  
0
IO  
PD  
nreswarm  
gpio_30  
sys_boot0  
gpio_2  
4
0
4
0
4
0
4
IO  
I
Open Drain  
LVCMOS  
AB19  
AB20  
W18  
Z
Z
Z
Z
Z
Z
0
0
0
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
30  
30  
30  
PU/ PD  
PU/ PD  
PU/ PD  
IO  
I
sys_boot1  
gpio_3  
LVCMOS  
LVCMOS  
IO  
I
sys_boot2  
gpio_4  
IO  
46  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
LOCATION [2]  
[1]  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
RESET  
STATE [5]  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
IO CELL [13]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
AA19  
sys_boot3  
0
4
0
I
Z
Z
0
VDDSHV  
VDDSHV  
1.8V/3.3V  
Yes  
Yes  
30  
30  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
gpio_5  
IO  
I
V18  
sys_boot4  
Z
Z
0
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
mmc2_dir_da 1  
t2  
O
gpio_6  
4
0
IO  
I
Y19  
sys_boot5  
Z
Z
Z
Z
0
0
VDDSHV  
Yes  
30  
PU/ PD  
LVCMOS  
mmc2_dir_da 1  
t3  
O
gpio_7  
4
0
4
0
0
0
4
0
4
0
0
0
0
IO  
I
W19  
sys_boot6  
gpio_8  
VDDSHV  
Yes  
30  
PU/ PD  
LVCMOS  
IO  
I
AA20  
Y20  
E9  
sys_boot7  
sys_boot8  
sys_clkout1  
gpio_10  
Z
Z
H
Z
0
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
30  
30  
30  
PU/PD  
PU/PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
I
Z
0
O
IO  
O
IO  
I
PD  
0/7(1)  
E10  
sys_clkout2  
gpio_186  
jtag_ntrst  
jtag_tck  
L
PD  
7
VDDSHV  
1.8V/3.3V  
Yes  
10  
PU/ PD  
LVCMOS  
D13  
E14  
C12  
A12  
L
L
L
H
PD  
PD  
Z
0
0
0
0
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
20  
20  
20  
20  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
I
jtag_rtck  
O
IO  
jtag_tms_tms  
c
PU  
B12  
D12  
E13  
jtag_tdi  
0
0
0
4
0
4
0
I
H
L
PU  
Z
0
0
0
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
20  
20  
20  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
jtag_tdo  
jtag_emu0  
gpio_11  
jtag_emu1  
gpio_31  
etk_clk  
O
IO  
IO  
IO  
IO  
O
H
PU  
E12  
G22  
H
H
PU  
PU  
0
4
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
20  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
9, 25  
mcbsp5_ clkx 1  
IO  
O
mmc3_clk  
hsusb1_stp  
gpio_12  
2
3
4
0
2
3
4
O
IO  
O
G21  
etk_ctl  
H
PU  
4
VDDSHV  
1.8V/3.3V  
Yes  
9, 25  
PU/ PD  
LVCMOS  
mmc3_cmd  
hsusb1_clk  
gpio_13  
IO  
O
IO  
IO  
mm_fsusb1_r 5  
xdp  
G20  
etk_d0  
0
1
O
H
PU  
4
VDDSHV  
1.8V/3.3V  
Yes  
9, 25  
PU/ PD  
LVCMOS  
mcspi3_  
simo  
IO  
mmc3_dat4  
2
3
IO  
IO  
hsusb1_  
data0  
gpio_14  
4
IO  
IO  
mm_fsusb1_r 5  
xrcv  
F22  
etk_d1  
0
1
O
H
PU  
4
VDDSHV  
1.8V/3.3V  
Yes  
9, 25  
PU/ PD  
LVCMOS  
mcspi3_  
somi  
IO  
hsusb1_  
data1  
3
IO  
gpio_15  
4
IO  
IO  
mm_fsusb1_t 5  
xse0  
(1) Mux0 if sys_boot6 is pulled down (clock master).  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
47  
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AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
LOCATION [2]  
[1]  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
RESET  
STATE [5]  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
IO CELL [13]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
F20  
etk_d2  
0
1
3
O
H
PU  
4
VDDSHV  
1.8V/3.3V  
Yes  
9, 25  
PU/ PD  
LVCMOS  
mcspi3_cs0  
IO  
IO  
hsusb1_  
data2  
gpio_16  
4
IO  
IO  
mm_fsusb1_t 5  
xdat  
G19  
E19  
F21  
F19  
E21  
etk_d3  
0
1
2
3
O
L
L
L
L
L
PU  
PD  
PD  
PD  
PD  
4
4
4
4
4
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
Yes  
Yes  
Yes  
9, 25  
9, 25  
9, 25  
9, 25  
9, 25  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
mcspi3_clk  
mmc3_dat3  
IO  
IO  
IO  
hsusb1_  
data7  
gpio_17  
4
0
1
2
3
IO  
O
I
etk_d4  
mcbsp5_dr  
mmc3_dat0  
IO  
IO  
hsusb1_  
data4  
gpio_18  
4
0
1
2
3
IO  
O
etk_d5  
mcbsp5_fsx  
mmc3_dat1  
IO  
IO  
IO  
hsusb1_  
data5  
gpio_19  
4
0
1
2
3
IO  
O
etk_d6  
mcbsp5_dx  
mmc3_dat2  
IO  
IO  
IO  
hsusb1_  
data6  
gpio_20  
4
0
1
2
3
IO  
O
etk_d7  
mcspi3_cs1  
mmc3_dat7  
O
IO  
IO  
hsusb1_  
data3  
gpio_21  
4
IO  
IO  
mm_fsusb1_t 5  
xen_n  
D22  
D21  
etk_d8  
0
2
3
4
0
2
3
4
O
IO  
I
L
L
PD  
PD  
4
4
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
9, 25  
9, 25  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
mmc3_dat6  
hsusb1_dir  
gpio_22  
IO  
O
IO  
I
etk_d9  
mmc3_dat5  
hsusb1_nxt  
gpio_23  
IO  
IO  
mm_fsusb1_r 5  
xdm  
E22  
E20  
etk_d10  
0
2
3
4
0
1
3
4
O
I
L
L
PD  
PD  
4
4
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
9, 25  
9, 25  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
uart1_rx  
hsusb2_clk  
gpio_24  
O
IO  
O
IO  
O
IO  
etk_d11  
mcspi3_clk  
hsusb2_stp  
gpio_25  
48  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
LOCATION [2]  
[1]  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
RESET  
STATE [5]  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
IO CELL [13]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
mm_fsusb2_r 5  
IO  
xdp  
E18  
D20  
etk_d12  
hsusb2_dir  
gpio_26  
etk_d13  
hsusb2_nxt  
gpio_27  
0
3
4
0
3
4
O
I
L
L
PD  
PD  
4
4
VDDSHV  
VDDSHV  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
9, 25  
9, 25  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
O
I
IO  
IO  
mm_fsusb2_r 5  
xdm  
D19  
D18  
M2  
etk_d14  
0
3
O
L
L
PD  
PD  
4
4
VDDSHV  
VDDSHV  
VDDS  
1.8V/3.3V  
1.8V/3.3V  
Yes  
Yes  
9, 25  
PU/ PD  
LVCMOS  
LVCMOS  
hsusb2_  
data0  
IO  
gpio_28  
4
IO  
IO  
mm_fsusb2_r 5  
xrcv  
etk_d15  
0
3
O
9, 25  
PU/ PD  
hsusb2_  
data1  
IO  
gpio_29  
4
IO  
IO  
mm_fsusb2_t 5  
xse0  
ddr_padref  
0
0
A
1.8V  
1.2V  
J8, J10,  
VDD_CORE  
PWR  
J12, J14,  
J16, K9,  
K11, K13,  
K15, L8,  
L10, L12,  
L14, M7,  
M9, M11,  
M13, M15,  
N8, N10,  
N12, N14,  
P7, P9,  
P11, P13,  
P15, R8,  
R10, R12,  
R14  
L17  
VDDS_SRA  
M_MPU  
0
0
PWR  
PWR  
1.8V  
1.8V  
J6  
VDDS_SRA  
M_CORE_B  
G
M17  
K6  
CAP_VDD_S  
RAM_MPU  
0
0
0
PWR  
PWR  
PWR  
1.2V  
1.2V  
1.8V  
CAP_VDD_S  
RAM_CORE  
K17  
VDDS_DPLL  
_MPU_USBH  
OST  
F11  
F7  
VDDS_DPLL  
_PER_CORE  
0
0
0
0
PWR  
PWR  
PWR  
PWR  
1.8V  
3.3V  
1.8V  
1.2V  
VDDA3P3V_  
USBPHY  
D7  
E7  
VDDA1P8V_  
USBPHY  
CAP_VDDA1  
P2LDO_USB  
PHY  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
49  
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AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
IO CELL [13]  
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)  
BALL  
PIN NAME  
MODE [3]  
TYPE [4]  
BALL  
BALL  
RESET REL. POWER [8] VOLTAGE  
HYS [10]  
LOAD (pF)  
[11]  
PULL U/D  
TYPE [12]  
LOCATION [2]  
[1]  
RESET  
STATE [5]  
RESET REL. MODE [7]  
STATE [6]  
[9]  
A21, B1,  
E15, E17,  
F12, F14,  
F18, G10,  
G12, G13,  
G8, G17,  
H18, J17,  
L22, N16,  
P17, R16,  
R18, T9,  
T11, T13,  
T17, U8,  
U10, U12,  
U14, U16,  
U18, V7,  
V8, V17,  
AA22,  
VDDSHV  
0
PWR  
1.8V/3.3V  
AB11  
F5, F16,  
G15, H5,  
K7, L6,  
VDDS  
0
PWR  
1.8V  
L16, N1,  
N5, N6, P5,  
R6, T5, T7,  
T15, U6,  
AA1  
L5  
VREFSSTL  
VDDSOSC  
VSS  
0
I
.5 * VDDS  
1.8V  
G9  
O
0
PWR  
GND  
A1, A11,  
A22, E6,  
E16, F6,  
F13, F15,  
F17, G5,  
G7, G11,  
G14, G16,  
G18, H6,  
H7, H8, H9,  
H10, H11,  
H12, H13,  
H14, H15,  
H16, H17,  
J9, J11,  
J13, J15,  
K8, K10,  
K12, K14,  
K16, L7,  
L9, L11,  
L13, L15,  
M1, M6,  
M8, M10,  
M12, M14,  
M16, M22,  
N7, N9,  
N11, N13,  
N15, N17,  
P6, P8,  
P10, P12,  
P14, P16,  
R5, R7, R9,  
R11, R13,  
R15, R17,  
T6, T8,  
T10, T12,  
T14, T16,  
T18, U5,  
U7, U9,  
U11, U13,  
U15, U17,  
V6, AB1,  
AB12,  
AB22  
B10  
VSSOSC  
NC(2)  
0
GND  
D8, D9,  
D10, E8,  
F8, F9,  
F10, J7, G6  
V15  
V16  
Reserved(3)  
Reserved(3)  
(2) "NC" indicates "No Connect". For proper device operation, these pins must be left unconnected.  
(3) For proper device operation, this pin must be pulled up via a 10k-Ω resistor.  
50  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
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AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
2.3 Multiplexing Characteristics  
Table 2-3 provides descriptions of the AM3517/05 pin multiplexing on the ZCN and ZER packages.  
Table 2-3. Multiplexing Characteristics  
ZER  
BALL NO  
E3  
ZCN  
BALL NO  
B21  
A21  
D20  
C20  
E19  
D19  
C19  
B19  
B18  
D17  
C17  
D16  
C16  
B16  
A16  
A15  
A7  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
MODE 6  
MODE 7  
sdrc_d0  
sdrc_d1  
sdrc_d2  
sdrc_d3  
sdrc_d4  
sdrc_d5  
sdrc_d6  
sdrc_d7  
sdrc_d8  
sdrc_d9  
sdrc_d10  
sdrc_d11  
sdrc_d12  
sdrc_d13  
sdrc_d14  
sdrc_d15  
sdrc_d16  
sdrc_d17  
sdrc_d18  
sdrc_d19  
sdrc_d20  
sdrc_d21  
sdrc_d22  
sdrc_d23  
sdrc_d24  
sdrc_d25  
sdrc_d26  
sdrc_d27  
sdrc_d28  
sdrc_d29  
sdrc_d30  
sdrc_d31  
sdrc_ba0  
sdrc_ba1  
sdrc_ba2  
sdrc_a0  
sdrc_a1  
sdrc_a2  
sdrc_a3  
sdrc_a4  
sdrc_a5  
sdrc_a6  
sdrc_a7  
sdrc_a8  
sdrc_a9  
sdrc_a10  
sdrc_a11  
sdrc_a12  
sdrc_a13  
sdrc_a14  
sdrc_ncs0  
D3  
C3  
C2  
F3  
D2  
C1  
D1  
G2  
G3  
H3  
G4  
H4  
G1  
J3  
J1  
T3  
U3  
U4  
V4  
B7  
D7  
E7  
V1  
C6  
V2  
D6  
V5  
B5  
V3  
C5  
W3  
W4  
Y3  
B4  
A3  
B3  
Y4  
C3  
AA2  
AA3  
AA4  
AB2  
L4  
C2  
D2  
B1  
C1  
A12  
C13  
D13  
A11  
B11  
C11  
D11  
E11  
A10  
B10  
C10  
D10  
E10  
A9  
K5  
J5  
M3  
M4  
M5  
N3  
N2  
N4  
P3  
P2  
P1  
P4  
R1  
R2  
R3  
R4  
T2  
B9  
A8  
B8  
D8  
J4  
E13  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
51  
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AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
Table 2-3. Multiplexing Characteristics (continued)  
ZER  
K4  
ZCN  
A14  
A13  
B13  
D14  
C14  
E14  
B14  
C21  
B15  
E8  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
MODE 6  
MODE 7  
sdrc_ncs1  
sdrc_clk  
L1  
L2  
sdrc_nclk  
K3  
sdrc_cke0  
sdrc_nras  
sdrc_ncas  
sdrc_nwe  
sdrc_dm0  
sdrc_dm1  
sdrc_dm2  
sdrc_dm3  
sdrc_dqs0p  
sdrc_dqs1p  
sdrc_dqs2p  
sdrc_dqs3p  
sdrc_dqs0n  
sdrc_dqs1n  
sdrc_dqs2n  
sdrc_dqs3n  
sdrc_odt  
sdrc_cke0_safe  
K1  
L3  
K2  
F4  
J2  
T4  
AB3  
E2  
D1  
B20  
B17  
A6  
H2  
U1  
Y1  
A2  
E1  
A20  
A17  
B6  
H1  
U2  
Y2  
B2  
T1  
C8  
A19  
A18  
A5  
F2  
sdrc_strben0  
sdrc_strben_dly0  
sdrc_strben1  
sdrc_strben_dly1  
gpmc_a1  
F1  
W1  
W2  
W5  
Y5  
A4  
E3  
gpio_34  
gpio_35  
gpio_36  
gpio_37  
gpio_38  
gpio_39  
gpio_40  
gpio_41  
gpio_42  
gpio_43  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
E2  
gpmc_a2  
AB4  
AA5  
AB5  
AB6  
AA6  
W6  
AB7  
Y6  
E1  
gpmc_a3  
F7  
gpmc_a4  
F6  
gpmc_a5  
F4  
gpmc_a6  
F3  
gpmc_a7  
F2  
gpmc_a8  
F1  
gpmc_a9  
sys_ndmareq2  
sys_ndmareq3  
G6  
G5  
G4  
G3  
G2  
G1  
H2  
H1  
J5  
gpmc_a10  
gpmc_d0  
AA7  
Y7  
gpmc_d1  
W7  
AA9  
Y8  
gpmc_d2  
gpmc_d3  
gpmc_d4  
AA8  
AB8  
W8  
W10  
AB9  
AB10  
W9  
AA10  
Y9  
gpmc_d5  
gpmc_d6  
gpmc_d7  
J4  
gpmc_d8  
gpio_44  
gpio_45  
gpio_46  
gpio_47  
gpio_48  
gpio_49  
gpio_50  
gpio_51  
J3  
gpmc_d9  
J2  
gpmc_d10  
gpmc_d11  
gpmc_d12  
gpmc_d13  
gpmc_d14  
gpmc_d15  
gpmc_ncs0  
gpmc_ncs1  
gpmc_ncs2  
gpmc_ncs3  
gpmc_ncs4  
gpmc_ncs5  
J1  
K4  
K3  
V10  
V9  
K2  
K1  
Y10  
Y11  
Y12  
V12  
AA11  
W12  
L2  
L1  
gpio_52  
gpio_53  
gpio_54  
gpio_55  
M4  
M3  
M2  
M1  
gpt9_pwm_evt  
gpt10_pwm_evt  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
sys_ndmareq0  
sys_ndmareq1  
sys_ndmareq2  
gpt9_pwm_evt  
gpt10_pwm_evt gpio_56  
52  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM3517 AM3505  
AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-3. Multiplexing Characteristics (continued)  
ZER  
AA12  
V11  
AB13  
AA14  
AB14  
AA15  
W11  
Y15  
W14  
V13  
AA16  
Y14  
V14  
B22  
B21  
B20  
B19  
A20  
A19  
A18  
B18  
A17  
C18  
D17  
B16  
B17  
C17  
C16  
D16  
D14  
A16  
D15  
B15  
A15  
A14  
C13  
C15  
A13  
B13  
C14  
B14  
NA  
ZCN  
N5  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
MODE 6  
MODE 7  
gpmc_ncs6  
gpmc_ncs7  
gpmc_clk  
sys_ndmareq3  
gpmc_io_dir  
gpt11_pwm_evt gpio_57  
safe_mode  
safe_mode  
N4  
gpt8_pwm_evt  
gpio_58  
gpio_59  
N1  
R1  
gpmc_nadv_ale  
gpmc_noe  
gpmc_nwe  
gpmc_nbe0_cle  
gpmc_nbe1  
gpmc_nwp  
gpmc_wait0  
gpmc_wait1  
gpmc_wait2  
gpmc_wait3  
dss_pclk  
R2  
R3  
R4  
gpio_60  
gpio_61  
gpio_62  
T1  
safe_mode  
T2  
T3  
T4  
uart4_tx  
gpio_63  
gpio_64  
gpio_65  
gpio_66  
gpio_67  
gpio_68  
gpio_69  
gpio_70  
gpio_71  
gpio_72  
gpio_73  
gpio_74  
gpio_75  
gpio_76  
gpio_77  
gpio_78  
gpio_79  
gpio_80  
gpio_81  
gpio_82  
gpio_83  
gpio_84  
gpio_85  
gpio_86  
gpio_87  
gpio_88  
gpio_89  
gpio_90  
gpio_91  
gpio_92  
gpio_93  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
T5  
uart4_rx  
U1  
sys_ndmareq1  
uart3_cts_rctx  
AE23  
AD22  
AD23  
AE24  
AD24  
AD25  
AC23  
AC24  
AC25  
AB24  
AB25  
AA23  
AA24  
AA25  
Y22  
Y23  
Y24  
Y25  
W21  
W22  
W23  
W24  
W25  
V24  
V25  
U21  
U22  
U23  
K20  
K21  
H23  
H24  
H20  
AD2  
AD1  
AE2  
AD3  
AE3  
AD4  
AE4  
AC5  
AD5  
AE5  
hw_dbg12  
hw_dbg13  
dss_hsync  
dss_vsync  
dss_acbias  
dss_data0  
dss_data1  
dss_data2  
dss_data3  
dss_data4  
dss_data5  
dss_data6  
dss_data7  
dss_data8  
dss_data9  
dss_data10  
dss_data11  
dss_data12  
dss_data13  
dss_data14  
dss_data15  
dss_data16  
dss_data17  
dss_data18  
dss_data19  
dss_data20  
dss_data21  
dss_data22  
dss_data23  
tv_vfb1  
uart1_cts  
uart1_rts  
uart3_rx_irrx  
uart3_tx_irtx  
uart1_tx  
hw_dbg14  
hw_dbg15  
hw_dbg16  
hw_dbg17  
uart1_rx  
mcspi3_clk  
mcspi3_simo  
mcspi3_somi  
mcspi3_cs0  
mcspi3_cs1  
dss_data4  
dss_data3  
dss_data2  
dss_data1  
dss_data0  
dss_data5  
NA  
tv_out1  
NA  
tv_vfb2  
NA  
tv_out2  
NA  
tv_vref  
AB21  
AA21  
Y21  
Y22  
W21  
W22  
W20  
V21  
V19  
V22  
ccdc_pclk  
ccdc_field  
ccdc_hd  
gpio_94  
gpio_95  
gpio_96  
gpio_97  
gpio_98  
gpio_99  
gpio_100  
gpio_101  
gpio_102  
gpio_103  
hw_dbg0  
hw_dbg1  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
ccdc_data8  
ccdc_data9  
uart4_tx  
uart4_rts  
uart4_cts  
uart4_rx  
i2c3_scl  
ccdc_vd  
hw_dbg2  
hw_dbg3  
ccdc_wen  
ccdc_data0  
ccdc_data1  
ccdc_data2  
ccdc_data3  
ccdc_data4  
i2c3_sda  
hw_dbg4  
hw_dbg5  
hw_dbg6  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
53  
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AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
Table 2-3. Multiplexing Characteristics (continued)  
ZER  
U20  
V20  
U19  
U21  
U22  
T19  
T20  
T21  
R22  
T22  
R20  
R19  
R21  
E5  
ZCN  
Y6  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
gpio_104  
gpio_105  
gpio_106  
gpio_107  
gpio_108  
gpio_109  
gpio_110  
gpio_111  
gpio_167  
gpio_126  
gpio_112  
gpio_113  
gpio_114  
gpio_116  
gpio_117  
gpio_118  
gpio_119  
gpio_120  
gpio_121  
gpio_122  
gpio_123  
gpio_124  
gpio_125  
gpio_126  
gpio_127  
gpio_128  
gpio_129  
gpio_130  
gpio_131  
gpio_132  
gpio_133  
gpio_134  
gpio_135  
gpio_136  
gpio_137  
gpio_138  
gpio_139  
gpio_140  
gpio_141  
gpio_142  
gpio_143  
gpio_144  
gpio_145  
gpio_146  
gpio_147  
gpio_148  
gpio_149  
gpio_150  
gpio_151  
gpio_152  
MODE 5  
MODE 6  
MODE 7  
ccdc_data5  
ccdc_data6  
ccdc_data7  
rmii_mdio_data  
rmii_mdio_clk  
rmii_rxd0  
hw_dbg7  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
AB6  
AC6  
AE6  
AD6  
Y7  
ccdc_data8  
ccdc_data9  
ccdc_data10  
ccdc_data11  
ccdc_data12  
ccdc_data13  
ccdc_data14  
ccdc_data15  
hw_dbg8  
hw_dbg9  
AA7  
AB7  
AC7  
AD7  
AE7  
AD8  
AE8  
D25  
rmii_rxd1  
rmii_crs_dv  
rmii_rxer  
hw_dbg10  
hw_dbg11  
rmii_txd0  
rmii_txd1  
rmii_txen  
rmii_50mhz_clk  
mcbsp2_fsx  
mcbsp2_clkx  
mcbsp2_dr  
mcbsp2_dx  
mmc1_clk  
mmc1_cmd  
mmc1_dat0  
mmc1_dat1  
mmc1_dat2  
mmc1_dat3  
mmc1_dat4  
mmc1_dat5  
mmc1_dat6  
mmc1_dat7  
mmc2_clk  
mmc2_cmd  
mmc2_dat0  
mmc2_dat1  
mmc2_dat2  
mmc2_dat3  
mmc2_dat4  
mmc2_dat5  
mmc2_dat6  
mmc2_dat7  
mcbsp3_dx  
mcbsp3_dr  
mcbsp3_clkx  
mcbsp3_fsx  
uart2_cts  
D5  
C25  
C5  
B25  
E4  
D24  
P22  
N21  
P21  
N20  
P19  
P20  
N22  
N19  
N18  
P18  
M21  
M20  
K20  
L19  
M18  
K21  
L18  
L20  
L21  
M19  
C4  
AA9  
AB9  
AC9  
AD9  
AE9  
AA10  
AB10  
AC10  
AD10  
AE10  
AD11  
AE11  
AB12  
AC12  
AD12  
AE12  
AB13  
AC13  
AD13  
AE13  
B24  
mcspi2_clk  
mcspi2_simo  
mcspi2_somi  
mcspi2_cs0  
mcspi3_clk  
uart4_cts  
uart4_rts  
uart4_tx  
uart4_rx  
mcspi3_simo  
mcspi3_somi  
mcspi3_cs1  
mcspi3_cs0  
mmc2_dir_dat0  
mmc2_dir_dat1  
mmc2_dir_cmd  
mmc2_clkin  
uart2_cts  
mmc3_dat0  
mmc3_dat1  
mmc3_dat2  
mmc3_dat3  
mm_fsusb3_rxdp safe_mode  
safe_mode  
mm_fsusb3_rxdm safe_mode  
safe_mode  
B4  
C24  
uart2_rts  
safe_mode  
D4  
A24  
uart2_tx  
safe_mode  
A4  
C23  
uart2_rx  
safe_mode  
A5  
F20  
mcbsp3_dx  
mcbsp3_dr  
mcbsp3_clkx  
mcbsp3_fsx  
gpt9_pwm_evt  
gpt10_pwm_evt  
gpt11_pwm_evt  
gpt8_pwm_evt  
safe_mode  
B5  
F19  
uart2_rts  
safe_mode  
D6  
E24  
uart2_tx  
safe_mode  
C6  
E23  
uart2_rx  
safe_mode  
C22  
C21  
C19  
C20  
A3  
AA19  
Y19  
uart1_tx  
safe_mode  
uart1_rts  
safe_mode  
Y20  
uart1_cts  
safe_mode  
W20  
B23  
uart1_rx  
mcbsp1_clkr  
mcspi4_clk  
safe_mode  
mcbsp4_clkx  
mm_fsusb3_txse safe_mode  
0
B3  
A2  
B2  
A23  
B22  
A22  
mcbsp4_dr  
mcbsp4_dx  
mcbsp4_fsx  
gpio_153  
gpio_154  
gpio_155  
mm_fsusb3_rxrcv safe_mode  
mm_fsusb3_txdat safe_mode  
mm_fsusb3_txen safe_mode  
_n  
B11  
D11  
R25  
P21  
mcbsp1_clkr  
mcbsp1_fsr  
mcspi4_clk  
gpio_156  
gpio_157  
safe_mode  
safe_mode  
54  
Terminal Description  
Copyright © 2009–2012, Texas Instruments Incorporated  
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AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-3. Multiplexing Characteristics (continued)  
ZER  
C10  
C9  
ZCN  
P22  
P23  
P25  
P24  
N24  
N2  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
gpio_158  
gpio_159  
gpio_160  
gpio_161  
gpio_162  
gpio_163  
gpio_164  
gpio_165  
gpio_166  
MODE 5  
MODE 6  
MODE 7  
mcbsp1_dx  
mcbsp1_dr  
mcbsp_clks  
mcbsp1_fsx  
mcbsp1_clkx  
uart3_cts_rctx  
uart3_rts_sd  
uart3_rx_irrx  
uart3_tx_irtx  
usb0_dp(1)  
usb0_dm(1)  
usb0_vbus  
usb0_id  
mcspi4_simo  
mcspi4_somi  
mcbsp3_dx  
mcbsp3_dr  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
E11  
C11  
C8  
uart1_cts  
mcspi4_cs0  
mcbsp3_fsx  
mcbsp3_clkx  
W15  
W13  
AA13  
Y13  
A6  
N3  
P1  
P2  
F25  
F24  
G24  
G25  
E25  
V2  
uart3_tx_irtx  
uart3_rx_irrx  
B6  
C7  
B7  
A7  
usb0_drvvbus  
hecc1_txd  
hecc1_rxd  
i2c1_scl  
uart3_tx_irtx  
uart3_rx_irrx  
uart3_rts_sd  
gpio_125  
gpio_130  
gpio_131  
safe_mode  
safe_mode  
safe_mode  
AB15  
AB16  
AA17  
AB17  
Y17  
Y16  
W16  
W17  
B9  
V3  
V4  
V5  
i2c1_sda  
W1  
i2c2_scl  
gpio_168  
gpio_183  
gpio_184  
gpio_185  
gpio_170  
gpio_171  
gpio_172  
gpio_173  
gpio_174  
gpio_175  
gpio_176  
gpio_177  
gpio_178  
gpio_179  
gpio_180  
gpio_181  
gpio_182  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
safe_mode  
W2  
i2c2_sda  
W4  
i2c3_scl  
W5  
i2c3_sda  
L25  
hdq_sio  
sys_altclk  
i2c2_sccbe  
i2c3_sccbe  
K22  
K19  
J18  
AE14  
AD15  
AC15  
AB15  
AD14  
AE15  
AE16  
AD16  
AC16  
AB16  
AA16  
AE17  
mcspi1_clk  
mcspi1_simo  
mcspi1_somi  
mcspi1_cs0  
mcspi1_cs1  
mcspi1_cs2  
mcspi1_cs3  
mcspi2_clk  
mcspi2_simo  
mcspi2_somi  
mcspi2_cs0  
mcspi2_cs1  
mmc2_dat4  
mmc2_dat5  
mmc2_dat6  
mmc2_dat7  
K18  
J20  
mmc3_cmd  
J19  
mmc3_clk  
J21  
hsusb2_data2  
hsusb2_data7  
hsusb2_data4  
hsusb2_data5  
hsusb2_data6  
hsusb2_data3  
mm_fsusb2_txdat  
J22  
H20  
H22  
H21  
H19  
gpt9_pwm_evt  
gpt10_pwm_evt  
gpt11_pwm_evt  
gpt8_pwm_evt  
mm_fsusb2_txen  
_n  
AB18  
E10  
G22  
G21  
G20  
F22  
Y1  
sys_nirq  
sys_clkout2  
etk_clk  
gpio_0  
safe_mode  
safe_mode  
hw_dbg0  
hw_dbg1  
hw_dbg2  
hw_dbg3  
M25  
gpio_186  
gpio_12  
gpio_13  
gpio_14  
gpio_15  
AD17  
AE18  
AD18  
AC18  
mcbsp5_clkx  
mmc3_clk  
hsusb1_stp  
etk_ctl  
mmc3_cmd  
mmc3_dat4  
hsusb1_clk  
mm_fsusb1_rxdp  
mm_fsusb1_rxrcv  
etk_d0  
mcspi3_simo  
mcspi3_somi  
hsusb1_data0  
hsusb1_data1  
etk_d1  
mm_fsusb1_txse  
0
F20  
G19  
E19  
F21  
F19  
E21  
AB18  
AA18  
Y18  
etk_d2  
etk_d3  
etk_d4  
etk_d5  
etk_d6  
etk_d7  
mcspi3_cs0  
mcspi3_clk  
mcbsp5_dr  
mcbsp5_fsx  
mcbsp5_dx  
mcspi3_cs1  
hsusb1_data2  
hsusb1_data7  
hsusb1_data4  
hsusb1_data5  
hsusb1_data6  
hsusb1_data3  
gpio_16  
gpio_17  
gpio_18  
gpio_19  
gpio_20  
gpio_21  
mm_fsusb1_txdat  
hw_dbg4  
hw_dbg5  
hw_dbg6  
hw_dbg7  
hw_dbg8  
hw_dbg9  
mmc3_dat3  
mmc3_dat0  
mmc3_dat1  
mmc3_dat2  
mmc3_dat7  
AE19  
AD19  
AB19  
mm_fsusb1_txen  
_n  
D22  
D21  
E22  
E20  
E18  
D20  
AE20  
AD20  
AC20  
AB20  
AE21  
AD21  
etk_d8  
mmc3_dat6  
mmc3_dat5  
uart1_rx  
hsusb1_dir  
hsusb1_nxt  
hsusb2_clk  
hsusb2_stp  
hsusb2_dir  
hsusb2_nxt  
gpio_22  
gpio_23  
gpio_24  
gpio_25  
gpio_26  
gpio_27  
hw_dbg10  
hw_dbg11  
hw_dbg12  
hw_dbg13  
hw_dbg14  
hw_dbg15  
etk_d9  
mm_fsusb1_rxdm  
mm_fsusb2_rxdp  
mm_fsusb2_rxdm  
etk_d10  
etk_d11  
etk_d12  
etk_d13  
mcspi3_clk  
(1) This mux selection is controlled by CONTROL_DEVCONF2 register.  
Copyright © 2009–2012, Texas Instruments Incorporated  
Terminal Description  
55  
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www.ti.com  
Table 2-3. Multiplexing Characteristics (continued)  
ZER  
D19  
D18  
ZCN  
MODE 0  
etk_d14  
etk_d15  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
gpio_28  
gpio_29  
MODE 5  
MODE 6  
MODE 7  
AC21  
AE22  
hsusb2_data0  
hsusb2_data1  
mm_fsusb2_rxrcv  
hw_dbg16  
hw_dbg17  
mm_fsusb2_txse  
0
A8  
K24  
K25  
H25  
M24  
Y2  
sys_32k  
A10  
A9  
sys_xtalin  
sys_xtalout  
sys_clkreq  
sys_nrespwron  
sys_nreswarm  
sys_boot0  
sys_boot1  
sys_boot2  
sys_boot3  
sys_boot4  
sys_boot5  
sys_boot6  
sys_boot7  
sys_boot8  
sys_clkout1  
jtag_ntrst  
B8  
gpio_1  
AA18  
Y18  
AB19  
AB20  
W18  
AA19  
V18  
Y19  
W19  
AA20  
Y20  
E9  
Y3  
gpio_30  
gpio_2  
gpio_3  
gpio_4  
gpio_5  
gpio_6  
gpio_7  
gpio_8  
Y4  
AA1  
AA2  
AA3  
AB1  
AB2  
AC1  
AC2  
AC3  
N25  
U24  
U25  
T21  
T22  
T23  
T24  
T25  
R24  
B12  
mmc2_dir_dat2  
mmc2_dir_dat3  
gpio_10  
safe_mode  
D13  
E14  
C12  
A12  
B12  
D12  
E13  
E12  
M2  
jtag_tck  
jtag_rtck  
jtag_tms_tmsc  
jtag_tdi  
jtag_tdo  
jtag_emu0  
jtag_emu1  
ddr_padref  
gpio_11  
gpio_31  
56  
Terminal Description  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
2.4 Signal Description  
Many signals are available on multiple pins according to the software configuration of the pin multiplexing  
options.  
1. SIGNAL NAME: The signal name  
2. DESCRIPTION: Description of the signal  
3. TYPE: Type = Ball type for this specific function:  
–
–
–
–
–
–
I = Input  
O = Output  
Z = High-impedance  
D = Open Drain  
DS = Differential  
A = Analog  
4. BALL: Associated ball location  
5. SUBSYSTEM PIN MULTIPLEXING: Contains a list of the pin multiplexing options at the  
module/subsystem level. The pin function is selected at the module/system level.  
Note: The Subsystem Multiplexing Signals are not described in Table 2-1 through Table 2-2.  
2.4.1 External Memory Interfaces  
Table 2-4. External Memory Interfaces - GPMC Signals Description  
SIGNAL NAME[1]  
DESCRIPTION[2]  
TYPE[3]  
ZCN BALL[4]  
ZER BALL[4]  
SUBSYSTEM PIN  
MULTIPLEXING [5]  
gpmc_a1  
gpmc_a2  
gpmc_a3  
gpmc_a4  
gpmc_a5  
gpmc_a6  
gpmc_a7  
gpmc_a8  
gpmc_a9  
gpmc_a10  
gpmc_a11  
GPMC Address bit 1  
GPMC Address bit 2  
GPMC Address bit 3  
GPMC Address bit 4  
GPMC Address bit 5  
GPMC Address bit 6  
GPMC Address bit 7  
GPMC Address bit 8  
GPMC Address bit 9  
GPMC Address bit 10  
O
O
O
O
O
O
O
O
O
O
O
E3/G5  
E2/G4  
E1/G3  
F7/G2  
F6/G1  
F4/H2  
F3/H1  
F2/J5  
F1/J4  
G6/J3  
J2  
W5/AA7  
Y5/Y7  
gpmc_a17  
gpmc_a18  
gpmc_a19  
gpmc_a20  
gpmc_a21  
gpmc_a22  
gpmc_a23  
gpmc_a24  
gpmc_a25  
gpmc_a26  
AB4/W7  
AA5/AA9  
AB5/Y8  
AB6/AA8  
AA6/AB8  
W6/W8  
AB7/W10  
Y6/AB9  
AB10  
GPMC Address bit 11  
multiplexed on  
gpmc_d10  
gpmc_a12  
gpmc_a13  
gpmc_a14  
gpmc_a15  
gpmc_a16  
gpmc_a17  
GPMC Address bit12  
multiplexed on  
gpmc_d11  
O
O
O
O
O
O
J1  
W9  
AA10  
Y9  
GPMC Address bit13  
multiplexed on  
gpmc_d12  
K4  
K3  
K2  
K1  
E3  
GPMC Address bit  
14multiplexed on  
gpmc_d13  
GPMC Address bit15  
multiplexed on  
gpmc_d14  
V10  
V9  
GPMC Address bit16  
multiplexed on  
gpmc_d15  
GPMC Address bit17  
multiplexed on  
gpmc_a1  
W5  
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Terminal Description  
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Table 2-4. External Memory Interfaces - GPMC Signals Description (continued)  
SIGNAL NAME[1]  
DESCRIPTION[2]  
TYPE[3]  
ZCN BALL[4]  
ZER BALL[4]  
SUBSYSTEM PIN  
MULTIPLEXING [5]  
gpmc_a18  
GPMC Address bit18  
multiplexed on  
gpmc_a2  
O
E2  
Y5  
gpmc_a19  
gpmc_a20  
gpmc_a21  
gpmc_a22  
gpmc_a23  
gpmc_a24  
gpmc_a25  
gpmc_a26  
GPMC Address bit19  
multiplexed on  
gpmc_a3  
O
O
O
O
O
O
O
O
E1  
F7  
F6  
F4  
F3  
F2  
F1  
G6  
AB4  
AA5  
AB5  
AB6  
AA6  
W6  
GPMC Address bit20  
multiplexed on  
gpmc_a4  
GPMC Address bit21  
multiplexed on  
gpmc_a5  
GPMC Address bit22  
multiplexed on  
gpmc_a6  
GPMC Address bit23  
multiplexed on  
gpmc_a7  
GPMC Address bit24  
multiplexed on  
gpmc_a8  
GPMC Address bit25  
multiplexed on  
gpmc_a9  
AB7  
Y6  
GPMC Address bit26  
multiplexed on  
gpmc_a10  
gpmc_d0  
GPMC Data bit 0  
GPMC Data bit 1  
GPMC Data bit 2  
GPMC Data bit 3  
GPMC Data bit 4  
GPMC Data bit 5  
GPMC Data bit 6  
GPMC Data bit 7  
GPMC Data bit 8  
GPMC Data bit 9  
GPMC Data bit 10  
GPMC Data bit 11  
GPMC Data bit 12  
GPMC Data bit 13  
GPMC Data bit 14  
GPMC Data bit 15  
GPMC Chip Select 0  
GPMC Chip Select 1  
GPMC Chip Select 2  
GPMC Chip Select 3  
GPMC Chip Select 4  
GPMC Chip Select 5  
GPMC Chip Select 6  
GPMC Chip Select 7  
GPMC clock  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
G5  
G4  
G3  
G2  
G1  
H2  
H1  
J5  
AA7  
Y7  
gpmc_a1/gpmc_d0  
gpmc_a2/gpmc_d1  
gpmc_a3/gpmc_d2  
gpmc_a4/gpmc_d3  
gpmc_a5/gpmc_d4  
gpmc_a6/gpmc_d5  
gpmc_a7/gpmc_d6  
gpmc_a8/gpmc_d7  
gpmc_a9/gpmc_d8  
gpmc_a10/gpmc_d9  
gpmc_a11/gpmc_d10  
gpmc_a12/gpmc_d11  
gpmc_a13/gpmc_d12  
gpmc_a14/gpmc_d13  
gpmc_a15/gpmc_d14  
gpmc_a16/gpmc_d15  
gpmc_d1  
gpmc_d2  
W7  
gpmc_d3  
AA9  
Y8  
gpmc_d4  
gpmc_d5  
AA8  
AB8  
W8  
gpmc_d6  
gpmc_d7  
gpmc_d8  
J4  
W10  
AB9  
AB10  
W9  
gpmc_d9  
J3  
gpmc_d10  
gpmc_d11  
gpmc_d12  
gpmc_d13  
gpmc_d14  
gpmc_d15  
gpmc_ncs0  
gpmc_ncs1  
gpmc_ncs2  
gpmc_ncs3  
gpmc_ncs4  
gpmc_ncs5  
gpmc_ncs6  
gpmc_ncs7  
gpmc_clk  
J2  
J1  
K4  
K3  
K2  
K1  
L2  
AA10  
Y9  
V10  
V9  
Y10  
Y11  
Y12  
V12  
AA11  
W12  
AA12  
V11  
AB13  
O
L1  
O
M4  
M3  
M2  
M1  
N5  
N4  
N1  
O
O
O
O
O
O
58  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-4. External Memory Interfaces - GPMC Signals Description (continued)  
SIGNAL NAME[1]  
DESCRIPTION[2]  
TYPE[3]  
ZCN BALL[4]  
ZER BALL[4]  
SUBSYSTEM PIN  
MULTIPLEXING [5]  
gpmc_nadv_ale  
Address Valid or  
Address Latch  
Enable  
O
R1  
AA14  
gpmc_noe  
Output Enable  
Write Enable  
O
O
O
R2  
R3  
R4  
AB14  
AA15  
W11  
gpmc_nwe  
gpmc_nbe0_cle  
Lower Byte Enable.  
Also used for  
Command Latch  
Enable  
gpmc_nbe1  
gpmc_nwp  
gpmc_wait0  
Upper Byte Enable  
Flash Write Protect  
O
O
I
T1  
T2  
T3  
Y15  
W14  
V13  
External indication of  
wait  
gpmc_wait1  
gpmc_wait2  
gpmc_wait3  
External indication of  
wait  
I
I
I
T4  
T5  
U1  
AA16  
Y14  
External indication of  
wait  
External indication of  
wait  
V14  
Table 2-5. External Memory Interfaces - SDRC Signals Description  
SIGNAL NAME[1]  
sdrc_d0  
DESCRIPTION [2]  
SDRAM data bit 0  
SDRAM data bit 1  
SDRAM data bit2  
SDRAM data bit 3  
SDRAM data bit 4  
SDRAM data bit 5  
SDRAM data bit 6  
SDRAM data bit 7  
SDRAM data bit 8  
SDRAM data bit 9  
SDRAM data bit 10  
SDRAM data bit 11  
SDRAM data bit 12  
SDRAM data bit 13  
SDRAM data bit 14  
SDRAM data bit 15  
SDRAM data bit 16  
SDRAM data bit 17  
SDRAM data bit 18  
SDRAM data bit 19  
SDRAM data bit 20  
SDRAM data bit 21  
SDRAM data bit 22  
SDRAM data bit 23  
SDRAM data bit 24  
SDRAM data bit 25  
SDRAM data bit 26  
TYPE [3]  
IO  
ZCN BALL [4]  
B21  
A21  
D20  
C20  
E19  
D19  
C19  
B19  
B18  
D17  
C17  
D16  
C16  
B16  
A16  
A15  
A7  
ZER BALL [4]  
E3  
D3  
C3  
C2  
F3  
D2  
C1  
D1  
G2  
G3  
H3  
G4  
H4  
G1  
J3  
sdrc_d1  
IO  
sdrc_d2  
IO  
sdrc_d3  
IO  
sdrc_d4  
IO  
sdrc_d5  
IO  
sdrc_d6  
IO  
sdrc_d7  
IO  
sdrc_d8  
IO  
sdrc_d9  
IO  
sdrc_d10  
sdrc_d11  
sdrc_d12  
sdrc_d13  
sdrc_d14  
sdrc_d15  
sdrc_d16  
sdrc_d17  
sdrc_d18  
sdrc_d19  
sdrc_d20  
sdrc_d21  
sdrc_d22  
sdrc_d23  
sdrc_d24  
sdrc_d25  
sdrc_d26  
IO  
IO  
IO  
IO  
IO  
IO  
J1  
IO  
T3  
U3  
U4  
V4  
V1  
V2  
V5  
V3  
W3  
W4  
Y3  
IO  
B7  
IO  
D7  
IO  
E7  
IO  
C6  
IO  
D6  
IO  
B5  
IO  
C5  
IO  
B4  
IO  
A3  
IO  
B3  
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Table 2-5. External Memory Interfaces - SDRC Signals Description (continued)  
SIGNAL NAME[1]  
sdrc_d27  
sdrc_d28  
sdrc_d29  
sdrc_d30  
sdrc_d31  
sdrc_ba0  
sdrc_ba1  
sdrc_ba2  
sdrc_a0  
DESCRIPTION [2]  
SDRAM data bit 27  
SDRAM data bit 28  
SDRAM data bit 29  
SDRAM data bit 30  
SDRAM data bit 31  
SDRAM bank select 0  
SDRAM bank select 1  
SDRAM bank select 2  
SDRAM address bit 0  
SDRAM address bit 1  
SDRAM address bit 2  
SDRAM address bit 3  
SDRAM address bit 4  
SDRAM address bit 5  
SDRAM address bit 6  
SDRAM address bit 7  
SDRAM address bit 8  
SDRAM address bit 9  
SDRAM address bit 10  
SDRAM address bit 11  
SDRAM address bit 12  
SDRAM address bit 13  
SDRAM address bit 14  
Chip select 0  
TYPE [3]  
IO  
IO  
IO  
IO  
IO  
O
ZCN BALL [4]  
C3  
ZER BALL [4]  
Y4  
C2  
AA2  
AA3  
AA4  
AB2  
L4  
D2  
B1  
C1  
A12  
C13  
D13  
A11  
B11  
C11  
D11  
E11  
A10  
B10  
C10  
D10  
E10  
A9  
O
K5  
O
J5  
O
M3  
M4  
M5  
N3  
sdrc_a1  
O
sdrc_a2  
O
sdrc_a3  
O
sdrc_a4  
O
N2  
sdrc_a5  
O
N4  
sdrc_a6  
O
P3  
sdrc_a7  
O
P2  
sdrc_a8  
O
P1  
sdrc_a9  
O
P4  
sdrc_a10  
sdrc_a11  
sdrc_a12  
sdrc_a13  
sdrc_a14  
sdrc_ncs0  
sdrc_ncs1  
sdrc_clk  
O
R1  
O
B9  
R2  
O
A8  
R3  
O
B8  
R4  
O
D8  
T2  
O
E13  
A14  
A13  
B13  
D14  
C14  
E14  
J4  
Chip select 1  
O
K4  
Clock  
O
L1  
sdrc_nclk  
sdrc_cke0  
sdrc_nras  
sdrc_ncas  
Clock Invert  
O
L2  
Clock Enable 0  
O
K3  
SDRAM Row Access  
O
K1  
SDRAM column address  
strobe  
O
L3  
sdrc_nwe  
sdrc_dm0  
sdrc_dm1  
sdrc_dm2  
sdrc_dm3  
sdrc_strben0  
SDRAM write enable  
Data Mask 0  
O
O
O
O
O
A
B14  
C21  
B15  
E8  
K2  
F4  
J2  
Data Mask 1  
Data Mask 2  
T4  
AB3  
F2  
Data Mask 3  
D1  
PCB layout trace loop 0  
pin 0  
A19  
sdrc_strben_dly0  
sdrc_strben1  
sdrc_strben_dly1  
sdrc_odt  
PCB layout trace loop 0  
pin 1  
A
A
A
O
A18  
A5  
F1  
PCB layout trace loop 1  
pin 0  
W1  
W2  
T1  
PCB layout trace loop 1  
pin 1  
A4  
On-die termination output  
for sdrc_ncs0 only  
C8  
sdrc_dqs0p  
sdrc_dqs0n  
sdrc_dqs1p  
Data Strobe 0  
Data Strobe 0  
Data Strobe 1  
IO  
IO  
IO  
B20  
A20  
B17  
E2  
E1  
H2  
60  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-5. External Memory Interfaces - SDRC Signals Description (continued)  
SIGNAL NAME[1]  
sdrc_dqs1n  
sdrc_dqs2p  
sdrc_dqs2n  
sdrc_dqs3p  
sdrc_dqs3n  
ddr_padref  
DESCRIPTION [2]  
Data Strobe 1  
Data Strobe 2  
Data Strobe 2  
Data Strobe 3  
Data Strobe 3  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
IO  
IO  
IO  
IO  
IO  
A
A17  
A6  
H1  
U1  
U2  
Y1  
Y2  
M2  
B6  
A2  
B2  
Impedance control for  
DDR2 output. This pin  
must be connected to  
ground via a 50-ohm (±  
2%) resistor.  
B12  
VREFSSTL  
VREFSSTL is .5 * VDDS  
= 0.9V for DDR data  
PHY0 reference voltage  
input  
IO  
F14  
L5  
2.4.2 Video Interfaces  
Table 2-6. Video Interfaces - CCDC Signals Description  
SIGNAL NAME[1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
SYSTEM MUX  
MODE(1)  
mode0  
mode0  
mode0  
ccdc_pclk  
ccdc_field  
ccdc_hd  
CCDC pixel clock  
IO  
AD2  
AD1  
AE2  
AB21  
AA21  
Y21  
CCDC field ID signal IO  
CCDC horizontal  
sync  
IO  
ccdc_vd  
CCDC vertical sync  
CCDC write enable  
CCDC data bit 0  
CCDC data bit 1  
CCDC data bit 2  
CCDC data bit 3  
CCDC data bit 4  
CCDC data bit 5  
CCDC data bit 6  
CCDC data bit 7  
CCDC data bit 8  
CCDC data bit 9  
CCDC data bit 10  
CCDC data bit 11  
CCDC data bit 12  
CCDC data bit 13  
CCDC data bit 14  
CCDC data bit 15  
IO  
I
AD3  
AE3  
AD4  
AE4  
AC5  
AD5  
AE5  
Y6  
Y22  
W21  
W22  
W20  
V21  
V19  
V22  
U20  
V20  
U19  
U21  
U22  
T19  
T20  
T21  
R22  
T22  
R20  
mode0  
mode0  
mode0  
mode0  
mode0  
mode0  
mode0  
mode0  
mode0  
mode0  
mode1  
mode1  
mode1  
mode1  
mode1  
mode1  
mode1  
mode1  
ccdc_wen  
ccdc_data0  
ccdc_data1  
ccdc_data2  
ccdc_data3  
ccdc_data4  
ccdc_data5  
ccdc_data6  
ccdc_data7  
ccdc_data8  
ccdc_data9  
ccdc_data10  
ccdc_data11  
ccdc_data12  
ccdc_data13  
ccdc_data14  
ccdc_data15  
I
I
I
I
I
I
I
AB6  
AC6  
AE6  
AD6  
Y7  
I
I
I
I
I
AA7  
AB7  
AC7  
AD7  
AE7  
I
I
I
I
(1) See Multiplexing Characteristics table for more information.  
Table 2-7. Video Interfaces - DSS Signals Description  
SIGNAL NAME[1]  
dss_pclk  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
AE23  
ZER BALL [4]  
LCD Pixel Clock  
O
O
B22  
B21  
dss_hsync  
LCD Horizontal  
Synchronization  
AD22  
dss_vsync  
LCD Vertical  
O
AD23  
B20  
Synchronization  
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Table 2-7. Video Interfaces - DSS Signals Description (continued)  
SIGNAL NAME[1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
dss_acbias  
AC bias control (STN) or  
pixel data enable (TFT)  
output  
O
AE24  
B19  
dss_data0  
dss_data1  
dss_data2  
dss_data3  
dss_data4  
dss_data5  
dss_data6  
dss_data7  
dss_data8  
dss_data9  
dss_data10  
dss_data11  
dss_data12  
dss_data13  
dss_data14  
dss_data15  
dss_data16  
dss_data17  
dss_data18  
dss_data19  
dss_data20  
dss_data21  
dss_data22  
dss_data23  
LCD Pixel Data bit 0  
LCD Pixel Data bit 1  
LCD Pixel Data bit 2  
LCD Pixel Data bit 3  
LCD Pixel Data bit 4  
LCD Pixel Data bit 5  
LCD Pixel Data bit 6  
LCD Pixel Data bit 7  
LCD Pixel Data bit 8  
LCD Pixel Data bit 9  
LCD Pixel Data bit 10  
LCD Pixel Data bit 11  
LCD Pixel Data bit 12  
LCD Pixel Data bit 13  
LCD Pixel Data bit 14  
LCD Pixel Data bit 15  
LCD Pixel Data bit 16  
LCD Pixel Data bit 17  
LCD Pixel Data bit 18  
LCD Pixel Data bit 19  
LCD Pixel Data bit 20  
LCD Pixel Data bit 21  
LCD Pixel Data bit 22  
LCD Pixel Data bit 23  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
AD24  
AD25  
AC23  
AC24  
AC25  
AB24  
AB25  
AA23  
AA24  
AA25  
Y22  
A20  
A19  
A18  
B18  
A17  
C18  
D17  
B16  
B17  
C17  
C16  
D16  
D14  
A16  
D15  
B15  
A15  
A14  
C13  
C15  
A13  
B13  
C14  
B14  
Y23  
Y24  
Y25  
W21  
W22  
W23  
W24  
W25  
V24  
V25  
O
U21  
O
U22  
O
U23  
Table 2-8. Video Interfaces – RFBI Signals Description  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
SUBSYSTEM PIN  
MULTIPLEXING [5]  
rfbi_a0  
RFBI command/data  
control  
O
AE24  
B19  
dss_acbias  
rfbi_cs0  
rfbi_da0  
rfbi_da1  
rfbi_da2  
rfbi_da3  
rfbi_da4  
rfbi_da5  
rfbi_da6  
rfbi_da7  
rfbi_da8  
rfbi_da9  
rfbi_da10  
rfbi_da11  
rfbi_da12  
rfbi_da13  
1st LCD chip select  
RFBI data bus 0  
RFBI data bus 1  
RFBI data bus 2  
RFBI data bus 3  
RFBI data bus 4  
RFBI data bus 5  
RFBI data bus 6  
RFBI data bus 7  
RFBI data bus 8  
RFBI data bus 9  
RFBI data bus 10  
RFBI data bus 11  
RFBI data bus 12  
RFBI data bus 13  
O
AD22  
AD24  
AD25  
AC23  
AC24  
AC25  
AB24  
AB25  
AA23  
AA24  
AA25  
Y22  
B21  
A20  
A19  
A18  
B18  
A17  
C18  
D17  
B16  
B17  
C17  
C16  
D16  
D14  
A16  
dss_hsync  
dss_data0  
dss_data1  
dss_data2  
dss_data3  
dss_data4  
dss_data5  
dss_data6  
dss_data7  
dss_data8  
dss_data9  
dss_data10  
dss_data11  
dss_data12  
dss_data13  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
Y23  
Y24  
Y25  
62  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-8. Video Interfaces – RFBI Signals Description (continued)  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
SUBSYSTEM PIN  
MULTIPLEXING [5]  
rfbi_da14  
rfbi_da15  
rfbi_rd  
RFBI data bus 14  
RFBI data bus 15  
Read enable for RFBI  
IO  
IO  
O
W21  
D15  
B15  
B22  
B20  
dss_data14  
dss_data15  
dss_pclk  
W22  
AE23  
AD23  
rfbi_wr  
Write Enable for  
RFBI  
O
dss_vsync  
rfbi_te_vsync0  
tearing effect removal  
and Vsync input from  
1st LCD  
I
W23  
A15  
dss_data16  
rfbi_hsync0  
Hsync for 1st LCD  
I
I
W24  
W25  
A14  
C13  
dss_data17  
dss_data18  
rfbi_te_vsync1  
tearing effect removal  
and Vsync input from  
2nd LCD  
rfbi_hsync1  
rfbi_cs1  
Hsync for 2nd LCD  
2nd LCD chip select  
I
V24  
V25  
C15  
A13  
dss_data19  
dss_data20  
O
Table 2-9. Video Interfaces – TV Signals Description  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
tv_out1  
TV analog output  
Composite: tv_out1  
O
K21  
NA  
NA  
NA  
tv_out2  
tv_vfb1  
TV analog output S-  
VIDEO: tv_out2  
O
O
H24  
K20  
tv_vfb1: Feedback  
through external resistor  
to composite  
tv_vfb2  
tv_vref  
tv_vfb2: Feedback  
through external resistor  
to S-VIDEO  
O
I
H23  
H20  
NA  
NA  
External capacitor  
2.4.3 Serial Communication Interfaces  
Table 2-10. HDQ Signals Description  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
hdq_sio  
Bidirectional HDQ 1-Wire IO  
control and data Interface.  
Output is open drain.  
L25  
B9  
Table 2-11. Serial Communication Interfaces – I2C Signals Description (I2C1)  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
i2c1_scl  
I2C Master Serial clock.  
Output is open drain.  
IOD  
V4  
AA17  
i2c1_sda  
I2C Serial Bidirectional  
Data. Output is open  
drain.  
IOD  
V5  
AB17  
Table 2-12. Serial Communication Interfaces - I2C Signals Description (I2C2)  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
i2c2_scl  
I2C Master Serial clock.  
Output is open drain.  
IOD  
W1  
Y17  
i2c2_sda  
I2C Serial Bidirectional  
Data. Output is open  
drain.  
IOD  
W2  
Y16  
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Table 2-13. Serial Communication Interfaces - I2C Signals Description (I2C3)  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
i2c3_scl  
I2C Master Serial clock.  
Output is open drain.  
IOD  
W4  
W16  
i2c3_sda  
I2C Serial Bidirectional  
Data. Output is open  
drain.  
IOD  
W5  
W17  
Table 2-14. Serial Communication Interfaces – McBSP LP Signals Description  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 1)  
mcbsp1_dr  
mcbsp1_clkr  
mcbsp1_fsr  
Received serial data  
Receive Clock  
I
P23  
R25  
P21  
C9  
IO  
IO  
B11  
D11  
Receive frame  
synchronization  
mcbsp1_dx  
mcbsp1_clkx  
mcbsp1_fsx  
Transmitted serial data  
Transmit clock  
IO  
IO  
IO  
P22  
N24  
P24  
C10  
C8  
Transmit frame  
synchronization  
C11  
mcbsp_clks  
External clock input  
(shared by McBSP1, 2, 3,  
4, and 5)  
I
P25  
E11  
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 2)  
mcbsp2_dr  
mcbsp2_dx  
mcbsp2_clkx  
mcbsp2_fsx  
Received serial data  
Transmitted serial data  
Combined serial clock  
I
B25  
D24  
C25  
D25  
C5  
E4  
D5  
E5  
IO  
IO  
IO  
Combined frame  
synchronization  
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 3)  
mcbsp3_dr  
mcbsp3_dx  
mcbsp3_clkx  
mcbsp3_fsx  
Received serial data  
Transmitted serial data  
Combined serial clock  
I
C24  
B24  
A24  
C23  
B4  
C4  
D4  
A4  
IO  
IO  
IO  
Combined frame  
synchronization  
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 4)  
mcbsp4_dr  
mcbsp4_dx  
mcbsp4_clkx  
mcbsp4_fsx  
Received serial data  
Transmitted serial data  
Combined serial clock  
I
A23  
B22  
B23  
A22  
B3  
A2  
A3  
B2  
IO  
IO  
IO  
Combined frame  
synchronization  
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 5)  
mcbsp5_dr  
mcbsp5_dx  
mcbsp5_clkx  
mcbsp5_fsx  
Received serial data  
Transmitted serial data  
Combined serial clock  
I
Y18  
E19  
F19  
G22  
F21  
IO  
IO  
IO  
AD19  
AD17  
AE19  
Combined frame  
synchronization  
Table 2-15. Serial Communication Interfaces – McSPI Signals Description  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
MULTICHANNEL SERIAL PORT INTERFACE (McSPI1)  
mcspi1_clk  
SPI Clock  
IO  
AE14  
K22  
64  
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Table 2-15. Serial Communication Interfaces – McSPI Signals Description (continued)  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
mcspi1_simo  
Slave data in, master data IO  
out  
AD15  
K19  
mcspi1_somi  
mcspi1_cs0  
mcspi1_cs1  
mcspi1_cs2  
mcspi1_cs3  
Slave data out, master  
data in  
IO  
IO  
O
AC15  
AB15  
AD14  
AE15  
AE16  
J18  
K18  
J20  
J19  
J21  
SPI Enable 0, polarity  
configured by software  
SPI Enable 1, polarity  
configured by software  
SPI Enable 2, polarity  
configured by software  
O
SPI Enable 3, polarity  
configured by software  
O
MULTICHANNEL SERIAL PORT INTERFACE (McSPI2)  
mcspi2_clk  
SPI Clock  
IO  
AD16,AC9  
AC16,AD9  
J22  
mcspi2_simo  
Slave data in, master data IO  
out  
H20  
mcspi2_somi  
mcspi2_cs0  
mcspi2_cs1  
Slave data out, master  
data in  
IO  
IO  
O
AB16,AE9  
AA16,AA10  
AE17  
H22  
H21  
H19  
SPI Enable 0, polarity  
configured by software  
SPI Enable 1, polarity  
configured by software  
MULTICHANNEL SERIAL PORT INTERFACE (McSPI3)  
mcspi3_clk  
SPI Clock  
IO  
W25,AD11,AA18  
V24,AE11,AD18  
C13, M21, G19, E20  
C15, M20, G20  
mcspi3_simo  
Slave data in, master data IO  
out  
mcspi3_somi  
mcspi3_cs0  
mcspi3_cs1  
Slave data out, master  
data in  
IO  
IO  
O
V25, AB12, AC18  
U21,AE12,AB18  
U22, AD12, AB19  
A13, K20, F22  
B13, K21, F20  
C14, M18, E21  
SPI Enable 0, polarity  
configured by software  
SPI Enable 1, polarity  
configured by software  
MULTICHANNEL SERIAL PORT INTERFACE (McSPI4)  
mcspi4_clk  
SPI Clock  
IO  
W20, R25  
P22  
C20, B11  
C10  
mcspi4_simo  
Slave data in, master data IO  
out  
mcspi4_somi  
mcspi4_cs0  
Slave data out, master  
data in  
IO  
P23  
P24  
C9  
SPI Enable 0, polarity  
configured by software  
IO  
C11  
Table 2-16. Serial Communication Interfaces – HECC Signals Description  
SIGNAL NAME [1]  
hecc1_txd  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
AB15  
Transmit serial data pin  
Receive serial data pin  
O
I
V2  
V3  
hecc1_rxd  
AB16  
Table 2-17. Serial Communication Interfaces – EMAC (RMII) Signals Description  
SIGNAL NAME [1]  
rmii_mdio_data  
rmii_mdio_clk  
rmii_rxd0  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
Management data I/O  
Management data clock  
EMAC receive data pin 0  
EMAC receive data pin 1  
IO  
O
I
AE6  
AD6  
Y7  
U21  
U22  
T19  
T20  
rmii_rxd1  
I
AA7  
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Table 2-17. Serial Communication Interfaces – EMAC (RMII) Signals Description (continued)  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
rmii_crs_dv  
EMAC carrier  
I
AB7  
T21  
sense/receive data valid  
rmii_rxer  
EMAC receive error  
I
AC7  
AD7  
AE7  
AD8  
AE8  
R22  
T22  
R20  
R19  
R21  
rmii_txd0  
EMAC transmit data pin 0  
EMAC transmit data pin 1  
EMAC transmit enable  
EMAC RMII 50 MHz clock  
O
O
O
I
rmii_txd1  
rmii_txen  
rmii_50mhz_clk  
Table 2-18. Serial Communication Interfaces – UARTs Signals Description  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART1)  
uart1_cts  
uart1_rts  
uart1_rx  
uart1_tx  
UART1 Clear To Send  
UART1 Request To Send  
UART1 Receive data  
UART1 Transmit data  
I
AD24,Y20,P25  
AD25,Y19  
C19,A20,E11  
C21,A19  
O
I
AA23,W20,AC20  
AB25,AA19  
C20,B16,E22  
C22,D17  
O
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2)  
uart2_cts  
uart2_rts  
uart2_rx  
uart2_tx  
UART2 Clear To Send  
UART2 Request To Send  
UART2 Receive data  
UART2 Transmit data  
I
B24,F20  
C24,F19  
C23,E23  
A24,E24  
A5,C4  
B5,B4  
C6,A4  
D6,D4  
O
I
O
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART3) / IrDA  
uart3_cts_rctx  
UART3 Clear To Send  
(input), Remote TX  
(output)  
IO  
U1,N2  
W15,V14  
uart3_rts_sd  
uart3_rx_irrx  
uart3_tx_irtx  
UART3 Request To  
Send , IR enable  
O
I
N3,V3  
W13AB16  
UART3 Receive data , IR  
and Remote RX  
AC25,P1,F25,V2  
AB24,P2,F24,E25  
AA13,A17,A6,AB15  
Y13,C18,B6,A7  
UART3 Transmit data , IR  
TX  
O
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART4)  
uart4_cts  
uart4_rts  
uart4_rx  
uart4_tx  
UART4 Clear To Send  
UART4 Request To Send  
UART4 Receive data  
UART4 Transmit data  
I
AD3,AD11  
Y22,M21  
O
I
AE2,AE11  
Y21,M20  
T5,AE3,AC12  
T4,AD1,AB12  
Y14,W21,L19  
AA16,AA21,K20  
O
Table 2-19. Serial Communication Interfaces – USB Signals Description  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
UNIVERSAL SERIAL BUS INTERFACE (USB0)  
usb0_dp  
USB D+ (differential signal  
pair)  
A
A
O
A
F25  
F24  
E25  
G25  
A6  
B6  
A7  
B7  
usb0_dm  
usb0_drvvbus  
usb0_id  
USB D- (differential signal  
pair)  
Digital output to control  
external supply  
USB operating mode  
identification pin  
66  
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Table 2-19. Serial Communication Interfaces – USB Signals Description (continued)  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
usb0_vbus  
For host or device mode  
operation, tie the  
A
G24  
C7  
VBUS/USB power signal  
to the USB connector.  
When used in OTG mode  
operation, tie VBUS to the  
external charge pump and  
to the VBUS signal on the  
USB connector.  
MM_FSUSB3  
mm_fsusb3_rxdm  
Vminus receive data (not IO  
used in 3- or 4-pin  
configurations)  
AE13  
AC13  
A23  
M19  
L20  
B3  
mm_fsusb3_rxdp  
mm_fsusb3_rxrcv  
mm_fsusb3_txse0  
mm_fsusb3_txdat  
Vplus receive data (not  
used in 3- or 4-pin  
configurations)  
IO  
Differential receiver signal IO  
input (not used in 3-pin  
mode)  
Single-ended zero. Used  
as VM in 4-pin VP_VM  
mode.  
IO  
B23  
A3  
USB data. Used as VP in IO  
4-pin VP_VM mode.  
B22  
A22  
A2  
B2  
mm_fsusb3_txen_n  
MM_FSUSB2  
Transmit enable  
IO  
mm_fsusb2_rxdm  
Vminus receive data (not IO  
used in 3- or 4-pin  
configurations)  
AD21  
AB20  
AC21  
AE22  
D20  
E20  
D19  
D18  
mm_fsusb2_rxdp  
mm_fsusb2_rxrcv  
mm_fsusb2_txse0  
mm_fsusb2_txdat  
Vplus receive data (not  
used in 3- or 4-pin  
configurations)  
IO  
Differential receiver signal IO  
input (not used in 3-pin  
mode)  
Single-ended zero. Used  
as VM in 4-pin VP_VM  
mode.  
IO  
USB data. Used as VP in IO  
4-pin VP_VM mode.  
AE16  
AE17  
J21  
mm_fsusb2_txen_n  
MM_FSUSB1  
Transmit enable  
IO  
H19  
mm_fsusb1_rxdm  
Vminus receive data (not IO  
used in 3- or 4-pin  
configurations)  
AD20  
AE18  
AD18  
AC18  
D21  
G21  
G20  
F22  
mm_fsusb1_rxdp  
mm_fsusb1_rxrcv  
mm_fsusb1_txse0  
mm_fsusb1_txdat  
Vplus receive data (not  
used in 3- or 4-pin  
configurations)  
IO  
Differential receiver signal IO  
input (not used in 3-pin  
mode)  
Single-ended zero. Used  
as VM in 4-pin VP_VM  
mode.  
IO  
USB data. Used as VP in IO  
4-pin VP_VM mode.  
AB18  
AB19  
F20  
E21  
mm_fsusb1_txen_n  
Transmit enable  
IO  
HSUSB2  
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Table 2-19. Serial Communication Interfaces – USB Signals Description (continued)  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
hsusb2_clk  
Dedicated for external  
transceiver 60-MHz clock  
input from PHY  
O
AC20  
E22  
hsusb2_stp  
hsusb2_dir  
Dedicated for external  
transceiver Stop signal  
O
I
AB20  
AE21  
E20  
E18  
Dedicated for external  
transceiver Data direction  
control from PHY  
hsusb2_nxt  
Dedicated for external  
transceiver Next signal  
from PHY  
I
AD21  
AC21  
AE22  
AE16  
AE17  
AC16  
D20  
D19  
D18  
J21  
hsusb2_data0  
hsusb2_data1  
hsusb2_data2  
hsusb2_data3  
hsusb2_data4  
Dedicated for external  
transceiver Bidirectional  
data bus  
IO  
IO  
IO  
IO  
IO  
Dedicated for external  
transceiver Bidirectional  
data bus  
Dedicated for external  
transceiver Bidirectional  
data bus  
Dedicated for external  
transceiver Bidirectional  
data bus  
H19  
H20  
Dedicated for external  
transceiver Bidirectional  
data bus additional signals  
for 12-pin ULPI operation.  
hsusb2_data5  
hsusb2_data6  
hsusb2_data7  
Dedicated for external  
IO  
IO  
IO  
AB16  
AA16  
AD16  
H22  
H21  
J22  
transceiver Bidirectional  
data bus additional signals  
for 12-pin ULPI operation.  
Dedicated for external  
transceiver Bidirectional  
data bus additional signals  
for 12-pin ULPI operation.  
Dedicated for external  
transceiver Bidirectional  
data bus  
HSUSB1  
hsusb1_clk  
Dedicated for external  
transceiver 60-MHz clock  
input from PHY  
O
AE18  
G21  
hsusb1_stp  
hsusb1_dir  
Dedicated for external  
transceiver Stop signal  
O
I
AD17  
AE20  
G22  
D22  
Dedicated for external  
transceiver Data direction  
control from PHY  
hsusb1_nxt  
Dedicated for external  
transceiver Next signal  
from PHY  
I
AD20  
AD18  
AC18  
AB18  
D21  
G20  
F22  
F20  
hsusb1_data0  
hsusb1_data1  
hsusb1_data2  
Dedicated for external  
transceiver Bidirectional  
data bus  
IO  
IO  
IO  
Dedicated for external  
transceiver Bidirectional  
data bus  
Dedicated for external  
transceiver Bidirectional  
data bus  
68  
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Table 2-19. Serial Communication Interfaces – USB Signals Description (continued)  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
hsusb1_data3  
Dedicated for external  
transceiver Bidirectional  
data bus  
IO  
AB19  
E21  
hsusb1_data4  
hsusb1_data5  
hsusb1_data6  
hsusb1_data7  
Dedicated for external  
IO  
IO  
IO  
IO  
Y18  
E19  
F21  
F19  
G19  
transceiver Bidirectional  
data bus additional signals  
for 12-pin ULPI operation  
Dedicated for external  
AE19  
AD19  
AA18  
transceiver Bidirectional  
data bus additional signals  
for 12-pin ULPI operation  
Dedicated for external  
transceiver Bidirectional  
data bus additional signals  
for 12-pin ULPI operation  
Dedicated for external  
transceiver Bidirectional  
data bus additional signals  
for 12-pin ULPI operation  
2.4.4 Removable Media Interfaces  
Table 2-20. Removable Media Interfaces – MMC/SDIO Signals Description  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
MULTIMEDIA MEMORY CARD (MMC1) / SECURE DIGITAL IO (SDIO1)  
mmc1_clk  
MMC/SD Output Clock  
O
AA9  
AB9  
AC9  
P22  
N21  
P21  
mmc1_cmd  
mmc1_dat0  
MMC/SD command signal IO  
MMC/SD Card Data bit 0 / IO  
SPI Serial Input  
mmc1_dat1  
mmc1_dat2  
mmc1_dat3  
mmc1_dat4  
mmc1_dat5  
mmc1_dat6  
mmc1_dat7  
MMC/SD Card Data bit 1 IO  
MMC/SD Card Data bit 2 IO  
MMC/SD Card Data bit 3 IO  
MMC/SD Card Data bit 4 IO  
MMC/SD Card Data bit 5 IO  
MMC/SD Card Data bit 6 IO  
MMC/SD Card Data bit 7 IO  
AD9  
N20  
P19  
P20  
N22  
N19  
N18  
P18  
AE9  
AA10  
AB10  
AC10  
AD10  
AE10  
MULTIMEDIA MEMORY CARD (MMC2) / SECURE DIGITAL IO (SDIO2)  
mmc2_clk  
MMC/SD Output Clock  
O
O
AD11  
AB13  
M21  
L18  
mmc2_dir_dat0  
Direction control for DAT0  
signal case an external  
transceiver used  
mmc2_dir_dat1  
mmc2_dir_dat2  
mmc2_dir_dat3  
Direction control for DAT1  
and DAT3 signals case an  
external transceiver used  
O
O
O
AC13  
AB1  
L20  
V18  
Y19  
Direction control for DAT2  
signal case an external  
transceiver used  
Direction control for DAT4,  
DAT5, DAT6, and DAT7  
signals case an external  
transceiver used  
AB2  
mmc2_clkin  
mmc2_dat0  
mmc2_dat1  
mmc2_dat2  
MMC/SD input clock  
I
AE13  
AB12  
AC12  
AD12  
NA  
MMC/SD Card Data bit 0 IO  
MMC/SD Card Data bit 1 IO  
MMC/SD Card Data bit 2 IO  
K20  
L19  
M18  
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Table 2-20. Removable Media Interfaces – MMC/SDIO Signals Description (continued)  
SIGNAL NAME [1]  
mmc2_dat3  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
AE12  
ZER BALL [4]  
MMC/SD Card Data bit 3 IO  
MMC/SD Card Data bit 4 IO  
MMC/SD Card Data bit 5 IO  
MMC/SD Card Data bit 6 IO  
MMC/SD Card Data bit 7 IO  
K21  
L18  
L20  
L21  
M19  
NA  
mmc2_dat4  
AB13  
mmc2_dat5  
AC13  
mmc2_dat6  
AD13  
mmc2_dat7  
AE13  
mmc2_dir_cmd  
Direction control for CMD  
signal case an external  
transceiver is used  
O
AD13  
mmc2_cmd  
MMC/SD command signal IO  
AE11  
M20  
MULTIMEDIA MEMORY CARD (MMC3) / SECURE DIGITAL IO (SDIO3)  
mmc3_clk  
MMC/SD Output Clock  
O
AE15,AD17  
AD14,AE18  
AB13,Y18  
J19,G22  
J20,G21  
E19,L18  
mmc3_cmd  
mmc3_dat0  
MMC/SD command signal IO  
MMC/SD Card Data bit 0 / IO  
SPI Serial Input  
mmc3_dat1  
mmc3_dat2  
mmc3_dat3  
mmc3_dat4  
mmc3_dat5  
mmc3_dat6  
mmc3_dat7  
MMC/SD Card Data bit 1 IO  
MMC/SD Card Data bit 2 IO  
MMC/SD Card Data bit 3 IO  
MMC/SD Card Data bit 4 IO  
MMC/SD Card Data bit 5 IO  
MMC/SD Card Data bit 6 IO  
MMC/SD Card Data bit 7 IO  
AC13,AE19  
AD13,AD19  
AE13,AA18  
AD18  
L20,F21  
L21,F19  
M19,G19  
G20  
AD20  
D21  
AE20  
D22  
AB19  
E21  
70  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
2.4.5 Test Interfaces  
Table 2-21. Test Interfaces – ETK Signals Description  
SIGNAL NAME [1]  
etk_ctl  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
AE18  
AD17  
AD18  
AC18  
AB18  
AA18  
Y18  
ZER BALL [4]  
G21  
G22  
G20  
F22  
ETK trace ctl  
ETK trace clock  
ETK data 0  
ETK data 1  
ETK data 2  
ETK data 3  
ETK data 4  
ETK data 5  
ETK data 6  
ETK data 7  
ETK data 8  
ETK data 9  
ETK data 10  
ETK data 11  
ETK data 12  
ETK data 13  
ETK data 14  
ETK data 15  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
etk_clk  
etk_d0  
etk_d1  
etk_d2  
F20  
etk_d3  
G19  
E19  
etk_d4  
etk_d5  
AE19  
AD19  
AB19  
AE20  
AD20  
AC20  
AB20  
AE21  
AD21  
AC21  
AE22  
F21  
etk_d6  
F19  
etk_d7  
E21  
etk_d8  
D22  
etk_d9  
D21  
etk_d10  
etk_d11  
etk_d12  
etk_d13  
etk_d14  
etk_d15  
E22  
E20  
E18  
D20  
D19  
D18  
Table 2-22. Test Interfaces – JTAG Signals Description  
SIGNAL NAME [1]  
jtag_ntrst  
DESCRIPTION [2]  
Test Reset  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
D13  
I
U24  
U25  
T21  
T22  
T23  
T24  
T25  
R24  
jtag_tck  
Test Clock  
I
E14  
jtag_rtck  
ARM Clock Emulation  
Test Mode Select  
Test Data Input  
Test Data Output  
Test emulation 0  
Test emulation 1  
O
IO  
I
C12  
jtag_tms_tmsc  
jtag_tdi  
A12  
B12  
jtag_tdo  
O
IO  
IO  
D12  
jtag_emu0  
jtag_emu1  
E13  
E12  
Table 2-23. Test Interfaces – HWDBG Signals Description  
SIGNAL NAME [1]  
hw_dbg0  
DESCRIPTION [2]  
Debug signal 0  
Debug signal 1  
Debug signal 2  
Debug signal 3  
Debug signal 4  
Debug signal 5  
Debug signal 6  
Debug signal 7  
Debug signal 8  
Debug signal 9  
Debug signal 10  
Debug signal 11  
Debug signal 12  
TYPE [3]  
ZCN BALL [4]  
AD2,AD17  
AD1,AE18  
AD3,AD18  
AE3,AC18  
AC5,AB18  
AD5,AA18  
Y18,AE5  
ZER BALL [4]  
G22  
O
O
O
O
O
O
O
O
O
O
O
O
O
hw_dbg1  
G21  
hw_dbg2  
G20  
hw_dbg3  
F22  
hw_dbg4  
F20  
hw_dbg5  
G19  
hw_dbg6  
E19  
hw_dbg7  
Y6,AE19  
F21  
hw_dbg8  
Y7,AD19  
F19  
hw_dbg9  
AA7,AB19  
AC7,AE20  
AD7,AD20  
AE23,AC20  
E21  
hw_dbg10  
hw_dbg11  
hw_dbg12  
D22  
D21  
E22  
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Terminal Description  
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Table 2-23. Test Interfaces – HWDBG Signals Description (continued)  
SIGNAL NAME [1]  
hw_dbg13  
DESCRIPTION [2]  
Debug signal 13  
Debug signal 14  
Debug signal 15  
Debug signal 16  
Debug signal 17  
TYPE [3]  
ZCN BALL [4]  
AD22,AB20  
AB25,AE21  
AA23,AD21  
AA24,AC21  
AA25,AE22  
ZER BALL [4]  
O
O
O
O
O
E20  
E18  
D20  
D19  
D18  
hw_dbg14  
hw_dbg15  
hw_dbg16  
hw_dbg17  
2.4.6 Miscellaneous  
Table 2-24. Miscellaneous – GP Timer Signals Description  
SIGNAL NAME [1]  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
gpt8_pwm_evt  
PWM or event for GP  
timer 8  
IO  
N4,E23,AE17  
V11,C6,H19  
gpt9_pwm_evt  
gpt10_pwm_evt  
gpt11_pwm_evt  
PWM or event for GP  
timer 9  
IO  
IO  
IO  
M4,M2,F20,AC16  
M3,M1,F19,AB16  
N5,E24,AA16  
Y12,AA11,A5,H20  
V12,W12,B5,H22  
AA12,D6,H21  
PWM or event for GP  
timer 10  
PWM or event for GP  
timer 11  
72  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
2.4.7 General-Purpose IOs  
Table 2-25. General-Purpose IOs Signals Description  
SIGNAL NAME [1]  
gpio_0  
DESCRIPTION [2]  
TYPE [3]  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
ZCN BALL [4]  
Y1  
ZER BALL [4]  
AB18  
B8  
General-purpose IO 0  
General-purpose IO 1  
General-purpose IO 2  
General-purpose IO 3  
General-purpose IO 4  
General-purpose IO 5  
General-purpose IO 6  
General-purpose IO 7  
General-purpose IO 8  
General-purpose IO 10  
General-purpose IO 11  
General-purpose IO 12  
General-purpose IO 13  
General-purpose IO 14  
General-purpose IO 15  
General-purpose IO 16  
General-purpose IO 17  
General-purpose IO 18  
General-purpose IO 19  
General-purpose IO 20  
General-purpose IO 21  
General-purpose IO 22  
General-purpose IO 23  
General-purpose IO 24  
General-purpose IO 25  
General-purpose IO 26  
General-purpose IO 27  
General-purpose IO 28  
General-purpose IO 29  
General-purpose IO 30  
General-purpose IO 31  
General-purpose IO 34  
General-purpose IO 35  
General-purpose IO 36  
General-purpose IO 37  
General-purpose IO 38  
General-purpose IO 39  
General-purpose IO 40  
General-purpose IO 41  
General-purpose IO 42  
General-purpose IO 43  
General-purpose IO 44  
General-purpose IO 45  
General-purpose IO 46  
General-purpose IO 47  
gpio_1  
M24  
Y4  
gpio_2  
AB19  
AB20  
W18  
AA19  
V18  
Y19  
W19  
E9  
gpio_3  
AA1  
AA2  
AA3  
AB1  
AB2  
AC1  
N25  
T25  
gpio_4  
gpio_5  
gpio_6  
gpio_7  
gpio_8  
gpio_10  
gpio_11  
gpio_12  
gpio_13  
gpio_14  
gpio_15  
gpio_16  
gpio_17  
gpio_18  
gpio_19  
gpio_20  
gpio_21  
gpio_22  
gpio_23  
gpio_24  
gpio_25  
gpio_26  
gpio_27  
gpio_28  
gpio_29  
gpio_30  
gpio_31  
gpio_34  
gpio_35  
gpio_36  
gpio_37  
gpio_38  
gpio_39  
gpio_40  
gpio_41  
gpio_42  
gpio_43  
gpio_44  
gpio_45  
gpio_46  
gpio_47  
E13  
G22  
G21  
G20  
F22  
AD17  
AE18  
AD18  
AC18  
AB18  
AA18  
Y18  
AE19  
AD19  
AB19  
AE20  
AD20  
AC20  
AB20  
AE21  
AD21  
AC21  
AE22  
Y3  
F20  
G19  
E19  
F21  
F19  
E21  
D22  
D21  
E22  
E20  
E18  
D20  
D19  
D18  
Y18  
E12  
W5  
R24  
E3  
E2  
Y5  
E1  
AB4  
AA5  
AB5  
AB6  
AA6  
W6  
F7  
F6  
F4  
F3  
F2  
F1  
AB7  
Y6  
G6  
J4  
W10  
AB9  
AB10  
W9  
J3  
J2  
J1  
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Table 2-25. General-Purpose IOs Signals Description (continued)  
SIGNAL NAME [1]  
gpio_48  
gpio_49  
gpio_50  
gpio_51  
gpio_52  
gpio_53  
gpio_54  
gpio_55  
gpio_56  
gpio_57  
gpio_58  
gpio_59  
gpio_60  
gpio_61  
gpio_62  
gpio_63  
gpio_64  
gpio_65  
gpio_66  
gpio_67  
gpio_68  
gpio_69  
gpio_70  
gpio_71  
gpio_72  
gpio_73  
gpio_74  
gpio_75  
gpio_76  
gpio_77  
gpio_78  
gpio_79  
gpio_80  
gpio_81  
gpio_82  
gpio_83  
gpio_84  
gpio_85  
gpio_86  
gpio_87  
gpio_88  
gpio_89  
gpio_90  
gpio_91  
gpio_92  
gpio_93  
gpio_94  
DESCRIPTION [2]  
TYPE [3]  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
ZCN BALL [4]  
K4  
ZER BALL [4]  
AA10  
Y9  
General-purpose IO 48  
General-purpose IO 49  
General-purpose IO 50  
General-purpose IO 51  
General-purpose IO 52  
General-purpose IO 53  
General-purpose IO 54  
General-purpose IO 55  
General-purpose IO 56  
General-purpose IO 57  
General-purpose IO 58  
General-purpose IO 59  
General-purpose IO 60  
General-purpose IO 61  
General-purpose IO 62  
General-purpose IO 63  
General-purpose IO 64  
General-purpose IO 65  
General-purpose IO 66  
General-purpose IO 67  
General-purpose IO 68  
General-purpose IO 69  
General-purpose IO 70  
General-purpose IO 71  
General-purpose IO 72  
General-purpose IO 73  
General-purpose IO 74  
General-purpose IO 75  
General-purpose IO 76  
General-purpose IO 77  
General-purpose IO 78  
General-purpose IO 79  
General-purpose IO 80  
General-purpose IO 81  
General-purpose IO 82  
General-purpose IO 83  
General-purpose IO 84  
General-purpose IO 85  
General-purpose IO 86  
General-purpose IO 87  
General-purpose IO 88  
General-purpose IO 89  
General-purpose IO 90  
General-purpose IO 91  
General-purpose IO 92  
General-purpose IO 93  
General-purpose IO 94  
K3  
K2  
V10  
K1  
V9  
L1  
Y11  
M4  
Y12  
M3  
V12  
M2  
AA11  
W12  
AA12  
V11  
M1  
N5  
N4  
N1  
AB13  
W11  
Y15  
R4  
T1  
T2  
W14  
AA16  
Y14  
T4  
T5  
U1  
V14  
AE23  
AD22  
AD23  
AE24  
AD24  
AD25  
AC23  
AC24  
AC25  
AB24  
AB25  
AA23  
AA24  
AA25  
Y22  
Y23  
Y24  
Y25  
W21  
W22  
W23  
W24  
W25  
V24  
V25  
U21  
U22  
U23  
AD2  
B22  
B21  
B20  
B19  
A20  
A19  
A18  
B18  
A17  
C18  
D17  
B16  
B17  
C17  
C16  
D16  
D14  
A16  
D15  
B15  
A15  
A14  
C13  
C15  
A13  
B13  
C14  
B14  
AB21  
74  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 2-25. General-Purpose IOs Signals Description (continued)  
SIGNAL NAME [1]  
gpio_95  
DESCRIPTION [2]  
TYPE [3]  
IO  
IO  
IO  
IO  
I
ZCN BALL [4]  
AD1  
ZER BALL [4]  
AA21  
Y21  
General-purpose IO 95  
General-purpose IO 96  
General-purpose IO 97  
General-purpose IO 98  
General-purpose IO 99  
General-purpose IO 100  
General-purpose IO 101  
General-purpose IO 102  
General-purpose IO 103  
General-purpose IO 104  
General-purpose IO 105  
General-purpose IO 106  
General-purpose IO 107  
General-purpose IO 108  
General-purpose IO 109  
General-purpose IO 110  
General-purpose IO 111  
General-purpose IO 112  
General-purpose IO 113  
General-purpose IO 114  
General-purpose IO 116  
General-purpose IO 117  
General-purpose IO 118  
General-purpose IO 119  
General-purpose IO 120  
General-purpose IO 121  
General-purpose IO 122  
General-purpose IO 123  
General-purpose IO 124  
General-purpose IO 125  
General-purpose IO 126  
General-purpose IO 127  
General-purpose IO 128  
General-purpose IO 129  
General-purpose IO 130  
General-purpose IO 131  
General-purpose IO 132  
General-purpose IO 133  
General-purpose IO 134  
General-purpose IO 135  
General-purpose IO 136  
General-purpose IO 137  
General-purpose IO 138  
General-purpose IO 139  
General-purpose IO 140  
General-purpose IO 141  
General-purpose IO 142  
gpio_96  
AE2  
gpio_97  
AD3  
Y22  
gpio_98  
AE3  
W21  
W22  
W20  
V21  
gpio_99  
AD4  
gpio_100  
gpio_101  
gpio_102  
gpio_103  
gpio_104  
gpio_105  
gpio_106  
gpio_107  
gpio_108  
gpio_109  
gpio_110  
gpio_111  
gpio_112  
gpio_113  
gpio_114  
gpio_116  
gpio_117  
gpio_118  
gpio_119  
gpio_120  
gpio_121  
gpio_122  
gpio_123  
gpio_124  
gpio_125  
gpio_126  
gpio_127  
gpio_128  
gpio_129  
gpio_130  
gpio_131  
gpio_132  
gpio_133  
gpio_134  
gpio_135  
gpio_136  
gpio_137  
gpio_138  
gpio_139  
gpio_140  
gpio_141  
gpio_142  
I
AE4  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
AC5  
AD5  
V19  
AE5  
V22  
Y6  
U20  
AB6  
V20  
AC6  
U19  
AE6  
U21  
AD6  
U22  
Y7  
T19  
AA7  
T20  
AB7  
T21  
AE7  
R20  
I
AD8  
R19  
I
AE8  
R21  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
D25  
E5  
C25  
D5  
B25  
C5  
D24  
E4  
AA9  
P22  
AB9  
N21  
AC9  
P21  
AD9  
N20  
AE9  
P19  
E25, AA10  
AB10, AD7  
AC10  
AD10  
AE10  
V2, AD11  
V3, AE11  
AB12  
AC12  
AD12  
AE12  
AB13  
AC13  
AD13  
AE13  
B24  
A7, P20  
N22, T22  
N19  
N18  
P18  
M21, AB15  
M20, AB16  
K20  
L19  
M18  
K21  
L18  
L20  
L21  
M19  
C4  
C24  
B4  
A24  
D4  
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Table 2-25. General-Purpose IOs Signals Description (continued)  
SIGNAL NAME [1]  
gpio_143  
gpio_144  
gpio_145  
gpio_146  
gpio_147  
gpio_148  
gpio_149  
gpio_150  
gpio_151  
gpio_152  
gpio_153  
gpio_154  
gpio_155  
gpio_156  
gpio_157  
gpio_158  
gpio_159  
gpio_160  
gpio_161  
gpio_162  
gpio_163  
gpio_164  
gpio_165  
gpio_166  
gpio_167  
gpio_168  
gpio_170  
gpio_171  
gpio_172  
gpio_173  
gpio_174  
gpio_175  
gpio_176  
gpio_177  
gpio_178  
gpio_179  
gpio_180  
gpio_181  
gpio_182  
gpio_183  
gpio_184  
gpio_185  
gpio_186  
DESCRIPTION [2]  
TYPE [3]  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
ZCN BALL [4]  
C23  
ZER BALL [4]  
A4  
General-purpose IO 143  
General-purpose IO 144  
General-purpose IO 145  
General-purpose IO 146  
General-purpose IO 147  
General-purpose IO 148  
General-purpose IO 149  
General-purpose IO 150  
General-purpose IO 151  
General-purpose IO 152  
General-purpose IO 153  
General-purpose IO 154  
General-purpose IO 155  
General-purpose IO 156  
General-purpose IO 157  
General-purpose IO 158  
General-purpose IO 159  
General-purpose IO 160  
General-purpose IO 161  
General-purpose IO 162  
General-purpose IO 163  
General-purpose IO 164  
General-purpose IO 165  
General-purpose IO 166  
General-purpose IO 167  
General-purpose IO 168  
General-purpose IO 170  
General-purpose IO 171  
General-purpose IO 172  
General-purpose IO 173  
General-purpose IO 174  
General-purpose IO 175  
General-purpose IO 176  
General-purpose IO 177  
General-purpose IO 178  
General-purpose IO 179  
General-purpose IO 180  
General-purpose IO 181  
General-purpose IO 182  
General-purpose IO 183  
General-purpose IO 184  
General-purpose IO 185  
General-purpose IO 186  
F20  
A5  
F19  
B5  
E24  
D6  
E23  
C6  
AA19  
Y19  
C22  
C21  
C19  
C20  
A3  
Y20  
W20  
B23  
A23  
B3  
B22  
A2  
A22  
B2  
R25  
B11  
D11  
C10  
C9  
P21  
P22  
P23  
P25  
E11  
C11  
C8  
P24  
N24  
N2  
W15  
W13  
AA13  
Y13  
R22  
Y17  
B9  
N3  
P1  
P2  
AC7  
W1  
L25  
AE14  
AD15  
AC15  
AB15  
AD14  
AE15  
AE16  
AD16  
AC16  
AB16  
AA16  
AE17  
W2  
K22  
K19  
J18  
K18  
J20  
J19  
J21  
J22  
H20  
H22  
H21  
H19  
Y16  
W16  
W17  
E10  
W4  
W5  
M25  
76  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
2.4.8 System and Miscellaneous Terminals  
Table 2-26. System and Miscellaneous Signals Description  
SIGNAL NAME [1]  
sys_32k  
DESCRIPTION [2]  
TYPE [3]  
ZCN BALL [4]  
ZER BALL [4]  
32-kHz clock input  
I
K24  
K25  
H25  
L25  
A8  
sys_xtalin  
Main input clock. Oscillator input  
Output of oscillator  
I
A10  
A9  
sys_xtalout  
sys_altclk  
O
I
Alternate clock source selectable for  
GPTIMERs (maximum 54 MHz), USB (48  
MHz) , or NTSC/PAL (54 MHz)  
B9  
sys_clkreq  
Request from device for system clock (open IO  
source type)  
M24  
B8  
sys_clkout1  
sys_clkout2  
sys_boot0  
sys_boot1  
sys_boot2  
sys_boot3  
sys_boot4  
sys_boot5  
sys_boot6  
sys_boot7  
sys_boot8  
sys_nrespwron  
sys_nreswarm  
sys_nirq  
Configurable output clock1  
Configurable output clock2  
Boot configuration mode bit 0  
Boot configuration mode bit 1  
Boot configuration mode bit 2  
Boot configuration mode bit 3  
Boot configuration mode bit 4  
Boot configuration mode bit 5  
Boot configuration mode bit 6  
Boot configuration mode bit 7  
Boot configuration mode bit 8  
Power On Reset  
O
N25  
M25  
Y4  
E9  
O
E10  
I
AB19  
AB20  
W18  
AA19  
V18  
I
AA1  
AA2  
AA3  
AB1  
AB2  
AC1  
AC2  
AC3  
Y2  
I
I
I
I
Y19  
I
W19  
AA20  
Y20  
I
I
I
AA18  
Y18  
Warm Boot Reset (open drain output)  
External FIQ input  
IOD  
Y3  
I
I
Y1  
AB18  
V12  
sys_ndmareq0  
External DMA request 0 (system  
expansion). Level (active low) or edge  
(falling) selectable.  
M3  
sys_ndmareq1  
sys_ndmareq2  
sys_ndmareq3  
External DMA request 1 (system  
expansion). Level (active low) or edge  
(falling) selectable.  
I
I
I
M2,U1  
F1,M1  
G6,N5  
AA11,V14  
W12,AB7  
AA12,V6  
External DMA request 2 (system  
expansion). Level (active low) or edge  
(falling) selectable.  
External DMA request 3 (system  
expansion). Level (active low) or edge  
(falling) selectable.  
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2.4.9 Power Supplies  
Table 2-27. Power Supplies Description  
BALL  
(ZCN Pkg.) [4]  
BALL  
(ZER Pkg.) [4]  
SIGNAL NAME[1]  
DESCRIPTION[2]  
V16, V15, V11,  
V10, U16, U15,  
U11, U10, T18,  
T17, T9, T8,  
R18, R17, R9,  
R8, M18, L18,  
L9, L8, K18,  
K17, K9, K8,  
J16, J15, J11,  
J10, H15, H11,  
H10  
J8,J10, J12, J14, J16, K9, K11, K13,  
K15, L8, L10, L12, L14, M7, M9,  
M11, M13, M15, N8, N10, N12, N14,  
P7, P9, P11, P13, P15, R8, R10,  
R12, R14  
VDD_CORE  
1.2-V core and oscillator macros power supply.  
AE25, AE1,  
V18, V17, V14,  
V13, V12, V9,  
V8, U18, U17,  
U14, U13, U12,  
U9, U8, T14,  
T13, T12, R16,  
R15, R14, R13,  
R12, R11, R10,  
P18, P17, P16,  
P15, P14, P13,  
P12, P11, P10,  
P9, P8, N18,  
A1, A11,A22, E6, E16, F6, F13, F15,  
F17, G5, G7, G11, G14, G16, G18,  
H6, H7, H8, H9, H10, H11, H12, H13,  
H14, H15, H16, H17, J9, J11, J13,  
J15, K8, K10, K12, K14, K16, L7, L9,  
L11, L13, L15, M1, M6, M8, M10,  
M12, M14, M16, M22, N7, N9, N11,  
N13, N15, N17, P6, P8, P10, P12,  
P14, P16, R5, R7, R9, R11, R13,  
R15, R17, T6, T8, T10, T12, T14,  
T16, T18, U5, U7, U9, U11, U13,  
U15, U17, V6, AB1, AB12, AB22  
VSS  
Core and I/O common ground.  
N17, N14, N13,  
N12, N9, N8,  
M17, M16, M15,  
M14, M13,M12,  
M11, M10, M9,  
M8, L17, L16,  
L15, L14, L13,  
L12, L11, L10,  
K14, K13, K12,  
J18, J17, J14,  
J13, J12, J9, J8,  
H14, H13, H12,  
H9, A25, A1,  
N23, G20, G21  
VDDS_SRAM_MPU  
1.8-V MPU SLDO analog power supply.  
AA13  
L17  
J6  
1.8-V Core SLDO and VDDA of BandGap analog  
power supply.  
VDDS_SRAM_CORE_BG  
E17  
1.2-V SRAMOUT for MPU SLDO.  
For proper device operation, connect to a 1μF  
decoupling capacitor.  
CAP_VDD_SRAM_MPU  
CAP_VDD_SRAM_CORE  
AA12  
E16  
M17  
K6  
1.2-V SRAMOUT for Core SLDO.  
For proper device operation, connect to a 1μF  
decoupling capacitor.  
VDDS_DPLL_MPU_USBH 1.8-V MPUSS DPLL and USBHOST DPLL analog  
AA15  
N20  
K17  
F11  
OST  
power supply.  
1.8-V DPLL and HSDIVIDER/ CORE and  
HSDIVIDER analog power supply.  
VDDS_DPLL_PER_CORE  
VDDA_DAC  
1.8-V DAC analog power supply.  
DAC analog ground.  
H21  
H22  
F23  
G22  
NA  
NA  
F7  
VSSA_DAC  
VDDA3P3V_USBPHY  
VDDA1P8V_USBPHY  
3.3-V USB transceiver analog power supply.  
1.8-V USB transceiver power supply.  
D7  
Output of the 1.2-V internal LDO.  
For proper device operation, connect a 0.22uF  
capacitor between this pin and VSSA.  
CAP_VDDA1P2LDO_USB  
PHY  
F22  
E7  
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Table 2-27. Power Supplies Description (continued)  
BALL  
(ZCN Pkg.) [4]  
BALL  
(ZER Pkg.) [4]  
SIGNAL NAME[1]  
DESCRIPTION[2]  
Y16, Y15, Y13,  
Y12, Y10, W16,  
W15, W13,  
W12,W10, W9,  
W6, V7, V6,  
A21, B1,E15, E17, F12, F14, F18,  
G10, G12, G13, G8, G17, H18, J17,  
L22, N16, P17, R16, R18, T9, T11,  
T13, T17, U8, U10, U12, U14, U16,  
U18, V7, V8, V17, AA22, AB11  
U19, T20, T19,  
T7, T6, R7, R6,  
P20, P19, N19,  
N7, N6, M7, M6,  
M5, L19, K19,  
K7, K6, K5, J7,  
H18, H17  
VDDSHV  
1.8/3.3-V power supply.  
Y9, W18, U20,  
R5, H16, H8,  
G17, G16, G14,  
G13, G11, G10,  
G8, F16, F13,  
F11, F10, F8  
F5, F16, G9, G15, H5, K7, L6, L16,  
N1, N5, N6, P5, R6, T5, T7, T15, U6,  
AA1  
VDDS  
1.8-V power supply.  
VDDSOSC  
VSSOSC  
1.8-V oscillator power supply.  
Oscillator ground.  
L20  
J25  
G9  
B10  
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3 Electrical Characteristics  
3.1 Absolute Maximum Ratings  
The following table specifies the absolute maximum ratings over the operating junction temperature range  
of commercial and extended temperature devices. Stresses beyond those listed under absolute maximum  
ratings may cause permanent damage to the device. These are stress ratings only and functional  
operation of the device at these or any other conditions beyond those indicated under recommended  
operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods  
may affect device reliability.  
Notes:  
•
Logic functions and parameter values are not assured out of the range specified in the recommended  
operating conditions.  
Table 3-1. Absolute Maximum Ratings Over Operating Junction Temperature Range  
PARAMETER  
MIN  
-0.5  
-0.5  
-0.5  
-0.5  
-0.5  
MAX  
1.6  
UNIT  
VDD_CORE  
Supply voltage range for core macros  
Second supply voltage range for 1.8-V I/O macros  
Supply voltage range for 1.8/3.3V I/O macros  
Analog Supply voltage range for 1.8-V MPU SLDO  
V
V
V
V
V
VDDS  
2.25  
3.8  
VDDSHV  
VDDS_SRAM_MPU  
VDDS_SRAM_CORE_BG  
2.25  
2.25  
Analog Supply voltage range for 1.8-V Core SLDO and  
VDDA of BandGap  
VDDS_DPLL_MPU_USBHOST Analog power supply for 1.8-V MPUSS DPLL and  
USBHOST DPLL  
-0.5  
-0.5  
2.1  
2.1  
V
V
VDDS_DPLL_PER_CORE  
Analog power supply for 1.8-V DPLL and HSDIVIDER/  
CORE and HSDIVIDER  
VDDA_DAC  
Analog Power Supply for 1.8-V DAC  
Analog power supply for 3.3-V USB transceiver  
Power Supply for 1.8-V USB transceiver  
Power Supply for 1.8-V oscillator  
Oscillator input (sys_xtalin)  
-0.5  
-0.5  
-0.5  
-0.5  
-0.3  
-0.3  
-0.3  
2.43  
3.6  
V
V
V
V
VDDA3P3V_USBPHY  
VDDA1P8V_USBPHY  
VDDSOSC  
2.0  
2.1  
VDDSOSC + 0.3  
VDDS + 0.3  
VDDSHV + 0.3  
VDDS 1.8-V I/O macros  
Dual-voltage LVCMOS inputs, VDDSHV  
= 1.8 V  
Voltage range at  
VPAD  
V
V
Dual-voltage LVCMOS inputs, VDDSHV  
PAD  
-0.3  
3.8  
= 3.3 V  
USB VBUS pin (usb0_vbus)  
5.5  
USB 5V Tolerant IOs (usb0_dp,  
usb0_dm, usb0_id)  
HBM (human body model)(2)  
5.25  
>1000  
>500  
ESD stress  
VESD  
voltage(1)  
CDM (charged device model)(3)  
IIOI  
Current-pulse injection on each I/O pin(4)  
Clamp current for an input or output  
Storage temperature range  
200  
20  
mA  
mA  
°C  
Iclamp  
Tstg  
-20  
-65  
150  
(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.  
(2) The level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500V HBM  
allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if necessary  
precautions are taken. Actual performance of the device may exceed the value listed above.  
(3) The level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows  
safe manufacturing with a standard ESD control process. Actual performance of the device may exceed the value listed above.  
(4) Each device is tested with I/O pin injection of 200 mA with a stress voltage of 1.5 times maximum vdd at room temperature.  
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The supply voltages and power consumption estimates are detailed in Table 3-2.  
Table 3-2. Estimated Power Consumption at Ball Level  
MAX  
CURRENT  
(mA)  
SIGNAL NAME  
VDD_CORE  
DESCRIPTION  
1.2-V core and oscillator macros power supply  
AM3517  
AM3505  
1500 mA  
1400 mA  
40 mA  
40 mA  
25 mA  
25 mA  
65 mA  
10 mA  
50 mA  
300 mA  
200 mA  
20 mA  
VDDS_SRAM_MPU  
VDDS_SRAM_CORE_BG  
VDDS_DPLL_MPU_USBHOST  
VDDS_DPLL_PER_CORE  
VDDA_DAC  
1.8-V MPU SLDO analog power supply  
1.8-V Core SLDO and VDDA of BandGap analog power supply  
1.8-V MPUSS DPLL and USBHOST DPLL analog power supply  
1.8-V DPLL and HSDIVIDER/ CORE and HSDIVIDER analog power supply  
1.8-V DAC analog power supply  
VDDA3P3V_USBPHY  
VDDA1P8V_USBPHY  
VDDSHV  
3.3-V USB transceiver analog power supply  
1.8-V USB transceiver power supply  
3.3-/1.8-V power supply  
VDDS  
1.8-V power supply  
VDDSOSC  
1.8-V oscillator power supply  
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3.2 Recommended Operating Conditions  
All AM3517/05 modules are used under the operating conditions contained in Table 3-3.  
Note: Logic functions and parameter values are not assured if the device is operated out of the range  
specified in the recommended operating conditions.  
Table 3-3. Recommended Operating Conditions  
PARAMETER  
DESCRIPTION  
MIN  
NOM  
MAX  
1.248  
24.00  
1.89  
UNIT  
V
VDD_CORE  
Core and oscillator macros power supply  
Noise (peak-peak)  
1.152  
1.20  
mVpp  
V
VDDS_SRAM_ MPU SRAM LDO analog power supply  
MPU  
1.71  
1.71  
1.80  
1.80  
Noise (peak-peak)  
50.00  
1.89  
mVpp  
V
VDDS_SRAM_ Core SRAM LDO and BandGap analog power  
CORE_BG  
supply  
Noise (peak-peak)  
50.00  
1.89  
mVpp  
V
VDDS_DPLL_  
MPU_  
USBHOST  
MPU and USBHOST DPLL analog power supply  
Noise (peak-peak)  
1.71  
1.80  
35.00  
mVpp  
VDDS_DPLL_  
PER_CORE  
Peripherals and Core DPLLs analog power supply 1.71  
Noise (peak-peak)  
1.80  
1.80  
1.89  
V
35.00  
1.89  
mVpp  
VDDA_DAC  
DAC analog power supply  
Noise (peak-peak)  
1.71  
V
30.00  
mVpp  
VSSA_DAC  
DAC analog ground  
0.00  
3.30  
V
VDDA3P3V_  
USBPHY  
Analog power supply for 3.3-V USB transceiver  
Noise (peak-peak)  
3.14  
1.71  
3.47  
70.00  
1.89  
50.00  
1.89  
3.47  
1.89  
90  
V
mVpp  
VDDA1P8V_  
USBPHY  
Power Supply for 1.8-V USB transceiver  
Noise (peak-peak)  
1.80  
V
mVpp  
VDDSHV  
3.3-/1.8-V power supply  
1.8 V Mode  
3.3 V Mode  
1.71  
3.14  
1.71  
0
1.80  
3.30  
1.80  
V
V
VDDS  
Tj  
1.8-V power supply  
V
Operating junction temperature Commercial  
°C  
range  
Temperature  
Extended  
-40  
105  
°C  
Temperature  
Device  
500 MHz ARM Clock Freq.  
600 MHz ARM Clock Freq.  
< 90°C TJ  
100K  
100K  
100K  
50K(2)  
hrs.  
Operating Life  
Power-On  
90 - 105 °C TJ  
< 90°C TJ  
Hours (POH)(1)  
90 - 105 °C TJ  
(1) The POH information is provided solely for your convenience and does not extend or modify the warranty provided under TI’s standard  
terms and conditions for TI semiconductor products.  
(2) Maximum lifetime will be 100k Power On Hours as long as no more than 50k is greater than 90°C.  
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The following diagram illustrates the power domains:  
vdds_dpll_mpu_usbhost  
DLL/DCDL  
BandGap  
LDO3  
1.0 V/1.2 V  
BCK  
MEM  
vddshv  
LDO  
in 1.8 V  
out 1.2 V  
MPU  
DPLL_MPU  
vdds  
LDO  
in 1.8 V  
out 1.2 V  
vdd_core  
Core  
SRAM 1 LDO  
0 V/1.0 V/1.2 V  
SRAM1  
ARRAY  
DPLL_CORE  
LDO  
tv_ref  
(for capacitor)  
HSDIVIDER  
vdds_dpll_per_core  
vdda_dac  
SRAM2  
ARRAY  
SRAM 2 LDO  
0 V/1.0 V/1.2 V  
Dual Video DAC  
cap_vdd_sram_core  
LDO  
in 1.8 V  
out 1.2 V  
Periph1  
DPLL4  
LDO  
vss  
HSDIVIDER  
vssa_dac  
LDO  
in 1.8 V  
out 1.2 V  
Periph2  
DPLL5  
vdd_core domain  
Device  
030-003  
Figure 3-1. AM3517/05 Voltage Domains  
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3.3 DC Electrical Characteristics  
Table 3-4 summarizes the dc electrical characteristics.  
Table 3-4. DC Electrical Characteristics  
PARAMETER  
MIN  
NOM  
MAX  
UNIT  
LVCMOS Pin Buffers  
VIH  
High-level input voltage  
0.65 x  
VDDSHV.  
V
V
(1)  
VDDSHV = 1.8 V  
VDDSHV = 3.3 V(1)  
sys_xtalin  
2
0.8 x  
VDDSOSC  
VDDSHV = 1.8 V(1)  
VIL  
Low-level input voltage  
0.35 x  
VDDSHV  
VDDSHV = 3.3 V(1)  
sys_xtalin  
0.8  
0.2 x  
VDDSOSC  
VDDSHV = 1.8 V(1)  
IOH = -2 mA  
VOH  
VOL  
II  
High-level output voltage  
VDDSHV -  
0.45  
V
VDDSHV = 3.3 V(1)  
IOH = -2 mA  
2.4  
VDDSHV = 1.8 V(1)  
IOL = 2 mA  
Low-level output voltage  
0.45  
0.4  
9
V
VDDSHV = 3.3 V(1)  
IOL = 2 mA  
Input current for dual voltage IO pins  
VI = Vss to  
VDDSHV  
Input pins with  
pull disabled  
-9  
µA  
VI = Vss to  
VDDSHV  
Input pins with  
100 µA pull-up  
enabled  
-310  
-70  
VI = Vss to  
VDDSHV  
Input pins with  
100 µA pull-down  
enabled  
75  
77  
-20  
270  
286  
Input current for DDR2/mDDR 1.8V IO  
pins  
VI = Vss to  
VDDSHV  
Input pins with  
100 µA pull-down  
enabled  
IOZ  
IOH  
IOL  
tT  
Off-state output current  
VO = VDDSHV Pull disabled  
or 0V  
20  
-2  
2
µA  
High-level output current (dual-voltage  
LVCMOS IOs)  
mA  
mA  
ns  
Low-level output current (dual-voltage  
LVCMOS IOs)  
Input transition time (rise time, tR or fall VDDSHV = 1.8 Normal mode  
time, tF evaluated between 10% and  
90% at PAD)  
10  
3
V(1)  
High-speed mode  
VDDSHV = 3.3 Normal mode  
10  
3
V(1)  
High-speed mode  
Capacitan Input capacitance  
3
3
pF  
pF  
ce  
(dual-voltage LVCMOS I/Os)  
Output capacitance  
(dual-voltage LVCMOS I/Os)  
Complex IO Dedicated to USB : USB0_DM and USB0_DP  
VIH  
High-level input voltage  
Low-level input voltage  
High-level output voltage  
Low/Full speed  
High speed  
2.0  
V
V
(2)  
V
Low/Full speed  
High speed  
0.8  
IL  
(2)  
VOH  
Low/Full speed  
2.8  
VDDA3P3V_  
USBPHY  
V
High speed  
360  
440  
mV  
(1) These IO specifications apply to the dual-voltage IOs only and do not apply to the DDR2/mDDR interfaces. DDR2/mDDR IOs are 1.8V  
IOs and adhere to the JESD79-2A standard.  
(2) These parameters must adhere to the requirements defined in section 7.1.7.2 of Universal Serial Bus Specifications revision 2.0.  
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PARAMETER  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
Table 3-4. DC Electrical Characteristics (continued)  
MIN  
NOM  
MAX  
UNIT  
VOL  
Low-level output voltage  
Low/Full speed  
High speed  
0.0  
-10  
0.3  
10  
V
mV  
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3.4 Core Voltage Decoupling  
For module performance, decoupling capacitors are required to suppress the switching noise generated  
by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is  
close to the device because this minimizes the inductance of the circuit board wiring and interconnects.  
Table 3-5 summarizes the power supplies decoupling characteristics.  
Table 3-5. Core Voltage Decoupling Characteristics  
PARAMETER  
MIN  
TYP  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
MAX  
UNIT  
nF  
nF  
nF  
nF  
nF  
nF  
nF  
nF  
nF  
nF  
nF  
Cvdd_core(1)  
50  
120  
Ccap_vdd_sram_core  
Cvdds_dpll_mpu_usbhost  
Cvdds_dpll_per_core  
Cvdda_dac  
Cvdd_sram_core  
Cvdd_sram_core_bg  
Cvdds_sram_mpu  
Cvddshv  
Cvdda3p3v_usbphy  
Cvdda1p8v_usbphy  
(1) 1 capacitor per 2 to 4 balls  
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The following illustrates an example of power supply decoupling.  
Device  
vdds_sram_mpu  
vdda_dac  
Cvdda_dac  
vdds_sram_mpu  
vdda_dac  
vssa_dac  
Cvdds_sram_mpu  
Video DAC  
cap_vdd_sram_mpu  
vdds_sram_core_bg  
SRAM_LDO1  
Ccap_vdd_sram_mpu  
vdds_sram_core_bg  
Cvdds_sram_core_bg  
vdd_sram_core  
vdd_sram_core  
SRAM_LDO2  
Cvdd_sram_core  
WKUP_LDO  
BG  
cap_vdd_sram  
_core  
Ccap_vdd_sram_core  
DPLL_MPU  
vdds_dpll_mpu  
_usbhost  
vdds_dpll_mpu_usbhost  
Cvdds_dpll_mpu_usbhost  
DPLL_CORE  
vdds_dpll_per_core  
Cvdds_dpll_per_core  
vdds_dpll_per_core  
DPLL5  
DPLL4  
Vdd_core  
vdd_core  
VSS  
Core  
MPU  
Cvdd_core  
030-004  
(1) Decoupling capacitors must be placed as closed as possible to the power ball. Choose the ground located closest to the power pin  
for each decoupling capacitor. Place the decoupling capacitor Ci in a group of 1, 2, or 3 balls; the total must be equal to the  
decoupling requirement. In case you interconnect powers, first insert the decoupling capacitor and then interconnect the powers.  
(2) The decoupling capacitor value depends on the board characteristics.  
Figure 3-2. Power Supply Decoupling  
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3.5 Power-up and Power-down  
This section provides the timing requirements for the AM3517/05 hardware signals.  
3.5.1 Power-up Sequence  
The following steps give an example of power-up sequence supported by the AM3517/05.  
1. IO 1.8V supply (VDDS), Band-gap and LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU)  
and oscillator supply (VDDSOSC) should come up first to a stable state.  
2. IO 3.3V (VDDSHV) supply should be ramped up next to a stable state.  
3. Core (VDD_CORE) supply follows next to a stable state.  
4. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) and 1.8 V complex  
IO supplies (VDDA_DAC, VDDA1P8V_USBPHY) should be ramped up next to a stable state.  
5. Finally, 3.3 V complex IO (VDDA_3P3V_USBPHY) should be ramped up.  
6. sys_nrespwron must be held low at the time the power supplies are ramped up till the time the  
sys_32k and sys_xtalin clocks are stable.  
Note: In VDDSHV 1.8 V operation mode, VDDSHV can be grouped and powered up together with VDDS,  
VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU and VDDSOSC.  
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Figure 3-3 shows the power-up sequence.  
1.8V  
VDDS, VDDS_SRAM_CORE_BG  
VDDS_SRAM_MPU,  
VDDSOSC  
3.3V  
VDDSHV  
1.2V  
VDD_CORE  
sys_nrespwron  
sys_32k  
sys_xtalin  
VDDS_DPLL_PER_CORE,  
VDDS_DPLL_MPU_USBHOST,  
VDDA_DAC,  
1.8V  
VDDA1P8V_USBPHY  
3.3V  
VDDA3P3V_USBPHY  
Figure 3-3. Power-up Sequence  
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3.5.2 Power-down Sequence  
The AM3517/05 device proceeds with the power-down sequence shown below.  
The following steps give an example of the power-down sequence supported by the AM3517/05  
device.  
1. Reset AM3517/05 device.  
2. Stop all signals driven to AM3517/05.  
3. Option 1: Power down all domains simutaneously.  
4. Option 2: If all domains cannot be powered down simultaneously, follow the below sequence:  
(a) Power off all complex I/O domains  
(b) Power off core domain (VDD_CORE)  
(c) Power off all PLL domains (VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE)  
(d) Power off all SRAM LDOs  
(e) Power off all standard I/O domains (VDDS and VDDSHV)  
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4 Clock Specifications  
The AM3517/05 device has three external input clocks, a low frequency (sys_32k), a high frequency  
(sys_xtalin), and an optional (sys_altclk). The AM3517/05 device has two configurable output clocks,  
sys_clkout1 and sys_clkout2.  
Figure 4-1 shows the interface to the external clock sources and clock outputs.  
Microprocessor  
sys_32k  
Power IC  
Alternate Clock Source Selectable (54, 48 MHz or other [up  
to 59 MHz])  
sys_altclk  
rmii_50mhz_clk  
sys_clkout1  
Ethernet input 50-MHz clock  
To Peripherals (From OSC_CLK: 26 MHz)  
To Peripherals (From OSC_CLK: 26 MHz, core_clk  
[DPLL, up to 166 MHz], DPLL-96 MHZ or DPLL-54 MHz  
outputs with a divider of 1, 2, 4, 8, or 16)  
sys_clkout2  
sys_xtalout  
To Quartz (Oscillator output) or Unconnected  
sys_xtalin  
sys_clkreq  
sys_xtalout  
sys_xtalin  
From Quartz (Oscillator input), Square Clock, or Crystal  
Clock Request. To Square Clock Source or from Peripherals  
sys_xtalout  
Unconnected  
Oscillator  
is Bypassed  
Oscillator  
is Used  
sys_xtalin  
Square  
Clock  
Source  
sys_clkreq  
sys_clkreq  
GPin  
Figure 4-1. Clock Interface  
The AM3517/05 device operation requires the following three input clocks:  
•
The 32-kHz clock can be generated using one of the following options and can be selected via the  
sys_boot7 pin. See Figure 4-2.  
–
–
External: Supplied by an oscillator on the sys_32k pin.  
Internal: 32-kHz clock generation using a fixed divider on the HS system clock (26MHz).  
•
•
The system alternative clock can be used (through the sys_altclk pin) to provide alternative 48 or 54  
MHz or other clock source (up to 54 MHz).  
The system clock input (26 MHz) is used to generate the main source clock of the AM3517/05 device.  
It supplies the DPLLs as well as several AM3517/05 modules. The system clock input can be  
connected to either:  
–
A crystal oscillator clock managed by sys_xtalin and sys_xtalout. In this case, the sys_clkreq is  
used as an input (GPIN).  
–
A CMOS digital clock through the sys_xtalin pin. In this case, the sys_clkreq is used as an output to  
request the external system clock.  
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0
1
Sys_32k  
Sys_32k_in  
Fixed  
Divider  
/800  
32.5 kHz  
Sys_clk=  
26 MHz  
Sys_xtalin  
Sys_xtalout  
Sys_boot7  
Latch  
0
1
JTAG Overrides  
for DFT  
1
Sys_clk  
PowerOn Reset  
Figure 4-2. 32-kHz Clock Generation  
The AM3517/05 outputs externally two clocks:  
•
•
sys_clkout1 can output the oscillator clock (26 MHz) at any time.  
sys_clkout2 can output the oscillator clock, core_clk, 96 MHz or 54 MHz. It can be divided by 2, 4, 8,  
or 16 and its off state polarity is programmable.  
4.1 Oscillator  
The sys_xtalin (26 MHz) oscillator provides the primary reference clock for the device. The on-chip  
oscillator requires an external crystal connected across the sys_xtalin and sys_xtalout pins, along with two  
load capacitors, as shown in Figure 4-3. The external crystal load capacitors must be connected only to  
the oscillator ground pin (VSSOSC). Do not connect to board ground (VSS).  
Note: If an external oscillator is to be used, the external oscillator clock signal should be connected to the  
sys_xtalin pin with a 1.8V amplitude. The sys_xtalout should be left unconnected and the VSSOSC signal  
should be connected to board ground (VSS).  
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sys_xtalout  
VSSOSC  
sys_xtalin  
Crystal  
26 MHz  
C1  
C2  
A. Oscillator components (Crystal, C1, C2) must be located close to the AM35x package. Parasitic capacitance to the  
printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled into the oscillator.  
The VSSOSC terminal provides a Kelvin ground reference for the external crystal components. External crystal  
component grounds should only be connected to the VSSOSC terminal and should not be connected to the PCB  
ground plane.  
B. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components  
(excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to  
provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL  
=
[(C1*C2)/(C1+C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer  
plus any mutual capacitance (Cpkg + CPCB) seen across the AM3517/05 sys_xtalin and sys_xtalout signals. For  
recommended values of crystal circuit components, see Table 4-1.  
Figure 4-3. AM3517/05 Oscillator Connections  
Table 4-1. Crystal Electrical Characteristics  
PARAMETER  
MIN  
TYP  
26  
MAX  
UNIT  
MHz  
Ω
Oscillation frequency  
Crystal ESR  
50  
Frequency stability  
+/- 50  
20  
ppm  
pF  
Parallel Load Capacitance  
(C1 and C2)  
Shunt Capacitance  
5
pF  
4.2 Input Clock Specifications  
The clock system accepts three input clock sources:  
•
•
•
32-kHz digital CMOS clock  
Crystal oscillator clock or CMOS digital clock (26 MHz)  
Alternate clock (48 or 54 MHz, or other up to 54 MHz)  
Table 4-2. 26-MHz SYS_CLK Input Clock Timing Requirements  
PARAMETER  
f(xtalin)  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
Frequency, sys_xtalin  
26  
MHz  
%
tw(xtalin)  
Duty Cycle,  
sys_xtalin  
45  
-1  
55  
tj(xtalin)  
tt(xtalin)  
Jitter, sys_xtalin  
1
5
%
Transition time,  
sys_xtalin  
ns  
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Table 4-3. 32-kHz Input Clock Source Electrical Characteristics  
PARAMET  
ER  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
f
Frequency, sys_32k  
Input capacitance  
Input resistance  
32.768  
kHz  
pF  
Ci  
Ri  
0.45  
106  
0.25  
GΩ  
Table 4-4 details the input requirements of the 32-kHz input clock.  
Table 4-4. 32-kHz Input Clock Source Timing Requirements(1)  
PARAMETE  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
R
1 / tc(32k)  
tR(32k)  
Frequency, sys_32k  
32  
kHz  
ns  
Rise transition time, sys_32k  
Fall transition time, sys_32k  
Frequency stability, sys_32k  
20  
20  
tF(32k)  
ns  
tJ(32k)  
+/-200  
ppm  
(1) See Electrical Characteristics for Standard LVCMOS IOs part for sys_32k VIH/VIL parameters.  
Table 4-5. 48-MHz, 54-MHz, or up to 59-MHz Input Clock Source Electrical Characteristics  
NAME  
DESCRIPTION  
Frequency , sys_altclk  
MIN  
MAX  
UNIT  
MHz  
pF  
f
48, 54, or up to 59  
Ci  
Ri  
Input capacitance  
Input resistance  
0.74  
106  
0.25  
GΩ  
Table 4-6 details the input requirements of the 48- or 54-MHz input clock.  
Table 4-6. 48-MHz, 54-MHz, or up to 59-MHz Input Clock Source Timing Requirements(1) (2)  
PARAMETER  
DESCRIPTION  
Frequency, sys_altclk  
MIN  
MAX  
UNIT  
MHz  
%
1 / tc(sys_altclk)  
tw(sys_altclk)  
tj(sys_altclk)  
tr(sys_altclk)  
tf(sys_altclk)  
ft(sys_altclk)  
48, 54, or up to 59  
Duty cycle  
45  
-1  
60  
1
Jitter  
%
Rise transition time  
Fall transition time  
Frequency tolerance  
10  
10  
50  
ns  
ns  
-50  
ppm  
(1) Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300  
period samples. The sinusoidal noise is added on top of the vdds supply voltage.  
(2) See Section 3, Electrical Characteristics, for sys_altclk VIH/VIL parameters.  
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4.3 Output Clock Specifications  
Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available:  
•
sys_clkout1 can output the oscillator clock (26 MHz) at any time. It can be controlled by software or  
externally using sys_clkreq control. When the device is in the off state, the sys_clkreq can be asserted  
to enable the oscillator and activate the sys_clkout1 without waking up the device. The off state polarity  
of sys_clkout1 is programmable.  
•
sys_clkout2 can output sys_clk (26 MHz), core_clk (core DPLL output), APLL-96 MHz, or APLL-54  
MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is programmable. This output is active  
only when the core domain is active.  
Table 4-7 summarizes the sys_clkout1 output clock electrical characteristics.  
Table 4-7. SYS_CLKOUT1 Output Clock Electrical Characteristics  
NAME  
DESCRIPTION  
MIN  
TYP  
26  
MAX  
UNIT  
MHz  
pF  
f
Frequency  
Load capacitance(1)  
CI  
f(max) = 38.4 MHz  
f(max) = 26 MHz  
70  
125  
(1) The load capacitance is adapted to a frequency.  
Table 4-8 details the sys_clkout1 output clock timing characteristics.  
Table 4-8. SYS_CLKOUT1 Output Clock Switching Characteristics  
NAME  
DESCRIPTION  
Frequency  
MIN  
TYP  
MAX  
UNIT  
MHz  
ns  
f
1 / CO0  
26  
CO1  
tw(CLKOUT1)  
Pulse duration, sys_clkout1 low or high  
0.40 *  
0.60 *  
tc(CLKOUT1)  
tc(CLKOUT1)  
CO2  
CO3  
tR(CLKOUT1)  
tF(CLKOUT1)  
Rise time, sys_clkout1(1)  
Fall time, sys_clkout1(1)  
3.31  
ns  
ns  
3.31  
(1) With a load capacitance of 25 pF.  
CO0  
CO1  
CO1  
sys_clkout1  
030-014  
Figure 4-4. SYS_CLKOUT1 System Output Clock  
Table 4-9 summarizes the sys_clkout2 output clock electrical characteristics.  
Table 4-9. SYS_CLKOUT2 Output Clock Electrical Characteristics  
NAME  
DESCRIPTION  
Frequency, sys_clkout2(1)  
Load capacitance(2)  
MIN  
TYP  
MAX  
166  
12  
UNIT  
MHz  
pF  
f
CL  
f(max) = 166 MHz  
2
8
(1) The maximum frequency supported is core_clk/2 MHz.  
(2) The load capacitance is adapted to a frequency.  
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Table 4-10 details the sys_clkout2 output clock timing characteristics.  
Table 4-10. SYS_CLKOUT2 Output Clock Switching Characteristics  
NAME  
DESCRIPTION  
Frequency  
MIN  
TYP  
MAX  
UNIT  
MHz  
ns  
f
1 / CO0  
166  
CO1  
CO2  
CO3  
tw(CLKOUT2)  
tR(CLKOUT2)  
tF(CLKOUT2)  
Pulse duration, sys_clkout2 low or high  
Rise time, sys_clkout2(1)  
Fall time, sys_clkout2(1)  
0.40 * tc(CLKOUT2)  
0.60 * tc(CLKOUT2)  
3.7  
4.3  
ns  
ns  
(1) With a load capacitance of 25 pF.  
CO0  
CO1  
CO1  
sys_clkout2  
030-015  
Figure 4-5. SYS_CLKOUT2 System Output Clock  
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4.4 DPLL Specifications  
The AM3517/05 integrates four DPLLs. The PRM and CM drive them.  
The four main DPLLs are:  
•
•
•
•
DPLL1 (MPU)  
DPLL3 (Core)  
DPLL4 (Peripherals)  
DPLL5 (Second Peripherals DPLL)  
Figure 4-6 illustrates the DPLL implementation.  
Device  
VDDS_DPLL_MPU_USBHOST Power Rail  
DPLL1  
DPLL3  
DPLL4  
DPLL5  
VDDS_DPLL_PER_CORE  
030-016  
Figure 4-6. DPLL Implementation  
4.4.1 Digital Phase-Locked Loop (DPLL)  
The DPLL provides all interface clocks and some functional clocks (such as the processor clocks) of the  
AM3517/05 device.  
DPLL1 gets an always-on clock used to produce the synthesized clock. They get a high-speed bypass  
clock used to switch the DPLL output clock on this high-speed clock during bypass mode.  
The high-speed bypass clock is an L3 divided clock (programmable by 1 or 2) that saves DPLL processor  
power consumption when the processor does not need to run faster than the L3 clock speed, or optimizes  
performance during frequency scaling.  
Each DPLL synthesized frequency is set by programming M (multiplier) and N (divider) factors. In addition,  
all DPLL outputs can be controlled by an independent divider (M2 to M6).  
The clock generating DPLLs of the AM3517/05 device have following features:  
•
•
•
•
Independent power domain per DPLL  
Controlled by clock-manager (CM)  
Fed with always-on system clock with independent gating control per DPLL  
Analog part supplied through dedicated power supply (1.8 V) and an embedded LDO to get rid of 1-  
MHz noise  
•
Up to four independent output dividers for simultaneous generation of multiple clock frequencies  
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4.4.1.1 DPLL1 (MPU)  
DPLL1 is located in the MPU subsystem and supplies all clocks of the subsystem. All MPU subsystem  
clocks are internally generated in the subsystem. When the core domain is on, it can use the DPLL3  
(CORE DPLL) output as a high-frequency bypass input clock.  
4.4.1.2 DPLL3 (CORE)  
DPLL3 supplies all interface clocks and also a few module functional clocks. It can be also source of the  
emulation trace clock. It is located in the core domain area. All interface clocks and a few module  
functional clocks are generated in the CM. When the core domain is on, it can be used as a bypass input  
to DPLL1.  
4.4.1.3 DPLL4 (Peripherals)  
DPLL4 generates clocks for the peripherals. It supplies five clock sources: 96-MHz functional clocks to  
subsystems and peripherals, 54 MHz to TV DAC, display functional clock, camera sensor clock, and  
emulation trace clock. It is located in the core domain area. All interface clocks and few module functional  
clocks are generated in the CM. Its outputs to the DSS, PER, and EMU domains are propagated with  
always-on clock trees.  
4.4.1.4 DPLL5 (Second peripherals DPLL)  
DPLL5 supplies the 120-MHz functional clock to the CM.  
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4.4.2 DPLL Noise Isolation  
The DPLL requires dedicated power supply pins to isolate the core analog circuit from the switching noise  
generated by the core logic that can cause jitter on the clock output signal. Guard rings are added to the  
cell to isolate it from substrate noise injection.  
The vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the  
supply rails. The maximum input noise level allowed is 30 mVPP for frequencies below 1 MHz.  
Figure 4-7 illustrates an example of a noise filter.  
Noise Filter  
VDDS_DPLL_MPU_USBHOST  
C
DPLL_MPU  
DLL  
DPLL_CORE  
Noise Filter  
VDDS_DPLL_PER_CORE  
C
DPLL5  
DPLL4  
030-017  
Figure 4-7. DPLL Noise Filter  
Table 4-11 specifies the noise filter requirements.  
Table 4-11. DPLL Noise Filter Requirements  
NAME  
MIN  
TYP  
MAX  
UNIT  
Filtering capacitor  
100  
nF  
(1) The capacitors must be inserted between power and ground as close as possible.  
(2) This circuit is provided only as an example.  
(3) The filter must be located as close as possible to the device.  
(4) No filtering required if noise is below 10 mVPP  
.
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5 Video DAC Specifications  
A dual-display interface equips the AM3517/05 processor. This display subsystem provides the necessary  
control signals to interface the memory frame buffer directly to the external displays (TV-set). Two (one  
per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to generate the  
video analog signal. One of the video DACs also includes TV detection and power-down mode. Figure 5-1  
illustrates the AM3517/05 DAC architecture.  
Device  
TV DCT  
tv_vfb1  
DIN1[9:0]  
TVOUT  
BUFFER  
Video DAC 1  
tv_out1  
DSS  
tv_vfb2  
DIN2[9:0]  
TVOUT  
BUFFER  
Video DAC 2  
tv_out2  
V_ref  
vdda_dac  
vssa_dac  
tv_vref  
CBG  
030-018  
Figure 5-1. Video DAC Architecture  
The following paragraphs detail the 10-bit DAC interface pinout, static and dynamic specifications, and  
noise requirements. The operating conditions and absolute maximum ratings are detailed in Table 5-2 and  
Table 5-4.  
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5.1 Interface Description  
Table 5-1 summarizes the external pins of the video DAC.  
Table 5-1. External Pins of 10-bit Video DAC  
PIN NAME  
I/O  
DESCRIPTION  
tv_out1  
O
TV analog output composite  
DAC1 video output. An external resistor is connected between this  
node and tv_vfb1. The nominal value of ROUT1 is 1650 . Finally, note  
that this is the output node that drives the load (75 ).  
tv_out2  
O
TV analog output S-VIDEO  
DAC2 video output. An external resistor is connected between this  
node and tv_vfb2. The nominal value of ROUT2 is 1650 . Finally, note  
that this is the output node that drives the load (75 ).  
tv_vref  
tv_vfb1  
tv_vfb2  
I
Reference output voltage from internal  
bandgap  
A decoupling capacitor (CBG) needs to be connected for optimum  
performance.  
O
O
Amplifier feedback node  
Amplifier feedback node. An external resistor is connected between  
this node and tv_out1. The nominal value of ROUT1 is 1650 (1%).  
Amplifier feedback node  
Amplifier feedback node. An external resistor is connected between  
this node and tv_out2. The nominal value of ROUT2 is 1650 (1%).  
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5.2 Electrical Specifications Over Recommended Operating Conditions  
(TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650Ω , RLOAD = 75Ω , unless otherwise noted)  
Table 5-2. DAC Static Electrical Specification  
PARAMETER  
Resolution  
DC ACCURACY  
CONDITIONS/ASSUMPTIONS  
MIN  
TYP  
MAX  
UNIT  
R
10  
Bits  
INL(1)  
DNL(2)  
Integral nonlinearity  
1
1
1
1
LSB  
LSB  
Differential nonlinearity  
ANALOG OUTPUT  
-
Full-scale output voltage  
RLOAD = 75Ω  
0,7  
0.88  
50  
1
V
-
Output offset voltage  
Output offset voltage drift  
Gain error  
mV  
-
20  
mV/C  
% FS  
-
17  
19  
RVOUT  
Output impedance  
67.5  
75  
82.5  
REFERENCE  
VREF  
-
Reference voltage range  
Reference noise density  
0.525  
3700  
0.55  
129  
0.575  
4200  
V
100-kHz reference noise  
bandwidth  
RSET  
PSRR  
Full-scale current adjust resistor  
Reference PSRR(3) (Up to 6 MHz)  
4000  
40  
dB  
POWER CONSUMPTION  
Ivdda-up  
Analog Supply Current(4)  
-
2 channels, no load  
2 channels  
8
mA  
mA  
Analog supply driving a 75- load  
(RMS)  
50  
Ivdda-up (peak) Peak analog supply current:  
Lasts less than 1 ns  
60  
2
mA  
mA  
Ivdd-up  
Digital supply current(5)  
Measured at fCLK = 54 MHz, fOUT  
= 2 MHz sine wave, vdd = 1.3 V  
Ivdd-up (peak)  
Ivdda-down  
Ivdd-down  
Peak digital supply current(6)  
Analog power at power-down  
Digital power at power-down  
Lasts less than 1 ns  
T = 30C, vdda = 1.8 V  
T = 30C, vdd = 1.3 V  
2.5  
1.5  
1
mA  
mA  
mA  
(1) The INL is measured at the output of the DAC (accessible at an external pin during bypass mode).  
(2) The DNL is measured at the output of the DAC (accessible at an external pin during bypass mode).  
(3) Assuming a capacitor of 0.1 F at the tv_ref node.  
(4) The analog supply current Ivdda is directly proportional to the full-scale output current IFS and is insensitive to fCLK  
(5) The digital supply current IVDD is dependent on the digital input waveform, the DAC update rate fCLK, and the digital supply VDD.  
(6) The peak digital supply current occurs at full-scale transition for duration less than 1 ns.  
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(TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650 , RLOAD = 75 , unless otherwise noted)  
Table 5-3. Video DAC Dynamic Electrical Specification  
PARAMETER  
Output update rate  
Clock jitter  
CONDITIONS/ASSUMPTIONS  
MIN  
TYP  
MAX  
UNIT  
MHz  
ps  
(1)  
fCLK  
Equal to input clock frequency  
54  
rms clock jitter required in order to assure 10-  
bit accuracy  
40  
Attenuation at 5.1 MHz  
Attenuation at 54 MHz(1)  
Output settling time  
Corner frequency for signal  
Image frequency  
0.1  
25  
0.5  
30  
85  
1.5  
33  
dB  
dB  
ns  
tST  
Time from the start of the output transition to  
output within 1 LSB of final value.  
tRout  
tFout  
BW  
Output rise time  
Output fall time  
Measured from 10% to 90% of full-scale  
transition  
25  
25  
ns  
ns  
Measured from 10% to 90% of full-scale  
transition  
Signal bandwidth  
Differential gain(2)  
Differential phase(2)  
Within bandwidth  
6
1.5%  
1
MHz  
deg.  
dB  
SFDR  
SNR  
fCLK = 54 MHz, fOUT = 1 MHz  
fCLK = 54 MHz, fOUT = 1 MHz  
45  
55(3)  
Signal-to-noise ratio  
dB  
1 kHz to 6 MHz bandwidth  
PSRR  
Power supply rejection ratio Up to 6 MHz  
20(4)  
50  
dB  
dB  
Crosstalk Between the two video  
channels  
40  
(1) For internal input clock information, For more information, see the Device Display Interface Subsystem Reference Guide [literature  
number SPRUFV2].  
(2) The differential gain and phase value is for dc coupling. Note that there is degradation for the ac coupling.  
(3) The SNR value is for dc coupling. Note that there is a 6-dB degradation for ac coupling.  
(4) The PSSR value is for dc coupling. Note that there is a 10-dB degradation for ac coupling.  
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5.3 Analog Supply (vdda_dac) Noise Requirements  
In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the  
noise requirements stated in this section.  
The DAC Power Supply Rejection Ratio is defined as the relative variation of the full-scale output current  
divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per volt of  
DIOUT  
100×  
IOUTFS  
% FSR  
PSRRDAC  
=
V
VAC  
supply variation as shown in the following equation:  
Depending on frequency, the PSRR is defined in Table 5-4.  
Table 5-4. Video DAC Power Supply Rejection Ratio  
Supply Noise Frequency  
PSRR % FSR/V  
0 to 100 kHz  
> 100 kHz  
1
The rejection decreases 20 dB/dec.  
Example: at 1 MHz the PSRR is 10% of FSR/V  
A graphic representation is shown in Figure 5-2.  
PSRR (% FSR/V)  
First pole of  
DAC output load  
10  
1
f
1 MHz  
100 kHz  
030-019  
Figure 5-2. Video DAC Power Supply Rejection Ratio  
To ensure that the DAC SFDR specification is met, the PSRR values and the clock jitter requirements  
translate to the following limits on vdda_dac (for the Video DAC).  
The maximum peak-to-peak noise on vdda (ripple) is defined in Table 5-5:  
Table 5-5. Video DAC Maximum Peak-to-Peak Noise on vdda_dac  
Tone Frequency  
0 to 100 kHz  
> 100 kHz  
Maximum Peak-to-Peak Noise on vdda_dac  
< 30 mVpp  
Decreases 20 dB/dec.  
Example: at 1 MHz the maximum is 3 mVpp  
The maximum noise spectral density (white noise) is defined in Table 5-6:  
Table 5-6. Video DAC Maximum Noise Spectral Density  
Supply Noise Bandwidth  
0 to 100 kHz  
Maximum Supply Noise Density  
< 20 V / Hz  
> 100 kHz  
Decreases 20 dB/dec.  
Example: at 1 MHz the maximum noise density is 2 / Hz  
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Because the DAC PSRR deteriorates at a rate of 20 dB/dec after 100 kHz, it is highly recommended to  
have vdda_dac low pass filtered (proper decoupling) (see the illustrated application: Section 5.4, External  
Component Value Choice).  
5.4 External Component Value Choice  
The full-scale output voltage VOUTMAX is regulated by the reference amplifier, and is set by an internal  
resistor RSET. IOUTMAX can be expressed as:  
IOUTMAX = IREF /8 * (63 + 15/16)  
(1)  
Where:  
VREF = 0.5V  
IREF = VREF/RSET  
(2)  
(3)  
The output current IOUT appearing at DAC output is a function of both the input code and IOUTMAX and can  
be expressed as:  
IOUT = (DAC_CODE/1023) * IOUTMAX  
(4)  
(5)  
(6)  
Where:  
DAC_CODE = 0 to 1023 is the DAC input code in decimal.  
The output voltage is:  
VOUT = IOUT *N* RCABLE  
Where:  
(N = amplifier gain = 21)  
(7)  
(8)  
RCABLEΩ (cable typical impedance)  
The TV-out buffer requires a per channel external resistors: ROUT1/2. The equation below can be used to  
select different resistor values (if necessary):  
ROUT = (N+1) RCABLE = 1650Ω  
(9)  
Recommended parameter values are:  
Table 5-7. Video DAC Recommended External Components Values  
Recommended Value  
UNIT  
nF  
CBG  
100  
ROUT1/2  
1650  
Ω
In order to limit the reference noise bandwidth and to suppress transients on VREF, it is necessary to  
connect a large decoupling capacitor ©BG) between the tv_vref and vssa_dac pins.  
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6 Timing Requirements and Switching Characteristics  
Note: The timing data shown is preliminary data and is subject to change in future revisions.  
6.1 Timing Test Conditions  
All timing requirements and switching characteristics are valid over the recommended operating conditions  
of Table 3-3, unless otherwise specified.  
6.2 Interface Clock Specifications  
6.2.1 Interface Clock Terminology  
The Interface clock is used at the system level to sequence the data and/or control transfers accordingly  
with the interface protocol.  
6.2.2 Interface Clock Frequency  
The two interface clock characteristics are:  
•
•
The maximum clock frequency  
The maximum operating frequency  
The interface clock frequency documented in this document is the maximum clock frequency, which  
corresponds to the maximum frequency programmable on this output clock. This frequency defines the  
maximum limit supported by the AM3517/05 IC and doesn't take into account any system consideration  
(PCB, peripherals).  
The system designer will have to consider these system considerations and AM3517/05 IC timings  
characteristics as well, to define properly the maximum operating frequency, which corresponds to the  
maximum frequency supported to transfer the data on this interface.  
6.2.3 Clock Jitter Specifications  
Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this  
document is the time difference between the typical cycle period and the actual cycle period affected by  
noise sources on the clock. The cycle (or period) jitter terminology identifies this type of jitter.  
Cycle (or Period) Jitter  
Tn-1  
Tn  
Tn+1  
Max. Cycle Jitter = Max (Ti)  
Min. Cycle Jitter = Min (Ti)  
Jitter Standard Deviation (or rms Jitter) = Standard Deviation (Ti)  
030-020  
Figure 6-1. Cycle (or Period) Jitter  
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6.2.4 Clock Duty Cycle Error  
The maximum duty cycle error is the difference between the absolute value of the maximum high-level  
pulse duration or the maximum low-level pulse duration and the typical pulse duration value:  
•
•
Maximum pulse duration = typical pulse duration + maximum duty cycle error  
Minimum pulse duration = typical pulse duration - maximum duty cycle error  
6.3 Timing Parameters  
The timing parameter symbols used in the timing requirement and switching characteristic tables are  
created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other  
related terminologies have been abbreviated as follows:  
Table 6-1. Timing Parameters  
LOWERCASE SUBSCRIPTS  
Symbols  
Parameter  
Cycle time (period)  
Delay time  
c
d
dis  
en  
h
Disable time  
Enable time  
Hold time  
su  
START  
t
Setup time  
Start bit  
Transition time  
Valid time  
v
w
Pulse duration (width)  
Unknown, changing, or dont care level  
High  
X
H
L
Low  
V
Valid  
IV  
AE  
FE  
LE  
Z
Invalid  
Active Edge  
First Edge  
Last Edge  
High impedance  
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6.4 External Memory Interfaces  
The AM3517/05 processor includes the following external memory interfaces:  
•
•
General-purpose memory controller (GPMC)  
SDRAM controller (SDRC)  
6.4.1 General-Purpose Memory Controller (GPMC)  
The GPMC is the AM3517/05 unified memory controller used to interface external memory devices such  
as:  
•
•
•
Asynchronous SRAM-like memories and ASIC devices  
Asynchronous page mode and synchronous burst NOR flash  
NAND flash  
6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing  
The following tables assume testing over the recommended operating conditions and electrical  
characteristic conditions.  
Table 6-2. GPMC/NOR Flash Synchronous Mode Timing Conditions  
TIMING CONDITION PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
Input Conditions  
tR  
Input signal rise time  
Input signal fall time  
0.3  
0.3  
1.8  
1.8  
ns  
ns  
tF  
Output Conditions  
CLOAD  
Output load capacitance  
30  
pF  
Table 6-3. GPMC/NOR Flash Interface Timing Requirements Synchronous Mode  
NO.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
F12  
tsu(DV-CLKH)  
Setup time, read gpmc_d[15:0] valid before  
gpmc_clk high  
2.021  
ns  
F13  
F21  
th(CLKH-DV)  
Hold time, gpmc_d[15:0] valid after gpmc_clk high  
Setup time, gpmc_waitx(1) valid before gpmc_clk  
high  
3.403  
3.782  
ns  
ns  
tsu(WAITV-CLKH)  
F22  
th(CLKH-WAITV)  
Hold Time, gpmc_waitx(1) valid after gpmc_clk  
high  
3.343  
ns  
(1) Wait monitoring support is limited to a WaitMonitoringTime value > 0.  
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Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
F0  
F1  
F1  
tc(CLK)  
Cycle time(1), output clock gpmc_clk  
period  
10  
ns  
ns  
ns  
tw(CLKH)  
tw(CLKL)  
Typical pulse duration, output clock  
gpmc_clk high  
0.5 P(2)  
0.5 P(2)  
-500  
0.5 P(2)  
0.5 P(2)  
Typical pulse duration, output clock  
gpmc_clk low  
tdc(CLK)  
tj(CLK)  
Duty cycle error, output clk gpmc_clk  
Jitter standard deviation(3), output clock  
gpmc_clk  
500  
ps  
ps  
33.30  
tR(CLK)  
Rise time, output clock gpmc_clk  
Fall time, output clock gpmc_clk  
Rise time, output data  
1.6  
1.6  
2
ns  
ns  
ns  
ns  
ns  
tF(CLK)  
tR(DO)  
tF(DO)  
Fall time, output data  
2
F2  
F3  
F4  
F5  
F6  
F7  
td(CLKH-nCSV)  
Delay time, gpmc_clk rising edge to  
gpmc_ncsx(4) transition  
F(5) - 1.9  
E(6) - 1.9  
B(7) - 4.1  
-2.103  
F(5) + 3.3  
E(6) + 3.3  
B(7) + 2.1  
td(CLKH-nCSIV)  
td(ADDV-CLK)  
td(CLKH-ADDIV)  
td(nBEV-CLK)  
Delay time, gpmc_clk rising edge to  
gpmc_ncsx(4) invalid  
ns  
ns  
ns  
ns  
ns  
Delay time, address bus valid to  
gpmc_clk first edge  
Delay time, gpmc_clk rising edge to  
gpmc_a[16:1] invalid  
Delay time, gpmc_nbe0_cle, gpmc_nbe1  
valid to gpmc_clk first edge  
B(7) - 1.37  
D(8) - 2.1  
B(7) + 2.1  
D(8) + 1.1  
td(CLKH-nBEIV)  
Delay time, gpmc_clk rising edge to  
gpmc_nbe0_cle, gpmc_nbe1 invalid  
(1) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the I/F module by setting the  
GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.  
(2) P = gpmc_clk period  
(3) The jitter probability density can be approximated by a Gaussian function.  
(4) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
(5) For nCS falling edge (CS activated):  
•
Case GpmcFCLKDivider = 0:  
F = 0.5 * CSExtraDelay * GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
•
•
•
F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are  
even)  
•
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise  
•
Case GpmcFCLKDivider = 2:  
•
•
•
F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 3)  
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)  
F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)  
(6) For single read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
For burst read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
For burst write: E = (CSWrOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
(7) B = ClkActivationTime * GPMC_FCLK  
(8) For single read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
For burst read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
For burst write: D = (WrCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
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Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode (continued)  
NO.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
F8  
td(CLKH-nADV)  
td(CLKH-nADVIV)  
td(CLKH-nOE)  
Delay time, gpmc_clk rising edge to  
gpmc_nadv_ale transition  
G(9) - 1.9  
G(9) + 4.1  
D(8) + 4.1  
H(10) + 2.1  
E(6) + 2.1  
ns  
ns  
ns  
ns  
F9  
Delay time, gpmc_clk rising edge to  
gpmc_nadv_ale invalid  
D(8) - 1.9  
H(10) - 2.1  
E(6) - 2.1  
F10  
F11  
Delay time, gpmc_clk rising edge to  
gpmc_noe transition  
td(CLKH-nOEIV)  
Delay time, gpcm rising edge to  
gpmc_noe invalid  
(9) For ADV falling edge (ADV activated):  
•
Case GpmcFCLKDivider = 0:  
G = 0.5 * ADVExtraDelay * GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
•
•
•
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime  
are even)  
•
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise  
•
Case GpmcFCLKDivider = 2:  
•
•
•
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime - ClkActivationTime) is a multiple of 3)  
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)  
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime --ClkActivationTime - 2) is a multiple of 3)  
For ADV rising edge (ADV deactivated) in Reading mode:  
•
Case GpmcFCLKDivider = 0:  
G = 0.5 * ADVExtraDelay * GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
•
•
•
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and  
ADVRdOffTime are even)  
•
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise  
•
Case GpmcFCLKDivider = 2:  
•
•
•
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)  
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime --ClkActivationTime --1) is a multiple of 3)  
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime --ClkActivationTime - 2) is a multiple of 3)  
For ADV rising edge (ADV deactivated) in Writing mode:  
•
Case GpmcFCLKDivider = 0:  
G = 0.5 * ADVExtraDelay * GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
•
•
•
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and  
ADVWrOffTime are even)  
•
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise  
•
Case GpmcFCLKDivider = 2:  
•
•
•
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)  
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)  
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)  
(10) For OE falling edge (OE activated) / IO DIR rising edge (Data Bus input direction):  
•
Case GpmcFCLKDivider = 0:  
H = 0.5 * OEExtraDelay * GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
•
•
•
H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are  
even)  
•
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise  
•
Case GpmcFCLKDivider = 2:  
•
•
•
H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 3)  
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)  
H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)  
For OE rising edge (OE deactivated):  
•
GpmcFCLKDivider = 0:  
H = 0.5 * OEExtraDelay * GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
•
•
•
H = 0.5 * OEExtraDelay * GPMC_FC if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are  
even)  
•
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise  
•
Case GpmcFCLKDivider = 2:  
•
•
•
H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 3)  
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)  
H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)  
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Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode (continued)  
NO.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
F14  
F15  
F17  
F18  
td(CLKH-nWE)  
td(CLKH-Data)  
td(CLKH-nBE)  
tW(nCSV)  
Delay time, gpmc_clk rising edge to  
gpmc_nwe transition  
I(11) - 1.9  
I(11) + 4.1  
J(12) + 1.1  
J(12) + 1.1  
ns  
ns  
ns  
Delay time, gpmc_clk rising edge to data  
bus transition  
J(12) - 2.1  
J(12) - 2.1  
Delay time, gpmc_clk rising edge to  
gpmc_nbex_cle transition  
Pulse duration,  
Read  
Write  
Read  
Write  
A(13)  
A(13)  
C(14)  
C(14)  
ns  
ns  
ns  
ns  
gpmc_ncsx(4) low  
F19  
F20  
tW(nBEV)  
Pulse duration,  
gpmc_nbe0_cle,  
gpmc_nbe1 low  
tW(nADVV)  
Pulse duration,  
gpmc_nadv_ale low  
Read  
Write  
K(15)  
K(15)  
H(10) - 2.1  
ns  
ns  
ns  
F23  
F24  
td(CLKH-IODIR)  
Delay time, gpmc_clk rising edge to  
gpmc_io_dir high (IN direction)  
H(10) + 4.1  
M(16) + 4.1  
td(CLKH-IODIRIV)  
Delay time, gpmc_clk rising edge to  
gpmc_io_dir low (OUT direction)  
M(16) - 2.1  
ns  
(11) For WE falling edge (WE activated):  
•
Case GpmcFCLKDivider = 0:  
I = 0.5 * WEExtraDelay * GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
•
•
•
I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are  
even)  
•
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise  
•
Case GpmcFCLKDivider = 2:  
•
•
•
I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 3)  
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime --ClkActivationTime - 1) is a multiple of 3)  
I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)  
For WE rising edge (WE deactivated):  
•
Case GpmcFCLKDivider = 0:  
I = 0.5 * WEExtraDelay * GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
•
•
•
I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are  
even)  
•
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise  
•
Case GpmcFCLKDivider = 2:  
•
•
•
I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 3)  
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)  
I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)  
(12) J = GPMC_FCLK period  
(13) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period  
For burst read: A = (CSRdOffTime - CSOnTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period  
For burst write: A = (CSWrOffTime - CSOnTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period  
with n being the page burst access number.  
(14) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK  
For burst read: C = (RdCycleTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
For burst write: C = (WrCycleTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n being the page  
burst access number.  
(15) For read: K = (ADVRdOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
For write: K = (ADVWrOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
(16) M = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both  
RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses  
performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR  
behavior is automatically handled by GPMC controller.  
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F1  
F0  
F1  
gpmc_clk  
F2  
F3  
F7  
F18  
gpmc_ncsx  
F4  
gpmc_a[10:1]  
Valid Address  
F19  
F6  
gpmc_nbe0_cle  
F19  
gpmc_nbe1  
F6  
F8  
F8  
F20  
F9  
gpmc_nadv_ale  
gpmc_noe  
F10  
F11  
F13  
F12  
D 0  
gpmc_d[15:0]  
gpmc_waitx  
gpmc_io_dir  
F23  
F24  
OUT  
IN  
OUT  
030-021  
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-2. GPMC/NOR Flash Synchronous Single Read (GpmcFCLKDivider = 0)  
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F1  
F0  
F1  
gpmc_clk  
F2  
F3  
gpmc_ncsx  
gpmc_a[10:1]  
gpmc_nbe0_cle  
gpmc_nbe1  
F4  
F6  
Valid Address  
F7  
F7  
F9  
F6  
F8  
F8  
gpmc_nadv_ale  
gpmc_noe  
F10  
F11  
F13  
F13  
F12  
D 0  
F22  
F12  
D 3  
gpmc_d[15:0]  
gpmc_waitx  
gpmc_io_dir  
D 1  
D 2  
F21  
F23  
F24  
OUT  
IN  
OUT  
030-022  
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-3. GPMC/NOR Flash Synchronous Burst Read 4x16-bit (GpmcFCLKDivider = 0)  
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F1  
F1  
F0  
gpmc_clk  
F2  
F3  
gpmc_ncsx  
F4  
gpmc_a[10:1]  
Valid Address  
F17  
F17  
F6  
F6  
F17  
F17  
F17  
F17  
gpmc_nbe0_cle  
gpmc_nbe1  
gpmc_nadv_ale  
gpmc_nwe  
F8  
F8  
F9  
F14  
F14  
F15  
D 1  
F15  
D 2  
F15  
gpmc_d[15:0]  
gpmc_waitx  
D 0  
D 3  
gpmc_io_dir  
OUT  
030-023  
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-4. GPMC/NOR Flash Synchronous Burst Write (GpmcFCLKDivider = 0)  
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F1  
F0  
F1  
gpmc_clk  
F2  
F3  
gpmc_ncsx  
F6  
F6  
F4  
F7  
gpmc_nbe0_cle  
gpmc_nbe1  
Valid  
F7  
Valid  
gpmc_a[26:17]  
Address (MSB)  
F5  
F12  
F13  
D1 D2  
F4  
F12  
gpmc_a[16:1]_d[15:0]  
gpmc_nadv_ale  
gpmc_noe  
Address (LSB)  
F8  
D0  
D3  
F8  
F9  
F10  
F11  
gpmc_waitx  
F24  
F23  
gpmc_io_dir  
OUT  
IN  
OUT  
030-024  
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-5. GPMC/Multiplexed NOR Flash Synchronous Burst Read  
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F1  
F1  
F0  
gpmc_clk  
F2  
F3  
gpmc_ncsx  
F4  
F6  
gpmc_a[26:17]  
Address (MSB)  
F17  
F17  
F17  
F17  
F17  
F17  
gpmc_nbe0_cle  
gpmc_nbe1  
gpmc_nadv_ale  
gpmc_nwe  
F6  
F8  
F8  
F9  
F14  
F14  
F15  
D 1  
F15  
D 2  
F15  
gpmc_d[15:0]  
gpmc_waitx  
Address (LSB)  
D 0  
D 3  
gpmc_io_dir  
OUT  
030-025  
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-6. GPMC/Multiplexed NOR Flash Synchronous Burst Write  
6.4.1.2 GPMC/NOR Flash Interface Asynchronous Timing  
The following tables assume testing over the recommended operating conditions and electrical  
characteristic conditions.  
Table 6-5. GPMC/NOR Flash Asynchronous Mode Timing Conditions  
TIMING CONDITION PARAMETER  
Input Conditions  
VALUE  
UNIT  
tR  
Input signal rise time  
Input signal fall time  
1.8  
1.8  
ns  
ns  
tF  
Output Conditions  
CLOAD  
Output load capacitance  
30  
pF  
Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters(1) (2)  
NO.  
PARAMETER  
1.8V,3.3V  
UNIT  
MIN  
MAX  
6.5  
4
FI1  
FI2  
FI3  
FI4  
FI5  
FI6  
Maximum output data generation delay from internal functional clock  
Maximum input data capture delay by internal functional clock  
Maximum device select generation delay from internal functional clock  
Maximum address generation delay from internal functional clock  
Maximum address valid generation delay from internal functional clock  
Maximum byte enable generation delay from internal functional clock  
ns  
ns  
ns  
ns  
ns  
ns  
6.5  
6.5  
6.5  
6.5  
(1) The internal parameters table must be used to calculate Data Access Time stored in the corresponding CS register bit field.  
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.  
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Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters(1) (2) (continued)  
NO.  
PARAMETER  
1.8V,3.3V  
UNIT  
MIN  
MAX  
6.5  
FI7  
FI8  
FI9  
Maximum output enable generation delay from internal functional clock  
Maximum write enable generation delay from internal functional clock  
Maximum functional clock skew  
ns  
ns  
ps  
6.5  
100  
Table 6-7. GPMC/NOR Flash Interface Timing Requirements – Asynchronous Mode  
NO.  
PARAMETER  
1.8V,3.3V  
MAX  
UNIT  
MIN  
FA5(1)  
FA20(3)  
tacc(DAT)  
Data maximum access time  
H(2)  
P(4)  
GPMC_FCLK cycles  
GPMC_FCLK cycles  
tacc1-pgmode(DAT)  
Page mode successive data maximum  
access time  
FA21(5)  
tacc2-pgmode(DAT)  
Page mode first data maximum access  
time  
H(2)  
GPMC_FCLK cycles  
(1) The FA5 parameter illustrates the amount of time required to internally sample input Data. It is expressed in number of GPMC functional  
clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data is internally sampled by active functional clock  
edge. FA5 value must be stored inside the AccessTime register bit field.  
(2) H = AccessTime * (TimeParaGranularity + 1)  
(3) The FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of  
GPMC functional clock cycles. After each access to input Page Data, next input Page Data is internally sampled by active functional  
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.  
(4) P = PageBurstAccessTime * (TimeParaGranularity + 1)  
(5) The FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data is internally sampled by  
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.  
Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode  
NO.  
PARAMETER  
1.8V/ 3.3V  
UNIT  
MIN  
MAX  
2.0  
tR(DO)  
Rise time, output data  
Fall time, output data  
ns  
ns  
ns  
ns  
tF(DO)  
2.0  
FA0  
tW(nBEV)  
Pulse duration,  
gpmc_nbe0_cle,  
gpmc_nbe1 valid time  
Read  
Write  
N(12)  
N(12)  
FA1  
FA3  
tW(nCSV)  
Pulse duration,  
gpmc_ncsx(13) v low  
Read  
Write  
Read  
Write  
A(1)  
A(1)  
ns  
ns  
ns  
ns  
td(nCSV-nADVIV)  
Delay time,  
gpmc_ncsx(13) valid to  
gpmc_nadv_ale invalid  
B(2) – 0.2  
B(2) – 0.2  
B(2) + 2.0  
B(2) + 2.0  
FA4  
td(nCSV-nOEIV)  
td(AV-nCSV)  
Delay time, gpmc_ncsx(13) valid to  
gpmc_noe invalid (Single read)  
C(3) – 0.2  
J(9) – 0.2  
J(9) – 0.2  
C(3) + 2.0  
J(9) + 2.0  
J(9) + 2.0  
ns  
ns  
ns  
FA9  
Delay time, address bus valid to  
gpmc_ncsx(13) valid  
FA10  
td(nBEV-nCSV)  
Delay time, gpmc_nbe0_cle,  
gpmc_nbe1 valid to gpmc_ncsx(13)  
valid  
FA12  
FA13  
FA14  
FA15  
FA16  
td(nCSV-nADVV)  
td(nCSV-nOEV)  
td(nCSV-IODIR)  
td(nCSV-IODIR)  
tw(AIV)  
Delay time, gpmc_ncsx(13) valid to  
gpmc_nadv_ale valid  
K(10) – 0.2  
L(11) – 0.2  
L(11) – 0.2  
M(14) – 0.2  
K(10) + 2.0  
L(11) + 2.0  
L(11) + 2.0  
M(14) + 2.0  
ns  
ns  
ns  
ns  
ns  
Delay time, gpmc_ncsx(13) valid to  
gpmc_noe valid  
Delay time, gpmc_ncsx(13) valid to  
gpmc_io_dir high  
Delay time, gpmc_ncsx(13) valid to  
gpmc_io_dir low  
Address invalid duration between 2  
successive R/W accesses  
G(7)  
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Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode (continued)  
NO.  
PARAMETER  
1.8V/ 3.3V  
UNIT  
MIN  
MAX  
FA18  
FA20  
FA25  
FA27  
FA28  
FA29  
FA37  
td(nCSV-nOEIV)  
tw(AV)  
Delay time, gpmc_ncsx(13) valid to  
gpmc_noe invalid (Burst read)  
I(8) – 0.2  
I(8) + 2.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Pulse duration, address valid – 2nd, 3rd,  
and 4th accesses  
D(4)  
td(nCSV-nWEV)  
td(nCSV-nWEIV)  
td(nWEV-DV)  
td(DV-nCSV)  
td(nOEV-AIV)  
Delay time, gpmc_ncsx(13) valid to  
gpmc_nwe valid  
E(5) – 0.2  
F(6) – 0.2  
E(5) + 2.0  
F(6) + 2.0  
2.0  
Delay time, gpmc_ncsx(13) valid to  
gpmc_nwe invalid  
Delay time, gpmc_ new valid to data bus  
valid  
Delay time, data bus valid to  
gpmc_ncsx(13) valid  
J(9) – 0.2  
J(9) + 2.0  
2.0  
Delay time, gpmc_noe valid to  
gpmc_a[16:1]_d[15:0] address phase  
end  
(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
For single write: A = (CSWrOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n  
being the page burst access number  
(2) For reading: B = ((ADVRdOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK  
For writing: B = ((ADVWrOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK  
(3) C = ((OEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK  
(4) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK  
(5) E = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK  
(6) F = ((WEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK  
(7) G = Cycle2CycleDelay * GPMC_FCLK  
(8) I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) *  
GPMC_FCLK  
(9) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK  
(10) K = ((ADVOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK  
(11) L = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK  
(12) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK  
For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK  
For burst read: N = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
For burst write: N = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
(14) M = ((RdCycleTime - CSOnTime) * (TimeParaGranularity + 1) - 0.5 * CSExtraDelay) * GPMC_FCLK  
Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both  
RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses  
performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR  
behavior is automatically handled by GPMC controller.  
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GPMC_FCLK  
gpmc_clk  
FA5  
FA1  
gpmc_ncsx  
FA9  
gpmc_a[10:1]  
Valid Address  
FA0  
FA10  
gpmc_nbe0_cle  
gpmc_nbe1  
Valid  
FA0  
Valid  
FA10  
FA3  
FA12  
gpmc_nadv_ale  
FA4  
FA13  
gpmc_noe  
gpmc_d[15:0]  
Data IN 0  
Data IN 0  
gpmc_waitx  
gpmc_io_dir  
FA15  
FA14  
OUT  
IN  
OUT  
030-026  
Figure 6-7. GPMC/NOR Flash – Asynchronous Read – Single Word Timing(1) (2) (3)  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.  
FA5 value must be stored inside AccessTime register bit field.  
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
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GPMC_FCLK  
gpmc_clk  
FA5  
FA5  
FA1  
FA1  
gpmc_ncsx  
FA16  
FA9  
FA9  
gpmc_a[10:1]  
Address 0  
FA0  
Address 1  
FA0  
FA10  
FA10  
gpmc_nbe0_cle  
gpmc_nbe1  
Valid  
FA0  
Valid  
FA0  
Valid  
Valid  
FA10  
FA10  
FA3  
FA12  
FA3  
FA12  
gpmc_nadv_ale  
FA4  
FA4  
FA13  
FA13  
gpmc_noe  
Data Upper  
gpmc_d[15:0]  
gpmc_waitx  
gpmc_io_dir  
FA15  
FA15  
FA14  
OUT  
FA14  
OUT  
IN  
IN  
030-027  
Figure 6-8. GPMC/NOR Flash – Asynchronous Read – 32-bit Timing(1) (2) (3)  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.  
FA5 value must be stored inside AccessTime register bit field.  
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
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GPMC_FCLK  
gpmc_clk  
FA21  
FA20  
Add1  
FA20  
Add3  
FA20  
FA1  
gpmc_ncsx  
FA9  
gpmc_a[10:1]  
Add0  
Add2  
Add4  
FA0  
FA10  
FA10  
gpmc_nbe0_cle  
FA0  
gpmc_nbe1  
FA12  
gpmc_nadv_ale  
FA18  
FA13  
gpmc_noe  
D3  
gpmc_d[15:0]  
D0  
D1  
D2  
D3  
gpmc_waitx  
gpmc_io_dir  
FA15  
FA14  
OUT  
OUT  
IN  
030-028  
Figure 6-9. GPMC/NOR Flash – Asynchronous Read – Page Mode 4x16-bit Timing(1) (2) (3) (4)  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
(2) FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by  
active functional clock edge. FA21 value must be stored inside AccessTime register bit field.  
(3) FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC  
functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge  
after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input  
page data). FA20 value must be stored in PageBurstAccessTime register bit field.  
(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
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gpmc_fclk  
gpmc_clk  
FA1  
gpmc_ncsx  
FA9  
gpmc_a[10:1]  
Valid Address  
FA0  
FA10  
gpmc_nbe0_cle  
FA0  
FA10  
gpmc_nbe1  
FA3  
FA12  
gpmc_nadv_ale  
FA27  
FA25  
gpmc_nwe  
gpmc_d[15:0]  
gpmc_waitx  
gpmc_io_dir  
FA29  
Data OUT  
OUT  
030-029  
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-10. GPMC/NOR Flash – Asynchronous Write – Single Word Timing  
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GPMC_FCLK  
gpmc_clk  
FA1  
FA5  
gpmc_ncsx  
FA9  
gpmc_a[26:17]  
Address (MSB)  
FA0  
FA10  
FA10  
gpmc_nbe0_cle  
gpmc_nbe1  
Valid  
FA0  
Valid  
FA3  
FA12  
gpmc_nadv_ale  
FA4  
FA13  
gpmc_noe  
gpmc_a[16:1]_d[15:0]  
gpmc_io_dir  
FA29  
FA37  
Data IN  
Data IN  
Address (LSB)  
FA15  
FA14  
OUT  
OUT  
IN  
gpmc_waitx  
030-030  
Figure 6-11. GPMC/Multiplexed NOR Flash – Asynchronous Read – Single Word Timing(1) (2) (3)  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.  
FA5 value must be stored inside AccessTime register bit field.  
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
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gpmc_fclk  
gpmc_clk  
FA1  
gpmc_ncsx  
FA9  
gpmc_a[26:17]  
Address (MSB)  
FA0  
FA10  
gpmc_nbe0_cle  
FA0  
FA10  
gpmc_nbe1  
FA3  
FA12  
gpmc_nadv_ale  
FA27  
FA25  
gpmc_nwe  
FA29  
FA28  
gpmc_a[16:1]_d[15:0]  
Valid Address (LSB)  
Data OUT  
gpmc_waitx  
gpmc_io_dir  
OUT  
030-031  
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-12. GPMC/Multiplexed NOR Flash – Asynchronous Write – Single Word Timing  
6.4.1.3 GPMC/NAND Flash Interface Timing  
The following tables assume testing over the recommended operating conditions and electrical  
characteristic conditions.  
Table 6-9. GPMC/NAND Flash Asynchronous Mode Timing Conditions  
TIMING CONDITION PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
Input Conditions  
tR  
Input signal rise time  
Input signal fall time  
Output load capacitance  
1.8  
1.8  
ns  
ns  
pF  
tF  
CLOAD  
30  
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Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing Internal Parameters(1) (2)  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
6.5  
4
GNFI1  
GNFI2  
GNFI3  
GNFI4  
Maximum output data generation delay from internal functional clock  
Maximum input data capture delay by internal functional clock  
Maximum device select generation delay from internal functional clock  
ns  
ns  
ns  
ns  
6.5  
6.5  
Maximum address latch enable generation delay from internal functional  
clock  
GNFI5  
Maximum command latch enable generation delay from internal  
functional clock  
6.5  
ns  
GNFI6  
GNFI7  
GNFI8  
Maximum output enable generation delay from internal functional clock  
Maximum write enable generation delay from internal functional clock  
Maximum functional clock skew  
6.5  
6.5  
100  
ns  
ns  
ps  
(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.  
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.  
Table 6-11. GPMC/NAND Flash Interface Timing Requirements  
NO.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
GNF12(1)  
tacc(DAT)  
Data maximum access time  
J(2)  
GPMC_FCLK cycles  
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC  
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the  
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.  
(2) J = AccessTime * (TimeParaGranularity + 1)  
Table 6-12. GPMC/NAND Flash Interface Switching Characteristics  
NO.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
2.0  
tR(DO)  
Rise time, output data  
ns  
ns  
ns  
tF(DO)  
Fall time, output data  
2.0  
GNF0  
GNF1  
GNF2  
GNF3  
GNF4  
GNF5  
GNF6  
GNF7  
GNF8  
tw(nWEV)  
Pulse duration, gpmc_nwe  
valid time  
A(1)  
td(nCSV-nWEV)  
tw(CLEH-nWEV)  
tw(nWEV-DV)  
Delay time, gpmc_ncsx(13)  
valid to gpmc_nwe valid  
B(2) - 0.2  
C(3) - 0.2  
D(4) - 0.2  
E(5) - 0.2  
F(6) - 0.2  
G(7) - 0.2  
C(3) - 0.2  
F(6) - 0.2  
B(2) + 2.0  
C(3) + 2.0  
D(4) + 2.0  
E(5) + 2.0  
F(6) + 2.0  
G(7) + 2.0  
C(3) + 2.0  
F(6) + 2.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Delay time, gpmc_nbe0_cle  
high to gpmc_nwe valid  
Delay time, gpmc_d[15:0]  
valid to gpmc_nwe valid  
tw(nWEIV-DIV)  
tw(nWEIV-CLEIV)  
tw(nWEIV-nCSIV)  
tw(ALEH-nWEV)  
tw(nWEIV-ALEIV)  
Delay time, gpmc_nwe invalid  
to gpmc_d[15:0] invalid  
Delay time, gpmc_nwe invalid  
to gpmc_nbe0_cle invalid  
Delay time, gpmc_nwe invalid  
to gpmc_ncsx(13) invalid  
Delay time, gpmc_nadv_ale  
High to gpmc_nwe valid  
Delay time, gpmc_nwe invalid  
to gpmc_nadv_ale invalid  
GNF9  
tc(nWE)  
Cycle time, Write cycle time  
H(8)  
ns  
ns  
GNF10  
td(nCSV-nOEV)  
Delay time, gpmc_ncsx(13)  
valid to gpmc_noe valid  
I(9) - 0.2  
I(9) + 2.0  
GNF13  
GN F14  
tw(nOEV)  
tc(nOE)  
Pulse duration, gpmc_noe  
valid time  
K(10)  
L(11)  
ns  
ns  
Cycle time, Read cycle time  
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Table 6-12. GPMC/NAND Flash Interface Switching Characteristics (continued)  
NO.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
M(12) + 2.0  
GNF15  
tw(nOEIV-nCSIV)  
Delay time, gpmc_noe invalid  
to gpmc_ncsx(13) invalid  
M(12) - 0.2  
ns  
(1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK  
(2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK  
(3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK  
(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK  
(5) E = (WrCycleTime – WEOffTime * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay ) * GPMC_FCLK  
(6) F = (ADVWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay ) * GPMC_FCLK  
(7) G = (CSWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay ) * GPMC_FCLK  
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK  
(9) I = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK  
(10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK  
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK  
(12) M = (CSRdOffTime – OEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay ) * GPMC_FCLK  
(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
GPMC_FCLK  
GNF1  
GNF2  
GNF6  
GNF5  
gpmc_ncsx  
gpmc_nbe0_cle  
gpmc_nadv_ale  
gpmc_noe  
GNF0  
gpmc_nwe  
GNF3  
GNF4  
gpmc_a[16:1]_d[15:0]  
Command  
030-032  
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
Figure 6-13. GPMC/NAND Flash – Command Latch Cycle Timing  
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GPMC_FCLK  
gpmc_ncsx  
GNF1  
GNF7  
GNF6  
GNF8  
gpmc_nbe0_cle  
gpmc_nadv_ale  
gpmc_noe  
GNF9  
GNF0  
gpmc_nwe  
GNF3  
GNF4  
gpmc_a[16:1]_d[15:0]  
Address  
030-033  
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
Figure 6-14. GPMC/NAND Flash – Address Latch Cycle Timing  
GPMC_FCLK  
GNF12  
GNF10  
GNF15  
gpmc_ncsx  
gpmc_nbe0_cle  
gpmc_nadv_ale  
GNF14  
GNF13  
gpmc_noe  
gpmc_a[16:1]_d[15:0]  
DATA  
gpmc_waitx  
030-034  
Figure 6-15. GPMC/NAND Flash – Data Read Cycle Timing(1) (2) (3)  
(1) The GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional  
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data is internally sampled by active functional clock  
edge. The GNF12 value must be stored inside AccessTime register bit field.  
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
(3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 ,1, 2, or 3.  
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GPMC_FCLK  
GNF1  
GNF6  
gpmc_ncsx  
gpmc_nbe0_cle  
gpmc_nadv_ale  
gpmc_noe  
GNF9  
GNF0  
gpmc_nwe  
GNF3  
GNF4  
gpmc_a[16:1]_d[15:0]  
DATA  
030-035  
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 or 1.  
Figure 6-16. GPMC/NAND Flash – Data Write Cycle Timing  
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6.4.2 SDRAM Controller (SDRC)  
The SDRC is a dedicated interface to DDR2/LPDDR1 SDRAM that performs the following functions:  
•
•
•
•
Buffering of input image data from sensors or video sources  
Intermediate buffering for processing/resizing of image data in the VPFE  
Numerous OSD display buffers  
Intermediate buffering for large raw Bayer data image files while performing image processing  
functions  
•
•
Buffering for intermediate data while performing video encode and decode functions  
Storage of executable code for the ARM  
The main features of the controller are:  
•
•
Open Core Protocol 2.2 (OCP) compliant [7].  
Supports JEDEC standard compliant DDR2 [2] and LPDDR1 [4] devices.  
–
–
SDRAM address range over 2 chip selects.  
Supports following data bus widths:  
OCP Data Bus Width SDRAM Data Bus Width  
64 and 128-Bit  
16, 32, and 64-Bit  
–
–
Supports following CAS latencies:  
SDRAM Type  
DDR2  
CAS Latencies  
2, 3, 4, 5, and 6  
2 and 3  
LPDDR1  
Supports following number of internal banks:  
SDRAM Type  
DDR2  
Internal Banks  
1, 2, 4, and 8  
1, 2, and 4  
LPDDR1  
–
–
Supports 256, 512, 1024, and 2048-word page sizes.  
Supports following burst lengths:  
SDRAM Type  
DDR2  
Burst Length  
8 (4 not supported)  
8 (2 and 4 not supported)  
LPDDR1  
–
–
–
–
–
–
Supports sequential burst type.  
SDRAM auto initialization from reset or configuration change.  
Supports Bank Interleaving across both the chip selects.  
Supports Clock Stop mode for LPDDR1 for low power.  
Supports Self Refresh and Precharge Power-Down modes for low power.  
Supports Partial Array Self Refresh and Temperature Controlled Self Refresh modes for low power  
in LPDDR1.  
–
Temperature Controlled Self Refresh is only supported for mobile SDRAM having on-chip  
temperature sensor.  
–
–
–
–
–
Supports ODT on DDR2.  
Supports prioritized refresh.  
Programmable SDRAM refresh rate and backlog counter.  
Programmable SDRAM timing parameters.  
Supports only little endian.  
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6.4.2.1 LPDDR Interface  
This section provides the timing specification for the LPDDR interface as a PCB design and manufacturing  
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,  
and signal timing. These rules, when followed, result in a reliable LPDDR memory system without the  
need for a complex timing closure process. For more information regarding guidelines for using this  
LPDDR specification, see the Understanding TI's PCB Routing Rule-Based DDR Timing Specification  
Application Report (literature number SPRAAV0).  
6.4.2.1.1 LPDDR Interface Schematic  
Figure 6-17 and Figure 6-18 show the LPDDR interface schematics for a LPDDR memory system. The 1  
x16 LPDDR system schematic is identical to Figure 6-17 except that the high word LPDDR device is  
deleted.  
Microprocessor  
sdrc_d0  
LPDDR  
DQ0  
T
T
T
T
T
sdrc_d7  
sdrc_dm0  
sdrc_dqs0p  
sdrc_d8  
DQ7  
LDM  
LDQS  
DQ8  
T
T
T
sdrc_d15  
sdrc_dm1  
DQ15  
UDM  
sdrc_dqs1p  
UDQS  
LPDDR  
DQ0  
T
sdrc_d16  
T
T
T
T
sdrc_d23  
sdrc_dm2  
sdrc_dqs2p  
sdrc_d24  
DQ7  
LDM  
LDQS  
DQ8  
T
T
T
sdrc_d31  
sdrc_dm3  
sdrc_dqs3p  
sdrc_ba0  
sdrc_ba1  
sdrc_a0  
DQ15  
UDM  
UDQS  
BA0  
BA1  
A0  
T
T
T
BA0  
BA1  
A0  
T
T
sdrc_a14  
A14  
CS  
A14  
CS  
sdrc_ncs0  
T
T
T
T
sdrc_ncas  
sdrc_nras  
sdrc_nwe  
sdrc_cke0  
CAS  
RAS  
WE  
CAS  
RAS  
WE  
CKE  
CKE  
T
T
sdrc_clk  
CK  
CK  
CK  
CK  
sdrc_nclk  
Figure 6-17. AM3517/05 LPDDR High Level Schematic (x16 memories)  
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Microprocessor  
sdrc_d0  
LPDDR  
DQ0  
T
T
T
T
T
sdrc_d7  
sdrc_dm0  
sdrc_dqs0  
sdrc_d8  
DQ7  
DM0  
DQS0  
DQ8  
T
T
T
sdrc_d15  
sdrc_dm1  
sdrc_dqs1  
DQ15  
DM1  
DQS1  
T
sdrc_d16  
DQ16  
T
T
T
T
sdrc_d23  
sdrc_dm2  
sdrc_dqs2  
sdrc_d24  
DQ23  
DM2  
DQS2  
DQ24  
T
T
T
sdrc_d31  
sdrc_dm3  
sdrc_dqs3  
sdrc_ba0  
sdrc_ba1  
sdrc_a0  
DQ31  
DM3  
DQS3  
BA0  
BA1  
A0  
T
T
T
T
T
sdrc_a14  
sdrc_ncs0  
sdrc_ncs1  
sdrc_ncas  
sdrc_nras  
sdrc_nwe  
sdrc_cke0  
sdrc_cke1  
sdrc_clk  
A14  
CS  
N/C  
N/C  
T
T
T
T
CAS  
RAS  
WE  
CKE  
T
T
CK  
CK  
sdrc_nclk  
Figure 6-18. AM3517/05 LPDDR High Level Schematic (x32 memory)  
6.4.2.1.2 Compatible JEDEC LPDDR Devices  
Table 6-13 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface.  
Generally, the LPDDR interface is compatible with x16 and x32 LPDDR333 speed grade LPDDR devices.  
Table 6-13. Compatible JEDEC LPDDR Devices  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
NOTES  
JEDEC LPDDR Device Speed  
Grade  
(1)  
(2)  
1
LPDDR333  
See Note  
2
3
JEDEC LPDDR Device Bit Width  
JEDEC LPDDR Device Count  
16  
1
32  
2
Bits  
Devices  
See Note  
JEDEC LPDDR Device Ball  
Count  
4
60  
90  
Balls  
(1) Higher LPDDR speed grades operating at the specified speeds are supported due to inherent JEDEC LPDDR backwards compatibility.  
(2) 1 x16 LPDDR device is used for 16 bit LPDDR memory system. 1x32 or 2x16 LPDDR devices are used for a 32-bit LPDDR memory  
system.  
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6.4.2.1.3 PCB Stackup  
The minimum stackup required for routing the microprocessor is a six layer stack as shown in Table 6-14.  
Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size  
of the PCB footprint.  
Table 6-14. Minimum PCB Stack Up  
LAYER  
TYPE  
Signal  
Plane  
Plane  
Signal  
Plane  
Signal  
DESCRIPTION  
Top Routing Mostly Horizontal  
Ground  
1
2
3
4
5
6
Power  
Internal Routing  
Ground  
Bottom Routing Mostly Vertical  
Table 6-15. PCB Stack Up Specifications  
NO.  
1
PARAMETER  
MIN  
6
TYP  
MAX  
UNIT  
NOTES  
PCB Routing/Plane Layers  
Signal Routing Layers  
2
3
3
Full ground layers under LPDDR routing region  
2
4
Number of ground plane cuts allowed within LPDDR routing region  
0
0
Number of ground reference planes required for each LPDDR routing 1  
layer  
5
6
1
Number of layers between LPDDR routing layer and reference ground 0  
plane  
7
PCB Routing Feature Size  
PCB Trace Width w  
4
4
Mils  
Mils  
Mils  
Mils  
8
9
PCB BGA escape via pad size  
PCB BGA escape via hole size  
Device BGA Pad Size  
18  
8
10  
11  
12  
13  
14  
See Note(1)  
See Note(2)  
LPDDR Device BGA Pad Size  
Single Ended Impedance, ZO  
Impedance Control  
50  
75  
Ω
Ω
Z-5  
Z
Z + 5  
See Note(3)  
(1) Please see the Flip Chip Ball Grid Array Package Reference Guide (literature number SPRU811) for device BGA pad size.  
(2) Please see the LPDDR device manufacturer documentation for the LPDDR device BGA pad size.  
(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.  
6.4.2.1.4 Placement  
Figure 6-19 shows the required placement for the microprocessor as well as the LPDDR devices. The  
dimensions for Figure 6-19 are defined in Table 6-16. The placement does not restrict the side of the PCB  
that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace  
lengths and allow for proper routing space. For 1x16 and 1x32 LPDDR memory systems, the second  
LPDDR device is omitted from the placement.  
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X
A1  
Y
OFFSET  
LPDDR  
Device  
Y
Y
OFFSET  
Microprocessor  
A1  
Recommended LPDDR Device  
Orientation  
Figure 6-19. AM3517/05 and LPDDR Device Placement  
Table 6-16. Placement Specifications  
NO.  
1
PARAMETER  
MIN  
MAX  
1440  
1030  
525  
UNIT  
Mils  
Mils  
Mils  
NOTES  
See Notes(1)  
See Notes(1)  
(2)  
(2)  
X
,
,
2
Y
3
Y Offset  
See Notes(1) (2) (3)  
, ,  
4
LPDDR Keepout Region  
See Note(4)  
Clearance from non-LPDDR signal to LPDDR  
Keepout Region  
5
4
w
See Note(5)  
(1) See Figure 6-19 for dimension definitions.  
(2) Measurements from center of device to center of LPDDR device.  
(3) For 16 bit memory systems it is recommended that Y Offset be as small as possible.  
(4) LPDDR keepout region to encompass entire LPDDR routing area.  
(5) Non-LPDDR signals allowed within LPDDR keepout region provided they are separated from LPDDR routing layers by a ground plane.  
6.4.2.1.5 LPDDR Keep Out Region  
The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR  
keep out region is defined for this purpose and is shown in Figure 6-20. The size of this region varies with  
the placement and LPDDR routing. Additional clearances required for the keep out region are shown in  
Table 6-16.  
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A1  
LPDDR Device  
A1  
Region should encompass all LPDDR circuitry and varies depending  
on placement. Non-LPDDR signals should not be routed on the  
LPDDR signal layers within the LPDDR keep out region. Non-LPDDR  
signals may be routed in the region provided they are routed on  
layers separated from LPDDR signal layers by a ground layer. No  
breaks should be allowed in the reference ground layers in this  
region. In addition, the 1.8 V power plane should cover the entire keep  
out region.  
Figure 6-20. LPDDR Keepout Region  
6.4.2.1.6 Net Classes  
Table 6-17 lists the clock net classes for the LPDDR interface. Table 6-18 lists the signal net classes, and  
associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the  
termination and routing rules that follow.  
Table 6-17. Clock Net Class Definitions  
CLOCK NET CLASS  
PIN NAMES  
sdrc_clk/sdrc_nclk  
sdrc_dqs0  
CK  
DQS0  
DQS1  
DQS2  
DQS3  
sdrc_dqs1  
sdrc_dqs2  
sdrc_dqs3  
Table 6-18. Signal Net Class Definitions  
CLOCK NET CLASS  
ASSOCIATED CLOCK NET CLASS  
PIN NAMES  
sdrc_ba, sdrc_a, sdrc_ncs0, sdrc_ncas,  
sdrc_nras, sdrc_nwe, sdrc_cke0  
ADDR_CTRL  
CK  
DQ0  
DQ1  
DQ2  
DQ3  
DQS0  
DQS1  
DQS2  
DQS3  
sdrc_d, sdrc_dm0  
sdrc_d, sdrc_dm1  
sdrc_d, sdrc_dm2  
sdrc_d, sdrc_dm3  
6.4.2.1.7 LPDDR Signal Termination  
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.  
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only  
type permitted. Table 6-19 shows the specifications for the series terminators.  
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Table 6-19. LPDDR Signal Terminations  
NO.  
1
PARAMETER  
CK Net Class  
MIN  
0
TYP  
MAX  
10  
UNIT  
Ω
NOTES  
See Note(1)  
2
ADDR_CTRL Net Class  
0
22  
22  
Zo  
Ω
See Notes(1) (2) (3)  
,
,
Data Byte Net Classes  
(DQS0-DQS3, DQ0-DQ3)  
3
0
Zo  
Ω
See Notes(1) (2) (3)  
, ,  
(1) Only series termination is permitted, parallel or SST specifically disallowed.  
(2) Terminator values larger than typical only recommended to address EMI issues.  
(3) Termination value should be uniform across net class.  
6.4.2.1.8 LPDDR CK and ADDR_CTRL Routing  
Figure 6-21 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a  
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A  
should be maximized.  
A1  
T
A
Microprocessor  
A1  
Figure 6-21. CK and ADDR_CTRL Routing and Topology  
Table 6-20. CK and ADDR_CTRL Routing Specification  
NO.  
1
PARAMETER  
MIN  
TYP  
MAX  
2w  
UNIT  
NOTES  
Center to Center CK-CK spacing  
CK A to B/A to C Skew Length Mismatch  
CK B to C Skew Length Mismatch  
2
25  
Mils  
Mils  
See Note(1)  
3
25  
Center to Center CK to other  
LPDDR trace spacing  
4
4w  
See Note(2)  
See Note(3)  
5
6
CK/ADDR_CTRL nominal trace length  
CACLM-50  
CACLM  
CACLM+50  
100  
Mils  
Mils  
ADDR_CTRL to CK Skew Length Mismatch  
ADDR_CTRL to ADDR_CTRL  
Skew Length Mismatch  
7
8
9
100  
Mils  
Center to Center ADDR_CTRL to other  
LPDDR trace 4w spacing  
4w  
3w  
See Note(2)  
See Note(2)  
See Note(1)  
Center to Center ADDR_CTRL to other  
ADDR_CTRL 3w trace spacing  
ADDR_CTRL A to B/A to C Skew Length  
Mismatch  
10  
11  
100  
100  
Mils  
Mils  
ADDR_CTRL B to C Skew Length Mismatch  
(1) Series terminator, if used, should be located closest to device.  
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing  
congestion.  
(3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.  
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Figure 6-22 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.  
Skew matching across bytes is not needed nor recommended.  
T
E0  
A1  
T
E1  
Microprocessor  
T
E2  
A1  
T
E3  
Figure 6-22. DQS and DQ Routing and Topology  
Table 6-21. DQS and DQ Routing Specification(1)  
NO.  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
NOTES  
2
DQS E Skew Length Mismatch  
25  
Mils  
Center to Center DQS to other LPDDR  
trace spacing  
3
4w  
See Note(2)  
See Note(3)  
4
5
6
DQS/DQ nominal trace length  
DQ to DQS Skew Length Mismatch  
DQ to DQ Skew Length Mismatch  
DQLM - 50  
DQLM  
DQLM + 50  
100  
Mils  
Mils  
Mils  
100  
Center to Center DQ to other LPDDR  
trace spacing  
7
4w  
3w  
See Note(2)  
Center to Center DQ to other DQ trace  
spacing  
8
9
See Note(2) (4)  
,
DQ E Skew Length Mismatch  
100  
Mils  
(1) Series terminator, if used, should be located closest to LPDDR.  
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing  
congestion.  
(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing  
congestion.  
(4) DQLM is the longest Manhattan distance of the DQS and DQ net classes.  
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6.4.2.2 DDR2 Interface  
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing  
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,  
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need  
for a complex timing closure process. For more information regarding guidelines for using this DDR2  
specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0).  
6.4.2.2.1 DDR2 Interface Schematic  
Figure 6-23 shows the DDR2 interface schematic for a dual-memory DDR2 system. The single-memory  
system is shown in Figure 6-24. Pin numbers for the AM3517/05 can be obtained from the pin description  
section.  
6.4.2.2.2 Compatible JEDEC DDR2 Devices  
Table 6-22 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.  
Generally, the DDR2 interface is compatible with x16 or x32 DDR2 speed grade DDR2-333 devices.  
Table 6-22. Compatible JEDEC DDR2 Devices  
No.  
1
Parameter  
Min  
Max  
Unit  
Notes  
(1)  
JEDEC DDR2 Device Speed Grade  
JEDEC DDR2 Device Bit Width  
JEDEC DDR2 Device Count  
JEDEC DDR2 Device Ball Count  
DDR2-333 MHz  
See Note  
2
x16  
1
x32  
2
Bits  
Devices  
Balls  
(2)  
(3)  
3
See Note  
See Note  
4
84  
92  
(1) Higher DDR2 speed grades operating at the specified speeds are supported due to inherent JEDEC DDR2 backwards compatibility.  
(2) Device count indicates number of dies. If a package contains 2 dies, that is the maximum number of devices that can be connected.  
(3) 92 ball devices retained for legacy support. New designs should use 84 ball DDR2 devices. Electrically, the 92 and 84 ball DDR2  
devices are the same.  
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6.4.2.2.3 PCB Stackup  
The minimum stackup required for routing the AM3517/05 is a six-layer stack as shown in Table 6-23.  
Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size  
of the PCB footprint.  
Table 6-23. Minimum PCB Stack Up  
Layer  
Type  
Signal  
Plane  
Plane  
Signal  
Plane  
Signal  
Description  
Top Routing Mostly Horizontal  
Ground  
1
2
3
4
5
6
Power  
Internal Routing  
Ground  
Bottom Routing Mostly Vertical  
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Complete stack up specifications are provided in Table 6-24.  
Microprocessor  
SDRC_D0  
T
T
DQ0  
DQ7  
SDRC_D7  
T
T
T
LDM  
LDQS  
LDQS#  
LQ8  
SDRC_DM0  
SDRC_DQS0P  
SDRC_DQS0N  
SDRC_D8  
T
T
LQ15  
SDRC_D15  
T
T
T
SDRC_DM1  
SDRC_DQS1P  
SDRC_DQS1N  
UDM  
UDQS  
UDQS#  
T
SDRC_STRBEN0  
SDRC_STRBEN_DLY0  
Length = avg DQS0-1 length+CLK  
x16 DDR2  
SDRC_D16  
T
DQ0  
T
T
SDRC_D23  
DQ7  
LDM  
LDQS  
LDQS#  
SDRC_DM2  
SDRC_DQS2P  
SDRC_DQS2N  
T
T
SDRC_D24  
T
T
DQ8  
SDRC_D31  
DQ15  
T
T
T
UDM  
UDQS  
UDQS#  
SDRC_DM3  
SDRC_DQS3P  
SDRC_DQS3N  
T
SDRC_STRBEN1  
SDRC_STRBEN_DLY1  
Length = avg DQS2-3 length+CLK  
T
T
T
BA0  
BA1  
BA2*  
BA0  
BA1  
BA2*  
SDRC_BA0  
SDRC_BA1  
SDRC_BA2  
A0  
A0  
T
T
SDRC_A0  
A14*  
A14*  
SDRC_A14  
T
T
T
T
T
T
T
T
CS1  
CS2*  
CAS#  
RAS#  
WE#  
CS1  
CS2*  
CAS#  
SDRC_nCS0  
SDRC_nCS1  
SDRC_nCAS  
SDRC_nRAS  
SDRC_nWE  
SDRC_nCKE0  
SDRC_CLK  
Vio1.8  
RAS#  
WE#  
CLK  
CLK  
CLK#  
0.1  
µF  
SDRC_nCLK  
CLK#  
1K Ω  
1%  
T
SDRC_ODT  
ODT*  
VREF  
ODT*  
VREF  
VREFSSTL  
0.1µF(A)  
0.1  
(A)  
µF  
0.1µF  
µF(A)  
0.1  
1K Ω  
1%  
DDR_PADREF  
50 1%  
A. See VREF Routing and Topology figure for information on capacitor placement.  
Figure 6-23. DDR2 Dual-Memory High Level Schematic  
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Microprocessor  
DDR2  
SDRC_D0  
DQ0  
T
SDRC_D7  
T
DQ7  
SDRC_DM0  
SDRC_DQS0P  
SDRC_DQS0N  
DM0  
DQS0  
DQS0#  
T
T
T
DQ8  
SDRC_D8  
T
SDRC_D15  
T
DQ15  
SDRC_DM1  
SDRC_DQS1P  
SDRC_DQS1N  
DM1  
DQS1  
DQS1#  
T
T
T
SDRC_STRBEN0  
SDRC_STRBEN_DLY0  
T
Length = avg D0-D15 length+CLK  
T
SDRC_D16  
SDRC_D23  
DQ16  
DQ23  
T
T
T
T
SDRC_DM2  
SDRC_DQS2P  
SDRC_DQS2N  
DM2  
DQS2  
DQS2#  
SDRC_D24  
DQ24  
DQ31  
T
T
SDRC_D31  
T
T
T
SDRC_DM3  
SDRC_DQS3P  
SDRC_DQS3N  
DM3  
DQS3  
DQS3#  
SDRC_STRBEN1  
SDRC_STRBEN_DLY1  
T
Length = avg D16-D31 length+CLK  
BA0  
BA1  
BA2*  
T
T
T
SDRC_BA0  
SDRC_BA1  
SDRC_BA2  
A0  
T
T
SDRC_A0  
A14*  
SDRC_A14  
SDRC_nCS0  
SDRC_nCS1  
SDRC_nCAS  
SDRC_nRAS  
SDRC_nWE  
SDRC_nCKE0  
CS1  
T
T
T
T
T
T
T
T
CS2*  
CAS#  
RAS#  
WE#  
CKE  
Vio1.8  
CLK  
CLK#  
SDRC_CLK  
SDRC_nCLK  
0.1µF  
0.1µF  
1K Ω 1%  
1K Ω 1%  
SDRC_ODT0  
ODT*  
VREF  
T
VREFSSTL  
0.1µF (A)  
0.1µF (A)  
0.1µF (A)  
DDR_PADREF  
50 1%  
A. See VREF Routing and Topology figure for information on capacitor placement.  
Figure 6-24. DDR2 Single-Memory High Level Schematic  
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Table 6-24. PCB Stack Up Specifications  
No. Parameter  
Min  
6
Typ  
Max Unit  
Notes  
1
2
PCB Routing/Plane Layers  
Signal Routing Layers  
3
3
Full ground layers under DDR2 routing Region  
Number of ground plane cuts allowed within DDR routing region  
Number of ground reference planes required for each DDR2 routing layer  
Number of layers between DDR2 routing layer and ground plane  
PCB Routing Feature Size  
2
4
0
5
1
6
0
7
4
4
Mils  
Mils  
Mils  
Mils  
8
PCB Trace Width w  
9
PCB BGA escape via pad size  
20  
10  
12  
10  
11  
12  
13  
14  
PCB BGA escape via hole size  
(1)  
(2)  
AM3517/05 BGA pad size  
See Note  
See Note  
DDR2 Device BGA pad size  
Single Ended Impedance, Zo  
50  
75  
Ω
Ω
(3)  
Impedance Control  
Z-5  
Z
Z+5  
See Note  
(1) The recommended pad size is 0.3 mm per IPC-7351 specification.  
(2) Please refer to IPC standard IPC-7351 or manufacturer's recommendations for correct BGA pad size.  
(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.  
6.4.2.2.4 Placement  
Figure 6-24 shows the required placement for the DDR2 devices. The dimensions for Figure 6-25 are  
defined in Table 6-25. The placement does not restrict the side of the PCB that the devices are mounted  
on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper  
routing space. For single-memory DDR2 systems, the second DDR2 device is omitted from the  
placement.  
X
A1  
Y
OFFSET  
DDR2  
Device  
Y
Y
OFFSET  
Microprocessor  
A1  
Recommended DDR2  
Device Orientation  
Figure 6-25. DDR2 Device Placement  
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Table 6-25. Placement Specifications  
No. Parameter  
Min  
Max  
1750  
1280  
650  
Unit  
Mils  
Mils  
Mils  
Notes  
(1) (2)  
1
2
3
X
See Notes  
,
(1) (2)  
Y
See Notes  
,
(1) (2)  
Y Offset  
See Notes  
.
,
(3)  
(4)  
(5)  
4
5
DDR2 Keepout Region  
See Note  
See Note  
Clearance from non-DDR2 signal to DDR2 Keepout Region  
4
w
(1) See Figure 6-23 for dimension definitions.  
(2) Measurements from center of AM3517/05 device to center of DDR2 device.  
(3) For single memory systems it is recommended that Y Offset be as small as possible.  
(4) DDR2 Keepout region to encompass entire DDR2 routing area  
(5) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.  
6.4.2.2.5 DDR2 Keep Out Region  
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keep  
out region is defined for this purpose and is shown in Figure 6-26. The size of this region varies with the  
placement and DDR routing. Additional clearances required for the keep out region are shown in Table 6-  
25.  
A1  
DDR2  
Device  
A1  
Region should encompass all DDR2 circuitry and varies depending  
on placement. Non-DDR2 signals should not be routed on the DDR  
signal layers within the DDR2 keep out region. Non-DDR2 signals may  
be routed in the region provided they are routed on layers separated  
from DDR2 signal layers by a ground layer. No breaks should be  
allowed in the reference ground layers in this region. In addition, the  
1.8 V power plane should cover the entire keep out region.  
Figure 6-26. DDR2 Keepout Region  
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6.4.2.2.6 Bulk Bypass Capacitors  
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.  
Table 6-26 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note  
that this table only covers the bypass needs of the AM3517/05and DDR2 interfaces. Additional bulk  
bypass capacitance may be needed for other circuitry.  
Table 6-26. Bulk Bypass Capacitors  
No. Parameter  
Min  
Max  
Unit  
Notes  
1
VDDS Bulk Bypass Capacitor Count  
3
Devices See Note  
(1)  
2
3
VDDS Bulk Bypass Total Capacitance  
DDR#1 Bulk Bypass Capacitor Count  
30  
1
uF  
Devices See Note  
(1)  
4
5
DDR#1 Bulk Bypass Total Capacitance  
DDR#2 Bulk Bypass Capacitor Count  
22  
1
uF  
Devices See Notes  
(1) (2)  
,
6
DDR#2 Bulk Bypass Total Capacitance  
22  
uF  
See Note  
(2)  
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed  
(HS) bypass caps.  
(2) Only used on dual-memory systems  
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6.4.2.2.7 High-Speed Bypass Capacitors  
High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly  
important to minimize the parasitic series inductance of the HS bypass cap, AM3517/05 DDR2 power, and  
AM3517/05 DDR2 ground connections. Table 6-27 contains the specification for the HS bypass capacitors  
as well as for the power connections on the PCB.  
6.4.2.2.8 Net Classes  
Table 6-28 lists the clock net classes for the DDR2 interface. Table 6-29 lists the signal net classes, and  
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the  
termination and routing rules that follow.  
Table 6-27. High-Speed Bypass Capacitors  
No. Parameter  
Min  
Max  
0402  
250  
Unit  
10 Mils  
Mils  
Notes  
(1)  
(2)  
1
2
3
4
5
6
7
8
9
HS Bypass Capacitor Package Size  
See Note  
Distance from HS bypass capacitor to device being bypassed  
Number of connection vias for each HS bypass capacitor  
Trace length from bypass capacitor contact to connection via  
Number of connection vias for each DDR2 device power or ground balls  
Trace length from DDR2 device power ball to connection via  
VDDS HS Bypass Capacitor Count  
2
1
1
Vias  
See Note  
30  
35  
Mils  
Vias  
Mils  
(3)  
(3)  
20  
1.2  
8
Devices  
μF  
See Note  
See Note  
VDDS HS Bypass Capacitor Total Capacitance  
DDR#1 HS Bypass Capacitor Count  
Devices  
μF  
10 DDR#1 HS Bypass Capacitor Total Capacitance  
11 DDR#2 HS Bypass Capacitor Count  
0.4  
8
Devices  
See Notes  
(3) (4)  
,
(4)  
12 DDR#2 HS Bypass Capacitor Total Capacitance  
0.4  
μF  
See Note  
(1) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor  
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.  
(3) These devices should be placed as close as possible to the device being bypassed.  
(4) Only used on dual-memory systems  
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Table 6-28. Clock Net Class Definitions  
Clock Net Class  
CK  
AM3517/05 Device Pin Names  
sdrc_clk/sdrc_nclk  
DQS0  
sdrc_dqs0p /sdrc_dqs0n  
sdrc_dqs1p /sdrc_dqs1n  
sdrc_dqs2p/sdrc_dqs2n  
sdrc_dqs3p/sdrc_dqs3n  
DQS1  
DQS2  
DQS3  
Table 6-29. Signal Net Class Definitions  
Associated Clock Net  
Clock Net Class  
Class  
AM3517/05 Device Pin Names  
ADDR_CTRL  
CK  
sdrc_ba[2:0], sdrc_ncs1, sdrc_a[14:0], sdrc_ncs0 , sdrc_ncas, sdrc_nras,  
sdrc_nwe, sdrc_cke0  
DQ0  
DQ1  
DQS0  
sdrc_d[7:0], sdrc_dm0  
DQS1  
sdrc_d[15:8], sdrc_dm1  
DQ2  
DQS2  
sdrc_d[23:16],sdrc_dm2  
sdrc_d[31:24],sdrc_dm3  
sdrc_strben0, sdrc_strben_dly0  
sdrc_strben1, sdrc_strben_dly1  
DQ3  
DQS3  
SDRC_STRBEN0  
SDRC_STRBEN1  
CK,DQS0,DQS1  
CK,DQS2,DQS3  
6.4.2.2.9 DDR2 Signal Termination  
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.  
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only  
type permitted. Table 6-30 shows the specifications for the series terminators.  
Table 6-30. DDR2 Signal Terminations  
No. Parameter  
Min  
0
Typ  
Max  
10  
Unit  
Ω
Notes  
See Note  
See Notes  
(1)  
(1)  
1
2
CLK Net Class  
ADDR_CTRL Net Class  
0
22  
22  
10  
Zo  
Ω
,
,
,
(2) (3)  
,
(1)  
(1)  
3
4
Data Byte Net Classes (DQS0-DQS1, D0-D31)  
SDRC_STRBENx Net Class (SDRC_STRBENx)  
0
0
Zo  
Zo  
Ω
Ω
See Notes  
(2) (3)  
,
See Notes  
(2) (3)  
,
(1) Only series termination is permitted, parallel or SST specifically disallowed.  
(2) Terminator values larger than typical only recommended to address EMI issues.  
(3) Termination value should be uniform across net class.  
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6.4.2.2.10 VREF Routing  
VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM3517/05. VREF  
is intended to be half of the DDR2 power supply voltage and should be created using a resistive divider as  
shown in Figure 6-23. Other methods of creating VREF are not recommended. Figure 6-27 shows the  
layout guidelines for VREF.  
VREF Bypass Capacitor  
DDR2 Device  
A1  
VREF Nominal Minimum  
Trace Width is 20 Mils  
Microprocessor  
A1  
Neck down to minimum in BGA escape  
regions is acceptable. Narrowing to  
accomodate via congestion for short  
distances is also acceptable. Best  
performance is obtained if the width  
of VREF is maximized.  
Figure 6-27. VREF Routing and Topology  
6.4.2.2.11 DDR2 CLK and ADDR_CTRL Routing  
Figure 6-28 shows the topology of the routing for the CLK and ADDR_CTRL net classes. The route is a  
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A  
should be maximized.  
A1  
T
A
Microprocessor  
A1  
Figure 6-28. CLK and ADDR_CTRL Routing and Topology  
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(1)  
Table 6-31. CLK and ADDR_CTRL Routing Specification  
No  
1
Parameter  
Min  
Typ  
Max  
2w  
25  
Unit  
Notes  
Center to center DQS-DQSN spacing  
CK differential pair Skew Length Mismatch(2)  
(1)  
2
Mils  
Mils  
See Note  
3
CLKB to CLKC Skew Length Mismatch  
25  
(3)  
(4)  
4
Center to center CLK to other DDR2 trace spacing  
CK/ADDR_CTRL nominal trace length  
4w  
See Note  
See Note  
5
CACLM-50  
CACLM  
CACLM+50  
100  
Mils  
Mils  
Mils  
6
ADDR_CTRL to CLK Skew Length Mismatch  
ADDR_CTRL to ADDR_CTRL Skew Length Mismatch  
7
100  
(3)  
(3)  
(1)  
8
Center to center ADDR_CTRL to other DDR2 trace  
spacing  
4w  
3w  
See Note  
See Note  
See Note  
9
Center to center ADDR_CTRL to other ADDR_CTRL  
trace spacing  
10  
11  
ADDR_CTRL A to B, ADDR_CTRL A to C, Skew Length  
Mismatch  
100  
100  
Mils  
Mils  
ADDR_CTRL B to C Skew Length Mismatch  
(1) Series terminator, if used, should be located closest to AM3517/05.  
(2) Differential impedance should be 100-ohms.  
(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing  
congestion.  
(4) CACLM is the longest Manhattan distance of the CLK and ADDR_CTRL net classes.  
Figure 6-29 shows the topology and routing for the DQS and Dx net classes; the routes are point to point.  
Skew matching across bytes is not needed nor recommended.  
T
E0  
A1  
T
E1  
Microprocessor  
T
E2  
A1  
T
E3  
Figure 6-29. DQS and Dx Routing and Topology  
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Table 6-32. DQS and Dx Routing Specification(1) (2)  
No. Parameter  
Min  
Typ  
Max  
2w  
Unit  
Mils  
Mils  
Notes  
1
2
3
4
Center to center DQS-DQSN spacing  
DQS E differential pair Skew Length Mismatch(3)  
Center to center DQS to other DDR2 trace spacing  
DQS/Dx nominal trace length  
25  
(4)  
4w  
See Note  
(2)  
DQLM-50 DQLM DQLM+  
50  
See Notes  
,
(5)  
(5)  
(5)  
(4)  
5
6
7
Dx to DQS Skew Length Mismatch  
100  
Mils  
Mils  
See Note  
See Note  
Dx to Dx Skew Length Mismatch  
100  
Center to center Dx to other DDR2 trace spacing  
4w  
See Notes  
,
(6)  
(7)  
8
Center to Center Dx to other Dx trace spacing  
3w  
See Notes  
,
(4)  
(1) "Dx" indicates a data line. E indicates length of DQS differential pair or Dx signal.  
(2) Series terminator, if used, should be located closest to DDR.  
(3) Differential impedance should be 100-ohms.  
(4) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing  
congestion.  
(5) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte  
1.  
(6) Dx's from other DQS domains are considered other DDR2 trace.  
(7) DQLM is the longest Manhattan distance of each of the DQS and Dx net classes.  
Figure 6-30 shows the routing for the SDRC_STRBENx net classes. Table 6-33 contains the routing  
specification. SDRC_STRBENx net classes should be shielded from or routed on different layers than the  
DQx net classes.  
A1  
T
T
Microprocessor  
A1  
Figure 6-30. SDRC_STRBENx Routing  
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Table 6-33. SDRC_STRBENx Routing Specification(1)(2)  
No. Parameter  
Min  
Typ  
Max  
Unit  
Notes  
See Note  
See Note  
(3)  
(4)  
1
SDRC_STRBEN0 Length F  
CKB0B1  
CKB0B2  
SDRC_STRBEN1 Length F  
3
4
5
Center to center SDRC_STRBENx to any other trace spacing  
DQS/Dx nominal trace length  
4w  
DQLM-50  
DQLM  
DQLM+50  
100  
Mils  
(5)  
SDRC_STRBENx Skew  
Mils See Note  
(1) STRBENx termination resistors should be placed close to AM3517/05 STRBENx signal (not close to STRBEN_DLYx signal).  
(2) Ensure signal velocities across different layers are taken into account when calculating STRBENx length. For example, if DQS0 and  
DSQ1 are 1inch each, and DQS0 is on a layer that is 10% faster, use 1.1inch as the length for DQS0.  
(3) CKB0B1 is the sum of the length of the CLK (the portion that goes to the memory associated with DQS0 and DQS1) plus the average  
length of the DQS0 and DQS1 differential pairs.  
(4) CKB0B2 is the sum of the length of the CLK (the portion that goes to the memory associated with DQS2 and DQS3) plus the average  
length of the DQS2 and DQS3 differential pairs.  
(5) Skew from CKB0B1 or CKB0B2.  
6.4.2.2.12 On Die Termination (ODT)  
ODT should only be used with 1 chip select as shown in Figure 6-31. If using sdrc_cs0 and sdrc_cs1,  
sdrc_odt should not be used. ODT signals should be tied off at the memory.  
sdrc_cs0  
sdrc_odt  
CS#  
ODT  
DDR2  
Microprocessor  
CS#  
ODT  
DDR2  
vo DDR2 on One Chip Select  
Figure 6-31. ODT Connection Using One Chip select (sdrc_cs0)  
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6.5.1 Video Processing Subsystem (VPSS)  
The Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input interface  
for external imaging peripherals (i.e., image sensors, video decoders, etc.).  
6.5.1.1 Video Processing Front End (VPFE)  
The Video Processing Front-End (VPFE) controller receives input video/image data from external capture  
devices and stores it to external memory which is transferred into the external memory via a built in DMA  
engine. An internal buffer block provides a high bandwidth path between the VPSS module and the  
external memory. The Cortex-A8 will process the image data based on application requirements.  
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6.5.1.1.1 Video Processing Front End (VPFE) Timing  
The following tables assume testing over recommended operating conditions.  
Table 6-34. VPFE Timing Requirements  
PARAMETER  
1.8V, 3.3V  
MIN MAX  
100  
NO.  
UNIT  
ns  
VF1 tc(VDIN_CLK)  
Cycle time, pixel clock input, VDIN_CLK  
13.33  
3.5  
3.5  
3.5  
3.5  
3.5  
2.5  
2.5  
2.5  
2.5  
2.5  
VF2 tsu(VDIN_D-VDIN_CLK)  
VF3 tsu(VDIN_HD-VDIN_CLK)  
VF4 tsu(VDIN_VD-VDIN_CLK)  
Setup time, VDIN_D to VDIN_CLK rising edge  
Setup time, VDIN_HD to VDIN_CLK rising edge  
Setup time, VDIN_VD to VDIN_CLK rising edge  
ns  
ns  
ns  
VF5 tsu(VDIN_WEN-VDIN_CLK) Setup time, VDIN_WEN to VDIN_CLK rising edge  
ns  
VF6 tsu(C_FLD-VDIN_CLK)  
VF7 th(VDIN_CLK-VDIN_D)  
VF8 th(VDIN-HD-VDIN_CLK)  
VF9 th(VDIN_VD-VDIN_CLK)  
VF10 th(VDIN_WEN-VDIN_CLK)  
VF11 th(C_FLD-VDIN_CLK)  
Setup time, VDIN_FIELD to VDIN_CLK rising edge  
Hold time, VDIN_D valid after VDIN_CLK rising edge  
Hold time, VDIN_HD to VDIN_CLK rising edge  
Hold time, VDIN_VD to VDIN_CLK rising edge  
Hold time, VDIN_WEN to VDIN_CLK rising edge  
Hold time, VDIN_FIELD to VDIN_CLK rising edge  
ns  
ns  
ns  
ns  
ns  
ns  
Table 6-35. VPFE Output Switching Characteristics  
1.8V, 3.3V  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
ns  
VF12 td(VDIN_HD-VDIN_CLK)  
VF13 td(VDIN_VD-VDIN_CLK)  
VF14 td(VDIN_WEN-VDIN_CLK)  
VF15 toh(VDIN_HD-VDIN_CLK)  
VF16 toh(VDIN_VD-VDIN_CLK)  
VF17 toh(C_FLD-VDIN_CLK)  
Output delay time, VDIN_HD to CLK rising edge  
Output delay time, VDIN_VD to CLK rising edge  
Output delay time, VDIN_WEN to CLK rising edge  
Output hold time, VDIN_HD to CLK rising edge  
Output hold time, VDIN_VD to CLK rising edge  
Output hold time, VDIN_FLD to CLK rising edge  
10  
10  
10  
ns  
ns  
0.5  
0.5  
0.5  
ns  
ns  
ns  
VF1  
VDIN_CLK  
(Falling Edge)  
VDIN_CLK  
(Rising Edge)  
VF7  
VF2  
VF7  
VDIN_D[xx]  
VF8, VF9, VF11  
VF3, VF4, VF6  
VF5  
VDIN_HD,  
VDIN_VD,  
VDIN_FIELD  
VF10  
VDIN_WEN  
SPRS550-001  
Figure 6-32. VPFE0 Input Timings  
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VDIN_CLK  
(Falling Edge)  
VDIN_CLK  
(Rising Edge)  
VF15, VF16,  
VF17  
VF15, VF16,  
VF17  
VF12,  
VF13, VF14  
VF12, VF13, VF14  
VDIN_HD,  
VDIN_VD,  
VDIN_FIELD  
SPRS550-002  
Figure 6-33. VPFE Output Timings  
VF18  
VDIN_HD  
(Falling Edge)  
VDIN_HD  
(Rising Edge)  
VF20  
VF19  
VDIN_D[xx]  
SPRS550-003  
Figure 6-34. VPFE Input Timings With VDIN0_HD as Pixel Clock  
6.5.2 Display Subsystem (DSS)  
The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or  
internal (SRAM) memory on an LCD panel or a TV set. The DSS integrates a display controller. It can be  
used in two configurations:  
•
LCD display support in:  
–
–
Bypass mode (RFBI module bypassed)  
RFBI mode (through RFBI module)  
•
TV display support (not discussed in this document because of its analog IO signals)  
The two display supports can be active at the same time.  
6.5.2.1 LCD Display Support in Bypass Mode  
Two types of LCD panel are supported:  
•
•
Thin film transistor (TFT) or active matrix technology  
Supertwisted nematic (STN) or passive matrix technology  
Both configurations are discussed in the following paragraphs.  
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6.5.2.1.1 LCD Display in TFT Mode  
Table 6-36 assumes testing over the recommended operating conditions (see Figure 6-35).  
Table 6-36. LCD Display Interface Switching Characteristics in TFT Mode(1)  
NO.  
PARAMETER  
1.8V, 3.3V  
MIN  
UNIT  
MAX  
4.215  
4.215  
4.215  
4.215  
DL0  
DL1  
DL2  
DL3  
DL4  
DL5  
td(PCLKA-HSYNCT)  
td(PCLKA-VSYNCT)  
td(PCLKA-ACBIASA)  
td(PCLKA-DATAV)  
tc(PCLK)  
Delay time, dss_pclk active edge to dss_hsync transition  
Delay time, dss_pclk active edge to dss_vsync transition  
Delay time, dss_pclk active edge to dss_acbias active level  
Delay time, dss_pclk active edge to dss_data bus valid  
Cycle time(2), dss_pclk  
-4.215  
-4.215  
-4.215  
-4.215  
13.468  
6.06  
ns  
ns  
ns  
ns  
ns  
ns  
pF  
tw(PCLK)  
Pulse duration, dss_pclk low or high  
7.46  
25  
cload  
Load capacitance  
(1) The capacitive load is equivalent to 25 pF.  
(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the  
DISPC_DIVISOR register.  
DL5  
DL4  
dss_pclk  
DL1  
dss_vsync  
DL0  
dss_hsync  
DL2  
dss_acbias  
DL3  
dss_data[23:0]  
030-061  
Figure 6-35. LCD Display in TFT Mode(1) (2) (3) (4)  
(1) The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.  
(2) The pixel clock frequency is programmable.  
(3) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.  
(4) For more information, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0).  
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6.5.2.1.2 LCD Display in STN Mode  
Table 6-37 assumes testing over the recommended operating conditions (see Figure 6-36).  
Table 6-37. LCD Display Interface Switching Characteristics in STN Mode(1) (2) (3)  
NO.  
PARAMETER  
1.8V, 3.3V  
MAX  
UNIT  
MIN  
-4.21  
22.73  
10.23  
DL3  
DL4  
DL5  
td(PCLKA-DATAV)  
tc(PCLK)  
Delay time, dss_pclk active edge to dss_data bus valid  
Cycle time(4), dss_pclk  
6.9  
ns  
ns  
ns  
pF  
tw(PCLK)  
Pulse duration, dss_pclk low or high  
Load capacitance  
12.5  
40  
cload  
(1) The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low.  
(2) The capacitive load is equivalent to 40 pF.  
(3) For more information, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0).  
(4) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the  
DISPC_DIVISOR register.  
DL5  
DL4  
dss_pclk  
dss_vsync  
dss_hsync  
dss_acbias  
DL3  
dss_data[23:0]  
030-062  
Figure 6-36. LCD Display in STN Mode(1) (2) (3) (4) (5)  
(1) The pixel data bus depends on the use 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins.  
(2) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.  
(3) dss_vsync width must be programmed to be as small as possible.  
(4) The pixel clock frequency is programmable.  
(5) For more information, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0).  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
6.6 Serial Communications Interfaces  
6.6.1 Multichannel Buffered Serial Port (McBSP) Timing  
There are five McBSP modules called McBSP1 through McBSP5. McBSP provides a full-duplex, direct  
serial interface between the AM3517/05 device and other devices in a system such as other application  
devices or codecs. It can accommodate a wide range of peripherals and clocked frame-oriented protocols  
(I2S, PCM, and TDM) due to its high level of versatility.  
The McBSP1-5 modules may support two types of data transfer at the system level:  
•
The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge  
and captured on the same edge (one clock period later).  
•
The half-cycle mode, for which one half clock period is used to transfer the data, generated on one  
edge and captured on the opposite edge (one half clock period later). Note that a new data is  
generated only every clock period, which secures the required hold time.  
The interface clock (CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be  
configured accordingly with the external peripheral (activation edge capability) and the type of data  
transfer required at the system level.  
The AM3517/05 McBSP1-5 timing characteristics are described for both rising and falling activation edges.  
McBSP1 supports:  
•
•
6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins.  
4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are  
internally looped back via software configuration, respectively, to the clkr and fsr internal signals for  
data receive.  
McBSP2, 3, 4, and 5 support only the 4-pin mode.  
The following sections describe the timing characteristics for applications in normal mode (that is,  
AM3517/05 McBSPx connected to one peripheral) and TDM applications in multipoint mode.  
6.6.1.1 McBSP in Normal Mode  
The following tables assume=testing over the recommended operating conditions.  
Table 6-38. McBSP Timing Conditions  
TIMING CONDITION PARAMETER  
Input Conditions  
1.8V, 3.3 V  
UNIT  
VALUE  
2(1)  
tR  
Input signal rise time  
Input signal fall time  
ns  
ns  
tF  
2
Output Conditions  
CLOAD  
Output load  
capacitance  
10  
pF  
(1) Maximum value.  
Table 6-39. McBSP1,2,4,5 Output Clock Pulse Duration  
PARAMETER  
VDDSHV = 1.8V, 3.3V  
UNIT  
MIN  
MAX  
tC(CLK)  
Cycle Time,  
20.83  
ns  
ns  
mcbsp1_clkr/mcbspx_clkx  
(1)  
tW(CLKH)  
Typical pulse duration,  
mcbsp1_clkr /  
0.5*P(2)  
0.5*P(2)  
mcbspx_clkx high(1)  
(1) In mcbspx, x identifies the McBSP number; 1, 2, 4, or 5.  
(2) P = mcbsp1_clkr / mcbspx_clkx clock period.  
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Table 6-39. McBSP1,2,4,5 Output Clock Pulse Duration (continued)  
PARAMETER  
VDDSHV = 1.8V, 3.3V  
0.5*P(2)  
UNIT  
tW(CLKL)  
Typical pulse duration,  
mcbsp1_clkr /  
0.5*P(2)  
0.75  
ns  
mcbspx_clkx low(1)  
tdc(CLK)  
Duty cycle error,  
mcbsp1_clkr /  
mcbspx_clkx(1)  
-0.75  
ns  
Table 6-40. McBSP3 Output Clock Pulse Duration  
PARAMETER  
VDDSHV = 1.8V, 3.3V  
UNIT  
MIN  
MAX  
tC(CLK)  
Cycle time, mcbsp3_clkx  
31.25  
0.5*P(1)  
ns  
ns  
tW(CLKH)  
Typical pulse duration,  
mcbsp3_clkx high  
0.5*P(1)  
0.5*P(1)  
0.75  
tW(CLKL)  
tdc(CLK)  
Typical pulse duration,  
mcbsp3_clkx low  
0.5*P(1)  
-0.75  
ns  
ns  
Duty cycle error,  
mcbsp3_clkx  
(1) P = mcbsp3_clkx clock period  
6.6.1.1.1 McBSP1  
The following tables show the timing requirements and switching characteristics for McBSP1.  
Table 6-41. McBSP1 Timing Requirements - Rising Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV=3.3V  
VDDSHV=1.8V  
UNIT  
MIN  
5.0  
MAX  
MIN  
5.0  
MAX  
B3  
tsu(DRV-  
CLKAE)  
Setup time,  
mcbsp1_dr  
valid before  
mcbsp1_clkr /  
mcbsp1_clkx  
active edge  
Half Cycle  
Master  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Half Cycle  
Slave  
5.2  
4.0  
4.2  
5.8  
5.2  
1.5  
0.9  
5.2  
4.2  
5.2  
4.0  
4.2  
5.8  
5.2  
1.5  
0.9  
5.2  
4.2  
Full Cycle  
Master  
Full Cycle  
Slave  
B4  
th(CLKAE-  
DRV)  
Hold time,  
mcbsp1_dr  
valid after  
mcbsp1_clkr /  
mcbsp1_clkx  
active edge  
Half Cycle  
Master  
Half Cycle  
Slave  
Full Cycle  
Master  
Full Cycle  
Slave  
B5  
B6  
tsu(FSV-  
CLKAE)  
Setup time,  
mcbsp1_fsr /  
mcbsp1_fsx  
valid before  
mcbsp1_clkr /  
mcbsp1_clkx  
active edge  
Half Cycle  
Slave  
Full Cycle  
Slave  
th(CLKAE-FSV) Hold time,  
mcbsp1_fsr /  
Half Cycle  
Slave  
0.5  
1.0  
0.5  
1.0  
ns  
ns  
mcbsp1_fsx  
valid after  
mcbsp1_clkr /  
mcbsp1_clkx  
Full Cycle  
Slave  
active edge  
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Table 6-42. McBSP1 Switching Characteristics - Rising Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV=3.3V  
MAX  
VDDSHV=1.8V  
MAX  
UNIT  
MIN  
0.2  
MIN  
0.2  
B2  
td(CLKAE-FSV) Delay time,  
mcbsp1_clkr  
14.8  
14.8  
ns  
active edge to  
mcbsp1_fsr /  
mcbsp1_fsx  
valid  
Table 6-43. McBSP1 Timing Requirements - Rising Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
5.2  
MAX  
MIN  
4.7  
MAX  
B5  
tsu(FSXV-  
CLKXAE)  
Setup time,  
mcbsp1_fsx  
valid before  
mcbsp1_clkx  
active edge  
Full Cycle  
Slave  
ns  
ns  
Half Cycle  
Slave  
4.2  
3.7  
B6  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp1_fsx  
valid after  
mcbsp1_clkx  
active edge  
Full Cycle  
Slave  
5.2  
1.0  
4.7  
0.5  
ns  
ns  
Half Cycle  
Slave  
Table 6-44. McBSP1 Switching Characteristics - Rising Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
14.8  
MIN  
0.7  
MAX  
14.8  
B2  
td(CLKXAE-  
FSXV)  
Delay time,  
mcbsp1_clkx  
active edge to  
mcbsp1_fsx  
valid  
ns  
B8  
td(CLKXAE-  
DXV)  
Delay time,  
mcbsp1_clkx  
active edge to  
mcbsp1_dx  
valid  
Master  
Slave  
0.6  
0.6  
14.8  
14.8  
0.6  
0.6  
14.8  
14.8  
ns  
ns  
Table 6-45. McBSP1 Timing Requirements - Falling Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
5.0  
MAX  
MIN  
5.0  
MAX  
B3  
tsu(DRV-  
CLKAE)  
Setup time,  
mcbsp1_dr  
valid before  
mcbsp1_clkr /  
mcbsp1_clkx  
active edge  
Half Cycle  
Master  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Half Cycle  
Slave  
5.2  
4.0  
4.2  
5.8  
5.2  
1.5  
0.9  
5.2  
4.2  
5.2  
4.0  
4.2  
5.8  
5.2  
1.5  
0.9  
5.2  
4.2  
Full Cycle  
Master  
Full Cycle  
Slave  
B4  
th(CLKAE-  
DRV)  
Hold time,  
mcbsp1_dr  
valid after  
mcbsp1_clkr /  
mcbsp1_clkx  
active edge  
Half Cycle  
Master  
Half Cycle  
Slave  
Full Cycle  
Master  
Full Cycle  
Slave  
B5  
tsu(FSV-  
CLKAE)  
Setup time,  
mcbsp1_fsr /  
mcbsp1_fsx  
valid before  
mcbsp1_clkr /  
mcbsp1_clkx  
active edge  
Half Cycle  
Slave  
Full Cycle  
Slave  
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Table 6-45. McBSP1 Timing Requirements - Falling Edge and Receive Mode (continued)  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
B6  
th(CLKAE-FSV) Hold time,  
mcbsp1_fsr /  
Half Cycle  
Slave  
0.5  
1.0  
0.5  
1.0  
ns  
mcbsp1_fsx  
valid after  
mcbsp1_clkr /  
mcbsp1_clkx  
Full Cycle  
Slave  
ns  
active edge  
Table 6-46. McBSP1 Switching Characteristics - Falling Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
14.8  
MIN  
0.7  
MAX  
14.8  
B2  
td(CLKAE-FSV) Delay time, mcbsp1_clkr /  
mcbsp1_clkx active edge to  
ns  
mcbsp1_fsr / mcbsp1_fsx valid  
Table 6-47. McBSP1 Timing Requirements - Falling Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
5.2  
MAX  
MIN  
5.2  
MAX  
B5  
tsu(FSXV-  
CLKXAE)  
Setup time,  
mcbsp1_fsx  
valid before  
mcbsp1_clkx  
active edge  
Half Cycle  
Slave  
ns  
ns  
Full Cycle  
Slave  
4.2  
4.2  
B6  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp1_fsx  
valid after  
mcbsp1_clkx  
active edge  
Half Cycle  
Slave  
5.2  
1.0  
5.2  
1.0  
ns  
ns  
Full Cycle  
Slave  
Table 6-48. McBSP1 Switching Characteristics - Falling Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
14.8  
MIN  
0.2  
MAX  
14.8  
B2  
td(CLKXAE-  
FSXV)  
Delay time,  
mcbsp1_clkx  
active edge to  
mcbsp1_fsx  
valid  
ns  
B8  
td(CLKXAE-  
DXV)  
Delay time,  
mcbsp1_clkx  
active edge to  
mcbsp1_dx  
valid  
Master  
Slave  
0.6  
0.6  
14.8  
14.8  
0.6  
0.6  
14.8  
14.8  
ns  
ns  
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6.6.1.1.2 McBSP2  
The following tables show the timing requirements and switching characteristics for McBSP2.  
Table 6-49. McBSP2 Timing Requirements - Rising Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
5.0  
MAX  
MIN  
5.0  
MAX  
B3  
tsu(DRV-  
CLKXAE)  
Setup time,  
mcbsp2_dr  
valid before  
mcbsp2_clkx  
active edge  
Half Cycle  
Master  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Half Cycle  
Slave  
5.2  
4.2  
4.2  
5.8  
5.2  
1.5  
0.9  
5.2  
4.2  
5.2  
4.2  
4.2  
5.8  
5.2  
1.5  
0.9  
5.2  
4.2  
Full Cycle  
Master  
Full Cycle  
Slave  
B4  
th(CLKXAE-  
DRV)  
Hold time,  
mcbsp2_dr  
valid after  
mcbsp2_clkx  
active edge  
Half Cycle  
Master  
Half Cycle  
Slave  
Full Cycle  
Master  
Full Cycle  
Slave  
B5  
B6  
tsu(FSV-  
CLKXAE)  
Setup time,  
mcbsp2_fsx  
valid before  
mcbsp2_clkx  
active edge  
Half Cycle  
Slave  
Full Cycle  
Slave  
th(CLKXAE-  
FSV)  
Hold time,  
mcbsp2_fsx  
valid after  
mcbsp2_clkx  
active edge  
Half Cycle  
Slave  
5.2  
1.0  
5.2  
1.0  
ns  
ns  
Full Cycle  
Slave  
Table 6-50. McBSP2 Switching Characteristics - Rising Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
14.8  
MIN  
0.2  
MAX  
14.8  
B2  
td(CLKXAE-  
FSXV)  
Delay time,  
mcbsp2_clkx  
active edge to  
mcbsp2_fsx  
valid  
ns  
Table 6-51. McBSP2 Timing Requirements - Rising Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
5.2  
MAX  
MIN  
4.7  
MAX  
B5  
tsu(FSXV-  
CLKXAE)  
Setup time,  
mcbsp2_fsx  
valid before  
mcbsp2_clkx  
active edge  
Half Cycle  
Slave  
ns  
ns  
Full Cycle  
Slave  
4.2  
3.7  
B6  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp2_fsx  
valid after  
mcbsp2_clkx  
active edge  
Half Cycle  
Slave  
5.2  
1.0  
4.7  
0.5  
ns  
ns  
Full Cycle  
Slave  
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Table 6-52. McBSP2 Switching Characteristics - Rising Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
14.8  
MIN  
0.2  
MAX  
14.8  
B2  
td(CLKXAE-  
FSXV)  
Delay time,  
mcbsp2_clkx  
active edge to  
mcbsp2_fsx  
valid  
ns  
B8  
td(CLKXAE-  
DXV)  
Delay time,  
mcbsp2_clkx  
active edge to  
mcbsp2_dx  
valid  
Master  
Slave  
0.6  
0.6  
14.8  
14.8  
0.6  
0.6  
14.8  
14.8  
ns  
ns  
Table 6-53. McBSP2 Timing Requirements - Falling Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
5.0  
MAX  
MIN  
5.0  
MAX  
B3  
tsu(DRV-  
CLKXAE)  
Setup time,  
mcbsp2_dr  
valid before  
mcbsp2_clkx  
active edge  
Half Cycle  
Master  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Half Cycle  
Slave  
5.2  
4.2  
4.2  
5.8  
5.2  
1.5  
0.9  
5.2  
4.2  
5.2  
4.2  
4.2  
5.8  
5.2  
1.5  
0.9  
5.2  
4.2  
Full Cycle  
Master  
Full Cycle  
Slave  
B4  
th(CLKXAE-  
DRV)  
Hold time,  
mcbsp2_dr  
valid after  
mcbsp2_clkx  
active edge  
Half Cycle  
Master  
Half Cycle  
Slave  
Full Cycle  
Master  
Full Cycle  
Slave  
B5  
B6  
tsu(FSXV-  
CLKXAE)  
Setup time,  
mcbsp2_fsx  
valid before  
mcbsp2_clkx  
active edge  
Half Cycle  
Slave  
Full Cycle  
Slave  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp2_fsx  
valid after  
mcbsp2_clkx  
active edge  
Half Cycle  
Slave  
5.2  
1.0  
5.2  
1.0  
ns  
ns  
Full Cycle  
Slave  
Table 6-54. McBSP2 Switching Characteristics - Falling Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
14.8  
MIN  
0.2  
MAX  
14.8  
B2  
td(CLKXAE-  
FSXV)  
Delay time, mcbsp2_clkx active  
edge to mcbsp2_fsx valid  
ns  
Table 6-55. McBSP2 Timing Requirements - Falling Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
5.2  
MAX  
MIN  
5.2  
MAX  
B5  
tsu(FSXV-  
CLKXAE)  
Setup time,  
mcbsp2_fsx  
valid before  
mcbsp2_clkx  
active edge  
Half Cycle  
Slave  
ns  
ns  
Full Cycle  
Slave  
4.2  
4.2  
160  
Timing Requirements and Switching Characteristics  
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Table 6-55. McBSP2 Timing Requirements - Falling Edge and Transmit Mode (continued)  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
B6  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp2_fsx  
valid after  
mcbsp2_clkx  
active edge  
Half Cycle  
Slave  
5.2  
1.0  
5.2  
1.0  
ns  
Full Cycle  
Slave  
ns  
Table 6-56. McBSP2 Switching Characteristics - Falling Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
14.8  
MIN  
0.2  
MAX  
14.8  
B2  
B8  
td(CLKXAE-  
FSXV)  
Delay time, mcbsp2_clkx active  
edge to mcbsp2_fsx valid  
ns  
td(CLKXAE-  
DXV)  
Delay time,  
mcbsp2_clkx  
active edge to  
mcbsp2_dx  
valid  
Master  
Slave  
0.6  
0.6  
14.8  
14.8  
0.6  
0.6  
14.8  
14.8  
ns  
ns  
6.6.1.1.3 McBSP3  
6.6.1.1.3.1 McBSP3 Multiplexed on McBSP3 Pins  
The following tables show the timing conditions and switching characteristics for McBSP3 multiplexed on  
McBSP3 pins.  
Note: All timings apply only to Set #1- multiplexing on mcbsp3 pins.  
Table 6-57. McBSP3 (Set #1) Timing Requirements - Rising Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
7.5  
MAX  
MIN  
7.5  
MAX  
B3  
tsu(DRV-  
CLKXAE)  
Setup time,  
mcbsp3_dr  
valid before  
mcbsp3_clkx  
active edge  
Half Cycle  
Master  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Half Cycle  
Slave  
7.7  
5.6  
5.8  
8.3  
7.7  
1.5  
0.9  
7.7  
5.8  
7.7  
5.6  
5.8  
8.3  
7.7  
1.5  
0.9  
7.7  
5.8  
Full Cycle  
Master  
Full Cycle  
Slave  
B4  
th(CLKXAE-  
DRV)  
Hold time,  
mcbsp3_dr  
valid after  
mcbsp3_clkx  
active edge  
Half Cycle  
Master  
Half Cycle  
Slave  
Full Cycle  
Master  
Full Cycle  
Slave  
B5  
B6  
tsu(FSV-  
CLKXAE)  
Setup time,  
mcbsp3_fsx  
valid before  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
Full Cycle  
Slave  
th(CLKXAE-  
FSV)  
Hold time,  
mcbsp3_fsx  
valid after  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
7.7  
1.0  
7.7  
1.0  
ns  
ns  
Full Cycle  
Slave  
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Table 6-58. McBSP3 (Set #1) Switching Characteristics - Rising Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
22.2  
MIN  
0.2  
MAX  
22.2  
B2  
td(CLKXAE-  
FSXV)  
Delay time, mcbsp3_clkx active  
edge to mcbsp3_fsx valid  
ns  
Table 6-59. McBSP3 (Set #1) Timing Requirements - Rising Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
7.7  
MAX  
MIN  
7.7  
MAX  
B5  
tsu(FSXV-  
CLKXAE)  
Setup time,  
mcbsp3_fsx  
valid before  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
ns  
ns  
Full Cycle  
Slave  
5.8  
5.8  
B6  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp3_fsx  
valid after  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
7.7  
1
7.7  
1
ns  
ns  
Full Cycle  
Slave  
Table 6-60. McBSP3 (Set #1) Switching Characteristics - Rising Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
22.2  
MIN  
0.2  
MAX  
22.2  
B2  
B8  
td(CLKXAE-  
FSXV)  
Delay time, mcbsp3_clkx active  
edge to mcbsp3_fsx valid  
ns  
td(CLKXAE-  
DXV)  
Delay time,  
mcbsp3_clkx  
active edge to  
mcbsp3_dx  
valid  
Master  
Slave  
0.6  
0.6  
22.2  
22.2  
0.6  
0.6  
22.2  
22.2  
ns  
ns  
Table 6-61. McBSP3 (Set #1) Timing Requirements - Falling Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
7.5  
MAX  
MIN  
7.5  
MAX  
tsu(DRV-  
CLKXAE)  
Setup time,  
mcbsp3_dr  
valid before  
mcbsp3_clkx  
active edge  
Half Cycle  
Master  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Half Cycle  
Slave  
7.7  
5.6  
5.8  
8.3  
7.7  
1.5  
0.9  
7.7  
5.8  
7.7  
5.6  
5.8  
8.3  
7.7  
1.5  
0.9  
7.7  
5.8  
Full Cycle  
Master  
Full Cycle  
Slave  
th(CLKXAE-  
DRV)  
Hold time,  
mcbsp3_dr  
valid after  
mcbsp3_clkx  
active edge  
Half Cycle  
Master  
Half Cycle  
Slave  
Full Cycle  
Master  
Full Cycle  
Slave  
B5  
B6  
tsu(FXSV-  
CLKXAE)  
Setup time,  
mcbsp3_fsx  
valid before  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
Full Cycle  
Slave  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp3_fsx  
valid after  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
7.7  
1.0  
7.7  
1.0  
ns  
ns  
Full Cycle  
Slave  
162  
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Table 6-62. McBSP3 (Set #1) Switching Characteristics - Falling Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
22.2  
MIN  
0.2  
MAX  
22.2  
B2  
td(CLKXAE-  
FSXV)  
Delay time, mcbsp3_clkx active  
edge to mcbsp3_fsx valid  
ns  
Table 6-63. McBSP3 (Set #1) Timing Requirements - Falling Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
5.2  
MAX  
MIN  
5.2  
MAX  
B5  
tsu(FSXV-  
CLKXAE)  
Setup time,  
mcbsp3_fsx  
valid before  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
ns  
ns  
Full Cycle  
Slave  
4.2  
4.2  
B6  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp3_fsx  
valid after  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
5.2  
1.0  
5.2  
1.0  
ns  
ns  
Full Cycle  
Slave  
Table 6-64. McBSP3 (Set #1) Switching Characteristics - Falling Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
22.2  
MIN  
0.2  
MAX  
22.2  
B2  
B8  
td(CLKXAE-  
FSXV)  
Delay time, mcbsp3_clkx active  
edge to mcbsp3_fsx valid  
ns  
td(CLKXAE-  
DXV)  
Delay time,  
mcbsp3_clkx  
active edge to  
mcbsp3_dx  
valid  
Master  
Slave  
0.6  
0.6  
22.2  
22.2  
0.6  
0.6  
22.2  
22.2  
ns  
ns  
6.6.1.1.3.2 McBSP3 Multiplexed on UART2 or McBSP1 Pins  
The following tables show the timing conditions and switching characteristics for McBSP3 multiplexed on  
UART2 or McBSP1 pins.  
Note: These timings only apply to Set #2 (multiplexing mode on uart2 pins) and Set #3 (multiplexing on  
mcbsp1 pins).  
Table 6-65. McBSP3 (Sets #2 and #3) Timing Requirements - Rising Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
5.0  
MAX  
MIN  
5.0  
MAX  
B3  
tsu(DRV-  
CLKXAE)  
Setup time,  
mcbsp3_dr  
valid before  
mcbsp3_clkx  
active edge  
Half Cycle  
Master  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Half Cycle  
Slave  
5.2  
4.2  
4.2  
5.8  
5.2  
1.5  
0.9  
5.2  
4.2  
4.2  
5.8  
5.2  
1.5  
0.9  
Full Cycle  
Master  
Full Cycle  
Slave  
B4  
th(CLKXAE-  
DRV)  
Hold time,  
mcbsp3_dr  
valid after  
mcbsp3_clkx  
active edge  
Half Cycle  
Master  
Half Cycle  
Slave  
Full Cycle  
Master  
Full Cycle  
Slave  
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Table 6-65. McBSP3 (Sets #2 and #3) Timing Requirements - Rising Edge and Receive Mode (continued)  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
B5  
tsu(FSV-  
CLKXAE)  
Setup time,  
mcbsp3_fsx  
valid before  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
5.2  
4.2  
5.2  
4.2  
ns  
Full Cycle  
Slave  
ns  
B6  
th(CLKXAE-  
FSV)  
Hold time,  
mcbsp3_fsx  
valid after  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
5.2  
1.0  
5.2  
1.0  
ns  
ns  
Full Cycle  
Slave  
Table 6-66. McBSP3 (Sets #2 and #3) Switching Characteristics - Rising Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
14.8  
MIN  
0.2  
MAX  
14.8  
B2  
td(CLKXAE-  
FSXV)  
Delay time,  
mcbsp3_clkx  
active edge to  
mcbsp3_fsx  
valid  
ns  
Table 6-67. McBSP3 (Sets #2 and #3) Timing Requirements - Rising Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
5.2  
MAX  
MIN  
5.2  
MAX  
B5  
tsu(FSXV-  
CLKXAE)  
Setup time,  
mcbsp3_fsx  
valid before  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
ns  
ns  
Full Cycle  
Slave  
4.2  
4.2  
B6  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp3_fsx  
valid after  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
5.2  
1.0  
5.2  
1.0  
ns  
ns  
Full Cycle  
Slave  
Table 6-68. McBSP3 (Sets #2 and #3) Switching Characteristics - Rising Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
14.8  
MIN  
0.2  
MAX  
14.8  
B2  
B8  
td(CLKXAE-  
FSXV)  
Delay time, mcbsp3_clkx active  
edge to mcbsp3_fsx valid  
ns  
td(CLKXAE-  
DXV)  
Delay time,  
mcbsp3_clkx  
active edge to  
mcbsp3_dx  
valid  
Master  
Slave  
0.6  
0.6  
14.8  
14.8  
0.6  
0.6  
14.8  
14.8  
ns  
ns  
Table 6-69. McBSP3 (Sets #2 and #3) Timing Requirements - Falling Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
5.0  
MAX  
MIN  
5.0  
MAX  
B3  
tsu(DRV-  
CLKXAE)  
Setup time,  
mcbsp3_dr  
valid before  
mcbsp3_clkx  
active edge  
Half Cycle  
Master  
ns  
ns  
ns  
ns  
Half Cycle  
Slave  
5.2  
4.2  
4.2  
5.2  
4.2  
4.2  
Full Cycle  
Master  
Full Cycle  
Slave  
164  
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Table 6-69. McBSP3 (Sets #2 and #3) Timing Requirements - Falling Edge and Receive Mode (continued)  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
B4  
th(CLKXAE-  
DRV)  
Hold time,  
mcbsp3_dr  
valid after  
mcbsp3_clkx  
active edge  
Half Cycle  
Master  
5.8  
5.2  
1.5  
0.9  
5.2  
4.2  
5.8  
5.2  
1.5  
0.9  
5.2  
4.2  
ns  
Half Cycle  
Slave  
ns  
ns  
ns  
ns  
ns  
Full Cycle  
Master  
Full Cycle  
Slave  
B5  
B6  
tsu(FXSV-  
CLKXAE)  
Setup time,  
mcbsp3_fsx  
valid before  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
Full Cycle  
Slave  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp3_fsx  
valid after  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
5.2  
1.0  
5.2  
1.0  
ns  
ns  
Full Cycle  
Slave  
Table 6-70. McBSP3 (Sets #2 and #3) Switching Characteristics - Falling Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
14.8  
MIN  
0.2  
MAX  
14.8  
B2  
td(CLKXAE-  
FSXV)  
Delay time, mcbsp3_clkx active  
edge to mcbsp3_fsx valid  
ns  
Table 6-71. McBSP3 (Sets #2 and #3) Timing Requirements - Falling Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
5.2  
MAX  
MIN  
5.2  
MAX  
B5  
tsu(FSXV-  
CLKXAE)  
Setup time,  
mcbsp3_fsx  
valid before  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
ns  
ns  
Full Cycle  
Slave  
4.2  
4.2  
B6  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp3_fsx  
valid after  
mcbsp3_clkx  
active edge  
Half Cycle  
Slave  
5.2  
1.0  
5.2  
1.0  
ns  
ns  
Full Cycle  
Slave  
Table 6-72. McBSP3 (Sets #2 and #3) Switching Characteristics - Falling Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1 .8V  
UNIT  
MIN  
0.2  
MAX  
14.8  
MIN  
0.2  
MAX  
14.8  
B2  
B8  
td(CLKXAE-  
FSXV)  
Delay time, mcbsp3_clkx active  
edge to mcbsp3_fsx valid  
ns  
ns  
td(CLKXAE-  
DXV)  
Delay time,  
mcbsp3_clkx  
active edge to  
mcbsp3_dx  
valid  
Master  
0.6  
14.8  
0.6  
14.8  
Slave  
0.6  
14.8  
0.6  
14.8  
ns  
6.6.1.1.4 McBSP4  
The following tables show the timing requirements and switching characteristics for McBSP4.  
Table 6-73. McBSP4 Timing Requirements - Rising Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
MAX  
MIN  
MAX  
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Table 6-73. McBSP4 Timing Requirements - Rising Edge and Receive Mode (continued)  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
B3  
tsu(DRV-  
CLKXAE)  
Setup time,  
mcbsp4_dr  
valid before  
mcbsp4_clkx  
active edge  
Half Cycle  
Master  
7.5  
7.7  
3.2  
4.2  
7.7  
5.2  
1.5  
0.9  
7.7  
4.2  
7.5  
7.7  
3.2  
4.2  
7.7  
5.2  
1.5  
0.9  
7.7  
4.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Half Cycle  
Slave  
Full Cycle  
Master  
Full Cycle  
Slave  
B4  
th(CLKXAE-  
DRV)  
Hold time,  
mcbsp4_dr  
valid after  
mcbsp4_clkx  
active edge  
Half Cycle  
Master  
Half Cycle  
Slave  
Full Cycle  
Master  
Full Cycle  
Slave  
B5  
B6  
tsu(FSV-  
CLKXAE)  
Setup time,  
mcbsp4_fsx  
valid before  
mcbsp4_clkx  
active edge  
Half Cycle  
Slave  
Full Cycle  
Slave  
th(CLKXAE-  
FSV)  
Hold time,  
mcbsp4_fsx  
valid after  
mcbsp4_clkx  
active edge  
Half Cycle  
Slave  
5.2  
1.0  
5.2  
1.0  
ns  
ns  
Full Cycle  
Slave  
Table 6-74. McBSP4 Switching Characteristics - Rising Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
16.6  
MIN  
0.2  
MAX  
16.6  
B2  
td(CLKXAE-  
FSXV)  
Delay time,  
mcbsp4_clkx  
active edge to  
mcbsp4_fsx  
valid  
ns  
Table 6-75. McBSP4 Timing Requirements - Rising Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
7.7  
MAX  
MIN  
7.7  
MAX  
B5  
tsu(FSXV-  
CLKXAE)  
Setup time,  
mcbsp4_fsx  
valid before  
mcbsp4_clkx  
active edge  
Half Cycle  
Slave  
ns  
ns  
Full Cycle  
Slave  
3.7  
3.7  
B6  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp4_fsx  
valid after  
mcbsp4_clkx  
active edge  
Half Cycle  
Slave  
1.0  
1.0  
1.0  
1.0  
ns  
ns  
Full Cycle  
Slave  
Table 6-76. McBSP4 Switching Characteristics - Rising Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
16.6  
MIN  
0.2  
MAX  
16.6  
B2  
td(CLKXAE-  
FSXV)  
Delay time,  
mcbsp4_clkx  
active edge to  
mcbsp4_fsx  
valid  
ns  
166  
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Table 6-76. McBSP4 Switching Characteristics - Rising Edge and Transmit Mode (continued)  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
ns  
B8  
td(CLKXAE-  
DXV)  
Delay time,  
mcbsp4_clkx  
active edge to  
mcbsp4_dx  
valid  
Master  
Slave  
0.6  
0.6  
16.6  
17.3  
0.6  
0.6  
16.6  
17.3  
ns  
Table 6-77. McBSP4 Timing Requirements - Falling Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
7.5  
MAX  
MIN  
7.5  
MAX  
B3  
tsu(DRV-  
CLKXAE)  
Setup time,  
mcbsp4_dr  
valid before  
mcbsp4_clkx  
active edge  
Half Cycle  
Master  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Half Cycle  
Slave  
7.7  
5.6  
5.8  
7.7  
5.2  
1.5  
0.9  
7.7  
5.8  
7.7  
5.6  
5.8  
7.7  
5.2  
1.5  
0.9  
7.7  
5.8  
Full Cycle  
Master  
Full Cycle  
Slave  
B4  
th(CLKXAE-  
DRV)  
Hold time,  
mcbsp4_dr  
valid after  
mcbsp4_clkx  
active edge  
Half Cycle  
Master  
Half Cycle  
Slave  
Full Cycle  
Master  
Full Cycle  
Slave  
B5  
B6  
tsu(FXSV-  
CLKXAE)  
Setup time,  
mcbsp4_fsx  
valid before  
mcbsp4_clkx  
active edge  
Half Cycle  
Slave  
Full Cycle  
Slave  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp4_fsx  
valid after  
Half Cycle  
Slave  
5.2  
5.2  
ns  
mcbsp4_clkx  
active edge  
Full Cycle  
Slave  
1.0  
1.0  
ns  
Table 6-78. McBSP4 Switching Characteristics - Falling Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
16.6  
MIN  
0.2  
MAX  
16.6  
B2  
td(CLKXAE-  
FSXV)  
Delay time, mcbsp4_clkx active  
edge to mcbsp4_fsx valid  
ns  
Table 6-79. McBSP4 Timing Requirements - Falling Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
7.7  
MAX  
MIN  
7.7  
MAX  
B5  
tsu(FSXV-  
CLKXAE)  
Setup time,  
mcbsp4_fsx  
valid before  
mcbsp4_clkx  
active edge  
Half Cycle  
Slave  
ns  
ns  
Full Cycle  
Slave  
3.7  
3.7  
B6  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp4_fsx  
valid after  
mcbsp4_clkx  
active edge  
Half Cycle  
Slave  
5.2  
1.0  
5.2  
1.0  
ns  
ns  
Full Cycle  
Slave  
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Table 6-80. McBSP4 Switching Characteristics - Falling Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
16.6  
MIN  
0.2  
MAX  
16.6  
B2  
B8  
td(CLKXAE-  
FSXV)  
Delay time, mcbsp4_clkx active  
edge to mcbsp4_fsx valid  
ns  
ns  
ns  
td(CLKXAE-  
DXV)  
Delay time,  
mcbsp4_clkx  
active edge to  
mcbsp4_dx  
valid  
Master  
0.6  
0.6  
16.6  
17.3  
0.6  
0.6  
16.6  
17.3  
Slave  
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6.6.1.1.5 McBSP5  
The following tables show the timing conditions and switching characteristics for McBSP5.  
Table 6-81. McBSP5 Timing Requirements - Rising Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
7.5  
MAX  
MIN  
7.5  
MAX  
B3  
tsu(DRV-  
CLKXAE)  
Setup time,  
mcbsp5_dr  
valid before  
mcbsp5_clkx  
active edge  
Half Cycle  
Master  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Half Cycle  
Slave  
7.7  
5.6  
5.8  
7.5  
7.7  
1.5  
0.9  
7.7  
5.8  
7.7  
5.6  
5.8  
7.5  
7.7  
1.5  
0.9  
7.7  
5.8  
Full Cycle  
Master  
Full Cycle  
Slave  
B4  
th(CLKXAE-  
DRV)  
Hold time,  
mcbsp5_dr  
valid after  
mcbsp5_clkx  
active edge  
Half Cycle  
Master  
Half Cycle  
Slave  
Full Cycle  
Master  
Full Cycle  
Slave  
B5  
B6  
tsu(FSV-  
CLKXAE)  
Setup time,  
mcbsp5_fsx  
valid before  
mcbsp5_clkx  
active edge  
Half Cycle  
Slave  
Full Cycle  
Slave  
th(CLKXAE-  
FSV)  
Hold time,  
mcbsp5_fsx  
valid after  
mcbsp5_clkx  
active edge  
Half Cycle  
Slave  
7.7  
1.0  
7.7  
1.0  
ns  
ns  
Full Cycle  
Slave  
Table 6-82. McBSP5 Switching Characteristics - Rising Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
14.8  
MIN  
0.7  
MAX  
14.8  
B2  
td(CLKXAE-  
FSXV)  
Delay time, mcbsp5_clkx active  
edge to mcbsp5_fsx valid  
ns  
Table 6-83. McBSP5 Timing Requirements - Rising Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
7.7  
MAX  
MIN  
7.7  
MAX  
B5  
tsu(FSXV-  
CLKXAE)  
Setup time,  
mcbsp5_fsx  
valid before  
mcbsp5_clkx  
active edge  
Half Cycle  
Slave  
ns  
ns  
Full Cycle  
Slave  
5.8  
5.8  
B6  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp5_fsx  
valid after  
mcbsp5_clkx  
active edge  
Half Cycle  
Slave  
7.7  
1.0  
7.7  
1.0  
ns  
ns  
Full Cycle  
Slave  
Table 6-84. McBSP5 Switching Characteristics - Rising Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
14.8  
MIN  
0.2  
MAX  
14.8  
B2  
td(CLKXAE-  
FSXV)  
Delay time,  
mcbsp5_clkx  
active edge to  
mcbsp5_fsx  
valid  
ns  
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Table 6-84. McBSP5 Switching Characteristics - Rising Edge and Transmit Mode (continued)  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
ns  
B8  
td(CLKXAE-  
DXV)  
Delay time,  
mcbsp5_clkx  
active edge to  
mcbsp5_dx  
valid  
Master  
Slave  
0.6  
0.6  
14.8  
14.8  
0.6  
0.6  
14.8  
14.8  
ns  
Table 6-85. McBSP5 Timing Requirements - Falling Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
7.5  
MAX  
MIN  
7.5  
MAX  
B3  
tsu(DRV-  
CLKXAE)  
Setup time,  
mcbsp5_dr  
valid before  
mcbsp5_clkx  
active edge  
Half Cycle  
Master  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Half Cycle  
Slave  
7.7  
5.6  
5.8  
8.3  
7.7  
1.5  
0.9  
7.7  
5.8  
7.7  
5.6  
5.8  
8.3  
7.7  
1.5  
0.9  
7.7  
5.8  
Full Cycle  
Master  
Full Cycle  
Slave  
B4  
th(CLKXAE-  
DRV)  
Hold time,  
mcbsp5_dr  
valid after  
mcbsp5_clkx  
active edge  
Half Cycle  
Master  
Half Cycle  
Slave  
Full Cycle  
Master  
Full Cycle  
Slave  
B5  
B6  
tsu(FXSV-  
CLKXAE)  
Setup time,  
mcbsp5_fsx  
valid before  
mcbsp5_clkx  
active edge  
Half Cycle  
Slave  
Full Cycle  
Slave  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp5_fsx  
valid after  
mcbsp5_clkx  
active edge  
Half Cycle  
Slave  
7.7  
1.0  
7.7  
1.0  
ns  
ns  
Full Cycle  
Slave  
Table 6-86. McBSP5 Switching Characteristics - Falling Edge and Receive Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
22.2  
MIN  
0.2  
MAX  
22.2  
B2  
td(CLKXAE-  
FSXV)  
Delay time, mcbsp5_clkx active  
edge to mcbsp5_fsx valid  
ns  
Table 6-87. McBSP5 Timing Requirements - Falling Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
7.7  
MAX  
MIN  
7.7  
MAX  
B5  
tsu(FSXV-  
CLKXAE)  
Setup time,  
mcbsp5_fsx  
valid before  
mcbsp5_clkx  
active edge  
Half Cycle  
Slave  
ns  
ns  
Full Cycle  
Slave  
5.8  
5.8  
B6  
th(CLKXAE-  
FSXV)  
Hold time,  
mcbsp5_fsx  
valid after  
mcbsp5_clkx  
active edge  
Half Cycle  
Slave  
7.7  
1.0  
7.7  
1.0  
ns  
ns  
Full Cycle  
Slave  
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Table 6-88. McBSP5 Switching Characteristics - Falling Edge and Transmit Mode  
No.  
PARAMETER  
VDDSHV = 3.3V  
VDDSHV = 1.8V  
UNIT  
MIN  
0.2  
MAX  
22.2  
MIN  
0.2  
MAX  
22.2  
B2  
td(CLKXAE-  
FSXV)  
Delay time,  
mcbsp5_clkx  
active edge to  
mcbsp5_fsx  
valid  
ns  
B8  
td(CLKXAE-  
DXV)  
Delay time,  
mcbsp5_clkx  
active edge to  
mcbsp5_dx  
valid  
Master  
Slave  
0.6  
0.6  
22.2  
22.2  
0.6  
0.6  
22.2  
22.2  
ns  
ns  
6.6.1.1.6 McBSP in TDM Mode  
The following tables assume=testing over the recommended operating conditions.  
Table 6-89. McBSP Timing Conditions – TDM in Multipoint Mode  
PARAMETER  
DESCRIPTION  
VDDSHV = 1.8V or 3.3V  
UNIT  
MIN  
1
MAX  
8.5  
8.5  
40  
tr  
Input signal rise time  
Input signal fall time  
Output load capacitance  
ns  
ns  
pf  
tf  
1
Cload  
Table 6-90. McBSP Timing Requirements — TDM in Multipoint Mode  
INDEX  
PARAMETER  
DESCRIPTION  
VDDSHV = 1.8V or 3.3V  
MAX  
UNIT  
MIN  
162.8  
81.4  
81.4  
-8.14  
9
tw(CLKH)  
Cycle Time, mcbspx_clkx  
ns  
ns  
ns  
ns  
ns  
tw(CLKH)  
Typical Pulse duration, mcbspx_clkx high  
Typical Pulse duration, mcbspx_clkx low  
Duty cycle error, mcbspx_clkx  
tw(CLKL)  
tdc(CLK)  
8.14  
B3  
B4  
B5  
B6  
tsu(DRV-CLKAE)  
Setup time, mcbspx_dr valid before  
mcbspx_clkx active edge  
th(CLKAE-DRV)  
tsu(FSV-CLKAE)  
th(CLKAE-FSV)  
Hold time, mcbspx_dr valid after mcbspx_clkx  
active edge  
2.4  
9
ns  
ns  
ns  
Setup time, mcbspx_fsx valid before  
mcbspx_clkx active edge  
Hold time, mcbspx_fsx valid after mcbspx_clkx  
active edge  
2.4  
Table 6-91. McBSP Switching Characteristics — TDM in Multipoint Mode  
INDEX  
PARAMETER  
DESCRIPTION  
VDDSHV = 1.8V or 3.3V  
UNIT  
MIN  
MAX  
B8  
td(CLKXAE-DXV)  
Delay time, mcbspx_clkx active edge to  
mcbspx_dx valid  
0.6  
16.8  
ns  
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6.6.1.1.7 McBSP Timing Diagrams  
mcbspx_clkr  
B2  
B2  
mcbspx_fsr  
B3  
B4  
mcbspx_dr  
D7  
D6  
D5  
030-068  
Figure 6-37. McBSP Rising Edge Receive Timing in Master Mode  
mcbspx_clkr  
mcbspx_fsr  
mcbspx_dr  
B5  
B6  
B3  
B4  
D7  
D6  
D5  
030-069  
Figure 6-38. McBSP Rising Edge Receive Timing in Slave Mode  
mcbspx_clkx  
mcbspx_fsx  
mcbspx_dx  
B2  
B2  
B8  
D7  
D6  
D5  
030-070  
Figure 6-39. McBSP Rising Edge Transmit Timing in Master Mode  
mcbspx_clkx  
mcbspx_fsx  
mcbspx_dx  
B5  
B6  
B8  
D7  
D6  
D5  
030-071  
Figure 6-40. McBSP Rising Edge Transmit Timing in Slave Mode  
mcbspx_clkr  
mcbspx_fsr  
mcbspx_dr  
B2  
B2  
B3  
B4  
D7  
D6  
D5  
030-072  
Figure 6-41. McBSP Falling Edge Receive Timing in Master Mode  
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mcbspx_clkr  
B5  
B6  
mcbspx_fsr  
mcbspx_dr  
B3  
B4  
D7  
D6  
D5  
030-073  
Figure 6-42. McBSP Falling Edge Receive Timing in Slave Mode  
mcbspx_clkx  
mcbspx_fsx  
mcbspx_dx  
B2  
B2  
B8  
D7  
D6  
D5  
030-074  
Figure 6-43. McBSP Falling Edge Transmit Timing in Master Mode  
mcbspx_clkx  
mcbspx_fsx  
mcbspx_dx  
B5  
B6  
B8  
D7  
D6  
D5  
030-075  
Figure 6-44. McBSP Falling Edge Transmit Timing in Slave Mode  
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6.6.2 Multichannel Serial Port Interface (McSPI) Timing  
The multichannel SPI is a master/slave synchronous serial bus. The McSPI1 module supports up to four  
peripherals and the others (McSPI2, McSPI3, and McSPI4) support up to two peripherals. The following  
timings are applicable to the different configurations of McSPI in master/slave mode for any McSPI and  
any channel (n).  
6.6.2.1 McSPI in Slave Mode  
The following tables assume testing over the recommended operating conditions.  
Table 6-92. McSPI Interface Timing Requirements – Slave Mode  
NO.  
PARAMETER  
1.8 V  
3.3 V  
UNIT  
MIN  
41.67  
18.75  
4.2  
MAX  
MIN  
41.67  
11.25  
4
MAX  
SS0 tc(CLK)  
Cycle time, mcspix_clk  
ns  
ns  
ns  
SS1 tw(CLK)  
Pulse duration, mcspix_clk high or low  
22.92  
SS2 tsu(SIMOV-CLKAE)  
Setup time, mcspix_simo valid before mcspix_clk  
active edge  
SS3 th(SIMOV-CLKAE)  
SS4 tsu(CS0V-CLKFE)  
SS5 th(CS0I-CLKLE)  
Hold time, mcspix_simo valid after mcspix_clk active  
edge  
4.6  
3
7
ns  
ns  
ns  
Setup time, mcspix_cs0 valid before mcspix_clk first  
edge  
13.8  
13.8  
Hold time, mcspix_cs0 invalid after mcspix_clk last  
edge  
9.17  
Table 6-93. McSPI Interface Switching Characteristics(1) (2) (3) (4)  
NO.  
PARAMETER  
1.8 V  
3.3 V  
UNIT  
MIN  
MAX  
MIN  
MAX  
SS6 td(CLKAE-SOMIV)  
SS7 td(CS0AE-SOMIV)  
Delay time, mcspix_clk active edge to mcspix_somi  
shifted  
1.8  
15.9  
2
16.5  
ns  
ns  
Delay time, mcspix_cs0 active edge to Modes 0 and 2  
mcspix_somi shifted  
16.38  
15.9  
(1) The capacitive load is equivalent to 20 pF.  
(2) In mcspix, x is equal to 1, 2, 3, or 4.  
(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all  
software configurable.  
(4) This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and  
capture input data.  
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Mode 0 & 2  
mcspix_cs0(EPOL=1)  
SS0  
SS1  
SS4  
SS5  
mcspix_clk(POL=0)  
mcspix_clk(POL=1)  
SS0  
SS1  
SS2  
SS3  
Bit n-1  
SS7  
Bit n-1  
mcspix_simo  
mcspix_somi  
Bit n-2  
SS6  
Bit n-3  
Bit n-4  
Bit 0  
Bit n-2  
Bit n-3  
Bit n-4  
Bit 0  
Mode 1 & 3  
mcspix_cs0(EPOL=1)  
mcspix_clk(POL=0)  
mcspix_clk(POL=1)  
SS0  
SS1  
SS0  
SS1  
SS4  
SS5  
SS3  
SS2  
Bit n-1  
SS6  
Bit n-1  
mcspix_simo  
mcspix_somi  
Bit n-2  
Bit n-2  
Bit n-3  
Bit 1  
Bit 0  
Bit n-3  
Bit 1  
Bit 0  
030-076  
Figure 6-45. McSPI Interface Transmit and Receive in Slave Mode(1) (2)  
(1) The active clock edge (rising or falling) on which mcspi_somi is driven and mcspi_simo data is latched is software configurable with the  
bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.  
(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL In mcspix, x is equal to 1, 2, 3, or 4.  
6.6.2.2 McSPI in Master Mode  
The following tables assume testing over the recommended operating conditions.  
Table 6-94. McSPI1, 2, and 4 Interface Timing Requirements – Master Mode(1) (2)  
NO.  
PARAMETER  
1.8 V  
3.3 V  
UNIT  
MIN  
MAX  
MIN  
MAX  
SM2 tsu(SOMIV-CLKAE)  
SM3 th(SOMIV-CLKAE)  
Setup time, mcspix_somi valid before mcspix_clk  
active edge  
2.56  
4
ns  
ns  
Hold time, mcspix_somi valid after mcspix_clk active  
edge  
2.93  
4
(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.  
(2) In mcspix, x is equal to 1, 2, 3, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 3.  
n is equal to 0 for x equal to 4.  
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UNIT  
Table 6-95. McSPI1, 2, and 4 Interface Switching Characteristics – Master Mode(1) (2) (3)  
NO.  
PARAMETER  
1.8 V  
3.3 V  
MIN  
20.83  
-200  
MAX  
MIN  
20.83  
-200  
MAX  
SM0  
tc(CLK)  
Cycle time, mcspix_clk  
Cycle jitter(4), mcspix_clk  
ns  
ps  
ns  
ns  
tj(CLK)  
200  
0.55P(5)  
5
200  
0.55P(5)  
6
SM1  
SM4  
tw(CLK)  
Pulse duration, mcspix_clk high or low  
0.45P(5)  
0.45P(5)  
td(CLKAE-SIMOV)  
Delay time, mcspix_clk active edge to  
mcspix_simo shifted  
-2.1  
-3  
SM5  
SM6  
SM7  
td(CSnA-CLKFE)  
td(CLKLE-CSnI)  
td(CSnAE-SIMOV)  
Delay time, mcspix_csi active to  
mcspix_clk first edge  
Modes 1  
and 3  
A(6) - 3.2  
B(7) - 3.2  
B(7) - 3.2  
A(6) - 3.2  
A(6) - 3.0  
B(7) -3.0  
B(7) - 3.0  
A(6) - 3.0  
6
6
ns  
ns  
ns  
ns  
ns  
Modes 0  
and 2  
Delay time, mcspix_clk last edge to  
mcspix_csi inactive  
Modes 1  
and 3  
Modes 0  
and 2  
Delay time, mcspix_csi active edge  
to mcspix_simo shifted  
Modes 0  
and 2  
5
5
(1) Timings are given for a maximum load capacitance of 20 pF for spix_csn signals, 30 pF for spix_clk and spix_simo signals with x = 1 or  
2, and 20 pF for spi4_clk and spi4_simo signals.  
(2) In mcspix, x is equal to 1, 2, 3, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 3.  
n is equal to 0 for x equal to 4.  
(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all  
software configurable.  
(4) Maximum cycle jitter supported by mcspix_clk input clock.  
(5) P = mcspix_clk clock period  
(6) Case P = 20.8 ns, A = (TCS+0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a  
bitfield of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port Interface (McSPI) Reference  
Guide [literature number SPRUFV6].  
(7) B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port  
Interface (McSPI) Reference Guide [literature number SPRUFV6].  
The following tables assume testing over the recommended operating conditions.  
Table 6-96. McSPI 3 Interface Timing Requirements – Master Mode(1) (2)  
NO.  
PARAMETER  
1.8 V  
3.3 V  
UNIT  
MIN  
MAX  
MIN  
MAX  
SM2 tsu(SOMIV-CLKAE)  
SM3 th(SOMIV-CLKAE)  
Setup time, mcspi3_somi valid before  
mcspi3_clk active edge  
2.5  
4
ns  
ns  
Hold time, mcspi3_somi valid after mcspi3_clk  
active edge  
2.89  
4
(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.  
(2) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and  
mcspi3_somi is latched is all software configurable.  
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Table 6-97. McSPI3 Interface Switching Characteristics – Master Mode(1) (2) (3)  
PARAMETER  
1.8 V  
3.3 V  
UNIT  
MIN  
41.67  
-200  
MAX  
MIN  
41.67  
-200  
MAX  
SM0 tc(CLK)  
tj(CLK)  
Cycle time, mcspix_clk  
Cycle jitter(4)  
ns  
ps  
ns  
ns  
200  
0.55P(5)  
200  
0.55P(5)  
SM1 tw(CLK)  
SM4 td(CLKAE-SIMOV)  
Pulse duration, mcspix_clk high or low  
0.45P(5)  
0.45P(5)  
Delay time, mcspix_clk active edge to  
mcspix_simo shifted  
-2.1  
11.3  
-3  
SM5 td(CSnA-CLKFE)  
SM6 td(CLKLE-CSnI)  
SM7 td(CSnAE-SIMOV)  
Delay time, mcspix_csi active Modes 1  
A(6) - 4.4  
B(7) - 4.4  
B(7) - 4.4  
A(6) - 4.4  
A(6) - 3.0  
B(7) - 3.0  
B(7) - 3.0  
A(6) - 3.0  
6
6
ns  
ns  
ns  
ns  
ns  
to mcspix_clk first edge  
and 3  
Modes 0  
and 2  
Delay time, mcspix_clk last  
edge to mcspix_csi inactive  
Modes 1  
and 3  
Modes 0  
and 2  
Delay time, mcspix_csi active Modes 0  
edge to mcspix_simo shifted and 2  
11.3  
5
(1) The capacitive load is equivalent to 20 pF.  
(2) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and  
mcspi3_somi is latched are all software configurable.  
(3) This timing applies to all configurations regardless of McSPI3_CLK polarity and which clock edges are used to drive output data and  
capture input data.  
(4) Maximum cycle jitter supported by mcspix_clk input clock.  
(5) P = mcspix_clk clock period.  
(6) Case P = 20.8 ns, A = (TCS + 0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a bit  
field of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port Interface (McSPI) Reference  
Guide [literature number SPRUFV6].  
(7) B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port  
Interface (McSPI) Reference Guide [literature number SPRUFV6].  
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Mode 0 & 2  
mcspix_csn(EPOL=1)  
SM0  
SM1  
SM5  
SM6  
mcspix_clk(POL=0)  
mcspix_clk(POL=1)  
SM0  
SM1  
SM7  
SM4  
Bit n-2  
mcspix_simo  
mcspix_somi  
Bit n-1  
SM2  
Bit n-3  
Bit n-4  
Bit n-4  
Bit 0  
SM3  
Bit n-1  
Bit n-2  
Bit n-3  
Bit 0  
Mode 1 & 3  
mcspix_csn(EPOL=1)  
mcspix_clk(POL=0)  
SM0  
SM1  
SM0  
SM1  
SM5  
SM6  
mcspix_clk(POL=1)  
mcspix_simo  
SM4  
Bit n-1  
SM2  
Bit n-2  
Bit n-2  
Bit n-3  
Bit 1  
Bit 0  
Bit 0  
SM3  
mcspix_somi  
Bit n-1  
Bit n-3  
Bit 1  
030-077  
Figure 6-46. McSPI Interface Transmit and Receive in Master Mode(1) (2) (3)  
(1) The active clock edge (rising or falling) on which mcspix_simo is driven and mcspi_somi data is latched is software configurable with the  
bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.  
(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL.  
(3) In mcspix, x is equal to 1. In mcspix_csn, n is equal to 0, 1, 2, or 3.  
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6.6.3 Multiport Full-Speed Universal Serial Bus (USB) Interface  
The AM3517/05 microprocessor provides three USB ports working in full- and low-speed data transactions  
(up to 12Mbit/s).  
Connected to either a serial link controller or a serial PHY (PHY interface modes) it supports:  
•
•
•
6-pin (Tx: Dat/Se0 or Tx: Dp/Dm) unidirectional mode  
4-pin bidirectional mode  
3-pin bidirectional mode  
6.6.3.1 Multiport Full-Speed Universal Serial Bus (USB) – Unidirectional Standard 6-pin Mode  
The following tables assume testing over the recommended operating conditions.  
Table 6-98. Low-/Full-Speed USB Timing Conditions Unidirectional Standard 6-pin Mode  
TIMING CONDITION PARAMETER  
Input Conditions  
1.8V, 3.3V  
UNIT  
tR  
Input signal rise time  
Input signal fall time  
2.0  
2.0  
ns  
ns  
tF  
Output Conditions  
CLOAD  
Output load capacitance  
15.0  
pF  
Table 6-99. Low-/Full-Speed USB Timing Requirements Unidirectional Standard 6-pin Mode  
NO.  
PARAMETER  
1.8V, 3.3V  
MIN MAX  
UNIT  
FSU1  
FSU2  
FSU3  
td(Vp,Vm)  
td(Vp,Vm)  
td(RCVU0)  
Time duration, mmx_rxdp and mmx_rxdm low together during transition  
Time duration, mmx_rxdp and mmx_rxdm high together during transition  
14.0  
8.0  
ns  
ns  
ns  
Time duration, mmx_rrxcv undefine during a single end 0 (mmx_rxdp and  
mmx_rxdm low together)  
14.0  
FSU4  
td(RCVU1)  
Time duration, mmx_rxrcv undefine during a single end 1 (mmx_rxdp and  
mmx_rxdm high together)  
8.0  
ns  
Table 6-100. Low-/Full-Speed USB Switching Characteristics Unidirectional Standard 6-pin Mode  
NO.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
84.8  
84.8  
1.5  
FSU5  
FSU6  
FSU7  
FSU8  
FSU9  
td(TXENL-DATV)  
td(TXENL-SE0V)  
ts(DAT-SE0)  
td(DATI-TXENH)  
td(SE0I-TXENH)  
tR(do)  
Delay time, mmx_txen_n low to mmx_txdat valid  
Delay time, mmx_txen_n low to mmx_txse0 valid  
Skew between mmx_txdat and mmx_txse0 transition  
Delay time, mmx_txdat invalid to mmx_txen_n high  
Delay time, mmx_txse0 invalid to mmx_txen_n high  
Rise time, mmx_txen_n  
81.8  
81.8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
81.8  
81.8  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
tF(do)  
Fall time, mmx_txen_n  
tR(do)  
Rise time, mmx_txdat  
tF(do)  
Fall time, mmx_txdat  
tR(do)  
Rise time, mmx_txse0  
tF(do)  
Fall time, mmx_txse0  
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Transmit  
mmx_txen_n  
mmx_txdat  
mmx_txse0  
mmx_rxdp  
mmx_rxdm  
mmx_rxrcv  
Receive  
FSU5  
FSU6  
FSU8  
FSU9  
FSU7  
FSU1  
FSU2  
FSU2  
FSU4  
FSU1  
FSU3  
030-080  
In mmx, x is equal to 0, 1, or 2.  
Figure 6-47. Low-/Full-Speed USB Unidirectional Standard 6-pin Mode  
6.6.3.2 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 4-pin Mode  
The following tables assume testing over the recommended operating conditions.  
Table 6-101. Low-/Full-Speed USB Timing Conditions Bidirectional Standard 4-pin Mode  
TIMING CONDITION PARAMETER  
1.8V, 3.3V  
UNIT  
Input Conditions  
tR  
Input signal rise time  
Input signal fall time  
2.0  
2.0  
ns  
ns  
tF  
Output Conditions  
CLOAD  
Output load capacitance  
15.0  
pF  
Table 6-102. Low-/Full-Speed USB Timing Requirements Bidirectional Standard 4-pin Mode  
NO.  
PARAMETER  
1.8V, 3.3V  
MIN MAX  
UNIT  
FSU10  
FSU11  
FSU12  
FSU13  
td(DAT,SE0)  
td(DAT,SE0)  
td(RCVU0)  
td(RCVU1)  
Time duration, mmx_txdat and mmx_txse0 low together during  
transition  
14.0  
ns  
ns  
ns  
ns  
Time duration, mmx_txdat and mmx_txse0 high together during  
transition  
8.0  
Time duration, mmx_rrxcv undefine during a single end 0  
(mmx_txdat and mmx_txse0 low together)  
14.0  
8.0  
Time duration, mmx_rxrcv undefine during a single end 1  
(mmx_txdat and mmx_txse0 high together)  
Table 6-103. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 4-pin Mode  
NO.  
PARAMETER  
1.8V, 3.3V  
MIN  
UNIT  
MAX  
84.8  
84.8  
1.5  
FSU14  
FSU15  
FSU16  
FSU17  
FSU18  
td(TXENL-DATV)  
td(TXENL-SE0V)  
ts(DAT-SE0)  
Delay time, mmx_txen_n low to mmx_txdat valid  
Delay time, mmx_txen_n low to mmx_txse0 valid  
Skew between mmx_txdat and mmx_txse0 transition  
Delay time, mmx_txdat invalid before mmx_txen_n high  
Delay time, mmx_txse0 invalid before mmx_txen_n high  
Rise time, mmx_txen_n  
81.8  
81.8  
ns  
ns  
ns  
ns  
ns  
ns  
td(DATV-TXENH)  
td(SE0V-TXENH)  
tR(txen)  
81.8  
81.8  
4.0  
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Table 6-103. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 4-pin  
Mode (continued)  
NO.  
PARAMETER  
1.8V, 3.3V  
MIN MAX  
UNIT  
tF(txen)  
tR(dat)  
tF(dat)  
tR(se0)  
tF(se0)  
Fall time, mmx_txen_n  
4.0  
4.0  
4.0  
4.0  
4.0  
ns  
ns  
ns  
ns  
ns  
Rise time, mmx_txdat  
Fall time, mmx_txdat  
Rise time, mmx_txse0  
Fall time, mmx_txse0  
Transmit  
FSU14  
mmx_txen_n  
mmx_txdat  
mmx_txse0  
mmx_rxrcv  
Receive  
FSU17  
FSU18  
FSU10  
FSU10  
FSU12  
FSU11  
FSU11  
FSU13  
FSU15  
FSU16  
030-081  
In mmx, x is equal to 0, 1, or 2.  
Figure 6-48. Low-/Full-Speed USB Bidirectional Standard 4-pin Mode  
6.6.3.3 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 3-pin Mode  
The following tables assume testing over the recommended operating conditions.  
Table 6-104. Low-/Full-Speed USB Timing Conditions Bidirectional Standard 3-pin Mode  
TIMING CONDITION PARAMETER  
1.8V, 3.3V  
UNIT  
Input Conditions  
tR  
Input signal rise time  
Input signal fall time  
2.0  
2.0  
ns  
ns  
tF  
Output Conditions  
CLOAD  
Output load capacitance  
15.0  
pF  
Table 6-105. Low-/Full-Speed USB Timing Requirements Bidirectional Standard 3-pin Mode  
NO.  
PARAMETER  
1.8V, 3.3V  
MIN MAX  
UNIT  
FSU19  
FSU20  
td(DAT,SE0)  
td(DAT,SE0)  
Time duration, mmx_txdat and mmx_txse0 low together during  
transition  
14.0  
ns  
ns  
Time duration, mmx_tsdat and mmx_txse0 high together during  
transition  
8.0  
Table 6-106. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 3-pin Mode  
NO.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
84.8  
84.8  
1.5  
FSU21  
FSU22  
FSU23  
td(TXENL-DATV)  
td(TXENL-SE0V)  
ts(DAT-SE0)  
Delay time, mmx_txen_n low to mmx_txdat valid  
Delay time, mmx_txen_n low to mmx_txse0 valid  
Skew between mmx_txdat and mmx_txse0 transition  
81.8  
81.8  
ns  
ns  
ns  
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Table 6-106. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 3-pin  
Mode (continued)  
NO.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
FSU24  
FSU25  
td(DATI-TXENH)  
td(SE0I-TXENH)  
tR(do)  
Delay time, mmx_txdat invalid to mmx_txen_n high  
Delay time, mmx_txse0 invalid to mmx_txen_n high  
Rise time, mmx_txen_n  
81.8  
81.8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
tF(do)  
Fall time, mmx_txen_n  
tR(do)  
Rise time, mmx_txdat  
tF(do)  
Fall time, mmx_txdat  
tR(do)  
Rise time, mmx_txse0  
tF(do)  
Fall time, mmx_txse0  
Transmit  
mmx_txen_n  
Receive  
FSU19  
FSU21  
FSU24  
FSU25  
FSU20  
mmx_txdat  
mmx_txse0  
FSU22  
FSU23  
FSU19  
FSU20  
030-082  
In mmx, x is equal to 0, 1, or 2.  
Figure 6-49. Low-/Full-Speed USB Bidirectional Standard 3-pin Mode  
6.6.4 Multiport High-Speed Universal Serial Bus (USB) Timing  
In addition to the full-speed USB controller, a high-speed (HS) USB controller is instantiated inside the  
AM3517/05. It allows high-speed transactions (up to 480 Mbit/s) on the USB ports 1 and 2.  
•
Port 1 and port 2:  
12-bit master mode (SDR)  
–
6.6.4.1 High-Speed Universal Serial Bus (USB) on Ports 1 and 2 12-bit Master Mode  
The following tables assume testing over the recommended operating conditions.  
Table 6-107. High-Speed USB Timing Conditions 12-bit Master Mode  
TIMING CONDITION PARAMETER  
1.8V, 3.3V  
UNIT  
Input Conditions  
tR  
Input signal rise time  
Input signal fall time  
2
2
ns  
ns  
tF  
Output Conditions  
CLOAD  
Output load capacitance  
3
pF  
Table 6-108. High-Speed USB Timing Requirements 12-bit Master Mode(1)  
NO.  
PARAMETER  
1.8V, 3.3V  
MIN MAX  
UNIT  
HSU3 ts(DIRV-CLKH)  
ts(NXTV-CLKH)  
Setup time, hsusbx_dir valid before hsusbx_clk rising edge  
Setup time, hsusbx_nxt valid before hsusbx_clk rising edge  
Hold time, hsusbx_dir valid after hsusbx_clk rising edge  
7.5  
7.5  
0.2  
ns  
ns  
ns  
HSU4 th(CLKH-DIRIV)  
(1) In hsusbx, x is equal to 1 or 2.  
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Table 6-108. High-Speed USB Timing Requirements 12-bit Master Mode(1) (continued)  
PARAMETER  
1.8V, 3.3V  
MIN MAX  
UNIT  
th(CLKH-NXT/IV)  
Hold time, hsusbx_nxt valid after hsusbx_clk rising edge  
Setup time, hsusbx_data[0:7] valid before hsusbx_clk rising edge  
Hold time, hsusbx_data[0:7] valid after hsusbx_clk rising edge  
0.2  
7.5  
0.2  
ns  
ns  
ns  
HSU5 ts(DATAV-CLKH)  
HSU6 th(CLKH-DATIV)  
Table 6-109. High-Speed USB Switching Characteristics 12-bit Master Mode(1)  
N O.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
HSU0  
HSU1  
HSU2  
fp(CLK)  
hsusbx_clk clock frequency  
Jitter standard deviation(2), hsusbx_clk  
60  
200  
13  
MHz  
ps  
tj(CLK)  
td(CLKH-STPV)  
td(CLKH-STPIV)  
td(CLKH-DV)  
td(CLKH-DIV)  
tR(do)  
Delay time, hsusbx_clk high to output hsusbx_stp valid  
Delay time, hsusbx_clk high to output hsusbx_stp invalid  
Delay time, hsusbx_clk high to output hsusbx_data[0:7] valid  
Delay time, hsusbx_clk high to output hsusbx_data[0:7] invalid  
Rise time, output signals  
ns  
2
2
ns  
13  
ns  
ns  
2
2
ns  
tF(do)  
Fall time, output signals  
ns  
(1) In hsusbx, x is equal to 1 or 2.  
(2) The jitter probability density can be approximated by a Gaussian function.  
HSU0  
hsusbx_clk  
HSU1  
HSU1  
hsusbx_stp  
hsusbx_dir_&_nxt  
hsusbx_data[7:0]  
HSU3  
HSU4  
HSU6  
HSU5  
HSU2  
HSU2  
Data_OUT  
Data_IN  
030-087  
In hsusbx, x is equal to 1 or 2.  
Figure 6-50. High-Speed USB 12-bit Master Mode  
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6.6.5 USB0 OTG (USB2.0 OTG)  
The AM3517/05 USB2.0 peripheral supports the following features:  
•
•
•
•
•
USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s)  
USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)  
All transfer modes (control, bulk, interrupt, and isochronous)  
16 Transmit (TX) and 16 Receive (RX) endpoints in addition to endpoint 0  
FIFO RAM  
–
–
32K endpoint  
Programmable size  
•
•
•
Integrated USB 2.0 High Speed PHY  
Connects to a standard Charge Pump for VBUS 5 V generation  
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB  
6.6.5.1 USB OTG Electrical Parameters  
The USB OTG electrical parameters meet or exceed those specified in the following documents which can  
be obtained from the USB Implementers Forum:  
•
•
•
Universal Serial Bus Specification, Revision 2.0, April 27, 2000  
On-The-Go Supplement to the USB 2.0 Specification, Revision 1.3, December 5, 2006  
Engineering Change Notice “Pull-up/pull-down resistors”, Universal Serial Bus Specification Revision  
2.0  
For additional information related to USB OTG electrical parameters, please see the respective  
documents on the USB Implementers Forum web site (http://www.usb.org).  
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6.6.6 High-End Controller Area Network Controller (HECC) Timing  
The AM3517/05 device has a High-End Controller Area Network Controller (HECC). The HECC uses  
established protocol to communicate serially with other controllers in harsh environments. The HECC is  
fully compliant with the Controller Area Network (CAN) protocol, version 2.0B.  
Key features of the HECC include the following:  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CAN, version 2.0B compliant  
32 RX/TX message objects  
32 receive identifier masks  
Programmable wake-up on bus activity  
Programmable interrupt scheme  
Automatic reply to a remote request  
Automatic re-transmission in case of error or loss of arbitration  
Protection against reception of a new message  
32-bit time stamp  
Local network time counter  
Programmable priority register for each message  
Programmable transmission and reception time-out  
HECC/SCC mode of operation  
Standard-Extended Identifier  
Self-test mode  
6.6.6.1 HECC Timing Requirements  
Table 6-110. Timing Requirements for HECC Receive (see Figure 6-51)  
1.8 V, 3.3 V  
MIN  
NO.  
UNIT  
MAX  
1
2
f(baud)  
Maximum programmable baud rate  
Pulse duration, receive data bit  
1
Mbps  
ns  
tw(HECC_RX)  
H-1(1)  
H+3(1)  
(1) These values are relative to H (where H = 1/(baud rate).  
6.6.6.2 HECC Switching Characteristics  
Table 6-111. Switching Characteristics Over Recommended Operating Conditions for HECC Transmit  
(see Figure 6-51)  
1.8 V, 3.3 V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
3
4
f(baud)  
Maximum programmable baud rate  
Pulse duration, transmit data bit  
1
Mbps  
ns  
tw(HECC_TX)  
H-1(1)  
H+3(1)  
(1) These values are relative to H (where H = 1/(baud rate).  
2
4
HECCx_RX  
HECCx_TX  
Figure 6-51. HECC Transmit/Receive Timing  
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6.6.7 Ethernet Media Access Controller (EMAC)  
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the AM3517/05 and  
the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100  
Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.  
The EMAC controls the flow of packet data from the AM3517/05 device to the PHY. The MDIO module  
controls PHY configuration and status monitoring.  
Both the EMAC and the MDIO modules interface to the AM3517/05 device through a custom interface that  
allows efficient data transmission and reception. This custom interface is referred to as the EMAC control  
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to  
multiplex and control interrupts.  
6.6.7.1 EMAC Electrical Data/ Timing  
The following tables assume testing over the recommended operating conditions.  
Table 6-112. RMII Input Timing Requirements  
1.8V, 3.3V  
NO.  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
MHz  
ppm  
ns  
fc(REFCLK)  
Frequency, REF_CLK  
50  
ft (REFCLK)  
Frequency stability, REF_CLK  
Cycle Time, REF_CLK  
+/-50  
1
2
3
6
tc(REFCLK)  
20  
tw(REFCLKH)  
tw(REFCLKL)  
tsu(RXD-REFCLK)  
Pulse Width, REF_CLK High  
Pulse Width, REF_CLK Low  
7
7
4
13  
13  
ns  
ns  
Input Setup Time, RXD Valid before REF_CLK  
High  
ns  
7
8
th(REFCLK-RXD)  
Input Hold Time, RXD Valid after REF_CLK High  
2
4
ns  
ns  
tsu(CRSDV-REFCLK)  
Input Setup Time, CRSDV Valid before  
REF_CLK High  
9
th(REFCLK-CRSDV)  
tsu(RXER-REFCLK)  
th(REFCLKR-RXER)  
Input Hold Time, CRSDV Valid after REF_CLK  
High  
2
4
2
ns  
ns  
ns  
10  
11  
Input Setup Time, RXER Valid before REF_CLK  
High  
Input Hold Time, RXER Valid after REF_CLK  
High  
Table 6-113. RMII Timing Conditions  
TIMING CONDITION PARAMETER  
1.8V, 3.3V  
UNIT  
Input Conditions  
MIN  
1
MAX  
tR  
Input signal rise time  
Input signal fall time  
5
5
ns  
ns  
tF  
1
Output Conditions  
CLOAD  
Output load capacitance  
5.5  
pF  
Table 6-114. RMII Output Switching Characteristics  
1.8V, 3.3V  
TYP  
NO.  
PARAMETER  
MIN  
2.5  
MAX  
13  
UNIT  
4
5
td(REFCLK-TXD)  
td(REFCLK-TXEN)  
Output Delay Time, REF_CLK High to TXD Valid  
ns  
ns  
Output Delay Time, REF_CLK High to TXEN  
Valid  
2.5  
13  
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1
2
3
REF_CLK  
5
5
TXEN  
4
TXD[1:0]  
6
7
RXD[1:0]  
CRS_DV  
8
9
10  
11  
RXER_IN  
SPRS550-004  
Figure 6-52. RMII Timing Diagram  
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6.6.8 Management Data Input/Output (MDIO)  
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to  
enumerate all PHY devices in the system.  
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to  
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO  
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the  
negotiation results, and configure required parameters in the EMAC module for correct operation. The  
module is designed to allow almost transparent operation of the MDIO interface, with very little  
maintenance from the core processor. Only one PHY may be connected at any given time.  
6.6.8.1 Management Data Input/Output (MDIO) Electrical Data/Timing  
Table 6-115. Timing Requirements for MDIO Input (see Figure 6-53 and Figure 6-54)  
No.  
PARAMETER  
UNIT  
MIN  
400  
20  
MAX  
1
4
5
tc(MD_CLK)  
Cycle time, MD_CLK  
ns  
ns  
ns  
tsu(MDIO-MDCLKH)  
th(MDCLKH-MDIO)  
Setup time, MDIO data input valid before MD_CLK high  
Hold time, MDIO data input valid after MDCLK high  
0
1
MD_CLK  
4
5
MDIO_D  
(input)  
Figure 6-53. MDIO Input Timing  
Table 6-116. Switching Characteristics Over Recommended Operating Conditions for MDIO Output  
(see Figure 6-54)  
No.  
PARAMETER  
UNIT  
MIN  
MAX  
7
td(MDCLKL-MDIO)  
Delay time, MDCLK low to MDIO data output valid  
0
100  
ns  
1
MD_CLK  
7
MDIO_D  
(output)  
Figure 6-54. MDIO Output Timing  
6.6.9 Universal Asynchronous Receiver/Transmitter (UART)  
The AM3517/05 has four UARTs (one with Infrared Data Association [IrDA] and Consumer Infrared [CIR]  
modes).  
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Table 6-117. Timing Requirements for UARTx Receive(1)  
1.8V, 3.3V  
MIN  
NO.  
UNIT  
MAX  
1.05U  
1.05U  
4
5
tw(URXDB)  
tw(URXSB)  
Pulse duration, receive data bit (RXDn)  
Pulse duration, receive start bit  
.96U  
ns  
ns  
.96U  
(1) U = UART baud time = 1/programmed baud rate.  
Table 6-118. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit(1)  
1.8V, 3.3V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
UART0 Maximum programmable baud rate f(baud_15)  
UART0 Maximum programmable baud rate f(baud_30)  
UART0 Maximum programmable baud rate f(baud_100)  
Pulse duration, transmit data bit, 15/30/100 pF  
Pulse duration, transmit start bit, 15/30/100 pF  
5
1
f(baud)  
0.23 mbps  
0.115  
2
3
tw(UTXDB)  
tw(UTXSB)  
U - 2  
U - 2  
U + 2  
U + 2  
ns  
ns  
(1) U = UART baud time = 1/programmed baud rate.  
3
2
Start  
Bit  
UART_TXDn  
Data Bits  
5
4
Start  
Bit  
UART_RXDn  
Data Bits  
Figure 6-55. UART Transmit/Receive Timing  
6.6.9.1 UART IrDA Interface  
The IrDA module can operate in three different modes:  
•
•
•
Slow infrared (SIR) (≤115.2 Kbits/s)  
Medium infrared (MIR) (0.576 Mbits/s and 1.152 Mbits/s)  
Fast infrared (FIR) (4 Mbits/s)  
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Pulse duration  
90%  
90%  
50%  
50%  
10%  
10%  
tr  
tf  
030-118  
Figure 6-56. UART IrDA Pulse Parameters  
6.6.9.1.1 IrDA—Receive Mode  
Table 6-119. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode  
ELECTRICAL PULSE DURATION  
SIGNALING RATE  
UNIT  
MIN  
NOMINAL  
SIR  
MAX  
2.4 Kbit/s  
9.6 Kbit/s  
1.41  
1.41  
1.41  
1.41  
1.41  
1.41  
78.1  
19.5  
9.75  
4.87  
3.25  
1.62  
88.55  
22.13  
11.07  
5.96  
μs  
μs  
μs  
μs  
μs  
μs  
19.2 Kbit/s  
38.4 Kbit/s  
57.6 Kbit/s  
115.2 Kbit/s  
4.34  
2.23  
MIR  
FIR  
0.576 Mbit/s  
1.152 Mbit/s  
297.2  
149.6  
416  
208  
518.8  
258.4  
ns  
ns  
4.0 Mbit/s (Single pulse)  
4.0 Mbit/s (Double pulse)  
67  
125  
250  
164  
289  
ns  
ns  
190  
Table 6-120. UART IrDA—Rise and Fall Time—Receive  
Mode  
PARAMETER  
MAX  
UNIT  
tR  
tF  
Rising time,  
uart3_rx_irrx  
200  
ns  
Falling time,  
uart3_rx_irrx  
200  
ns  
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6.6.9.1.2 IrDA—Transmit Mode  
Table 6-121. UART IrDA—Signaling Rate and Pulse Duration—Transmit Mode  
SIGNALING RATE  
ELECTRICAL PULSE DURATION  
UNIT  
MIN  
NOMINAL  
SIR  
MAX  
2.4 Kbit/s  
9.6 Kbit/s  
78.1  
19.5  
9.75  
4.87  
3.25  
1.62  
78.1  
19.5  
9.75  
4.87  
3.25  
1.62  
MIR  
78.1  
19.5  
9.75  
4.87  
3.25  
1.62  
μs  
μs  
μs  
μs  
μs  
μs  
19.2 Kbit/s  
38.4 Kbit/s  
57.6 Kbit/s  
115.2 Kbit/s  
0.576 Mbit/s  
1.152 Mbit/s  
414  
206  
416  
419  
211  
ns  
ns  
208  
FIR  
4.0 Mbit/s (Single pulse)  
4.0 Mbit/s (Double pulse)  
123  
248  
125  
128  
253  
ns  
ns  
250  
6.6.10 HDQ / 1-Wire Interfaces  
This module is intended to work with both the HDQ and the 1-Wire protocols. The protocols use a single  
wire to communicate between the master and the slave. The protocols employ an asynchronous return to  
1 mechanism where, after any command, the line is pulled high.  
6.6.10.1 HDQ Protocol  
Table 6-122 and Table 6-123 assume testing over the recommended operating conditions (see Figure 6-  
57 through Figure 6-60).  
Table 6-122. HDQ Timing Requirements  
PARAMETER  
tCYCD  
DESCRIPTION  
Bit window  
MIN  
MAX  
UNIT  
253  
s
tHW1  
Reads 1  
68  
tHW0  
Reads 0  
180  
tRSPS  
Command to host respond time(1)  
(1) Defined by software.  
Table 6-123. HDQ Switching Characteristics  
PARAMETER  
DESCRIPTION  
MIN  
TYP  
193  
63  
MAX  
UNIT  
tB  
Break timing  
Break recovery  
Bit window  
s
tBR  
tCYCH  
tDW1  
tDW0  
253  
1.3  
Sends1 (write)  
Sends0 (write)  
101  
tB  
tBR  
HDQ  
030-095  
Figure 6-57. HDQ Break (Reset) Timing  
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tCYCH  
tHW0  
tHW1  
HDQ  
030-096  
Figure 6-58. HDQ Read Bit Timing (Data)  
tCYCD  
tDW0  
tDW1  
HDQ  
030-097  
Figure 6-59. HDQ Write Bit Timing (Command/Address or Data)  
Command _byte_written  
0_(LSB)  
Data_byte_received  
tRSPS  
1
Break  
1
6
7_(MSB)  
0_(LSB)  
6
HDQ  
030-098  
Figure 6-60. HDQ Communication Timing  
6.6.10.2 1-Wire Protocol  
Table 6-124 and Table 6-125 assume testing over the recommended operating conditions (see Figure 6-  
61 through Figure 6-63).  
Table 6-124. 1-Wire Timing Requirements  
PARAMETER  
tPDH  
DESCRIPTION  
MIN  
MAX  
UNIT  
Presence pulse delay high  
Presence pulse delay low  
Read bit-zero time  
68  
s
tPDL  
68 tPDH  
tRDV + tREL  
102  
Table 6-125. 1-Wire Switching Characteristics  
PARAMETER  
tRSTL  
DESCRIPTION  
MIN  
TYP  
484  
484  
102  
1.3  
MAX  
UNIT  
Reset time low  
s
tRSTH  
Reset time high  
Write bit cycle time  
Write bit-one time  
Write bit-zero time  
Recovery time  
tSLOT  
tLOW1  
tLOW0  
101  
134  
13  
tREC  
tLOWR  
Read bit strobe time  
tRSTH  
tPDL  
tRTSL  
tPDH  
1-WIRE  
030-099  
Figure 6-61. 1-Wire Break (Reset) Timing  
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tSLOT_and_ tREC  
tRDV_and_ tREL  
tLOWR  
1-WIRE  
030-100  
Figure 6-62. 1-Wire Read Bit Timing (Data)  
tSLOT_and_tREC  
tLOW0  
1-WIRE  
tLOW1  
030-101  
Figure 6-63. 1-Wire Write Bit Timing (Command/Address or Data)  
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6.6.11 I2C Interface  
The multimaster I2C peripheral provides an interface between two or more devices via an I2C serial bus.  
The I2C controller supports the multimaster mode which allows more than one device capable of  
controlling the bus to be connected to it. Each I2C device is recognized by a unique address and can  
operate as either transmitter or receiver, according to the function of the device. In addition to being a  
transmitter or receiver, a device connected to the I2C bus can also be considered as master or slave when  
performing data transfers. This data transfer is carried out via two serial bidirectional wires:  
•
•
An SDA data line  
An SCL clock line  
The following sections illustrate the data transfer is in master or slave configuration with 7-bit addressing  
format. The I2C interface is compliant with Philips I2C specification version 2.1. It supports standard mode  
(up to 100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s) .  
6.6.11.1 I2C Standard/Fast-Speed Mode  
Table 6-126. I2C Standard/Fast-Speed Mode Timings  
1.8V, 3.3-V  
NO.  
PARAMETER(1)  
STANDARD  
MODE  
FAST MODE  
UNIT  
MIN  
MAX  
MIN MAX  
fSCL  
Clock Frequency, i2cX_scl  
100  
400  
kHz  
s
I1  
I2  
I3  
I4  
I5  
tw(SCLH)  
Pulse Duration, i2cX_scl high  
4
0.6  
1.3  
100(2)  
tw(SCLL)  
Pulse Duration, i2cX_scl low  
4.7  
250  
s
tsu(SDAV-SCLH)  
th(SCLHSDAV)  
tsu(SDAL-SCLH)  
Setup time, i2cX_sda valid before i2cX_scl active level  
Hold time, i2cX_sda valid after i2cX_scl active level  
ns  
s
3.45(3)  
0.9(3)  
Setup time, i2cX_scl high after i2cX_sda low (for a  
START(4) condition or a repeated START condition)  
4.7  
4
0.6  
0.6  
0.6  
1.3  
s
I6  
I7  
I8  
th(SCLHSDAH)  
th(SCLHRSTART)  
tw(SDAH)  
Hold time, i2cX_sda low level after i2cX_scl high level  
(STOP condition)  
s
s
s
Hold time, i2cX_sda low level after i2cX_scl high level (for  
a repeated START condition)  
4
Pulse duration, i2cX_sda high between STOP and START  
conditions  
4.7  
tR(SCL)  
tF(SCL)  
tR(SDA)  
tF(SDA)  
CB  
Rise time, i2cX_scl  
1000  
300  
1000  
300  
60  
300  
300  
300  
300  
60  
ns  
ns  
ns  
ns  
pF  
Fall time, i2cX_scl  
Rise time, i2cX_sda  
Fall time, i2cX_sda  
Capacitive load for each bus line  
(1) In i2cX, X is equal to 1, 2, or 3.  
(2) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDAV-SCLH) 250 ns must then be  
met. This is automatically the case if the device does not stretch the low period of the i2cx_scl. If such a device does stretch the low  
period of the i2cx_scl, it must output the next data bit to the i2cx_sda line tr(SDA) max + tsu(SDAV-SCLH) = 1000 + 250 = 1250 ns (according  
to the standard-mode I2C-bus specification) before the i2cx_scl line is released.  
(3) The maximum th(SCLH-SDA) has only to be met if the device does not stretch the low period of the i2cx_scl signal.  
(4) After this time, the first clock is generated.  
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START REPEAT  
START  
START  
STOP  
i2cX_sda  
i2cX_scl  
I2  
I5  
I8  
I7  
I6  
I1  
I3  
I4  
I6  
030-093  
Figure 6-64. I2C Standard/Fast Mode  
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6.6.11.2 I2C High-Speed Mode  
Table 6-127. I2C High-Speed Mode Timings(1) (2)  
1.8V, 3.3V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
fSCL  
Clock frequency, i2cX_scl  
3.4  
MHz  
I1  
I2  
I3  
I4  
I5  
tw(SCLH)  
Pulse duration, i2cX_scl high  
60(3)  
160(3)  
s
s
tw(SCLL)  
Pulse duration, i2cX_scl low  
tsu(SDAV-SCLH)  
th(SCLHSDAV)  
tsu(SDAL-SCLH)  
Setup time, i2cX_sda valid before i2cX_scl active level  
Hold time, i2cX_sda valid after i2cX_scl active level  
10  
ns  
s
70  
Setup time, i2cX_scl high after i2cX_sda low  
(for a START(4) condition or a repeated START  
condition)  
160  
s
I6  
I7  
th(SCLHSDAH)  
Hold time, i2cX_sda low level after i2cX_scl high level  
(STOP condition)  
160  
160  
s
th(SCLHRSTART)  
Hold time, i2cX_sda low level after i2cX_scl high level  
(for a repeated START condition)  
ns  
tR(SCL)  
tR(SCL)  
Rise time, i2cX_scl  
10  
10  
40  
80  
ns  
ns  
Rise time, i2cX_scl after a repeated START condition  
and after a bit acknowledge  
tF(SCL)  
tR(SDA)  
tF(SDA)  
Fall time, i2cX_scl  
Rise time, i2cX_sda  
Fall time, i2cX_sda  
10  
10  
10  
40  
80  
80  
ns  
ns  
ns  
(1) In i2cX, X is equal to 1, 2, or 3.  
(2) The device provides (via the I2C bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to  
bridge the undefined region of the falling edge of i2cx_scl.  
(3) HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. tw(SCLL) > 2 tw(SCLH)  
.
(4) After this time, the first clock is generated.  
START REPEAT  
STOP  
I7  
i2cX_sda  
I5  
I6  
I1  
I2  
I3  
I4  
i2cX_scl  
030-094  
Figure 6-65. I2C High-Speed Mode(1) (2) (3)  
(1) HS-mode master devices generate a serial clock signal with a high-to-low ratio of 1 to 2. tw(SCLL) > 2 x tw(SCLH)  
.
(2) In i2cX, X is equal to 1, 2, or 3.  
(3) After this time, the first clock is generated.  
Table 6-128. Correspondence Standard vs. TI Timing References  
AM3517/05  
STANDARD-I2C  
S/F Mode  
FSCL  
HS Mode  
FSCLH  
THIGH  
fSCL  
I1  
I2  
I3  
I4  
I5  
I6  
I7  
I8  
tw(SCLH)  
THIGH  
tw(SCLL)  
TLOW  
TLOW  
tsu(SDAV-SCLH)  
th(SCLH-SDAV)  
tsu(SDAL-SCLH)  
th(SCLH-SDAH)  
th(SCLH-RSTART)  
tw(SDAH)  
TSU;DAT  
TSU;DAT  
TSU;STA  
THD;STA  
TSU;STO  
TBUF  
TSU;DAT  
TSU;DAT  
TSU;STA  
THD;STA  
TSU;STO  
196  
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6.7 Removable Media Interfaces  
6.7.1 High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing  
The MMC/SDIO host controller provides an interface to high-speed and standard MMC, SD memory  
cards, or SDIO cards. The application interface is responsible for managing transaction semantics. The  
MMC/SDIO host controller deals with MMC/SDIO protocol at transmission level, packing data, adding  
CRC, start/end bit, and checking for syntactical correctness.  
There are three MMC interfaces on the AM3517/05:  
•
MMC/SD/SDIO Interface 1:  
–
–
1.8-V/3.3-V support  
8 bits  
•
MMC/SD/SDIO Interface 2:  
–
–
–
1.8-V/3.3-V support  
8 bits  
4 bits with external transceiver allowing to support 1.8-V/3.3-V peripherals in 1.8-V mode operation.  
Transceiver direction control signals are multiplexed with the upper four data bits.  
•
MMC/SD/SDIO Interface 3:  
–
–
1.8-V/3.3-V support  
8 bits  
6.7.1.1 MMC/SD/SDIO in SD Identification Mode  
The following tables assume testing over the recommended operating conditions and electrical  
characteristic conditions.  
Table 6-129. MMC/SD/SDIO Timing Conditions SD Identification Mode  
TIMING CONDITION PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
SD Identification Mode  
Input Conditions  
tr  
Input signal rise time  
Input signal fall time  
10  
10  
ns  
ns  
tf  
Output Conditions  
CLOAD  
Output load capacitance  
30  
pF  
Table 6-130. MMC/SD/SDIO Timing Requirements SD Identification Mode(1) (2) (3)(4)  
NO.  
PARAMETER  
1.8V, 3.3V  
MIN MAX  
UNIT  
SD Identification Mode  
MMC/SD/SDIO Interface 1  
HSSD3/SD3  
tsu(CMDV-CLKIH)  
Setup time, mmc1_cmd valid before mmc1_clk rising  
clock edge  
1198.4  
1249.2  
ns  
ns  
HSSD4/SD4  
tsu(CLKIH-CMDIV)  
Hold time, mmc1_cmd valid after mmc1_clk rising  
clock edge  
MMC/SD/SDIO Interface 2  
HSSD3/SD3 tsu(CMDV-CLKIH)  
Setup time, mmc2_cmd valid before mmc2_clk rising  
clock edge  
1198.4  
ns  
(1) Timing parameters refer to output clock specified in Table 6-131.  
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-131.  
(3) Corresponding figures showing timing parameters are common with other interface modes. (See SD and HS SD modes).  
(4) For more information, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0).  
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Table 6-130. MMC/SD/SDIO Timing Requirements SD Identification Mode(1) (2) (3)(4) (continued)  
NO.  
PARAMETER  
1.8V, 3.3V  
MIN MAX  
UNIT  
HSSD4/SD4  
tsu(CLKIH-CMDIV)  
Hold time, mmc2_cmd valid after mmc2_clk rising  
clock edge  
1249.2  
ns  
MMC/SD/SDIO Interface 3  
HSSD3/SD3  
tsu(CMDV-CLKIH)  
Setup time, mmc3_cmd valid before mmc3_clk rising  
clock edge  
1198.4  
1249.2  
ns  
ns  
HSSD4/SD4  
tsu(CLKIH-CMDIV)  
Hold time, mmc3_cmd valid after mmc3_clk rising  
clock edge  
Table 6-131. MMC/SD/SDIO Switching Characteristics SD Identification Mode(1)(2)  
NO.  
PARAMETER  
1.8V, 3.3V  
MAX  
UNIT  
MIN  
SD Identification Mode  
HSSD1/SD1  
HSSD2/SD2  
HSSD2/SD2  
tc(clk)  
Cycle time, output clk period  
2500  
ns  
ns  
ns  
ns  
ps  
tW(clkH)  
tW(clkL)  
tdc(clk)  
tj(clk)  
Typical pulse duration, output clk high  
Typical pulse duration, output clk low  
Duty cycle error, output clk  
X(3)*PO(4)  
Y(5)*PO(4)  
125  
200  
Jitter standard deviation, output clk  
MMC/SD/SDIO Interface 1  
tr(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
10  
10  
ns  
ns  
ns  
ns  
ns  
tf(clkH)  
tr(clkL)  
tf(clk)  
10  
10  
HSSD5/SD5  
td(CLKOH-CMD)  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
6.3  
6.3  
6.3  
2492.7  
MMC/SD/SDIO Interface 2  
tr(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
10  
10  
ns  
ns  
ns  
ns  
ns  
tf(clkH)  
tr(clkL)  
tf(clk)  
10  
10  
HSSD5/SD5  
td(CLKOH-CMD)  
Delay time, mmc2_clk rising clock edge to mmc2_cmd  
transition  
2492.7  
MMC/SD/SDIO Interface 3  
tr(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
10  
10  
ns  
ns  
ns  
ns  
ns  
tf(clkH)  
tr(clkL)  
tf(clk)  
10  
10  
HSSD5/SD5  
td(CLKOH-CMD)  
Delay time, mmc3_clk rising clock edge to mmc3_cmd  
transition  
2492.7  
(1) Corresponding figures showing timing parameters are common with other interface modes (see SD and HS SD modes).  
(2) The jitter probability density can be approximated by a Gaussian function.  
(3) The X parameter is defined as shown below.  
(4) PO = output clk period in ns.  
(5) The Y parameter is defined as shown below.  
Table 6-132. X Parameter  
CLKD  
1 or Even  
Odd  
X
0.5  
(trunc[CLKD/2]+1)/CLKD  
198  
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Table 6-133. Y Parameter  
CLKD  
1 or Even  
Odd  
Y
0.5  
(trunc[CLKD/2])/CLKD  
6.7.1.2 MMC/SD/SDIO in High-Speed MMC Mode  
The following tables assume testing over the recommended operating conditions and electrical  
characteristic conditions.  
Table 6-134. MMC/SD/SDIO Timing Conditions High-Speed MMC Mode  
TIMING CONDITION PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
High-Speed MMC Mode  
Input Conditions  
tr  
Input signal rise time  
Input signal fall time  
0.19  
0.19  
3
3
ns  
ns  
tf  
Output Conditions  
CLOAD  
Output load capacitance  
30  
pF  
Table 6-135. MMC/SD/SDIO Timing Requirements High-Speed MMC Mode(1)(2)(3)(4)  
NO.  
PARAMETER  
1.8 V  
3.3V  
UNIT  
MIN  
MAX  
MIN  
MAX  
High-Speed MMC Mode  
MMC/SD/SDIO Interface 1  
MMC3 tsu(CMDV-CLKIH)  
Setup time, mmc1_cmd valid before mmc1_clk  
rising clock edge  
2.13  
3.47  
2.13  
3.47  
2.41  
2.09  
2.41  
2.09  
ns  
ns  
ns  
ns  
MMC4 th(CLKIH-CMDIV)  
MMC7 tsu(DATxV-CLKIH)  
MMC8 th(CLKIH-DATxIV)  
Hold time, mmc1_cmd valid after mmc1_clk  
rising clock edge  
Setup time, mmc1_datx valid before mmc1_clk  
rising clock edge  
Hold time, mmc1_datx valid after mmc1_clk  
rising clock edge  
MMC/SD/SDIO Interface 2  
MMC3 tsu(CMDV-CLKIH)  
Setup time, mmc2_cmd valid before mmc2_clk  
rising clock edge  
2.88  
2.90  
2.88  
2.90  
3.23  
1.46  
3.23  
1.46  
ns  
ns  
ns  
ns  
MMC4 th(CLKIH-CMDIV)  
MMC7 tsu(DATxV-CLKIH)  
MMC8 th(CLKIH-DATxIV)  
Hold time, mmc2_cmd valid after mmc2_clk  
rising clock edge  
Setup time, mmc2_datx valid before mmc2_clk  
rising clock edge  
Hold time, mmc2_datx valid after mmc2_clk  
rising clock edge  
MMC/SD/SDIO Interface 3  
MMC3 tsu(CMDV-CLKIH)  
Setup time, mmc3_cmd valid before mmc3_clk  
rising clock edge  
3.38  
2.83  
3.38  
2.83  
3.41  
1.46  
3.41  
1.46  
ns  
ns  
ns  
ns  
MMC4 th(CLKIH-CMDIV)  
MMC7 tsu(DATxV-CLKIH)  
MMC8 th(CLKIH-DATxIV)  
Hold time, mmc3_cmd valid after mmc3_clk  
rising clock edge  
Setup time, mmc3_datx valid before mmc3_clk  
rising clock edge  
Hold time, mmc3_datx valid after mmc3_clk  
rising clock edge  
(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.  
(2) Timing parameters refer to output clock specified in Table 6-136.  
(3) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-136.  
(4) Corresponding figures showing timing parameters are common with Standard MMC mode.  
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UNIT  
Table 6-136. MMC/SD/SDIO Switching Characteristics High-Speed MMC Mode(1)(2)  
N O.  
PARAMETER  
1.8V, 3.3V  
MIN  
MAX  
High-Speed MMC Mode  
MMC1  
MMC2  
MMC2  
tc(clk)  
Cycle time, output clk period  
20.83  
ns  
ns  
ns  
ps  
ps  
tW(clkH)  
tW(clkL)  
tdc(clk)  
tj(clk)  
Typical pulse duration, output clk high  
Typical pulse duration, output clk low  
Duty cycle error, output clk  
X(3)*PO(4)  
Y(5)*PO(4)  
1041.67  
200  
Jitter standard deviation, output clk  
MMC/SD/SDIO Interface 1  
tc(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
3
ns  
ns  
ns  
ns  
ns  
tW(clkH)  
tW(clkL)  
tdc(clk)  
3
3
3
MMC5  
MMC6  
td(CLKOH-CMD)  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
3.7  
3.7  
14.11  
td(CLKOH-DATx)  
Delay time, mmc1_clk rising clock edge to mmc1_datx  
transition  
16.50  
ns  
MMC/SD/SDIO Interface 2  
tc(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
3
ns  
ns  
ns  
ns  
ns  
tW(clkH)  
tW(clkL)  
tdc(clk)  
3
3
3
MMC5  
MMC6  
td(CLKOH-CMD)  
Delay time, mmc2_clk rising clock edge to mmc2_cmd  
transition  
3.7  
3.7  
14.11  
td(CLKOH-DATx)  
Delay time, mmc2_clk rising clock edge to mmc2_datx  
transition  
16.50  
ns  
MMC/SD/SDIO Interface 3  
tc(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
3
ns  
ns  
ns  
ns  
ns  
tW(clkH)  
tW(clkL)  
tdc(clk)  
3
3
3
MMC5  
MMC6  
td(CLKOH-CMD)  
Delay time, mmc3_clk rising clock edge to mmc3_cmd  
transition  
3.7  
3.7  
14.11  
td(CLKOH-DATx)  
Delay time, mmc3_clk rising clock edge to mmc3_datx  
transition  
14.11  
ns  
(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.  
(2) The jitter probability density can be approximated by a Gaussian function.  
(3) The X parameter is defined as shown below.  
(4) PO = output clk period in ns.  
(5) The Y parameter is defined as shown below.  
Table 6-137. X Parameter  
CLKD  
1 or Even  
Odd  
X
0.5  
(trunc[CLKD/2]+1)/CLKD  
Table 6-138. Y Parameter  
CLKD  
1 or Even  
Odd  
Y
0.5  
(trunc[CLKD/2])/CLKD  
200  
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For details about clock division factor CLKD, see the AM35x ARM Microprocessor Technical Reference  
Manual (literature number SPRUGR0).  
6.7.1.3 MMC/SD/SDIO in Standard MMC Mode and MMC Identification Mode  
The following tables assume testing over the recommended operating conditions and electrical  
characteristic conditions.  
Table 6-139. MMC/SD/SDIO Timing Conditions Standard MMC Mode and MMC Identification Mode  
TIMING CONDITION PARAMETER  
1.8-V,3.3-V  
UNIT  
MIN  
MAX  
Standard MMC Mode and MMC Identification Mode  
Input Conditions  
tr  
Input signal rise time  
Input signal fall time  
0.19  
0.19  
10  
10  
ns  
ns  
tf  
Output Conditions  
CLOAD  
Output load capacitance  
30  
pF  
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Table 6-140. MMC/SD/SDIO Timing Requirements Standard MMC Mode and MMC Identification  
Mode(1)(2)(3)  
NO.  
PARAMETER  
1.8 V  
3.3V  
UNIT  
MIN  
MAX  
MIN  
MAX  
Standard MMC Mode and MMC Identification Mode  
MMC/SD/SDIO Interface 1  
MMC3 tsu(CMDV-CLKIH)  
MMC4 th(CLKIH-CMDIV)  
MMC7 tsu(DATxV-CLKIH)  
MMC8 th(CLKIH-DATxIV)  
Setup time, mmc1_cmd valid before  
mmc1_clk rising clock edge  
2.13  
3.47  
2.13  
3.47  
2.41  
2.09  
2.41  
2.09  
ns  
ns  
ns  
ns  
Hold time, mmc1_cmd valid after mmc1_clk  
rising clock edge  
Setup time, mmc1_datx valid before  
mmc1_clk rising clock edge  
Hold time, mmc1_datx valid after mmc1_clk  
rising clock edge  
MMC/SD/SDIO Interface 2  
MMC3 tsu(CMDV-CLKIH)  
Setup time, mmc2_cmd valid before  
mmc2_clk rising clock edge  
2.88  
2.90  
2.88  
2.90  
3.23  
1.46  
3.23  
1.46  
ns  
ns  
ns  
ns  
MMC4 th(CLKIH-CMDIV)  
MMC7 tsu(DATxV-CLKIH)  
MMC8 th(CLKIH-DATxIV)  
Hold time, mmc2_cmd valid after mmc2_clk  
rising clock edge  
Setup time, mmc2_datx valid before  
mmc2_clk rising clock edge  
Hold time, mmc2_datx valid after mmc2_clk  
rising clock edge  
MMC/SD/SDIO Interface 3  
MMC3 tsu(CMDV-CLKIH)  
Setup time, mmc3_cmd valid before  
mmc3_clk rising clock edge  
3.38  
2.83  
3.38  
2.83  
3.41  
1.46  
3.41  
1.46  
ns  
ns  
ns  
ns  
MMC4 th(CLKIH-CMDIV)  
MMC7 tsu(DATxV-CLKIH)  
MMC8 th(CLKIH-DATxIV)  
Hold time, mmc3_cmd valid after mmc3_clk  
rising clock edge  
Setup time, mmc3_datx valid before  
mmc3_clk rising clock edge  
Hold time, mmc3_datx valid after mmc3_clk  
rising clock edge  
(1) Timing parameters are referred to output clock specified in Table 6-141.  
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-141.  
(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.  
Table 6-141. MMC/SD/SDIO Switching Characteristics Standard MMC Mode and MMC Identification  
Mode(1)(2)  
NO.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
MMC Identification Mode  
MMC1  
MMC2  
MMC2  
tc(clk)  
Cycle time  
2500  
ns  
ns  
ns  
ns  
ps  
tW(clkH)  
tW(clkL)  
tdc(clk)  
tj(clk)  
Typical pulse duration, output clk high  
Typical pulse duration, output clk low  
Duty cycle error, output clk  
X(3)*PO(4)  
Y(5)*PO(4)  
2604.17  
200  
Jitter standard deviation  
Standard MMC Mode  
MMC1  
MMC2  
MMC2  
tc(clk)  
Cycle time  
2500  
ns  
ns  
ns  
tW(clkH)  
tW(clkL)  
Typical pulse duration, output clk high  
Typical pulse duration, output clk low  
X(3)*PO(4)  
Y(5)*PO(4)  
(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.  
(2) The jitter probability density can be approximated by a Gaussian function.  
(3) The X parameter is defined as shown below.  
(4) PO = output clk period in ns.  
(5) The Y parameter is defined as shown below.  
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Table 6-141. MMC/SD/SDIO Switching Characteristics Standard MMC Mode and MMC Identification  
Mode(1)(2) (continued)  
NO.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
tdc(clk)  
tj(clk)  
Duty cycle error, output clk  
Jitter standard deviation  
2604.17  
200  
ps  
ps  
MMC/SD/SDIO Interface 1  
tr(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
10  
10  
ns  
ns  
ns  
ns  
ns  
tf(clkH)  
tr(clkL)  
tf(clk)  
10  
10  
MMC5  
MMC6  
td(CLKOH-CMD)  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
4.3  
4.3  
47.78  
td(CLKOH-DATx)  
Delay time, mmc1_clk rising clock edge to mmc1_datx  
transition  
47.78  
ns  
MMC/SD/SDIO Interface 2  
tr(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
10  
10  
ns  
ns  
ns  
ns  
ns  
tf(clkH)  
tr(clkL)  
tf(clk)  
10  
10  
MMC5  
MMC6  
td(CLKOH-CMD)  
Delay time, mmc2_clk rising clock edge to mmc2_cmd  
transition  
4.3  
4.3  
47.78  
td(CLKOH-DATx)  
Delay time, mmc2_clk rising clock edge to mmc2_datx  
transition  
47.78  
ns  
MMC/SD/SDIO Interface 3  
tr(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
10  
10  
ns  
ns  
ns  
ns  
ns  
tf(clkH)  
tr(clkL)  
tf(clk)  
10  
10  
MMC5  
MMC6  
td(CLKOH-CMD)  
Delay time, mmc3_clk rising clock edge to mmc3_cmd  
transition  
4.3  
4.3  
47.78  
td(CLKOH-DATx)  
Delay time, mmc3_clk rising clock edge to mmc3_datx  
transition  
47.78  
ns  
Table 6-142. X Parameter  
CLKD  
1 or Even  
Odd  
X
0.5  
(trunc[CLKD/2]+1)/CLKD  
Table 6-143. Y Parameter  
CLKD  
1 or Even  
Odd  
Y
0.5  
(trunc[CLKD/2])/CLKD  
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For details about clock division factor CLKD, see the AM35x ARM Microprocessor Technical Reference  
Manual (literature number SPRUGR0).  
MMC1  
MMC2  
mmcx_clk  
MMC3  
MMC7  
MMC4  
mmcx_cmd  
MMC8  
mmcx_dat[3:0]  
030-104  
In mmcx, x is equal to 1, 2, or 3.  
Figure 6-66. MMC/SD/SDIO High-Speed and Standard MMC Modes Data/Command Receive  
MMC1  
MMC2  
mmcx_clk  
MMC5  
MMC6  
MMC5  
mmcx_cmd  
MMC6  
mmcx_dat[3:0]  
030-105  
In mmcx, x is equal to 1, 2, or 3.  
Figure 6-67. MMC/SD/SDIO High-Speed and Standard MMC Modes Data/Command Transmit  
6.7.1.4 MMC/SD/SDIO in High-Speed SD Mode  
The following tables assume testing over the recommended operating conditions and electrical  
characteristic conditions.  
Table 6-144. MMC/SD/SDIO Timing Conditions High-Speed SD Mode  
TIMING CONDITION PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
High-Speed SD Mode  
Input Conditions  
tR  
Input signal rise time  
Input signal fall time  
0.19  
0.19  
3
3
ns  
ns  
tF  
Output Conditions  
CLOAD  
Output load capacitance  
30  
pF  
Table 6-145. MMC/SD/SDIO Timing Requirements High-Speed SD Mode(1)(2)(3)  
NO.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
High-Speed SD Mode  
MMC/SD/SDIO Interface 1  
HSSD3  
tsu(CMDV-CLKIH)  
Setup time, mmc1_cmd valid before mmc1_clk rising  
clock edge  
5.61  
2.28  
ns  
ns  
HSSD4  
th(CLKIH-CMDIV)  
Hold time, mmc1_cmd valid after mmc1_clk rising  
clock edge  
(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.  
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-146.  
(3) Timing Parameters refer to output clock specified in Table 6-146.  
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Table 6-145. MMC/SD/SDIO Timing Requirements High-Speed SD Mode(1)(2)(3) (continued)  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
HSSD7  
HSSD8  
tsu(DATxV-CLKIH)  
th(CLKIH-DATxIV)  
Setup time, mmc1_datx valid before mmc1_clk rising  
clock edge  
5.61  
ns  
ns  
Hold time, mmc1_datx valid after mmc1_clk rising  
clock edge  
2.28  
MMC/SD/SDIO Interface 2  
HSSD3  
HSSD4  
HSSD7  
HSSD8  
tsu(CMDV-CLKIH)  
th(CLKIH-CMDIV)  
tsu(DATxV-CLKIH)  
th(CLKIH-DATxIV)  
Setup time, mmc2_cmd valid before mmc2_clk rising  
clock edge  
5.61  
2.28  
5.61  
2.28  
ns  
ns  
ns  
ns  
Hold time, mmc2_cmd valid after mmc2_clk rising  
clock edge  
Setup time, mmc2_datx valid before mmc2_clk rising  
clock edge  
Hold time, mmc2_datx valid after mmc2_clk rising  
clock edge  
MMC/SD/SDIO Interface 3  
HSSD3  
HSSD4  
HSSD7  
HSSD8  
tsu(CMDV-CLKIH)  
th(CLKIH-CMDIV)  
tsu(DATxV-CLKIH)  
th(CLKIH-DATxIV)  
Setup time, mmc3_cmd valid before mmc3_clk rising  
clock edge  
5.61  
2.28  
5.61  
2.28  
ns  
ns  
ns  
ns  
Hold time, mmc3_cmd valid after mmc3_clk rising  
clock edge  
Setup time, mmc3_datx valid before mmc3_clk rising  
clock edge  
Hold time, mmc3_datx valid after mmc3_clk rising  
clock edge  
Table 6-146. MMC/SD/SDIO Switching Characteristics High-Speed SD Mode(1)(2)  
NO.  
PARAMETER  
1.8 V, 3.3 V  
UNIT  
MIN  
MAX  
High-Speed SD Mode  
HSSD1  
HSSD2  
HSSD2  
tc(clk)  
Cycle time  
20.83  
ns  
ns  
ns  
ps  
ps  
tW(clkH)  
tW(clkL)  
tdc(clk)  
tj(clk)  
Typical pulse duration, output clk high  
Typical pulse duration, output clk low  
Duty cycle error, output clk  
X(3)*PO(4)  
Y(5)*PO(4)  
1041.67  
200  
Jitter standard deviation  
MMC/SD/SDIO Interface 1  
tr(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
3
ns  
ns  
ns  
ns  
ns  
tf(clkH)  
tr(clkL)  
tf(clk)  
3
3
3
HSSD5  
HSSD6  
td(CLKOH-CMD)  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
3.72  
3.72  
14.11  
td(CLKOH-DATx)  
Delay time, mmc1_clk rising clock edge to mmc1_datx  
transition  
14.11  
ns  
MMC/SD/SDIO Interface 2  
tr(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
3
3
3
3
ns  
ns  
ns  
ns  
tf(clkH)  
tr(clkL)  
tf(clk)  
(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.  
(2) The jitter probability density can be approximated by a Gaussian function.  
(3) The X parameter is defined as shown in Table 6-147.  
(4) PO = output clk period in ns.  
(5) The Y parameter is defined as shown in Table 6-148.  
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Table 6-146. MMC/SD/SDIO Switching Characteristics High-Speed SD Mode(1)(2) (continued)  
NO.  
PARAMETER  
1.8 V, 3.3 V  
UNIT  
MIN  
MAX  
HSSD5  
HSSD6  
td(CLKOH-CMD)  
td(CLKOH-DATx)  
Delay time, mmc2_clk rising clock edge to mmc2_cmd  
transition  
3.72  
14.11  
ns  
ns  
Delay time, mmc2_clk rising clock edge to mmc2_datx  
transition  
3.72  
14.11  
MMC/SD/SDIO Interface 3  
tr(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
3
ns  
ns  
ns  
ns  
ns  
tf(clkH)  
tr(clkL)  
tf(clk)  
3
3
3
HSSD5  
HSSD6  
td(CLKOH-CMD)  
Delay time, mmc3_clk rising clock edge to mmc3_cmd  
transition  
3.72  
3.72  
14.11  
td(CLKOH-DATx)  
Delay time, mmc3_clk rising clock edge to mmc3_datx  
transition  
14.11  
ns  
Table 6-147. X Parameters  
CLKD  
1 or Even  
Odd  
X
0.5  
(trunc[CLKD/2]+1)/CLKD  
Table 6-148. Y Parameters  
CLKD  
1 or Even  
Odd  
Y
0.5  
(trunc[CLKD/2])/CLKD  
For details about clock division factor CLKD, see the AM35x ARM Microprocessor Technical Reference  
Manual (literature number SPRUGR0).  
HSSD1  
HSSD2  
mmcx_clk  
HSSD3  
HSSD7  
HSSD4  
mmcx_cmd  
HSSD8  
mmcx_dat[3:0]  
030-106  
In mmcx, x is equal to 1, 2, or 3.  
Figure 6-68. MMC/SD/SDIO High-Speed SD Mode Data/Command Receive  
HSSD1  
HSSD2  
mmcx_clk  
HSSD5  
HSSD6  
HSSD5  
mmcx_cmd  
HSSD6  
mmcx_dat[3:0]  
030-107  
In mmcx, x is equal to 1, 2, or 3.  
Figure 6-69. MMC/SD/SDIO High-Speed SD Mode Data/Command Transmit  
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6.7.1.5 MMC/SD/SDIO in Standard SD Mode  
The following tables assume testing over the recommended operating conditions and electrical  
characteristic conditions.  
Table 6-149. MMC/SD/SDIO Timing Conditions Standard SD Mode  
TIMING CONDITION PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
Standard SD Mode  
Input Conditions  
tR  
Input signal rise time  
Input signal fall time  
0.19  
0.19  
10  
10  
ns  
ns  
tF  
Output Conditions  
CLOAD  
Output load capacitance  
30  
pF  
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UNIT  
Table 6-150. MMC/SD/SDIO Timing Requirements Standard SD Mode(1)(2)(3)  
NO.  
PARAMETER  
1.8 V, 3.3V  
MAX  
MIN  
Standard SD Mode  
MMC/SD/SDIO Interface 1  
SD3  
SD4  
SD7  
SD8  
tsu(CMDV-CLKIH)  
th(CLKIH-CMDIV)  
tsu(DATxV-CLKIH)  
th(CLKIH-DATxIV)  
Setup time, mmc1_cmd valid before mmc1_clk rising clock  
edge  
6.23  
ns  
ns  
ns  
ns  
Hold time, mmc1_cmd valid after mmc1_clk rising clock  
edge  
19.37  
6.23  
Setup time, mmc1_datx valid before mmc1_clk rising clock  
edge  
Hold time, mmc1_datx valid after mmc1_clk rising clock  
edge  
19.37  
MMC/SD/SDIO Interface 2  
SD3  
SD4  
SD7  
SD8  
tsu(CMDV-CLKIH)  
th(CLKIH-CMDIV)  
tsu(DATxV-CLKIH)  
th(CLKIH-DATxIV)  
Setup time, mmc2_cmd valid before mmc2_clk rising clock  
edge  
6.23  
19.37  
6.23  
ns  
ns  
ns  
ns  
Hold time, mmc2_cmd valid after mmc2_clk rising clock  
edge  
Setup time, mmc2_datx valid before mmc2_clk rising clock  
edge  
Hold time, mmc2_datx valid after mmc2_clk rising clock  
edge  
19.37  
MMC/SD/SDIO Interface 3  
SD3  
SD4  
SD7  
SD8  
tsu(CMDV-CLKIH)  
th(CLKIH-CMDIV)  
tsu(DATxV-CLKIH)  
th(CLKIH-DATxIV)  
Setup time, mmc3_cmd valid before mmc3_clk rising clock  
edge  
6.23  
19.37  
6.23  
ns  
ns  
ns  
ns  
Hold time, mmc3_cmd valid after mmc3_clk rising clock  
edge  
Setup time, mmc3_datx valid before mmc3_clk rising clock  
edge  
Hold time, mmc3_datx valid after mmc3_clk rising clock  
edge  
19.37  
(1) Timing parameters refer to output clock specified in Table 6-151.  
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-151.  
(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.  
Table 6-151. MMC/SD/SDIO Switching Characteristics Standard SD Mode(1)(2)  
NO.  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
Standard SD Mode  
SD1  
SD2  
SD2  
tc(clk)  
Cycle time  
41.67  
ns  
ns  
ns  
ps  
ps  
tW(clkH)  
tW(clkL)  
tdc(clk)  
tj(clk)  
Typical pulse duration, output clk high  
Typical pulse duration, output clk low  
Duty cycle error, output clk  
X(3)*PO(4)  
Y(5)*PO(4)  
2083.33  
200  
Jitter standard deviation  
MMC/SD/SDIO Interface 1  
tr(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
tf(clkH)  
tr(clkL)  
tf(clk)  
(1) The jitter probability density can be approximated by a Gaussian function.  
(2) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.  
(3) The X parameter is defined as shown in Table 6-152.  
(4) PO = output clk period in ns.  
(5) The Y parameter is defined as shown in Table 6-153.  
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Table 6-151. MMC/SD/SDIO Switching Characteristics Standard SD Mode(1)(2) (continued)  
PARAMETER  
1.8V, 3.3V  
UNIT  
MIN  
MAX  
SD5  
SD6  
td(CLKOH-CMD)  
td(CLKOH-DATx)  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
6.13  
35.53  
ns  
ns  
Delay time, mmc1_clk rising clock edge to mmc1_datx  
transition  
6.13  
35.53  
MMC/SD/SDIO Interface 2  
tr(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
10  
10  
ns  
ns  
ns  
ns  
ns  
tf(clkH)  
tr(clkL)  
tf(clk)  
10  
10  
SD5  
SD6  
td(CLKOH-CMD)  
Delay time, mmc2_clk rising clock edge to mmc2_cmd  
transition  
6.13  
6.13  
35.53  
td(CLKOH-DATx)  
Delay time, mmc2_clk rising clock edge to mmc2_datx  
transition  
35.53  
ns  
MMC/SD/SDIO Interface 3  
tr(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
10  
10  
ns  
ns  
ns  
ns  
ns  
tf(clkH)  
tr(clkL)  
tf(clk)  
10  
10  
SD5  
SD6  
td(CLKOH-CMD)  
Delay time, mmc3_clk rising clock edge to mmc3_cmd  
transition  
6.13  
6.13  
35.53  
td(CLKOH-DATx)  
Delay time, mmc3_clk rising clock edge to mmc3_datx  
transition  
35.53  
ns  
Table 6-152. X Parameter  
CLKD  
X
1 or Even  
Odd  
0.5  
(trunc[CLKD/2]+1)/CLKD  
Table 6-153. Y Parameter  
CLKD  
1 or Even  
Odd  
Y
0.5  
(trunc[CLKD/2])/CLKD  
For details about clock division factor CLKD, see the AM35x ARM Microprocessor Technical Reference  
Manual (literature number SPRUGR0).  
SD1  
SD2  
mmcx_clk  
SD3  
SD4  
mmcx_cmd  
SD7  
SD8  
mmcx_dat[3:0]  
030-108  
In mmcx, x is equal to 1, 2, or 3.  
Figure 6-70. MMC/SD/SDIO Standard SD Mode Data/Command Receive  
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SD1  
SD2  
mmcx_clk  
SD5  
SD6  
SD5  
mmcx_cmd  
SD6  
mmcx_dat[3:0]  
030-109  
In mmcx, x is equal to 1, 2, or 3.  
Figure 6-71. MMC/SD/SDIO Standard SD Mode Data/Command Transmit  
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6.8 Test Interfaces  
The emulation and trace interfaces allow tracing activities of the following CPUs:  
•
ARM CortexTM-A8 through an Embedded Trace Macro-cell (ETM11) dedicated to enable real-time  
trace of the ARM subsystem operations.  
All processors can be emulated via JTAG ports.  
6.8.1 Embedded Trace Macro Interface (ETM)  
The following tables assume testing over the recommended operating conditions.  
Table 6-154. Embedded Trace Macro Interface Switching Characteristics  
NO.  
PARAMETER  
Frequency, etk_clk  
MIN  
MAX  
UNIT  
f
1/tc(CLK)  
166  
MHz  
ns  
ETM0 tc(CLK)  
Cycle time  
6.02  
3.01  
-0.5  
-0.5  
ETM1 tW(CLK)  
ETM2 td(CLK-CTL)  
ETM3 td(CLK-D)  
Clock pulse width, etk_clk  
ns  
Delay time, etk_clk clock edge to etk_ctl transition  
Delay time, etk_clk clock high to etk_d[15:0] transition  
0.5  
0.5  
ns  
ns  
ETM0  
ETM1  
etk_clk  
etk_ctl  
ETM2  
ETM2  
ETM3  
ETM3  
etk_d[15:0]  
030-110  
Figure 6-72. Embedded Trace Macro Interface  
6.8.2 JTAG Interfaces  
AM3517/05 JTAG TAP controller handles standard IEEE JTAG interfaces. The following sections define  
the timing requirements for several tools used to test the AM3517/05 processors as:  
•
•
Free running clock tool, like XDS560 and XDS510 tools  
Adaptive clock tool, like RealView ICE tool and Lauterbach tool  
6.8.2.1 JTAG Free Running Clock Mode  
The following tables assume testing over the recommended operating conditions and electrical  
characteristic conditions.  
Table 6-155. JTAG Timing Conditions Free Running Clock Mode  
1.8 V  
MAX  
3.3 V  
MAX  
TIMING CONDITION PARAMETER  
UNIT  
Input Conditions  
tR  
Input signal rise time  
Input signal fall time  
5
5
3
3
ns  
ns  
tF  
Output Conditions  
CLOAD  
Output load capacitance  
30  
pF  
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UNIT  
Table 6-156. JTAG Timing Requirements Free Running Clock Mode(1)(2)(3)  
1.8V  
3.3V  
NO.  
PARAMETER  
Cycle time  
MIN  
20  
MAX  
MIN  
20  
MAX  
JT4  
JT5  
JT6  
tc(tck)  
tw(tckL)  
ns  
ns  
ns  
ps  
ps  
ns  
ns  
ns  
ns  
ns  
ns  
Typical pulse duration, jtag_tck low  
Typical pulse duration, jtag_tck high  
Duty cycle error, jtag_tck  
10  
10  
tw(tckH)  
10  
10  
tdc(tck)  
-1250  
-1250  
1.8  
1250  
1250  
-1250  
-1250  
3.8  
1250  
1250  
tj(tck)  
Cycle jitter  
JT7  
JT8  
tsu(tdiV-rtckH)  
th(tdiV-rtckH)  
tsu(tmsV-rtckH)  
th(tmsV-rtckH)  
Setup time, jtag_tdi valid before jtag_rtck high  
Hold time, jtag_tdi valid after jtag_rtck high  
Setup time, jtag_tms valid before jtag_rtck high  
Hold time, jtag_tms valid after jtag_rtck high  
Setup time, jtag_emux  
0.7  
2.7  
JT9  
1.8  
3.8  
JT10  
0.7  
2.7  
JT12 tsu(emuxV-rtckH)  
JT13 th(emuxV-rtckH)  
14.6  
2
14.6  
2
Hold time,jtag_emux  
(1) Maximum cycle jitter supported by jtag _tck input clock.  
(2) x = 0 to 1  
(3) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.  
Table 6-157. JTAG Switching Characteristics Free Running Clock Mode(1)(2)  
1.8 V  
3.3 V  
NO.  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
UNIT  
JT1 tc(rtck)  
JT2 tw(rtckL)  
JT3 tw(rtckH)  
tdc(rtck)  
Cycle time(1), jtag_rtck period  
Typical pulse duration, jtag_rtck low  
Typical pulse duration, jtag_rtck high  
Duty cycle error, jtag_rtck  
Jitter standard deviation(2), jtag_rtck  
Rise time, jtag_rtck  
20  
10  
20  
10  
ns  
ns  
ns  
ps  
ps  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10  
10  
-1250  
1250  
-1250  
1250  
tj(rtck)  
33.33  
33.33  
tR(rtck)  
4
4
4
4
tF(rtck)  
Fall time, jtag_rtck  
JT11 td(rtckL-tdoV)  
tR(tdo)  
Delay time, jtag_rtck low to jtag_tdo valid  
Rise time, jtag_tdo  
-5.8  
2.7  
5.8  
4
-8  
8
4
tF(tdo)  
Fall time, jtag_tdo  
4
4
JT14 td(rtckH-emuxV)  
tR(emux)  
Delay time, jtag_rtck high to ,jtag_emux  
Rise time, jtag_emux  
15.1  
6
2.7  
15.1  
6
tF(emux)  
Fall time, jtag_emux  
6
6
(1) Related with the jtag_rtck maximum frequency.  
(2) The jitter probability density can be approximated by a Gaussian function.  
212  
Timing Requirements and Switching Characteristics  
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Submit Documentation Feedback  
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SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
JT4  
JT1  
JT5  
JT2  
JT6  
JT3  
jtag_tck  
jtag_rtck  
jtag_tdi  
JT7  
JT9  
JT8  
JT10  
JT13  
jtag_tms  
JT12  
jtag_emux(IN)  
jtag_tdo  
JT11  
JT14  
jtag_emux(OUT)  
030-113  
In jtag_emux, x is equal to 0 to 1.  
Figure 6-73. JTAG Interface Timing Free Running Clock Mode  
6.8.2.2 JTAG Adaptive Clock Mode  
The following tables assume testing over the recommended operating conditions and electrical  
characteristic conditions.  
Table 6-158. JTAG Timing Conditions Adaptive Clock Mode  
1.8 V  
MAX  
3.3 V  
MAX  
TIMING CONDITION PARAMETER  
Input Conditions  
UNIT  
tR  
Input signal rise time  
Input signal fall time  
5
5
3
3
ns  
ns  
tF  
Output Conditions  
CLOAD  
Output load capacitance  
30  
pF  
Table 6-159. JTAG Timing Requirements Adaptive Clock Mode(1)(2)  
1.8 V  
3.3 V  
NO.  
PARAMETER  
Cycle time  
MIN  
MAX  
MIN  
MAX  
UNIT  
JA4  
JA5  
JA6  
tc(tck)  
20  
10  
20  
10  
ns  
ns  
ns  
ps  
ps  
ns  
ns  
ns  
ns  
tw(tckL)  
Typical pulse duration, jtag_tck low  
Typical pulse duration, jtag_tck high  
Duty cycle error, jtag_tck  
tw(tckH)  
10  
10  
tdc(lclk)  
-2500  
-1500  
13.8  
13.8  
13.8  
13.8  
2500  
1500  
-2500  
-1500  
13.8  
13.8  
13.8  
13.8  
2500  
1500  
tj(lclk)  
Cycle jitter  
JA7  
JA8  
JA9  
tsu(tdiV-tckH)  
th(tdiV-tckH)  
tsu(tmsV-tckH)  
Setup time, jtag_tdi valid before jtag_tck high  
Hold time, jtag_tdi valid after jtag_tck high  
Setup time, jtag_tms valid before jtag_tck high  
Hold time, jtag_tms valid after jtag_tck high  
JA10 th(tmsV-tckH)  
(1) Maximum cycle jitter supported by jtag _tck input clock.  
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.  
Copyright © 2009–2012, Texas Instruments Incorporated  
Timing Requirements and Switching Characteristics  
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AM3517, AM3505  
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www.ti.com  
Table 6-160. JTAG Switching Characteristics Adaptive Clock Mode(1)  
1.8 V  
3.3 V  
NO.  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
UNIT  
JA1  
JA2  
JA3  
tc(rtck)  
Cycle time  
20  
10  
20  
10  
ns  
ns  
ns  
ps  
ps  
ns  
ns  
ns  
ns  
ns  
tw(rtckL)  
tw(rtckH)  
tdc(rtck)  
tj(rtck)  
Typical pulse duration, jtag_rtck low  
Typical pulse duration, jtag_rtck high  
Duty cycle error, jtag_rtck  
Jitter standard deviation  
Rise time, jtag_rtck  
10  
10  
-2500  
2500  
-2500  
2500  
33.33  
33.33  
tR(rtck)  
tF(rtck)  
4
4
4
4
Fall time, jtag_rtck  
JA11 td(rtckL-tdoV)  
Delay time, jtag_rtck low to jtag_tdo valid  
Rise time, jtag_tdo,  
-14.6  
14.6  
4
-14.6  
14.6  
4
tR(tdo)  
tF(tdo)  
Fall time, jtag_tdo  
4
4
(1) The jitter probability density can be approximated by a Gaussian function.  
JA4  
JA5  
JA6  
jtag_tck  
JA7  
JA8  
JA10  
JA1  
jtag_tdi  
JA9  
JA2  
jtag_tms  
JA3  
jtag_rtck  
jtag_tdo  
JA11  
030-114  
Figure 6-74. JTAG Interface Timing Adaptive Clock Mode  
214  
Timing Requirements and Switching Characteristics  
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AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
7 Package Characteristics  
7.1 Package Thermal Resistance  
Table 7-1 provides the thermal resistance characteristics for the recommended package types used on the  
AM3517/05.  
Table 7-1. AM3517/05 Thermal Resistance Characteristics(1)  
BOARD TYPE  
Figure 6-31  
PACKAGE  
POWER (W)  
RJA(C/W)  
RJB(C/W)  
RJC(C/W)  
ZCN Pkg.  
ZER Pkg.  
1.6  
1.6  
24.58  
15.8  
10.81  
6
-
2S2P  
6
2S2P  
(1) RJA (Theta-JA) = Thermal Resistance Junction-to-Ambient, C/W  
RJB (Theta-JB) = Thermal Resistance Junction-to-Board, C/W  
RJC (Theta-JC) = Thermal Resistance Junction-to-Case, C/W  
7.2 Device Support  
7.2.1 Device and Development-Support Tool Nomenclature  
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all  
AM3517/05 microprocessors and support tools. Each device has one of three prefixes: X, P, or null (no  
prefix). Texas Instruments recommends two of three possible prefix designators for its support tools:  
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering  
prototypes (TMDX) through fully qualified production devices/tools (TMDS).  
Device development evolutionary flow:  
X
Experimental device that is not necessarily representative of the final devices electrical  
specifications and may not use production assembly flow. (TMX definition)  
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet  
final electrical specifications. (TMP definition)  
null  
Production version of the silicon die that is fully qualified. (TMS definition)  
Support tool development evolutionary flow:  
TMDX  
TMDS  
Development support product that has not yet completed Texas Instruments internal  
qualification testing.  
Fully qualified development support product.  
TMX and TMP devices and TMDX development-support tools are shipped against the following  
disclaimer:  
Developmental product is intended for internal evaluation purposes.  
Production devices and TMDS development-support tools have been characterized fully, and the quality  
and reliability of the device have been demonstrated fully. TIs standard warranty applies.  
Predictions show that prototype devices (X or P), have a greater failure rate than the standard production  
devices. Texas Instruments recommends that these devices not be used in any production system  
because their expected end-use failure rate still is undefined. Only qualified production devices are to be  
used.  
For additional description of the device nomenclature markings, see the AM35x ARM Microprocessor  
Silicon Errata (literature number SPRZ306).  
Copyright © 2009–2012, Texas Instruments Incorporated  
Package Characteristics  
215  
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AM3517, AM3505  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
www.ti.com  
X
AM3517  
A
ZCN  
(
)
( )  
blank = no security  
= crypto enabled  
PREFIX  
C
X
P
= Experimental Device  
= Prototype Device  
blank = commercial temperature  
= extended temperature  
blank = Production Device  
A
PACKAGE TYPE  
DEVICE  
ZCN = 491-pin sPBGA  
ZER = 484-pin sPBGA  
SILICON REVISION  
Figure 7-1. Device Nomenclature  
7.2.2 Documentation Support  
7.2.2.1 Related Documentation from Texas Instruments  
The following documents describe the AM3517/05 device. Copies of these documents are available on the  
Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.  
The current documentation that describes the AM3517/05 ARM microprocessor, related peripherals, and  
other technical collateral, is available in the product folder at: www.ti.com.  
SPRUGR0 AM35x ARM Microprocessor Technical Reference Manual. Collection of documents  
providing detailed information on the Sitara™ architecture including power, reset, and clock  
control, interrupts, memory map, and switch fabric interconnect. Detailed information on the  
microprocessor unit (MPU) subsystem as well a functional description of the peripherals  
supported on AM3517/05 devices is also included.  
7.2.2.2 Community Resources  
The following links connect to TI community resources. Linked contents are provided "AS IS" by the  
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;  
see TI's Terms of Use.  
TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration  
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and  
help solve problems with fellow engineers.  
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help  
developers get started with Embedded Processors from Texas Instruments and to foster  
innovation and growth of general knowledge about the hardware and software surrounding  
these devices.  
7.2.2.3 Related Documentation from Other Sources  
The following documents are related to the AM3517/05 device. Copies of these documents can be  
obtained directly from the internet or from your Texas Instruments representative.  
Cortex-A8 Technical Reference Manual. This is the technical reference manual for the Cortex-A8  
processor. A copy of this document can be obtained via the internet at http://infocenter.arm.com. See the  
AM35x ARM Microprocessor Silicon Errata (literature number SPRZ306) to determine the revision of the  
Cortex-A8 core used on your device.  
ARM Core Cortex™-A8 (AT400/AT401) Errata Notice. Provides a list of advisories for the different  
revisions of the Cortex-A8 processor. Contact your TI representative for a copy of this document. See the  
AM35x ARM Microprocessor Silicon Errata (literature number SPRZ306) to determine the revision of the  
Cortex-A8 core used on your device.  
216  
Package Characteristics  
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AM3517, AM3505  
www.ti.com  
SPRS550D –OCTOBER 2009–REVISED MARCH 2012  
7.3 Mechanical Data  
The following packaging information reflects the most current data available for the designated device(s).  
This data is subject to change without notice and without revision of this document.  
Copyright © 2009–2012, Texas Instruments Incorporated  
Package Characteristics  
217  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
7-Sep-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
AM3505AZCN  
AM3505AZCNA  
AM3505AZCNAC  
AM3505AZCNC  
AM3505AZER  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
OBSOLETE  
NFBGA  
NFBGA  
NFBGA  
NFBGA  
BGA  
ZCN  
ZCN  
ZCN  
ZCN  
ZER  
ZER  
ZER  
ZER  
ZCN  
ZCN  
ZCN  
ZCN  
ZER  
ZER  
ZER  
ZER  
ZCN  
491  
491  
491  
491  
484  
484  
484  
484  
491  
491  
491  
491  
484  
484  
484  
484  
491  
90  
90  
90  
90  
60  
60  
60  
60  
90  
90  
90  
90  
60  
60  
60  
60  
Green (RoHS  
& no Sb/Br)  
SNAGCU Level-3-260C-168 HR  
Green (RoHS  
& no Sb/Br)  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
SNAGCU Level-3-260C-168 HR  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
AM3505AZERA  
AM3505AZERAC  
AM3505AZERC  
AM3517AZCN  
BGA  
Green (RoHS  
& no Sb/Br)  
BGA  
Green (RoHS  
& no Sb/Br)  
BGA  
Green (RoHS  
& no Sb/Br)  
NFBGA  
NFBGA  
NFBGA  
NFBGA  
BGA  
Green (RoHS  
& no Sb/Br)  
AM3517AZCNA  
AM3517AZCNAC  
AM3517AZCNC  
AM3517AZER  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
AM3517AZERA  
AM3517AZERAC  
AM3517AZERC  
XAM3517AZCN  
BGA  
Green (RoHS  
& no Sb/Br)  
BGA  
Green (RoHS  
& no Sb/Br)  
BGA  
Green (RoHS  
& no Sb/Br)  
NFBGA  
TBD  
Call TI  
Call TI  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
7-Sep-2012  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
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