AM3359_14 [TI]
Sitara AM335x ARM Cortex-A8 Microprocessors (MPUs);
| 型号： | AM3359_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Sitara AM335x ARM Cortex-A8 Microprocessors (MPUs) |
| 文件： | 总222页 (文件大小：2693K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
®
AM335x ARM Cortex™-A8 Microprocessors (MPUs)
Check for Samples: AM3359, AM3358
1 Device Summary
1.1 Features
1234567
– 32KB of L1 Instruction Cache with Single-
Error Detection (parity)
– 32KB of L1 Data Cache with Single Error-
Detection (parity)
• Highlights
– 275-MHz, 500-MHz, 600-MHz, or 720-MHz
ARM® Cortex™-A8 32-Bit RISC
Microprocessor
– 256KB of L2 Cache with Error Correcting
Code (ECC)
– 176KB of On-Chip Boot ROM
– 64KB of Dedicated RAM
– Emulation/Debug
•
•
NEON™ SIMD Coprocessor
32KB/32KB of L1 Instruction/Data Cache
with Single-Error Detection (parity)
256KB of L2 Cache with Error Correcting
Code (ECC)
•
– mDDR(LPDDR)/DDR2/DDR3 Support
•
•
•
JTAG
– General-Purpose Memory Support (NAND,
NOR, SRAM, etc.) Supporting Up to 16-bit
ECC
Embedded Trace Module
Embedded Trace Buffer
– Interrupt Controller (up to 128 interrupt
requests)
– SGX530 3D Graphics Engine
– LCD and Touchscreen Controller
• On-Chip Memory (Shared L3 RAM)
– Programmable Real-Time Unit and Industrial
Communication Subsystem (PRU-ICSS)
– 64 KB of General-Purpose On-Chip Memory
Controller (OCMC) RAM
– Real-Time Clock (RTC)
– Accessible to all Masters
– Up to Two USB 2.0 High-Speed OTG Ports
with Integrated PHY
– 10/100/1000 Ethernet Switch Supporting Up
to Two Ports
– Supports Retention for Fast Wake-Up
• External Memory Interfaces (EMIF)
– mDDR/DDR2/DDR3 Controller:
•
•
•
mDDR: 200-MHz Clock (400-MHz Data
Rate)
DDR2: 266-MHz Clock (532-MHz Data
Rate)
DDR3: 303-MHz-MHz Clock (606-MHz Data
Rate)
– Serial Interfaces Including:
•
•
Two Controller Area Network Ports (CAN)
Six UARTs, Two McASPs, Two McSPI,
and Three I2C Ports
– 12-Bit Successive Approximation Register
(SAR) ADC
– Up to Three 32-Bit Enhanced Capture
Modules (eCAP)
– Up to Three Enhanced High-Resolution PWM
Modules (eHRPWM)
– Crypto Hardware Accelerators (AES, SHA,
PKA, RNG)
•
•
•
16-Bit Data Bus
1 GB of Total Addressable Space
Supports One x16 or Two x8 Memory
Device Configurations
•
Supports Retention for Fast Wake-Up
– General-Purpose Memory Controller (GPMC)
•
Flexible 8/16-Bit Asynchronous Memory
Interface with Up to seven Chip Selects
(NAND, NOR, Muxed-NOR, SRAM, etc.)
• MPU Subsystem
– 275-MHz, 500-MHz, 600-MHz, or 720-MHz
ARM® Cortex™-A8 32-Bit RISC
Microprocessor
•
•
Uses BCH Code to Support 4-Bit, 8-Bit, or
16-Bit ECC
Uses Hamming Code to Support 1-Bit
ECC
– NEON™ SIMD Coprocessor
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SmartReflex, DSP/BIOS, XDS are trademarks of Texas Instruments.
Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.
ARM is a registered trademark of ARM Ltd or its subsidiaries.
EtherCAT is a registered trademark of EtherCAT Technology Group.
POWERVR SGX is a trademark of Imagination Technologies Limited.
All other trademarks are the property of their respective owners.
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PRODUCT PREVIEW information concerns products in the formative or design phase of
development. Characteristic data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue these products without notice.
Copyright © 2011–2012, Texas Instruments Incorporated
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717D –OCTOBER 2011–REVISED MAY 2012
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– Error Locator Module (ELM)
• Real-Time Clock (RTC)
•
•
Used in Conjunction with the GPMC to
Locate Addresses of Data Errors from
Syndrome Polynomials Generated Using
a BCH Algorithm
Supports 4-Bit, 8-Bit, and 16-Bit per 512-
byte Block Error Location Based on BCH
Algorithms
– Real-Time Date (Day/Month/Year/Day of
Week) and Time (Hours/Minutes/Seconds)
Information
– Internal 32.768-kHz Oscillator, RTC Logic
and 1.1-V Internal LDO
– Independent Power-on-Reset
(RTC_PWRONRSTn) Input
• Programmable Real-Time Unit and Industrial
Communication Subsystem (PRU-ICSS)
– Dedicated Input Pin (EXT_WAKEUP) for
External Wake Events
– Programmable Alarm Can be Used to
Generate Internal Interrupts to the PRCM (for
Wake Up) or Cortex-A8 (for Event
Notification)
– Supports protocols such as EtherCAT®,
PROFIBUS, PROFINET, EtherNet/IP™, and
more
– Peripherals Inside the PRU-ICSS
•
One UART Port with Flow Control Pins,
Supports Up to 12 Mbps
Two MII Ethernet Ports that Support
Industrial Ethernet, such as EtherCAT
– Programmable Alarm Can be Used with
External Output (PMIC_POWER_EN) to
Enable the Power Management IC to Restore
Non-RTC Power Domains
•
• Peripherals
•
•
One MDIO Port
One Enhanced Capture (eCAP) Module
– Up to Two USB 2.0 High-Speed OTG Ports
with Integrated PHY
– Up to Two Industrial Gigabit Ethernet MACs
(10/100/1000 Mbps)
• Power Reset and Clock Management (PRCM)
Module
– Controls the entry and Exit of Stand-By and
Deep-Sleep Modes
– Responsible for Sleep Sequencing, Power
Domain Switch-Off Sequencing, Wake-Up
Sequencing and Power Domain Switch-On
Sequencing
•
•
Integrated Switch
Each MAC Supports MII/RMII/RGMII and
MDIO Interfaces
•
•
Ethernet MACs and Switch Can Operate
Independent of Other Functions
IEEE 1588v2 Precision Time Protocol
(PTP)
– Clocks
•
•
•
Integrated 15-35 MHz High-Frequency
Oscillator Used to Generate a Reference
Clock for Various System and Peripheral
Clocks
Supports Individual Clock Enable/Disable
Control for Subsystems and Peripherals
to Facilitate Reduced Power
Consumption
Five ADPLLs to Generate System Clocks
(MPU Subsystem, DDR Interface, USB
and Peripherals [MMC/SD, UART, SPI,
I2C, etc.], L3, L4, Ethernet, GFX [SGX530],
LCD Pixel Clock)
– Up to Two Controller-Area Network (CAN)
Ports
•
Supports CAN Version 2 Parts A and B
– Up to Two Multichannel Audio Serial Ports
(McASP)
•
•
Transmit/Receive Clocks Up to 50 MHz
Up to Four Serial Data Pins per McASP
Port with Independent TX/RX Clocks
•
•
•
Supports Time Division Multiplexing
(TDM), Inter-IC Sound (I2S), and similar
Formats
Supports Digital Audio Interface
Transmission (SPDIF, IEC60958-1, and
AES-3 Formats)
– Power
•
•
•
Two Non-Switchable Power Domains
(Real-Time Clock [RTC], Wake-Up Logic
[WAKE-UP])
FIFO Buffers for Transmit and Receive
(256 bytes)
Three Switchable Power Domains (MPU
Subsystem [MPU], SGX530 [GFX],
Peripherals and Infrastructure [PER])
Implements SmartReflex™ Class 2B for
Core Voltage Scaling Based On Die
Temperature, Process Variation and
Performance (Adaptive Voltage Scaling
[AVS])
– Up to Six UARTs
•
•
All UARTs Support IrDA and CIR Modes
All UARTs Support RTS and CTS Flow
Control
•
UART1 Supports Full Modem control
– Up to Two Master/Slave McSPI Serial
Interfaces
•
•
Up to Two Chip Selects
Up to 48 MHz
•
Dynamic Voltage Frequency Scaling
(DVFS)
2
Device Summary
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
– Up to Three MMC/SD/SDIO Ports
the External Frame Buffer without
Burdening the Processor via Interrupts or
a Firmware Timer
•
1-Bit, 4-Bit and 8-Bit MMC/SD/SDIO
Modes
•
•
512-Word Deep Internal FIFO
Supported Display Types:
•
MMCSD0 has dedicated Power Rail for
1.8-V or 3.3-V Operation
•
•
•
Up to 48-MHz Data Transfer Rate
Supports Card Detect and Write Protect
Complies with MMC4.3 and SD/SDIO 2.0
Specifications
–
Character Displays - Uses LCD
Interface Display Driver (LIDD)
Controller to Program these Displays
Passive Matrix LCD Displays - Uses
LCD Raster Display Controller to
Provide Timing and Data for Constant
Graphics Refresh to a Passive Display
Active Matrix LCD Displays - Uses
External Frame Buffer Space and the
Internal DMA Engine to Drive
–
– Up to Three I2C Master/Slave Interfaces
•
•
Standard Mode (up to 100 kHz)
Fast Mode (up to 400 kHz)
–
– Up to Four Banks of General-Purpose IO
(GPIO)
•
32 GPIOs per Bank (Multiplexed with
Other Functional Pins)
GPIOs Can be Used as Interrupt Inputs
(Up to Two Interrupt Inputs per Bank)
Streaming Data to the Panel
– 12-Bit Successive Approximation Register
(SAR) ADC
•
•
•
200K Samples per Second
– Up to Three External DMA Event Inputs That
Can Also be Used as Interrupt Inputs
– Eight 32-Bit General-Purpose Timers
Input Can be Selected from any of the
Eight Analog Inputs Multiplexed Through
an 8:1 analog Switch
•
DMTIMER1 is a 1-ms Timer Used for
Operating System (OS) Ticks
DMTIMER4 - DMTIMER7 are Pinned Out
•
Can be Configured to Operate as a 4-wire,
5-wire, or 8-wire Resistive Touch Screen
Controller (TSC) Interface
•
– One Watchdog Timer
– SGX530 3D Graphics Engine
– Up to Three 32-Bit Enhanced Capture
Modules (eCAP)
•
Configurable as Three Capture Inputs or
Three Auxiliary PWM Outputs
•
Tile-Based Architecture Delivering Up to
20 MPloy/sec
– Up to Three Enhanced High-Resolution PWM
Modules (eHRPWM)
•
Universal Scalable Shader Engine is a
Multi-Threaded Engine Incorporating
Pixel and Vertex Shader Functionality
Advanced Shader Feature Set in Excess
of Microsoft VS3.0, PS3.0 and OGL2.0
Industry Standard API Support of
Direct3D Mobile, OGL-ES 1.1 and 2.0,
OpenVG 1.0, and OpenMax
Fine-Grained Task Switching, Load
Balancing and Power Management
•
Dedicated 16-Bit Time-Base Counter with
Time and Frequency Controls
•
•
•
Configurable as Six Single-Ended, Six
Dual-Edge Symmetric, or Three Dual-
Edge Asymmetric Outputs
– Up to Three 32-Bit Enhanced Quadrature
Encoder Pulse (eQEP) Modules
• Device Identification
•
•
•
•
Advanced Geometry DMA Driven
Operation for Minimum CPU Interaction
– Contains Electrical fuse Farm (FuseFarm) of
Which Some Bits are Factory Programmable
Programmable High-Quality Image Anti-
Aliasing
Fully Virtualized Memory Addressing for
OS Operation in a Unified Memory
Architecture
•
•
•
Production ID
Device Part Number (Unique JTAG ID)
Device Revision (readable by Host ARM)
• Debug Interface Support
– JTAG/cJTAG for ARM (Cortex-A8 and
PRCM), PRU-ICSS Debug
– Embedded Trace Module (ETM) and
Embedded Trace Buffer (ETB)
– LCD Controller
•
•
•
Up to 24-Bits Data Output; 8-Bits per
Pixel (RGB)
Resolution Up to 2048x2048 (With
Maximum 126-MHz Pixel Clock)
Integrated LCD Interface Display Driver
(LIDD) Controller
– Supports Device Boundary Scan
– Supports IEEE 1500
• DMA
– On-Chip Enhanced DMA Controller (EDMA)
has Three Third-Party Transfer Controllers
(TPTC) and One Third-Party Channel
•
•
Integrated Raster Controller
Integrated DMA Engine to Pull Data from
Copyright © 2011–2012, Texas Instruments Incorporated
Device Summary
3
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Controller (TPCC), Which Supports Up to 64
Programmable Logical Channels and Eight
QDMA Channels. EDMA is Used for:
•
Spinlock has 128 Software-Assigned
Lock Registers
• Security
•
•
Transfers to/from On-Chip Memories
– Crypto Hardware Accelerators (AES, SHA,
PKA, RNG)
• Boot Modes
Transfers to/from External Storage (EMIF,
General-Purpose Memory Controller,
Slave Peripherals)
– Boot Mode is Selected via Boot
• Inter-Processor Communication (IPC)
Configuration Pins Latched on the Rising
Edge of the PWRONRSTn Reset Input Pin
• Packages:
– Integrates Hardware-Based Mailbox for IPC
and Spinlock for Process Synchronization
Between the Cortex-A8, PRCM, and PRU-
ICSS
– 298-Pin S-PBGA-N298 Via Channel™
package
(ZCE Suffix), 0.65-mm Ball Pitch
– 324-Pin S-PBGA-N324 package
(ZCZ Suffix), 0.80-mm Ball Pitch
•
Mailbox Registers that Generate
Interrupts
–
Four Initiators (Cortex-A8, PRCM,
PRU0, PRU1)
1.2 Applications
•
•
•
•
•
Gaming Peripherals
•
•
•
•
Connected Vending Machines
Weighing Scales
Home and Industrial Automation
Consumer Medical Appliances
Printers
Educational Consoles
Advanced Toys
Smart Toll Systems
1.3 Description
The AM335x microprocessors, based on the ARM Cortex-A8, are enhanced with image, graphics
processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The device
supports the following high-level operating systems (HLOSs) that are available free of charge from TI:
•
•
Linux®
Android™
The AM335x microprocessor contains these subsystems:
•
•
Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor.
POWERVR SGX™ Graphics Accelerator subsystem for 3D graphics acceleration to support display
and gaming effects.
•
The Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) is separate
from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility.
The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT,
PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others.
4
Device Summary
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
1.4 Functional Block Diagram
The AM335x microprocessor functional block diagram is shown in Figure 1-1.
Display
Graphics
ARM
Cortex-A8
275/500/600/720 MHz
PowerVR
SGX
3D GFX
24-bit LCD controller
Touch screen controller
PRU-ICSS
Crypto
32K/32K L1 w/SED
256K L2 w/ECC
EtherCAT, PROFINET,
EtherNet/IP,
and more
64K
shared
RAM
176K ROM 64K RAM
L3/L4 interconnect
Serial
System
Parallel
eCAP x3
UART x6
SPI x2
I2C x3
eDMA
Timers x8
WDT
MMC/SD/
SDIO x3
ADC (8 channel)
12-bit SAR
GPIO
JTAG/
ETM/ETB
McASP x2
(4 channel)
RTC
eHRPWM x3
eQEP x3
PRCM
Crystal
Oscillator x2
CAN x2
(Ver. 2 A and B)
USB 2.0 HS
OTG + PHY x2
Memory interface
mDDR(LPDDR) / DDR2 / DDR3
(16-bit, 200 / 266 / 303 MHz)
EMAC (2-port) 10M/100M/1G
IEEE 1588v2, and switch
(MII, RMII, RGMII)
NAND/NOR (16-bit ECC)
Figure 1-1. AM335x Functional Block Diagram
Copyright © 2011–2012, Texas Instruments Incorporated
Device Summary
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
1
Device Summary ........................................ 1
1.1 Features ............................................. 1
1.2 Applications .......................................... 4
1.3 Description ........................................... 4
1.4 Functional Block Diagram ........................... 5
5.1 Parameter Information ............................ 108
5.2
Recommended Clock and Control Signal Transition
Behavior ........................................... 108
5.3 Controller Area Network (CAN) ................... 109
5.4
Ethernet Media Access Controller (EMAC)/Switch
..................................................... 110
Revision History .............................................. 7
2
5.5 External Memory Interfaces ....................... 117
5.6 Inter-Integrated Circuit (I2C) ...................... 179
5.7 LCD Controller (LCDC) ............................ 181
Terminal Description ................................... 8
2.1 Pin Assignments ..................................... 8
2.2 Ball Characteristics ................................. 16
2.3 Signal Description .................................. 48
Device Operating Conditions ....................... 77
3.1 Absolute Maximum Ratings ........................ 77
3.2 Recommended Operating Conditions .............. 80
3.3 DC Electrical Characteristics ....................... 83
3.4 External Capacitors ................................. 87
5.8
Multichannel Audio Serial Port (McASP) .......... 197
Multichannel Serial Port Interface (McSPI) ....... 202
5.9
3
5.10 Multimedia Card (MMC) Interface ................. 208
5.11 Universal Asynchronous Receiver Transmitter
(UART) ............................................ 211
6
7
Device and Documentation Support ............. 214
6.1 Device Support .................................... 214
6.2 Documentation Support ........................... 215
3.5
Touchscreen Controller and Analog-to-Digital
Subsystem Electrical Parameters .................. 90
Mechanical Packaging and Orderable
4
5
Power and Clocking ................................... 92
4.1 Power Supplies ..................................... 92
4.2 Clock Specifications ................................ 99
Peripheral Information and Timings ............. 108
Information ............................................ 217
7.1
Thermal Data for ZCE and ZCZ Packages ....... 217
7.2 Via Channel ....................................... 217
7.3 Packaging Information ............................ 217
6
Contents
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2012) to Revision D
Page
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•
Changed SAR Samples per Second features list item ...................................................................... 3
Changed Table 2-7, Ball Characteristics (ZCE and ZCZ Packages) .................................................... 17
Changed Steady State Max. Voltage at all IO pins value in Table 3-1 ................................................. 77
Changed Transient Overshoot / Undershoot specification at IO terminal value in Table 3-1 ..................... 77
Added Latch-up Performance parameter and Footnote 10 in Table 3-1 ............................................... 77
Added a second VDD_MPU OPP100 description and value in Table 3-2 .............................................. 79
Changed MAX value for VDDA1P8V_USB0 in Table 3-2 .................................................................. 79
Changed MAX value for VDDA1P8V_USB1 in Table 3-2 .................................................................. 79
Changed MAX value for VDDA3P3V_USB1 in Table 3-2 .................................................................. 79
Added Footnote (1) to Table 3-2 ............................................................................................... 79
Added Footnote (3) to Table 3-2 ............................................................................................... 79
Changed Turbo POH values in Table 3-3 .................................................................................... 80
Changed CAP_VDD_RTC description and values in Table 3-4 .......................................................... 80
Added Footnote (3) in Table 3-4 ............................................................................................... 82
Added Section 3.5, Touchscreen Controller and Analog-to-Digital Subsystem Electrical Parameters ......... 90
Moved VDD_MPU_MON Connections to Section 4.1.3 .................................................................... 97
Added Section 4.1.4, Digital Phase-Locked Loop Power Supply Requirements .................................... 98
Deleted Pxtal parameter from Table 4-2 ...................................................................................... 100
Added Table 4-3, OSC0 Crystal Circuit Characteristics, and moved Pxtal parameter here ....................... 101
Deleted Pxtal parameter from Table 4-4 ...................................................................................... 104
Added Table 4-5, OSC1 Crystal Circuit Characteristics, and moved Pxtal parameter here ....................... 104
Added second paragraph in Section 5.1.1, Timing Parameters and Board Routing Analysis .................. 108
Added Section 5.3, Controller Area Network (CAN) ...................................................................... 109
Changed Figure 5-4 ............................................................................................................. 111
Changed Figure 5-5 ............................................................................................................. 112
Changed Figure 5-7 ............................................................................................................. 113
Changed Figure 5-8 ............................................................................................................. 114
Added Section 5.6, Inter-Integrated Circuit (I2C) ......................................................................... 179
Added Section 5.8, Multichannel Audio Serial Port (McASP) .......................................................... 197
Added Section 5.9, Multichannel Serial Port Interface (McSPI) ........................................................ 202
Added Section 5.10, Multimedia Card (MMC) Interface .................................................................. 208
Added Section 5.11, Universal Asynchronous Receiver Transmitter (UART) ...................................... 211
Copyright © 2011–2012, Texas Instruments Incorporated
Contents
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2 Terminal Description
2.1 Pin Assignments
NOTE
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An
attempt is made to use "ball" only when referring to the physical package.
2.1.1 ZCE Package Pin Maps (Top View)
The pin maps below show the pin assignments on the ZCE package in three sections (left, middle, and
right).
8
Terminal Description
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-1. ZCE Pin Map [Section Left - Top View]
A
B
I2C0_SCL
SPI0_D0
C
UART1_TXD
I2C0_SDA
D
UART1_RTSn
UART1_RXD
XXXX
E
UART0_RXD
ECAP0_IN_PWM0_OUT
UART1_CTSn
XXXX
F
19
VSS
UART0_CTSn
UART0_RTSn
UART0_TXD
VDDS
18
17
16
15
14
13
12
11
10
9
SPI0_SCLK
SPI0_CS0
WARMRSTn
EMU0
SPI0_D1
EXTINTn
SPI0_CS1
XDMA_EVENT_INTR1
TCK
XXXX
XXXX
XDMA_EVENT_INTR0
TMS
XXXX
PWRONRSTn
XXXX
XXXX
TDO
EMU1
VDDSHV6
VSS
TRSTn
TDI
CAP_VBB_MPU
VDDS_SRAM_MPU_BB
XXXX
CAP_VDD_SRAM_MPU
VDDS
VDDSHV6
VDDSHV6
VDDSHV6
VSS
AIN7
AIN5
VSS
AIN1
AIN3
XXXX
VDD_CORE
XXXX
AIN6
CAP_VDD_SRAM_CORE
VREFN
VDDS_SRAM_CORE_BG
XXXX
VSS
VREFP
XXXX
VSS
VDD_CORE
VSS
8
AIN2
AIN0
AIN4
VSSA_ADC
VDDA_ADC
CAP_VDD_RTC
XXXX
VSS
7
RTC_KALDO_ENn
RTC_XTALIN
RTC_XTALOUT
DDR_WEn
DDR_BA0
DDR_A5
VSS
RTC_PWRONRSTn
RESERVED
EXT_WAKEUP
DDR_BA2
DDR_A3
PMIC_POWER_EN
VDDS_RTC
VDDS_PLL_DDR
XXXX
VSS
VSS
6
XXXX
VSS
5
DDR_A4
XXXX
XXXX
4
XXXX
DDR_A12
DDR_A0
DDR_RASn
DDR_CASn
3
DDR_A8
XXXX
DDR_A15
DDR_A10
DDR_BA1
2
DDR_A9
DDR_CK
DDR_A7
DDR_A2
1
DDR_A6
DDR_CKn
Pin map section location
Left
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Terminal Description
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Table 2-2. ZCE Pin Map [Section Middle - Top View]
G
MMC0_CLK
MMC0_DAT0
MMC0_CMD
USB0_DRVVBUS
VDDSHV4
XXXX
H
J
K
MII1_RX_ER
RMII1_REF_CLK
MII1_TX_EN
VDD_CORE
VDD_CORE
XXXX
L
M
19
18
17
16
15
14
13
12
11
10
9
MMC0_DAT3
MMC0_DAT2
MMC0_DAT1
VDDS_PLL_MPU
VDDSHV4
VDDSHV4
VDD_CORE
VDD_CORE
VSS
MII1_COL
MII1_CRS
XXXX
MII1_RX_DV
MII1_TXD0
XXXX
MII1_RX_CLK
MII1_TXD1
MII1_TXD3
VDDS
XXXX
XXXX
VSS
VSS
VDDSHV5
VDDSHV5
VDD_CORE
VDD_CORE
VSS
VSS
VSS
XXXX
VDD_CORE
VDD_CORE
VSS
XXXX
VDD_CORE
VDD_CORE
VSS
VSS
VSS
VDD_CORE
XXXX
VSS
VSS
XXXX
XXXX
XXXX
VSS
VDD_CORE
VSS
VSS
VSS
VSS
VSS
VSS
8
VDD_CORE
VDD_CORE
VDDS_DDR
VDDS_DDR
DDR_VREF
DDR_A14
DDR_CSn0
DDR_A13
VDD_CORE
VDD_CORE
VSS
VSS
VDD_CORE
VDD_CORE
VSS
VDD_CORE
VDD_CORE
VDDS_DDR
VDDS_DDR
DDR_D11
DDR_D10
DDR_D12
DDR_D13
7
XXXX
XXXX
6
XXXX
XXXX
5
VDDS_DDR
DDR_A11
DDR_CKE
DDR_RESETn
DDR_ODT
VSS
VDDS_DDR
VDDS_DDR
DDR_DQM1
DDR_D8
DDR_D9
VSS
4
XXXX
XXXX
3
XXXX
XXXX
2
DDR_A1
DDR_VTP
DDR_DQSn1
DDR_DQS1
1
Pin map section location
Middle
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-3. ZCE Pin Map [Section Right - Top View]
N
P
R
MDC
T
USB0_VBUS
USB0_CE
XXXX
U
V
W
19
18
17
16
15
14
13
12
11
10
9
MII1_TX_CLK
MII1_TXD2
MII1_RXD3
MII1_RXD2
VDDSHV5
XXXX
MII1_RXD1
MII1_RXD0
MDIO
USB0_DP
USB0_ID
VSS
VDDA3P3V_USB0
VDDA1P8V_USB0
XXXX
USB0_DM
GPMC_CSn3
XXXX
GPMC_BEn1
GPMC_AD15
GPMC_CLK
GPMC_AD8
GPMC_CSn1
GPMC_AD4
GPMC_AD2
VSS_OSC
GPMC_WPn
GPMC_AD14
GPMC_AD9
GPMC_AD7
GPMC_AD5
GPMC_AD3
XTALOUT
VSSA_USB
XXXX
XXXX
GPMC_WAIT0
XXXX
XXXX
GPMC_CSn2
GPMC_AD6
GPMC_AD12
GPMC_AD11
XXXX
VSS
VDDS
XXXX
VSS
VDDSHV1
VDDSHV1
VDDSHV1
VSS
GPMC_AD13
GPMC_AD10
XXXX
VSS
VSS
VDD_CORE
XXXX
VDD_CORE
XXXX
XTALIN
VSS
VDDS_OSC
XXXX
GPMC_ADVn_ALE
GPMC_AD1
GPMC_BEn0_CLE
LCD_DATA15
LCD_DATA12
LCD_DATA11
LCD_DATA8
LCD_DATA6
LCD_DATA3
LCD_DATA2
GPMC_AD0
GPMC_OEn_REn
GPMC_CSn0
LCD_AC_BIAS_EN
LCD_DATA14
LCD_PCLK
LCD_DATA9
LCD_DATA5
LCD_DATA4
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDDSHV1
VDDSHV1
VDDSHV6
XXXX
XXXX
8
VDDS_PLL_CORE_LCD
LCD_HSYNC
VDDS
GPMC_WEn
LCD_VSYNC
LCD_DATA13
LCD_DATA10
XXXX
7
XXXX
VSS
6
XXXX
VDDSHV6
XXXX
5
VDDS_DDR
DDR_D0
DDR_DQM0
DDR_D14
DDR_D15
VPP
XXXX
4
DDR_D1
DDR_D4
DDR_D2
DDR_D3
XXXX
XXXX
3
DDR_D7
XXXX
LCD_DATA7
LCD_DATA1
LCD_DATA0
2
DDR_DQSn0
DDR_DQS0
DDR_D6
DDR_D5
1
Pin map section location
Right
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Terminal Description
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2.1.2 ZCZ Package Pin Maps (Top View)
The pin maps below show the pin assignments on the ZCZ package in three sections (left, middle, and
right).
12
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-4. ZCZ Pin Map [Section Left - Top View]
A
B
EXTINTn
C
ECAP0_IN_PWM0_OUT
I2C0_SDA
I2C0_SCL
D
UART1_CTSn
UART1_RTSn
UART1_RXD
E
UART0_CTSn
UART0_RTSn
UART0_TXD
UART0_RXD
VDDS
F
18
VSS
MMC0_DAT2
MMC0_DAT3
USB0_DRVVBUS
USB1_DRVVBUS
VDDSHV6
VDD_MPU
VDD_MPU
VDD_MPU
VDD_MPU
VDDS
17
16
15
14
13
12
11
10
9
SPI0_SCLK
SPI0_CS0
SPI0_D0
SPI0_D1
XDMA_EVENT_INTR0
MCASP0_AHCLKX
MCASP0_ACLKX
TCK
PWRONRSTn
EMU1
SPI0_CS1
EMU0
UART1_TXD
XDMA_EVENT_INTR1
MCASP0_AXR1
MCASP0_AXR0
CAP_VDD_SRAM_MPU
VDDS_SRAM_MPU_BB
CAP_VDD_SRAM_CORE
VDDA_ADC
MCASP0_FSX
MCASP0_ACLKR
TDI
MCASP0_FSR
MCASP0_AHCLKR
TMS
VDDSHV6
VDDSHV6
TDO
VDDSHV6
WARMRSTn
VREFN
TRSTn
CAP_VBB_MPU
AIN7
VDDSHV6
VREFP
VDDS_SRAM_CORE_BG
VSSA_ADC
VDDS_PLL_DDR
VDDS
8
AIN6
AIN5
AIN4
VSS
7
AIN3
AIN2
AIN1
VDDS_RTC
VDD_CORE
VDD_CORE
VDDS_DDR
DDR_A10
6
RTC_XTALIN
VSS_RTC
AIN0
PMIC_POWER_EN
EXT_WAKEUP
DDR_BA0
CAP_VDD_RTC
DDR_A6
5
RTC_PWRONRSTn
RTC_KALDO_ENn
DDR_BA2
DDR_WEn
DDR_A5
VDDS_DDR
DDR_A2
4
RTC_XTALOUT
RESERVED
VDD_MPU_MON
VSS
DDR_A8
3
DDR_A3
DDR_A15
DDR_A12
DDR_A0
2
DDR_A4
DDR_CK
DDR_A7
DDR_A11
1
DDR_A9
DDR_CKn
DDR_BA1
DDR_CASn
Pin map section location
Left
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Terminal Description
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Table 2-5. ZCZ Pin Map [Section Middle - Top View]
G
H
RMII1_REF_CLK
MII1_CRS
MII1_COL
VDDS_PLL_MPU
VDDSHV4
VDD_MPU
VSS
J
K
L
M
18
17
16
15
14
13
12
11
10
9
MMC0_CMD
MMC0_CLK
MMC0_DAT0
MMC0_DAT1
VDDSHV6
VDD_MPU
VSS
MII1_TXD3
MII1_RX_DV
MII1_TX_EN
MII1_RX_ER
VDDSHV4
VDD_MPU
VDD_CORE
VSS
MII1_TX_CLK
MII1_TXD0
MII1_TXD1
MII1_TXD2
VDDSHV5
VDDS
MII1_RX_CLK
MII1_RXD3
MII1_RXD2
MII1_RXD1
VDDSHV5
VSS
MDC
MDIO
MII1_RXD0
USB0_CE
VSSA_USB
VDD_CORE
VSS
VDD_CORE
VSS
VSS
VSS
VDD_CORE
VSS
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDDS_DDR
DDR_D14
DDR_D13
DDR_DQSn1
DDR_DQS1
VSS
8
VSS
VSS
VSS
VDD_CORE
VSS
VSS
7
VDD_CORE
VDD_CORE
VDDS_DDR
DDR_RASn
DDR_CKE
DDR_RESETn
DDR_ODT
VSS
VSS
VSS
6
VSS
VSS
VDD_CORE
VDDS_DDR
DDR_D12
DDR_D11
DDR_D10
DDR_D9
VSS
5
VDDS_DDR
DDR_A14
DDR_A13
DDR_CSn0
DDR_A1
VDDS_DDR
DDR_VREF
DDR_VTP
DDR_DQM1
DDR_D8
VPP
4
DDR_D1
DDR_D0
DDR_DQM0
DDR_D15
3
2
1
Pin map section location
Middle
14
Terminal Description
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-6. ZCZ Pin Map [Section Right - Top View]
N
P
R
USB1_DM
T
U
V
18
17
USB0_DM
USB0_DP
USB1_CE
USB1_ID
USB0_ID
USB0_VBUS
VDDS
USB1_VBUS
GPMC_WAIT0
GPMC_A10
GPMC_BEn1
GPMC_WPn
GPMC_A9
VSS
USB1_DP
GPMC_A11
GPMC_A8
GPMC_A5
GPMC_A1
GPMC_AD14
GPMC_CLK
VSS_OSC
XTALIN
16
15
14
13
12
11
10
9
VDDA1P8V_USB0
VDDA3P3V_USB0
VSSA_USB
VDD_CORE
VDD_CORE
VSS
VDDA1P8V_USB1
VDDA3P3V_USB1
GPMC_A4
GPMC_A7
GPMC_A6
GPMC_A3
GPMC_A2
VDDSHV3
VDDSHV3
VDDSHV2
VDDSHV2
VDDS
GPMC_A0
GPMC_CSn3
GPMC_AD12
GPMC_AD10
GPMC_AD9
GPMC_AD7
GPMC_AD3
GPMC_OEn_REn
GPMC_BEn0_CLE
LCD_DATA15
LCD_DATA7
LCD_DATA6
LCD_DATA5
LCD_DATA4
GPMC_AD15
GPMC_AD11
XTALOUT
GPMC_AD13
VDDS_OSC
VSS
VDDS_PLL_CORE_LCD
GPMC_AD6
GPMC_AD8
GPMC_CSn1
GPMC_AD4
GPMC_AD0
GPMC_WEn
LCD_VSYNC
LCD_DATA11
LCD_DATA10
LCD_DATA9
LCD_DATA8
VDD_CORE
VDD_CORE
VSS
GPMC_CSn2
GPMC_AD5
GPMC_AD1
GPMC_CSn0
LCD_PCLK
LCD_DATA14
LCD_DATA13
LCD_DATA12
VSS
8
VDDSHV1
VDDSHV1
VDDSHV6
VDDSHV6
DDR_D7
GPMC_AD2
7
GPMC_ADVn_ALE
LCD_AC_BIAS_EN
LCD_HSYNC
LCD_DATA3
6
VDDS
5
VDDSHV6
DDR_D5
4
3
DDR_D4
DDR_D6
LCD_DATA2
2
DDR_D3
DDR_DQSn0
DDR_DQS0
LCD_DATA1
1
DDR_D2
LCD_DATA0
Pin map section location
Right
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Terminal Description
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2.2 Ball Characteristics
The AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number
SPRUH73) and this document may reference internal signal names when discussing peripheral input and
output signals since many of the AM335x package terminals can be multiplexed to one of several
peripheral signals. The following table has a Pin Name column that lists all device terminal names and a
Signal Name column that lists all internal signal names multiplexed to each terminal which provides a
cross reference of internal signal names to terminal names. This table also identifies other important
terminal characteristics.
1. BALL NUMBER: Package ball number(s) associated with each signal(s).
2. PIN NAME: The name of the package pin or terminal.
Note: The table does not take into account subsystem terminal multiplexing options.
3. SIGNAL NAME: The signal name for that pin in the mode being used.
4. MODE: Multiplexing mode number.
(a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the
terminal corresponds to the name of the terminal. There is always a function mapped on the
primary mode. Notice that primary mode is not necessarily the default mode.
Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE
column.
(b) Modes 1 to 7 are possible modes for alternate functions. On each terminal, some modes are
effectively used for alternate functions, while some modes are not used and do not correspond to a
functional configuration.
5. TYPE: Signal direction
–
–
–
–
–
–
–
–
I = Input
O = Output
I/O = Input/Output
D = Open drain
DS = Differential
A = Analog
PWR = Power
GND = Ground
Note: In the safe_mode, the buffer is configured in high-impedance.
6. BALL RESET STATE: The state of the terminal at the power-on reset.
–
0: The buffer drives VOL (pulldown/pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor
1: The buffer drives VOH (pulldown/pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor
Z: High-impedance
–
–
–
–
L: High-impedance with an active pulldown resistor
H : High-impedance with an active pullup resistor
7. BALL RESET REL. STATE: The state of the terminal at the release of the System Control Module
reset (PRCM CORE_RSTPWRON_RET reset signal).
–
0: The buffer drives VOL (pulldown/pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor
1: The buffer drives VOH (pulldown/pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor
Z: High-impedance.
–
–
–
–
L: High-impedance with an active pulldown resistor
H : High-impedance with an active pullup resistor
8. RESET REL. MODE: The mode is automatically configured at the release of the System Control
Module reset (PRCM CORE_RSTPWRON_RET reset signal).
16
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
9. POWER: The voltage supply that powers the terminal’s I/O buffers.
10. HYS: Indicates if the input buffer is with hysteresis.
11. BUFFER STRENGTH: Drive strength of the associated output buffer.
12. PULLUP/DOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and
pulldown resistors can be enabled or disabled via software.
13. I/O CELL: IO cell information.
Note: Configuring two terminals to the same input signal is not supported as it can yield unexpected
results. This can be easily prevented with the proper software configuration.
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Terminal Description
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
Analog
[5]
STATE [6]
B8
B6
C7
B7
A7
C8
B8
A8
C9
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
0
A (17)
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
VDDA_ADC /
VDDA_ADC
NA
NA
NA
NA
NA
NA
NA
NA
25
NA
A11
A8
0
0
0
0
0
0
0
A (16)
A (16)
A (15)
A (15)
A
Z
Z
Z
Z
Z
Z
Z
VDDA_ADC /
VDDA_ADC
25
NA
NA
NA
NA
NA
NA
NA
Analog
VDDA_ADC /
VDDA_ADC
25
Analog
B11
C8
VDDA_ADC /
VDDA_ADC
25
Analog
VDDA_ADC /
VDDA_ADC
25
Analog
B12
A10
A12
VDDA_ADC /
VDDA_ADC
NA
NA
NA
Analog
A
VDDA_ADC /
VDDA_ADC
Analog
A
VDDA_ADC /
VDDA_ADC
Analog
C13
D6
C10
D6
CAP_VBB_MPU
CAP_VBB_MPU
CAP_VDD_RTC
NA
NA
NA
NA
0
A
A
A
A
O
CAP_VDD_RTC
B10
D13
F3
D9
CAP_VDD_SRAM_CORE
CAP_VDD_SRAM_MPU
DDR_A0
CAP_VDD_SRAM_CORE
CAP_VDD_SRAM_MPU
ddr_a0
D11
F3
H
H
H
H
H
H
H
H
H
H
H
H
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
VDDS_DDR /
VDDS_DDR
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
8
8
8
8
8
8
8
8
8
8
8
8
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS/SSTL/
HSTL
J2
H1
E4
C3
C2
B1
D5
E2
D4
C1
F4
F2
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
ddr_a1
ddr_a2
ddr_a3
ddr_a4
ddr_a5
ddr_a6
ddr_a7
ddr_a8
ddr_a9
ddr_a10
ddr_a11
0
0
0
0
0
0
0
0
0
0
0
O
O
O
O
O
O
O
O
O
O
O
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
D1
B3
E5
A2
B1
D2
C3
B2
E2
G4
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
18
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ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
DDR_A12
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
F4
H1
H3
E3
A3
E1
B4
F1
C2
G3
C1
H2
N4
P4
P2
P1
P3
T1
T2
R3
K2
K1
M3
E3
H3
H4
D3
C4
E1
B3
F1
D2
G3
D1
H2
M3
M4
N1
N2
N3
N4
P3
P4
J1
ddr_a12
ddr_a13
ddr_a14
ddr_a15
ddr_ba0
ddr_ba1
ddr_ba2
ddr_casn
ddr_ck
0
O
O
O
O
O
O
O
O
O
O
O
O
H
H
H
H
H
H
H
H
L
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDDS_DDR /
VDDS_DDR
NA
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS/SSTL/
HSTL
DDR_A13
DDR_A14
DDR_A15
DDR_BA0
DDR_BA1
DDR_BA2
DDR_CASn
DDR_CK
DDR_CKE
DDR_CKn
DDR_CSn0
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
ddr_cke
ddr_nck
ddr_csn0
ddr_d0
L
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
H
H
L
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDS_DDR /
VDDS_DDR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LVCMOS/SSTL/
HSTL
ddr_d1
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d2
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d3
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d4
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d5
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d6
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d7
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d8
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
K1
K2
ddr_d9
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d10
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
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Terminal Description
19
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
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I/O CELL [13]
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
DDR_D11
SIGNAL NAME [3]
MODE [4]
[5]
STATE [6]
M4
M2
M1
N2
N1
N3
K3
R1
L1
K3
K4
L3
ddr_d11
ddr_d12
ddr_d13
ddr_d14
ddr_d15
ddr_dqm0
ddr_dqm1
ddr_dqs0
ddr_dqs1
ddr_dqsn0
ddr_dqsn1
ddr_odt
0
I/O
L
L
L
L
L
H
H
L
L
L
L
L
H
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
Yes
Yes
Yes
Yes
NA
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
NA
LVCMOS/SSTL/
HSTL
DDR_D12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I/O
I/O
I/O
I/O
O
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
DDR_D13
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
L4
DDR_D14
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
M1
M2
J2
DDR_D15
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
DDR_DQM0
DDR_DQM1
DDR_DQS0
DDR_DQS1
DDR_DQSn0
DDR_DQSn1
DDR_ODT
1
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
O
1
0
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
P1
L1
I/O
I/O
I/O
I/O
O
Z
0
VDDS_DDR /
VDDS_DDR
Yes
Yes
Yes
Yes
NA
LVCMOS/SSTL/
HSTL
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
R2
L2
P2
L2
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
G1
F2
G1
G4
G2
J4
0
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
DDR_RASn
DDR_RESETn
DDR_VREF
DDR_VTP
ddr_rasn
ddr_resetn
ddr_vref
ddr_vtp
O
1
0
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
G2
H4
J1
O
0
0
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
A (13) NA
NA
NA
1
NA
NA
0
VDDS_DDR /
VDDS_DDR
NA
NA
NA
8
Analog
(14)
J3
I
NA
H
VDDS_DDR /
VDDS_DDR
NA
NA
Analog
A4
E18
B2
C18
DDR_WEn
ddr_wen
O
VDDS_DDR /
VDDS_DDR
NA
PU/PD
PU/PD
LVCMOS/SSTL/
HSTL
ECAP0_IN_PWM0_OUT
eCAP0_in_PWM0_out
uart3_txd
0
1
2
3
4
5
6
7
0
7
I/O
O
Z
L
7
VDDSHV6 /
VDDSHV6
Yes
4
LVCMOS
spi1_cs1
I/O
I/O
I/O
I
pr1_ecap0_ecap_capin_apwm_o
spi1_sclk
mmc0_sdwp
xdma_event_intr2
gpio0_7
I
I/O
I/O
I/O
A15
C14
EMU0
EMU0
H
H
0
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
gpio3_7
20
Terminal Description
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ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
D14
B14
EMU1
EMU1
gpio3_8
nNMI
0
I/O
H
H
0
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
7
0
I/O
I
C17
B5
B18
C5
EXTINTn
Z
L
L
H
L
L
0
0
7
VDDSHV6 /
VDDSHV6
Yes
Yes
NA
NA
6
PU/PD
NA
LVCMOS
LVCMOS
LVCMOS
EXT_WAKEUP
GPMC_A0
EXT_WAKEUP
0
I
VDDS_RTC /
VDDS_RTC
NA
R13
gpmc_a0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
O
O
O
O
I
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
PU/PD
gmii2_txen
rgmii2_tctl
rmii2_txen
gpmc_a16
pr1_mii_mt1_clk
ehrpwm1_tripzone_input
gpio1_16
I
I/O
O
I
NA
NA
NA
V14
U14
T14
GPMC_A1
GPMC_A2
GPMC_A3
gpmc_a1
L
L
L
L
L
L
7
7
7
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
gmii2_rxdv
rgmii2_rctl
I
mmc2_dat0
gpmc_a17
pr1_mii1_txd3
ehrpwm0_synco
gpio1_17
I/O
O
O
O
I/O
O
O
O
I/O
O
O
O
I/O
O
O
O
I/O
O
O
O
I/O
gpmc_a2
gmii2_txd3
rgmii2_td3
mmc2_dat1
gpmc_a18
pr1_mii1_txd2
ehrpwm1A
gpio1_18
gpmc_a3
gmii2_txd2
rgmii2_td2
mmc2_dat2
gpmc_a19
pr1_mii1_txd1
ehrpwm1B
gpio1_19
Copyright © 2011–2012, Texas Instruments Incorporated
Terminal Description
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_A4
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
NA
NA
NA
NA
R14
V15
U15
T15
gpmc_a4
0
O
O
O
O
O
O
I
L
L
L
L
L
7
7
7
7
NA / VDDSHV3 Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
gmii2_txd1
rgmii2_td1
rmii2_txd1
gpmc_a20
pr1_mii1_txd0
eQEP1A_in
gpio1_20
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I/O
O
O
O
O
O
I
GPMC_A5
GPMC_A6
GPMC_A7
gpmc_a5
L
L
L
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
LVCMOS
LVCMOS
LVCMOS
gmii2_txd0
rgmii2_td0
rmii2_txd0
gpmc_a21
pr1_mii1_rxd3
eQEP1B_in
gpio1_21
I
I/O
O
I
gpmc_a6
gmii2_txclk
rgmii2_tclk
mmc2_dat4
gpmc_a22
pr1_mii1_rxd2
eQEP1_index
gpio1_22
O
I/O
O
I
I/O
I/O
O
I
gpmc_a7
gmii2_rxclk
rgmii2_rclk
mmc2_dat5
gpmc_a23
pr1_mii1_rxd1
eQEP1_strobe
gpio1_23
I
I/O
O
I
I/O
I/O
22
Terminal Description
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ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_A8
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
NA
NA
NA
NA
V16
U16
T16
V17
gpmc_a8
0
O
I
L
L
L
L
L
7
7
7
7
NA / VDDSHV3 Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
gmii2_rxd3
rgmii2_rd3
mmc2_dat6
gpmc_a24
pr1_mii1_rxd0
mcasp0_aclkx
gpio1_24
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
7
0
1
7
I
I/O
O
I
I/O
I/O
O
GPMC_A9
GPMC_A10
GPMC_A11
gpmc_a9
L
L
L
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
LVCMOS
LVCMOS
LVCMOS
gmii2_rxd2
rgmii2_rd2
mmc2_dat7
gpmc_a25
I
I
I/O
O
pr1_mii_mr1_clk
mcasp0_fsx
gpio1_25
I
I/O
I/O
O
gpmc_a10
gmii2_rxd1
rgmii2_rd1
rmii2_rxd1
gpmc_a26
pr1_mii1_rxdv
mcasp0_axr0
gpio1_26
I
I
I
O
I
I/O
I/O
O
gpmc_a11
gmii2_rxd0
rgmii2_rd0
rmii2_rxd0
gpmc_a27
pr1_mii1_rxer
mcasp0_axr1
gpio1_27
I
I
I
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
W10
V9
U7
V7
GPMC_AD0
GPMC_AD1
gpmc_ad0
mmc1_dat0
gpio1_0
L
L
L
L
7
7
VDDSHV1 /
VDDSHV1
Yes
Yes
6
6
PU/PD
PU/PD
LVCMOS
LVCMOS
gpmc_ad1
mmc1_dat1
gpio1_1
VDDSHV1 /
VDDSHV1
Copyright © 2011–2012, Texas Instruments Incorporated
Terminal Description
23
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_AD2
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
V12
W13
V13
W14
U14
W15
V15
R8
T8
gpmc_ad2
mmc1_dat2
gpio1_2
0
I/O
L
L
L
L
L
L
L
L
7
7
7
7
7
7
7
VDDSHV1 /
VDDSHV1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
6
6
6
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
2
3
4
5
7
0
1
2
3
4
5
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
GPMC_AD3
GPMC_AD4
GPMC_AD5
GPMC_AD6
GPMC_AD7
GPMC_AD8
gpmc_ad3
mmc1_dat3
gpio1_3
L
L
L
L
L
L
VDDSHV1 /
VDDSHV1
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
U8
V8
R9
T9
gpmc_ad4
mmc1_dat4
gpio1_4
VDDSHV1 /
VDDSHV1
gpmc_ad5
mmc1_dat5
gpio1_5
VDDSHV1 /
VDDSHV1
gpmc_ad6
mmc1_dat6
gpio1_6
VDDSHV1 /
VDDSHV1
gpmc_ad7
mmc1_dat7
gpio1_7
VDDSHV1 /
VDDSHV1
U10
gpmc_ad8
lcd_data23
mmc1_dat0
mmc2_dat4
ehrpwm2A
VDDSHV1 /
VDDSHV2
I/O
I/O
O
pr1_mii_mt0_clk
gpio0_22
I
I/O
I/O
O
W16
T10
GPMC_AD9
gpmc_ad9
lcd_data22
mmc1_dat1
mmc2_dat5
ehrpwm2B
pr1_mii0_col
gpio0_23
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
I/O
I/O
O
I
I/O
24
Terminal Description
Copyright © 2011–2012, Texas Instruments Incorporated
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ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_AD10
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
T12
U12
U13
T11
U12
T12
gpmc_ad10
lcd_data21
mmc1_dat2
mmc2_dat6
0
I/O
L
L
L
L
7
7
7
VDDSHV1 /
VDDSHV2
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
I/O
I/O
I
ehrpwm2_tripzone_input
pr1_mii0_txen
gpio0_26
O
I/O
I/O
O
GPMC_AD11
gpmc_ad11
L
VDDSHV1 /
VDDSHV2
LVCMOS
lcd_data20
mmc1_dat3
I/O
I/O
O
mmc2_dat7
ehrpwm0_synco
pr1_mii0_txd3
gpio0_27
O
I/O
I/O
O
GPMC_AD12
gpmc_ad12
L
VDDSHV1 /
VDDSHV2
LVCMOS
lcd_data19
mmc1_dat4
I/O
I/O
I
mmc2_dat0
eQEP2A_in
pr1_mii0_txd2
pr1_pru0_pru_r30_14
gpio1_12
O
O
I/O
I/O
O
T13
R12
GPMC_AD13
gpmc_ad13
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
lcd_data18
mmc1_dat5
I/O
I/O
I
mmc2_dat1
eQEP2B_in
pr1_mii0_txd1
pr1_pru0_pru_r30_15
gpio1_13
O
O
I/O
I/O
O
W17
V13
GPMC_AD14
gpmc_ad14
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
lcd_data17
mmc1_dat6
I/O
I/O
I/O
O
mmc2_dat2
eQEP2_index
pr1_mii0_txd0
pr1_pru0_pru_r31_14
gpio1_14
I
I/O
Copyright © 2011–2012, Texas Instruments Incorporated
Terminal Description
25
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_AD15
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
V17
U13
gpmc_ad15
lcd_data16
0
I/O
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
2
7
0
2
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
7
O
mmc1_dat7
mmc2_dat3
eQEP2_strobe
I/O
I/O
I/O
I/O
I
pr1_ecap0_ecap_capin_apwm_o
pr1_pru0_pru_r31_15
gpio1_15
I/O
O
V10
V8
R7
GPMC_ADVn_ALE
GPMC_BEn0_CLE
GPMC_BEn1
gpmc_advn_ale
timer4
H
H
H
H
H
H
7
7
7
VDDSHV1 /
VDDSHV1
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
I/O
I/O
O
gpio2_2
T6
gpmc_be0n_cle
timer5
VDDSHV1 /
VDDSHV1
I/O
I/O
O
gpio2_5
V18
U18
gpmc_be1n
gmii2_col
VDDSHV1 /
VDDSHV3
I
gpmc_csn6
mmc2_dat3
gpmc_dir
O
I/O
O
pr1_mii1_rxlink
mcasp0_aclkr
gpio1_28
I
I/O
I/O
I/O
O
V16
V12
GPMC_CLK
gpmc_clk
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
lcd_memory_clk
gpmc_wait1
mmc2_clk
I
I/O
I
pr1_mii1_crs
pr1_mdio_mdclk
mcasp0_fsr
gpio2_1
O
I/O
I/O
O
W8
V6
GPMC_CSn0
gpmc_csn0
gpio1_29
H
H
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
I/O
26
Terminal Description
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ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_CSn1
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
V14
U15
U17
U9
gpmc_csn1
gpmc_clk
mmc1_clk
0
O
H
H
H
H
7
7
7
VDDSHV1 /
VDDSHV1
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
3
4
5
6
7
0
2
7
0
1
2
3
4
5
6
7
0
2
7
I/O
I/O
I
pr1_edio_data_in6
pr1_edio_data_out6
pr1_pru1_pru_r30_12
pr1_pru1_pru_r31_12
gpio1_30
O
O
I
I/O
O
O
I/O
I
V9
GPMC_CSn2
gpmc_csn2
H
VDDSHV1 /
VDDSHV1
LVCMOS
gpmc_be1n
mmc1_cmd
pr1_edio_data_in7
pr1_edio_data_out7
pr1_pru1_pru_r30_13
pr1_pru1_pru_r31_13
gpio1_31
O
O
I
I/O
O
I/O
I
T13
GPMC_CSn3
gpmc_csn3
H
VDDSHV1 /
VDDSHV2
LVCMOS
mmc2_cmd
pr1_mii0_crs
pr1_mdio_data
EMU4
I/O
I/O
I/O
O
I/O
I/O
I
gpio2_0
W9
T7
GPMC_OEn_REn
GPMC_WAIT0
gpmc_oen_ren
timer7
H
H
H
H
7
7
VDDSHV1 /
VDDSHV1
Yes
Yes
6
6
PU/PD
PU/PD
LVCMOS
LVCMOS
gpio2_3
R15
T17
gpmc_wait0
gmii2_crs
VDDSHV1 /
VDDSHV3
I
gpmc_csn4
O
I
rmii2_crs_dv
mmc1_sdcd
pr1_mii1_col
uart4_rxd
I
I
I
gpio0_30
I/O
O
I/O
I/O
U8
U6
GPMC_WEn
gpmc_wen
H
H
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
timer6
gpio2_4
Copyright © 2011–2012, Texas Instruments Incorporated
Terminal Description
27
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_WPn
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
W18
U17
gpmc_wpn
gmii2_rxerr
gpmc_csn5
rmii2_rxerr
mmc2_sdcd
pr1_mii1_txen
uart4_txd
0
O
I
H
H
7
VDDSHV1 /
VDDSHV3
Yes
6
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
O
I
I
O
O
gpio0_31
I/O
I/OD
I/O
I
C18
B19
W7
C17
C16
R6
I2C0_SDA
I2C0_SDA
timer4
Z
Z
Z
H
H
L
7
7
7
VDDSHV6 /
VDDSHV6
Yes
Yes
Yes
4
4
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
uart2_ctsn
eCAP2_in_PWM2_out
gpio3_5
I/O
I/O
I/OD
I/O
O
I2C0_SCL
I2C0_SCL
VDDSHV6 /
VDDSHV6
timer7
uart2_rtsn
eCAP1_in_PWM1_out
gpio3_6
I/O
I/O
O
LCD_AC_BIAS_EN
lcd_ac_bias_en
gpmc_a11
VDDSHV6 /
VDDSHV6
O
pr1_mii1_crs
I
pr1_edio_data_in5
pr1_edio_data_out5
pr1_pru1_pru_r30_11
pr1_pru1_pru_r31_11
gpio2_25
I
O
O
I
I/O
I/O
O
U1
R1
LCD_DATA0 (3)
lcd_data0
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
gpmc_a0
pr1_mii_mt0_clk
ehrpwm2A
I
O
pr1_pru1_pru_r30_0
pr1_pru1_pru_r31_0
gpio2_6
O
I
I/O
28
Terminal Description
Copyright © 2011–2012, Texas Instruments Incorporated
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AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
LCD_DATA1 (3)
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
U2
V1
V2
W2
W3
R2
R3
R4
T1
T2
lcd_data1
0
I/O
Z
Z
Z
Z
Z
Z
7
7
7
7
7
VDDSHV6 /
VDDSHV6
Yes
Yes
Yes
Yes
Yes
6
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
gpmc_a1
1
2
3
5
6
7
0
1
2
3
5
6
7
0
1
2
3
5
6
7
0
1
2
3
5
6
7
0
1
2
3
5
6
7
O
O
O
O
I
pr1_mii0_txen
ehrpwm2B
pr1_pru1_pru_r30_1
pr1_pru1_pru_r31_1
gpio2_7
I/O
I/O
O
O
I
LCD_DATA2 (3)
LCD_DATA3 (3)
LCD_DATA4 (3)
LCD_DATA5 (3)
lcd_data2
Z
Z
Z
Z
VDDSHV6 /
VDDSHV6
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpmc_a2
pr1_mii0_txd3
ehrpwm2_tripzone_input
pr1_pru1_pru_r30_2
pr1_pru1_pru_r31_2
gpio2_8
O
I
I/O
I/O
O
O
O
O
I
lcd_data3
VDDSHV6 /
VDDSHV6
gpmc_a3
pr1_mii0_txd2
ehrpwm0_synco
pr1_pru1_pru_r30_3
pr1_pru1_pru_r31_3
gpio2_9
I/O
I/O
O
O
I
lcd_data4
VDDSHV6 /
VDDSHV6
gpmc_a4
pr1_mii0_txd1
eQEP2A_in
pr1_pru1_pru_r30_4
pr1_pru1_pru_r31_4
gpio2_10
O
I
I/O
I/O
O
O
I
lcd_data5
VDDSHV6 /
VDDSHV6
gpmc_a5
pr1_mii0_txd0
eQEP2B_in
pr1_pru1_pru_r30_5
pr1_pru1_pru_r31_5
gpio2_11
O
I
I/O
Copyright © 2011–2012, Texas Instruments Incorporated
Terminal Description
29
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AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
LCD_DATA6 (3)
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
V3
U3
V4
W4
T3
T4
U1
U2
lcd_data6
gpmc_a6
0
I/O
Z
Z
Z
Z
Z
7
7
7
7
VDDSHV6 /
VDDSHV6
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
I
pr1_edio_data_in6
eQEP2_index
pr1_edio_data_out6
pr1_pru1_pru_r30_6
pr1_pru1_pru_r31_6
gpio2_12
I/O
O
O
I
I/O
I/O
O
I
LCD_DATA7 (3)
LCD_DATA8 (3)
LCD_DATA9 (3)
lcd_data7
Z
Z
Z
VDDSHV6 /
VDDSHV6
LVCMOS
LVCMOS
LVCMOS
gpmc_a7
pr1_edio_data_in7
eQEP2_strobe
pr1_edio_data_out7
pr1_pru1_pru_r30_7
pr1_pru1_pru_r31_7
gpio2_13
I/O
O
O
I
I/O
I/O
O
I
lcd_data8
VDDSHV6 /
VDDSHV6
gpmc_a12
ehrpwm1_tripzone_input
mcasp0_aclkx
uart5_txd
I/O
O
I
pr1_mii0_rxd3
uart2_ctsn
I
gpio2_14
I/O
I/O
O
O
I/O
I
lcd_data9
VDDSHV6 /
VDDSHV6
gpmc_a13
ehrpwm0_synco
mcasp0_fsx
uart5_rxd
pr1_mii0_rxd2
uart2_rtsn
I
O
I/O
gpio2_15
30
Terminal Description
Copyright © 2011–2012, Texas Instruments Incorporated
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AM3356, AM3354, AM3352
www.ti.com
ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
LCD_DATA10 (3)
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
U5 U3
lcd_data10
gpmc_a14
ehrpwm1A
mcasp0_axr0
pr1_mii0_rxd1
uart3_ctsn
gpio2_16
0
I/O
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
1
2
3
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
O
I/O
I
I
I/O
I/O
O
V5
U4
LCD_DATA11 (3)
LCD_DATA12 (3)
LCD_DATA13 (3)
lcd_data11
gpmc_a15
ehrpwm1B
Z
Z
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
O
mcasp0_ahclkr
mcasp0_axr2
pr1_mii0_rxd0
uart3_rtsn
I/O
I/O
I
O
gpio2_17
I/O
I/O
O
V6
V2
lcd_data12
gpmc_a16
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
eQEP1A_in
mcasp0_aclkr
mcasp0_axr2
pr1_mii0_rxlink
uart4_ctsn
I
I/O
I/O
I
I
gpio0_8
I/O
I/O
O
U6
V3
lcd_data13
gpmc_a17
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
eQEP1B_in
mcasp0_fsr
mcasp0_axr3
pr1_mii0_rxer
uart4_rtsn
I
I/O
I/O
I
O
gpio0_9
I/O
Copyright © 2011–2012, Texas Instruments Incorporated
Terminal Description
31
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AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
LCD_DATA14 (3)
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
W6
V4
lcd_data14
gpmc_a18
0
I/O
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
3
4
5
6
7
O
I/O
I/O
I
eQEP1_index
mcasp0_axr1
uart5_rxd
pr1_mii_mr0_clk
uart5_ctsn
I
I
gpio0_10
I/O
I/O
O
I/O
I/O
I/O
I
V7
T5
LCD_DATA15 (3)
lcd_data15
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
gpmc_a19
eQEP1_strobe
mcasp0_ahclkx
mcasp0_axr3
pr1_mii0_rxdv
uart5_rtsn
O
I/O
O
O
I
gpio0_11
T7
R5
LCD_HSYNC
lcd_hsync
Z
L
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
gpmc_a9
pr1_edio_data_in3
pr1_edio_data_out3
pr1_pru1_pru_r30_9
pr1_pru1_pru_r31_9
gpio2_23
O
O
I
I/O
O
O
I
W5
V5
LCD_PCLK
lcd_pclk
Z
L
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
gpmc_a10
pr1_mii0_crs
pr1_edio_data_in4
pr1_edio_data_out4
pr1_pru1_pru_r30_10
pr1_pru1_pru_r31_10
gpio2_24
I
O
O
I
I/O
O
O
I
U7
U5
LCD_VSYNC
lcd_vsync
Z
L
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
gpmc_a8
pr1_edio_data_in2
pr1_edio_data_out2
pr1_pru1_pru_r30_8
pr1_pru1_pru_r31_8
gpio2_22
O
O
I
I/O
32
Terminal Description
Copyright © 2011–2012, Texas Instruments Incorporated
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ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MCASP0_FSX
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
NA B13
mcasp0_fsx
ehrpwm0B
spi1_d0
0
I/O
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
1
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
3
4
5
6
7
O
I/O
I
mmc1_sdcd
pr1_pru0_pru_r30_1
pr1_pru0_pru_r31_1
gpio3_15
O
I
I/O
I/O
I
NA
B12
MCASP0_ACLKR
MCASP0_AHCLKR
MCASP0_AHCLKX
MCASP0_ACLKX
mcasp0_aclkr
eQEP0A_in
L
L
L
L
L
7
NA / VDDSHV6 Yes
NA / VDDSHV6 Yes
NA / VDDSHV6 Yes
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
mcasp0_axr2
mcasp1_aclkx
mmc0_sdwp
I/O
I/O
I
pr1_pru0_pru_r30_4
pr1_pru0_pru_r31_4
gpio3_18
O
I
I/O
I/O
I
NA
NA
NA
C12
A14
A13
mcasp0_ahclkr
ehrpwm0_synci
mcasp0_axr2
spi1_cs0
L
L
L
7
7
7
6
6
6
PU/PD
PU/PD
PU/PD
I/O
I/O
I/O
O
eCAP2_in_PWM2_out
pr1_pru0_pru_r30_3
pr1_pru0_pru_r31_3
gpio3_17
I
I/O
I/O
I/O
I/O
I/O
I/O
O
mcasp0_ahclkx
eQEP0_strobe
mcasp0_axr3
mcasp1_axr1
EMU4
pr1_pru0_pru_r30_7
pr1_pru0_pru_r31_7
gpio3_21
I
I/O
I/O
O
mcasp0_aclkx
ehrpwm0A
spi1_sclk
I/O
I
mmc0_sdcd
pr1_pru0_pru_r30_0
pr1_pru0_pru_r31_0
gpio3_14
O
I
I/O
Copyright © 2011–2012, Texas Instruments Incorporated
Terminal Description
33
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AM3356, AM3354, AM3352
SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MCASP0_FSR
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
NA
C13
mcasp0_fsr
eQEP0B_in
mcasp0_axr3
mcasp1_fsx
EMU2
0
I/O
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I
I/O
I/O
I/O
O
pr1_pru0_pru_r30_5
pr1_pru0_pru_r31_5
gpio3_19
I
I/O
I/O
I
NA
D12
D13
M18
MCASP0_AXR0
MCASP0_AXR1
MDC
mcasp0_axr0
ehrpwm0_tripzone_input
spi1_d1
L
L
H
L
L
H
7
7
7
NA / VDDSHV6 Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
I/O
I
mmc2_sdcd
pr1_pru0_pru_r30_2
pr1_pru0_pru_r31_2
gpio3_16
O
I
I/O
I/O
I/O
I/O
I/O
O
NA
mcasp0_axr1
eQEP0_index
mcasp1_axr0
EMU3
NA / VDDSHV6 Yes
pr1_pru0_pru_r30_6
pr1_pru0_pru_r31_6
gpio3_20
I
I/O
O
R19
mdio_clk
VDDSHV5 /
VDDSHV5
Yes
timer5
I/O
O
uart5_txd
uart3_rtsn
O
mmc0_sdwp
mmc1_clk
I
I/O
I/O
I/O
I/O
I/O
O
mmc2_clk
gpio0_1
P17
M17
MDIO
mdio_data
H
H
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
timer6
uart5_rxd
uart3_ctsn
I
mmc0_sdcd
mmc1_cmd
mmc2_cmd
gpio0_0
I
I/O
I/O
I/O
34
Terminal Description
Copyright © 2011–2012, Texas Instruments Incorporated
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Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MII1_RX_DV
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
L19
K17
K19
M19
J17
J16
J15
L18
gmii1_rxdv
0
I
L
L
L
L
L
7
7
7
7
VDDSHV5 /
VDDSHV5
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
lcd_memory_clk
rgmii1_rctl
uart5_txd
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
I
O
mcasp1_aclkx
mmc2_dat0
mcasp0_aclkr
gpio3_4
I/O
I/O
I/O
I/O
O
MII1_TX_EN
MII1_RX_ER
MII1_RX_CLK
gmii1_txen
rmii1_txen
rgmii1_tctl
timer4
L
L
L
VDDSHV5 /
VDDSHV5
LVCMOS
LVCMOS
LVCMOS
O
O
I/O
I/O
I/O
I/O
I/O
I
mcasp1_axr0
eQEP0_index
mmc2_cmd
gpio3_3
gmii1_rxerr
rmii1_rxerr
spi1_d1
VDDSHV5 /
VDDSHV5
I
I/O
I/OD
I/O
O
I2C1_SCL
mcasp1_fsx
uart5_rtsn
uart2_txd
O
gpio3_2
I/O
I
gmii1_rxclk
uart2_txd
VDDSHV5 /
VDDSHV5
O
rgmii1_rclk
mmc0_dat6
mmc1_dat1
uart1_dsrn
mcasp0_fsx
gpio3_10
I
I/O
I/O
I
I/O
I/O
Copyright © 2011–2012, Texas Instruments Incorporated
Terminal Description
35
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AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MII1_TX_CLK
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
N19
J19
J18
P18
K18
H16
H17
M16
gmii1_txclk
uart2_rxd
0
I
L
L
L
L
L
7
7
7
7
VDDSHV5 /
VDDSHV5
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I
rgmii1_tclk
mmc0_dat7
mmc1_dat0
uart1_dcdn
mcasp0_aclkx
gpio3_9
O
I/O
I/O
I
I/O
I/O
I
MII1_COL
MII1_CRS
MII1_RXD0
gmii1_col
L
L
L
VDDSHV5 /
VDDSHV5
LVCMOS
LVCMOS
LVCMOS
rmii2_refclk
spi1_sclk
I/O
I/O
I
uart5_rxd
mcasp1_axr2
mmc2_dat3
mcasp0_axr2
gpio3_0
I/O
I/O
I/O
I/O
I
gmii1_crs
VDDSHV5 /
VDDSHV5
rmii1_crs_dv
spi1_d0
I
I/O
I/OD
I/O
I
I2C1_SDA
mcasp1_aclkx
uart5_ctsn
uart2_rxd
I
gpio3_1
I/O
I
gmii1_rxd0
rmii1_rxd0
rgmii1_rd0
VDDSHV5 /
VDDSHV5
I
I
mcasp1_ahclkx
mcasp1_ahclkr
mcasp1_aclkr
mcasp0_axr3
gpio2_21
I/O
I/O
I/O
I/O
I/O
36
Terminal Description
Copyright © 2011–2012, Texas Instruments Incorporated
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Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MII1_RXD1
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
P19
N16
N17
L18
L15
L16
L17
K17
gmii1_rxd1
rmii1_rxd1
rgmii1_rd1
mcasp1_axr3
mcasp1_fsr
eQEP0_strobe
mmc2_clk
gpio2_20
0
I
I
I
L
L
L
L
L
7
7
7
7
VDDSHV5 /
VDDSHV5
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I
MII1_RXD2
MII1_RXD3
MII1_TXD0
gmii1_rxd2
uart3_txd
L
L
L
VDDSHV5 /
VDDSHV5
LVCMOS
LVCMOS
LVCMOS
O
rgmii1_rd2
mmc0_dat4
mmc1_dat3
uart1_rin
I
I/O
I/O
I
mcasp0_axr1
gpio2_19
I/O
I/O
I
gmii1_rxd3
uart3_rxd
VDDSHV5 /
VDDSHV5
I
rgmii1_rd3
mmc0_dat5
mmc1_dat2
uart1_dtrn
mcasp0_axr0
gpio2_18
I
I/O
I/O
O
I/O
I/O
O
gmii1_txd0
rmii1_txd0
rgmii1_td0
mcasp1_axr2
mcasp1_aclkr
eQEP0B_in
mmc1_clk
gpio0_28
VDDSHV5 /
VDDSHV5
O
O
I/O
I/O
I
I/O
I/O
Copyright © 2011–2012, Texas Instruments Incorporated
Terminal Description
37
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Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MII1_TXD1
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
M18
N18
M17
G17
K16
K15
J18
G18
gmii1_txd1
rmii1_txd1
rgmii1_td1
mcasp1_fsr
mcasp1_axr1
eQEP0A_in
mmc1_cmd
gpio0_21
0
O
O
O
L
L
L
H
L
7
7
7
7
VDDSHV5 /
VDDSHV5
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I/O
I/O
I
I/O
I/O
O
MII1_TXD2
MII1_TXD3
MMC0_CMD
gmii1_txd2
dcan0_rx
L
L
H
VDDSHV5 /
VDDSHV5
LVCMOS
LVCMOS
LVCMOS
I
rgmii1_td2
uart4_txd
O
O
mcasp1_axr0
mmc2_dat2
I/O
I/O
I/O
I/O
O
mcasp0_ahclkx
gpio0_17
gmii1_txd3
dcan0_tx
VDDSHV5 /
VDDSHV5
O
rgmii1_td3
O
uart4_rxd
I
mcasp1_fsx
mmc2_dat1
mcasp0_fsr
gpio0_16
I/O
I/O
I/O
I/O
I/O
O
mmc0_cmd
gpmc_a25
VDDSHV4 /
VDDSHV4
uart3_rtsn
O
uart2_txd
O
dcan1_rx
I
pr1_pru0_pru_r30_13
pr1_pru0_pru_r31_13
gpio2_31
O
I
I/O
38
Terminal Description
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MMC0_CLK
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
G19
G18
H17
H18
G17
G16
G15
F18
mmc0_clk
gpmc_a24
uart3_ctsn
uart2_rxd
dcan1_tx
0
I/O
H
H
H
H
H
7
7
7
7
VDDSHV4 /
VDDSHV4
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
I
I
O
O
I
pr1_pru0_pru_r30_12
pr1_pru0_pru_r31_12
gpio2_30
I/O
I/O
O
O
O
I
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
mmc0_dat0
H
H
H
VDDSHV4 /
VDDSHV4
LVCMOS
LVCMOS
LVCMOS
gpmc_a23
uart5_rtsn
uart3_txd
uart1_rin
pr1_pru0_pru_r30_11
pr1_pru0_pru_r31_11
gpio2_29
O
I
I/O
I/O
O
I
mmc0_dat1
VDDSHV4 /
VDDSHV4
gpmc_a22
uart5_ctsn
uart3_rxd
I
uart1_dtrn
O
O
I
pr1_pru0_pru_r30_10
pr1_pru0_pru_r31_10
gpio2_28
I/O
I/O
O
O
I/O
I
mmc0_dat2
VDDSHV4 /
VDDSHV4
gpmc_a21
uart4_rtsn
timer6
uart1_dsrn
pr1_pru0_pru_r30_9
pr1_pru0_pru_r31_9
gpio2_27
O
I
I/O
Copyright © 2011–2012, Texas Instruments Incorporated
Terminal Description
39
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Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MMC0_DAT3
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
H19
F17
mmc0_dat3
gpmc_a20
uart4_ctsn
timer5
0
I/O
H
H
7
VDDSHV4 /
VDDSHV4
Yes
6
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
O
I
I/O
I
uart1_dcdn
pr1_pru0_pru_r30_8
pr1_pru0_pru_r31_8
gpio2_26
O
I
I/O
O
C7
C6
PMIC_POWER_EN
PWRONRSTn
PMIC_POWER_EN
H
Z
1
0
VDDS_RTC /
VDDS_RTC
NA
6
NA
LVCMOS
LVCMOS
Analog
E15
B6
B15
A3
porz
0
0
I
Z
0
VDDSHV6 /
VDDSHV6
Yes
NA
NA
NA
6
NA
RESERVED
testout
O
NA
L
NA
L
NA
7
VDDSHV6 /
VDDSHV6
NA
K18
H18
RMII1_REF_CLK
rmii1_refclk
0
1
2
3
4
5
6
7
0
I/O
I
VDDSHV5 /
VDDSHV5
Yes
PU/PD
LVCMOS
xdma_event_intr2
spi1_cs0
I/O
O
uart5_txd
mcasp1_axr3
mmc0_pow
I/O
O
mcasp1_ahclkx
gpio0_29
I/O
I/O
I
A7
B7
A6
A5
A18
B4
B5
A6
A4
A17
RTC_KALDO_ENn
RTC_PWRONRSTn
RTC_XTALIN
ENZ_KALDO_1P8V
Z
Z
Z
Z
Z
Z
Z
H
0
0
0
0
7
VDDS_RTC /
VDDS_RTC
NA
NA
NA
NA
NA (8)
6
NA
Analog
RTC_porz
OSC1_IN
0
0
0
I
VDDS_RTC /
VDDS_RTC
Yes
Yes
NA
NA
LVCMOS
LVCMOS
LVCMOS
LVCMOS
I
VDDS_RTC /
VDDS_RTC
NA (2)
NA
(18)
RTC_XTALOUT
SPI0_SCLK
OSC1_OUT
O
Z
Z
VDDS_RTC /
VDDS_RTC
spi0_sclk
0
1
2
3
4
5
6
7
I/O
I
VDDSHV6 /
VDDSHV6
Yes
PU/PD
uart2_rxd
I2C2_SDA
ehrpwm0A
pr1_uart0_cts_n
pr1_edio_sof
EMU2
I/OD
O
I
O
I/O
I/O
gpio0_2
40
Terminal Description
Copyright © 2011–2012, Texas Instruments Incorporated
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ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SPI0_CS0
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
A17
B16
B18
B17
A16
C15
B17
B16
spi0_cs0
0
I/O
Z
Z
Z
Z
H
7
7
7
7
VDDSHV6 /
VDDSHV6
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
mmc2_sdwp
I2C1_SCL
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
I
I/OD
I
ehrpwm0_synci
pr1_uart0_txd
pr1_edio_data_in1
pr1_edio_data_out1
gpio0_5
O
I
O
I/O
I/O
I
SPI0_CS1
SPI0_D0
SPI0_D1
spi0_cs1
H
H
H
VDDSHV6 /
VDDSHV6
LVCMOS
LVCMOS
LVCMOS
uart3_rxd
eCAP1_in_PWM1_out
mmc0_pow
I/O
O
xdma_event_intr2
mmc0_sdcd
EMU4
I
I
I/O
I/O
I/O
O
gpio0_6
spi0_d0
VDDSHV6 /
VDDSHV6
uart2_txd
I2C2_SCL
I/OD
O
ehrpwm0B
pr1_uart0_rts_n
pr1_edio_latch_in
EMU3
O
I
I/O
I/O
I/O
I
gpio0_3
spi0_d1
VDDSHV6 /
VDDSHV6
mmc1_sdwp
I2C1_SDA
I/OD
I
ehrpwm0_tripzone_input
pr1_uart0_rxd
pr1_edio_data_in0
pr1_edio_data_out0
gpio0_4
I
I
O
I/O
I
B14
B13
A14
C14
A12
B11
A11
C11
TCK
TDI
TCK
H
H
H
H
H
H
H
H
0
0
0
0
VDDSHV6 /
VDDSHV6
Yes
Yes
NA
NA
NA
4
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
TDI
0
0
0
I
VDDSHV6 /
VDDSHV6
TDO
TMS
TDO
TMS
O
I
VDDSHV6 /
VDDSHV6
VDDSHV6 /
VDDSHV6
Yes
NA
Copyright © 2011–2012, Texas Instruments Incorporated
Terminal Description
41
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
LVCMOS
[5]
STATE [6]
A13
F17
B10
E16
TRSTn
nTRST
0
I
L
Z
L
0
7
VDDSHV6 /
VDDSHV6
Yes
Yes
NA
PU/PD
UART0_TXD
UART0_CTSn
UART0_RXD
UART0_RTSn
uart0_txd
spi1_cs1
dcan0_rx
I2C2_SCL
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
H
H
H
H
VDDSHV6 /
VDDSHV6
4
4
4
4
PU/PD
LVCMOS
I/O
I
I/OD
I/O
O
eCAP1_in_PWM1_out
pr1_pru1_pru_r30_15
pr1_pru1_pru_r31_15
gpio1_11
I
I/O
I
F19
E19
F18
E18
E15
E17
uart0_ctsn
Z
Z
Z
7
7
7
VDDSHV6 /
VDDSHV6
Yes
Yes
Yes
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
uart4_rxd
I
dcan1_tx
O
I2C1_SDA
I/OD
I/O
I/O
O
spi1_d0
timer7
pr1_edc_sync0_out
gpio1_8
I/O
I
uart0_rxd
VDDSHV6 /
VDDSHV6
spi1_cs0
I/O
O
dcan0_tx
I2C2_SDA
I/OD
I/O
O
eCAP2_in_PWM2_out
pr1_pru1_pru_r30_14
pr1_pru1_pru_r31_14
gpio1_10
I
I/O
O
uart0_rtsn
VDDSHV6 /
VDDSHV6
uart4_txd
O
dcan1_rx
I
I2C1_SCL
I/OD
I/O
I/O
O
spi1_d1
spi1_cs0
pr1_edc_sync1_out
gpio1_9
I/O
42
Terminal Description
Copyright © 2011–2012, Texas Instruments Incorporated
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ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
UART1_TXD
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
C19
D18
D19
D15
D16
D17
uart1_txd
0
O
I
Z
Z
Z
H
7
7
7
VDDSHV6 /
VDDSHV6
Yes
Yes
Yes
4
4
4
PU/PD
PU/PD
PU/PD
LVCMOS
mmc2_sdwp
dcan1_rx
1
2
3
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
I
I2C1_SCL
pr1_uart0_txd
I/OD
O
pr1_pru0_pru_r31_16
gpio0_15
I
I/O
UART1_RXD
uart1_rxd
I
H
VDDSHV6 /
VDDSHV6
LVCMOS
mmc1_sdwp
dcan1_tx
I
O
I2C1_SDA
I/OD
I
pr1_uart0_rxd
pr1_pru1_pru_r31_16
gpio0_14
I
I/O
O
UART1_RTSn
uart1_rtsn
H
VDDSHV6 /
VDDSHV6
LVCMOS
timer5
I/O
I
dcan0_rx
I2C2_SCL
I/OD
I/O
O
spi1_cs1
pr1_uart0_rts_n
pr1_edc_latch1_in
gpio0_13
I
I/O
I
E17
D18
UART1_CTSn
uart1_ctsn
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
timer6
I/O
O
dcan0_tx
I2C2_SDA
I/OD
I/O
I
spi1_cs0
pr1_uart0_cts_n
pr1_edc_latch0_in
gpio0_12
I
I/O
A
T18
T19
U18
G16
M15
P15
N18
F16
USB0_CE
USB0_CE
Z
Z
Z
L
Z
0
0
0
0
VDDA*_USB0 / NA
NA
NA
NA
Analog
Analog
Analog
LVCMOS
VDDA*_USB0
(20)
USB0_VBUS
USB0_DM
USB0_VBUS
USB0_DM
0
0
A
A
Z
VDDA*_USB0 / NA
NA
VDDA*_USB0
(20)
(6)
(9)
(9)
Z
VDDA*_USB0 / Yes
8
4
NA
VDDA*_USB0
(20)
USB0_DRVVBUS
USB0_DRVVBUS
gpio0_18
0
7
O
0(PD)
VDDSHV6 /
VDDSHV6
Yes
PU/PD
I/O
Copyright © 2011–2012, Texas Instruments Incorporated
Terminal Description
43
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AM3356, AM3354, AM3352
SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
USB0_ID
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
V19
U19
NA
P16
N17
P18
P17
T18
R17
USB0_ID
0
A
A
A
A
A
A
O
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
VDDA*_USB0 / NA
NA
NA
Analog
VDDA*_USB0
(20)
(6)
(9)
(9)
USB0_DP
USB1_CE
USB1_ID
USB0_DP
USB1_CE
USB1_ID
0
0
0
0
0
Z
Z
Z
Z
Z
VDDA*_USB0 / Yes
8
NA
NA
NA
NA
NA
Analog
Analog
Analog
Analog
Analog
VDDA*_USB0
(20)
NA /
NA
NA
NA
NA
NA
NA
VDDA*_USB1
(21)
NA
NA /
VDDA*_USB1
(21)
NA
USB1_VBUS
USB1_DP
USB1_VBUS
USB1_DP
NA /
VDDA*_USB1
(21)
(7)
(10)
NA
NA /
Yes
8
(10)
VDDA*_USB1
(21)
NA
NA
F15
R18
USB1_DRVVBUS
USB1_DM
USB1_DRVVBUS
gpio3_13
0
7
0
L
Z
0(PD)
Z
0
0
NA / VDDSHV6 Yes
4
8
PU/PD
NA
LVCMOS
Analog
I/O
A
(7)
(10)
USB1_DM
NA /
VDDA*_USB1
Yes
(10)
(21)
R17
N16
R16
N15
R15
D8
VDDA1P8V_USB0
VDDA1P8V_USB1
VDDA3P3V_USB0
VDDA3P3V_USB1
VDDA_ADC
VDDA1P8V_USB0
VDDA1P8V_USB1
VDDA3P3V_USB0
VDDA3P3V_USB1
VDDA_ADC
NA
NA
NA
NA
NA
NA
PWR
PWR
PWR
PWR
PWR
PWR
NA
R18
NA
D7
D12, F16,
E6, E14, F9, VDDS
VDDS
M16, T6, T14 K13, N6, P9,
P14
R8, R9, R11, P7, P8
R12, R13
VDDSHV1
VDDSHV1
NA
PWR
NA
NA
P10, P11
P12, P13
H14, J14
VDDSHV2
VDDSHV3
VDDSHV4
VDDSHV2
VDDSHV3
VDDSHV4
NA
NA
NA
PWR
PWR
PWR
G15, H14,
H15
M14, M15,
N15
K14, L14
VDDSHV5
VDDSHV6
VDDSHV5
VDDSHV6
NA
NA
PWR
PWR
E11, E12,
E10, E11,
E13, F14, P6, E12, E13,
R7
F14, G14, N5,
P5, P6
G5, H5, H6,
K4, K5, M5,
M6, N5
E5, F5, G5,
H5, J5, K5, L5
VDDS_DDR
VDDS_OSC
VDDS_DDR
VDDS_OSC
NA
NA
PWR
PWR
U10
R11
44
Terminal Description
Copyright © 2011–2012, Texas Instruments Incorporated
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AM3356, AM3354, AM3352
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ZCE BALL
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
T8
R10
E7
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
VDDS_PLL_CORE_LCD
NA
PWR
PWR
PWR
PWR
PWR
PWR
PWR
C5
VDDS_PLL_DDR
VDDS_PLL_MPU
VDDS_RTC
NA
NA
NA
NA
NA
NA
H16
C6
H15
D7
VDDS_PLL_MPU
VDDS_RTC
C10
C12
E9
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDD_CORE
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDD_CORE
D10
F9, F11, G9, F6, F7, G6,
G11, H7, H8, G7, G10,
H12, H13, J7, H11, J12, K6,
J8, J12, J13, K8, K12, L6,
K15, K16, L7, L7, L8, L9,
L8, L12, L13, M11, M13,
M7, M8, M12, N8, N9, N12,
M13, N9,
N13
N11, P9, P11
NA
F10, F11,
F12, F13,
G13, H13,
J13
VDD_MPU
VDD_MPU (22)
NA
PWR
(23)
NA
R5
B9
A2
M5
A9
VDD_MPU_MON
VPP
VDD_MPU_MON
NA
NA
0
A
VPP
PWR
AP
VREFN
VREFN
Z
Z
Z
0
0
VDDA_ADC /
VDDA_ADC
NA
NA
NA
NA
NA
Analog
Analog
A9
B9
VREFP
VREFP
VSS
0
AP
Z
VDDA_ADC /
VDDA_ADC
NA
A1, A19, D10, A1, A18, F8, VSS
E7, E8, E9, G8, G9, G11,
NA
GND
E10, F6, F7, G12, H6, H7,
F8, F12, F13, H8, H9, H10,
G8, G12, H9, H12, J6, J7,
H10, H11, J5, J8, J9, J10,
J6, J9, J11,
J11, K7, K9,
J14, J15, K8, K10, K11,
K9, K11, K12, L10, L11, L12,
L5, L6, L9,
L13, M6, M7,
L11, L14, L15, M8, M9, M10,
M9, M10,
M11, N8,
M12, N7,
N10, N11, V1,
N12, P7, P8, V18
P12, P13,
P14, R10,
T10, W1, W19
D8
E8
VSSA_ADC
VSSA_USB
VSS_OSC
VSS_RTC
VSSA_ADC
NA
NA
NA
NA
0
GND
GND
A
P16
V11
NA
M14, N14
V11
VSSA_USB
VSS_OSC (24)
VSS_RTC (24)
nRESETIN_OUT
A5
A
A16
A10
WARMRSTn
I/OD
0
0(PU)
0
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
(4)
Copyright © 2011–2012, Texas Instruments Incorporated
Terminal Description
45
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AM3356, AM3354, AM3352
SPRS717D –OCTOBER 2011–REVISED MAY 2012
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
(12)
(11)
(5)
C15
A15
XDMA_EVENT_INTR0
xdma_event_intr0
0
I
Z
Z
Z
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
timer4
2
3
4
5
6
7
0
2
3
4
5
6
7
0
I/O
O
clkout1
spi1_cs1
I/O
I
pr1_pru1_pru_r31_16
EMU2
I/O
I/O
I
gpio0_19
B15
D14
XDMA_EVENT_INTR1
xdma_event_intr1
tclkin
L
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
I
clkout2
O
timer7
I/O
I
pr1_pru0_pru_r31_16
EMU3
I/O
I/O
I
gpio0_20
W11
W12
V10
U11
XTALIN
OSC0_IN
Z
0
0
VDDS_OSC /
VDDS_OSC
Yes
NA
NA
PD (1)
NA
LVCMOS
LVCMOS
(19)
XTALOUT
OSC0_OUT
0
O
VDDS_OSC /
VDDS_OSC
NA (8)
(1) A internal 15 kohm pull down is turned on when the oscillator is disabled. The oscillator is enabled by default after power is applied.
(2) An external pull-down resistor should be connected to this terminal to minmize leakage current when not using the oscillator.
(3) LCD_DATA[15:0] terminals are respectively SYSBOOT[15:0] inputs, latched on the rising edge of PWRONRSTn.
(4) Refer to the External Warm Reset section of the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual for more information related to the operation of this
terminal.
(5) Reset Release Mode = 7 if sysboot[5] is low. Mode = 3 if sysboot[5] is high.
(6) The internal USB PHY can be configured to multiplex the UART2_TX or UART2_RX signals to this terminal. For more details refer to USB GPIO Details section of the TRM.
(7) The internal USB PHY can be configured to multiplex the UART3_TX or UART3_RX signals to this terminal. For more details refer to USB GPIO Details section of the TRM.
(8) This output should only be used to source the recommended crystal circuit.
(9) This parameter only applies when this USB PHY terminal is operating in UART2 mode.
(10) This parameter only applies when this USB PHY terminal is operating in UART3 mode.
(11) This terminal has an internal pull-down that remains on after reset is released if sysboot[5] is low on the rising edge or PWRONRSTn. This terminal will initially be driven low after reset is
released if sysboot[5] is high on the rising edge or PWRONRSTn, then it begins to toggle at the same frequency of the XTALIN terminal.
(12) This terminal has an internal pull-down turned on while reset is asserted.
(13) This terminal is a analog input used to set the switching threshold of the DDR input buffers to (VDDS_DDR / 2).
(14) This terminal is a analog passive signal that connects to an external 49.9 ohm 1%, 20mW reference resistor which is used to calibrate the DDR input/output buffers.
(15) This terminal is analog input that may also be configured as an open-drain output.
(16) This terminal is analog input that may also be configured as an open-source or open-drain output.
46
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
(17) This terminal is analog input that may also be configured as an open-source output.
(18) This terminal is high-Z when the oscillator is diasabled. This terminal is driven high if RTC_XTALIN is less than VIL, driven low if RTC_XTALIN is greater than VIH, and driven to a
unknown value if RTC_XTALIN is between VIL and VIH when the oscillator is enabled. The oscillator is disabled by default after power is applied.
(19) This terminal is high-Z when the oscillator is diasabled. This terminal is driven high if XTALIN is less than VIL, driven low if XTALIN is greater than VIH, and driven to a unknown value if
XTALIN is between VIL and VIH when the oscillator is enabled. The oscillator is enabled by default after power is applied.
(20) This terminal requires two power supplies, VDDA3p3v_USB0 and VDDA1p8v_USB0. The "*" character in the power supply name is a wild card that represents "3p3v" and "1p8v".
(21) This terminal requires two power supplies, VDDA3p3v_USB1 and VDDA1p8v_USB1. The "*" character in the power supply name is a wild card that represents "3p3v" and "1p8v".
(22) This power rail is connected to VDD_CORE in the ZCE package.
(23) This terminal provides a Kelvin connection to VDD_MPU. It can be connected to the power supply feedback input to provide remote sensing which compensates for voltage drop in the
PCB power distribution network and package. When the Kelvin connection is not used it should be connected to the same power source as VDD_MPU.
(24) This terminal provides a Kelvin ground reference for the external crystal components. External crystal component grounds should only be connected to this terminal and should not be
connected to the PCB ground plane.
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2.3 Signal Description
The AM335x device contains many peripheral interfaces. In order to reduce package size and lower
overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex
up to eight signal functions. Although there are many combinations of pin multiplexing that are possible,
only a certain number of sets, called IO Sets, are valid due to timing limitations. These valid IO Sets were
carefully chosen to provide many possible application scenarios for the user.
Texas Instruments has developed a Windows-based application called Pin Mux Utility that helps a system
designer select the appropriate pin-multiplexing configuration for their AM335x-based product design. The
Pin Mux Utility provides a way to select valid IO Sets of specific peripheral interfaces to ensure the pin-
multiplexing configuration selected for a design only uses valid IO Sets supported by the AM335x device.
48
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
(1) SIGNAL NAME: The signal name
(2) DESCRIPTION: Description of the signal
(3) TYPE: Ball type for this specific function:
–
–
–
–
–
–
I = Input
O = Output
I/O = Input/Output
D = Open drain
DS = Differential
A = Analog
(4) BALL: Package ball location
Table 2-8. ADC Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
B8
ZCZ BALL [4]
B6
AIN0
Analog Input/Output
A
A
A
A
A
A
A
A
AIN1
Analog Input/Output
Analog Input/Output
Analog Input/Output
Analog Input/Output
Analog Input
A11
A8
C7
B7
A7
C8
B8
A8
C9
A9
B9
AIN2
AIN3
B11
C8
AIN4
AIN5
B12
A10
A12
B9
AIN6
Analog Input
AIN7
Analog Input
VREFN
VREFP
Analog Negative Reference Input
Analog Positive Reference Input
AP
AP
A9
Table 2-9. Debug Subsystem Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
A15
ZCZ BALL [4]
EMU0
EMU1
EMU2
EMU3
EMU4
nTRST
TCK
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
JTAG TEST RESET (ACTIVE LOW)
JTAG TEST CLOCK
I/O
I/O
I/O
I/O
I/O
I
C14
D14
B14
A18, C15
B15, B18
B16, U17
A13
A15, A17, C13
B17, D13, D14
A14, C15, T13
B10
I
B14
A12
TDI
JTAG TEST DATA INPUT
JTAG TEST DATA OUTPUT
JTAG TEST MODE SELECT
I
B13
B11
TDO
O
A14
A11
TMS
I
C14
C11
Table 2-10. LCD Controller Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
lcd_ac_bias_en
lcd_data0
LCD AC bias enable chip select
LCD data bus
O
W7
U1
U2
U5
V5
R6
R1
R2
U3
U4
V2
V3
V4
T5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
lcd_data1
LCD data bus
lcd_data10
lcd_data11
lcd_data12
lcd_data13
lcd_data14
lcd_data15
lcd_data16
LCD data bus
LCD data bus
LCD data bus
V6
LCD data bus
U6
W6
V7
LCD data bus
LCD data bus
LCD data bus
V17
U13
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Table 2-10. LCD Controller Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
lcd_data17
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
O
W17
V13
lcd_data18
lcd_data19
lcd_data2
lcd_data20
lcd_data21
lcd_data22
lcd_data23
lcd_data3
lcd_data4
lcd_data5
lcd_data6
lcd_data7
lcd_data8
lcd_data9
lcd_hsync
lcd_memory_clk
lcd_pclk
O
T13
U13
V1
R12
T12
R3
O
I/O
O
U12
T12
W16
V15
V2
U12
T11
T10
U10
R4
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
W2
W3
V3
T1
T2
T3
U3
T4
V4
U1
W4
T7
U2
LCD Horizontal Sync
LCD MCLK
R5
O
L19, V16
W5
U7
J17, V12
V5
LCD pixel clock
LCD Vertical Sync
O
lcd_vsync
O
U5
50
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
2.3.1 External Memory Interfaces
Table 2-11. External Memory Interfaces/DDR Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
F3
ZCZ BALL [4]
F3
ddr_a0
ddr_a1
ddr_a10
ddr_a11
ddr_a12
ddr_a13
ddr_a14
ddr_a15
ddr_a2
ddr_a3
ddr_a4
ddr_a5
ddr_a6
ddr_a7
ddr_a8
ddr_a9
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
O
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
J2
H1
F4
F2
E3
H3
H4
D3
E4
C3
C2
B1
D5
E2
D4
C1
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
E2
G4
F4
H1
H3
E3
D1
B3
E5
A2
B1
D2
C3
B2
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
ddr_ba0
ddr_ba1
ddr_ba2
ddr_casn
DDR SDRAM BANK ADDRESS OUTPUT
DDR SDRAM BANK ADDRESS OUTPUT
DDR SDRAM BANK ADDRESS OUTPUT
O
O
O
O
A3
E1
B4
F1
C4
E1
B3
F1
DDR SDRAM COLUMN ADDRESS STROBE
OUTPUT (ACTIVE LOW)
ddr_ck
DDR SDRAM CLOCK OUTPUT (Differential+)
DDR SDRAM CLOCK ENABLE OUTPUT
DDR SDRAM CHIP SELECT OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
O
C2
G3
H2
N4
P4
M3
M4
M2
M1
N2
N1
P2
P1
D2
G3
H2
M3
M4
K2
K3
K4
L3
ddr_cke
ddr_csn0
ddr_d0
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ddr_d1
ddr_d10
ddr_d11
ddr_d12
ddr_d13
ddr_d14
ddr_d15
ddr_d2
L4
M1
N1
N2
ddr_d3
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Terminal Description
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Table 2-11. External Memory Interfaces/DDR Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
ddr_d4
ddr_d5
ddr_d6
ddr_d7
ddr_d8
ddr_d9
ddr_dqm0
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
I/O
P3
N3
I/O
I/O
I/O
I/O
I/O
O
T1
T2
R3
K2
K1
N3
N4
P3
P4
J1
K1
M2
DDR WRITE ENABLE / DATA MASK FOR
DATA[7:0]
ddr_dqm1
ddr_dqs0
ddr_dqs1
DDR WRITE ENABLE / DATA MASK FOR
DATA[15:8]
O
K3
R1
L1
R2
L2
J2
P1
L1
P2
L2
DDR DATA STROBE FOR DATA[7:0]
(Differential+)
I/O
I/O
I/O
I/O
DDR DATA STROBE FOR DATA[15:8]
(Differential+)
ddr_dqsn0
ddr_dqsn1
DDR DATA STROBE FOR DATA[7:0]
(Differential-)
DDR DATA STROBE FOR DATA[15:8]
(Differential-)
ddr_nck
ddr_odt
ddr_rasn
DDR SDRAM CLOCK OUTPUT (Differential-)
ODT OUTPUT
O
O
O
C1
G1
F2
D1
G1
G4
DDR SDRAM ROW ADDRESS STROBE
OUTPUT (ACTIVE LOW)
ddr_resetn
ddr_vref
ddr_vtp
DDR3 RESET OUTPUT (ACTIVE LOW)
Voltage Reference Input
O
A
I
G2
H4
J1
G2
J4
VTP Compensation Resistor
J3
ddr_wen
DDR SDRAM WRITE ENABLE OUTPUT
(ACTIVE LOW)
O
A4
B2
Table 2-12. External Memory Interfaces/General Purpose Memory Controller Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
U1
ZCZ BALL [4]
gpmc_a0
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
R1, R13
R2, V14
T16, V5
R6, V17
U1
gpmc_a1
U2
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
gpmc_a2
W5
W7
V4
W4
U5
U2
U3
V5
U4
V6
R13, V2
V14, V3
U14, V4
T14, T5
R3, U14
F17, R14
F18, V15
G15, U15
G16, T15
G17, V16
U6
W6
V7
V1
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
H19
H18
H17
G18
G19
52
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-12. External Memory Interfaces/General Purpose Memory Controller Signals
Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
G17
ZCZ BALL [4]
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_a3
GPMC Address
O
G18, U16
T16
GPMC Address
O
NA
GPMC Address
O
NA
V17
GPMC Address
O
V2
R4, T14
R14, T1
T2, V15
T3, U15
T15, T4
U5, V16
R5, U16
U7
gpmc_a4
GPMC Address
O
W2
gpmc_a5
GPMC Address
O
W3
gpmc_a6
GPMC Address
O
V3
gpmc_a7
GPMC Address
O
U3
gpmc_a8
GPMC Address
O
U7
gpmc_a9
GPMC Address
O
T7
gpmc_ad0
gpmc_ad1
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_advn_ale
gpmc_be0n_cle
gpmc_be1n
gpmc_clk
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address Valid / Address Latch Enable
GPMC Byte Enable 0 / Command Latch Enable
GPMC Byte Enable 1
GPMC Clock
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
W10
V9
V7
T12
U12
U13
T13
W17
V17
V12
W13
V13
W14
U14
W15
V15
W16
V10
V8
T11
U12
T12
R12
V13
U13
R8
T8
U8
V8
R9
T9
U10
T10
R7
O
T6
O
U15, V18
V14, V16
W8
U18, V9
U9, V12
V6
I/O
O
gpmc_csn0
gpmc_csn1
gpmc_csn2
gpmc_csn3
gpmc_csn4
gpmc_csn5
gpmc_csn6
gpmc_dir
GPMC Chip Select
GPMC Chip Select
O
V14
U15
U17
R15
W18
V18
V18
W9
U9
GPMC Chip Select
O
V9
GPMC Chip Select
O
T13
GPMC Chip Select
O
T17
GPMC Chip Select
O
U17
GPMC Chip Select
O
U18
GPMC Data Direction
GPMC Output / Read Enable
GPMC Wait 0
O
U18
gpmc_oen_ren
gpmc_wait0
gpmc_wait1
gpmc_wen
gpmc_wpn
O
T7
I
R15
V16
U8
T17
GPMC Wait 1
I
V12
GPMC Write Enable
GPMC Write Protect
O
U6
O
W18
U17
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2.3.2 General Purpose IOs
Table 2-13. General Purpose IOs/GPIO0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
P17
ZCZ BALL [4]
gpio0_0
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
M17
gpio0_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R19
W6
M18
V4
gpio0_10
gpio0_11
gpio0_12
gpio0_13
gpio0_14
gpio0_15
gpio0_16
gpio0_17
gpio0_18
gpio0_19
gpio0_2
V7
T5
E17
D19
D18
C19
M17
N18
G16
C15
A18
B15
M18
V15
W16
T12
U12
L18
K18
B18
R15
W18
B17
A17
B16
E18
V6
D18
D17
D16
D15
J18
K15
F16
A15
A17
D14
K16
U10
T10
T11
U12
K17
H18
B17
T17
U17
B16
A16
C15
C18
V2
gpio0_20
gpio0_21
gpio0_22
gpio0_23
gpio0_26
gpio0_27
gpio0_28
gpio0_29
gpio0_3
gpio0_30
gpio0_31
gpio0_4
gpio0_5
gpio0_6
gpio0_7
gpio0_8
gpio0_9
U6
V3
Table 2-14. General Purpose IOs/GPIO1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
gpio1_0
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
W10
V9
U7
gpio1_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V7
gpio1_10
gpio1_11
gpio1_12
gpio1_13
gpio1_14
gpio1_15
gpio1_16
gpio1_17
gpio1_18
E19
F17
U13
T13
W17
V17
NA
E15
E16
T12
R12
V13
U13
R13
V14
U14
NA
NA
54
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-14. General Purpose IOs/GPIO1 Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
T14
gpio1_19
gpio1_2
gpio1_20
gpio1_21
gpio1_22
gpio1_23
gpio1_24
gpio1_25
gpio1_26
gpio1_27
gpio1_28
gpio1_29
gpio1_3
gpio1_30
gpio1_31
gpio1_4
gpio1_5
gpio1_6
gpio1_7
gpio1_8
gpio1_9
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
NA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V12
NA
R8
R14
V15
U15
T15
V16
U16
T16
V17
U18
V6
NA
NA
NA
NA
NA
NA
NA
V18
W8
W13
V14
U15
V13
W14
U14
W15
F19
F18
T8
U9
V9
U8
V8
R9
T9
E18
E17
Table 2-15. General Purpose IOs/GPIO2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
gpio2_0
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
U17
V16
W2
W3
V3
T13
V12
T1
gpio2_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
gpio2_10
gpio2_11
gpio2_12
gpio2_13
gpio2_14
gpio2_15
gpio2_16
gpio2_17
gpio2_18
gpio2_19
gpio2_2
T2
T3
U3
T4
V4
U1
W4
U5
U2
U3
V5
U4
N17
N16
V10
P19
P18
U7
L17
L16
R7
gpio2_20
gpio2_21
gpio2_22
gpio2_23
gpio2_24
gpio2_25
gpio2_26
gpio2_27
gpio2_28
L15
M16
U5
T7
R5
W5
W7
H19
H18
H17
V5
R6
F17
F18
G15
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Table 2-15. General Purpose IOs/GPIO2 Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
gpio2_29
gpio2_3
gpio2_30
gpio2_31
gpio2_4
gpio2_5
gpio2_6
gpio2_7
gpio2_8
gpio2_9
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
G18
G16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
W9
G19
G17
U8
T7
G17
G18
U6
T6
V8
U1
R1
R2
R3
R4
U2
V1
V2
Table 2-16. General Purpose IOs/GPIO3 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
gpio3_0
gpio3_1
gpio3_10
gpio3_13
gpio3_14
gpio3_15
gpio3_16
gpio3_17
gpio3_18
gpio3_19
gpio3_2
gpio3_20
gpio3_21
gpio3_3
gpio3_4
gpio3_5
gpio3_6
gpio3_7
gpio3_8
gpio3_9
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
J19
J18
M19
NA
H16
H17
L18
F15
A13
B13
D12
C12
B12
C13
J15
D13
A14
J16
J17
C17
C16
C14
B14
K18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NA
NA
NA
NA
NA
NA
K19
NA
NA
K17
L19
C18
B19
A15
D14
N19
56
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
2.3.3 Miscellaneous
Table 2-17. Miscellaneous/Miscellaneous Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
C15
ZCZ BALL [4]
A15
clkout1
Clock out1
Clock out2
O
clkout2
O
I
B15
A7
D14
B4
ENZ_KALDO_1P8V
Active low enable input for internal
CAP_VDD_RTC voltage regulator
EXT_WAKEUP
nNMI
EXT_WAKEUP input
I
B5
C5
External Interrupt to ARM Cortext A8 core
Chip Reset
I
C17
A16
W11
W12
A6
B18
A10
V10
U11
A6
nRESETIN_OUT
OSC0_IN
I/OD
High frequency oscillator input
High frequency oscillator output
I
OSC0_OUT
OSC1_IN
O
I
Low frequency (32.768 KHz) Real Time Clock
oscillator input
OSC1_OUT
Low frequency (32.768 KHz) Real Time Clock
oscillator output
O
A5
A4
PMIC_POWER_EN
porz
PMIC_POWER_EN output
Power on Reset
O
I
C7
C6
E15
B15
tclkin
Timer Clock In
I
B15
D14
xdma_event_intr0
xdma_event_intr1
xdma_event_intr2
External DMA Event or Interrupt 0
External DMA Event or Interrupt 1
External DMA Event or Interrupt 2
I
C15
A15
I
B15
D14
I
B16, E18, K18
C15, C18, H18
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2.3.3.1 eCAP
Table 2-18. eCAP/eCAP0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
eCAP0_in_PWM0_out
DESCRIPTION [2]
ZCE BALL [4]
E18
ZCZ BALL [4]
Enhanced Capture 0 input or Auxiliary PWM0
output
I/O
C18
Table 2-19. eCAP/eCAP1 Signals Description
TYPE
SIGNAL NAME [1]
eCAP1_in_PWM1_out
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
Enhanced Capture 1 input or Auxiliary PWM1
output
I/O
B16, B19, F17
C15, C16, E16
Table 2-20. eCAP/eCAP2 Signals Description
TYPE
SIGNAL NAME [1]
eCAP2_in_PWM2_out
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
Enhanced Capture 2 input or Auxiliary PWM2
output
I/O
C18, E19
C12, C17, E15
58
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
2.3.3.2 eHRPWM
Table 2-21. eHRPWM/eHRPWM0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
eHRPWM0 A output.
ZCE BALL [4]
A18
ZCZ BALL [4]
ehrpwm0A
O
A13, A17
B13, B17
A16, C12
ehrpwm0B
eHRPWM0 B output.
O
I
B18
A17
ehrpwm0_synci
Sync input to eHRPWM0 module from an
external pin
ehrpwm0_synco
Sync Output from eHRPWM0 module to an
external pin
O
I
U12, V2, W4
B17
R4, U12, U2, V14
B16, D12
ehrpwm0_tripzone_input
eHRPWM0 trip zone input
Table 2-22. eHRPWM/eHRPWM1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
eHRPWM1 A output.
ZCE BALL [4]
ZCZ BALL [4]
ehrpwm1A
O
O
I
U5
V5
V4
U14, U3
T14, U4
R13, U1
ehrpwm1B
eHRPWM1 B output.
ehrpwm1_tripzone_input
eHRPWM1 trip zone input
Table 2-23. eHRPWM/eHRPWM2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
eHRPWM2 A output.
ZCE BALL [4]
ZCZ BALL [4]
ehrpwm2A
O
O
I
U1, V15
U2, W16
T12, V1
R1, U10
R2, T10
R3, T11
ehrpwm2B
eHRPWM2 B output.
ehrpwm2_tripzone_input
eHRPWM2 trip zone input
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2.3.3.3 eQEP
Table 2-24. eQEP/eQEP0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
eQEP0A_in
DESCRIPTION [2]
eQEP0A quadrature input
ZCE BALL [4]
M18
ZCZ BALL [4]
I
I
B12, K16
C13, K17
D13, J16
A14, L15
eQEP0B_in
eQEP0B quadrature input
eQEP0 index.
L18
K17
P19
eQEP0_index
eQEP0_strobe
I/O
I/O
eQEP0 strobe.
Table 2-25. eQEP/eQEP1 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
eQEP1A_in
eQEP1A quadrature input
eQEP1B quadrature input
eQEP1 index.
I
V6
U6
W6
V7
R14, V2
V15, V3
U15, V4
T15, T5
eQEP1B_in
I
eQEP1_index
eQEP1_strobe
I/O
I/O
eQEP1 strobe.
Table 2-26. eQEP/eQEP2 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
eQEP2A_in
eQEP2A quadrature input
eQEP2B quadrature input
eQEP2 index.
I
U13, W2
T13, W3
V3, W17
U3, V17
T1, T12
R12, T2
T3, V13
T4, U13
eQEP2B_in
I
eQEP2_index
eQEP2_strobe
I/O
I/O
eQEP2 strobe.
60
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
2.3.3.4 Timer
Table 2-27. Timer/Timer4 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
timer4
timer5
timer6
timer7
Timer trigger event / PWM out
I/O
C15, C18, K17,
V10
A15, C17, J16,
R7
Table 2-28. Timer/Timer5 Signals Description
TYPE
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
Timer trigger event / PWM out
I/O
D19, H19, R19,
V8
D17, F17, M18,
T6
Table 2-29. Timer/Timer6 Signals Description
TYPE
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
Timer trigger event / PWM out
I/O
E17, H18, P17,
U8
D18, F18, M17,
U6
Table 2-30. Timer/Timer7 Signals Description
TYPE
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
Timer trigger event / PWM out
I/O
B15, B19, F19,
W9
C16, D14, E18,
T7
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2.3.4 PRU-ICSS
Table 2-31. PRU-ICSS/eCAP Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
pr1_ecap0_ecap_capin_apwm_o
Enhanced capture input or Auxiliary PWM out
I/O
E18, V17
C18, U13
Table 2-32. PRU-ICSS/ECAT Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_edc_latch0_in
pr1_edc_latch1_in
pr1_edc_sync0_out
pr1_edc_sync1_out
pr1_edio_data_in0
pr1_edio_data_in1
pr1_edio_data_in2
pr1_edio_data_in3
pr1_edio_data_in4
pr1_edio_data_in5
pr1_edio_data_in6
pr1_edio_data_in7
pr1_edio_data_out0
pr1_edio_data_out1
pr1_edio_data_out2
pr1_edio_data_out3
pr1_edio_data_out4
pr1_edio_data_out5
pr1_edio_data_out6
pr1_edio_data_out7
pr1_edio_latch_in
pr1_edio_sof
Data In
I
E17
D18
D17
E18
E17
B16
A16
U5
Data In
I
D19
F19
Data Out
Data Out
Data In
O
O
I
F18
B17
Data In
I
A17
Data In
I
U7
Data In
I
T7
R5
Data In
I
W5
V5
Data In
I
W7
R6
Data In
I
V14, V3
U15, U3
B17
T3, U9
T4, V9
B16
A16
U5
Data In
I
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Latch In
Start of Frame
O
O
O
O
O
O
O
O
I
A17
U7
T7
R5
W5
V5
W7
R6
V14, V3
U15, U3
B18
T3, U9
T4, V9
B17
A17
O
A18
Table 2-33. PRU-ICSS/MDIO Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_mdio_data
pr1_mdio_mdclk
MDIO Data
MDIO Clk
I/O
O
U17
V16
T13
V12
Table 2-34. PRU-ICSS/MII0 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_mii0_col
pr1_mii0_crs
pr1_mii0_rxd0
pr1_mii0_rxd1
pr1_mii0_rxd2
pr1_mii0_rxd3
pr1_mii0_rxdv
pr1_mii0_rxer
MII Collision Detect
I
I
I
I
I
I
I
I
W16
U17, W5
V5
T10
T13, V5
U4
MII Carrier Sense
MII Receive Data bit 0
MII Receive Data bit 1
MII Receive Data bit 2
MII Receive Data bit 3
MII Receive Data Valid
MII Receive Data Error
U5
U3
W4
U2
V4
U1
V7
T5
U6
V3
62
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Table 2-34. PRU-ICSS/MII0 Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
V2
pr1_mii0_rxlink
pr1_mii0_txd0
pr1_mii0_txd1
pr1_mii0_txd2
pr1_mii0_txd3
pr1_mii0_txen
pr1_mii_mr0_clk
pr1_mii_mt0_clk
MII Receive Link
I
V6
MII Transmit Data bit 0
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
MII Receive Clock
O
O
O
O
O
I
W17, W3
T13, W2
U13, V2
U12, V1
T12, U2
W6
T2, V13
R12, T1
R4, T12
R3, U12
R2, T11
V4
MII Transmit Clock
I
U1, V15
R1, U10
Table 2-35. PRU-ICSS/MII1 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_mii1_col
MII Collision Detect
MII Carrier Sense
I
R15
V16, W7
NA
T17
pr1_mii1_crs
I
R6, V12
V16
T15
pr1_mii1_rxd0
pr1_mii1_rxd1
pr1_mii1_rxd2
pr1_mii1_rxd3
pr1_mii1_rxdv
pr1_mii1_rxer
pr1_mii1_rxlink
pr1_mii1_txd0
pr1_mii1_txd1
pr1_mii1_txd2
pr1_mii1_txd3
pr1_mii1_txen
pr1_mii_mr1_clk
pr1_mii_mt1_clk
MII Receive Data bit 0
MII Receive Data bit 1
MII Receive Data bit 2
MII Receive Data bit 3
MII Receive Data Valid
MII Receive Data Error
MII Receive Link
I
I
NA
I
NA
U15
V15
T16
I
NA
I
NA
I
NA
V17
U18
R14
T14
I
V18
NA
MII Transmit Data bit 0
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
MII Receive Clock
O
O
O
O
O
I
NA
NA
U14
V14
U17
U16
R13
NA
W18
NA
MII Transmit Clock
I
NA
Table 2-36. PRU-ICSS/UART0 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_uart0_cts_n
pr1_uart0_rts_n
pr1_uart0_rxd
pr1_uart0_txd
UART Clear to Send
UART Request to Send
UART Receive Data
UART Transmit Data
I
A18, E17
B18, D19
B17, D18
A17, C19
A17, D18
B17, D17
B16, D16
A16, D15
O
I
O
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2.3.4.1 PRU0
Table 2-37. PRU0/General Purpose Inputs Signals Description
TYPE
[3]
SIGNAL NAME [1]
pr1_pru0_pru_r31_0
DESCRIPTION [2]
ZCE BALL [4]
NA
ZCZ BALL [4]
PRU0 Data In
PRU0 Data In
PRU0 Data In
PRU0 Data In
PRU0 Data In
PRU0 Data In
PRU0 Data In
PRU0 Data In
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
A13
pr1_pru0_pru_r31_1
pr1_pru0_pru_r31_10
pr1_pru0_pru_r31_11
pr1_pru0_pru_r31_12
pr1_pru0_pru_r31_13
pr1_pru0_pru_r31_14
pr1_pru0_pru_r31_15
pr1_pru0_pru_r31_16
pr1_pru0_pru_r31_2
pr1_pru0_pru_r31_3
pr1_pru0_pru_r31_4
pr1_pru0_pru_r31_5
pr1_pru0_pru_r31_6
pr1_pru0_pru_r31_7
pr1_pru0_pru_r31_8
pr1_pru0_pru_r31_9
NA
B13
H17
G18
G19
G17
W17
V17
B15, C19
NA
G15
G16
G17
G18
V13
U13
D14, D15
D12
C12
B12
PRU0 Data In Capture Enable
PRU0 Data In
PRU0 Data In
NA
PRU0 Data In
NA
PRU0 Data In
NA
C13
D13
A14
PRU0 Data In
NA
PRU0 Data In
NA
PRU0 Data In
H19
H18
F17
PRU0 Data In
F18
Table 2-38. PRU0/General Purpose Outputs Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
pr1_pru0_pru_r30_0
pr1_pru0_pru_r30_1
pr1_pru0_pru_r30_10
pr1_pru0_pru_r30_11
pr1_pru0_pru_r30_12
pr1_pru0_pru_r30_13
pr1_pru0_pru_r30_14
pr1_pru0_pru_r30_15
pr1_pru0_pru_r30_2
pr1_pru0_pru_r30_3
pr1_pru0_pru_r30_4
pr1_pru0_pru_r30_5
pr1_pru0_pru_r30_6
pr1_pru0_pru_r30_7
pr1_pru0_pru_r30_8
pr1_pru0_pru_r30_9
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
NA
A13
B13
G15
G16
G17
G18
T12
R12
D12
C12
B12
C13
D13
A14
F17
F18
NA
H17
G18
G19
G17
U13
T13
NA
NA
NA
NA
NA
NA
H19
H18
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
2.3.4.2 PRU1
Table 2-39. PRU1/General Purpose Inputs Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
U1
ZCZ BALL [4]
R1
pr1_pru1_pru_r31_0
pr1_pru1_pru_r31_1
pr1_pru1_pru_r31_10
pr1_pru1_pru_r31_11
pr1_pru1_pru_r31_12
pr1_pru1_pru_r31_13
pr1_pru1_pru_r31_14
pr1_pru1_pru_r31_15
pr1_pru1_pru_r31_16
pr1_pru1_pru_r31_2
pr1_pru1_pru_r31_3
pr1_pru1_pru_r31_4
pr1_pru1_pru_r31_5
pr1_pru1_pru_r31_6
pr1_pru1_pru_r31_7
pr1_pru1_pru_r31_8
pr1_pru1_pru_r31_9
PRU1 Data In
PRU1 Data In
PRU1 Data In
PRU1 Data In
PRU1 Data In
PRU1 Data In
PRU1 Data In
PRU1 Data In
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
U2
R2
W5
W7
V14
U15
E19
F17
C15, D18
V1
V5
R6
U9
V9
E15
E16
A15, D16
R3
PRU1 Data In Capture Enable
PRU1 Data In
PRU1 Data In
V2
R4
PRU1 Data In
W2
W3
V3
T1
PRU1 Data In
T2
PRU1 Data In
T3
PRU1 Data In
U3
T4
PRU1 Data In
U7
U5
PRU1 Data In
T7
R5
Table 2-40. PRU1/General Purpose Outputs Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
pr1_pru1_pru_r30_0
pr1_pru1_pru_r30_1
pr1_pru1_pru_r30_10
pr1_pru1_pru_r30_11
pr1_pru1_pru_r30_12
pr1_pru1_pru_r30_13
pr1_pru1_pru_r30_14
pr1_pru1_pru_r30_15
pr1_pru1_pru_r30_2
pr1_pru1_pru_r30_3
pr1_pru1_pru_r30_4
pr1_pru1_pru_r30_5
pr1_pru1_pru_r30_6
pr1_pru1_pru_r30_7
pr1_pru1_pru_r30_8
pr1_pru1_pru_r30_9
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
U1
R1
R2
V5
R6
U9
V9
E15
E16
R3
R4
T1
U2
W5
W7
V14
U15
E19
F17
V1
V2
W2
W3
V3
T2
T3
U3
T4
U7
U5
R5
T7
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2.3.5 Removable Media Interfaces
Table 2-41. Removable Media Interfaces/MMC0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
mmc0_clk
DESCRIPTION [2]
MMC/SD/SDIO Clock
ZCE BALL [4]
G19
ZCZ BALL [4]
I/O
G17
mmc0_cmd
mmc0_dat0
mmc0_dat1
mmc0_dat2
mmc0_dat3
mmc0_dat4
mmc0_dat5
mmc0_dat6
mmc0_dat7
mmc0_pow
mmc0_sdcd
mmc0_sdwp
MMC/SD/SDIO Command
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD Power Switch Control
SD Card Detect
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
G17
G18
G18
G16
H17
G15
H18
F18
H19
F17
N16
L16
N17
L17
M19
L18
N19
K18
B16, K18
B16, P17
E18, R19
C15, H18
A13, C15, M17
B12, C18, M18
I
SD Write Protect
I
Table 2-42. Removable Media Interfaces/MMC1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
MMC/SD/SDIO Clock
ZCE BALL [4]
ZCZ BALL [4]
mmc1_clk
I/O
L18, R19, V14
M18, P17, U15
N19, V15, W10
M19, V9, W16
N17, T12, V12
N16, U12, W13
U13, V13
K17, M18, U9
K16, M17, V9
K18, U10, U7
L18, T10, V7
L17, R8, T11
L16, T8, U12
T12, U8
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_dat4
mmc1_dat5
mmc1_dat6
mmc1_dat7
mmc1_sdcd
mmc1_sdwp
MMC/SD/SDIO Command
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
SD Card Detect
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
T13, W14
R12, V8
U14, W17
R9, V13
V17, W15
T9, U13
R15
B13, T17
SD Write Protect
I
B17, D18
B16, D16
Table 2-43. Removable Media Interfaces/MMC2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
MMC/SD/SDIO Clock
ZCE BALL [4]
ZCZ BALL [4]
mmc2_clk
I/O
P19, R19, V16
K17, P17, U17
L19, U13
M17, T13
N18, W17
J19, V17, V18
V15
L15, M18, V12
J16, M17, T13
J17, T12, V14
J18, R12, U14
K15, T14, V13
H16, U13, U18
U10, U15
mmc2_cmd
mmc2_dat0
mmc2_dat1
mmc2_dat2
mmc2_dat3
mmc2_dat4
mmc2_dat5
mmc2_dat6
mmc2_dat7
mmc2_sdcd
mmc2_sdwp
MMC/SD/SDIO Command
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
SD Card Detect
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
W16
T10, T15
T12
T11, V16
U12
U12, U16
W18
D12, U17
SD Write Protect
I
A17, C19
A16, D15
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
2.3.6 Serial Communication Interfaces
2.3.6.1 CAN
Table 2-44. CAN/DCAN0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
dcan0_rx
dcan0_tx
DCAN0 Receive Data
DCAN0 Transmit Data
I
D19, F17, N18
E17, E19, M17
D17, E16, K15
D18, E15, J18
O
Table 2-45. CAN/DCAN1 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
dcan1_rx
dcan1_tx
DCAN1 Receive Data
DCAN1 Transmit Data
I
C19, F18, G17
D18, F19, G19
D15, E17, G18
D16, E18, G17
O
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2.3.6.2 GEMAC_CPSW
Table 2-46. GEMAC_CPSW/MDIO Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
mdio_clk
MDIO Clk
O
R19
P17
M18
M17
mdio_data
MDIO Data
I/O
Table 2-47. GEMAC_CPSW/MII1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
gmii1_col
gmii1_crs
MII Colision
I
J19
H16
H17
L18
M16
L15
L16
L17
J17
J15
K18
K17
K16
K15
J18
J16
MII Carrier Sense
I
J18
gmii1_rxclk
gmii1_rxd0
gmii1_rxd1
gmii1_rxd2
gmii1_rxd3
gmii1_rxdv
gmii1_rxer
gmii1_txclk
gmii1_txd0
gmii1_txd1
gmii1_txd2
gmii1_txd3
gmii1_txen
MII Receive Clock
I
M19
P18
P19
N16
N17
L19
K19
N19
L18
M18
N18
M17
K17
MII Receive Data bit 0
MII Receive Data bit 1
MII Receive Data bit 2
MII Receive Data bit 3
MII Receive Data Valid
MII Receive Data Error
MII Transmit Clock
I
I
I
I
I
I
I
MII Transmit Data bit 0
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
O
O
O
O
O
Table 2-48. GEMAC_CPSW/MII2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
gmii2_col
MII Colision
I
V18
R15
NA
NA
NA
NA
NA
NA
W18
NA
NA
NA
NA
NA
NA
U18
T17
T15
V17
T16
U16
V16
V14
U17
U15
V15
R14
T14
U14
R13
gmii2_crs
MII Carrier Sense
I
gmii2_rxclk
gmii2_rxd0
gmii2_rxd1
gmii2_rxd2
gmii2_rxd3
gmii2_rxdv
gmii2_rxer
gmii2_txclk
gmii2_txd0
gmii2_txd1
gmii2_txd2
gmii2_txd3
gmii2_txen
MII Receive Clock
I
MII Receive Data bit 0
MII Receive Data bit 1
MII Receive Data bit 2
MII Receive Data bit 3
MII Receive Data Valid
MII Receive Data Error
MII Transmit Clock
I
I
I
I
I
I
I
MII Transmit Data bit 0
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
O
O
O
O
O
Table 2-49. GEMAC_CPSW/RGMII1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
rgmii1_rclk
68 Terminal Description
DESCRIPTION [2]
RGMII Receive Clock
ZCE BALL [4]
M19
ZCZ BALL [4]
L18
I
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-49. GEMAC_CPSW/RGMII1 Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
J17
rgmii1_rctl
rgmii1_rd0
rgmii1_rd1
rgmii1_rd2
rgmii1_rd3
rgmii1_tclk
rgmii1_tctl
rgmii1_td0
rgmii1_td1
rgmii1_td2
rgmii1_td3
RGMII Receive Control
I
I
I
I
I
L19
RGMII Receive Data bit 0
RGMII Receive Data bit 1
RGMII Receive Data bit 2
RGMII Receive Data bit 3
RGMII Transmit Clock
P18
P19
N16
N17
N19
K17
L18
M18
N18
M17
M16
L15
L16
L17
K18
J16
K17
K16
K15
J18
O
O
O
O
O
O
RGMII Transmit Control
RGMII Transmit Data bit 0
RGMII Transmit Data bit 1
RGMII Transmit Data bit 2
RGMII Transmit Data bit 3
Table 2-50. GEMAC_CPSW/RGMII2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
RGMII Receive Clock
ZCE BALL [4]
ZCZ BALL [4]
rgmii2_rclk
rgmii2_rctl
rgmii2_rd0
rgmii2_rd1
rgmii2_rd2
rgmii2_rd3
rgmii2_tclk
rgmii2_tctl
rgmii2_td0
rgmii2_td1
rgmii2_td2
rgmii2_td3
I
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
T15
V14
V17
T16
U16
V16
U15
R13
V15
R14
T14
U14
RGMII Receive Control
RGMII Receive Data bit 0
RGMII Receive Data bit 1
RGMII Receive Data bit 2
RGMII Receive Data bit 3
RGMII Transmit Clock
I
I
I
I
I
O
O
O
O
O
O
RGMII Transmit Control
RGMII Transmit Data bit 0
RGMII Transmit Data bit 1
RGMII Transmit Data bit 2
RGMII Transmit Data bit 3
Table 2-51. GEMAC_CPSW/RMII1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
rmii1_crs_dv
rmii1_refclk
rmii1_rxd0
rmii1_rxd1
rmii1_rxer
rmii1_txd0
rmii1_txd1
rmii1_txen
RMII Carrier Sense / Data Valid
RMII Reference Clock
I
J18
K18
P18
P19
K19
L18
M18
K17
H17
H18
M16
L15
J15
K17
K16
J16
I/O
I
RMII Receive Data bit 0
RMII Receive Data bit 1
RMII Receive Data Error
RMII Transmit Data bit 0
RMII Transmit Data bit 1
RMII Transmit Enable
I
I
O
O
O
Table 2-52. GEMAC_CPSW/RMII2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
rmii2_crs_dv
rmii2_refclk
rmii2_rxd0
rmii2_rxd1
RMII Carrier Sense / Data Valid
RMII Reference Clock
I
R15
J19
NA
T17
H16
V17
T16
I/O
RMII Receive Data bit 0
RMII Receive Data bit 1
I
I
NA
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Table 2-52. GEMAC_CPSW/RMII2 Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
rmii2_rxer
rmii2_txd0
rmii2_txd1
rmii2_txen
RMII Receive Data Error
I
W18
U17
RMII Transmit Data bit 0
RMII Transmit Data bit 1
RMII Transmit Enable
O
O
O
NA
NA
NA
V15
R14
R13
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
2.3.6.3 I2C
Table 2-53. I2C/I2C0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
I2C0_SCL
I2C0_SDA
I2C0 Clock
I2C0 Data
I/OD
I/OD
B19
C18
C16
C17
Table 2-54. I2C/I2C1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
I2C1_SCL
I2C1_SDA
I2C1 Clock
I2C1 Data
I/OD
A17, C19, F18,
K19
A16, D15, E17,
J15
I/OD
B17, D18, F19,
J18
B16, D16, E18,
H17
Table 2-55. I2C/I2C2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
I2C2_SCL
I2C2_SDA
I2C2 Clock
I2C2 Data
I/OD
I/OD
B18, D19, F17
A18, E17, E19
B17, D17, E16
A17, D18, E15
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2.3.6.4 McASP
Table 2-56. McASP/MCASP0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
mcasp0_aclkr
DESCRIPTION [2]
McASP0 Receive Bit Clock
ZCE BALL [4]
ZCZ BALL [4]
I/O
L19, V18, V6
B12, J17, U18,
V2
mcasp0_aclkx
McASP0 Transmit Bit Clock
I/O
N19, V4
A13, K18, U1,
V16
mcasp0_ahclkr
mcasp0_ahclkx
mcasp0_axr0
McASP0 Receive Master Clock
McASP0 Transmit Master Clock
McASP0 Serial Data (IN/OUT)
I/O
I/O
I/O
V5
C12, U4
N18, V7
N17, U5
A14, K15, T5
D12, L17, T16,
U3
mcasp0_axr1
mcasp0_axr2
mcasp0_axr3
mcasp0_fsr
McASP0 Serial Data (IN/OUT)
McASP0 Serial Data (IN/OUT)
McASP0 Serial Data (IN/OUT)
McASP0 Receive Frame Sync
McASP0 Transmit Frame Sync
I/O
I/O
I/O
I/O
I/O
N16, W6
D13, L16, V17,
V4
J19, V5, V6
P18, U6, V7
M17, U6, V16
M19, W4
B12, C12, H16,
U4, V2
A14, C13, M16,
T5, V3
C13, J18, V12,
V3
mcasp0_fsx
B13, L18, U16,
U2
Table 2-57. McASP/MCASP1 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
mcasp1_aclkr
mcasp1_aclkx
mcasp1_ahclkr
mcasp1_ahclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr2
mcasp1_axr3
mcasp1_fsr
McASP1 Receive Bit Clock
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L18, P18
J18, L19
P18
K17, M16
B12, H17, J17
M16
McASP1 Transmit Bit Clock
McASP1 Receive Master Clock
McASP1 Transmit Master Clock
McASP1 Serial Data (IN/OUT)
McASP1 Serial Data (IN/OUT)
McASP1 Serial Data (IN/OUT)
McASP1 Serial Data (IN/OUT)
McASP1 Receive Frame Sync
McASP1 Transmit Frame Sync
K18, P18
K17, N18
M18
H18, M16
D13, J16, K15
A14, K16
J19, L18
K18, P19
M18, P19
K19, M17
H16, K17
H18, L15
K16, L15
mcasp1_fsx
C13, J15, J18
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
2.3.6.5 SPI
Table 2-58. SPI/SPI0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
A17
ZCZ BALL [4]
A16
spi0_cs0
spi0_cs1
spi0_d0
spi0_d1
spi0_sclk
SPI Chip Select
SPI Chip Select
SPI Data
I/O
I/O
I/O
I/O
I/O
B16
B18
B17
A18
C15
B17
B16
A17
SPI Data
SPI Clock
Table 2-59. SPI/SPI1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
spi1_cs0
spi1_cs1
SPI Chip Select
SPI Chip Select
I/O
E17, E19, F18,
K18
C12, D18, E15,
E17, H18
I/O
C15, D19, E18,
F17
A15, C18, D17,
E16
spi1_d0
spi1_d1
spi1_sclk
SPI Data
SPI Data
SPI Clock
I/O
I/O
I/O
F19, J18
F18, K19
E18, J19
B13, E18, H17
D12, E17, J15
A13, C18, H16
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
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2.3.6.6 UART
Table 2-60. UART/UART0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
UART Clear to Send
ZCE BALL [4]
F19
ZCZ BALL [4]
uart0_ctsn
uart0_rtsn
uart0_rxd
uart0_txd
I
E18
UART Request to Send
UART Receive Data
UART Transmit Data
O
I
F18
E19
F17
E17
E15
E16
O
Table 2-61. UART/UART1 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
uart1_ctsn
UART Clear to Send
I
E17
D18
uart1_dcdn
uart1_dsrn
uart1_dtrn
uart1_rin
UART Data Carrier Detect
UART Data Set Ready
UART Data Terminal Ready
UART Ring Indicator
I
H19, N19
H18, M19
H17, N17
G18, N16
D19
F17, K18
F18, L18
G15, L17
G16, L16
D17
I
O
I
uart1_rtsn
uart1_rxd
uart1_txd
UART Request to Send
UART Receive Data
O
I
D18
D16
UART Transmit Data
O
C19
D15
Table 2-62. UART/UART2 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
uart2_ctsn
uart2_rtsn
uart2_rxd
UART Clear to Send
UART Request to Send
UART Receive Data
I
C18, V4
B19, W4
C17, U1
C16, U2
O
I
A18, G19, J18,
N19
A17, G17, H17,
K18
uart2_txd
UART Transmit Data
O
B18, G17, K19,
M19
B17, G18, J15,
L18
Table 2-63. UART/UART3 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
uart3_ctsn
uart3_rtsn
uart3_rxd
uart3_txd
UART Clear to Send
UART Request to Send
UART Receive Data
UART Transmit Data
I
G19, P17, U5
G17, R19, V5
B16, H17, N17
E18, G18, N16
G17, M17, U3
G18, M18, U4
C15, G15, L17
C18, G16, L16
O
I
O
Table 2-64. UART/UART4 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
uart4_ctsn
uart4_rtsn
uart4_rxd
uart4_txd
UART Clear to Send
UART Request to Send
UART Receive Data
UART Transmit Data
I
H19, V6
F17, V2
O
I
H18, U6
F18, V3
F19, M17, R15
F18, N18, W18
E18, J18, T17
E17, K15, U17
O
74
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 2-65. UART/UART5 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
UART Clear to Send
ZCE BALL [4]
ZCZ BALL [4]
uart5_ctsn
uart5_rtsn
uart5_rxd
I
H17, J18, W6
G18, K19, V7
G15, H17, V4
G16, J15, T5
UART Request to Send
UART Receive Data
O
O
J19, P17, W4,
W6
H16, M17, U2, V4
uart5_txd
UART Transmit Data
O
K18, L19, R19,
V4
H18, J17, M18,
U1
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2.3.6.7 USB
Table 2-66. USB/USB0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
T18
ZCZ BALL [4]
USB0_CE
USB0_DM
USB0_DP
USB0 Active high Charger Enable output
USB0 Data minus
A
M15
A
A
O
A
A
U18
U19
G16
V19
T19
N18
N17
F16
P16
P15
USB0 Data plus
USB0_DRVVBUS
USB0_ID
USB0 Active high VBUS control output
USB0 OTG ID (Micro-A or Micro-B Plug)
USB0 VBUS
USB0_VBUS
Table 2-67. USB/USB1 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
USB1_CE
USB1 Active high Charger Enable output
USB1 Data minus
A
A
A
O
A
A
NA
NA
NA
NA
NA
NA
P18
R18
R17
F15
P17
T18
USB1_DM
USB1_DP
USB1 Data plus
USB1_DRVVBUS
USB1_ID
USB1 Active high VBUS control output
USB1 OTG ID (Micro-A or Micro-B Plug)
USB1 VBUS
USB1_VBUS
76
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
3 Device Operating Conditions
3.1 Absolute Maximum Ratings
Table 3-1. Absolute Maximum Ratings Over Junction Temperature Range (Unless Otherwise Noted)(1)(2)
PARAMETER
MIN
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.3
MAX UNIT
VDD_MPU(3)
Supply voltage for the MPU core domain
Supply voltage range for the core domain
Supply voltage range for the RTC core domain
Supply voltage range for the FUSE ROM domain
Supply voltage range for the RTC domain
Supply voltage range for the System oscillator
Supply voltage range for the Core SRAM LDOs
Supply voltage range for the MPU SRAM LDOs
Supply voltage range for the DPLL DDR
1.5
1.5
1.5
2.2
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
3.8
3.8
3.8
3.8
3.8
3.8
4
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD_CORE
CAP_VDD_RTC(4)
VPP(5)
VDDS_RTC
VDDS_OSC
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDDS_PLL_DDR
VDDS_PLL_CORE_LCD
VDDS_PLL_MPU
VDDS_DDR
Supply voltage range for the DPLL Core and LCD
Supply voltage range for the DPLL MPU
Supply voltage range for the DDR IO domain
Supply voltage range for all dual-voltage IO domains
Supply voltage range for USBPHY
VDDS
VDDA1P8V_USB0
VDDA1P8V_USB1(6)
VDDA_ADC
Supply voltage range for USBPHY
Supply voltage range for ADC
VDDSHV1
VDDSHV2(6)
VDDSHV3(6)
Supply voltage range for the dual-voltage IO domain
Supply voltage range for the dual-voltage IO domain
Supply voltage range for the dual-voltage IO domain
Supply voltage range for the dual-voltage IO domain
Supply voltage range for the dual-voltage IO domain
Supply voltage range for the dual-voltage IO domain
Supply voltage range for USBPHY
VDDSHV4
VDDSHV5
VDDSHV6
VDDA3P3V_USB0
VDDA3P3V_USB1(6)
USB0_VBUS
Supply voltage range for USBPHY
4
Supply voltage range for USB VBUS comparator input
Supply voltage range for USB VBUS comparator input
5.25
5.25
1.1
USB1_VBUS(6)
DDR_VREF
Supply voltage range for the DDR SSTL/HSTL reference
voltage
Steady State Max. Voltage
at all IO pins
-0.5V to IO supply voltage + 0.3 V
USB0_ID
USB1_ID(6)
Steady state maximum voltage range for the USB ID input
Steady state maximum voltage range for the USB ID input
-0.5
-0.5
2.1
2.1
V
V
Transient Overshoot /
Undershoot specification at
IO terminal
25% of corresponding IO supply
voltage for up to 30% of signal period
-55 155
±2000
Storage temperature range,
°C
V
(7)
Tstg
ESD-HBM (Human Body Model)(8)
ESD-CDM (Charged-Device Model)(9)
ESD-CDM (Charged-Device Model) Corner Terminals
Class I (25°C)
Electrostatic Discharge
(ESD) Performance
±500
±750
40
25
mA
mA
Latch-up Performance(10)
Class II (105°C)
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Device Operating Conditions
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(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to their associated VSS or VSSA_x.
(3) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE on the ZCE package.
(4) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
from an external power supply.
(5) During functional operation, this pin is a no connect.
(6) Not availabe on the ZCE package.
(7) For tape and reel the storage temperature range is [-10°C; +50°C] with a maximum relative humidity of 70%. It is recommended
returning to ambient room temperature before usage.
(8) Based on JEDEC JESD22-A114E [Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)].
(9) Based on JEDEC JESD22-C101C (Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds
of Microelectronic Components).
(10) Based on JEDEC JESD78D [IC Latch-Up Test].
78
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 3-2 summarizes the power consumption at the AM335x power terminals.
Table 3-2. Maximum Current Ratings at AM335x Power Terminals(1)
PARAMETER
MAX UNIT
SUPPLY NAME
VDD_CORE(2)
DESCRIPTION
Maximum current rating for the core domain; OPP100
Maximum current rating for the core domain; OPP50
Maximum current rating for the MPU domain; Turbo
Maximum current rating for the MPU domain; OPP120
Maximum current rating for the MPU domain; OPP100
Maximum current rating for the MPU domain; OPP100(3)
Maximum current rating for the MPU domain; OPP50
Maximum current rating for RTC domain input/LDO output
Maximum current rating for the RTC domain
400
250
720
600
500
300
300
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD_MPU(2)
CAP_VDD_RTC(4)
VDDS_RTC
5
VDDS_DDR
Maximum current rating for DDR IO domain
200
50
VDDS
Maximum current rating for all dual-voltage IO domains
Maximum current rating for core SRAM LDOs
Maximum current rating for MPU SRAM LDOs
Maximum current rating for the DPLL DDR
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDDS_PLL_DDR
VDDS_PLL_CORE_LCD
VDDS_PLL_MPU
VDDS_OSC
10
10
10
Maximum current rating for the DPLL Core and LCD
Maximum current rating for the DPLL MPU
20
10
Maximum current rating for the system oscillator IOs
Maximum current rating for USBPHY 1.8 V
5
VDDA1P8V_USB0
VDDA1P8V_USB1(5)
VDDA3P3V_USB0
VDDA3P3V_USB1(5)
VDDA_ADC
VDDSHV1(6)
VDDSHV2(5)
25
Maximum current rating for USBPHY 1.8 V
25
Maximum current rating for USBPHY 3.3 V
40
Maximum current rating for USBPHY 3.3 V
40
Maximum current rating for ADC
10
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
50
50
VDDSHV3(5)
50
VDDSHV4
50
VDDSHV5
50
VDDSHV6
100
(1) Current ratings specified in this table are worst-case estimates. Actual application power supply estimates could be lower. For more
information, see the AM335x Power Consumption Summary application report (literature number SPRABN5).
(2) VDD_MPU is merged with VDD_CORE and is not available separately on the ZCE package. The maximum current rating for
VDD_CORE on the ZCE package is the sum of VDD_CORE and VDD_MPU shown in this table.
(3) Applies to all orderable AM335x devices with a 275-MHz speed grade.
(4) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
from an external power supply.
(5) Not available on the ZCE package.
(6) VDDSHV1 and VDDSHV2 are merged in the ZCE package. The maximum current rating for VDDSHV1 on the ZCE package is the sum
of VDDSHV1 and VDDSHV2 shown in this table.
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Device Operating Conditions
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3.2 Recommended Operating Conditions
The device is used under the recommended operating conditions described in Table 3-4.
Table 3-3. Reliability Data
COMMERCIAL
INDUSTRIAL
EXTENDED
OPERATING
CONDITION
VDD_MPU(1)(2) VDD_CORE(2)
JUNCTION
LIFETIME
(POH)(3)
JUNCTION
LIFETIME
(POH)(3)
JUNCTION
TEMP (Tj)
LIFETIME
(POH)(3)
TEMP (Tj)
TEMP (Tj)
Turbo
OPP120
OPP100
OPP50
1.26 V ±4%
1.2 V ±4%
1.1 V ±4%
0.95 V ±4%
1.1 V ±4%
1.1 V ±4%
1.1 V ±4%
0.95 V ±4%
0°C to 90°C
100K
100K
100K
100K
-40°C to 90°C
100K
100K
100K
100K
-40°C to
105°C
80K
0°C to 90°C
0°C to 90°C
0°C to 90°C
-40°C to 90°C
-40°C to 90°C
-40°C to 90°C
-40°C to
105°C
100K
100K
100K
-40°C to
105°C
-40°C to
105°C
(1) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE on the ZCE package.
(2) Voltage specification at the device package pin.
(3) POH = Power-on hours when the device is fully functional.
NOTE
Logic functions and parameter values are not assured out of the range specified in the
recommended operating conditions.
Table 3-4. Recommended Operating Conditions
PARAMETER
MIN
NOM
MAX
UNIT
SUPPLY NAME
DESCRIPTION
Supply voltage range for core
domain; OPP100
1.06
0.91
1.21
1.15
1.06
0.91
0.9
1.1
0.95
1.26
1.2
1.15
0.99
1.31
1.25
1.15
0.99
1.25
1.89
1.89
1.58
1.89
1.89
1.89
1.89
V
V
VDD_CORE
Supply voltage range for core
domain; OPP50
Supply voltage range for MPU
domain; Turbo
Supply voltage range for MPU
domain; OPP120
VDD_MPU(1)
V
Supply voltage range for MPU
domain; OPP100
1.1
Supply voltage range for MPU
domain; OPP50
0.95
1.1
Supply voltage range for RTC
domain input
CAP_VDD_RTC(2)
VDDS_RTC
V
V
Supply voltage range for RTC
domain
1.71
1.71
1.43
1.71
1.71
1.71
1.71
1.8
Supply voltage range for DDR IO
domain (DDR2)
1.8
VDDS_DDR
V
Supply voltage range for DDR IO
domain (DDR3)
1.5
Supply voltage range for all dual-
voltage IO domains
VDDS(3)
1.8
V
V
V
V
Supply voltage range for Core
SRAM LDOs, Analog
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDDS_PLL_DDR(4)
1.8
Supply voltage range for MPU
SRAM LDOs, Analog
1.8
Supply voltage range for DPLL
DDR, Analog
1.8
80
Device Operating Conditions
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 3-4. Recommended Operating Conditions (continued)
PARAMETER
MIN
NOM
MAX
UNIT
SUPPLY NAME
DESCRIPTION
Supply voltage range for DPLL
CORE and LCD, Analog
VDDS_PLL_CORE_LCD(4)
VDDS_PLL_MPU(4)
VDDS_OSC
1.71
1.71
1.71
1.8
1.8
1.8
1.89
1.89
1.89
V
V
V
Supply voltage range for DPLL
MPU, Analog
Supply voltage range for system
oscillator IO's, Analog
Supply voltage range for
USBPHY and PER DPLL,
Analog, 1.8V
VDDA1P8V_USB0(4)
1.71
1.8
1.89
V
Supply voltage range for USB
PHY, Analog, 1.8V
VDDA1P8V_USB1(5)
VDDA3P3V_USB0
VDDA3P3V_USB1(5)
VDDA_ADC
1.71
3.14
3.14
1.71
1.8
3.3
3.3
1.8
1.89
3.47
3.47
1.89
V
V
V
V
Supply voltage range for USB
PHY, Analog, 3.3V
Supply voltage range for USB
PHY, Analog, 3.3V
Supply voltage range for ADC,
Analog
Supply voltage range for dual-
voltage IO domain (1.8-V
operation)
VDDSHV1
VDDSHV2(5)
VDDSHV3(5)
VDDSHV4
VDDSHV5
VDDSHV6
VDDSHV1
VDDSHV2(5)
VDDSHV3(5)
VDDSHV4
VDDSHV5
VDDSHV6
1.71
1.71
1.71
1.71
1.71
1.71
3.14
3.14
3.14
3.14
3.14
3.14
1.8
1.8
1.8
1.8
1.8
1.8
3.3
3.3
3.3
3.3
3.3
3.3
1.89
1.89
1.89
1.89
1.89
1.89
3.47
3.47
3.47
3.47
3.47
3.47
V
V
V
V
V
V
V
V
V
V
V
V
Supply voltage range for dual-
voltage IO domain (1.8-V
operation)
Supply voltage range for dual-
voltage IO domain (1.8-V
operation)
Supply voltage range for dual-
voltage IO domain (1.8-V
operation)
Supply voltage range for dual-
voltage IO domain (1.8-V
operation)
Supply voltage range for dual-
voltage IO domain (1.8-V
operation)
Supply voltage range for dual-
voltage IO domain (3.3-V
operation)
Supply voltage range for dual-
voltage IO domain (3.3-V
operation)
Supply voltage range for dual-
voltage IO domain (3.3-V
operation)
Supply voltage range for dual-
voltage IO domain (3.3-V
operation)
Supply voltage range for dual-
voltage IO domain (3.3-V
operation)
Supply voltage range for dual-
voltage IO domain (3.3-V
operation)
Voltage range for DDR
SSTL/HSTL reference input
(DDR2/DDR3)
DDR_VREF
USB0_VBUS
0.49*VDDS_DDR
0
0.50*VDDS_DDR
5
0.51*VDDS_DDR
5.25
V
V
Voltage range for USB VBUS
comparator input
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UNIT
Table 3-4. Recommended Operating Conditions (continued)
PARAMETER
MIN
NOM
MAX
SUPPLY NAME
USB1_VBUS(5)
DESCRIPTION
Voltage range for USB VBUS
comparator input
0
1.71
1.71
5
1.8
1.8
5.25
1.89
1.89
V
V
V
Voltage range for the USB ID
input
USB0_ID
Voltage range for the USB ID
input
USB1_ID(5)
Commercial Temperature
Industrial Temperature
Extended Temperature
0
-40
-40
90
90
Operating Temperature
Range, Tj
°C
105
(1) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE on the ZCE package.
(2) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
from an external power supply.
(3) VDDS should be supplied irrespective of 1.8-V or 3.3-V mode of operation of the dual-voltage IOs.
(4) For more details on power supply requirements, see Section 4.1.4.
(5) Not available on the ZCE package.
Table 3-5. Operating Performance Points for ZCZ Package(1)
OPP
Turbo
VDD_MPU(2)
1.26 V ±4%
1.2 V ±4%
1.1 V ±4%
1.1 V ±4%
0.95 V ±4%
VDD_CORE(2)
1.1 V ±4%
1.1 V ±4%
1.1 V ±4%
1.1 V ±4%
0.95 V ±4%
ARM (A8)
720 MHz
600 MHz
500 MHz
275 MHz
275 MHz
DDR3(3)
303 MHz(4)
303 MHz(4)
303 MHz(4)
303 MHz(4)
-
DDR2(3)
266 MHz
266 MHz
266 MHz
266 MHz
125 MHz
mDDR(3)
200 MHz
200 MHz
200 MHz
200 MHz
90 MHz
L3/L4
200/100 MHz
200/100 MHz
200/100 MHz
200/100 MHz
100/50 MHz
OPP120
OPP100(5)
OPP100(6)
OPP50
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) Interfaces in this row are validated and available on OPP50.
(3) This parameter represents the maximum memory clock frequency. Since data is transferred on both edges of the clock, double-data rate
(DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
(4) The JEDEC JESD79-3E specification defines the maximum clock period of 3.3 ns for all standard speed bin DDR3 memory devices.
Therefore, all standard speed bin DDR3 memory devices are required to operate at 303 MHz.
(5) Applies to all orderable AM335x devices with a 500 MHz or higher speed grade.
(6) Applies to all orderable AM335x devices with a 275 MHz speed grade.
Table 3-6. Operating Performance Points for ZCE Package(1)
OPP
VDD_CORE(2)
1.1 V ±4%
ARM (A8)
500 MHz
275 MHz
275 MHz
DDR3(3)
303 MHz(4)
303 MHz(4)
-
DDR2(3)
266 MHz
266 MHz
125 MHz
mDDR(3)
200 MHz
200 MHz
90 MHz
L3/L4
OPP100(5)
OPP100(6)
OPP50
200/100 MHz
200/100 MHz
100/50 MHz
1.1 V ±4%
0.95 V ±4%
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) Interfaces in this row are validated and available on OPP50.
(3) This parameter represents the maximum memory clock frequency. Since data is transferred on both edges of the clock, double-data rate
(DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
(4) The JEDEC JESD79-3E specification defines the maximum clock period of 3.3 ns for all standard-speed bin DDR3 memory devices.
Therefore, all standard-speed bin DDR3 memory devices are required to operate at 303 MHz.
(5) Applies to all orderable AM335x devices with a 500 MHz or higher speed grade.
(6) Applies to all orderable AM335x devices with a 275 MHz speed grade.
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
3.3 DC Electrical Characteristics
Table 3-7 summarizes the dc electrical characteristics.
Note: The interfaces or signals described in Table 3-7 correspond to the interfaces or signals available in
multiplexing mode 0. All interfaces or signals multiplexed on the terminals described in Table 3-7 have the same
dc electrical characteristics.
Table 3-7. DC Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted)
PARAMETER
MIN
NOM
MAX UNIT
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A
0,DDR_A1,DDR_A2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A
14,DDR_A15,DDR_ODT,DDR_D0,DDR_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_
D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 pins
(mDDR - LVCMOS mode)
0.65 *
VDDS_DDR
VIH
High-level input voltage
V
0.35 *
VDDS_DDR
VIL
Low-level input voltage
V
V
V
VHYS
VOH
Hysteresis voltage at an input
0.07
0.25
High level output voltage, driver enabled, pullup
or pulldown disbaled
VDDS_DDR -
0.4
IOH = 8 mA
IOL = 8 mA
Low level output voltage, driver enabled, pullup
or pulldown disbaled
VOL
0.4
10
V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
-240
80
-80
240
Total leakage current through the terminal connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
IOZ
10
µA
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A
0,DDR_A1,DDR_A2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A
14,DDR_A15,DDR_ODT,DDR_D0,DDR_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_
D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 pins
(DDR2 - SSTL mode)
VIH
High-level input voltage
DDR_VREF +
0.125
V
VIL
Low-level input voltage
DDR_VREF -
0.125
V
VHYS
VOH
Hysteresis voltage at an input
NA
V
V
High-level output voltage, driver enabled, pullup
or pulldown disbaled
IOH = 8 mA
IOL = 8 mA
VDDS_DDR -
0.4
VOL
Low-level output voltage, driver enabled, pullup
or pulldown disbaled
0.4
10
V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
µA
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
-240
80
-80
240
10
IOZ
Total leakage current through the terminal connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
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Table 3-7. DC Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted) (continued)
PARAMETER
MIN
NOM
MAX UNIT
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A
0,DDR_A1,DDR_A2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A
14,DDR_A15,DDR_ODT,DDR_D0,DDR_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_
D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 pins
(DDR3 - HSTL mode)
VIH
High-level input voltage
DDR_VREF +
0.1
V
VIL
Low-level input voltage
DDR_VREF -
0.1
V
VHYS
VOH
Hysteresis voltage at an input
NA
V
V
High-level output voltage, driver enabled, pullup
or pulldown disbaled
IOH = 8 mA
IOL = 8 mA
VDDS_DDR -
0.4
VOL
Low-level output voltage, driver enabled, pullup
or pulldown disbaled
0.4
10
V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
µA
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
-240
80
-80
240
10
IOZ
Total leakage current through the terminal connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
ECAP0_IN_PWM0_OUT,UART0_CTSn,UART0_RTSn,UART0_RXD,UART0_TXD,UART1_CTSn,UART1_RTSn,UART1_RXD,UART1_T
XD,I2C0_SDA,I2C0_SCL,XDMA_EVENT_INTR0,XDMA_EVENT_INTR1,WARMRSTn,PWRONRSTn,NMIn,TMS,TDO,USB0_DRVVBUS,U
SB1_DRVVBUS (VDDSHV6 = 1.8 V)
VIH
High-level input voltage
0.65 *
V
VDDSHV6
VIL
Low-level input voltage
0.35 *
V
VDDSHV6
VHYS
VOH
Hysteresis voltage at an input
0.18
0.305
V
V
High-level output voltage, driver enabled, pullup
or pulldown disbaled
IOH = 4 mA
IOL = 4 mA
VDDSHV6 -
0.45
VOL
Low-level output voltage, driver enabled, pullup
or pulldown disbaled
0.45
5
V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
µA
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
-161
52
-100
100
-52
170
5
IOZ
Total leakage current through the terminal connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
84
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 3-7. DC Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted) (continued)
PARAMETER
MIN
NOM
MAX UNIT
ECAP0_IN_PWM0_OUT,UART0_CTSn,UART0_RTSn,UART0_RXD,UART0_TXD,UART1_CTSn,UART1_RTSn,UART1_RXD,UART1_T
XD,I2C0_SDA,I2C0_SCL,XDMA_EVENT_INTR0,XDMA_EVENT_INTR1,WARMRSTn,PWRONRSTn,NMIn,TMS,TDO,USB0_DRVVBUS,U
SB1_DRVVBUS (VDDSHV6 = 3.3 V)
VIH
High-level input voltage
Low-level input voltage
2
V
V
V
V
VIL
0.8
VHYS
VOH
Hysteresis voltage at an input
0.265
0.44
High-level output voltage, driver enabled, pullup
or pulldown disbaled
IOH = 4 mA
IOL = 4 mA
VDDSHV6 -
0.2
VOL
Low-level output voltage, driver enabled, pullup
or pulldown disbaled
0.2
18
V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
µA
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
-243
51
-100
110
-19
210
18
IOZ
Total leakage current through the terminal connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
TCK (VDDSHV6 = 1.8 V)
VIH
VIL
VHYS
II
High-level input voltage
1.45
0.4
V
V
Low-level input voltage
0.46
5
Hysteresis voltage at an input
V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
-161
52
-100
100
-52
170
TCK (VDDSHV6 = 3.3 V)
VIH
High-level input voltage
2.15
0.4
V
V
V
VIL
Low-level input voltage
0.46
18
VHYS
Hysteresis voltage at an input
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
-243
51
-100
110
-19
210
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Table 3-7. DC Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted) (continued)
PARAMETER
MIN
NOM
MAX UNIT
All other LVCMOS pins (VDDSHVx = 1.8 V; x=1-6)
VIH
High-level input voltage
0.65 *
V
VDDSHVx
VIL
Low-level input voltage
0.35 *
V
VDDSHVx
VHYS
VOH
Hysteresis voltage at an input
0.18
0.305
V
V
High-level output voltage, driver enabled, pullup
or pulldown disbaled
IOH = 6 mA
IOL = 6 mA
VDDSHVx -
0.45
VOL
Low-level output voltage, driver enabled, pullup
or pulldown disbaled
0.45
5
V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
µA
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
-161
52
-100
100
-52
170
5
IOZ
Total leakage current through the terminal connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
All other LVCMOS pins (VDDSHVx = 3.3 V; x=1-6)
VIH
High-level input voltage
Low-level input voltage
2
V
V
V
V
VIL
0.8
VHYS
VOH
Hysteresis voltage at an input
0.265
0.44
High-level output voltage, driver enabled, pullup
or pulldown disbaled
IOH = 6 mA
IOL = 6 mA
VDDSHVx -
0.2
VOL
Low-level output voltage, driver enabled, pullup
or pulldown disbaled
0.2
18
V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
µA
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
-243
51
-100
110
-19
210
18
IOZ
Total leakage current through the terminal connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
86
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
3.4 External Capacitors
To improve module performance, decoupling capacitors are required to suppress the switching noise generated
by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is close to
the device, because this minimizes the inductance of the circuit board wiring and interconnects.
3.4.1 Voltage Decoupling Capacitors
Table 3-8 summarizes the Core voltage decoupling characteristics.
3.4.1.1 Core Voltage Decoupling Capacitors
To improve module performance, decoupling capacitors are required to suppress high-frequency switching noise
and to stabilize the supply voltage. A decoupling capacitor is most effective when located close to the AM335x
device, because this minimizes the inductance of the circuit board wiring and interconnects.
Table 3-8. Core Voltage Decoupling Characteristics
PARAMETER
MIN
TBD
TBD
TYP
10.08
10.05
MAX
TBD
TBD
UNIT
μF
(1)
CVDD_CORE
(2)(3)
CVDD_MPU
(1) The typical value corresponds to 1 cap of 10 μF and 8 caps of 10 nF.
μF
(2) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE on the ZCE package.
(3) The typical value corresponds to 1 cap of 10 μF and 5 caps of 10 nF.
3.4.1.2 IO and Analog Voltage Decoupling Capacitors
Table 3-9 summarizes the power-supply decoupling capacitor recommendations.
Table 3-9. Power-Supply Decoupling Capacitor Characteristics
PARAMETER
MIN
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TYP
10
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
UNIT
nF
nF
nF
nF
nF
μF
μF
nF
nF
nF
nF
nF
nF
nF
μF
μF
μF
CVDDA_ADC
CVDDA1P8V_USB0
CCVDDA3P3V_USB0
10
10
(1)
CVDDA1P8V_USB1
10
(1)
CVDDA3P3V_USB1
10
(2)
CVDDS
10.04
10.06
10
(3)(4)
CVDDS_DDR
CVDDS_OSC
CVDDS_PLL_DDR
10
CVDDS_PLL_CORE_LCD
CVDDS_SRAM_CORE_BG
CVDDS_SRAM_MPU_BB
CVDDS_PLL_MPU
10
10
10
10
CVDDS_RTC
10
(5)
CVDDSHV1
10.02
10.02
10.02
(1)(5)
CVDDSHV2
(1)(5)
CVDDSHV3
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Table 3-9. Power-Supply Decoupling Capacitor Characteristics (continued)
PARAMETER
MIN
TBD
TBD
TBD
TYP
10.02
10.02
10.06
MAX
TBD
TBD
TBD
UNIT
μF
(5)
(5)
(3)
CVDDSHV4
CVDDSHV5
CVDDSHV6
μF
μF
(1) Not available on the ZCE package.
(2) Typical values consist of 1 cap of 10 μF and 4 caps of 10 nF.
(3) Typical values consist of 1 cap of 10 μF and 6 caps of 10 nF.
(4) For more details on decoupling capacitor requirements for the mDDR(LPDDR)/DDR2/DDR3 memory interface, see Section 5.5.2.2.2.6
and Section 5.5.2.2.2.7.
(5) Typical values consist of 1 cap of 10 μF and 2 caps of 10 nF.
3.4.2 Output Capacitors
Internal low dropout output (LDO) regulators require external capacitors to stabilize their outputs. These
capacitors should be placed as close as possible to the respective terminals of the AM335x device. Table 3-10
summarizes the LDO output capacitor recommendations.
Table 3-10. Output Capacitor Characteristics
PARAMETER
MIN
0.7
0.7
0.7
0.7
TYP
MAX
1.3
UNIT
μF
(1)
CCAP_VDD_SRAM_CORE
1
1
1
1
(1)(2)
CCAP_VDD_RTC
1.3
μF
(1)
CCAP_VDD_SRAM_MPU
1.3
μF
(1)
CCAP_VBB_MPU
1.3
μF
(1) LDO regulator outputs should not be used as a power source for any external components.
(2) The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the RTC_KLDO_ENn terminal is high.
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Figure 3-1 illustrates an example of the external capacitors.
AM335x Device
VDDS_PLL_MPU
CVDDS_PLL_MPU
MPU
PLL
VDD_MPU
MPU
CVDD_MPU
VDDS_PLL_CORE_LCD
CVDDS_PLL_CORE_LCD
CORE
PLL
LCD
PLL
VDD_CORE
CVDD_CORE
CORE
CAP_VBB_MPU
CCAP_VBB_MPU
VDDS
IO
CVDDS
VDDS_SRAM_MPU_BB
CVDDS_SRAM_MPU_BB
VDDSHV1
IOs
MPU SRAM
LDO
CVDDSHV1
Back Bias
LDO
CAP_VDD_SRAM_MPU
CCAP_VDD_SRAM_MPU
VDDSHV2
IOs
CVDDSHV2
CVDDSHV3
CVDDSHV4
CVDDSHV5
CVDDSHV6
CVDDS_DDR
CVDDS_RTC
VDDS_SRAM_CORE_BG
CVDDS_SRAM_CORE_BG
VDDSHV3
IOs
CORE SRAM
LDO
Band Gap
Reference
CAP_VDD_SRAM_CORE
CCAP_VDD_SRAM_CORE
VDDSHV4
IOs
VDDA_3P3V_USBx
CVDDA_3P3V_USBx
VDDSHV5
IOs
VSSA_USB
USB PHYx
VDDA_1P8V_USBx
VDDSHV6
IOs
CVDDA_1P8V_USBx
VSSA_USB
VDDA_ADC
VDDS_DDR
IOs
CVDDA_ADC
VSSA_ADC
ADC
VDDS_RTC
IOs
VDDS_OSC
CVDDS_OSC
VDDS_PLL_DDR
CVDDS_PLL_DDR
DDR
PLL
CAP_VDD_RTC
CCAP_VDD_RTC
RTC
A. Decoupling capacitors must be placed as closed as possible to the power terminal. Choose the ground located
closest to the power pin for each decoupling capacitor. In case of interconnecting powers, first insert the decoupling
capacitor and then interconnect the powers.
B. The decoupling capacitor value depends on the board characteristics.
Figure 3-1. External Capacitors
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3.5 Touchscreen Controller and Analog-to-Digital Subsystem Electrical Parameters
The touchscreen controller (TSC) and analog-to-digital converter (ADC) subsystem (TSC_ADC) is an 8-channel
general-purpose ADC with optional support for interleaving TSC conversions for 4-wire, 5-wire, or 8-wire resistive
panels. The TSC_ADC subsystem can be configured for use in one of the following applications:
•
•
•
•
8 general-purpose ADC channels
4-wire TSC with 4 general-purpose ADC channels
5-wire TSC with 3 general-purpose ADC channels
8-wire TSC.
Table 3-11 summarizes the TSC_ADC subsystem electrical parameters.
Table 3-11. TSC_ADC Electrical Parameters
PARAMETER
Analog Input
CONDITION
MIN
NOM
MAX UNIT
(0.5 * VDDA_ADC) +
0.25
VREFP(1)
VDDA_ADC
V
(0.5 * VDDA_ADC) -
0.25
VREFN(1)
0
V
V
VREFP + VREFN(1)
VDDA_ADC
Internal Voltage Reference
External Voltage Reference
0
VDDA_ADC
VREFP
Full-scale Input Range
V
VREFN
Internal Voltage Reference:
VDDA_ADC = 1.8V
External Voltage Reference:
VREFP - VREFN = 1.8V
Differential Non-Linearity
(DNL)
-1
-2
0.5
±1
1
LSB
Source impedance = 50 Ω
Internal Voltage Reference:
VDDA_ADC = 1.8V
2
LSB
External Voltage Reference:
VREFP - VREFN = 1.8V
Integral Non-Linearity (INL)
Source Impedance = 1k Ω
Internal Voltage Reference:
VDDA_ADC = 1.8V
±1
LSB
LSB
External Voltage Reference:
VREFP - VREFN = 1.8V
Internal Voltage Reference:
VDDA_ADC = 1.8V
External Voltage Reference:
VREFP - VREFN = 1.8V
Gain Error
+/- 2
Internal Voltage Reference:
VDDA_ADC = 1.8V
External Voltage Reference:
VREFP - VREFN = 1.8V
Offset Error
+/- 2
5.5
LSB
pF
Input Sampling Capacitance
Internal Voltage Reference:
VDDA_ADC = 1.8V
Signal-to-Noise Ratio
(SNR)
External Voltage Reference:
VREFP - VREFN = 1.8V
Input Signal: 30 kHz sine wave at
-0.5 dB Full Scale
70
75
dB
dB
Internal Voltage Reference:
VDDA_ADC = 1.8V
External Voltage Reference:
VREFP - VREFN = 1.8V
Input Signal: 30 kHz sine wave at
-0.5 dB Full Scale
Total Harmonic Distortion
(THD)
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 3-11. TSC_ADC Electrical Parameters (continued)
PARAMETER
CONDITION
MIN
NOM
MAX UNIT
Internal Voltage Reference:
VDDA_ADC = 1.8V
Spurious Free Dynamic
Range
External Voltage Reference:
VREFP - VREFN = 1.8V
Input Signal: 30 kHz sine wave at
-0.5 dB Full Scale
80
dB
Internal Voltage Reference:
VDDA_ADC = 1.8V
Signal-to-Noise Plus
Distortion
External Voltage Reference:
VREFP - VREFN = 1.8V
Input Signal: 30 kHz sine wave at
-0.5 dB Full Scale
69
20
dB
VREFP/VREFN Input Impedance
Input Impedance of
kΩ
f = input frequency
[1/(65.97 x 10-12 * f)]
Ω
AIN[8:0](2)
Sampling Dynamics
ADC
Clock
Cycles
Conversion Time
Acquisition Time
15
2
ADC
Clock
Cycles
Sampling Rate
ADC Clock = 3 MHz
200
100
kSPS
dB
Channel-to-Channel Isolation
Touchscreen Switch Drivers
Pull-Up and Pull-Down Switch ON Resistance (Ron)
2
Ω
Pull-Up and Pull-Down
Switch Current Leakage
Ileak
Source impedance = 500 Ω
0.5
uA
Drive Current
25
6
mA
kΩ
kΩ
Touchscreen Resistance
Pen Touch Detect
2
(1) VREFP and VREFN must be tied to ground if the internal voltage reference is used.
(2) This parameter is valid when the respective AIN terminal is configured to operate as a general-purpose ADC input.
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4 Power and Clocking
4.1 Power Supplies
4.1.1 Power-Up Sequencing
1.8V
1.8V
VDDS_RTC
RTC_PWRONRSTn
1.8V
1.8V
PMIC_POWER_EN
All 1.8-V Supplies
1.8V/1.5V
3.3V
VDDS_DDR
IO 3.3-V Supplies
1.1V
3.3V
VDD_CORE, VDD_MPU
PWRONRSTn
CLK_M_OSC
A. RTC_PWRONRSTn should be asserted for at least 1ms.
B. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
C. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
D. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V
I/O power supplies.
E. VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE. The power sequence shown provides the lowest leakage option.
F. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended
sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the
recommended sequence.
Figure 4-1. Preferred Power-Supply Sequencing with Dual-Voltage I/Os Configured as 3.3 V
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
1.8V
1.8V
VDDS_RTC
RTC_PWRONRSTn
1.8V
PMIC_POWER_EN
3.3V
1.8V
See Notes Below
All 1.8-V Supplies
All 3.3-V Supplies
1.8V/1.5V
1.1V
VDDS_DDR
VDD_CORE, VDD_MPU
PWRONRSTn
CLK_M_OSC
A. RTC_PWRONRSTn should be asserted for at least 1ms.
B. The 3.3-V I/O power supplies may be ramped simultaneously with the 1.8-V I/O power supplies if the voltage sourced
by any 3.3-V power supplies does not exceed the voltage sourced by any 1.8-V power supply by more than 2 V.
Serious reliability issues may occur if the system power supply design allows any 3.3-V I/O power supplies to exceed
any 1.8-V I/O power supplies by more than 2 V.
C. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
D. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
E. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V
I/O power supplies.
F. VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE. The power sequence shown provides the lowest leakage option.
G. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended
sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the
recommended sequence.
Figure 4-2. Alternate Power-Supply Sequencing with Dual-Voltage I/Os Configured as 3.3 V
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1.8V
1.8V
VDDS_RTC
RTC_PWRONRSTn
1.8V
1.8V
PMIC_POWER_EN
All 1.8-V Supplies
1.8V/1.5V
VDDS_DDR
All 3.3-V Supplies
3.3V
1.1V
VDD_CORE, VDD_MPU
1.8V
PWRONRSTn
CLK_M_OSC
A. RTC_PWRONRSTn should be asserted for at least 1ms.
B. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
C. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
D. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V
I/O power supplies.
E. VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE. The power sequence shown provides the lowest leakage option.
F. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended
sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the
recommended sequence.
Figure 4-3. Power-Supply Sequencing with Dual-Voltage I/Os Configured as 1.8 V
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
1.8V
1.1V
VDDS_RTC,
CAP_VDD_RTC
1.8V
1.8V
1.8V
RTC_PWRONRSTn
PMIC_POWER_EN
VDDSHV 1-6
All other 1.8-V Supplies
1.8V/1.5V
VDDS_DDR
3.3V
1.1V
All 3.3-V Supplies
VDD_CORE, VDD_MPU
PWRONRSTn
1.8V
CLK_M_OSC
A. RTC_PWRONRSTn should be asserted for at least 1ms.
B. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is
disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled,
CAP_VDD_RTC should be sourced from an external 1.1-V power supply.
C. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
D. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
E. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V
I/O power supplies.
F. VDDS_RTC should be ramped at the same time or before CAP_VDD_RTC, but these power inputs can be ramped
independent of other power supplies if PMIC_POWER_EN functionality is not required. If CAP_VDD_RTC is ramped
after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The power sequence
shown provides the lowest leakage option.
G. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended
sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the
recommended sequence.
Figure 4-4. Power-Supply Sequencing with Internal RTC LDO Disabled
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1.8V
VDDS_RTC,
All other 1.8-V Supplies
1.8V/1.5V
3.3V
VDDS_DDR
All 3.3-V Supplies
1.1V
VDD_CORE, VDD_MPU
CAP_VDD_RTC
PWRONRSTn
CLK_M_OSC
A. CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is
disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled,
CAP_VDD_RTC should be sourced from an external 1.1-V power supply. The PMIC_POWER_EN output cannot be
used when the RTC is disabled.
B. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
C. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
D. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V
I/O power supplies.
E. VDDS_RTC should be ramped at the same time or before CAP_VDD_RTC, but these power inputs can be ramped
independent of other power supplies if PMIC_POWER_EN functionality is not required. If CAP_VDD_RTC is ramped
after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The power sequence
shown provides the lowest leakage option.
F. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended
sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the
recommended sequence.
Figure 4-5. Power-Supply Sequencing with RTC Feature Disabled
4.1.2 Power-Down Sequencing
PWRONRSTn input terminal should be taken low, which stops all internal clocks before power supplies
are turned off. All other external clocks to the device should be shut off.
The preferred way to sequence power down is to have all the power supplies ramped down sequentially in
the exact reverse order of the power-up sequencing. In other words, the power supply that has been
ramped up first should be the last one that should be ramped down. This ensures there would be no
spurious current paths during the power-down sequence. The VDDS power supply must ramp down after
all 3.3-V VDDSHVx [1-6] power supplies.
If it is desired to ramp down VDDS and VDDSHVx [1-6] simultaneously, it should always be ensured that
the difference between VDDS and VDDSHVx [1-6] during the entire power-down sequence is <2 V. If this
is violated it can result in reliability risks for the device. Further, it should also be ensured that the VDDS
supply should be ≥1.5 V of all the other supplies in the system during the ramp down.
If there is no 3.3-V VDDSHVx [1-6] power supply, the VDDS power supply may ramp down at the same
time or after all 1.8-V VDDSHVx[1-6] power supplies. It should be ensured that the VDDS supply should
be ≥1.5 V of all the other supplies in the system during ramp down.
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4.1.3 VDD_MPU_MON Connections
Figure 4-6 shows the VDD_MPU_MON connectivity. VDD_MPU_MON connectivity is available only on the
ZCZ package.
VDD_MPU
Power
Management
IC
AM335x Device
VDD_MPU_MON
Vfeedback
Connection for VDD_MPU_MON if voltage monitoring is used
VDD_MPU
Power
Source
VDD_MPU_MON
AM335x Device
Connection for VDD_MPU_MON if voltage monitoring is NOT used
Figure 4-6. VDD_MPU_MON Connectivity
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4.1.4 Digital Phase-Locked Loop Power Supply Requirements
The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor
of the AM335x device. The AM335x device integrates 5 different DPLLs—Core DPLL, Per DPLL, Display
DPLL, DDR DPLL, MPU DPLL.
Figure 4-7 illustrates the power supply connectivity implemented in the AM335x device. Table 4-1 provides
the power supply requirements for the DPLL.
MPU
PLL
PER
PLL
VDDS_PLL_MPU
VDDA1P8V_USB0
CORE
PLL
DDR
PLL
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
LCD
PLL
Figure 4-7. DPLL Power Supply Connectivity
Table 4-1. DPLL Power Supply Requirements
SUPPLY NAME
DESCRIPTION
MIN NOM MAX UNITS
VDDA1P8V_USB0
Supply voltage range for USBPHY and PER DPLL, Analog, 1.8V
Max. peak-to-peak supply noise
1.71 1.8
1.71 1.8
1.71 1.8
1.71 1.8
1.89
V
50 mV (p-p)
VDDS_PLL_MPU
Supply voltage range for DPLL MPU, Analog
Max. peak-to-peak supply noise
1.89
V
50 mV (p-p)
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
Supply voltage range for DPLL CORE and LCD, Analog
Max. peak-to-peak supply noise
1.89
V
50 mV (p-p)
Supply voltage range for DPLL DDR, Analog
Max. peak-to-peak supply noise
1.89
V
50 mV (p-p)
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4.2 Clock Specifications
4.2.1 Input Clock Specifications
The AM335x device has two clock inputs. Each clock input passes through an internal oscillator which can
be connected to an external crystal circuit (oscillator mode) or external LVCMOS square-wave digital clock
source (bypass mode). The oscillators automatically operate in bypass mode when their input is
connected to an external LVCMOS square-wave digital clock source. The oscillator associated with a
specific clock input must be enabled when the clock input is being used in either oscillator mode or bypass
mode.
The OSC1 oscillator provides a 32.768-kHz reference clock to the real-time clock (RTC) and is connected
to the RTC_XTALIN and RTC_XTALOUT terminals. This clock source is referred to as the 32K oscillator
(CLK_32K_RTC) in the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual
(literature number SPRUH73). OSC1 is disabled by default after power is applied. This clock input is
optional and may not be required if the RTC is configured to receive a clock from the internal 32k RC
oscillator (CLK_RC32K) or peripheral PLL (CLK_32KHZ) which receives a reference clock from the OSC0
input.
The OSC0 oscillator provides a 19.2-MHz, 24-MHz, 25-MHz, or 26-MHz reference clock which is used to
clock all non-RTC functions and is connected to the XTALIN and XTALOUT terminals. This clock source is
referred to as the master oscillator (CLK_M_OSC) in the AM335x ARM Cortex-A8 Microprocessors
(MPUs) Technical Reference Manual (literature number SPRUH73). OSC0 is enabled by default after
power is applied.
For more information related to recommended circuit topologies and crystal oscillator circuit requirements
for these clock inputs, see Section 4.2.2.
4.2.2 Input Clock Requirements
4.2.2.1 OSC0 Internal Oscillator Clock Source
Figure 4-8 shows the recommended crystal circuit. It is recommended that pre-production printed circuit
board (PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper
oscillator operation when combined with production crystal circuit components. In most cases, Rbias is not
required and Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after
evaluating oscillator performance with production crystal circuit components installed on pre-production
PCBs.
The XTALIN terminal has a 15 - 40 kΩ internal pull-down resistor which is enabled when OSC0 is
disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which
may increase leakage current through the oscillator input buffer.
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AM335x
XTALIN
VSS_OSC
XTALOUT
C1
C2
Optional Rbias
Optional Rd
Crystal
A. Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the AM335x package.
Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise
coupled into the oscillator. The VSS_OSC terminal provides a Kelvin ground reference for the external crystal
components. External crystal component grounds should only be connected to the VSS_OSC terminal and should not
be connected to the PCB ground plane.
B. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components
(excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to
provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL
=
[(C1*C2)/(C1+C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer
plus any mutual capacitance (Cpkg + CPCB) seen across the AM335x XTALIN and XTALOUT signals. For
recommended values of crystal circuit components, see Table 4-2.
Figure 4-8. OSC0 Crystal Circuit Schematic
Table 4-2. OSC0 Crystal Circuit Requirements
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
fxtal
Crystal parallel resonance
frequency
Fundamental mode oscillation only
19.2, 24.0,
25.0, or
26.0
MHz
Crystal frequency
stability/tolerance
-50.0
50.0
ppm
CC1
C1 capacitance
C2 capacitance
Shunt capacitance
12.0
12.0
24.0
24.0
5.0
pF
pF
pF
Ω
CC2
Cshunt
ESR
Crystal effective series
resistance
fxtal = 19.2 MHz, oscillator has nominal
negative resistance of 272 Ω and worst-
case negative resistance of 163 Ω
54.4
fxtal = 24.0 MHz, oscillator has nominal
negative resistance of 240 Ω and worst-
case negative resistance of 144 Ω
48.0
46.6
45.3
Ω
Ω
Ω
fxtal = 25.0 MHz, oscillator has nominal
negative resistance of 233 Ω and worst-
case negative resistance of 140 Ω
fxtal = 26.0 MHz, oscillator has nominal
negative resistance of 227 Ω and worst-
case negative resistance of 137 Ω
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Table 4-3. OSC0 Crystal Circuit Characteristics
NAME
DESCRIPTION
MIN
TYP
0.01
0.01
MAX
UNIT
pF
Cpkg
Shunt capacitance of
package
ZCE package
ZCZ package
pF
Pxtal
The actual values of the ESR, fxtal, and CL should be used to yield a
typical crystal power dissipation value. Using the maximum values
specified for ESR, fxtal, and CL parameters yields a maximum power
dissipation value.
Pxtal = 0.5 ESR (2 π fxtal
CL VDDS_OSC)2
tsX
Start-up time
1.5
ms
VDD_CORE (min.)
VDD_CORE
VSS
VDDS_OSC (min.)
VDDS_OSC
XTALOUT
VSS
tsX
Time
Figure 4-9. OSC0 Start-up Time
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4.2.2.2 OSC0 LVCMOS Digital Clock Source
Figure 4-10 shows the recommended oscillator connections when OSC0 is connected to an LVCMOS
square-wave digital clock source. The LVCMOS clock source is connected to the XTALIN terminal. In this
mode of operation, the XTALOUT terminal should not be used to source any external components. The
printed circuit board design should provide a mechanism to disconnect the XTALOUT terminal from any
external components or signal traces that may couple noise into OSC0 via the XTALOUT terminal.
The XTALIN terminal has a 15 - 40 kΩ internal pull-down resistor which is enabled when OSC0 is
disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which
may increase leakage current through the oscillator input buffer.
AM335x
XTALIN
VSS_OSC
XTALOUT
LVCMOS
Digital
Clock
Source
Figure 4-10. OSC0 LVCMOS Circuit Schematic
4.2.2.3 OSC1 Internal Oscillator Clock Source
Figure 4-11 shows the recommended crystal circuit for OSC1 of the ZCE package and Figure 4-12 shows
the recommended crystal circuit for OSC1 of the ZCZ package. It is recommended that pre-production
printed circuit board (PCB) designs include the two optional resistors Rbias and Rd in case they are
required for proper oscillator operation when combined with production crystal circuit components. In most
cases, Rbias is not required and Rd is a 0-Ω resistor. These resistors may be removed from production
PCB designs after evaluating oscillator performance with production crystal circuit components installed on
pre-production PCBs.
The RTC_XTALIN terminal does not enable an internal pull-down resistor when OSC1 is disabled. If this
oscillator is disabled, the RTC_XTALIN terminal may float to an invalid logic level which may increase
leakage current through the oscillator input buffer. This should not be an issue for most applications that
use this oscillator to source the RTC clock since the RTC requires a continuous clock to maintain time.
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AM335x
(ZCE Package)
RTC_XTALIN
RTC_XTALOUT
Optional Rbias
Optional Rd
Crystal
C1
C2
A. Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the AM335x package.
Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise
coupled into the oscillator.
B. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components
(excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to
provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL
=
[(C1*C2)/(C1+C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer
plus any mutual capacitance (Cpkg + CPCB) seen across the AM335x RTC_XTALIN and RTC_XTALOUT signals. For
recommended values of crystal circuit components, see Table 4-4.
Figure 4-11. OSC1 (ZCE Package) Crystal Circuit Schematic
AM335x
(ZCZ Package)
RTC_XTALIN
VSS_RTC
RTC_XTALOUT
C1
C2
Optional Rbias
Optional Rd
Crystal
A. Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the AM335x package.
Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise
coupled into the oscillator.
B. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components
(excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to
provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL
=
[(C1*C2)/(C1+C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer
plus any mutual capacitance (Cpkg + CPCB) seen across the AM335x RTC_XTALIN and RTC_XTALOUT signals. For
recommended values of crystal circuit components, see Table 4-4.
Figure 4-12. OSC1 (ZCZ Package) Crystal Circuit Schematic
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Table 4-4. OSC1 Crystal Circuit Requirements
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
fxtal
Crystal parallel resonance
frequency
Fundamental mode oscillation only
32.768
kHz
Crystal frequency
stability/tolerance
Maximum RTC error = 10.512
minutes/year
-20.0
-50.0
20.0
50.0
ppm
ppm
Maximum RTC error = 26.28
minutes/year
CC1
C1 capacitance
C2 capacitance
Shunt capacitance
12.0
12.0
24.0
24.0
1.5
pF
pF
pF
kΩ
CC2
Cshunt
ESR
Crystal effective series
resistance
fxtal = 32.768 kHz, oscillator has nominal
negative resistance of 725 kΩ and worst-
case negative resistance of 250 kΩ
80
Table 4-5. OSC1 Crystal Circuit Characteristics
NAME
DESCRIPTION
MIN
TYP
0.17
0.01
MAX
UNIT
pF
Cpkg
Shunt capacitance of
package
ZCE package
ZCZ package
pF
Pxtal
The actual values of the ESR, fxtal, and CL should be used to yield a
typical crystal power dissipation value. Using the maximum values
specified for ESR, fxtal, and CL parameters yields a maximum power
dissipation value.
Pxtal = 0.5 ESR (2 π fxtal
CL VDDS_RTC)2
tsX
Start-up time
2
s
CAP_VDD_RTC (min.)
CAP_VDD_RTC
VSS_RTC
VDDS_RTC (min.)
VDDS_RTC
RTC_XTALOUT
VSS_RTC
tsX
Time
Figure 4-13. OSC1 Start-up Time
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4.2.2.4 OSC1 LVCMOS Digital Clock Source
Figure 4-14 shows the recommended oscillator connections when OSC1 of the ZCE package is connected
to an LVCMOS square-wave digital clock source and Figure 4-15 shows the recommended oscillator
connections when OSC1 of the ZCZ package is connected to an LVCMOS square-wave digital clock
source. The LVCMOS clock source is connected to the RTC_XTALIN terminal. In this mode of operation,
the RTC_XTALOUT terminal should not be used to source any external components. The printed circuit
board design should provide a mechanism to disconnect the RTC_XTALOUT terminal from any external
components or signal traces that may couple noise into OSC1 via the RTC_XTALOUT terminal.
The RTC_XTALIN terminal does not enable an internal pull-down resistor when OSC1 is disabled. If this
oscillator is disabled, the RTC_XTALIN terminal may float to an invalid logic level which may increase
leakage current through the oscillator input buffer. This should not be an issue for most applications that
use this oscillator to source the RTC clock since the RTC requires a continuous clock to maintain time.
AM335x
(ZCE Package)
RTC_XTALIN
RTC_XTALOUT
LVCMOS
Digital
Clock
N/C
Source
Figure 4-14. OSC1 (ZCE Package) LVCMOS Circuit Schematic
AM335x
(ZCZ Package)
RTC_XTALIN
VSS_RTC
RTC_XTALOUT
LVCMOS
Digital
Clock
N/C
Source
Figure 4-15. OSC1 (ZCZ Package) LVCMOS Circuit Schematic
4.2.2.5 OSC1 Not Used
Figure 4-16 shows the recommended oscillator connections when OSC1 of the ZCE package is not used
and Figure 4-17 shows the recommended oscillator connections when OSC1 of the ZCZ package is not
used. An external 10 kΩ maximum pull-down resistor should be connected to the RTC_XTALIN terminal to
prevent this input from floating to an invalid logic level which may increase leakage current through the
oscillator input buffer. The RTC_XTALOUT terminal is a no connect (NC).
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AM335x
(ZCE Package)
RTC_XTALIN
RTC_XTALOUT
Rpd
N/C
Figure 4-16. OSC1 (ZCE Package) Not Used Schematic
AM335x
(ZCZ Package)
RTC_XTALIN
Rpd
VSS_RTC
RTC_XTALOUT
N/C
Figure 4-17. OSC1 (ZCZ Package) Not Used Schematic
4.2.3 Output Clock Specifications
The AM335x device has two clock output signals. The CLKOUT1 signal is always a replica of the OSC0
input clock which is referred to as the master oscillator (CLK_M_OSC) in the AM335x ARM Cortex-A8
Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73). The CLKOUT2
signal can be configured to output the OSC1 input clock, which is referred to as the 32K oscillator
(CLK_32K_RTC) in the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual
(literature number SPRUH73), or four other internal clocks. For more information related to configuring
these clock output signals, see the CLKOUT Signals section of the AM335x ARM Cortex-A8
Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73).
4.2.4 Output Clock Characteristics
4.2.4.1 CLKOUT1
The CLKOUT1 signal can be output on the XDMA_EVENT_INTR0 terminal. This terminal connects to one
of seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR0 multiplexer must be
configured for Mode 3 to connect the CLKOUT1 signal to the XDMA_EVENT_INTR0 terminal.
The default reset configuration of the XDMA_EVENT_INTR0 multiplexer is selected by the logic level
applied to the LCD_DATA5 terminal on the rising edge of PWRONRSTn. The XDMA_EVENT_INTR0
multiplexer is configured to Mode 7 if the LCD_DATA5 terminal is low on the rising edge of PWRONRSTn
or Mode 3 if the LCD_DATA5 terminal is high on the rising edge of PWRONRSTn. This allows the
CLKOUT1 signal to be output on the XDMA_EVENT_INTR0 terminal without software intervention. In this
mode, the output is held low while PWRONRSTn is active and begins to toggle after PWRONRSTn is
released.
4.2.4.2 CLKOUT2
The CLKOUT2 signal can be output on the XDMA_EVENT_INTR1 terminal. This terminal connects to one
of seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR1 multiplexer must be
configured for Mode 3 to connect the CLKOUT2 signal to the XDMA_EVENT_INTR1 terminal.
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The default reset configuration of the XDMA_EVENT_INTR1 multiplexer is always Mode 7. Software must
configure the XDMA_EVENT_INTR1 multiplexer to Mode 3 for the CLKOUT2 signal to be output on the
XDMA_EVENT_INTR1 terminal.
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5 Peripheral Information and Timings
The AM335x device contains many peripheral interfaces. In order to reduce package size and lower
overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex
up to eight signal functions. Although there are many combinations of pin multiplexing that are possible,
only a certain number of sets, called IO Sets, are valid due to timing limitations. These valid IO Sets were
carefully chosen to provide many possible application scenarios for the user.
Texas Instruments has developed a Windows-based application called Pin Mux Utility that helps a system
designer select the appropriate pin-multiplexing configuration for their AM335x-based product design. The
Pin Mux Utility provides a way to select valid IO Sets of specific peripheral interfaces to ensure the pin-
multiplexing configuration selected for a design only uses valid IO Sets supported by the AM335x device.
5.1 Parameter Information
5.1.1 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external
logic hardware such as buffers may be used to compensate any timing differences.
The timing parameter values specified in this data manual assume the SLEWCTRL bit in each pad control
register is configured for fast mode (0b).
For the mDDR(LPDDR)/DDR2/DDR3 memory interface, it is not necessary to use the IBIS models to
analyze timing characteristics. TI provides a PCB routing rules solution that describes the routing rules to
ensure the mDDR(LPDDR)/DDR2/DDR3 memory interface timings are met.
5.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
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5.3 Controller Area Network (CAN)
For more information, see the Controller Area Network (CAN) section of the AM335x ARM Cortex-A8
Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73).
5.3.1 DCAN Electrical Data and Timing
Table 5-1. Timing Requirements for DCANx Receive
(see Figure 5-1)
NO.
MIN
MAX
1
H + 2(1)
UNIT
Mbps
ns
fbaud(baud)
tw(RX)
Maximum programmable baud rate
Pulse duration, receive data bit
1
H - 2(1)
(1) H = period of baud rate, 1/programmed baud rate.
Table 5-2. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
(see Figure 5-1)
NO.
PARAMETER
Maximum programmable baud rate
Pulse duration, transmit data bit
MIN
MAX
1
H + 2(1)
UNIT
Mbps
ns
fbaud(baud)
tw(TX)
2
H - 2(1)
(1) H = period of baud rate, 1/programmed baud rate.
1
2
DCANx_RX
DCANx_TX
Figure 5-1. DCANx Timings
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5.4 Ethernet Media Access Controller (EMAC)/Switch
5.4.1 Ethernet MAC/Switch Electrical Data and Timing
The Ethernet MAC/Switch implemented in the AM335x device supports GMII mode, but the AM335x
design does not pin out 9 of the 24 GMII signals. This was done to reduce the total number of package
terminals. Therefore, the AM335x device does not support GMII mode. MII mode is supported with the
remaining GMII signals.
The AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number
SPRUH73) and this document may reference internal signal names when discussing peripheral input and
output signals since many of the AM335x package terminals can be multiplexed to one of several
peripheral signals. For example, the AM335x terminal names for port 1 of the Ethernet MAC/Switch have
been changed from GMII to MII to indicate their Mode 0 function, but the internal signal is named GMII.
However, documents that describe the Ethernet switch reference these signals by their internal signal
name. For a cross-reference of internal signal names to terminal names, see Table 2-7.
Operation of the Ethernet MAC/Switch is not supported for OPP50.
5.4.1.1 Ethernet MAC/Switch MII Electrical Data and Timing
Table 5-3. Ethernet MAC/Switch Timing Conditions
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1(1)
1(1)
5(1)
5(1)
ns
ns
Output Condition
CLOAD Output load capacitance
(1) Except when specified otherwise.
3
30
pF
Table 5-4. Timing Requirements for GMII[x]_RXCLK - MII Mode
(see Figure 5-2)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
399.96
140
MAX
400.04
260
MIN
39.996
14
MAX
40.004
26
1
2
3
4
tc(RX_CLK)
tw(RX_CLKH)
tw(RX_CLKL)
tt(RX_CLK)
Cycle time, RX_CLK
ns
ns
ns
ns
Pulse Duration, RX_CLK high
Pulse Duration, RX_CLK low
Transition time, RX_CLK
140
260
14
26
5
5
1
4
2
3
GMII[x]_RXCLK
4
Figure 5-2. GMII[x]_RXCLK Timing - MII Mode
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Table 5-5. Timing Requirements for GMII[x]_TXCLK - MII Mode
(see Figure 5-3)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
399.96
140
MAX
400.04
260
MIN
39.996
14
MAX
40.004
26
1
2
3
4
tc(TX_CLK)
tw(TX_CLKH)
tw(TX_CLKL)
tt(TX_CLK)
Cycle time, TX_CLK
ns
ns
ns
ns
Pulse Duration, TX_CLK high
Pulse Duration, TX_CLK low
Transition time, TX_CLK
140
260
14
26
5
5
1
4
2
3
GMII[x]_TXCLK
4
Figure 5-3. GMII[x]_TXCLK Timing - MII Mode
Table 5-6. Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
(see Figure 5-4)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
MAX
MIN
MAX
tsu(RXD-RX_CLK)
Setup time, RXD[3:0] valid before RX_CLK
1
tsu(RX_DV-RX_CLK) Setup time, RX_DV valid before RX_CLK
tsu(RX_ER-RX_CLK) Setup time, RX_ER valid before RX_CLK
8
8
ns
th(RX_CLK-RXD)
Hold time RXD[3:0] valid after RX_CLK
Hold time RX_DV valid after RX_CLK
Hold time RX_ER valid after RX_CLK
2
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
8
8
ns
1
2
GMII[x]_MRCLK (Input)
GMII[x]_RXD[3:0], GMII[x]_RXDV,
GMII[x]_RXER (Inputs)
Figure 5-4. GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER Timing - MII Mode
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Table 5-7. Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
(see Figure 5-5)
10 Mbps
TYP
100 Mbps
TYP
NO.
PARAMETER
UNIT
MAX
MIN
MAX
MIN
td(TX_CLK-TXD)
Delay time, TX_CLK high to TXD[3:0] valid
Delay time, TX_CLK to TX_EN valid
1
5
25
5
25 ns
td(TX_CLK-TX_EN)
1
GMII[x]_TXCLK (input)
GMII[x]_TXD[3:0],
GMII[x]_TXEN (outputs)
Figure 5-5. GMII[x]_TXD[3:0], GMII[x]_TXEN Timing - MII Mode
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5.4.1.2 Ethernet MAC/Switch RMII Electrical Data and Timing
Table 5-8. Timing Requirements for RMII[x]_REFCLK - RMII Mode
(see Figure 5-6)
NO.
MIN
TYP
MAX
20.001
13
UNIT
ns
1
2
3
tc(REF_CLK)
tw(REF_CLKH)
tw(REF_CLKL)
Cycle time, REF_CLK
19.999
Pulse Duration, REF_CLK high
Pulse Duration, REF_CLK low
7
7
ns
13
ns
1
2
RMII[x]_REFCLK
(Input)
3
Figure 5-6. RMII[x]_REFCLK Timing - RMII Mode
Table 5-9. Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
(see Figure 5-7)
NO.
MIN
TYP
MAX
UNIT
tsu(RXD-REF_CLK)
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
th(REF_CLK-RXD)
Setup time, RXD[1:0] valid before REF_CLK
Setup time, CRS_DV valid before REF_CLK
Setup time, RX_ER valid before REF_CLK
Hold time RXD[1:0] valid after REF_CLK
Hold time, CRS_DV valid after REF_CLK
Hold time, RX_ER valid after REF_CLK
1
4
ns
2
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
2
ns
1
2
RMII[x]_REFCLK (input)
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RXER (inputs)
Figure 5-7. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing - RMII Mode
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Table 5-10. Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
(see Figure 5-8)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
td(REF_CLK-TXD)
td(REF_CLK-TXEN)
tr(TXD)
Delay time, REF_CLK high to TXD[1:0] valid
Delay time, REF_CLK to TXEN valid
Rise time, TXD outputs
1
2
13
ns
2
3
1
1
5
5
ns
ns
tr(TX_EN)
Rise time, TX_EN output
tf(TXD)
Fall time, TXD outputs
tf(TX_EN)
Fall time, TX_EN output
1
RMII[x]_REFCLK (Input)
RMII[x]_TXD[1:0],
RMII[x]_TXEN (Outputs)
3
2
Figure 5-8. RMII[x]_TXD[1:0], RMII[x]_TXEN Timing - RMII Mode
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5.4.1.3 Ethernet MAC/Switch RGMII Electrical Data and Timing
RGMII mode is not supported for OPP50.
Table 5-11. Timing Requirements for RGMII[x]_RCLK - RGMII Mode
(see Figure 5-9)
10 Mbps
TYP
100 Mbps
TYP
1000 Mbps
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
TYP
MAX
1
2
tc(RXC)
Cycle time, RXC
360
440
36
44
7.2
8.8 ns
Pulse duration, RXC
high
tw(RXCH)
160
160
240
16
16
24
3.6
3.6
4.4 ns
3
4
tw(RXCL)
tt(RXC)
Pulse duration, RXC low
Transition time, RXC
240
24
4.4 ns
0.75
0.75
0.75 ns
1
4
2
4
3
RGMII[x]_RCLK
Figure 5-9. RGMII[x]_RCLK Timing - RGMII Mode
Table 5-12. Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
(see Figure 5-10)
10 Mbps
MIN TYP
100 Mbps
MIN TYP
1000 Mbps
MIN TYP
NO.
UNIT
MAX
MAX
MAX
Setup time, RD[3:0] valid
before RXC high/low
tsu(RD-RXC)
tsu(RX_CTL-RXC)
1
1
1
1
1
1
1
1
1
1
1
1
1
ns
Setup time, RX_CTL valid
before RXC high/low
Hold time, RD[3:0] valid
after RXC high/low
th(RXC-RD)
2
3
ns
ns
Hold time, RX_CTL valid
after RXC high/low
th(RXC-RX_CTL)
tt(RD)
Transition time, RD
0.75
0.75
0.75
0.75
0.75
0.75
tt(RX_CTL)
Transition time, RX_CTL
RGMII[x]_RCLK(A)
1
1st Half-byte
2
2nd Half-byte
RGMII[x]_RD[3:0](B)
RGMII[x]_RCTL(B)
RGRXD[3:0]
RXDV
RGRXD[7:4]
3
A. RGMII[x]_RCLK must be externally delayed relative to the RGMII[x]_RD[3:0] and RGMII[x]_RCTL signals to meet the
respective timing requirements.
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the
rising edge of RGMII[x]_RCLK and data bits 7-4 on the falling edge of RGMII[x]_RCLK. Similarly, RGMII[x]_RCTL
carries RXDV on rising edge of RGMII[x]_RCLK and RXERR on falling edge of RGMII[x]_RCLK.
Figure 5-10. RGMII[x]_RD[3:0], RGMII[x]_RCTL Timing - RGMII Mode
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Table 5-13. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
(see Figure 5-11)
10 Mbps
TYP
100 Mbps
TYP
1000 Mbps
TYP
NO.
PARAMETER
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
1
2
tc(TXC)
Cycle time, TXC
360
440
36
44
7.2
8.8 ns
Pulse duration, TXC
high
tw(TXCH)
160
160
240
16
16
24
3.6
3.6
4.4 ns
3
4
tw(TXCL)
tt(TXC)
Pulse duration, TXC low
Transition time, TXC
240
24
4.4 ns
0.75
0.75
0.75 ns
1
4
2
4
3
RGMII[x]_TCLK
Figure 5-11. RGMII[x]_TCLK Timing - RGMII Mode
Table 5-14. Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
(see Figure 5-12)
10 Mbps
MIN TYP
100 Mbps
MIN TYP
1000 Mbps
MIN TYP
NO.
PARAMETER
UNIT
ns
MAX
0.5
MAX
0.5
MAX
0.5
tsk(TD-TXC)
TD to TXC output skew
TX_CTL to TXC output skew
Transition time, TD
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
1
tsk(TX_CTL-TXC)
0.5
0.5
0.5
tt(TD)
0.75
0.75
0.75
0.75
0.75
0.75
2
ns
tt(TX_CTL)
Transition time, TX_CTL
RGMII[x]_TCLK(A)
1
1
2
RGMII[x]_TD[3:0](B)
RGMII[x]_TCTL(B)
1st Half-byte
2nd Half-byte
TXERR
TXEN
A. The Ethernet MAC/Switch implemented in the AM335x device supports internal delay mode, but timing closure was
not performed for this mode of operation. Therefore, the AM335x device does not support internal delay mode.
B. Data and control information is transmitted using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on
the rising edge of RGMII[x]_TCLK and data bits 7-4 on the falling edge of RGMII[x]_TCLK. Similarly, RGMII[x]_TCTL
carries TXEN on rising edge of RGMII[x]_TCLK and TXERR of falling edge of RGMII[x]_TCLK.
Figure 5-12. RGMII[x]_TD[3:0], RGMII[x]_TCTL Timing - RGMII Mode
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5.5 External Memory Interfaces
The device includes the following external memory interfaces:
•
•
General-purpose memory controller (GPMC)
mDDR(LPDDR)/DDR2/DDR3 Memory Interface (EMIF)
5.5.1 General-Purpose Memory Controller (GPMC)
NOTE
For more information, see the Memory Subsystem/General-Purpose Memory Controller
section of the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference
Manual (literature number SPRUH73).
The GPMC is the unified memory controller used to interface external memory devices such as:
•
•
•
Asynchronous SRAM-like memories and ASIC devices
Asynchronous page mode and synchronous burst NOR flash
NAND flash
5.5.1.1 GPMC/NOR Flash—Synchronous Mode
Synchronous mode is not supported for OPP50.
Table 5-16 and Table 5-17 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-13 through Figure 5-17).
Table 5-15. GPMC/NOR Flash Timing Conditions—Synchronous Mode
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1
1
5
5
ns
ns
Output Condition
CLOAD
Output load capacitance
3
30
pF
Table 5-16. GPMC/NOR Flash Timing Requirements—Synchronous Mode
OPP100
NO.
UNIT
MIN
MAX
F12 tsu(dV-clkH)
Setup time, input data gpmc_ad[15:0] valid before output clock gpmc_clk
high
3.2
ns
F13 th(clkH-dV)
Hold time, input data gpmc_ad[15:0] valid after output clock gpmc_clk high
Setup time, input wait gpmc_wait[x](1) valid before output clock gpmc_clk
high
2.5
3.2
ns
ns
F21 tsu(waitV-clkH)
F22 th(clkH-waitV)
Hold time, input wait gpmc_wait[x](1) valid after output clock gpmc_clk high
2.5
ns
(1) In gpmc_wait[x], x is equal to 0 or 1.
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UNIT
Table 5-17. GPMC/NOR Flash Switching Characteristics—Synchronous Mode(2)
NO.
PARAMETER
OPP100
MIN
MAX
F0
F1
F1
1 / tc(clk)
tw(clkH)
tw(clkL)
tdc(clk)
tJ(clk)
Frequency(15), output clock gpmc_clk
Typical pulse duration, output clock gpmc_clk high
Typical pulse duration, output clock gpmc_clk low
Duty cycle error, output clock gpmc_clk
Jitter standard deviation(16), output clock gpmc_clk
Rise time, output clock gpmc_clk
100
0.5P(12)
0.5P(12)
MHz
ns
ns
ps
ps
ns
ns
ns
ns
ns
0.5P(12)
0.5P(12)
–500
500
33.33
tR(clk)
2
tF(clk)
Fall time, output clock gpmc_clk
2
tR(do)
Rise time, output data gpmc_ad[15:0]
Fall time, output data gpmc_ad[15:0]
2
2
tF(do)
F2
F3
F4
F5
F6
td(clkH-csnV)
Delay time, output clock gpmc_clk rising edge to output chip
select gpmc_csn[x](11) transition
F(6) – 2.2
E(5) – 2.2
B(2) – 4.5
–2.3
F(6) + 4.5
td(clkH-csnIV)
td(aV-clk)
td(clkH-aIV)
td(be[x]nV-clk)
Delay time, output clock gpmc_clk rising edge to output chip
select gpmc_csn[x](11) invalid
E(5) + 4.5
B(2) + 2.3
4.5
ns
ns
ns
ns
Delay time, output address gpmc_a[27:1] valid to output clock
gpmc_clk first edge
Delay time, output clock gpmc_clk rising edge to output address
gpmc_a[27:1] invalid
Delay time, output lower byte enable/command latch enable
gpmc_be0n_cle, output upper byte enable gpmc_be1n valid to
output clock gpmc_clk first edge
B(2) – 1.9
B(2) + 2.3
F7
td(clkH-be[x]nIV)
Delay time, output clock gpmc_clk rising edge to output lower
byte enable/command latch enable gpmc_be0n_cle, output
upper byte enable gpmc_be1n invalid
D(4) – 2.3
D(4) + 1.9
ns
F8
td(clkH-advn)
td(clkH-advnIV)
td(clkH-oen)
td(clkH-oenIV)
td(clkH-wen)
td(clkH-do)
Delay time, output clock gpmc_clk rising edge to output address
valid/address latch enable gpmc_advn_ale transition
G(7) + 2.3
D(4) – 2.3
H(8) – 2.3
E(5) – 2.3
I(9) – 2.3
G(7) + 4.5
D(4) + 3.5
H(8) + 3.5
E(5) + 3.5
I(9) + 4.5
ns
ns
ns
ns
ns
ns
ns
F9
Delay time, output clock gpmc_clk rising edge to output address
valid/address latch enable gpmc_advn_ale invalid
F10
F11
F14
F15
F17
F18
Delay time, output clock gpmc_clk rising edge to output enable
gpmc_oen transition
Delay time, output clock gpmc_clk rising edge to output enable
gpmc_oen invalid
Delay time, output clock gpmc_clk rising edge to output write
enable gpmc_wen transition
Delay time, output clock gpmc_clk rising edge to output data
gpmc_ad[15:0] transition
J(10) – 2.3
J(10) – 2.3
J(10) + 1.9
J(10) + 1.9
td(clkH-be[x]n)
tw(csnV)
Delay time, output clock gpmc_clk rising edge to output lower
byte enable/command latch enable gpmc_be0n_cle transition
Pulse duration, output chip select gpmc_csn[x](11)
low
Read
Write
Read
Write
A(1)
A(1)
C(3)
C(3)
ns
ns
ns
ns
F19
F20
tw(be[x]nV)
Pulse duration, output lower byte enable/command
latch enable gpmc_be0n_cle, output upper byte
enable gpmc_be1n low
tw(advnV)
Pulse duration, output address valid/address latch
enable gpmc_advn_ale low
Read
Write
K(13)
K(13)
ns
ns
(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
With n being the page burst access number.
(2) B = ClkActivationTime * GPMC_FCLK(14)
(14)
(3) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: C = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst write: C = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
With n being the page burst access number.
(4) For single read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
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For burst read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst write: D = (WrCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
(5) For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
(6) For csn falling edge (CS activated):
–
Case GpmcFCLKDivider = 0:
–
F = 0.5 * CSExtraDelay * GPMC_FCLK(14)
–
Case GpmcFCLKDivider = 1:
–
F = 0.5 * CSExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime
are even)
–
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK(14) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
F = 0.5 * CSExtraDelay * GPMC_FCLK(14) if ((CSOnTime – ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK(14) if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)
F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK(14) if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
(7) For ADV falling edge (ADV activated):
–
Case GpmcFCLKDivider = 0:
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14)
–
Case GpmcFCLKDivider = 1:
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)
–
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if ((ADVOnTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
–
Case GpmcFCLKDivider = 0:
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14)
–
Case GpmcFCLKDivider = 1:
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
–
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
–
Case GpmcFCLKDivider = 0:
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14)
–
Case GpmcFCLKDivider = 1:
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
–
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)
(8) For OE falling edge (OE activated) / IO DIR rising edge (Data Bus input direction):
–
Case GpmcFCLKDivider = 0:
–
H = 0.5 * OEExtraDelay * GPMC_FCLK(14)
–
Case GpmcFCLKDivider = 1:
–
H = 0.5 * OEExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime
are even)
–
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
H = 0.5 * OEExtraDelay * GPMC_FCLK(14) if ((OEOnTime – ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)
H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)
For OE rising edge (OE deactivated):
–
Case GpmcFCLKDivider = 0:
–
H = 0.5 * OEExtraDelay * GPMC_FCLK(14)
–
Case GpmcFCLKDivider = 1:
–
H = 0.5 * OEExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime
are even)
–
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) otherwise
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–
Case GpmcFCLKDivider = 2:
–
–
–
H = 0.5 * OEExtraDelay * GPMC_FCLK(14) if ((OEOffTime – ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)
H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)
(9) For WE falling edge (WE activated):
–
Case GpmcFCLKDivider = 0:
–
I = 0.5 * WEExtraDelay * GPMC_FCLK(14)
–
Case GpmcFCLKDivider = 1:
–
I = 0.5 * WEExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime
are even)
–
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
I = 0.5 * WEExtraDelay * GPMC_FCLK(14) if ((WEOnTime – ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)
I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)
For WE rising edge (WE deactivated):
–
Case GpmcFCLKDivider = 0:
I = 0.5 * WEExtraDelay * GPMC_FCLK
(14)
–
–
Case GpmcFCLKDivider = 1:
–
I = 0.5 * WEExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime
are even)
–
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
I = 0.5 * WEExtraDelay * GPMC_FCLK(14) if ((WEOffTime – ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)
I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)
(10) J = GPMC_FCLK(14)
(11) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
(12) P = gpmc_clk period in ns
(13) For read: K = (ADVRdOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For write: K = (ADVWrOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.
(16) The jitter probability density can be approximated by a Gaussian function.
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csn[x]
gpmc_a[10:1]
F4
F6
Valid Address
F19
F7
gpmc_be0n_cle
gpmc_be1n
F19
F6
F8
F8
F20
F9
gpmc_advn_ale
gpmc_oen
F10
F11
F13
F12
D 0
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-13. GPMC/NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0)
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F1
F0
F1
gpmc_clk
F2
F3
gpmc_csn[x]
gpmc_a[10:1]
gpmc_be0n_cle
gpmc_be1n
F4
F6
Valid Address
F7
F7
F9
F6
F8
F8
gpmc_advn_ale
gpmc_oen
F10
F11
F13
F13
F12
D 0
F22
F12
D 3
gpmc_ad[15:0]
gpmc_wait[x]
D 1
D 2
F21
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-14. GPMC/NOR Flash—Synchronous Burst Read—4x16-bit (GpmcFCLKDivider = 0)
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F1
F1
F0
gpmc_clk
F2
F3
gpmc_csn[x]
gpmc_a[10:1]
F4
F6
Valid Address
F17
F17
F17
F17
gpmc_be0n_cle
F17
F17
gpmc_be1n
gpmc_advn_ale
gpmc_wen
F6
F8
F8
F9
F14
F14
F15
D 1
F15
D 2
F15
gpmc_ad[15:0]
gpmc_wait[x]
D 0
D 3
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-15. GPMC/NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0)
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F1
F0
F1
gpmc_clk
F2
F3
gpmc_csn[x]
F6
F7
gpmc_be0n_cle
Valid
F6
F7
gpmc_be1n
Valid
F4
gpmc_a[27:17]
Address (MSB)
F5
F12
F13
F4
F12
gpmc_ad[15:0]
gpmc_advn_ale
gpmc_oen
Address (LSB)
D0
D1
D2
D3
F8
F8
F9
F10
F11
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-16. GPMC/Multiplexed NOR Flash—Synchronous Burst Read
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csn[x]
F4
F6
F6
gpmc_a[27:17]
Address (MSB)
F17
F17
F17
F17
gpmc_be1n
gpmc_be0n_cle
gpmc_advn_ale
F17
F17
F8
F8
F20
F9
F14
F14
gpmc_wen
F15
D 1
F15
D 2
F15
gpmc_ad[15:0]
Address (LSB)
D 0
D 3
F22
F21
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-17. GPMC/Multiplexed NOR Flash—Synchronous Burst Write
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5.5.1.2 GPMC/NOR Flash—Asynchronous Mode
Table 5-19 and Table 5-20 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-18 through Figure 5-23).
Table 5-18. GPMC/NOR Flash Timing Conditions—Asynchronous Mode
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1
1
5
5
ns
ns
Output Condition
CLOAD
Output load capacitance
3
30
pF
Table 5-19. GPMC/NOR Flash Internal Timing Parameters—Asynchronous Mode(1)(2)
OPP100
MIN
OPP50
MIN
NO.
UNIT
MAX
MAX
FI1 Delay time, output data gpmc_ad[15:0] generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
ns
FI2 Delay time, input data gpmc_ad[15:0] capture from internal functional clock
GPMC_FCLK(3)
4
6.5
6.5
6.5
6.5
4
6.5
6.5
6.5
6.5
ns
ns
ns
ns
ns
FI3 Delay time, output chip select gpmc_csn[x] generation from internal functional
clock GPMC_FCLK(3)
FI4 Delay time, output address gpmc_a[27:1] generation from internal functional clock
GPMC_FCLK(3)
FI5 Delay time, output address gpmc_a[27:1] valid from internal functional clock
GPMC_FCLK(3)
FI6 Delay time, output lower-byte enable/command latch enable gpmc_be0n_cle,
output upper-byte enable gpmc_be1n generation from internal functional clock
GPMC_FCLK(3)
FI7 Delay time, output enable gpmc_oen generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
6.5
6.5
ns
ns
ps
FI8 Delay time, output write enable gpmc_wen generation from internal functional
clock GPMC_FCLK(3)
FI9 Skew, internal functional clock GPMC_FCLK(3)
100
100
(1) The internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.
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NO.
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Table 5-20. GPMC/NOR Flash Timing Requirements—Asynchronous Mode
OPP100
MIN
OPP50
MIN
UNIT
MAX
H(5)
P(4)
MAX
H(5)
P(4)
FA5(1) tacc(d)
FA20(2) tacc1-pgmode(d)
FA21(3) tacc2-pgmode(d)
Data access time
ns
ns
ns
Page mode successive data access time
Page mode first data access time
H(5)
H(5)
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock
edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock
edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
(4) P = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(6)
(5) H = AccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(6)
(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
Table 5-21. GPMC/NOR Flash Switching Characteristics—Asynchronous Mode
OPP100
MIN
OPP50
MIN
NO.
PARAMETER
UNIT
MAX
2
MAX
2
tR(d)
Rise time, output data gpmc_ad[15:0]
Fall time, output data gpmc_ad[15:0]
ns
ns
ns
tF(d)
2
2
FA0
tw(be[x]nV)
Pulse duration, output lower-byte
enable/command latch enable
gpmc_be0n_cle, output upper-byte
enable gpmc_be1n valid time
Read
Write
N(12)
N(12)
N(12)
N(12)
FA1
FA3
tw(csnV)
Pulse duration, output chip select
gpmc_csn[x](13) low
Read
Write
Read
Write
A(1)
A(1)
B(2) + 2.0
B(2) + 2.0
A(1)
A(1)
B(2) + 2.0
B(2) + 2.0
ns
ns
td(csnV-advnIV)
Delay time, output chip select
gpmc_csn[x](13) valid to output
address valid/address latch enable
gpmc_advn_ale invalid
B(2) – 0.2
B(2) – 0.2
B(2) – 0.2
B(2) – 0.2
FA4
FA9
td(csnV-oenIV)
Delay time, output chip select gpmc_csn[x](13)
valid to output enable gpmc_oen invalid (Single
read)
C(3) – 0.2
C(3) + 2.0
C(3) – 0.2
C(3) + 2.0
ns
td(aV-csnV)
Delay time, output address gpmc_a[27:1] valid
to output chip select gpmc_csn[x](13) valid
J(9) – 0.2
J(9) – 0.2
J(9) + 2.0
J(9) + 2.0
J(9) – 0.2
J(9) – 0.2
J(9) + 2.0
J(9) + 2.0
ns
ns
FA10 td(be[x]nV-csnV)
Delay time, output lower-byte enable/command
latch enable gpmc_be0n_cle, output upper-byte
enable gpmc_be1n valid to output chip select
gpmc_csn[x](13) valid
FA12 td(csnV-advnV)
Delay time, output chip select gpmc_csn[x](13)
valid to output address valid/address latch
enable gpmc_advn_ale valid
K(10) – 0.2 K(10) + 2.0 K(10) – 0.2 K(10) + 2.0
ns
FA13 td(csnV-oenV)
FA16 tw(aIV)
Delay time, output chip select gpmc_csn[x](13)
valid to output enable gpmc_oen valid
L(11) – 0.2 L(11) + 2.0
G(7)
L
(11) – 0.2 L(11) + 2.0
G(7)
ns
ns
ns
Pulse durationm output address gpmc_a[26:1]
invalid between 2 successive R/W accesses
Delay time, output chip select gpmc_csn[x](13)
valid to output enable gpmc_oen invalid (Burst
read)
FA18 td(csnV-oenIV)
I(8) – 0.2
I(8) + 2.0
I(8) – 0.2
I(8) + 2.0
FA20 tw(aV)
Pulse duration, output address gpmc_a[27:1]
valid – 2nd, 3rd, and 4th accesses
Delay time, output chip select gpmc_csn[x](13)
valid to output write enable gpmc_wen valid
D(4)
D(4)
ns
ns
FA25 td(csnV-wenV)
E(5) – 0.2
E(5) + 2.0
E(5) – 0.2
E(5) + 2.0
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Table 5-21. GPMC/NOR Flash Switching Characteristics—Asynchronous Mode (continued)
OPP100
OPP50
MIN
F(6) – 0.2
NO.
PARAMETER
UNIT
MIN
MAX
MAX
F(6) + 2.0
FA27 td(csnV-wenIV)
Delay time, output chip select gpmc_csn[x](13)
valid to output write enable gpmc_wen invalid
F(6) – 0.2
F(6) + 2.0
ns
FA28 td(wenV-dV)
FA29 td(dV-csnV)
FA37 td(oenV-aIV)
Delay time, output write enable gpmc_ wen
valid to output data gpmc_ad[15:0] valid
2.0
2.0
J(9) + 2.0
2.0
ns
ns
ns
Delay time, output data gpmc_ad[15:0] valid to
output chip select gpmc_csn[x](13) valid
J(9) – 0.2
J(9) + 2.0
2.0
J(9) – 0.2
Delay time, output enable gpmc_oen valid to
output address gpmc_ad[15:0] phase end
(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For single write: A = (CSWrOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
with n being the page burst access number
(2) For reading: B = ((ADVRdOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) *
GPMC_FCLK(14)
For writing: B = ((ADVWrOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) *
GPMC_FCLK(14)
(3) C = ((OEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(4) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(14)
(5) E = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(6) F = ((WEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(7) G = Cycle2CycleDelay * GPMC_FCLK(14)
(8) I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) *
GPMC_FCLK(14)
(9) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK(14)
(10) K = ((ADVOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(11) L = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(12) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst read: N = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst write: N = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
(13) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
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GPMC_FCLK
gpmc_clk
FA5
FA1
gpmc_csn[x]
gpmc_a[10:1]
FA9
Valid Address
FA0
FA10
gpmc_be0n_cle
gpmc_be1n
Valid
FA0
Valid
FA10
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen
Data IN 0
Data IN 0
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-18. GPMC/NOR Flash—Asynchronous Read—Single Word
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GPMC_FCLK
gpmc_clk
FA5
FA5
FA1
FA1
gpmc_csn[x]
FA16
FA9
FA9
gpmc_a[10:1]
Address 0
FA0
Address 1
FA0
FA10
FA10
FA10
gpmc_be0n_cle
gpmc_be1n
Valid
FA0
Valid
FA0
Valid
Valid
FA10
FA3
FA3
FA12
FA12
gpmc_advn_ale
FA4
FA4
FA13
FA13
gpmc_oen
Data Upper
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-19. GPMC/NOR Flash—Asynchronous Read—32-bit
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GPMC_FCLK
gpmc_clk
FA20
FA20
FA20
Add1
FA21
FA1
gpmc_csn[x]
gpmc_a[10:1]
FA9
Add0
Add2
Add3
Add4
FA0
FA10
FA10
gpmc_be0n_cle
FA0
gpmc_be1n
FA12
gpmc_advn_ale
FA18
FA13
gpmc_oen
D3
D0
D1
D2
D3
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in
number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input
page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside
AccessTime register bits field.
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in
number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally
sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address
phases for successive input page data (excluding first input page data). FA20 value must be stored in
PageBurstAccessTime register bits field.
D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-20. GPMC/NOR Flash—Asynchronous Read—Page Mode 4x16-bit
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gpmc_fclk
gpmc_clk
FA1
gpmc_csn[x]
FA9
gpmc_a[10:1]
Valid Address
FA0
FA10
gpmc_be0n_cle
FA0
FA10
gpmc_be1n
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
FA29
gpmc_ad[15:0]
Data OUT
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-21. GPMC/NOR Flash—Asynchronous Write—Single Word
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GPMC_FCLK
gpmc_clk
FA1
FA5
gpmc_csn[x]
FA9
Address (MSB)
FA0
gpmc_a[27:17]
FA10
FA10
gpmc_be0n_cle
gpmc_be1n
Valid
FA0
Valid
FA3
FA12
gpmc_advn_ale
gpmc_oen
FA4
FA13
FA29
FA37
Data IN
Data IN
Address (LSB)
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-22. GPMC / Multiplexed NOR Flash—Asynchronous Read—Single Word
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gpmc_fclk
gpmc_clk
FA1
gpmc_csn[x]
FA9
gpmc_a[27:17]
Address (MSB)
FA0
FA10
gpmc_be0n_cle
FA0
FA10
gpmc_be1n
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
gpmc_ad[15:0]
gpmc_wait[x]
FA29
Valid Address (LSB)
FA28
Data OUT
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-23. GPMC/Multiplexed NOR Flash—Asynchronous Write—Single Word
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5.5.1.3 GPMC/NAND Flash—Asynchronous Mode
Table 5-23 and Table 5-24 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-24 through Figure 5-27).
Table 5-22. GPMC/NAND Flash Timing Conditions—Asynchronous Mode
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1
1
5
5
ns
ns
Output Condition
CLOAD
Output load capacitance
3
30
pF
Table 5-23. GPMC/NAND Flash Internal Timing Parameters—Asynchronous Mode(1)(2)
OPP100
MIN
OPP50
MIN
NO.
UNIT
MAX
MAX
GNFI1 Delay time, output data gpmc_ad[15:0] generation from internal
functional clock GPMC_FCLK(3)
6.5
6.5
ns
GNFI2 Delay time, input data gpmc_ad[15:0] capture from internal functional
clock GPMC_FCLK(3)
4.0
6.5
6.5
6.5
4.0
6.5
6.5
6.5
ns
ns
ns
ns
GNFI3 Delay time, output chip select gpmc_csn[x] generation from internal
functional clock GPMC_FCLK(3)
GNFI4 Delay time, output address valid/address latch enable gpmc_advn_ale
generation from internal functional clock GPMC_FCLK(3)
GNFI5 Delay time, output lower-byte enable/command latch enable
gpmc_be0n_cle generation from internal functional clock
GPMC_FCLK(3)
GNFI6 Delay time, output enable gpmc_oen generation from internal functional
clock GPMC_FCLK(3)
6.5
6.5
6.5
6.5
ns
ns
ps
GNFI7 Delay time, output write enable gpmc_wen generation from internal
functional clock GPMC_FCLK(3)
GNFI8 Skew, functional clock GPMC_FCLK(3)
100
100
(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.
Table 5-24. GPMC/NAND Flash Timing Requirements—Asynchronous Mode
OPP100
MIN
OPP50
MIN
NO.
UNIT
MAX
J(2)
MAX
J(2)
GNF12(1) tacc(d)
Access time, input data gpmc_ad[15:0]
ns
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(3)
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
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UNIT
Table 5-25. GPMC/NAND Flash Switching Characteristics—Asynchronous Mode
OPP100
MIN
OPP50
MIN
NO.
PARAMETER
MAX
MAX
tR(d)
tF(d)
Rise time, output data gpmc_ad[15:0]
Fall time, output data gpmc_ad[15:0]
2
2
2
ns
ns
ns
2
GNF0 tw(wenV)
Pulse duration, output write enable gpmc_wen
valid
A(1)
A(1)
GNF1 td(csnV-wenV)
GNF2 tw(cleH-wenV)
Delay time, output chip select gpmc_csn[x](13)
valid to output write enable gpmc_wen valid
B(2) – 0.2
B(2) + 2.0
B(2) – 0.2
B(2) + 2.0
ns
ns
Delay time, output lower-byte enable/command
latch enable gpmc_be0n_cle high to output write
enable gpmc_wen valid
C(3) – 0.2 C(3) + 2.0
D(4) – 0.2 D(4) + 2.0
C(3) – 0.2 C(3) + 2.0
D(4) – 0.2 D(4) + 2.0
GNF3 tw(wenV-dV)
GNF4 tw(wenIV-dIV)
GNF5 tw(wenIV-cleIV)
Delay time, output data gpmc_ad[15:0] valid to
output write enable gpmc_wen valid
ns
ns
ns
Delay time, output write enable gpmc_wen
invalid to output data gpmc_ad[15:0] invalid
E(5) – 0.2
F(6) – 0.2
E(5) + 2.0
F(6) + 2.0
E(5) – 0.2
F(6) – 0.2
E(5) + 2.0
F(6) + 2.0
Delay time, output write enable gpmc_wen
invalid to output lower-byte enable/command
latch enable gpmc_be0n_cle invalid
GNF6 tw(wenIV-csnIV)
GNF7 tw(aleH-wenV)
GNF8 tw(wenIV-aleIV)
Delay time, output write enable gpmc_wen
invalid to output chip select gpmc_csn[x](13)
invalid
G(7) – 0.2 G(7) + 2.0 G(7) – 0.2 G(7) + 2.0
ns
ns
ns
Delay time, output address valid/address latch
enable gpmc_advn_ale high to output write
enable gpmc_wen valid
C(3) – 0.2 C(3) + 2.0
C(3) – 0.2 C(3) + 2.0
Delay time, output write enable gpmc_wen
invalid to output address valid/address latch
enable gpmc_advn_ale invalid
F(6) – 0.2
F(6) + 2.0
F(6) – 0.2
F(6) + 2.0
GNF9 tc(wen)
Cycle time, write
Delay time, output chip select gpmc_csn[x](13)
valid to output enable gpmc_oen valid
H(8)
I(9) + 2.0
H(8)
I(9) + 2.0
ns
ns
GNF10 td(csnV-oenV)
I(9) – 0.2
I(9) – 0.2
GNF13 tw(oenV)
GNF14 tc(oen)
Pulse duration, output enable gpmc_oen valid
Cycle time, read
K(10)
K(10)
ns
ns
ns
L(11)
L(11)
GNF15 tw(oenIV-csnIV)
Delay time, output enable gpmc_oen invalid to
output chip select gpmc_csn[x](13) invalid
M(12) – 0.2 M(12) + 2.0 M(12) – 0.2 M(12) + 2.0
(1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
(2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK(14)
(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay) * GPMC_FCLK(14)
(5) E = ((WrCycleTime – WEOffTime) * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay) * GPMC_FCLK(14)
(6) F = ((ADVWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay)) * GPMC_FCLK(14)
(7) G = ((CSWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay)) * GPMC_FCLK(14)
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK(14)
(9) I = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK(14)
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK(14)
(12) M = ((CSRdOffTime – OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay)) * GPMC_FCLK(14)
(13) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
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GPMC_FCLK
GNF1
GNF2
GNF6
GNF5
gpmc_csn[x]
gpmc_be0n_cle
gpmc_advn_ale
gpmc_oen
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
Command
(1) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
Figure 5-24. GPMC/NAND Flash—Command Latch Cycle
GPMC_FCLK
gpmc_csn[x]
GNF1
GNF7
GNF6
gpmc_be0n_cle
gpmc_advn_ale
gpmc_oen
GNF8
GNF9
GNF0
gpmc_wen
GNF3
GNF4
Address
gpmc_ad[15:0]
(1) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
Figure 5-25. GPMC/NAND Flash—Address Latch Cycle
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GPMC_FCLK
GNF12
GNF10
GNF15
gpmc_csn[x]
gpmc_be0n_cle
gpmc_advn_ale
GNF14
GNF13
gpmc_oen
gpmc_ad[15:0]
DATA
gpmc_wait[x]
(1) GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active
functional clock edge. GNF12 value must be stored inside AccessTime register bits field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-26. GPMC/NAND Flash—Data Read Cycle
GPMC_FCLK
GNF1
GNF6
gpmc_csn[x]
gpmc_be0n_cle
gpmc_advn_ale
gpmc_oen
GNF9
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
DATA
(1) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
Figure 5-27. GPMC / NAND Flash—Data Write Cycle
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5.5.2 mDDR(LPDDR)/DDR2/DDR3 Memory Interface
The device has a dedicated interface to mDDR(LPDDR), DDR2, and DDR3 SDRAM. It supports JEDEC
standard compliant mDDR(LPDDR), DDR2, and DDR3 SDRAM devices with a 16-bit data path to external
SDRAM memory.
For more details on the mDDR(LPDDR)/DDR2/DDR3 memory interface, see the EMIF section of the
AM335x Sitara ARM Cortex A-8 Microprocessors (MPUs) Technical Reference Manual (literature number
SPRUH73).
5.5.2.1 mDDR(LPDDR) Routing Guidelines
It is common to find industry references to mobile double data rate (mDDR) when discussing JEDEC
defined low-power double-data rate (LPDDR) memory devices. The following guidelines use LPDDR when
referencing JEDEC defined low-power double-data rate memory devices.
5.5.2.1.1 Board Designs
TI only supports board designs that follow the guidelines outlined in this document. The switching
characteristics and the timing diagram for the LPDDR memory interface are shown in Table 5-26 and
Figure 5-28.
Table 5-26. Switching Characteristics Over Recommended Operating Conditions for LPDDR Memory
Interface
NO.
PARAMETER
MIN
MAX
UNIT
(1)
1
tc(DDR_CK/DDR_CKn) Cycle time, DDR_CK/DDR_CKn
5
ns
(1) The JEDEC JESD209B specification only defines the maximum clock period for LPDDR333 and faster speed bin LPDDR memory
devices. To determine the maximum clock period, see the respective LPDDR memory data sheet.
1
DDR_CK
DDR_CKn
Figure 5-28. LPDDR Memory Interface Clock Timing
5.5.2.1.2 LPDDR Interface
This section provides the timing specification for the LPDDR interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable LPDDR memory system without the
need for a complex timing closure process. For more information regarding the guidelines for using this
LPDDR specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification
application report (literature number SPRAAV0). This application report provides generic guidelines and
approach. All the specifications provided in the data manual take precedence over the generic guidelines
and must be adhered to for a reliable LPDDR interface operation.
5.5.2.1.2.1 LPDDR Interface Schematic
Figure 5-29 shows the schematic connections for 16-bit interface on AM335x device using one x16
LPDDR device. The AM335x LPDDR memory interface only supports 16-bit wide mode of operation. The
AM335x° device can only source one load connected to the DQS[x] and DQ[x] net class signals and one
load connected to the CK and ADDR_CTRL net class signals. For more information related to net classes,
see Section 5.5.2.1.2.8.
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16-Bit LPDDR
Device
AM335x
DDR_D0
DQ0
DDR_D7
DQ7
LDM
LDQS
DDR_DQM0
DDR_DQS0
NC(A)
DDR_DQSn0
DDR_D8
DQ8
DDR_D15
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DQ15
UDM
UDQS
NC(A)
NC
DDR_ODT
DDR_BA0
DDR_BA1
DDR_BA2
T
BA0
BA1
T
NC
DDR_A0
T
A0
DDR_A15
T
T
A15
CS
DDR_CSn0
DDR_CASn
DDR_RASn
DDR_WEn
DDR_CKE
DDR_CK
CAS
RAS
T
T
T
T
T
T
WE
CKE
CK
CK
DDR_CKn
DDR_VREF
NC
DDR_RESETn
DDR_VTP
NC
49.9 Ω
( 1%, 20 mW)
A. Enable internal weak pulldown on these pins. For details, see the EMIF section of the AM335x Sitara ARM Cortex A-8
Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73).
B. For all the termination requirements, see Section 5.5.2.1.2.9.
Figure 5-29. 16-Bit LPDDR Interface Using One 16-Bit LPDDR Device
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5.5.2.1.2.2 Compatible JEDEC LPDDR Devices
Table 5-27 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface.
Generally, the LPDDR interface is compatible with x16 LPDDR400 speed grade LPDDR devices.
Table 5-27. Compatible JEDEC LPDDR Devices (Per Interface)(1)
NO.
1
PARAMETER
JEDEC LPDDR device speed grade
MIN
LPDDR400
x16
MAX
UNIT
2
JEDEC LPDDR device bit width
JEDEC LPDDR device count
x16
1
Bits
3
Devices
4
JEDEC LPDDR device terminal count
60 Terminals
(1) If the LPDDR interface is operated with a clock frequency less than 200 MHz, lower-speed grade LPDDR devices may be used if the
minimum clock period specified for the LPDDR device is less than or equal to the minimum clock period selected for the AM335x
LPDDR interface.
5.5.2.1.2.3 PCB Stackup
The minimum stackup required for routing the AM335x device is a four-layer stackup as shown in Table 5-
28. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal
integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
Table 5-28. Minimum PCB Stackup(1)
LAYER
TYPE
Signal
Plane
Plane
Signal
DESCRIPTION
Top signal routing
Ground
1
2
3
4
Split Power Plane
Bottom signal routing
(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these
signals on layer 1 which requires some to be routed on layer 4. When this is done, the signal routes on layer 4 should not cross splits in
the power plane.
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Complete stackup specifications are provided in Table 5-29.
Table 5-29. PCB Stackup Specifications(1)
NO.
1
PARAMETER
MIN
4
TYP
MAX
UNIT
PCB routing/plane layers
Signal routing layers
2
2
3
Full ground layers under LPDDR routing region
1
4
Number of ground plane cuts allowed within LPDDR routing region
Full VDDS_DDR power reference layers under LPDDR routing region
0
0
5
1
6
Number of layers between LPDDR routing layer and reference ground
plane
7
8
9
PCB routing feature size
PCB trace width, w
PCB BGA escape via pad size(2)
4
4
mils
mils
mils
mils
18
10
0.5
0.4
20
10 PCB BGA escape via hole size(2)
ZCZ package
ZCE package
11 AM335x BGA pad size
mm
13 Single-ended impedance, Zo(3)
14 Impedance control(4)(5)
50
75
ohms
ohms
Zo-5
Zo
Zo+5
(1) For the LPDDR device BGA pad size, see the LPDDR device manufacturer documentation.
(2) A 20/10 via may be used if enough power routing resources are available. An 18/10 via allows for more flexible power routing to the
AM335xƒ device.
(3) Zo is the nominal singled-ended impedance selected for the PCB.
(4) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo
defined by the single-ended impedance parameter.
(5) Tighter impedance control is required to ensure flight time skew is minimal.
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5.5.2.1.2.4 Placement
Figure 5-30 shows the required placement for the LPDDR devices. The dimensions for this figure are
defined in Table 5-30. The placement does not restrict the side of the PCB on which the devices are
mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for
proper routing space. For single-memory LPDDR systems, the second LPDDR device is omitted from the
placement.
X
A1
Y
OFFSET
LPDDR
Y
Device
Y
OFFSET
AM335x
A1
Recommended LPDDR
Device Orientation
Figure 5-30. AM335x Device and LPDDR Device Placement
Table 5-30. Placement Specifications(1)
NO.
1
PARAMETER
MIN
MAX
1750
1280
650
UNIT
mils
mils
mils
w
X(2)(3)
Y(2)(3)
Y Offset(2)(3)(4)
2
3
4
Clearance from non-LPDDR signal to LPDDR keepout region(5)(6)
4
(1) LPDDR keepout region to encompass entire LPDDR routing area.
(2) For dimension definitions, see Figure 5-30.
(3) Measurements from center of AM335x device to center of LPDDR device.
(4) For single-memory systems, it is recommended that Y offset be as small as possible.
(5) w is defined as the signal trace width.
(6) Non-LPDDR signals allowed within LPDDR keepout region provided they are separated from LPDDR routing layers by a ground plane.
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5.5.2.1.2.5 LPDDR Keepout Region
The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR
keepout region is defined for this purpose and is shown in Figure 5-31. This region should encompass all
LPDDR circuitry and the region size varies with component placement and LPDDR routing. Additional
clearances required for the keepout region are shown in Table 5-30. Non-LPDDR signals should not be
routed on the same signal layer as LPDDR signals within the LPDDR keepout region. Non-LPDDR signals
may be routed in the region provided they are routed on layers separated from LPDDR signal layers by a
ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this
region. In addition, the VDDS_DDR power plane should cover the entire keepout region.
A1
LPDDR
Device
A1
Figure 5-31. LPDDR Keepout Region
5.5.2.1.2.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the LPDDR and other circuitry.
Table 5-31 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the AM335x LPDDR interface and LPDDR device(s).
Additional bulk bypass capacitance may be needed for other circuitry.
Table 5-31. Bulk Bypass Capacitors(1)
NO.
1
PARAMETER
AM335x VDDS_DDR bulk bypass capacitor count
MIN
1
MAX
UNIT
Devices
μF
2
AM335x VDDS_DDR bulk bypass total capacitance
LPDDR#1 bulk bypass capacitor count
10
1
3
Devices
μF
4
LPDDR#1 bulk bypass total capacitance
LPDDR#2 bulk bypass capacitor count(2)
LPDDR#2 bulk bypass total capacitance(2)
10
1
5
Devices
μF
6
10
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass capacitors.
(2) Only used when two LPDDR devices are used.
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5.5.2.1.2.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper LPDDR interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, AM335x/LPDDR
power, and AM335x/LPDDR ground connections. Table 5-32 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB.
Table 5-32. High-Speed Bypass Capacitors
NO.
1
PARAMETER
MIN
MAX
UNIT
HS bypass capacitor package size(1)
0402 10 mils
2
Distance from HS bypass capacitor to device being bypassed
Number of connection vias for each HS bypass capacitor(2)
250
30
mils
Vias
mils
3
2
1
1
4
Trace length from bypass capacitor contact to connection via
Number of connection vias for each AM335x VDDS_DDR/VSS terminal
Trace length from AM335x VDDS_DDR/VSS terminal to connection via
Number of connection vias for each LPDDR device power/ground terminal
Trace length from LPDDR device power/ground terminal to connection via
AM335x VDDS_DDR HS bypass capacitor count(3)
5
Vias
mils
6
35
7
Vias
mils
8
35
9
10
0.6
8
Devices
μF
10 AM335x VDDS_DDR HS bypass capacitor total capacitance
11 LPDDR device HS bypass capacitor count(3)(4)
12 LPDDR device HS bypass capacitor total capacitance(4)
Devices
μF
0.4
(1) LxW, 10-mil units; i.e., a 0402 is a 40x20-mil surface-mount capacitor.
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Per LPDDR device.
5.5.2.1.2.8 Net Classes
Table 5-33 lists the clock net classes for the LPDDR interface. Table 5-34 lists the signal net classes, and
associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the
termination and routing rules that follow.
Table 5-33. Clock Net Class Definitions
CLOCK NET CLASS AM335x PIN NAMES
CK
DDR_CK/DDR_CKn
DDR_DQS0
DQS0
DQS1
DDR_DQS1
Table 5-34. Signal Net Class Definitions
ASSOCIATED CLOCK
SIGNAL NET CLASS
AM335x PIN NAMES
NET CLASS
ADDR_CTRL
CK
DDR_BA[1:0], DDR_A[15:0], DDR_CSn0, DDR_CASn, DDR_RASn,
DDR_WEn, DDR_CKE
DQ0
DQ1
DQS0
DQS1
DDR_D[7:0], DDR_DQM0
DDR_D[15:8], DDR_DQM1
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5.5.2.1.2.9 LPDDR Signal Termination
There is no specific need for adding terminations on the LPDDR interface. However, system designers
may evaluate the need for serial terminators for EMI and overshoot reduction. Placement of serial
terminations for DQS[x] and DQ[x] net class signals should be determined based on PCB analysis.
Placement of serial terminations for ADDR_CTRL net class signals should be close to the AM335x device.
Table 5-35 shows the specifications for the serial terminators in such cases.
Table 5-35. LPDDR Signal Terminations
No. Parameter
Min
0
Typ
22
Max Unit
Zo(2) ohms
Zo(2) ohms
Zo(2) ohms
1
2
3
CK net class(1)
ADDR_CTRL net class(1)(3)(4)
0
22
DQS0, DQS1, DQ0, and DQ1 net classes
0
22
(1) Only series termination is permitted.
(2) Zo is the LPDDR PCB trace characteristic impedance.
(3) Series termination values larger than typical only recommended to address EMI issues.
(4) Series termination values should be uniform across net class.
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
5.5.2.1.3 LPDDR CK and ADDR_CTRL Routing
Figure 5-32 shows the topology of the routing for the CK and ADDR_CTRL net classes. The length of
signal path AB and AC should be minimized with emphasis to minimize lengths C and D such that length
A is the majority of the total length of signal path AB and AC.
A1
A
AM335x
A1
Figure 5-32. CK and ADDR_CTRL Routing and Topology
Table 5-36. CK and ADDR_CTRL Routing Specification(1)(2)
NO.
1
PARAMETER
MIN
TYP
MAX
2w
UNIT
Center-to-center CK spacing
2
CK differential pair skew length mismatch(2)(3)
25
mils
mils
3
CK B-to-CK C skew length mismatch
25
4
Center-to-center CK to other LPDDR trace spacing(4)
CK/ADDR_CTRL nominal trace length(5)
4w
5
CACLM-50
CACLM
CACLM+50
100
mils
mils
mils
6
ADDR_CTRL-to-CK skew length mismatch
7
ADDR_CTRL-to-ADDR_CTRL skew length mismatch
Center-to-center ADDR_CTRL to other LPDDR trace spacing(4)
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(4)
ADDR_CTRL A-to-B/ADDR_CTRL A-to-C skew length mismatch(2)
ADDR_CTRL B-to-C skew length mismatch
100
8
4w
3w
9
10
11
100
100
mils
mils
(1) CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
(2) Series terminator, if used, should be located closest to the AM335x device.
(3) Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in Table 5-29.
(4) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(5) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
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Figure 5-33 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to
point. Skew matching across bytes is not needed nor recommended.
DQ[0]
A1
DQ[1]
AM335x
Figure 5-33. DQS[x] and DQ[x] Routing and Topology
Table 5-37. DQS[x] and DQ[x] Routing Specification(1)
NO.
1
PARAMETER
Center-to-center DQS[x] spacing
MIN
TYP
MAX
UNIT
2w
2
Center-to-center DDR_DQS[x] to other LPDDR trace spacing(2)
DQS[x]/DQ[x] nominal trace length(3)
4w
3
DQLM-50
DQLM
DQLM+50
100
mils
mils
mils
4
DQ[x]-to-DQS[x] skew length mismatch(3)
5
DQ[x]-to-DQ[x] skew length mismatch(3)
100
6
Center-to-center DQ[x] to other LPDDR trace spacing(2)(4)
Center-to-center DQ[x] to other DQ[x] trace spacing(2)(5)
4w
3w
7
(1) DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
(2) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) There is no requirement, and it is not recommended, to skew match between data bytes; i.e., from net classes DQS0 and DQ0 to net
classes DQS1 and DQ1.
(4) Signals from one DQ net class should be considered other LPDDR traces to another DQ net class.
(5) DQLM is the longest Manhattan distance of each of the DQS[x] and DQ[x] net classes.
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
5.5.2.2 DDR2 Routing Guidelines
5.5.2.2.1 Board Designs
TI only supports board designs that follow the guidelines outlined in this document. The switching
characteristics and the timing diagram for the DDR2 memory interface are shown in Table 5-38 and
Figure 5-34.
Table 5-38. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Interface
NO.
PARAMETER
MIN
MAX
UNIT
1
tc(DDR_CK/DDR_CKn) Cycle time, DDR_CK/DDR_CKn
3.75
8(1)
ns
(1) The JEDEC JESD79-2F specification defines the maximum clock period of 8 ns for all standard-speed bin DDR2 memory devices.
Therefore, all standard-speed bin DDR2 memory devices are required to operate at 125 MHz.
1
DDR_CK
DDR_CKn
Figure 5-34. DDR2 Memory Interface Clock Timing
5.5.2.2.2 DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR2
specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification application
report (literature number SPRAAV0). This application report provides generic guidelines and approach. All
the specifications provided in the data manual take precedence over the generic guidelines and must be
adhered to for a reliable DDR2 interface operation.
5.5.2.2.2.1 DDR2 Interface Schematic
Figure 5-35 shows the schematic connections for 16-bit interface on AM335x device using one x16 DDR2
device and Figure 5-36 shows the schematic connections for 16-bit interface on AM335x using two x8
DDR2 devices. The AM335x DDR2 memory interface only supports 16-bit wide mode of operation. The
AM335x device can only source one load connected to the DQS[x] and DQ[x] net class signals and two
loads connected to the CK and ADDR_CTRL net class signals. For more information related to net
classes, see Section 5.5.2.2.2.8.
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16-Bit DDR2
Device
AM335x
DDR_D0
DQ0
DDR_D7
DQ7
LDM
LDQS
DDR_DQM0
DDR_DQS0
DDR_DQSn0
DDR_D8
LDQS
DQ8
DDR_D15
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DQ15
UDM
UDQS
UDQS
DDR_ODT
DDR_BA0
T
T
ODT
BA0
DDR_BA2
DDR_A0
T
T
BA2
A0
DDR_A15
T
T
A15
CS
DDR_CSn0
DDR_CASn
DDR_RASn
DDR_WEn
DDR_CKE
DDR_CK
CAS
RAS
T
T
T
T
T
T
VDDS_DDR(A)
WE
CKE
CK
CK
1 K Ω 1%
0.1 µF
0.1 µF
DDR_CKn
DDR_VREF
DDR_VREF
1 K Ω 1%
VREF
0.1 µF(B)
0.1 µF(B)
DDR_RESETn
DDR_VTP
NC
49.9 Ω
( 1%, 20 mW)
A. VDDS_DDR is the power supply for the DDR2 memories and the AM335x DDR2 interface.
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a DDR_VREF pin.
C. For all the termination requirements, see Section 5.5.2.2.2.9.
Figure 5-35. 16-Bit DDR2 Interface Using One 16-Bit DDR2 Device
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
8-Bit DDR2
Devices
AM335x
DDR_D0
DQ0
DDR_D7
DQ7
DM
DDR_DQM0
DDR_DQS0
DQS
DDR_DQSn0
DQS
DDR_D8
DQ0
DDR_D15
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DQ7
DM
DQS
DQS
DDR_ODT
DDR_BA0
T
T
ODT
BA0
ODT
BA0
DDR_BA2
DDR_A0
T
T
BA2
A0
BA2
A0
DDR_A15
T
T
A15
CS
A15
CS
DDR_CSn0
DDR_CASn
DDR_RASn
DDR_WEn
DDR_CKE
DDR_CK
CAS
RAS
CAS
RAS
T
T
T
T
T
T
VDDS_DDR(A)
WE
WE
CKE
CKE
CK
CK
CK
CK
1 K Ω 1%
0.1 µF
0.1 µF
DDR_CKn
DDR_VREF
DDR_VREF
VREF
VREF
0.1 µF(B) 0.1 µF(B)
0.1 µF(B)
1 K Ω 1%
DDR_RESETn
DDR_VTP
NC
49.9 Ω
( 1%, 20 mW)
A. VDDS_DDR is the power supply for the DDR2 memories and the AM335x DDR2 interface.
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a DDR_VREF pin.
C. For all the termination requirements, see Section 5.5.2.2.2.9.
Figure 5-36. 16-Bit DDR2 Interface Using Two 8-Bit DDR2 Devices
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5.5.2.2.2.2 Compatible JEDEC DDR2 Devices
Table 5-39 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16 or x8 DDR2-533 speed grade DDR2 devices.
Table 5-39. Compatible JEDEC DDR2 Devices (Per Interface)(1)
NO.
1
PARAMETER
JEDEC DDR2 device speed grade(2)
MIN
MAX
UNIT
DDR2-533
2
JEDEC DDR2 device bit width
JEDEC DDR2 device count
x8
1
x16
2
Bits
3
Devices
4
JEDEC DDR2 device terminal count(3)
60
84 Terminals
(1) If the DDR2 interface is operated with a clock frequency less than 266 MHz, lower-speed grade DDR2 devices may be used if the
minimum clock period specified for the DDR2 device is less than or equal to the minimum clock period selected for the AM335x DDR2
interface.
(2) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.
(3) 92-terminal devices are also supported for legacy reasons. New designs will migrate to 84-terminal DDR2 devices. Electrically, the 92-
and 84-terminal DDR2 devices are the same.
5.5.2.2.2.3 PCB Stackup
The minimum stackup required for routing the AM335x device is a four-layer stackup as shown in Table 5-
40. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal
integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
Table 5-40. Minimum PCB Stackup(1)
LAYER
TYPE
Signal
Plane
Plane
Signal
DESCRIPTION
Top signal routing
Ground
1
2
3
4
Split Power Plane
Bottom signal routing
(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these
signals on layer 1 which requires some to be routed on layer 4. When this is done, the signal routes on layer 4 should not cross splits in
the power plane.
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Complete stackup specifications are provided in Table 5-41.
Table 5-41. PCB Stackup Specifications(1)
NO.
1
PARAMETER
MIN
TYP
MAX
UNIT
PCB routing/plane layers
4
2
1
2
Signal routing layers
3
Full ground layers under DDR2 routing region
Number of ground plane cuts allowed within DDR2 routing region
Full VDDS_DDR power reference layers under DDR2 routing region
Number of layers between DDR2 routing layer and reference ground plane
PCB routing feature size
4
0
0
5
1
6
7
4
4
mils
mils
mils
mils
8
PCB trace width, w
9
PCB BGA escape via pad size(2)
18
10
0.5
0.4
20
10 PCB BGA escape via hole size(2)
ZCZ package
ZCE package
11 AM335x BGA pad size
mm
13 Single-ended impedance, Zo(3)
14 Impedance control(4)(5)
50
75
ohms
ohms
Zo-5
Zo
Zo+5
(1) For the DDR2 device BGA pad size, see the DDR2 device manufacturer documentation.
(2) A 20/10 via may be used if enough power routing resources are available. An 18/10 via allows for more flexible power routing to the
AM335x device.
(3) Zo is the nominal singled-ended impedance selected for the PCB.
(4) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo
defined by the single-ended impedance parameter.
(5) Tighter impedance control is required to ensure flight time skew is minimal.
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5.5.2.2.2.4 Placement
Figure 5-37 shows the required placement for the DDR2 devices. The dimensions for this figure are
defined in Table 5-42. The placement does not restrict the side of the PCB on which the devices are
mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for
proper routing space. For single-memory DDR2 systems, the second DDR2 device is omitted from the
placement.
X
A1
Y
OFFSET
DDR2
Y
Device
Y
OFFSET
AM335x
A1
Recommended DDR2
Device Orientation
Figure 5-37. AM335x Device and DDR2 Device Placement
Table 5-42. Placement Specifications(1)
NO.
1
PARAMETER
MIN
MAX
1750
1280
650
UNIT
mils
mils
mils
w
X(2)(3)
Y(2)(3)
Y Offset(2)(3)(4)
2
3
4
Clearance from non-DDR2 signal to DDR2 keepout region(5)(6)
4
(1) DDR2 keepout region to encompass entire DDR2 routing area.
(2) For dimension definitions, see Figure 5-37.
(3) Measurements from center of AM335x device to center of DDR2 device.
(4) For single-memory systems, it is recommended that Y offset be as small as possible.
(5) w is defined as the signal trace width.
(6) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.
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5.5.2.2.2.5 DDR2 Keepout Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2
keepout region is defined for this purpose and is shown in Figure 5-38. This region should encompass all
DDR2 circuitry and the region size varies with component placement and DDR2 routing. Additional
clearances required for the keepout region are shown in Table 5-42. Non-DDR2 signals should not be
routed on the same signal layer as DDR2 signals within the DDR2 keepout region. Non-DDR2 signals
may be routed in the region provided they are routed on layers separated from DDR2 signal layers by a
ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this
region. In addition, the VDDS_DDR power plane should cover the entire keepout region.
A1
DDR2
Device
A1
Figure 5-38. DDR2 Keepout Region
5.5.2.2.2.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 5-43 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the AM335x DDR2 interface and DDR2 device(s).
Additional bulk bypass capacitance may be needed for other circuitry.
Table 5-43. Bulk Bypass Capacitors(1)
NO.
1
PARAMETER
AM335x VDDS_DDR bulk bypass capacitor count
AM335x VDDS_DDR bulk bypass total capacitance
DDR2#1 bulk bypass capacitor count
MIN
1
MAX
UNIT
Devices
μF
2
10
1
3
Devices
μF
4
DDR2#1 bulk bypass total capacitance
DDR2#2 bulk bypass capacitor count(2)
DDR2#2 bulk bypass total capacitance(2)
10
1
5
Devices
μF
6
10
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass capacitors.
(2) Only used when two DDR2 devices are used.
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5.5.2.2.2.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, AM335x/DDR2 power,
and AM335x/DDR2 ground connections. Table 5-44 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB.
Table 5-44. High-Speed Bypass Capacitors
NO.
1
PARAMETER
MIN
MAX
UNIT
HS bypass capacitor package size(1)
0402 10 mils
2
Distance from HS bypass capacitor to device being bypassed
Number of connection vias for each HS bypass capacitor(2)
250
30
mils
Vias
mils
3
2
1
1
4
Trace length from bypass capacitor contact to connection via
Number of connection vias for each AM335x VDDS_DDR/VSS terminal
Trace length from AM335x VDDS_DDR/VSS terminal to connection via
Number of connection vias for each DDR2 device power/ground terminal
Trace length from DDR2 device power/ground terminal to connection via
AM335x VDDS_DDR HS bypass capacitor count(3)
5
Vias
mils
6
35
7
Vias
mils
8
35
9
10
0.6
8
Devices
μF
10 AM335x VDDS_DDR HS bypass capacitor total capacitance
11 DDR2 device HS bypass capacitor count(3)(4)
12 DDR2 device HS bypass capacitor total capacitance(4)
Devices
μF
0.4
(1) LxW, 10-mil units; i.e., a 0402 is a 40x20-mil surface-mount capacitor.
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Per DDR2 device.
5.5.2.2.2.8 Net Classes
Table 5-45 lists the clock net classes for the DDR2 interface. Table 5-46 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 5-45. Clock Net Class Definitions
CLOCK NET CLASS AM335x PIN NAMES
CK
DDR_CK/DDR_CKn
DQS0
DQS1
DDR_DQS0/DDR_DQSn0
DDR_DQS1/DDR_DQSn1
Table 5-46. Signal Net Class Definitions
ASSOCIATED CLOCK
SIGNAL NET CLASS
AM335x PIN NAMES
NET CLASS
ADDR_CTRL
CK
DDR_BA[2:0], DDR_A[15:0], DDR_CSn0, DDR_CASn, DDR_RASn,
DDR_WEn, DDR_CKE, DDR_ODT
DQ0
DQ1
DQS0
DQS1
DDR_D[7:0], DDR_DQM0
DDR_D[15:8], DDR_DQM1
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5.5.2.2.2.9 DDR2 Signal Termination
Signal terminations are required on the CK and ADDR_CTRL net class signals. Serial terminations should
be used on the CK and ADDR_CTRL lines and is the preferred termination scheme. On-device
terminations (ODTs) are required on the DQS[x] and DQ[x] net class signals. They should be enabled to
ensure signal integrity. Table 5-47 shows the specifications for the series terminators. Placement of serial
terminations for ADDR_CTRL net class signals should be close to the AM335x device.
Table 5-47. DDR2 Signal Terminations
NO.
1
PARAMETER
MIN
0
TYP
MAX
10
Zo(4)
UNIT
ohms
ohms
ohms
CK net class(1)
ADDR_CTRL net class(1)(2)(3)
2
0
22
3
DQS0, DQS1, DQ0, and DQ1 net classes(5)
NA
NA
(1) Only series termination is permitted.
(2) Series termination values larger than typical only recommended to address EMI issues.
(3) Series termination values should be uniform across net class.
(4) Zo is the DDR2 PCB trace characteristic impedance.
(5) No external termination resistors are allowed and ODT must be used for these net classes.
If the DDR2 interface is operated at a lower frequency (<200-MHz clock rate), on-device terminations are
not specifically required for the DQS[x] and DQ[x] net class signals and serial terminations for the CK and
ADDR_CTRL net class signals are not mandatory. System designers may evaluate the need for serial
terminators for EMI and overshoot reduction. Placement of serial terminations for DQS[x] and DQ[x] net
class signals should be determined based on PCB analysis. Placement of serial terminations for
ADDR_CTRL net class signals should be close to the AM335x device. Table 5-48 shows the
specifications for the serial terminators in such cases.
Table 5-48. Lower-Frequency DDR2 Signal Terminations
NO. PARAMETER
MIN
0
TYP
22
MAX
Zo(2)
Zo(2)
Zo(2)
UNIT
ohms
ohms
ohms
1
2
3
CK net class(1)
ADDR_CTRL net class(1)(3)(4)
0
22
DQS0, DQS1, DQ0, and DQ1 net classes
0
22
(1) Only series termination is permitted.
(2) Zo is the DDR2 PCB trace characteristic impedance.
(3) Series termination values larger than typical only recommended to address EMI issues.
(4) Series termination values should be uniform across net class.
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5.5.2.2.2.10 DDR_VREF Routing
DDR_VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM335x
device. DDR_VREF is intended to be half the DDR2 power supply voltage and should be created using a
resistive divider as shown in Figure 5-35 and Figure 5-36. Other methods of creating DDR_VREF are not
recommended. Figure 5-39 shows the layout guidelines for DDR_VREF.
DDR_VREF Bypass Capacitor
DDR2 Device
A1
DDR_VREF Nominal Minimum
Trace Width is 20 Mils
AM335x
A1
Neck down to minimum in BGA escape
regions is acceptable. Narrowing to
accommodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of DDR_VREF is maximized.
Figure 5-39. DDR_VREF Routing and Topology
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5.5.2.2.3 DDR2 CK and ADDR_CTRL Routing
Figure 5-40 shows the topology of the routing for the CK and ADDR_CTRL net classes. The length of
signal path AB and AC should be minimized with emphasis to minimize lengths C and D such that length
A is the majority of the total length of signal path AB and AC.
A1
T
A
AM335x
A1
Figure 5-40. CK and ADDR_CTRL Routing and Topology
Table 5-49. CK and ADDR_CTRL Routing Specification(1)(2)
NO.
1
PARAMETER
MIN
TYP
MAX
2w
UNIT
Center-to-center CK spacing
2
CK differential pair skew length mismatch(2)(3)
25
mils
mils
3
CK B-to-CK C skew length mismatch
25
4
Center-to-center CK to other DDR2 trace spacing(4)
CK/ADDR_CTRL nominal trace length(5)
4w
5
CACLM-50
CACLM
CACLM+50
100
mils
mils
mils
6
ADDR_CTRL-to-CK skew length mismatch
7
ADDR_CTRL-to-ADDR_CTRL skew length mismatch
Center-to-center ADDR_CTRL to other DDR2 trace spacing(4)
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(4)
ADDR_CTRL A-to-B/ADDR_CTRL A-to-C skew length mismatch(2)
ADDR_CTRL B-to-C skew length mismatch
100
8
4w
3w
9
10
11
100
100
mils
mils
(1) CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
(2) Series terminator, if used, should be located closest to the AM335x device.
(3) Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in Table 5-41.
(4) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(5) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
Figure 5-41 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to
point. Skew matching across bytes is not needed nor recommended.
DQ[0]
A1
DQ[1]
AM335x
Figure 5-41. DQS[x] and DQ[x] Routing and Topology
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Table 5-50. DQS[x] and DQ[x] Routing Specification(1)
NO.
1
PARAMETER
Center-to-center DQS[x] spacing
MIN
TYP
MAX
2w
UNIT
2
DQS[x] differential pair skew length mismatch(2)
Center-to-center DDR_DQS[x] to other DDR2 trace spacing(3)
DQS[x]/DQ[x] nominal trace length(4)
DQ[x]-to-DQS[x] skew length mismatch(4)
DQ[x]-to-DQ[x] skew length mismatch(4)
25
mils
3
4w
4
DQLM-50
DQLM
DQLM+50
100
mils
mils
mils
5
6
100
7
Center-to-center DQ[x] to other DDR2 trace spacing(3)(5)
Center-to-center DQ[x] to other DQ[x] trace spacing(3)(6)
4w
3w
8
(1) DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
(2) Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in Table 5-41.
(3) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(4) There is no requirement, and it is not recommended, to skew match between data bytes; i.e., from net classes DQS0 and DQ0 to net
classes DQS1 and DQ1.
(5) Signals from one DQ net class should be considered other DDR2 traces to another DQ net class.
(6) DQLM is the longest Manhattan distance of each of the DQS[x] and DQ[x] net classes.
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5.5.2.3 DDR3 Routing Guidelines
5.5.2.3.1 Board Designs
TI only supports board designs utilizing DDR3 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the DDR3 memory interface are shown in Table 5-51 and
Figure 5-42.
Table 5-51. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory
Interface
NO.
PARAMETER
MIN
MAX
UNIT
1
tc(DDR_CK/DDR_CKn) Cycle time, DDR_CK/DDR_CKn
3.3
3.3(1)
ns
(1) The JEDEC JESD79-3E specification defines the maximum clock period of 3.3 ns for all standard-speed bin DDR3 memory devices.
Therefore, all standard-speed bin DDR3 memory devices are required to operate at 303 MHz.
1
DDR_CK
DDR_CKn
Figure 5-42. DDR3 Memory Interface Clock Timing
5.5.2.3.1.1 DDR3 versus DDR2
This specification only covers AM335x PCB designs that utilize DDR3 memory. Designs using DDR2
memory should use the DDR2 routing guidleines described in Section 5.5.2.2. While similar, the two
memory systems have different requirements. It is currently not possible to design one PCB that meets
the requirements of both DDR2 and DDR3.
5.5.2.3.2 DDR3 Device Combinations
Since there are several possible combinations of device counts and single-side or dual-side mounting,
Table 5-52 summarizes the supported device configurations.
Table 5-52. Supported DDR3 Device Combinations
NUMBER OF DDR3 DEVICES
DDR3 DEVICE WIDTH (BITS)
MIRRORED?
DDR3 EMIF WIDTH (BITS)
1
2
16
8
N
Y(1)
16
16
(1) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of
the board.
5.5.2.3.3 DDR3 Interface
5.5.2.3.3.1 DDR3 Interface Schematic
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used. Figure 5-43
shows the schematic connections for 16-bit interface on AM335x device using one x16 DDR3 device and
Figure 5-44 shows the schematic connections for 16-bit interface on AM335x device using two x8 DDR3
devices. The AM335x DDR3 memory interface only supports 16-bit wide mode of operation. The AM335x
device can only source one load connected to the DQS[x] and DQ[x] net class signals and two loads
connected to the CK and ADDR_CTRL net class signals. For more information related to net classes, see
Section 5.5.2.3.3.8.
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16-Bit DDR3
Interface
16-Bit DDR3
Device
DDR_D15
8
DQU7
DDR_D8
DQU0
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DMU
DQSU
DQSU#
DDR_D7
8
DQL7
DDR_D0
DQL0
DDR_DQM0
DDR_DQS0
DDR_DQSn0
DML
DQSL
DQSL#
0.1 µF
Zo
Zo
DDR_CK
CK
VDDS_DDR
DDR_CKn
CK#
DDR_ODT
DDR_CSn0
DDR_BA0
DDR_BA1
DDR_BA2
ODT
CS#
BA0
BA1
BA2
DDR_VTT
Zo
Zo
DDR_A0
15
A0
DDR_A15
A15
DDR_CASn
DDR_RASn
DDR_WEn
CAS#
RAS#
WE#
DDR_CKE
CKE
DDR_RESETn
DDR_VREF
RESET#
ZQ
ZQ
VREFDQ
VREFCA
DDR_VREF
0.1 µF
0.1 µF
0.1 µF
DDR_VTP
49.9 Ω
( 1%, 20 mW)
Zo
Termination is required. See terminator comments.
Value determined according to the DDR3 memory device data sheet.
ZQ
Figure 5-43. 16-Bit DDR3 Interface Using One 16-Bit DDR3 Device
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16-Bit DDR3
Interface
8-Bit DDR3
Devices
DDR_D15
DQ7
DQ0
8
DDR_D8
DDR_DQM1
DM/TDQS
TDQS#
DQS
NC
DDR_DQS1
DDR_DQSn1
DQS#
DDR_D7
DQ7
DQ0
8
DDR_D0
DDR_DQM0
DM/TDQS
TDQS#
DQS
NC
DDR_DQS0
DDR_DQSn0
DQS#
0.1 µF
Zo
DDR_CK
CK
CK
VDDS_DDR
DDR_CKn
CK#
CK#
Zo
DDR_ODT
DDR_CSn0
DDR_BA0
DDR_BA1
DDR_BA2
ODT
ODT
CS#
BA0
BA1
BA2
CS#
BA0
BA1
BA2
DDR_VTT
Zo
DDR_A0
A0
A0
15
Zo
DDR_A15
A15
A15
DDR_CASn
DDR_RASn
DDR_WEn
CAS#
RAS#
WE#
CAS#
RAS#
WE#
DDR_CKE
CKE
CKE
DDR_RESETn
DDR_VREF
RESET#
ZQ
RESET#
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
DDR_VREF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
DDR_VTP
49.9 Ω
( 1%, 20 mW)
Zo
ZQ
Termination is required. See terminator comments.
Value determined according to the DDR3 memory device data sheet.
Figure 5-44. 16-Bit DDR3 Interface Using Two 8-Bit DDR3 Devices
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5.5.2.3.3.2 Compatible JEDEC DDR3 Devices
Table 5-53 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Generally, the DDR3 interface is compatible with DDR3-800 devices in the x8 or x16 widths.
Table 5-53. Compatible JEDEC DDR3 Devices (Per Interface)
NO.
1
PARAMETER
MIN
MAX
UNIT
JEDEC DDR3 device speed grade(1)
JEDEC DDR3 device bit width
JEDEC DDR3 device count(2)
DDR3-800
2
x8
1
x16
2
Bits
3
Devices
(1) DDR3 speed grade depends on desired clock rate. Data rate is 2x the clock rate. For DDR3-800, the clock rate is 400 MHz.
(2) For valid DDR3 device configurations and device counts, see Section 5.5.2.3.3.1, Figure 5-43, and Figure 5-44.
5.5.2.3.3.3 PCB Stackup
The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 5-54.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal
integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
Table 5-54. Minimum PCB Stackup(1)
LAYER
TYPE
Signal
Plane
Plane
Signal
DESCRIPTION
Top signal routing
Ground
1
2
3
4
Split Power Plane
Bottom signal routing
(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these
signals on layer 1 which requires some to be routed on layer 4. When this is done, the signal routes on layer 4 should not cross splits in
the power plane.
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Table 5-55. PCB Stackup Specifications(1)
PARAMETER
MIN
TYP
MAX
UNIT
1
2
3
4
5
6
7
8
9
PCB routing/plane layers
4
2
1
1
Signal routing layers
Full ground reference layers under DDR3 routing region(2)
Full VDDS_DDR power reference layers under the DDR3 routing region(2)
Number of reference plane cuts allowed within DDR3 routing region(3)
Number of layers between DDR3 routing layer and reference plane(4)
PCB routing feature size
0
0
4
4
mils
mils
mils
mils
PCB trace width, w
PCB BGA escape via pad size(5)
18
10
0.5
0.4
20
10 PCB BGA escape via hole size
ZCZ package
ZCE package
11 AM335x BGA pad size
mm
13 Single-ended impedance, Zo(6)
14 Impedance control(7)(8)
50
75
ohms
ohms
Zo-5
Zo
Zo+5
(1) For the DDR3 device BGA pad size, see the DDR3 device manufacturer documentation.
(2) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers.
(3) No traces should cross reference plane cuts within the DDR3 routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(4) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(5) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
(6) Zo is the nominal singled-ended impedance selected for the PCB.
(7) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo
defined by the single-ended impedance parameter.
(8) Tighter impedance control is required to ensure flight time skew is minimal.
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5.5.2.3.3.4 Placement
Figure 5-45 shows the required placement for the AM335x device as well as the DDR3 devices. The
dimensions for this figure are defined in Table 5-56. The placement does not restrict the side of the PCB
on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace
lengths and allow for proper routing space.
X1
X2
DDR3
Interface
Y
Figure 5-45. Placement Specifications
Table 5-56. Placement Specifications(1)
NO.
1
PARAMETER
MIN
MAX
1000
600
UNIT
mils
mils
mils
w
X1(2)(3)(4)
X2(2)(3)
Y Offset(2)(3)(4)
2
3
1500
4
Clearance from non-DDR3 signal to DDR3 keepout region(5)(6)
4
(1) DDR3 keepout region to encompass entire DDR3 routing area.
(2) For dimension definitions, see Figure 5-45.
(3) Measurements from center of AM335x device to center of DDR3 device.
(4) Minimizing X1 and Y improves timing margins.
(5) w is defined as the signal trace width.
(6) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
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5.5.2.3.3.5 DDR3 Keepout Region
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout
region is defined for this purpose and is shown in Figure 5-46. This region should encompass all DDR3
circuitry and the region size varies with component placement and DDR3 routing. Additional clearances
required for the keepout region are shown in Table 5-56. Non-DDR3 signals should not be routed on the
same signal layer as DDR3 signals within the DDR3 keepout region. Non-DDR3 signals may be routed in
the region provided they are routed on layers separated from DDR3 signal layers by a ground layer. No
breaks should be allowed in the reference ground or VDDS_DDR power plane in this region. In addition,
the VDDS_DDR power plane should cover the entire keepout region.
DDR3 Interface
DDR3 Keepout Region
Encompasses Entire
DDR3 Routing Area
Figure 5-46. DDR3 Keepout Region
5.5.2.3.3.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry.
Table 5-57 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the AM335x DDR3 interface and DDR3 device(s).
Additional bulk bypass capacitance may be needed for other circuitry.
Table 5-57. Bulk Bypass Capacitors(1)
NO.
1
PARAMETER
AM335x VDDS_DDR bulk bypass capacitor count
AM335x VDDS_DDR bulk bypass total capacitance
DDR3#1 bulk bypass capacitor count
MIN
2
MAX
UNIT
Devices
μF
2
20
2
3
Devices
μF
4
DDR3#1 bulk bypass total capacitance
DDR3#2 bulk bypass capacitor count(2)
DDR3#2 bulk bypass total capacitance(2)
20
2
5
Devices
μF
6
20
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-
speed (HS) bypass capacitors and DDR3 signal routing.
(2) Only used when two DDR3 devices are used.
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5.5.2.3.3.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, AM335x/DDR3 power,
and AM335x/DDR3 ground connections. Table 5-58 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible.
2. Minimize the distance from the bypass cap to the power terminals being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
5. Minimize via sharing. Note the limites on via sharing shown in Table 5-58.
Table 5-58. High-Speed Bypass Capacitors
NO.
1
PARAMETER
HS bypass capacitor package size(1)
MIN
TYP
MAX
UNIT
0201
0402 10 mils
2
Distance, HS bypass capacitor to AM335x VDDS_DDR/VSS terminal
being bypassed(2)(3)(4)
400
mils
3
4
5
6
7
8
9
AM335x VDDS_DDR HS bypass capacitor count
20
1
Devices
μF
AM335x VDDS_DDR HS bypass capacitor total capacitance
Trace length from AM335x VDDS_DDR/VSS terminal to connection via(2)
Distance, HS bypass capacitor to DDR3 device being bypassed(5)
DDR3 device HS bypass capacitor count(6)
DDR3 device HS bypass capacitor total capacitance(6)
Number of connection vias for each HS bypass capacitor(7)(8)
35
70
mils
150
mils
12
0.85
2
Devices
μF
Vias
mils
10 Trace length from bypass capacitor connect to connection via(2)(8)
11 Number of connection vias for each DDR3 device power/ground terminal(9)
35
35
100
60
1
Vias
mils
12 Trace length from DDR3 device power/ground terminal to connection
via(2)(7)
(1) LxW, 10-mil units, i.e., a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer/shorter is better.
(3) Measured from the nearest AM335x VDDS_DDR and ground terminal to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the AM335x device, between the cluster of VDDS_DDR and ground terminals,
between the DDR3 interfaces on the package.
(5) Measured from the DDR3 device power/ground terminal to the center of the capacitor package.
(6) Per DDR3 device.
(7) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
(8) An HS bypass capacitor may share a via with a DDR3 device mounted on the same side of the PCB. A wide trace should be used for
the connection and the length from the capacitor pad to the DDR3 device pad should be less than 150 mils.
(9) Up to a total of two pairs of DDR3 power/ground terminals may share a via.
5.5.2.3.3.7.1 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. Since these are returns for signal current, the signal via size may be used for these capacitors.
5.5.2.3.3.8 Net Classes
Table 5-59 lists the clock net classes for the DDR3 interface. Table 5-60 lists the signal net classes, and
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the
termination and routing rules that follow.
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Table 5-59. Clock Net Class Definitions
CLOCK NET CLASS AM335x PIN NAMES
CK
DDR_CK/DDR_CKn
DQS0
DQS1
DDR_DQS0/DDR_DQSn0
DDR_DQS1/DDR_DQSn1
Table 5-60. Signal Net Class Definitions
ASSOCIATED CLOCK
SIGNAL NET CLASS
AM335x PIN NAMES
NET CLASS
ADDR_CTRL
CK
DDR_BA[2:0], DDR_A[15:0], DDR_CSn0, DDR_CASn, DDR_RASn,
DDR_WEn, DDR_CKE, DDR_ODT
DQ0
DQ1
DQS0
DQS1
DDR_D[7:0], DDR_DQM0
DDR_D[15:8], DDR_DQM1
5.5.2.3.3.9 DDR3 Signal Termination
Signal terminations are required for the CK and ADDR_CTRL net class signals. On-device terminations
(ODTs) are required on the DQS[x] and DQ[x] net class signals. Detailed termination specifications are
covered in the routing rules in the following sections.
5.5.2.3.3.10 DDR_VREF Routing
DDR_VREF is used as a reference by the input buffers of the DDR3 memories as well as the AM335x
device. DDR_VREF is intended to be half the DDR3 power supply voltage and is typically generated with
a voltage divider connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide
trace with 0.1 µF bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to
accommodate routing congestion.
5.5.2.3.3.11 VTT
Like DDR_VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike
DDR_VREF, VTT is expected to source and sink current, specifically the termination current for the
ADDR_CTRL net class Thevinen terminators. VTT is needed at the end of the address bus and it should
be routed as a power sub-plane. VTT should be bypassed near the terminator resistors.
5.5.2.3.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.
The following subsections show the topology and routing for various DDR3 configurations for CK and
ADDR_CTRL. The figures in the following subsections define the terms for the routing specification
detailed in Table 5-61.
5.5.2.3.4.1 Two DDR3 Devices
Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as
one 16-bit bank. These two devices may be mounted on a single side of the PCB, or may be mirrored in a
pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
5.5.2.3.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
Figure 5-47 shows the topology of the CK net classes and Figure 5-48 shows the topology for the
corresponding ADDR_CTRL net classes.
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DDR3 Differential CK Input Buffers
–
–
+
+
Clock Parallel
Terminator
VDDS_DDR
Rcp
A1
A2
A2
A3
A3
AT
AT
Cac
AM335x
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
A1
Routed as Differential Pair
Figure 5-47. CK Topology for Two DDR3 Devices
DDR3 Address/Control Input Buffers
Address/Control
Terminator
Rtt
AM335x
Address/Control
Output Buffer
A1
A2
A3
AT
Vtt
Figure 5-48. ADDR_CTRL Topology for Two DDR3 Devices
5.5.2.3.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
Figure 5-49 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 5-50
shows the corresponding ADDR_CTRL routing.
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VDDS_DDR
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
Figure 5-49. CK Routing for Two Single-Side DDR3 Devices
Rtt
A2
A3
AT
Vtt
=
Figure 5-50. ADDR_CTRL Routing for Two Single-Side DDR3 Devices
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To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased
routing and assembly complexity. Figure 5-51 and Figure 5-52 show the routing for CK and ADDR_CTRL,
respectively, for two DDR3 devices mirrored in a single-pair configuration.
VDDS_DDR
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
Figure 5-51. CK Routing for Two Mirrored DDR3 Devices
Rtt
A2
A3
AT
Vtt
=
Figure 5-52. ADDR_CTRL Routing for Two Mirrored DDR3 Devices
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5.5.2.3.4.2 One DDR3 Device
A single DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged
as one 16-bit bank.
5.5.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device
Figure 5-53 shows the topology of the CK net classes and Figure 5-54 shows the topology for the
corresponding ADDR_CTRL net classes.
DDR3 Differential CK Input Buffer
–
+
Clock Parallel
Terminator
VDDS_DDR
Rcp
A1
A1
A2
A2
AT
AT
Cac
AM335x
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
Figure 5-53. CK Topology for One DDR3 Device
DDR3 Address/Control Input Buffers
Address/Control
Terminator
Rtt
AM335x
Address/Control
Output Buffer
A1
A2
AT
Vtt
Figure 5-54. ADDR_CTRL Topology for One DDR3 Device
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5.5.2.3.4.2.2 CK and ADDR/CTRL Routing, One DDR3 Device
Figure 5-55 shows the CK routing for one DDR3 device. Figure 5-56 shows the corresponding
ADDR_CTRL routing.
VDDS_DDR
Cac
Rcp
Rcp
A2
A2
AT
AT
0.1 µF
=
Figure 5-55. CK Routing for One DDR3 Device
Rtt
A2
AT
Vtt
=
Figure 5-56. ADDR_CTRL Routing for One DDR3 Device
5.5.2.3.5 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point to point, so its
definition is simple.
5.5.2.3.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
DQS[x] lines are point-to-point differential, and DQ[x] lines are point-to-point singled ended. Figure 5-57
and Figure 5-58 show these topologies.
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AM335x
DQS[x]
DDR3
DQS[x]+
DQS[x]-
DQS[x]
I/O Buffer
I/O Buffer
Routed Differentially
x = 0, 1
Figure 5-57. DQS[x] Topology
AM335x
DQ[x]
DDR3
DQ[x]
DQ[x]
I/O Buffer
I/O Buffer
x = 0, 1
Figure 5-58. DQ[x] Topology
5.5.2.3.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
Figure 5-59 and Figure 5-60 show the DQS[x] and DQ[x] routing.
DQS[x]
DQS[x]+
DQS[x]-
Routed Differentially
x = 0, 1
Figure 5-59. DQS[x] Routing With Any Number of Allowed DDR3 Devices
DQ[x]
x = 0, 1
Figure 5-60. DQ[x] Routing With Any Number of Allowed DDR3 Devices
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5.5.2.3.6 Routing Specification
5.5.2.3.6.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
Given the clock and address pin locations on the AM335x device and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. Figure 5-61 shows this distance for
two loads. It is from this distance that the specifications on the lengths of the transmission lines for the
address bus are determined. CACLM is determined similarly for other address bus configurations; i.e., it is
based on the longest net of the CK/ADDR_CTRL net class. For CK and ADDR_CTRL routing, these
specifications are contained in Table 5-61.
A8(A)
CACLMY
CACLMX
A8(A)
A8(A)
Rtt
A2
A3
AT
Vtt
=
A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
Figure 5-61. CACLM for Two Address Loads on One Side of PCB
Table 5-61. CK and ADDR_CTRL Routing Specification(1)(2)(3)
NO.
1
PARAMETER
MIN
TYP
MAX
2500
25
UNIT
mils
mils
mils
mils
mils
mils
A1+A2 length
A1+A2 skew
A3 length
A3 skew(4)
A3 skew(5)
AS length
2
3
660
25
4
5
125
100
6
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NO.
SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 5-61. CK and ADDR_CTRL Routing Specification(1)(2)(3) (continued)
PARAMETER
MIN
TYP
MAX
25
UNIT
mils
mils
mils
mils
mils
mils
mils
7
8
9
AS skew
AS+/AS- length
AS+/AS- skew
70
5
10 AT length(6)
11 AT skew(7)
12 AT skew(8)
500
100
5
13 CK/ADDR_CTRL nominal trace length(9)
14 Center-to-center CK to other DDR3 trace spacing(10)
15 Center-to-center ADDR_CTRL to other DDR3 trace spacing(10)(11)
16 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(10)
17 CK center-to-center spacing(12)
CACLM-50
CACLM
CACLM+50
4w
4w
3w
18 CK spacing to other net(10)
19 Rcp(13)
20 Rtt(13)(14)
4w
Zo-1
Zo-5
Zo
Zo
Zo+1
Zo+5
ohms
ohms
(1) CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
(2) The use of vias should be minimized.
(3) Additional bypass capacitors are required when using the VDDS_DDR plane as the reference plane to allow the return current to jump
between the VDDS_DDR plane and the ground plane when the net class switches layers at a via.
(4) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
(5) Non-mirrored configuration (all DDR3 memories on same side of PCB).
(6) While this length can be increased for convenience, its length should be minimized.
(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
(8) CK net class only.
(9) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see Section 5.5.2.3.6.1
and Figure 5-61.
(10) Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length.
(11) Signals from one DQ net class should be considered other DDR3 traces to another DQ net class.
(12) CK spacing set to ensure proper differential impedance.
(13) Source termination (series resistor at driver) is specifically not allowed.
(14) Termination values should be uniform across the net class.
5.5.2.3.6.2 DQS[x] and DQ[x] Routing Specification
Skew within the DQS[x] and DQ[x] net classes directly reduces setup and hold margin and, thus, this skew
must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces
up to the length of the longest net in the net class and its associated clock. DQLMn is defined as DQ
Longest Manhattan distance n, where n is the byte number. For a 16-bit interface, there are two DQLMs,
DQLM0-DQLM1.
NOTE
It is not required, nor is it recommended, to match the lengths across all bytes. Length
matching is only required within each byte.
Given the DQS[x] and DQ[x] pin locations on the AM335x device and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. Figure 5-62 shows this distance for
a two-load case. It is from this distance that the specifications on the lengths of the transmission lines for
the data bus are determined. For DQS[x] and DQ[x] routing, these specifications are contained in Table 5-
62.
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DQLMX0
DQ0
DQ[0:7]/DM0/DQS0
DQ[8:15]/DM1/DQS1
DQ1
DQLMX1
DQLMY0
DQLMY1
1
0
DQ0 - DQ1 represent data bytes 0 - 1.
There are two DQLMs, one for each byte (16-bit interface). Each DQLM is the longest Manhattan distance of the byte;
therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
Figure 5-62. DQLM for Any Number of Allowed DDR3 Devices
Table 5-62. DQS[x] and DQ[x] Routing Specification(1)(2)
NO.
1
PARAMETER
MIN
TYP
MAX
DQLM0
DQLM1
25
UNIT
mils
mils
mils
mils
mils
DQ0 nominal length(3)(4)
DQ1 nominal length(3)(5)
DQ[x] skew(6)
2
3
4
DQS[x] skew
DQS[x]-to-DQ[x] skew(6)(7)
5
5
25
6
Center-to-center DQ[x] to other DDR3 trace spacing(8)(9)
Center-to-center DQ[x] to other DQ[x] trace spacing(8)(10)
DQS[x] center-to-center spacing(11)
4w
3w
7
8
9
DQS[x] center-to-center spacing to other net(8)
4w
(1) DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
(2) External termination disallowed. Data termination should use built-in ODT functionality.
(3) DQLMn is the longest Manhattan distance of a byte. For definition, see Section 5.5.2.3.6.2 and Figure 5-62.
(4) DQLM0 is the longest Manhattan length for the DQ0 net class.
(5) DQLM1 is the longest Manhattan length for the DQ1 net class.
(6) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
(7) Each DQS clock net class is length matched to its associated DQ signal net class.
(8) Center-to-center spacing is allowed to fall to minimum for up to 1250 mils of routed length.
(9) Other DDR3 trace spacing means signals that are not part of the same DQ[x] signal net class.
(10) This applies to spacing within same DQ[x] signal net class.
(11) DQS[x] pair spacing is set to ensure proper differential impedance.
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
5.6 Inter-Integrated Circuit (I2C)
For more information, see the Inter-Integrated Circuit (I2C) section of the AM335x ARM Cortex-A8
Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73).
5.6.1 I2C Electrical Data and Timing
Table 5-63. I2C Timing Conditions - Slave Mode
STANDARD MODE
MIN MAX
FAST MODE
MIN
TIMING CONDITION PARAMETER
UNIT
MAX
Output Condition
Cb
Capacitive load for each bus line
400
400
pF
Table 5-64. Timing Requirements for I2C Input Timings
(see Figure 5-63)
STANDARD MODE
FAST MODE
NO.
UNIT
MIN
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
us
us
Setup Time, SCL high before SDA low (for a repeated
START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
3
th(SDAL-SCLL)
us
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(1)
0(2)
us
us
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
th(SCLL-SDAV)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0(2)
3.45(3)
0.9(3) us
Pulse duration, SDA high between STOP and START
conditions
8
9
tw(SDAH)
tr(SDA)
4.7
1.3
us
(4)
Rise time, SDA
1000 20 + 0.1Cb
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300 ns
300 ns
300 ns
300 ns
us
(4)
(4)
(4)
10 tr(SCL)
Rise time, SCL
11 tf(SDA)
Fall time, SDA
12 tf(SCL)
Fall time, SCL
13 tsu(SCLH-SDAH)
14 tw(SP)
Setup time, high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
4
0
0.6
0
50
50 ns
(1) A fast-mode I2C-bus™ device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device stretches the LOW
period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the
standard-mode I2C-Bus Specification) before the SCL line is released.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(3) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(4) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall times are allowed.
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9
11
I2C[x]_SDA
6
8
14
4
13
5
10
I2C[x]_SCL
1
12
3
7
2
3
Stop
Start
Repeated
Start
Stop
Figure 5-63. I2C Receive Timing
Table 5-65. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
(see Figure 5-64)
STANDARD MODE
FAST MODE
NO.
PARAMETER
Cycle time, SCL
UNIT
MIN
MAX
MIN
MAX
15 tc(SCL)
10
2.5
us
us
Setup Time, SCL high before SDA low (for a repeated
START condition)
16 tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
17 th(SDAL-SCLL)
us
18 tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
us
us
ns
19 tw(SCLH)
Pulse duration, SCL high
20 tsu(SDAV-SCLH)
21 th(SCLL-SDAV)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0
3.45
0.9 us
Pulse duration, SDA high between STOP and START
conditions
22 tw(SDAH)
4.7
1.3
us
(1)
23 tr(SDA)
Rise time, SDA
1000 20 + 0.1Cb
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300 ns
300 ns
300 ns
300 ns
us
(1)
(1)
(1)
24 tr(SCL)
Rise time, SCL
25 tf(SDA)
Fall time, SDA
26 tf(SCL)
Fall time, SCL
27 tsu(SCLH-SDAH)
Setup time, high before SDA high (for STOP condition)
4
0.6
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall times are allowed.
26
24
I2C[x]_SDA
21
23
19
28
20
25
I2C[x]_SCL
27
16
18
22
17
18
Stop
Start
Repeated
Start
Stop
Figure 5-64. I2C Transmit Timing
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5.7 LCD Controller (LCDC)
The LCD controller consists of two independent controllers, the raster controller and the LCD interface
display driver (LIDD) controller. Each controller operates independently from the other and only one of
them is active at any given time.
•
The raster controller handles the synchronous LCD interface. It provides timing and data for constant
graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display
types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale/serializer.
Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous memory block
in the system. A built-in DMA engine supplies the graphics data to the raster engine which, in turn,
outputs to the external LCD device.
•
The LIDD controller supports the asynchronous LCD interface. It provides full-timing programmability of
control signals (CS, WE, OE, ALE) and output data.
The maximum resolution for the LCD controller is 2048 x 2048 pixels. The maximum frame rate is
determined by the image size in combination with the pixel clock rate.
Table 5-66. LCD Controller Timing Conditions
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Output Condition
LIDD mode
5
3
60
30
pF
pF
CLOAD Output load capacitance
Raster mode
5.7.1 LCD Interface Display Driver (LIDD Mode)
Table 5-67. Timing Requirements for LCD LIDD Mode
(see Figure 5-66 through Figure 5-74)
OPP100
NO.
PARAMETER
UNIT
MIN
MAX
Setup time, LCD_DATA[15:0] valid before
LCD_MEMORY_CLK high
16
tsu(LCD_DATA-LCD_MEMORY_CLK)
18
ns
Hold time, LCD_DATA[15:0] valid after
LCD_MEMORY_CLK high
17
18
th(LCD_MEMORY_CLK-LCD_DATA)
tt(LCD_DATA)
0
1
ns
pf
Transition time, LCD_DATA[15:0]
3
Table 5-68. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode
(see Figure 5-66 through Figure 5-74)
OPP100
NO.
PARAMETER
UNIT
MIN
23.7
MAX
1
2
3
tc(LCD_MEMORY_CLK)
tw(LCD_MEMORY_CLKH)
tw(LCD_MEMORY_CLKL)
Cycle time, LCD_MEMORY_CLK
ns
ns
ns
Pulse duration, LCD_MEMORY_CLK high
Pulse duration, LCD_MEMORY_CLK low
0.45tc
0.45tc
0.55tc
0.55tc
Delay time, LCD_MEMORY_CLK high to
LCD_DATA[15:0] valid (write)
4
5
td(LCD_MEMORY_CLK-LCD_DATAV)
td(LCD_MEMORY_CLK-LCD_DATAI)
td(LCD_MEMORY_CLK-LCD_AC_BIAS_EN)
tt(LCD_AC_BIAS_EN)
td(LCD_MEMORY_CLK-LCD_VSYNC)
tt(LCD_VSYNC)
7
ns
ns
Delay time, LCD_MEMORY_CLK high to
LCD_DATA[15:0] invalid (write)
0
Delay time, LCD_MEMORY_CLK high to
LCD_AC_BIAS_EN
6
7
0
1
0
1
0
6.8
10
7
ns
ns
ns
ns
ns
Transition time, LCD_AC_BIAS_EN
Delay time, LCD_MEMORY_CLK high to
LCD_VSYNC
8
9
Transition time, LCD_VSYNC
10
7
Delay time, LCD_MEMORY_CLK high to
LCD_HSYNC
10
td(LCD_MEMORY_CLK-LCD_HYSNC)
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Table 5-68. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD
Mode (continued)
(see Figure 5-66 through Figure 5-74)
OPP100
NO.
PARAMETER
UNIT
MIN
1
MAX
10
11
12
13
tt(LCD_HSYNC)
Transition time, LCD_HYSNC
ns
ns
ns
td(LCD_MEMORY_CLK-LCD_PCLK)
tt(LCD_PCLK)
Delay time, LCD_MEMORY_CLK high to LCD_PCLK
Transition time, LCD_PCLK
0
7
1
10
Delay time, LCD_MEMORY_CLK high to
LCD_DATA[15:0] high-Z
14
15
td(LCD_MEMORY_CLK-LCD_DATAZ)
td(LCD_MEMORY_CLK-LCD_DATA)
0
0
7
7
ns
ns
Delay time, LCD_MEMORY_CLK high to
LCD_DATA[15:0] driven
19
20
tt(LCD_MEMORY_CLK)
tt(LCD_DATA)
Transition time, LCD_MEMORY_CLK
Transition time, LCD_DATA
1
1
2.5
10
ns
ns
CS_DELAY
(0 to 3)
W_SU
(0 to 31)
W_STROBE
(1 to 63)
W_HOLD
(1 to 15)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
7
4
8
5
8
LCD_DATA[7:0]
Write Instruction
LCD_VSYNC
(RS)
9
10
10
LCD_HSYNC
(R/W)
11
6
6
LCD_AC_BIAS_EN
(E0)
7
A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
Figure 5-65. Command Write in Hitachi Mode
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
CS_DELAY
(0 to 3)
W_SU
(0 to 31)
W_STROBE
(1 to 63)
W_HOLD
(1 to 15)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
7
4
5
LCD_DATA[15:0]
Write Data
20
10
LCD_VSYNC
(RS)
10
11
LCD_HSYNC
(R/W)
6
6
LCD_AC_BIAS_EN
(E0)
7
A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
Figure 5-66. Data Write in Hitachi Mode
R_SU
(0 to 31)
R_HOLD
(1 to 15)
CS_DELAY
(0 to 3)
R_STROBE
(1 to 63)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
7
17
16
15
8
14
8
LCD_DATA[15:0]
Read Command
18
LCD_VSYNC
(RS)
9
LCD_HSYNC
(R/W)
6
6
LCD_AC_BIAS_EN
(E0)
7
A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
Figure 5-67. Command Read in Hitachi Mode
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R_SU
(0 to 31)
R_HOLD
(1 to 15)
CS_DELAY
(0 to 3)
R_STROBE
(1 to 63)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
7
17
16
15
14
LCD_DATA[15:0]
Read Data
18
LCD_VSYNC
(RS)
LCD_HSYNC
(R/W)
6
6
LCD_AC_BIAS_EN
(E0)
7
A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
Figure 5-68. Data Read in Hitachi Mode
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
W_HOLD
(1−15)
W_HOLD
(1−15)
W_SU
(0−31)
W_SU
(0−31)
1
W_STROBE
(1−63)
W_STROBE
(1−63)
2
CS_DELAY
(0−3)
CS_DELAY
(0−3)
3
LCD_MEMORY_CLK
(MCLK) Sync Mode
19
6
6
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
7
5
4
4
5
LCD_DATA[15:0]
Write Address
Write Data
20
6
6
6
6
LCD_AC_BIAS_EN
(CS0)
7
8
8
LCD_VSYNC
(ALE)
9
10
10
10
10
LCD_HSYNC
(DIR)
11
12
13
12
12
12
LCD_PCLK
(EN)
A. Motorola mode can be configured to perform asynchronous operations or synchronous operations. When configured
in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 5-69. Micro-Interface Graphic Display Motorola Write
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W_HOLD
(1−15)
R_SU
(0−31)
W_SU
(0−31)
R_HOLD
(1−15)
1
W_STROBE
(1−63)
R_STROBE
(1−63)
2
CS_DELAY
(0−3)
CS_DELAY
(0−3)
3
LCD_MEMORY_CLK
(MCLK) Sync Mode
19
6
6
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
7
5
16
18
4
14
15
17
LCD_DATA[15:0]
Write Address
20
6
Read
Data
6
6
6
LCD_AC_BIAS_EN
(CS0)
7
8
8
LCD_VSYNC
(ALE)
9
10
10
LCD_HSYNC
(DIR)
11
12
13
12
12
12
LCD_PCLK
(EN)
A. Motorola mode can be configured to perform asynchronous operations or synchronous operations. When configured
in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 5-70. Micro-Interface Graphic Display Motorola Read
186
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
R_SU
(0−31)
1
R_HOLD
(1−15)
R_STROBE
(1−63)
2
CS_DELAY
(0−3)
3
LCD_MEMORY_CLK
(MCLK) Sync Mode
19
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
7
16
14
15
17
LCD_DATA[15:0]
Read
Status
18
6
6
8
LCD_AC_BIAS_EN
(CS0)
7
8
LCD_VSYNC
(ALE)
9
LCD_HSYNC
(DIR)
12
12
LCD_PCLK
(EN)
13
A. Motorola mode can be configured to perform asynchronous operations or synchronous operations. When configured
in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 5-71. Micro-Interface Graphic Display Motorola Status
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W_HOLD
(1−15)
W_HOLD
(1−15)
W_SU
(0−31)
W_SU
(0−31)
1
W_STROBE
(1−63)
W_STROBE
2
(1−63)
Write Data
10
CS_DELAY
(0−3)
CS_DELAY
(0−3)
3
LCD_MEMORY_CLK
(MCLK) Sync Mode
19
6
6
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
7
4
5
4
5
LCD_DATA[15:0]
Write Address
20
6
6
8
6
6
LCD_AC_BIAS_EN
(CS0)
7
8
LCD_VSYNC
(ALE)
9
10
11
10
10
LCD_HSYNC
(WS)
LCD_PCLK
(RS)
A. Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in
asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 5-72. Micro-Interface Graphic Display Intel Write
188
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
W_HOLD
(1−15)
R_SU
(0−31)
W_SU
(0−31)
R_HOLD
(1−15)
1
W_STROBE
(1−63)
R_STROBE
(1−63)
2
CS_DELAY
(0−3)
CS_DELAY
(0−3)
3
LCD_MEMORY_CLK
(MCLK) Sync Mode
19
6
6
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
7
4
16
5
14
15
17
LCD_DATA[15:0]
Write Address
18
20
6
Read
Data
6
8
6
6
LCD_AC_BIAS_EN
(CS0)
7
8
LCD_VSYNC
(ALE)
9
10
11
10
LCD_HSYNC
(WS)
12
12
LCD_PCLK
(RS)
13
A. Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in
asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 5-73. Micro-Interface Graphic Display Intel Read
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R_SU
(0−31)
1
R_HOLD
(1−15)
R_STROBE
(1−63)
2
CS_DELAY
(0−3)
3
LCD_MEMORY_CLK
(MCLK) Sync Mode
19
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
7
16
14
15
17
LCD_DATA[15:0]
Read
Status
18
6
6
8
LCD_AC_BIAS_EN
(CS0)
7
8
LCD_VSYNC
(ALE)
9
LCD_HSYNC
(WS)
12
12
LCD_PCLK
(RS)
13
A. Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in
asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 5-74. Micro-Interface Graphic Display Intel Status
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
5.7.2 LCD Raster Mode
Table 5-69. Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode
(see Figure 5-76 through Figure 5-79)
OPP50
MIN
OPP100
MIN
NO.
PARAMETER
UNIT
MAX
MAX
1
2
3
tc(LCD_PCLK)
tw(LCD_PCLKH)
tw(LCD_PCLKL)
Cycle time, pixel clock
7.9
0.45tc
0.45tc
7.9
ns
ns
ns
Pulse duration, pixel clock high
Pulse duration, pixel clock low
0.55tc
0.55tc
0.45tc
0.45tc
0.55tc
0.55tc
Delay time, LCD_PCLK to LCD_DATA[23:0] valid
(write)
4
5
td(LCD_PCLK-LCD_DATAV)
td(LCD_PCLK-LCD_DATAI)
1
1
ns
ns
Delay time, LCD_PCLK to LCD_DATA[23:0] invalid
(write)
-1.5
-1
6
7
8
9
td(LCD_PCLK-LCD_AC_BIAS_EN) Delay time, LCD_PCLK to LCD_AC_BIAS_EN
-1.5
0.5
-1.5
0.5
-1.5
0.5
0.5
0.5
1
2.4
1
-1
0.5
-1
1
2.4
1
ns
ns
ns
ns
ns
ns
ns
ns
tt(LCD_AC_BIAS_EN)
td(LCD_PCLK-LCD_VSYNC)
tt(LCD_VSYNC)
Transition time, LCD_AC_BIAS_EN
Delay time, LCD_PCLK to LCD_VSYNC
Transition time, LCD_VSYNC
2.4
1
0.5
-1
2.4
1
10 td(LCD_PCLK-LCD_HSYNC)
11 tt(LCD_HSYNC)
12 tt(LCD_PCLK)
Delay time, LCD_PCLK to LCD_HSYNC
Transition time, LCD_HSYNC
2.4
2.4
2.4
0.5
0.5
0.5
2.4
2.4
2.4
Transition time, LCD_PCLK
13 tt(LCD_DATA)
Transition time, LCD_DATA
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:
•
•
•
•
Vertical front porch (VFP)
Vertical sync pulse width (VSW)
Vertical back porch (VBP)
Lines per panel (LPP_B10 + LPP)
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
•
•
•
•
Horizontal front porch (HFP)
Horizontal sync pulse width (HSW)
Horizontal back porch (HBP)
Pixels per panel (PPLMSB + PPLLSB)
LCD_AC_BIAS_EN timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:
•
AC bias frequency (ACB)
The display format produced in raster mode is shown in Figure 5-75. An entire frame is delivered one line
at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of I/O signal LCD_HSYNC.
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Data Pixels (From 1 to P)
P−2,
1
P−1,
1
1, 1
1, 2
1, 3
2, 1
2, 2
3, 1
P, 1
P, 2
P, 3
P−1,
2
LCD
1,
L−2
P,
L−2
1,
L−1
2,
L−1
P−1,
L−1
P,
L−1
P−2,
L
P−1,
L
1, L
2, L
3, L
P, L
Figure 5-75. LCD Raster-Mode Display Format
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Frame Time
LPP_B10 + LPP
(1 to 2048)
VSW
VBP
VFP
VSW
(1 to 64)
(0 to 255)
(1 to 64)
(0 to 255)
Line
Time
LCD_HSYNC
LCD_VSYNC
LCD_DATA[23:0]
1, 1 1, 2
P, 1 P, 2
1, L-1 1, L
P, L-1 P, L
LCD_AC_BIAS_EN
(ACTVID)
10
10
LCD_HSYNC
11
LCD_PCLK
LCD_DATA[23:0]
2, 1
1, 2
P, 2
P, 1
1, 1
2, 2
LCD_AC_BIAS_EN
(ACTVID)
PPLMSB + PPLLSB
16 × (1 to 2048)
Line 2
PPLMSB + PPLLSB
16 × (1 to 2048)
Line 1
HFP
(1 to 256)
HSW
HBP
(1 to 256)
(1 to 64)
Figure 5-76. LCD Raster-Mode Active
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Frame Time
VBP = 0
VFP = 0
VSW = 1
LPP_B10 + LPP
(1 to 2048)
Line
Time
LCD_HSYNC
LCD_VSYNC
1, L
Data
1, L:
P, L
1, 1:
P, 1
1, 2:
P, 2
1, 3:
P, 3
1, 4:
P, 4
1, 5:
P, 5
1, 6:
P, 6
1, L
P, L
1, 1
P, 1
1, 2
P, 2
LCD_DATA[7:0]
1, L−1
P, L−1
1, L−4
P, L−4
1, L−3 1, L−2 1, L−1
P, L−1
P, L−3 P, L−2
LCD_AC_BIAS_EN
ACB
ACB
(0 to 255)
(0 to 255)
10
11
10
LCD_HSYNC
LCD_PCLK
1, 5 2, 5
P, 5
1, 6 2, 6
P, 6
LCD_DATA[7:0]
PPLMSB + PPLLSB
16 x (1 to 2048)
Line 5
HFP
HSW
HBP
PPLMSB + PPLLSB
16 x (1 to 2048)
Line 6
(1 to 256)
(1 to 64)
(1 to 256)
A. The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
Figure 5-77. LCD Raster-Mode Passive
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
6
LCD_AC_BIAS_EN
7
8
LCD_VSYNC
LCD_HSYNC
9
10
10
11
1
2
3
LCD_PCLK
(passive mode)
4
5
LCD_DATA[7:0]
(passive mode)
1, L 2, L
P, L
1, 1 2, 1
P, 1
1
3
2
LCD_PCLK
(active mode)
4
5
LCD_DATA[23:0]
(active mode)
1, L 2, L
P, L
VBP = 0
VFP = 0
VWS = 1
PPLMSB + PPLLSB
16 x (1 to 2048)
PPLMSB + PPLLSB
16 x (1 to 2048)
HSW
HBP
HFP
(1 to 256)
(1 to 64)
(1 to 256)
Line L
Line 1 (Passive Only)
A. The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
Figure 5-78. LCD Raster-Mode Control Signal Activation
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6
LCD_AC_BIAS_EN
8
LCD_VSYNC
LCD_HSYNC
10
10
11
1
2
3
LCD_PCLK
(passive mode)
4
5
LCD_D[7:0]
(passive mode)
1, 1 2, 1
P, 1
1, 2 2, 2
P, 2
1
3
2
LCD_PCLK
(active mode)
4
5
LCD_DATA[23:0]
(active mode)
1, 1 2, 1
P, 1
VBP = 0
VFP = 0
VWS = 1
PPLMSB + PPLLSB
16 x (1 to 2048)
PPLMSB + PPLLSB
16 x (1 to 2048)
HSW
HBP
HFP
(1 to 256)
(1 to 64)
(1 to 256)
Line 1
Line 1 for active
Line 2 for passive
A. The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
Figure 5-79. LCD Raster-Mode Control Signal Deactivation
196
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
5.8 Multichannel Audio Serial Port (McASP)
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission
(DIT).
Operation of the McASP is not supported for OPP50.
5.8.1 McASP Device-Specific Information
The device includes two multichannel audio serial port (McASP) interface peripherals (McASP0 and
McASP1). The McASP module consists of a transmit and receive section. These sections can operate
completely independently with different data formats, separate master clocks, bit clocks, and frame syncs
or, alternatively, the transmit and receive sections may be synchronized. The McASP module also
includes shift registers that may be configured to operate as either transmit data or receive data.
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM)
synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for
S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP peripheral supports
the TDM synchronous serial format.
The McASP module can support one transmit data format (either a TDM format or DIT format) and one
receive format at a time. All transmit shift registers use the same format and all receive shift registers use
the same format; however, the transmit and receive formats need not be the same. Both the transmit and
receive sections of the McASP also support burst mode, which is useful for non-audio data (for example,
passing control information between two devices).
The McASP peripheral has additional capability for flexible clock generation and error detection/handling,
as well as error management.
The device McASP0 and McASP1 modules have up to four serial data pins each. The McASP FIFO size
is 256 bytes and two DMA and two interrupt requests are supported. Buffers are used transparently to
better manage DMA, which can be leveraged to manage data flow more efficiently.
For more detailed information on and the functionality of the McASP peripheral, see the Multichannel
Audio Serial Port (McASP) section of the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical
Reference Manual (literature number SPRUH73).
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5.8.2 McASP Electrical Data and Timing
Table 5-70. McASP Timing Conditions
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1(1)
1(1)
4(1)
4(1)
ns
ns
Output Condition
CLOAD Output load capacitance
15
30
pF
(1) Except when specified otherwise.
Table 5-71. Timing Requirements for McASP(1)
(see Figure 5-80)
NO.
MIN
MAX UNIT
1
2
3
4
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
Cycle time, MCA[x]_AHCLKR/X
20
ns
0.5P -
2.5(2)
Pulse duration, MCA[x]_AHCLKR/X high or low
Cycle time, MCA[x]_ACLKR/X
ns
ns
ns
20
0.5R -
2.5(3)
Pulse duration, MCA[x]_ACLKR/X high or low
ACLKR/X int
11.5
ACLKR/X ext
in
tsu(AFSRX-
ACLKRX)
Setup time, MCA[x]_AFSR/X input valid before
MCA[X]_ACLKR/X
4
5
6
7
8
ns
ns
ns
ns
ACLKR/X ext
out
4
-1
2
ACLKR/X int
ACLKR/X ext
th(ACLKRX-
AFSRX)
Hold time, MCA[x]_AFSR/X input valid after MCA[X]_ACLKR/X in
ACLKR/X ext
out
2
11.5
4
ACLKR/X int
ACLKR/X ext
in
tsu(AXR-ACLKRX) Setup time, MCA[x]_AXR input valid before MCA[X]_ACLKR/X
ACLKR/X ext
out
4
-1
2
ACLKR/X int
ACLKR/X ext
in
th(ACLKRX-AXR)
Hold time, MCA[x]_AXR input valid after MCA[X]_ACLKR/X
ACLKR/X ext
out
2
(1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
(2) P = MCA[x]_AHCLKR/X period in nano seconds (ns).
(3) R = MCA[x]_ACLKR/X period in ns.
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2
1
2
MCA[x]_ACLKR/X (Falling Edge Polarity)
MCA[x]_AHCLKR/X (Rising Edge Polarity)
4
4
3
MCA[x]_ACLKR/X (CLKRP = CLKXP = 0)(A)
MCA[x]_ACLKR/X (CLKRP = CLKXP = 1)(B)
6
5
MCA[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCA[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCA[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 2 Bit Delay)
8
7
MCA[x]_AXR[x] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 5-80. McASP Input Timing
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Table 5-72. Switching Characteristics Over Recommended Operating Conditions for McASP(1)
(see Figure 5-81)
NO.
MIN
MAX UNIT
9
tc(AHCLKRX)
Cycle time, MCA[X]_AHCLKR/X
20(2)
ns
0.5P -
2.5(3)
10 tw(AHCLKRX)
11 tc(ACLKRX)
12 tw(ACLKRX)
Pulse duration, MCA[X]_AHCLKR/X high or low
Cycle time, MCA[X]_ACLKR/X
ns
20
ns
0.5P -
2.5(3)
Pulse duration, MCA[X]_ACLKR/X high or low
ns
ACLKR/X int
0
1
6
Delay time, MCA[X]_ACLKR/X transmit edge to
MCA[X]_AFSR/X output valid
ACLKR/X ext in
13.5
ns
13 td(ACLKRX-AFSRX)
14 td(ACLKX-AXR)
15 tdis(ACLKX-AXR)
Delay time, MCA[X]_ACLKR/X transmit edge to
MCA[X]_AFSR/X output valid with Pad Loopback
ACLKR/X ext out
1
13.5
ACLKX int
0
1
6
Delay time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output valid
ACLKX ext in
13.5
ns
Delay time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output valid with Pad Loopback
ACLKX ext out
1
13.5
ACLKX int
0
1
6
Disable time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output high impedance
ACLKX ext in
13.5
ns
Disable time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output high impedance with Pad Loopback
ACLKX ext out
1
13.5
(1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
(2) 50 MHz
(3) P = AHCLKR/X period.
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
10
10
9
MCA[x]_ACLKR/X (Falling Edge Polarity)
MCA[x]_AHCLKR/X (Rising Edge Polarity)
12
11
12
MCA[x]_ACLKR/X (CLKRP = CLKXP = 1)(A)
MCA[x]_ACLKR/X (CLKRP = CLKXP = 0)(B)
13
13
13
13
MCA[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCA[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCA[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 2 Bit Delay)
13
13
13
MCA[x]_AXR[x] (Data Out/Transmit)
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 5-81. McASP Output Timing
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5.9 Multichannel Serial Port Interface (McSPI)
For more information, see the Multichannel Serial Port Interface (McSPI) section of the AM335x ARM
Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73).
5.9.1 McSPI Electrical Data and Timing
The following timings are applicable to the different configurations of McSPI in master or slave mode for
any McSPI and any channel (n).
5.9.1.1 McSPI—Slave Mode
Table 5-73. McSPI Timing Conditions—Slave Mode
TIMING CONDITION PARAMETER
MIN
MAX UNIT
Input Conditions
tr
Input signal rise time
5
5
ns
ns
tf
Input signal fall time
Output Condition
Cload
Output load capacitance
20
pF
Table 5-74. Timing Requirements for McSPI Input Timings—Slave Mode
(see Figure 5-82)
NO.
MIN
MAX UNIT
1
2
3
4
5
8
9
tc(SPICLK)
Cycle time, SPI_CLK
62.5
0.5P(1)
0.5P(1)
12.92
12.92
12.92
12.92
ns
tw(SPICLKL)
Typical Pulse duration, SPI_CLK low
0.5P(1)
0.5P(1)
ns
ns
ns
ns
ns
ns
tw(SPICLKH)
Typical Pulse duration, SPI_CLK high
tsu(SIMO-SPICLK)
th(SPICLK-SIMO)
tsu(CS-SPICLK)
th(SPICLK-CS)
Setup time, SPI_D[x] (SIMO) valid before SPI_CLK active edge(2)(3)
Hold time, SPI_D[x] (SIMO) valid after SPI_CLK active edge(2)(3)
Setup time, SPI_CS valid before SPI_CLK first edge(2)
Hold time, SPI_CS valid after SPI_CLK last edge(2)
(1) P = SPI_CLK period.
(2) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and
capture input data.
(3) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
Table 5-75. Switching Characteristics Over Recommended Operating Conditions for McSPI Output
Timings—Slave Mode
(see Figure 5-83)
NO.
6
PARAMETER
MIN
MAX UNIT
td(SPICLK-SOMI)
td(CS-SOMI)
Delay time, SPI_CLK active edge to SPI_D[x] (SOMI) transition(1)(2)
Delay time, SPI_CS active edge to SPI_D[x] (SOMI) transition(1)(2)
-4.00
17.12
17.12
ns
ns
7
(1) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and
capture input data.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
PHA=0
EPOL=1
SPI_CS[x] (In)
1
1
3
3
8
2
2
9
POL=0
POL=1
SPI_SCLK (In)
SPI_SCLK (In)
4
4
5
5
SPI_D[x] (SIMO, In)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (In)
SPI_SCLK (In)
1
3
2
8
2
3
9
POL=0
POL=1
1
SPI_SCLK (In)
4
4
5
5
SPI_D[x] (SIMO, In)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 5-82. SPI Slave Mode Receive Timing
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PHA=0
EPOL=1
SPI_CS[x] (In)
1
1
3
3
8
2
2
9
POL=0
SPI_SCLK (In)
POL=1
SPI_SCLK (In)
6
7
6
SPI_D[x] (SOMI, Out)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (In)
1
1
3
2
8
2
3
9
POL=0
SPI_SCLK (In)
POL=1
SPI_SCLK (In)
6
6
6
6
SPI_D[x] (SOMI, Out)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 5-83. SPI Slave Mode Transmit Timing
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5.9.1.2 McSPI—Master Mode
Table 5-76. McSPI Timing Conditions—Master Mode
LOW LOAD
MIN
HIGH LOAD
MIN
TIMING CONDITION PARAMETER
UNIT
MAX
MAX
Input Conditions
tr
tf
Input signal rise time
Input signal fall time
8
8
16
16
ns
ns
Output Condition
Cload
Output load capacitance
5
25
pF
Table 5-77. Timing Requirements for McSPI Input Timings—Master Mode
(see Figure 5-84)
LOW LOAD
HIGH LOAD
NO.
UNIT
MIN
MAX
MIN
MAX
Setup time, SPI_D[x] (SOMI) valid before SPI_CLK active
edge(1)
4
5
tsu(SOMI-SPICLKH)
th(SPICLKH-SOMI)
2.29
3.02
ns
ns
Hold time, SPI_D[x] (SOMI) valid after SPI_CLK active
edge(1)
2.67
2.76
(1) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
Table 5-78. Switching Characteristics Over Recommended Operating Conditions for McSPI Output
Timings—Master Mode
(see Figure 5-85)
LOW LOAD
HIGH LOAD
NO.
PARAMETER
Cycle time, SPI_CLK
UNIT
MIN
20.8
MAX
MIN
20.8
MAX
1
2
tc(SPICLK)
tw(SPICLKL)
tw(SPICLKH)
tr(SPICLK)
tf(SPICLK)
ns
ns
ns
ns
ns
Typical Pulse duration, SPI_CLK low
Typical Pulse duration, SPI_CLK high
Rising time, SPI_CLK
0.5P(1)
0.5P(1)
0.5P(1)
0.5P(1)
3.82
0.5P(1)
0.5P(1)
TBD
TBD
3
10.685
10.685
Falling time, SPI_CLK
3.44
Delay time, SPI_CLK active edge to SPI_D[x] (SIMO)
transition(2)
6
7
td(SPICLK-SIMO)
td(CS-SIMO)
td(CS-SPICLK)
-3.57
3.57
3.57
-4.62
4.62
4.62
ns
ns
Delay time, SPI_CS active edge to SPI_D[x] (SIMO)
transition(2)
Mode 1 and 3(3)
A-4.2(4)
B-4.2(5)
B-4.2(5)
A-4.2(4)
A-2.54(4)
B-2.54(5)
B-2.54(5)
A-2.54(4)
ns
ns
ns
ns
Delay time, SPI_CS active to SPI_CLK
first edge
8
9
Mode 0 and 2(3)
Mode 1 and 3(3)
Mode 0 and 2(3)
Delay time, SPI_CLK last edge to
SPI_CS inactive
td(SPICLK-CS)
(1) P = SPI_CLK period.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
(3) The polarity of SPIx_CLK and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable:
–
–
SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).
SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).
(4) Case P = 20.8 ns, A = (TCS+1)*TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
Case P > 20.8 ns, A = (TCS+0.5)*Fratio*TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
Note: P = SPI_CLK clock period.
(5) B = (TCS+0.5)*TSPICLKREF*Fratio (TCS is a bit field of MCSPI_CH(i)CONF register, Fratio: Even≥2).
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PHA=0
EPOL=1
SPI_CS[x] (Out)
1
1
3
2
8
2
3
9
POL=0
SPI_SCLK (Out)
POL=1
SPI_SCLK (Out)
4
4
5
5
SPI_D[x] (SOMI, In)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (Out)
1
2
1
3
3
2
8
9
POL=0
SPI_SCLK (Out)
POL=1
SPI_SCLK (Out)
4
4
5
5
SPI_D[x] (SOMI, In)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 5-84. SPI Master Mode Receive Timing
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
PHA=0
EPOL=1
SPI_CS[x] (Out)
1
1
3
2
8
2
3
9
POL=0
POL=1
SPI_SCLK (Out)
SPI_SCLK (Out)
6
7
6
SPI_D[x] (SIMO, Out)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (Out)
SPI_SCLK (Out)
1
3
2
8
2
3
9
POL=0
POL=1
1
SPI_SCLK (Out)
6
6
6
6
SPI_D[x] (SIMO, Out)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 5-85. SPI Master Mode Transmit Timing
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5.10 Multimedia Card (MMC) Interface
For more information, see the Multimedia Card (MMC) section of the AM335x ARM Cortex-A8
Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73).
5.10.1 MMC Electrical Data and Timing
Table 5-79. MMC Timing Conditions
TIMING CONDITION PARAMETER
MIN
TYP
MAX UNIT
Input Conditions
tr
tf
Input signal rise time
Input signal fall time
1
1
5
5
ns
ns
Output Condition
Cload
Output load capacitance
3
30
pF
Table 5-80. Timing Requirements for MMC[x]_CMD and MMC[x]_DAT[7:0]
(see Figure 5-86)
NO.
MIN
4.1
1.9
4.1
1.9
TYP
MAX
UNIT
Setup time, MMC_CMD valid before MMC_CLK rising clock
edge
1
2
3
4
tsu(CMDV-CLKH)
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
ns
ns
ns
ns
Hold time, MMC_CMD valid after MMC_CLK rising clock edge
Setup time, MMC_DATx valid before MMC_CLK rising clock
edge
Hold time, MMC_DATx valid after MMC_CLK rising clock edge
1
2
MMC[x]_CLK (Output)
MMC[x]_CMD (Input)
MMC[x]_DAT[7:0] (Inputs)
3
4
Figure 5-86. MMC[x]_CMD and MMC[x]_DAT[7:0] Input Timing
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
Table 5-81. Switching Characteristics for MMC[x]_CLK
(see Figure 5-87)
STANDARD MODE
HIGH-SPEED MODE
MIN TYP MAX
NO.
PARAMETER
UNIT
MIN TYP MAX
fop(CLK)
Operating frequency, MMC_CLK
Operating period: MMC_CLK
24
48 MHz
ns
tcop(CLK)
41.7
20.8
5
fid(CLK)
Identification mode frequency, MMC_CLK
Identification mode period: MMC_CLK
400
400 kHz
ns
tcid(CLK)
2500
2500
(0.5*P) -
tf(CLK)
(0.5*P) -
tf(CLK)
6
7
tw(CLKL)
tw(CLKH)
Pulse duration, MMC_CLK low
Pulse duration, MMC_CLK high
ns
ns
(1)
(1)
(0.5*P) -
(0.5*P) -
(1)
(1)
tr(CLK)
tr(CLK)
8
9
tr(CLK)
tf(CLK)
Rise time, All Signals (10% to 90%)
Fall time, All Signals (10% to 90%)
2.2
2.2
2.2 ns
2.2 ns
(1) P = MMC_CLK period.
5
6
7
8
9
RMII[x]_REFCLK
(Input)
Figure 5-87. MMC[x]_CLK Timing
Table 5-82. Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—Standard Mode
(see Figure 5-88)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
Delay time, MMC_CLK falling clock edge to MMC_CMD
transition
10
td(CLKL-CMD)
td(CLKL-DAT)
-4
14
ns
Delay time, MMC_CLK falling clock edge to MMC_DATx
transition
11
-4
14
ns
10
MMC[x]_CLK (Output)
MMC[x]_CMD (Output)
MMC[x]_DAT[7:0] (Outputs)
11
Figure 5-88. MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing—Standard Mode
Copyright © 2011–2012, Texas Instruments Incorporated
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Table 5-83. Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—High-Speed Mode
(see Figure 5-89)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
Delay time, MMC_CLK rising clock edge to MMC_CMD
transition
12
td(CLKL-CMD)
td(CLKL-DAT)
2.5
14
ns
Delay time, MMC_CLK rising clock edge to MMC_DATx
transition
13
2.5
14
ns
12
MMC[x]_CLK (Output)
MMC[x]_CMD (Output)
MMC[x]_DAT[7:0] (Outputs)
13
Figure 5-89. MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing—High Speed Mode
210
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5.11 Universal Asynchronous Receiver Transmitter (UART)
For more information, see the Universal Asynchronous Receiver Transmitter (UART) section of the
AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number
SPRUH73).
5.11.1 UART Electrical Data and Timing
Table 5-84. Timing Requirements for UARTx Receive
(see Figure 5-90)
NO.
MIN
MAX
UNIT
3
tw(RX)
Pulse width, receive start, stop, data bit
0.96U(1)
1.05U(1)
ns
(1) U = UART baud time = 1/programmed baud rate.
Table 5-85. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit
(see Figure 5-90)
NO.
1
PARAMETER
Maximum programmable baud rate
Pulse width, transmit start, stop, data bit
MIN
MAX
3.6864
U + 2(1)
UNIT
MHz
ns
fbaud(baud)
tw(TX)
2
U - 2(1)
(1) U = UART baud time = 1/programmed baud rate.
2
2
2
Start
Bit
UARTx_TXD
Stop Bit
Data Bits
3
3
3
Start
Bit
UARTx_RXD
Stop Bit
Data Bits
Figure 5-90. UART Timings
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5.11.2 UART IrDA Interface
The IrDA module operates in three different modes:
•
•
•
Slow infrared (SIR) (≤ 115.2 Kbits/s)
Medium infrared (MIR) (0.576 Mbits/s and 1.152 Mbits/s)
Fast infrared (FIR) (4 Mbits/s).
Figure 5-91 illustrates the UART IrDA pulse parameters. Table 5-86 and Table 5-87 list the signaling rates
and pulse durations for UART IrDA receive and transmit modes.
Pulse Duration
Pulse Duration
50%
50%
50%
Figure 5-91. UART IrDA Pulse Parameters
Table 5-86. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode
ELECTRICAL PULSE DURATION
SIGNALING RATE
UNIT
MIN
MAX
SIR
2.4 Kbits/s
1.41
1.41
1.41
1.41
1.41
1.41
88.55
22.13
11.07
5.96
µs
µs
µs
µs
µs
µs
9.6 Kbits/s
19.2 Kbits/s
38.4 Kbits/s
57.6 Kbits/s
115.2 Kbits/s
MIR
4.34
2.23
0.576 Mbits/s
1.152 Mbits/s
FIR
297.2
149.6
518.8
258.4
ns
ns
4 Mbits/s (Single pulse)
4 Mbits/s (Double pulse)
67
164
289
ns
ns
190
212
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Table 5-87. UART IrDA—Signaling Rate and Pulse Duration—Transmit Mode
ELECTRICAL PULSE DURATION
MIN
SIGNALING RATE
UNIT
MAX
SIR
2.4 Kbits/s
78.1
19.5
9.75
4.87
3.25
1.62
78.1
19.5
9.75
4.87
3.25
1.62
µs
µs
µs
µs
µs
µs
9.6 Kbits/s
19.2 Kbits/s
38.4 Kbits/s
57.6 Kbits/s
115.2 Kbits/s
MIR
0.576 Mbits/s
1.152 Mbits/s
FIR
414
206
419
211
ns
ns
4 Mbits/s (Single pulse)
4 Mbits/s (Double pulse)
123
248
128
253
ns
ns
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6 Device and Documentation Support
6.1 Device Support
6.1.1 Development Support
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
The following products support development of AM335x device applications:
Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any AM335x device application. DSP/BIOS™
Hardware Development Tools: Extended Development System (XDS™) Emulator XDS™
For a complete listing of development-support tools for the AM335x microprocessor platform, visit the
Texas Instruments website at www.ti.com. For information on pricing and availability, contact the nearest
TI field sales office or authorized distributor.
6.1.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(e.g., XAM3358ZCE). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices/tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
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TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZCE), the temperature range (for example, blank is the default commercial
temperature range), and the device speed range, in megahertz (for example, 27 is 275 MHz). Figure 6-1
provides a legend for reading the complete device name for any AM335x device.
For orderable part numbers of AM335x devices in the ZCE and ZCZ package types, see the Package
Option Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the AM335x ARM Cortex-
A8 Microprocessors (MPUs) Silicon Errata (literature number SPRZ360).
(
)
X
(
)
AM3358
(
)
ZCE
PREFIX
DEVICE SPEED RANGE
27 = 275-MHZ Cortex-A8
50 = 500-MHZ Cortex-A8
60 = 600-MHZ Cortex-A8
72 = 720-MHz Cortex-A8
X = Experimental device
Blank = Qualified device
DEVICE(A)
ARM Cortex-A8 MPU:
AM3352
AM3354
AM3356
AM3357
AM3358
AM3359
TEMPERATURE RANGE
Blank = 0°C to 90°C (commercial junction temperature)
A = -40°C to 105°C (extended temperature)
D = -40°C to 90°C (industrial temperature)
PACKAGE TYPE(B)
ZCE = 298-pin plastic BGA, with Pb-Free solder balls
ZCZ = 324-pin plastic BGA, with Pb-Free solder balls
SILICON REVISION
Blank = silicon revision 1.0
A. The AM3358 device shown in this device nomenclature example is one of several valid part numbers for the AM335x
family of devices. For orderable device part numbers, see the Package Option Addendum of this document.
B. BGA = Ball Grid Array.
Figure 6-1. AM335x Device Nomenclature
6.2 Documentation Support
6.2.1 Related Documentation from Texas Instruments
The following documents describe the AM335x MPU. Copies of these documents are available on the
Internet at www.ti.com. Tip: Enter the literature number in the search box.
The current documentation that describes the AM335x MPU, related peripherals, and other technical
collateral, is available in the product folder at: www.ti.com.
SPRUH73 AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual.
Collection of documents providing detailed information on the AM335x device including
power, reset, and clock control, interrupts, memory map, and switch fabric interconnect.
Detailed information on the microprocessor unit (MPU) subsystem as well as a functional
description of the peripherals supported on AM335x devices is also included.
SPRZ360
AM335x ARM Cortex-A8 Microprocessors (MPUs) Silicon Errata. Describes the known
exceptions to the functional specifications for the AM335x ARM Cortex-A8 Microprocessors.
6.2.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and
help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
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innovation and growth of general knowledge about the hardware and software surrounding
these devices.
6.2.3 Related Documentation from Other Sources
The following documents are related to the AM335x MPU. Copies of these documents can be obtained
directly from the internet or from your Texas Instruments representative.
Cortex-A8 Technical Reference Manual. This is the technical reference manual for the Cortex-A8
processor. A copy of this document can be obtained via the internet at http://infocenter.arm.com. To
determine the revision of the Cortex-A8 core used on your device, see the AM335x ARM Cortex-A8
Microprocessors (MPUs) Silicon Errata (literature number SPRZ360).
ARM Core Cortex™-A8 (AT400/AT401) Errata Notice. Provides a list of advisories for the different
revisions of the Cortex-A8 processor. Contact your TI representative for a copy of this document. To
determine the revision of the Cortex-A8 core used on your device, see the AM335x ARM Cortex-A8
Microprocessors (MPUs) Silicon Errata (literature number SPRZ360).
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SPRS717D –OCTOBER 2011–REVISED MAY 2012
7 Mechanical Packaging and Orderable Information
7.1 Thermal Data for ZCE and ZCZ Packages
Table 7-1 provides thermal characteristics for the packages used on this device.
NOTE
Table 7-1 provides simulation data and may not represent actual use-case values.
Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZCE and ZCZ]
NAME
DESCRIPTION
AIR
ZCE
ZCZ
FLOW(1)
(°C/W)(2)
(°C/W)(2)
ΘJC
ΘJB
ΘJA
Junction-to-case (1S0P)(3)
Junction-to-board (2S2P)(3)
Junction-to-free air (2S2P)(3)
N/A
N/A
0.0
1.0
2.0
3.0
0.0
1.0
2.0
3.0
0.0
1.0
2.0
3.0
10.3
11.6
24.7
20.5
19.7
19.2
0.4
10.2
12.1
24.2
20.1
19.3
18.8
0.3
ΨJT
Junction-to-package top (2S2P)(3)
Junction-to-board (2S2P)(3)
0.6
0.6
0.7
0.7
0.9
0.8
ΨJB
11.9
11.7
11.7
11.6
12.7
12.3
12.3
12.2
(1) m/s = meters per second.
(2) °C/W = degress celsius per watt.
(3) The board types are defined by JEDEC (reference JEDEC standard JESD51-9, Test Board for Area
Array Surface Mount Package Thermal Measurements).
7.2 Via Channel
The ZCE package has been specially engineered with Via Channel™ technology. This allows larger than
normal PCB via and trace sizes and reduced PCB signal layers to be used in a PCB design with the 0.65-
mm pitch package, and substantially reduces PCB costs. It allows PCB routing in only two signal layers
(four layers total) due to the increased layer efficiency of the Via Channel™ BGA technology.
Via Channel™ technology implemented on the ZCE package makes it possible to build an AM335x-based
product with a 4-layer PCB, but a 4-layer PCB may not meet system performance goals. Therefore,
system performance using a 4-layer PCB design must be evaluated during product design.
7.3 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated devices. This data is subject to change without notice and without revision of this document.
The figures below show the package drawings for the ZCE and ZCZ package options.
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217
PACKAGE OPTION ADDENDUM
www.ti.com
12-Nov-2012
PACKAGING INFORMATION
Orderable Device
AM3352ZCE27
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Samples
Drawing
(1)
(2)
(3)
(Requires Login)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
ZCE
ZCE
ZCZ
ZCZ
ZCE
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
298
298
324
324
298
324
324
324
324
324
324
324
1
1
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
AM3352ZCED50
AM3352ZCZ60
Green (RoHS
& no Sb/Br)
126
126
1
Green (RoHS
& no Sb/Br)
AM3352ZCZD72
AM3354ZCED50
AM3354ZCZ60
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
1
Green (RoHS
& no Sb/Br)
AM3354ZCZ80
126
1
Green (RoHS
& no Sb/Br)
AM3354ZCZD72
AM3357ZCZD27
AM3357ZCZD72
AM3358ZCZD72
AM3359ZCZD72
Green (RoHS
& no Sb/Br)
126
1
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
1
Green (RoHS
& no Sb/Br)
1
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Nov-2012
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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