AIC111RHBRG4 [TI]
IC DESIGN SPECIFICATION 1.3-V microPower DSP/uC VOICE BAND AUDIO CODEC; IC设计规范1.3 -V微功耗DSP / UC VOICE宽带音频编解码器
| 型号： | AIC111RHBRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC DESIGN SPECIFICATION 1.3-V microPower DSP/uC VOICE BAND AUDIO CODEC |
| 文件： | 总29页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.ti.com
AIC111
SLAS382 – JUNE 2003
IC DESIGN SPECIFICATION
1.3-V microPower DSP/µC VOICE BAND AUDIO CODEC
D
Available in:
FEATURES
– 32-Pin QFN 5×5-mm Plastic Package
– 32-Pad Bumped Die in Waffle Pack (wafer
scale packaging), or Tape and Reel,
(Preview, Available 3rd Quarter 2003)
D
Single Channel Codec
D
Noise Shaped Delta Sigma ADC and DAC
Technology
D
D
Low Supply Voltage and Current:
– 1.3-V Typical Power Supply
– 350-µA Typical Supply Current Drain
APPLICATIONS
D
D
D
D
D
Hearing Instruments
Personal Medical Devices
Hearing Protection
Aural Processing
Power Supply Up Monitor and Low Battery
Monitor That Also Automatically Shuts Off
H-Bridge Output When Battery Decays Below
1.05 V in a Nontransient Manner
Low-Power Headsets
D
D
Typical 2.4-µVrms Input Referred Noise With
0.01% Total Harmonic Distortion for Front
End and 108-dB Dynamic Range
DESCRIPTION
The AIC111 IC design specification serves to provide
product development teams with a guideline for how the
AIC111 IC is specified and programmable options that are
available. The document outlines a top-level block
description of the IC along with system specifications and
functions. Individual block descriptions and target
specifications are also outlined.
ADC Has 87-dB Dynamic Range With 73-dB
Total Harmonic Distortion 100 Hz–10 kHz,
40-kHz Sampling Rate
D
D
Typical 55-dB PSRR 100 Hz to 10 kHz for
Analog Front End
Low Noise Programmable Gain
Amplifier/Compressor Front End With
Programmable Fast and Slow Attack and
Decay Rates With Dual or Single Attack and
Decay Rate Option
The Texas Instruments AIC111 is a TI µPower DSP
compatible, or microcontroller compatible audio codec
product, or analog interface circuit. The AIC111 is part of
a comprehensive family of DSP/µC based high-
performance analog interface solutions. The AIC111 is
targeted primarily at personal medical devices, such as
hearing instruments, aural preprocessing applications,
and low-power headset applications. The AIC111 is used
in any design requiring a programmable time constant
D
D
Typical Output Noise of 12 µVrms With 0.05%
Total Harmonic Distortion for Delta Sigma
DAC and H-Bridge Output Driver
Low Jitter Oscillator That Generates all
Internal Clocks and Generates 5-MHz Output
DSP/µC Clock
PGA/compressor interface,
analog-to-digital converter, an external
handling signal processing, or low distortion
high
dynamic range
DSP/µC
a
D
D
Regulated Bandgap Voltage Reference
digital-to-analog converter with a balanced H-Bridge
speaker driver. It supports a CMOS digital interface
tailored for TI DSPs with the McBSP protocol such as
TMS320VC54x DSP family and SPI-based controllers
such as TI MSP430x family of microcontrollers. The
AIC111 also has an external microphone or sensor supply
and bias and power supply up low-battery monitor
indicator.
Programmable Functionality via Digital Serial
Interface
– McBSP Interface, DSP Protocol
– TI TMS320VC54x , TMS320VC55x DSPs
– SPI Interface, Microcontroller Protocol
– TI MSP430xx
D
External Chip Power Down and Reset
Pleasebe aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
This document contains information on products in more than one phase of
development. The status of each device is indicated on the page(s) specifying its
electrical characteristics.
Copyright 2003, Texas Instruments Incorporated
AIC111
SLAS382 – JUNE 2003
www.ti.com
Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduring
storageor handling to prevent electrostatic damage to the MOS gates.
The AIC111 comes in a 32-pin QFN 5×5-mm package. A 32-pad solder ball bumped flip chip die that comes in waffle
packs or tape and reel is in preview and will be available 3rd quarter 2003.
AVAILABLE OPTIONS
PART NUMBER
AIC111RHB
PACKAGE
32-pin QFN (5 mm x 5 mm), in tube.
32-pin QFN (5 mm x 5 mm), tape and reel
AIC111RHBR
32-padwaffle scale chip package, bumped die in waffle pack (contact the factory for availability) – Preview,
AIC111YE
available 3rd quarter 2003
32-pad (WSCP) bumped die in tape and reel (contact the factory for availability) – Preview, available 3rd
AIC111YER
quarter2003
ABSOLUTE MAXIMUM RATINGS
overoperating free-air temperature range unless otherwise noted
(1)(2)
UNIT
Inputvoltage
AI or DI pins
–0.3 V to 4 V
–0.3 V to 4.5 V
100 mA
Power supply
VDD, power pins
Latch-uptolerance
JEDEC latch-up (EIA/JEDS78)
Operating free-air temperature range, T
0°C to 70°C
–15°C to 85°C
220°C to 230°C
–40°C to 125°C
65% R.H.
A
Functionaltemperaturerange
Reflow temperature range (flip chip)
Storage temperature range, T
stg
Storagehumidity
(1)
Stresses beyond those listed under absolutemaximumratings may cause permanent damage to the device. These are stress ratings only, and
functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.
Exposureto absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Specifications are assured operating at maximum device limits for QFN package only, unless otherwise specified.
ELECTRICAL CHARACTERISTICS
INPUT/OUTPUT, OPERATING TEMPERATURE AT 25°C
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Digital interface (see Notes 1 and 2)
BUF_DVDD (see Note 1)
3.6
V
V
V
V
V
V
V
V
V
High-level input voltage
Low-level input voltage
BUF_DVDD–0.2
BUF_DVSS+0.2
BUF_DVDD
IH
IL
High-level output voltage
Low-level output voltage
OH
OL
BUF_DVSS
Maximum allowed input voltage (AVIN)
Input impedance (AVIN) (see Note 3)
Input capacitance (AVIN)
Differential
450 mVpk
Nominal gain = 50x
20
5
kΩ
pF
Microphone bias voltage (MIC_VSUP)
Microphone bias resistor (MIC_BIAS)
20-µAmaximum
0.87
27
0.94
0.99
31
V
29.1
kΩ
Fixed Q
3/4 HB_VDD
HB_VDD
20 or 40
H-bridgeamplifieroutput
Outputresistance
DAC full scale output differential
V
PP
Adaptive Q
Differential, HB – V
= 1.3 V
Ω
DD
(1)
DVDD, VDD_OSC, and AVDD should be within 50 mV, preferably connected together.
AVSS1, 2, DVSS, and VSS_OSC should be within 50 mV, preferably connected together.
Maximum (0.9 V, DVDD –0.5 V) ≤ BUF_DVDD ≤3.6 V
Driving single-ended: Rin = R × [(1+A)/(2+A)], A = PGAC Gain (linear), R = 20.4 kΩ for A ≥ 4 or 20.4 kΩ × (4/A) for A<4.
Rin(min) = 17 kΩ (A=4), Rin(max) = 59.89 kΩ (A = 0.89), Rin(nom) = 20 kΩ (A = 50).
(2)
(3)
2
www.ti.com
AIC111
SLAS382 – JUNE 2003
TERMINAL ASSIGNMENTS
32 31 30 29 28
1
26
27
FRAME
SDIN
AVSS1
AVSS2
25
24
2
3
4
5
6
SDOUT
23
AVINP
AIC111
22
21
20
19
18
BUF_DVSS
BUF_DVDD
AVINM
VMID_FILT
MIC_BIAS
DVDD
Bumped Side
DVSS1
VREF
7
8
9
MCLK
MIC_VSUP
17
10 11 12 13 14 15 16
IMODE
Alignment
Marker
Bumped View
PCB View
For exact bump
location see Spec.
Section 2.2
(0,0)
IMODE
9
8
10 11 12 13 14 15 16
17
18
MIC_VSUP
VREF
MCLK
7
6
5
4
3
2
1
19
20
DVSS1
MIC_BIAS
VMID_FILT
AVINM
Back Side
DVDD
21
22
BUF_DVDD
BUF_DVSS
AVINP
AIC111
23
24
SDOUT
SDIN
AVSS2
AVSS1
25
FRAME
27
32 31 30 29 28
26
Figure 1. AIC111YE Bumped View and PCB Flipped Pin Placements
3
AIC111
SLAS382 – JUNE 2003
www.ti.com
32
31
30
29
27
26
25
28
1
2
3
4
5
6
7
8
24
23
22
21
20
19
SDIN
AVSS1
AVSS2
SDOUT
BUF_DVSS
BUF_DVDD
DVDD
AVINP
AVINM
AIC111RHB
VMID_FILT
DVSS
MIC_BIAS
VREF_BG
MCLK
18
17
IMODE
MIC_VSUP
9
10
11
12
13
14
15
16
Figure 2. AIC111RHB 32-Pin QFN Pinout
4
www.ti.com
AIC111
SLAS382 – JUNE 2003
Terminal Functions
TERMINAL
NAME
TYPE
DESCRIPTION
NO.
1
AVSS1
AVSS2
AVINP
GND
GND
AI
Groundreturn for ADC analog circuits
Ground return for PGAC and MIC power analog circuits
2
3
Noninverting differential analog input coupled through an external 1-µF capacitor to external microphone
output
4
5
6
7
8
9
AVINM
AI
Invertingdifferential analog signal input coupled through an external 1-µF capacitor to ground
Midsupply ac ground reference filter pin bypassed by a 1-µF capacitor connected to ground
Source connection of external microphone source follower preamp. (Provides 29.1 kΩ to AVSS2)
Bandgap reference output bypassed by external 1-µF VREF filter capacitor
Supplyvoltageforexternalmicrophonesourcefollowerpreampbypassedwithanexternal0.1-µFcapacitor
Isolatedsubstrate VSS for analog circuits
VMID_FILT
MIC_BIAS
VREF
AO
AO
AO
MIC_VSUP
SUB_VSS
AO
GND
VDD
GND
GND
AO
10 VDD_OSC
11 VSS_OSC
Power pin for internal oscillator
Ground return for internal oscillator
12 HB_VSS_P
13 VOUT_P
14 HB_VDD
15 VOUT_M
16 HB_VSS_M
17 IMODE
18 MCLK
Ground return for noninverting stack of H-bridge amplifier
NoninvertingH-bridgeoutputvoltage
VDD
AO
Power pin for H-bridge amplifier
InvertingH-bridgeoutputvoltage
GND
DI
Ground return for inverting stack of H-bridge amplifier
Digital interface format selection pin
DO
5-MHz output clock for external DSP/µC
19 DVSS1
20 DVDD
GND
VDD
VDD
GND
DO
Ground return for digital circuits
Power pin for digital circuits
21 BUF_DVDD
22 BUF_DVSS
23 SDOUT
24 SDIN
Power pin for interface digital I/O circuits
Ground return for interface digital I/O circuits
Digital interface serial data output pin
DI
Digital interface serial data input pin
25 FRAME
26 SCLK
DO
Digital interface serial data framer
DO
Digital interface serial shift clock
27 DVSS2
28 RST/LBM
GND
DO
Ground return for digital circuits
Provides external reset and low battery monitor
Powers down all analog blocks and holds digital outputs low until internal system is up
VDD power pin for analog circuits
29 EXT_RST/PWDN DI
30 AVDD
VDD
31 VRFILT
32 AVSS_REF
AO
Positive ADC reference pin bypassed with 1-µF capacitor to AVSS_REF
Ground for ADC voltage reference
GND
5
AIC111
SLAS382 – JUNE 2003
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
Dec.
Filter
&
Delta
Sigma
ADC
Delta
Sigma
DAC
H–Bridge
Speaker
Driver
AVINP
VOUT_P
RC
PGA/Compressor
Flt
AVINM
VOUT_M
HPF
MIC/Sensor
Power and
Bias
MIC_VSUP
MIC_BIAS
DVDD
DVSS
Biases
Generator
RST/LBM
POR
Digital
Interface
BUF_DVDD
BUF_DVSS
VDD_OSC
VSS_OSC
Output Buffers
Oscillator
Bandgap
Reference
VREF
6
www.ti.com
AIC111
SLAS382 – JUNE 2003
OPERATION
The power source may be a zinc-air battery operating at a typical voltage of 1.3 V. A single external de-coupling
capacitor of 1 µF is recommended on the main power supply.
VOLTAGE and CURRENT, OPERATING TEMPERATURE AT 25°C
PARAMETER
TEST CONDITION
MIN
1.1
TYP
1.3
MAX
UNIT
AVDD, DVDD (All pins of type AVDD, DVDD in
pin-outtable)
1.5
V
Steady-state battery supply
S Unloaded: H-Bridge output open
S Microphone resistor model connected (see Figure 6)
S Power supplies = 1.3 V
I
S
(supply current)
350
µA
S No receiver attached
FUNCTIONAL INPUT CHANNEL PERFORMANCE REQUIREMENTS
The front end is defined as the differential signal path from the PGA/compressor inputs, AVINP, and AVINM through
the delta-sigma ADC and decimation filter.
Typical Conditions; deviations are noted in table.
D
D
D
D
D
D
D
Operating Temperature Range: 0°C to 70°C. All specification are at 25°C and 1.3 V unless otherwise noted.
AVDD, DVDD range: 1.1 V to 1.5 V
AVINP, AVINM inputs: AC coupled, Frequency ranging from 100 Hz–10 kHz
Measurement Bandwidth: 100 Hz–10 kHz A-weighted.
Idle channel definition: AVINP and AVINM are both ac-coupled to AVSS.
Typical PGAC gain range is –1 dB to 40 dB.
Maximum input voltage: 450 mVpk.
PARAMETER
Broad-bandnoise
TEST CONDITION
Input referred idle channel
MIN
TYP
2.4
0.01 0.2%
MAX
UNIT
µV RMS
THD (low level)
DC Offset
AVIN ≤ PGAC threshold (see Note 1)
Idlechannel
–5
0
5
mV
dB
Droop at 10 kHz
Referenced to amplitude at 1 kHz
1.2
(1)
PGAC threshold = PGAC threshold voltage/maximum gain of PGAC.
0
0
–10
–20
–30
–2
–4
–6
–8
–40
–50
–60
–70
–80
–10
–12
–14
–16
–18
–20
–90
–100
0
2
4
6
8
10 12 14 16 18 20
0
10 20 30 40 50 60 70 80 90 100
f – Frequency – kHz
f – Frequency – kHz
Figure 3. Input Channel Frequency Response With HPF Bypassed
7
AIC111
SLAS382 – JUNE 2003
www.ti.com
Analog-to-Digital Converter Filtered Input Voltage Reference
Function – Filters analog supply AVDD for DS-ADC reference. With a recommended 0.1-µF external capacitor
between pins VRFILT and AVSS_REF, the pole is set at approximately 72 Hz, with 1 µF, the pole is set at
approximately 7 Hz.
Programmable Gain Amplifier and Compressor
Function: The programmable gain amplifier and compressor (PGAC) amplifies the microphone or sensor output
signal, provides an appropriate impedance to the microphone buffer or sensor, and provides input gain compression
limiting depending on the input signal level if one is not using the fixed gain mode, where the PGAC gain is set by
selected register bits. Input compression limiting is discrete automatic gain correction (AGC) based on detecting the
peak input signal level using a peak detector circuit that has programmable time responses to provide AGC control,
and is intended to prevent a steady state input level up to the defined PGAC limit from being clipped. The
attack/release times of the PGAC are programmable by internal clock selection inside the PGAC digital level circuitry
that affects the rate of gain changes.
The PGAC has four modes of operation: automatic dual-rate (default), automatic single-rate, fixed single-rate, and
fixed immediate. Mode selection is controlled by bits 3 and 2 of the PDCREG register.
Automatic dual-rate mode (00, default):
In this mode of operation, the PGAC has two attack (gain decrease) ratesandtworelease(gainincrease)rates,which
may be selected by programming the FASTARREG and FORMAT4 registers. Internally, two counters are used to
control the compressor gain. The fast rate counter responds at the fast attack and release rates, and it counts down
at the attack rate to decrease the PGAC gain if the output of the PGAC is instantaneously larger than a preset
threshold (PGAC_THRES = 400-mV peak), or it counts up to increase the gain, up to the maximum allowed gain
as set by the PGACREG register, if the output of the PGAC falls below a second threshold, which is 3 dB lower
(283-mV peak), which provides hysteresis. Before the gain is allowed to increase, the signal at the output of the
PGAC must be below the lower threshold for a period of time which is controlled by bit 4 of PDCREG, and can be
50 ms (0, default) or 25 ms (1). The slow-rate counter responds at the slow attack and release rates, and it attempts
to track the state of the fast rate counter. The PGAC gain is determined by whichever counter is smaller. In this way,
the PGAC can respond and recover rapidly to short signal bursts while responding more slowly to the signal average.
Automatic single-rate mode (01):
In this mode of operation, the PGAC has one attack rate and one release rate, which may be selected by
programming the FASTARREG register. The operation of the PGAC is similar to the dual-rate mode, except that
the slow-rate counter is disabled and the PGAC gain is solely determined by the fast-rate counter.
Fixed single-rate mode (10):
In this mode of operation, the PGAC gain tracks the value specified in the PGACREG register regardless of the signal
amplitude, and changes in PGACREG cause the gain to decrease or increase at the corresponding fast attack or
release rate specified in the FASTARREG register.
Fixed immediate mode (11):
In this mode of operation, the PGAC gain tracks the value specified in the PGACREG register regardless of the signal
amplitude, and changes in PGACREG cause the gain to change immediately to the desired gain without stepping
through the intermediate gain states.
Bit 7 of the PGACREG register controls the PGAC gain read mode. While this bit is low (default), reading PGACREG
returns the contents of PGACREG. However, if this bit is set high, then any subsequent read(s) of PGACREG returns
the actual, instantaneous PGAC gain. This information may be useful, for example, for dynamic range expansion,
effectively undoing the compression effect in the automatic modes of operation.
Characteristics: Compression limits the PCAG output. PGACREG is a programmable register.
8
www.ti.com
AIC111
SLAS382 – JUNE 2003
Specifications at 25°C, AVDD = 1.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
InputSignalParameters
Maximum signal swing
Gain = –1 dB
900
mV
PP
BlockParameters
Gain size step
0.3
0.5
0.7
dB
(1)
(2)
Based on a system clock of 1.280 MHz.
Forfixed gain mode the rate is 80 KdB/s to new programmed value of gain. All intermediate 0.5 dB gain steps are passed through to reach new
gain.
Delta Sigma A/D Converter/Anti-alias Filter
Function: Converts the PGAC differential output to a digital word with an equivalent dynamic range of approximately
14 bits.
Characteristics: The delta sigma ADC has a 64 oversampling ratio, a 1.28-MHz master clock, and a 40-kHz output
data rate. Digital coding is 2s complement. Tones are at least 12 dB below broadband noise level. Full-scale signal
15
15
range corresponds to +2 –1, –2
Specifications at 25°C, AVDD = 1.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Blockparameters
Dynamicrange
Input sample rate
Output sample rate
THD
–3 dB rel. to reference
87
dB
MHz
kHz
dB
1.28
40
BW: 100 Hz–10 kHz
85
Digital High-Pass Filter
Function: Provide a high-pass filter in ADC signal path. The high-pass filter (HPF first order) removes dc offsets
introduced into the channel. FORMAT1 register selections for a 50 Hz, 100 Hz, or bypass are available.
Characteristics: Programmable selections for a 50 Hz, 100 Hz, or bypass are available. The default HPF pole is
50 Hz.
Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
50
MAX
UNIT
HPF corner frequency
–3 dB nom mode
Hz
Delta Sigma DAC
Function: Generates an over-sampled bit string to drive the H-bridge output amplifier such that when filtered
reproduces the desired analog waveform.
Characteristics: A 32 times over-sampled modulator multi-bit design.
Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
40
640
MAX
UNIT
kHz
fd
Signal; BW = 10 kHz
(input_data)
f
kHz
clk
9
AIC111
SLAS382 – JUNE 2003
www.ti.com
H-bridge Output Driver
Function: An H-bridge output driver efficiently converts the delta sigma DAC modulator output signals. The external
load provides the low-pass filtering that recovers the differential analog signal from the H-bridge.
Characteristics: Standard H-bridge configuration with transistors sized to differentially drive the load impedance.
The load impedance is complex and a function of frequency.
H-Bridge Load Switching
NoninvertingPhase
VDD (vbat)
InvertingPhase
VDD ( vbat)
OUTMM
OUTMM
OUTPM
OUTPM
Receiver
Load
OUTP
OUTMP
OUTM
OUTPP
Receiver
Load
OUTP
OUTMP
OUTM
OUTPP
AVSS
AVSS
NOTE:
VDDdoesnotnecessarilyhavetobeconnectedtothesamepotentialasAVDD,itcouldbeconnectedtoahigherpotentialthanAVDD,equal
to AVDD, but not less than AVDD.
Figure 4. Definition of Phase and Output Switching Current Polarity
Specifications at 25°C, HB_VDD = 1.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BlockParameters
DC offset
Idle channel; Differential across VOUT_P and VOUT_M
–5
0
33
12
5
mV
Fixed Q
Idle channel, measured at output of channel,
BW = 100 Hz–10 kHz, HB_VDD = 1.3 V,A-weighted
Broadbandnoise
µVrms
Adaptive Q
THD
BW = 100 Hz–10 kHz
0.03%
Switchingfrequency
640
3/4 HB_VDD
HB_VDD
kHz
Fixed Q
Maximumoutputswing
V
PP
Adaptive Q
10
www.ti.com
AIC111
SLAS382 – JUNE 2003
Microphone Power Supply
Function: The microphone power supply circuit provides a constant power supply voltage and bias current for the
microphone preamp or sensor bias, provides a low-noise voltage reference (ac ground) for the PGAC, provides
regulated PGAC comparator threshold levels, provides bandgap regulated POR comparator trip voltage levels, and
provides a bandgap regulated current for the biases generator circuit.
Characteristics: The low-dropout regulator configuration or single stage, single-pole amplifier drives an external
0.1-µF capacitor. The regulator does not oscillate under no-load or loaded conditions. The circuit supplies up to 50-µA
of continuous current.
Specifications at 25°C, AVDD = 1.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
0.94
MAX
UNIT
V
MIC_VSUP
I
L
= 20 µA
0.87
0.97
VMID_FILT
PSRR
0.59 × AVDD
0.1-µF external bypass cap from MIC_VSUP to AVSS2.
0.78
55
V
dB
kΩ
Output impedance
1.5
MCLK Output
Function: Provides a clock signal for external use.
Specifications at 25°C, VDD_OSC, DVDD, BUF_DVDD = 1.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
ps
Frequency
4.7
5.12
150
5.5
Jitter
RMS jitter
Duty cycle
50%
Power-On Reset
Function: Provides a reset signal upon power up (stable voltage reference) that initializes the digital interface. Italso
provides a gating signal to the delta-sigma DAC modulator to prevent audible pops and clicks from erroneous data
sent to the H-bridge circuit at power up and during periods when battery voltage has degraded below 1.05 V for an
extended period of time (typically greater than 44 µs). The reset signal is asynchronous to MCLK. Digital interface
does not start operating until after t
_valid has transpired.
(VDD)
POR has to:
D
D
D
D
Deal with system’s on/off switch bounce lasting 100 ms or less.
Detect when the power supply AVDD is ≥1.1 V to enable the H-bridge output.
Provide kick-start to oscillator.
Detect when VDD degrades below 1.05 V for a period of time that is nontransient, and gate H-bridge output.
Specifications at 25°C, AVDD = 1.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
100
MAX
UNIT
t
_valid:
(VDD)
V
DD
> 1.1 V
ms
Time VDD considered valid at powerup after switch bounce has settled.
Allowed transient spike below 1.05 V before H-bridge output and digital interface
are not asserted.
V
DD
< 1.05 V
44
µs
POR on
POR off
1.1
V
1.05
11
AIC111
SLAS382 – JUNE 2003
www.ti.com
DIGITAL INTERFACE
Function: The digital interface can be selected (IMODE=LOW) as a serial audio/control interface (SACI), which is
the McBSP DSP-codec protocol, or (IMODE=HIGH), a serial peripheral interface (SPI). Either SACI or SPI sends
out a 16-bit audio stream from the ∆–Σ ADC and receives a 20-bit audio stream going to the ∆–Σ DAC/H-Bridge.
Several control functions, READ/WRITE to user registers, are also included totaling five 8-bit registers. Four pins,
SCLK, FRAME, SDIN and SDOUT, are employed in SACI or SPI. An internal register map exists that contains
read/write program registers for a variety of FORMAT (user) settings. The register bits that are designated not used
will always read back zero or voltage level VSS regardless of what is written to them.
DIG INTERFACE PIN
SCLK
I/O
DESCRIPTION
Output Bit shift clock. SCLK has an internal pull down.
FRAME
Output Data frame sync: controls the separation of audio channels and provides areset/synchronization
to the interface’s internal state machine. FRAME has an internal pull down.
SDIN
SDOUT
IMODE
MCLK
Input
Input
Input
Serial audio/control data input pin.
Serial audio/control data output pin.
Interface protocol selection pin. LOW=SACI, HIGH=SPI.
Output Clock output pin.
SLAVE
C54x
MASTER
SDOUT
DR
FRAME
FSX
FSR
SDIN
DX
AIC111
SCLK
CLKR
CLKS
CLKX
MCLK
CLKIN
(See Note A)
NOTE A: The dotted line indicates the connection is not essential for communication to work.
Figure 5. AIC111 McBSP DSP-Codec Interface
McBSP DSP-Codec (SACI) Protocol
Use this protocol when interfacing to TI DSPs.
D
D
D
The SACI works in a master mode.
SCLK = 1.28 MHz. FRAME (= 40 kHz) has a 50% duty cycle. FRAME is an output.
32-bit control/audio data, written on the SDIN pin, consist of a 20-bit audio word going to the ∆–Σ DAC, and a
12-bit control word.
D
D
DAC input has two modes of operation, a 20-bit mode, and a 16-bit mode.
The 12-bit control word consists of: a R/W bit, 3 address bits, and 8-bits of control register content. Note that
the R/W bit is defined as 0=READ, and 1=WRITE.
D
D
When the 3 address bits are all zeros, the control function of the SACI is disabled.
24-bit audio/control data, read from the SDOUT pin, consist of one 16-bit output from the ∆–Σ ADC followed by
an 8-bit control word.
D
All data/control words are formatted as the MSB first.
12
www.ti.com
AIC111
SLAS382 – JUNE 2003
20-BitMode
D/A Input
D19 – D0
D19 – D0
AIC111 Input
16-BitMode
D/A Input
D19 – D0
D19 – D4
D19 – D4
D19 D19 D19 D19
D19 D19 D19
D19 D19
Shift = 0
Shift = 1
AIC111 Input
0
0 0
D19 – D4
D19 – D4
D19 – D4
Shift = 2
Shift = 3
0 0 0
D19
0 0 0 0
Shift = 4
Shift = 5
D18 – D4
0 0 0 0 0
See Note B
NOTE B: For 5-bit left shift, digital word is limited to 15 bits with sataration.
Figure 6. AIC111 Data Output
13
FRAME
SCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W/R A2 A1 A0 C7 C6 C5 C4 C3 C2 C1 C0 D19 D18
SDIN
C7 C6 C5 C4 C3 C2 C1 C0 D15 D14
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
www.ti.com
AIC111
SLAS382 – JUNE 2003
SLAVE
GPIO
STE
MASTER
AIC111
FRAME
SDOUT
SDIN
SIMO
SOMI
UCLK
MCLK
MSP430x
SCLK
MCLK
Figure 8. AIC111 SPI I/O Diagram
SPI Protocol
D
D
D
AIC111 can also implement a master SPI protocol.
SCLK supplies a bit shift clock of 1.28 MHz to the SPI port of a slave device.
FRAME must be in the active low state prior to data transaction and must stay low for the duration of data
transaction. Before communication, there are eight silent cycles on SCLK. During this period FRAME also sends
a pulse to reset the slave device.
D
When the control function is not required, the AIC111 transmits a 16-bit audio word to and receives a 20-bit audio
word from the slave device in every FRAME cycle.
D
D
A WRITE/READ of an 8-bit user register (address 0x01 to 0x07) takes two FRAME cycles.
All data/control words are formatted as the MSB first.
15
AIC111
SLAS382 – JUNE 2003
www.ti.com
NOTE:
IfA2, A1, and A0 = 0, one gets audio data only and W/R is a don’t care. If in the previous frame A2, A1, and A0 = 0, then one gets both audio
and control data depending on the W/R bit defined as Read = 0 and Write = 1.
Figure 9. AIC111 SPI Signals
16
www.ti.com
AIC111
SLAS382 – JUNE 2003
NOTE:
SDIN shows writing to A2, A1, and A0 specified from the previous frame. SDOUT shows reading from A2, A1, and A0 specified from a
different previous frame.
Figure 10. AIC111 SPI Signals
17
AIC111
SLAS382 – JUNE 2003
www.ti.com
Digital Interface Timing
PARAMETER
MIN
TYP
1.28
F-sclk/32
MAX
UNIT
F_sclk
SCLK frequency
MHz
MHz
F_frame
FRAMEfrequency
Digital Interface Block Diagram
PGA/Compressor
ADC
SCLK
FRAME
SDIN
DAC/H–Bridge
Oscillator
CONTROL REGISTERS
CONTROL LOGIC
DATA BLOCK
McBSP/SPI
SDOUT
IMODE
MCLK
Power–onReset
MicPower/VREF
Register Map and Register Bit Definitions
ADDRESS
0x00
REGISTER NAME
Reserved
DETAILED DESCRIPTION
Reserved for future use
0x01
PGACREG
PGAC gain register
0x02
HPFSFTREG
PDCREG
HPF and shift control register
Power-downcontrolregister
Fast attack/release rate control register
Slow attack/release rate control register
Reserved for future use
0x03
0x04
FASTARREG
SLOWARREG
Reserved
0x05
0x06–07
NOTE:
Do not write to the reserved registers.
18
www.ti.com
AIC111
SLAS382 – JUNE 2003
PGACREG
BIT
NAME
FUNCTION
DEFAULT=0x46
7
PGAC_READ_MODE
Select register contents or actual gain to read
0: Read FORMAT0 register contents (default)
1: Read actual PGAC gain
6:0
PGAC_GAIN [6:0]
PGAC gain adjustment (0.5 dB steps). A full table is found in the
AppendixSection of this data sheet.
0x52 = +40.0 dB
0x51 = +39.5 dB
0x50 = +39.0 dB
…
0x46 =+34.0 dB (default)
….
0x01 = –0.5 dB
0x00 = –1.0 dB
HPFSFTREG
BIT
7
NAME
DBUFF_EN
FUNCTION
DEFAULT=0x11
Enable weak (1/2 strength) dig I/O buffer
6:5
HPF_CTL[1:0]
Control bits for high-pass filter
00: normal mode
01: HPF bypass
10: 100 Hz corner frequency
11: Not used
4:2
SHIFT [2:0]
Select shift bits when ADC 16-b output is used as DAC 20-b input.
000: no shift
–24 db gain
–18 dB gain
–12 dB gain
–6 dB gain
001: 1b left shift
010: 2b left shift
011: 3b left shift
100: 4b left shift (default) 0 dB gain
101: 5b left shift
11X: 5b left shift
+6 dB gain
1:0
DAC_MODE
Select DAC mode of operation.
00: DAC off, powered down
01: 16-bit input goes through shifter (default)
10: 20-bit input bypasses shifter
11: ADC→DAC digital loopback
PDCREG
BIT
7
NAME
DAC_ADAPTIVE_Q
HB_OUT_EN
FUNCTION
DEFAULT=0x00
0 = fixed quantization, 1 = adaptive quantization
H-bridgeoutputenable
6
5
HB_DRIVE
H-bridge drive strength, 0 = 40 Ω, 1 = 20 Ω
4
HIST_TIMEOUT_SEL PGAC hysteresis timeout select
0: 50 ms (default)
1: 25 ms
3:2
PGAC_GAIN_MODE
Set gain mode of PGAC
00: Automatic, dual rate (default)
01: Automatic, single rate
10: Fixed, single rate
11:Fixed, immediate
1
0
MIC_VSUP_PD
FRONTEND_PD
Power down MIC_VSUP
Power down PGAC+ADC
19
AIC111
SLAS382 – JUNE 2003
www.ti.com
FASTARREG PGAC Fast Rates
BIT
NAME
FUNCTION
DEFAULT=0xF7
7:4
ATTACK<7:4>
1111: Attack rate = 80000 dB/s
1110: Attack rate = 40000 dB/s
1101: Attack rate = 20000 dB/s
1100: Attack rate = 10000 dB/s
1011: Attack rate = 5000 dB/s
1010: Attack rate = 2500 dB/s
1001: Attack rate = 1250 dB/s
1000: Attack rate = 625 dB/s
0111: Attack rate = 312.5 dB/s
0110: Attack rate = 156.25 dB/s
0101: Attack rate = 78.13 dB/s
0100: Attack rate = 39.1 dB/s
0011: Attack rate = 19.53 dB/s
0010: Attack rate = 9.77 dB/s
0001: Attack rate = 4.88 dB/s
0000: Attack rate = 2.44 dB/s
3:0
RELEASE<3:0>
1111: Release rate = 80000 dB/s
1110: Release rate = 40000 dB/s
…
0001: Release rate = 4.88 dB/s
0000: Release rate = 2.44 dB/s
SLOWARREG PGAC Slow Rates (Dual Rate Mode Only)
BIT
NAME
FUNCTION
DEFAULT=0x42
7:4
ATTACK<7:4>
1111: Attack rate = 80000 dB/s
1110: Attack rate = 40000 dB/s
…
0001: Attack rate = 4.88 dB/s
0000: Attack rate = 2.44 dB/s
3:0
RELEASE<3:0>
1111: Release rate = 80000 dB/s
1110: Release rate = 40000 dB/s
…
0001: Release rate = 4.88 dB/s
0000: Release rate = 2.44 dB/s
20
www.ti.com
AIC111
SLAS382 – JUNE 2003
APPENDIX
PGAC GAIN
PGAC GAIN VALUES
BUS NAME
PGAC_GAIN<6:0>
HEX VALUE
0x52
0x51
0x50
0x4F
0x4E
0x4D
0x4C
0x4B
0x4A
0x49
0x48
0x47
0x46
0x45
0x44
0x43
0x42
0x41
0x40
0x3F
0x3E
0x3D
0x3C
0x3B
0x3A
0x39
0x38
0x37
0x36
0x35
0x34
0x33
0x32
0x31
0x30
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
BINARY
1010010
1010001
1010000
1001111
1001110
1001101
1001100
1001011
1001010
1001001
1001000
1000111
1000110
1000101
1000100
1000011
1000010
1000001
1000000
0111111
0111110
0111101
0111100
0111011
0111010
0111001
0111000
0110111
0110110
0110101
0110100
0110011
0110010
0110001
0110000
0101111
0101110
0101101
0101100
0101011
0101010
0101001
0101000
0100111
0100110
0100101
0100100
0100011
GAIN (DB)
40
PGAC
39.5
39
38.5
38
37.5
37
36.5
36
35.5
35
34.5
34
33.5
33
32.5
32
31.5
31
30.5
30
29.5
29
28.5
28
27.5
27
PGAC
PGAC_GAIN<6:0>
26.5
26
25.5
25
24.5
24
23.5
23
22.5
22
21.5
21
20.5
20
19.5
19
18.5
18
17.5
17
16.5
21
AIC111
SLAS382 – JUNE 2003
www.ti.com
PGAC GAIN VALUES
BUS NAME
HEX VALUE
0x22
0x21
0x20
0x1F
0x1E
0x1D
0x1C
0x1B
0x1A
0x19
0x18
0x17
0x16
0x15
0x14
0x13
0x12
0x11
BINARY
0100010
0100001
0100000
0011111
0011110
0011101
0011100
0011011
0011010
0011001
0011000
0010111
0010110
0010101
0010100
0010011
0010010
0010001
0010000
0001111
0001110
0001101
0001100
0001011
0001010
0001001
0001000
0000111
0000110
0000101
0000100
0000011
0000010
0000001
0000000
GAIN (DB)
16
PGAC(Continued)
PGAC_GAIN<6:0>
15.5
15
14.5
14
13.5
13
12.5
12
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
0x10
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
PGAC
PGAC_GAIN<6:0>
1.5
1
0.5
0
–0.5
–1
Default
22
www.ti.com
AIC111
SLAS382 – JUNE 2003
TI TMS320C54xx APPLICATION CIRCUIT
ZINC AIR
BATTERY
1.3V
MIC_VSUP
MIC_BIAS
SCLK
CLKR
CLKS
CLKX
DX
DR
SDIN
M
c
B
S
P
Microphone
SDOUT
I/O
AIC111
’C54x
B
U
F
F
E
R
S
FRAME
FSX
FSR
1.3V
HB_VDD
RST
RST/LBM
H
B
R
I
HB_VSS
MCLK
CLKIN
D
G
E
Speaker
EXT_RST/PWDN
LBM = Low Battery Monitor
Figure 11. Interfacing to the TMS320C54xx for a Hearing Aid Application
Required external capacitors:
D 1-µF coupling capacitor on AVINP, AVINM
D 1-µF from VMID_FILT to analog ground
D 1-µF from VREF to analog ground
D 0.1-µF from MIC_VSUP to analog ground
D At least 0.1-µF from VRFILT to analog ground. 1-µF from VRFILT to analog ground is recommended.
23
AIC111
SLAS382 – JUNE 2003
www.ti.com
TI MSP430F12x APPLICATION CIRCUIT
1.3 V
2.8 V
P2.5
(See Note A)
MIC_VSUP
MIC_BIAS
MSP430F12x
INCLK
SCLK
SDIN
SOMI
SIMO
Microphone
I/O
SDOUT
B
U
F
AIC111
FRAME
RST/LBM
MCLK
STE
F
E
R
S
Speaker
RST/NMI
XIN
LBM = Low Battery Monitor ’430 Can Also Use
EXT_RST/PWDN to Reset or Power Down the AIC111
Note A: P2.5 enables the MSP430F12x to shut down the AIC111 when desired.
Figure 12. Interfacing to the MSP430F12x for a Hearing Aid Application
24
www.ti.com
AIC111
SLAS382 – JUNE 2003
MECHANICAL AND ENVIRONMENTAL
Packaging
The AIC111 is available in a 32-pin quad QFN 5x5-mm package. The AIC111 will be available 3rd quarter 2003 as
bare solder ball bumped die intended for direct PCB mounting (also known as wafer scale packaging).
D
D
D
D
For QFN packaged part in tubes order: AIC111RHB.
For QFN packaged part in tape and reel order: AIC111RHBR.
For ball bumped die (in waffle pack) order: AIC111YE (Preview, available 3rd quarter 2003).
For ball bumped die (in tape and reel) order: AIC111YER (Preview, available 3rd quarter 2003).
BOND PAD PITCH AND DIE AREA
Diedimensions
X = 2737.62 µ, Y = 3175.02 µ,
(107.78 mil, 125.0 mil)
(2,74 mm, 3,18 mm)
2
2
Maximum die area (includes scribe area)
Minimum bond pad pitch
Nearest
13.47kmil (8.69mm )
202.95 µ or 7.99 mil
PITCH
PAD (#)
PAD (#)
(micron)
(mil)
7
8
202.950
202.950
237.690
237.690
237.690
241.200
256.410
256.410
256.410
256.410
287.651
295.470
295.470
306.360
327.147
327.147
356.940
357.034
359.453
369.450
371.520
380.700
(7.990)
(7.990)
(9.358)
(9.358)
(9.358)
30
12
14
16
28
18
20
21
22
25
9
10
23
1
32
4
31
13
15
15
29
19
19
20
21
26
10
11
24
32
1
(9.496)
(10.095)
(10.095)
(10.095)
(10.095)
(11.325)
(11.633)
(11.633)
(12.061)
(12.880)
(12.880)
(14.053)
(14.056)
(14.152)
(14.545)
(14.627)
(14.988)
5
27
17
6
2
3
28
16
7
1
2
25
AIC111
SLAS382 – JUNE 2003
www.ti.com
Number of pins
Padlocations:
Units: microns
32
Bond Pad Coordinates
Bond Pad Dimensions
Pad #
Xcenter
Ycenter
Diameter
Dimensions:
Bond pad origin: X = 0.000
Bond pad offset: X = 0.000
(X,Y) = (0,0) is located at the left bottom of the die by pads 8 and 9.
See section 1.6, Figure 1–1.
X = 2737.62 Y = 3175
1
2
3
4
5
6
7
8
154.080
154.080
154.080
154.080
154.080
154.080
154.080
154.080
410.310
705.780
1001.250
1327.860
1565.550
1803.240
2040.930
2278.620
2574.990
2574.990
2574.990
2574.990
2574.990
2574.990
2574.990
2574.990
2574.990
2371.590
1910.430
1553.850
1312.650
955.530
752.580
410.310
2808.990
2437.470
2056.770
1676.070
1319.130
938.430
568.980
366.030
162.630
162.630
162.630
162.630
162.630
162.630
162.630
162.630
366.030
782.550
1038.960
1295.370
1551.780
1808.190
2188.890
2495.250
2808.990
3012.390
2994.390
3012.390
3012.390
3012.390
3012.390
3012.390
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
70.020
Y = 0.000
Y = 0.000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DIE THICKNESS
TYPICAL
TOLERANCE
Finaldie thickness Z (without solder bump)
29.59 mil or 725 µm
±0.79 mil or 20 µm
SOLDER BUMP
D
D
Bump metal composition: 37% Pb (lead)/63% Sn (tin)
Type: Spherical
BUMP SPEC.
TYPICAL
TOLERANCE
+8 µm
NOTE
100 µm
Tolerance across a single die.
Tolerance across any wafer.
Bumpheight
+16 µm
Re-flowtemperature
183°C
WAFFLE SCALE PACKAGE DISCLAIMERS FOR AIC11YE AND AIC11YER
D
D
26
The AIC111’s die bond pads, their peripheral placement, passivation opening, and layout are in accordance with
ASE’s Bumping Design Guide revision D, June, 2001.
The final application is assumed to use plastic overmolding where the die is hermetically sealed, and the
maximum ratings apply only to the QFN package and not to the WSCP.
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2005
PACKAGING INFORMATION
Orderable Device
AIC111RHB
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RHB
32
32
32
73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
AIC111RHBR
QFN
QFN
RHB
RHB
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
AIC111RHBRG4
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
AIC111YE
ACTIVE
ACTIVE
XCEPT
XCEPT
YE
YE
32
32
39
TBD
TBD
Call TI
Call TI
Call TI
Call TI
AIC111YER
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明