ADS9218 [TI]
具有全差分 ADC 输入驱动器的双通道、同步采样、18 位、10MSPS SAR ADC;
| 型号： | ADS9218 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有全差分 ADC 输入驱动器的双通道、同步采样、18 位、10MSPS SAR ADC 驱动 驱动器 |
| 文件： | 总58页 (文件大小：2847K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS9218
ZHCSR17 –JANUARY 2023
ADS921x 具有全差分ADC 输入驱动器的双路同步采样18 位10MSPS SAR ADC
1 特性
3 说明
• 高速、10MSPS/通道采样率
ADS921x 是一款 18-bit、10MSPS/通道、双通道、同
步采样模数转换器 (ADC)，此转换器具有一个用于
ADC 输入的集成驱动器。该 ADC 在 10 MSPS/ch 下
的功耗仅为 180 mW/ch，功耗随采样率减小而迅速降
低。
– ADS9218：10 MSPS/ch
– ADS9217：5 MSPS/ch
• 2 通道同步采样
• 特性集成：
– 集成ADC 驱动器
– 精密的集成基准
– 共模电压输出缓冲器
• 高性能
ADS921x 使用串行低电压差动信号 (SLVDS) 数据接
口，可实现高速数字接口，同时更大限度地降低数字开
关噪声。该器件采用节省空间的 6-mm × 6-mm、
VQFN 封装。
– 18-bit，无丢码
ADS921x 的额定工作温度范围为–40°C 至+125°C。
– INL：±1 LSB，DNL：±0.75 LSB
– SNR：95 dB，THD：fIN = 2kHz 时为–115 dB
• 宽输入带宽：
– ADS9218：90 MHz (-3dB)
– ADS9217：45 MHz (-3dB)
• 10 MSPS/ch 时低功耗180 mW/ch
• 串行LVDS 接口：
封装信息
封装(1)
封装尺寸（标称值）
器件型号
ADS9218
ADS9217(2)
RHA（VQFN，40） 6.0 mm × 6.0 mm
RHA（VQFN，40） 6.0 mm × 6.0 mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– SDR 和DDR 输出模式
– 同步时钟和数据输出
(2) 预发布信息（非量产数据）。
• 扩展工作温度范围：–40°C 至+125°C
• 6-mm × 6-mm VQFN 封装
2 应用
• 功率分析仪
• 源测量单元(SMU)
• 船用设备
• 伺服驱动器位置反馈
• 直流电源、交流电源、电子负载
REFIO
SMPL_CLK
AVDD_5V
AVDD_1V8
DVDD_1V8
DOUT_A
SAR
ADC
A
AINP_A
AINM_A
DCLK
FCLK
Serial
LVDS
Data
÷2
VCMOUT
Interface
SAR
ADC
B
AINP_B
AINM_B
DOUT_B
DGND
Configuration Registers
SDO
SCLK
SDI
AGND
CS
器件框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBASA74
ADS9218
ZHCSR17 –JANUARY 2023
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................20
7.5 Programming............................................................ 21
7.6 Register Map.............................................................25
8 Application and Implementation..................................45
8.1 Application Information............................................. 45
8.2 Typical Applications.................................................. 45
8.3 Power Supply Recommendations.............................50
8.4 Layout....................................................................... 51
9 Device and Documentation Support............................52
9.1 Documentation Support............................................ 52
9.2 接收文档更新通知..................................................... 52
9.3 支持资源....................................................................52
9.4 Trademarks...............................................................52
9.5 静电放电警告............................................................ 52
9.6 术语表....................................................................... 52
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Thermal Information....................................................5
6.4 Recommended Operating Conditions.........................6
6.5 Electrical Characteristics.............................................7
6.6 Timing Requirements..................................................8
6.7 Switching Characteristics............................................9
6.8 Timing Diagrams.......................................................10
6.9 Typical Characteristics: ADS9218.............................13
6.10 Typical Characteristics: ADS9217...........................14
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................15
Information.................................................................... 52
10.1 Mechanical Data..................................................... 53
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
January 2023
*
Initial Release
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5 Pin Configuration and Functions
40
39
38
37
36
33
32
31
35
34
AVDD_5V
FCLKP
1
2
3
4
5
6
30
29
28
27
26
25
24
23
22
GND
AINAP
FCLKM
DOUTAP
AINAM
DOUTAM
DOUTBP
DOUTBM
DCLKP
VCMOUT
REFM
Thermal Pad
AINBP
7
8
DCLKM
PWDN
AINBM
GND
9
RESET
10
21
AVDD_5V
11
20
12
13
14
15
18
19
16
17
Not to scale
图5-1. RHA Package, 6-mm × 6-mm, 40-Pin VQFN (Top View)
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
AINAM
NO.
4
3
I
I
Negative analog input for ADC A.
Positive analog input for ADC A.
Negative analog input for ADC B.
Positive analog input for ADC B.
1.8-V analog power-supply pin.
5-V analog power-supply pin.
AINAP
AINBM
AINBP
8
I
7
I
AVDD_1V8
AVDD_5V
CS
13, 37
1, 10
17
P
P
I
Chip-select input pin for the configuration interface; active low.
Negative differential data clock output. Connect a 100-Ω resistor between DCLKP
DCLKM
DCLKP
23
24
O
O
and DCLKM close to the receiver.
Positive differential data clock output. Connect a 100-Ω resistor between DCLKP
and DCLKM close to the receiver.
Negative differential data output. Connect a 100-Ω resistor between DOUTAP and
DOUTAM close to the receiver.
Transmits ADC A data in 2-lane mode.
DOUTAM
27
O
Transmits ADC A and ADC B data in 1-lane mode.
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Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Positive differential data output corresponding to ADC A. Connect a 100-Ω resistor
between DOUTAP and DOUTAM close to the receiver.
Transmits ADC A data in 2-lane mode.
DOUTAP
28
O
Transmits ADC A and ADC B data in 1-lane mode.
Positive differential data output corresponding to ADC B in 2-lane mode. Connect a
100-Ω resistor between DOUTBP and DOUTBM close to the receiver. Unused in 1-
lane mode.
DOUTBM
DOUTBP
25
26
O
O
Negative differential data output corresponding to ADC B in 2-lane mode. Connect
a 100-Ω resistor between DOUTBP and DOUTBM close to the receiver. Unused in
1-lane mode.
DVDD_1V8
FCLKM
14, 35, 36
29
P
1.8-V digital power supply.
Negative differential data frame clock output. Connect a 100-Ω resistor between
FCLKP and FCLKM close to the receiver.
O
Positive differential data frame clock output. Connect a 100-Ω resistor between
FCLKP
30
O
P
I
FCLKP and FCLKM close to the receiver.
GND
2, 9, 12, 15, 34, 38
22
Ground.
Power-down control; active low.
Connect to DVDD_1V8 if unused.
PWDN
Internal reference voltage output. External reference voltage input. Connect a 10-
μF decoupling capacitor to REFM.
REFIO
REFM
RESET
39
6, 11, 40
21
I/O
P
Reference ground. Connect to GND.
Reset input; active low.
Connect to DVDD_1V8 if unused.
I
SCLK
18
19
20
31
32
I
I
Serial clock input for the configuration interface.
SDI
Serial data input for the configuration interface.
SDO
O
I
Serial data output for the configuration interface.
SMPL_CLKM
SMPL_CLKP
ADC sampling clock input. Connect this pin to GND for the CMOS sampling clock.
ADC sampling clock input. Clock input for the CMOS sampling clock.
I
Control to enable configuration of the SPI interface; active high.
Connect a pullup resistor to DVDD_1V8 to keep the configuration interface
enabled.
SPI_EN
16
I
Connect to GND if SPI configuration is unused.
Synchronization input for internal averaging filter.
Connect to GND if unused.
SYNC
33
5
I
Common-mode voltage output. Use this output to set the common-mode voltage at
the ADC inputs. Connect a 1-μF decoupling capacitor to GND.
VCMOUT
O
(1) I = input, O = output, I/O = input or output, G = ground, P = power.
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English Data Sheet: SBASA74
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
V
DVDD_1V8 to GND
2.1
AVDD_1V8 to GND
2.1
V
–0.3
AVDD_5V to GND
5.5
V
–0.3
AINAP, AINAM, AINBP, and AINBM to GND
REFIO to REFM
AVDD_5V + 0.3
V
GND –0.3
REFM –0.3
GND –0.3
–0.3
AVDD_5V + 0.3
V
Digital inputs to GND
DVDD_1V8 + 0.3
V
REFM to GND
0.3
10
V
Input current to any pin except supply pins(2)
Junction temperature, TJ
Storage temperature, Tstg
mA
°C
°C
–10
150
150
–40
–60
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Pin current must be limited to 10 mA or less.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, analog input pins AINAP,
AINAM, AINBP, and AINBM((1))
±2000
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all other pins((1))
V
±1000
±500
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
ADS92XX
THERMAL METRIC(1)
RHA (VQFN)
40 PINS
25.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
13.3
7.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ΨJT
7.4
ΨJB
RθJC(bot)
1.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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MAX UNIT
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
POWER SUPPLY
AVDD_5V
Analog power supply
AVDD_5V to GND
AVDD_1V8 to GND
DVDD_1V8 to GND
4.75
1.75
1.75
5
1.8
1.8
5.25
1.85
1.85
V
V
V
AVDD_1V8
Analog power supply
Digital power supply
DVDD_1V8
REFERENCE VOLTAGE
Reference voltage to
the ADC
VREF
External reference
4.076
4.096
4.116
V
ANALOG INPUTS
VIN
Absolute input voltage AINx(1) to GND
0.7
4.1
3.2
V
V
(AINAP –AINAM) and
(AINBP –AINBM)
FSR
VCM
Full-scale input range
–3.2
(AINAP –AINAM) / 2
and
(AINBP –AINBM) / 2
Common-mode input
range
VCMOUT + 0.025
V
V
CMOUT –0.025
TEMPERATURE RANGE
TA
Ambient temperature
25
125
°C
–40
(1) AINx refers to analog inputs AINAP, AINAM, AINBP, and AINBM.
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6.5 Electrical Characteristics
at AVDD_5V = 4.75 V to 5.25 V, AVDD_1V8 = 1.75 V to 1.85 V, DVDD_1V8 = 1.75 V to 1.85 V, internal VREF = 4.096 V, and
maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at
TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
IB
IB
Input bias current
0.5
1
TBD
µA
Input bias current thermal drift
nA/℃
DC PERFORMANCE
Resolution
No missing codes
18
±0.4
±1
Bits
LSB
DNL
INL
Differential nonlinearity
0.75
4
–0.75
–4
Integral nonlinearity
Input offset error
LSB
V(OS)
±2
LSB
dVOS/dT Input offset error thermal drift
Offset error match
±1
ppm/°C
LSB
0.5
V(OS) (ADC_A –ADC_B)
GE (ADC_A –ADC_B)
GE
Gain error(1)
±0.01
±1
0.05 %FSR
ppm/°C
–0.05
dGE/dT
Gain error thermal drift((2))
Gain error match
±0.001
%FSR
AC PERFORMANCE
fIN = 2 kHz
fIN = 1 MHz
fIN = 2 kHz
fIN = 1 MHz
fIN = 2 kHz
fIN = 1 MHz
fIN = 2 kHz
fIN = 1 MHz
fIN = 1 MHz
95
94
SINAD
SNR
Signal-to-noise + distortion ratio
dB
dB
dB
dB
95.1
94.1
–115
–102
120
102
TBD
0.3
Signal-to-noise ratio
THD
Total harmonic distortion
Spurious-free dynamic range
SFDR
Isolation crosstalk
Aperture Jitter
dB
psRMS
ADS9218
ADS9217
90
BW
MHz
Input Bandwidth (–3-dB)
45
COMMON-MODE OUTPUT BUFFER
VCMOUT Common-mode output voltage
Output current drive
2.4
V
0
5
μA
LVDS OUTPUT (CLKOUT, DOUTA, and DOUTB)
VODIFF
VOCM
Differential output voltage
250
350
1.1
450
mV
V
RL = 100Ω
RL = 100Ω
Output common-mode voltage
1.08
1.32
CMOS INPUTS (CS, SCLK, and SDI)
VIL
VIH
Input low logic level
Input high logic level
0.3 DVDD
DVDD
V
V
–0.3
0.7 DVDD
CMOS OUTPUT (SDO)
VOL
VOH
Output low logic level
Output high logic level
IOL = 200 µA sink
0
0.2 DVDD
DVDD
V
V
IOH = 200 µA source
0.8 DVDD
POWER SUPPLY
Maximum throughput
36
TBD
TBD
IAVDD_5V Supply current from AVDD_5V
mA
No conversion, external reference
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6.5 Electrical Characteristics (continued)
at AVDD_5V = 4.75 V to 5.25 V, AVDD_1V8 = 1.75 V to 1.85 V, DVDD_1V8 = 1.75 V to 1.85 V, internal VREF = 4.096 V, and
maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at
TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TBD
TBD
TBD
TBD
UNIT
Maximum throughput
67
mA
IAVDD_1V8 Supply current from AVDD_1V8
No conversion, external reference
Maximum throughput
mA
34
5
IDVDD_1V8 Supply current from DVDD_1V8
mA
No conversion, external reference
(1) These specifications include full temperature range variation but not the error contribution from internal reference.
6.6 Timing Requirements
at AVDD_5V = 4.75 V to 5.25 V, AVDD_1V8 = 1.75 V to 1.85 V, DVDD_1V8 = 1.75 V to 1.85 V, and maximum throughput
(unless otherwise noted); minimum and maximum values at TA = -40°C to +125°C; typical values at TA = 25°C.
MIN
MAX
UNIT
CONVERSION CYCLE
fCYCLE Sampling frequency
tCYCLE ADC cycle-time period
ADS9218
ADS9217
10
5
MSPS
1/fCYCLE
0.48
s
tPL_SMPLCLK Sample clock low time
tPH_SMPLCLK Sample clock high time
0.52
0.52
10
tCYCLE
tCYCLE
MHz
ns
0.48
fCLK
tCLK
Maximum SCLK frequency
Minimum SCLK time period
100
SPI INTERFACE TIMINGS
thi_CSZ
tPH_CK
tPL_CK
Pulse duration: CS high
220
0.48
0.48
20
ns
tCLK
tCLK
ns
SCLK high time
0.52
0.52
SCLK low time
td_CSCK
tsu_CKDI
tht_CKDI
td_CKCS
Setup time: CS falling to the first SCLK rising edge
Setup time: SDI data valid to the corresponding SCLK rising edge
Hold time: SCLK rising edge to corresponding data valid on SDI
Delay time: last SCLK falling edge to CS rising
10
ns
5
ns
5
ns
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6.7 Switching Characteristics
at AVDD_5V = 4.75 V to 5.25 V, AVDD_1V8 = 1.75 V to 1.85 V, DVDD_1V8 = 1.75 V to 1.85 V, and maximum throughput
(unless otherwise noted); minimum and maximum values at TA = -40°C to +125°C; typical values at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
MAX
25
UNIT
ms
ps
RESET
tPU
Power-up time for device
LVDS DATA INTERFACE
tRT
Rise time
600
600
with 50Ω
transmission line of
length = 20 mm,
differential RL =
100Ω, and CL = 1 pF
tFT
Fall time
ps
ADS9218
ADS9217
100
200
ns
ns
ns
%
tCYCLE
tDCLK
Sampling clock period
Clock output
4.167
45
Clock duty cycle
55
Time delay: DCLKP rising to corresponding at 5Msps, SDR
data valid mode
td_DCLKDO
toff_DCLKDO_r
toff_DCLKDO_f
tPD
0.8
ns
ns
ns
ns
µs
–0.8
tDCLK/4 –0.8
tDCLK/4 –0.8
Time offset: DCLKP rising to corresponding at 5Msps, DDR
data valid mode
tDCLK/4 + 0.8
tDCLK/4 + 0.8
tDCLK
Time offset: DCLKP falling to corresponding at 5Msps, DDR
data valid
mode
Time delay: SMPL_CLK falling to DCLKP
rising
Time delay: free running clock connected to
SMPL_CLK to ADC data valid
tPU_SMPL_CLK
100
SPI INTERFACE TIMINGS
Time delay: 8th SCLK rising edge to SDO
enable
tden_CKDO
tdz_CKDO
td_CKDO
30
30
20
ns
ns
ns
ns
Time delay: 24th SCLK rising edge to SDO
going Hi-Z
Time delay: SCLK launch edge to
corresponding data valid on SDO
Hold time: SCLK launch edge to previous
data valid on SDO
tht_CKDO
2
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6.8 Timing Diagrams
Sample N
Sample N + 1
tCYCLE
SMPL_CLK
tPH_SMPLCLK
tPL_SMPLCLK
tPD
DCLKP –
1
2
5
6
7
12
13
14
15
22
23
24
DCLKM
6 x tDCLK
tDCLK
FCLKP –
FCLKM
toff_DCLKDO_r
toff_DCLKDO_f
DOUTAP –
DOUTAM
D
D
D
D
D
D
D
9
D
8
D
7
D
6
D
1
D
0
D
23
D
D
D
D
D
5
D
4
D
3
D
2
D
1
D
0
D
19
23 22 21 20 11 10
22 21 20 19
ADC A Data
ADC B Data
Data for sample N
Data for sample N –
图6-1. LVDS Data Interface: 1-Lane DDR
Sample N+1
Sample N
tCYCLE
SMPL_CLK
tPH_SMPLCLK
tPL_SMPLCLK
tPD
DCLKP –
DCLKM
27
1
1
2
3
12
13
24
25
26
46
47
48
12 x tDCLK
tDCLK
FCLKP –
FCLKM
td_DCLKDO
ADC A Data
ADC B Data
DOUTAP –
DOUTAM
D23
ADC A
D22
ADC A
D8
ADC A
D0
ADC A
D23
ADC B
D22
ADC B
D2
ADC B
D1
ADC B
D0
ADC B
Data for sample N –
Data for sample N
图6-2. LVDS Data Interface: 1-Lane SDR
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Sample N+1
Sample N
tCYCLE
SMPL_CLK
tPH_SMPLCLK
tPL_SMPLCLK
tPD
DCLKP –
DCLKM
1
2
3
4
5
6
7
8
9
10
11
12
6 x tDCLK
tDCLK
FCLKP –
FCLKM
toff_DCLKDO_r
toff_DCLKDO_f
ADC A Data
DOUTAP –
DOUTAM
D
D
D
D
D
D
D
D
16
D
D
D
D
D
D
10
D
9
D
8
D
7
D
5
D
4
D
3
D
2
D
1
D
0
D
24
D
6
23 22 21 20 19 18 17
15 14 13 12 11
ADC B Data
DOUTBP –
DOUTBM
D
D
D
D
D
D
D
D
16
D
D
D
D
D
D
10
D
9
D
8
D
7
D
5
D
4
D
3
D
2
D
1
D
0
D
24
D
6
23 22 21 20 19 18 17
15 14 13 12 11
Data for sample N
Data for sample N –
图6-3. LVDS Data Interface: 2-Lane DDR
Sample N+1
Sample N
tCYCLE
SMPL_CLK
tPH_SMPLCLK
tPL_SMPLCLK
tPD
DCLKP –
DCLKM
17
1
1
2
3
12
13
14
15
16
22
23
24
12 x tDCLK
tDCLK
FCLKP –
FCLKM
td_DCLKDO
ADC A Data
DOUTAP –
DOUTAM
D23
ADC A
D22
ADC A
D12
ADC A
D11
ADC A
D10
ADC A
D9
ADC A
D8
ADC A
D2
ADC A
D1
ADC A
D0
ADC A
ADC B Data
D10
DOUTBP –
DOUTBM
D23
ADC B
D22
ADC B
D12
ADC B
D11
ADC B
D9
ADC B
D8
ADC B
D2
ADC B
D1
ADC B
D0
ADC B
ADC B
Data for sample N –
Data for sample N
图6-4. LVDS Data Interface: 2-Lane SDR
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VOD
VDIFF = (OUT+) – –OUT)
–VOD
80%
20%
80%
20%
tRT
tFT
图6-5. LVDS Output Transition Times
thi_CS
CS
td_CKCS
td_CSCK
SCLK
SDI
tsu_CKDI
tht_CKDI
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
D
D
D
D
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
15 14 13 12 11
tden_CKDO
td_CKDO
tdz_CKDO
tht_SDO
Hi-Z
DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO
15 14 13 12 11 10
SDO
9
8
7
6
5
4
3
2
1
0
SDO active only when reading registers; Hi-Z otherwise
图6-6. Configuration SPI Interface
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6.9 Typical Characteristics: ADS9218
at TA = 25°C, AVDD_5V = 5 V, AVDD_1V8 = 1.8 V, DVDD_1V8 = 1.8 V, external VREF = 4.096V, and maximum throughput
(unless otherwise noted)
0
0.75
0.45
-40
0.15
-80
-0.15
-0.45
-0.75
-120
-160
-200
0
65536
131072
Output Code
196608
262144
0
1250
2500
Frequency (kHz)
3750
5000
Typical INL = ±0.6 LSB
fIN = 2 kHz, SNR = 94.8 dB, THD = –115.1 dB
图6-7. Typical FFT
图6-8. Typical INL
0.6
0.3
0
0
-3
-6
-0.3
-0.6
-9
-12
0
65536
131072
Output Code
196608
262144
0
40
80
120
160
200
Frequency (MHz)
Typical DNL = ±0.4 LSB
Typical BW (–3 dB) = 90 MHz
图6-9. Typical DNL
图6-10. Typical Analog Input Bandwidth
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6.10 Typical Characteristics: ADS9217
at TA = 25°C, AVDD_5V = 5 V, AVDD_1V8 = 1.8 V, DVDD_1V8 = 1.8 V, external VREF = 4.096V, and maximum throughput
(unless otherwise noted)
0
0.75
0.45
-40
0.15
-80
-0.15
-0.45
-0.75
-120
-160
-200
0
65536
131072
Output Code
196608
262144
0
625
1250
Frequency (kHz)
1875
2500
Typical INL = ±0.6 LSB
fIN = 2 kHz, SNR = 94.8 dB, THD = –115.2 dB
图6-11. Typical FFT
图6-12. Typical INL
0.6
0.3
0
0
-3
-6
-9
-12
-15
-18
-21
-24
-0.3
-0.6
0
65536
131072
Output Code
196608
262144
0
40
80
120
160
200
Frequency (MHz)
Typical DNL = ±0.4 LSB
Typical BW (–3 dB) = 45 MHz
图6-13. Typical DNL
图6-14. Typical Analog Input Bandwidth
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7 Detailed Description
7.1 Overview
The ADS921x is an 18-bit, 10-MSPS/ch, dual-channel, simultaneous-sampling, analog-to-digital converter
(ADC). The ADS921x integrates a high-impedance buffer at the ADC inputs, voltage reference, reference buffer,
and common-mode voltage output buffer. The ADS9218 supports unipolar differential analog input signals. The
buffer at the ADC inputs is optimized for low-distortion and low-power operation.
For DC level shifting of the analog input signals, the device has a common-mode voltage output buffer. The
common-mode voltage is derived from the output of the integrated reference buffer. When a conversion is
initiated, the differential input between the (AINAP – AINAM) and (AINBP – AINBM) pins is sampled. The
ADS921x uses a clock input on the SMPL_CLKP pin to initiate conversions.
The ADS921x consumes only 180 mW/ch of power when operating at 10 MSPS/ch, which includes the power
dissipation of the buffer at the ADC inputs. The serial LVDS (SLVDS) digital interface simplifies board layout,
timing, firmware, and supports full throughput at lower clock speeds.
7.2 Functional Block Diagram
AVDD_5V
AVDD_1V8
REFIO
SMPL_CLK
DVDD_1V8
DOUTA
SAR
ADC
A
AINAP
AINAM
DCLK
FCLK
Serial
LVDS
Data
÷2
VCMOUT
Interface
4.096V
SAR
ADC
B
AINBP
AINBM
DOUTB
Configuration Registers
SDO
SCLK
SDI
CS
GND
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7.3 Feature Description
7.3.1 Analog Inputs
The analog inputs of the ADS921x are intended to be driven differentially. Both AC coupling and DC coupling of
the analog inputs is supported. The analog inputs are designed for an input common-mode voltage that must be
equal to the voltage on the VCMOUT pin. DC-coupled input signals must have a common-mode voltage that
meets the device input common-mode voltage range. 图7-1 shows an equivalent input network diagram.
AVDD_5V
220 pF
2
0.6
AINAP
AINBP
ADC
0.6
AINAM
AINBM
2
220 pF
AVDD_5V
图7-1. Equivalent Input Network
7.3.2 Analog Input Bandwidth
图 6-10 and 图 6-14 illustrate the analog full-power input bandwidth of the ADS921x device family. The –3-dB
bandwidth is 90 MHz and 45 MHz for the ADS9218 and ADS9217, respectively.
7.3.3 ADC Transfer Function
The ADS921x supports a ±3.2-V differential input range. The device outputs 18-bit conversion data in either
straight-binary or binary two's-complement formats. As shown in 表 7-1, the format for the output codes is the
same across all analog channels. The format for the output codes can be configured using the DATA_FORMAT
field in register address 0x0D. The least significant bit (LSB) for the ADC is given by 1 LSB = 6.4 V / 218
.
表7-1. Transfer Characteristics
ADC OUTPUT IN TWO'S-
COMPLEMENT FORMAT
ADC OUTPUT IN STRAIGHT-
BINARY FORMAT
INPUT VOLTAGE
DESCRIPTION
Negative full-scale code
Mid-code
0x80000
0x00000
0x1FFFF
0x00000
0x1FFFF
0x3FFFF
≤–3.2 V + 1 LSB
0 V + 1 LSB
Positive full-scale code
≥3.2 V –1 LSB
7.3.4 Reference
The ADS921x has a precision, low-drift voltage reference internal to the device. For best performance, filter the
internal reference noise by connecting a 10-µF ceramic bypass capacitor to the REFIO pin. An external
reference can also be connected at the REFIO pin with the internal reference voltage disabled by writing to
PD_REF field in register address 0xC1.
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7.3.4.1 Internal Reference Voltage
The ADS921x features an internal reference voltage with a nominal output voltage of 4.096 V. On power-up, the
internal reference is enabled by default. Place a minimum 10-µF decoupling capacitor between the REFIO and
REFM pins. 图7-2 shows a block diagram of the internal reference voltage.
AVDD_5V
SAR
ADC
A
REFIO
External capacitor
10 μF
for reference
noise reduction
÷2
1 k
GND
PD_REF = 0
GND
User register bit
SAR
4.096 V
ADC
B
图7-2. Internal Reference Voltage
7.3.4.2 External Reference Voltage
An external 4.096-V reference voltage can be connected at the REFIO pin with an appropriate decoupling
capacitor placed between the REFIO and REFM pins. For improved thermal drift performance, the REF7040 is
recommended. To disable the internal reference, set PD_REF = 1b in address 0xC1 in register bank 1. The
REFIO pin has electrostatic discharge (ESD) protection diodes connected to the AVDD_5V and REFM pins. 图
7-3 shows an external reference diagram.
5V
VIN
EN
OUTF
OUTS
AVDD_5V
REF7040
SAR
ADC
A
GND
REFIO
REFM
10 μF
÷2
1 k
PD_REF = 1
User register bit
GND
SAR
ADC
B
4.096 V
GND
图7-3. External Reference Voltage
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7.3.5 Data Interface
The ADS921x features a high-speed serial LVDS data interface with 2-lane and 1-lane options for data output.
The host can configure the output data frame width to 20 bits or 24 bits with the single-data rate (SDR) and
double-data rate (DDR) modes.
The ADS921x generates a data clock DCLK that is a multiple of the ADC sampling clock SMPL_CLK. The data
clock frequency depends on the number of data output lanes (1 or 2), data frame width (20 bit or 24 bit) and data
rate (SDR or DDR). 方程式 1 calculates the DCLK speed. 表 7-2 lists the possible values for the output data
clock frequency.
2 ADC channels × Data Frame Width 24 bit or 20 bit
Data Lanes 1 or 2 × Data Rate SDR = 1, DDR = 2
DCLK speed =
× SMPL_CLK
(1)
表7-2. Data Clock (DCLK) Speed(1)
DCLK
DCLK
DATA FRAME
WIDTH (Bits)
DATA RATE (1 =
SDR, 2 = DDR)
SMPL_CLK
MULTIPLIER
ADC CHANNELS
OUTPUT LANES
(SMPL_CLK = 5 (SMPL_CLK = 10
MHz)
MHz)
1
2
1
2
1
2
1
2
48
24
24
12
40
20
20
10
240 MHz
120 MHz
120 MHz
60 MHz
200 MHz
100 MHz
100 MHz
50 MHz
480 MHz
240 MHz
240 MHz
120 MHz
400 MHz
200 MHz
200 MHz
100 MHz
1
24
2
1
2
2
20
(1) The LVDS output data and clock are specified up to 600 MHz. Faster speeds are not supported.
7.3.5.1 Data Frame Width
As shown in 图 7-4, the ADS921x supports 24-bit and 20-bit data frame width options. Configure the
DATA_WIDTH field in address 0x12 to select the data frame width. The default output data frame width is 24
bits. The ADC resolution is 18 bits, represented by 20 bits. The two extra lower bits in the 20-bit data can be
ignored.
2 bit noise
(don’t care)
18 bit (MSB aligned) ADC conversion result
4-bit (0000)
DATA_WIDTH = 0 (20-bit)
DATA_WIDTH = 1 (24-bit)
图7-4. Data Frame Width Composition
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7.3.5.2 Test Patterns for Data Interface
The ADS921x features test patterns that can be used by the host for debugging and verifying the data interface.
The test patterns replace the ADC output data with predefined digital data. The test patterns can be enabled by
configuring the corresponding register addresses 0x13 through 0x1B in bank 1.
The ADS921x supports the following test patterns:
• User-defined output: User-defined, 24-bit pattern. Separate patterns for ADC A and ADC B; see the User-
Defined Test Pattern section.
• Ramp output: Digital ramp output with a user-defined increment between two steps. There are separate ramp
outputs for ADC A and ADC B; see the Ramp Test Pattern section.
• Alternate output: User-defined, 24-bit outputs that alternate between ADC A and ADC B user-defined
patterns; see the User-Defined Alternating Test Pattern section.
To disable the test patterns, set TEST_PAT_EN_CHA and TEST_PAT_EN_CHB to 0b.
7.3.5.2.1 User-Defined Test Pattern
The user-defined test pattern allows the host to specify a fixed 24-bit value that is output by the ADS921x.
Configure the registers in bank 1 to enable the user-defined test pattern:
• Configure the test patterns in TEST_PAT0_CHA (address = 0x14, 0x15) and TEST_PAT0_CHB (address =
0x19, 0x1A)
• Set TEST_PAT_EN_CHA = 1, TEST_PATMODE_CHA = 0 (address = 0x13) and TEST PAT_EN_CHB = 1,
TEST_PATMODE_CHB = 0 (address = 0x18)
The ADS921x outputs the TEST_PAT0_CHA and TEST_PAT0_CHB register values in place of the ADC A and
ADC B data, respectively.
7.3.5.2.2 User-Defined Alternating Test Pattern
The user-defined alternating test pattern allows the host to specify two fixed 24-bit values that are output by the
ADS921x alternately. Configure the registers in bank 1 to enable the user-defined alternating test pattern:
• Configure the test patterns in TEST_PAT0_CHA (address = 0x14, 0x15), TEST_PAT1_CHA (address = 0x15,
0x16) and TEST_PAT0_CHB (address = 0x19, 0x1A), TEST_PAT1_CHB (address = 0x1A, 0x1B)
• Set TEST_PAT_EN_CHA = 1, TEST_PATMODE_CHA = 3 (address = 0x13) and TEST PAT_EN_CHB = 1,
TEST_PATMODE_CHB = 3 (address = 0x18)
The ADS921x outputs the TEST_PAT0_CHA and TEST_PAT0_CHB register values in place of the ADC A and
ADC B data, respectively, in one output frame and the TEST_PAT1_CHA and TEST_PAT1_CHB register values
in the next frame.
7.3.5.2.3 Ramp Test Pattern
The ramp test pattern allows the host to specify a digital ramp that is output by the ADS921x. Configure the
registers in bank 1 to enable the ramp test pattern:
• Configure the increment value between two successive steps of the digital ramp in the RAMP_INC_CHA
(address = 0x13) and RAMP_INC_CHB (address = 0x18) registers, respectively. The digital ramp increments
by N + 1, where N is the value configured in these registers.
• Set TEST_PAT_EN_CHA = 1, TEST_PATMODE_CHA = 2 (address = 0x13) and TEST PAT_EN_CHB = 1,
TEST_PATMODE_CHB = 2 (address = 0x18).
The ADS921x outputs digital ramp values in place of the ADC A and ADC B data, respectively.
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7.3.6 ADC Sampling Clock Input
Use a low jitter external clock with a high slew rate to maximize the ADC SNR performance. The ADS921x can
be operated using a single-ended clock input where the single-ended clock consumes less power consumption.
Clock amplitude impacts the ADC aperture jitter and consequently the SNR. For maximum SNR performance, a
large clock signal with fast slew rates must be provided.
The sampling clock must be a free-running continuous clock. The ADC generates valid output data, a data clock,
and a frame clock tPU_SMPL_CLK, as specified in the Switching Characteristics section after a free-running
sampling clock is applied. ADC output data, the data clock, and the frame clock are invalid when the sampling
clock is stopped.
图 7-5 shows a diagram of the single-ended sampling clock. Connect a single-ended sampling clock to
SMPL_CLKP and connect SMPL_CLKM to ground.
1.8V
SMPL_CLKP
0V
ADS92XX
SMPL_CLKM
GND
图7-5. Single-Ended Sampling Clock
7.4 Device Functional Modes
7.4.1 Normal Operation
In normal operating mode, the ADS921x is powered-up and digitizes the analog inputs at the falling edge of the
sampling clock. The ADC outputs the data clock, frame clock, and MSB-aligned, 18-bit conversion result.
7.4.2 Power-Down Options
Power-down mode can be enabled by a register write or with the PWDN pin. The PWDN pin has an internal
pullup resistor to DVDD_1V8. The PWDN pin must be pulled low to enable power-down mode.
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7.5 Programming
7.5.1 Register Write
Register write access is enabled by setting SPI_RD_EN = 0b. The 16-bit configuration registers are grouped in
three register banks and are addressable with an 8-bit register address. Register bank 1 and register bank 2 can
be selected for read or write operation by configuring the PAGE_SEL0 and PAGE_SEL1 bits, respectively.
Registers in bank 0 are always accessible, irrespective of the PAGE_SELx bits because the register addresses
are unique and are not used in register banks 1 and 2.
As shown in 图7-6, steps to write to a register are:
1. Frame 1: Write to register address 0x03 in register bank 0 to select either register bank 1 or bank 2 for a
subsequent register write. This frame has no effect when writing to registers in bank 0.
2. Frame 2: Write to a register in the bank selected in frame 1. Repeat this step for writing to multiple registers
in the same register bank.
Frame 1
24-bits
Frame 2
CS
SCLK
SDI
{ addr[23:16] = 0x03, data[15:0] = 0x0002 or
0x0010 }
{ addr[23:16] = REG_ADDR, data[15:0] = DATA }
Register Write
Register Write for Bank Selection (ADDR = 0x03)
Not Required for Register Bank 0
Logic 0 (when SPI_MODE = 0b) and Hi-Z (when SPI_MODE = 1b)
SDO
图7-6. Register Write
7.5.2 Register Read
Select the desired register bank by writing to register address 0x03 in register bank 0. Register read access is
enabled by setting SPI_RD_EN = 1b and SPI_MODE = 1b in register bank 0. As illustrated in 图 7-7, registers
can be read using two 24-bit SPI frames after SPI_RD_EN and SPI_MODE are set. The first SPI frame selects
the register bank. The ADC returns the 16-bit register value in the second SPI frame corresponding to the 8-bit
register address.
As illustrated in 图7-7, steps to read a register are:
1. Frame 1: With SPI_RD_EN = 0b, write to register address 0x03 in register bank 0 to select the desired
register bank 0 for reading.
2. Frame 2: Set SPI_RD_EN = 1b and SPI_MODE = 1b in register address 0x00 in register bank 0.
3. Frame 3: Read any register in the selected bank using a 24-bit SPI frame containing the desired register
address. Repeat this step with the address of any register in the selected bank to read the corresponding
register.
4. Frame 4: Set SPI_RD_EN = 0 to disable register reads and re-enable register writes.
5. Repeat steps 1 through 4 to read registers in a different bank.
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Frame 1
Frame 2
Frame 3
Frame 4
CS
24-bits
SCLK
SDI
{ addr[23:16] = 0x03, data[15:0] = 0x0002 or
0x0010 }
{ addr[23:16] = 0x00, data[15:0] = 0x0006 }
Register Write for Read Enable (ADDR = 0x00)
{ addr[23:16] = REG_ADDR, data[15:0] = 0 }
{ addr[23:16] = 0x00, data[15:0] = 0x0004 }
Register Write for Bank Selection (ADDR = 0x03)
Not Required for Register Bank 0
Register Write for Read Disable (ADDR = 0x00)
Register Read: 8-bit address of register to be read
Hi-Z (when SPI_MODE = 1b)
Logic 0 (when SPI_MODE = 0b)
16-bit Register Data
SDO
图7-7. Register Read
7.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
图7-8 shows a typical connection diagram showing multiple devices in a daisy-chain topology.
SCLK
CS
SCLK
ADS92XX
SCLK
ADS92XX
SCLK
ADS92XX
SCLK
ADS92XX
CS
CS
CS
CS
HOST
ADC4
ADC3
ADC2
ADC1
SDO
SDI
SDO
SDI
SDO
SDI
SDO
SDI
24-bit
24-bit
24-bit
24-bit
PICO
POCI
图7-8. Daisy-Chain Connections for SPI Configuration
The CS and SCLK inputs of all ADCs are connected together and are controlled by a single CS and SCLK pin of
the controller, respectively. The SDI input pin of the first ADC in the chain (ADC1) is connected to the peripheral
IN controller OUT (PICO) pin of the controller, the SDO output pin of ADC1 is connected to the SDI input pin of
ADC2, and so on. The SDO output pin of the last ADC in the chain (ADC4) is connected to the peripheral OUT
controller IN (POCI) pin of the controller. The data on the PICO pin passes through ADC1 with a 24-SCLK delay,
as long as CS is active.
The daisy-chain mode must be enabled after power-up or after the device is reset. Set the daisy-chain length in
the DAISY_CHAIN_LENGTH register to enable daisy-chain mode. The daisy-chain length is the number of
ADCs in the chain, excluding ADC1. In 图7-8, the DAISY_CHAIN_LENGTH is 3.
7.5.3.1 Register Write With Daisy-Chain
Writing to registers in daisy-chain configuration requires N × 24 SCLKs in one SPI frame. Register writes in a
daisy-chain configuration containing four ADCs, as shown in 图7-8, requires 96 SCLKs.
The daisy-chain mode is enabled on power-up or after device reset. Configure the DAISY_CHAIN_LENGTH field
to enable daisy-chain mode. The waveform in 图 7-9 must be repeated N times, where N is the number of ADCs
in the daisy-chain. 图 7-10 provides the SPI waveform, containing N SPI frames, for enabling daisy-chain mode
for N ADCs.
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CS
N x 24 bits
SCLK
DADCN
DADC3
DADC2
DADC1
PICO
POCI
Logic 0 (when SPI_MODE = 0b)
图7-9. Register Write With Daisy-Chain
DADC1[23:0] = DADC2[23:0] = DADC3[23:0] = DADCN[23:0] = { 0000 0001, 0000 0000, N-1, 00}
Frame 1
Frame 2
Frame 3
Frame N
CS
N x 24 bits
SCLK
DADCN
PICO
DADC3
DADC2
DADC1
DADCN
DADC3
DADC2
DADC1
DADCN
DADC3
DADC2
DADC1
DADCN
DADC3
DADC2
DADC1
DAISY_CHAIN_LENGTH = 3 {ADC1}
DAISY_CHAIN_LENGTH = 0 {ADC2, ADC3, and ADCN} DAISY_CHAIN_LENGTH = 0 {ADC3, ADCN}
DAISY_CHAIN_LENGTH = 3 {ADC1 and ADC2}
DAISY_CHAIN_LENGTH = 3 {ADC1, ADC2 and ADC3}
DAISY_CHAIN_LENGTH = 0 {ADCN}
DAISY_CHAIN_LENGTH = 3 {ADC1,
ADC2, ADC3 and ADCN}
POCI
Logic 0 (when SPI_MODE = 0b)
图7-10. Register Write to Configure Daisy-Chain Length
7.5.3.2 Register Read With Daisy-Chain
图 7-11 illustrates an SPI waveform for reading registers in daisy-chain configuration. Steps for reading registers
from N ADCs connected in daisy-chain are:
1. Register read is enabled by writing to the following registers:
a. Write to PAGE_SEL to select the desired register bank
b. Enable register reads by writing SPI_RD_EN = 0b (default on power-up)
2. With the register bank selected and SPI_RD_EN = 0b, the controller can read register data by:
a. N × 24-bit SPI frame containing the 8-bit register address to be read: N times (0xFE, 0x00, 8-bit register
address)
b. N × 24-bit SPI frame to read out register data: N times (0xFF, 0xFF, 0xFF)
The 0xFE in step 2a configures the ADC for register read from the specified 8-bit address. At the end of step 2a,
the output shift register in the ADC is loaded with register data. The ADC returns the 8-bit register address and
corresponding 16-bit register data in step 2b.
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CS
N x 24 bits
N x 24 bits
SCLK
24 bits
0x00
24 bits
0xFF
8-bit register
address
0xFE
PICO
0xFE
0xFF
0xFF
0xFF
8-bit
address
8-bit
address
16-bit register data
POCI
图7-11. Register Read With Daisy-Chain
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7.6 Register Map
7.6.1 Register Bank 0
图7-12. Register Bank 0 Map
ADD
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESERVED
SPI_MO SPI_RD SOFT_R
00h
01h
03h
DE _EN ESET
RESERVED
DAISY_CHAIN_LEN
REG_BANK_SEL
RESERVED
RESERVED
7.6.1.1 Register 0h (offset = 0h) [reset = 0h]
图7-13. Register 0h
15
14
13
12
11
10
9
8
RESERVED
W-0h
7
6
5
4
3
2
1
0
RESERVED
W-0h
SPI_MODE
W-0h
SPI_RD_EN
W-0h
SOFT_RESET
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-14. Register 00 Field Descriptions
Bit
Field
Type
Reset
Description
15-3
RESERVED
W
0h
Reserved. Do not change from default reset value.
Select between legacy SPI mode and daisy-chain SPI
mode for the configuration interface for register access.
0 : Daisy-chain SPI mode
2-2
SPI_MODE
W
0h
1 : Legacy SPI mode
Enable register read access
0 : Register read disabled.
1 : Register read enabled.
1-1
0-0
SPI_RD_EN
W
W
0h
0h
Software reset all registers to default values
0 : Normal operation
SOFT_RESET
1 : Reset device registers
7.6.1.2 Register 1h (offset = 1h) [reset = 0h]
图7-15. Register 1h
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
RESERVED
R/W-0h
DAISY_CHAIN_LEN
R/W-0h
RESERVED
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
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图7-16. Register 01 Field Descriptions
Bit
Field
Type
Reset
Description
15-7
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Configure the number of devices connected in daisy-chain
for the configuration SPI interface.
0 : 1 device in daisy-chain
1 : 2 devices in daisy-chain
2 : 3 devices in daisy-chain
DAISY_CHAIN_L
EN
6-2
R/W
R/W
0h
0h
31 : 32 devices in daisy-chain
1-0
RESERVED
Reserved. Do not change from default reset value.
7.6.1.3 Register 3h (offset = 3h) [reset = 2h]
图7-17. Register 3h
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
REG_BANK_SEL
R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-18. Register 03 Field Descriptions
Bit
Field
Type
Reset
Description
15-8
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Register bank selection for read and write operations.
0 : Select Register Bank 0
2 : Select Register Bank 1
7-0
REG_BANK_SEL
R/W
2h
16 : Select Register Bank 2
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7.6.2 Register Bank 1
图7-19. Register Bank 1 Map
ADD
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESERV
ED
TMP_REG_L8_3
TMP_REG_L8_2
TMP_REG_L8_1
08h
0Bh
0Ch
RESERVED
TMP_REG_LB_1
RESERVED
RESERVED
TMP_REG_LC_1
RESERVED
DATA_F
ORMAT
TMP_REG_LD_2
TMP_RE
G_LD_1
RESERVED
0Dh
11h
12h
RESERVED
TMP_RE TMP_RE TMP_RE TMP_RE
G_L11_5 G_L11_4 G_L11_3 G_L11_2
RESERVED
TMP_REG_L11_1
RESERVED
XOR_EN
DATA_WIDTH
DATA_L
ANES
RESERVED
RAMP_INC_CH0
TEST_PAT_MODE_ TEST_P RESERV
CH0
AT_EN_
CH0
ED
13h
14h
15h
16h
TEST_PAT0_CH0
TEST_PAT1_CH0
TEST_PAT1_CH0
RESERVED
TEST_PAT0_CH0
RAMP_INC_CH1
TEST_PAT_MODE_ TEST_P RESERV
CH1
AT_EN_
CH1
ED
18h
19h
1Ah
1Bh
TEST_PAT0_CH1
TEST_PAT1_CH1
TEST_PAT1_CH1
TEST_PAT0_CH1
RESERV TMP_RE TMP_RE
RESERVED
RESERVED
TMP_RE
G_L33_2
RESERVED
TMP_RE
G_L33_1
RESERVED
33h
34h
50h
ED
G_L33_4 G_L33_3
TMP_RE
G_L34_3
RESERVED
TMP_RE TMP_RE
G_L34_2 G_L34_1
RESERV
ED
TMP_REG_L50_3
TMP_REG_L50_2
TMP_REG_L50_1
TMP_REG_L51_1
TMP_REG_L52_1
RESERV
ED
TMP_REG_L51_3
TMP_REG_L51_2
TMP_REG_L52_2
51h
52h
C0h
RESERVED
DCLK_CFG4
DCLK_CFG2
RESERVED
DCLK_CFG1
PD_REF RESERVED
RESERVED
RESERVED
PD_ADC
DATA_R
DCLK_CFG3
C1h
ATE
7.6.2.1 Register 8h (offset = 8h) [reset = 0h]
图7-20. Register 8h
15
14
13
5
12
11
10
9
8
RESERVED
R/W-0h
TMP_REG_L8_3
R/W-0h
TMP_REG_L8_2
R/W-0h
7
6
4
3
2
1
0
TMP_REG_L8_2
R/W-0h
TMP_REG_L8_1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-21. Register 08 Field Descriptions
Bit
Field
Type
Reset
Description
15-15
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register.
0 : Normal device operation.
14-10
TMP_REG_L8_3
R/W
0h
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图7-21. Register 08 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
8 : Use for 40-bit 1-lane mode.
10 : Use for 48-bit 1-lane mode.
9-5
4-0
TMP_REG_L8_2
TMP_REG_L8_1
R/W
0h
Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
4 : Use for 40-bit 1-lane, and 48-bit 1-lane modes.
R/W
0h
7.6.2.2 Register Bh (offset = Bh) [reset = 0h]
图7-22. Register Bh
15
14
13
12
11
10
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
2
RESERVED
R/W-0h
TMP_REG_LB_1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-23. Register 0B Field Descriptions
Bit
Field
Type
Reset
Description
15-5
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register.
4-0
TMP_REG_LB_1
R/W
0h
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
6 : Use for 40-bit 1-lane, and 40-bit 1-lane modes.
7.6.2.3 Register Ch (offset = Ch) [reset = 0h]
图7-24. Register Ch
15
14
13
12
11
10
9
8
RESERVED
R/W-0h
TMP_REG_LC_1
R/W-0h
7
6
5
4
3
2
1
0
TMP_REG_LC_1
R/W-0h
RESERVED
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-25. Register 0C Field Descriptions
Bit
Field
Type
Reset
Description
15-10
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register.
9-5
4-0
TMP_REG_LC_1
RESERVED
R/W
R/W
0h
0h
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
1 : Use for 40-bit 1-lane, and 48-bit 1-lane modes.
Reserved. Do not change from default reset value.
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7.6.2.4 Register Dh (offset = Dh) [reset = 2002h]
图7-26. Register Dh
15
14
6
13
12
11
10
9
1
8
0
RESERVED
R/W-0h
DATA_FORMAT
R/W-1h
TMP_REG_LD_2
R/W-0h
7
5
4
3
2
TMP_REG_LD_
1
RESERVED
R/W-0h
R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-27. Register 0D Field Descriptions
Bit
Field
Type
Reset
Description
15-14
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Select output data format for ADC conversion result.
0 : Straight binary
1 : 2's compliment
13-13
12-8
DATA_FORMAT
TMP_REG_LD_2
R/W
R/W
1h
0h
Temporary register. Write 00000b for normal device
operation.
0 : Normal device operation.
Temporary register.
1 : Normal device operation.
7-7
6-0
TMP_REG_LD_1
RESERVED
R/W
R/W
0h
2h
Reserved. Do not change from default reset value.
7.6.2.5 Register 11h (offset = 11h) [reset = A02h]
图7-28. Register 11h
15
14
13
12
11
10
9
8
RESERVED
TMP_REG_L11 TMP_REG_L11 TMP_REG_L11 TMP_REG_L11
RESERVED
_5
_4
_3
_2
R/W-0h
6
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
0
7
5
4
3
2
1
RESERVED
R/W-0h
TMP_REG_L11_1
R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-29. Register 11 Field Descriptions
Bit
Field
Type
Reset
Description
15-13
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register.
0 : Normal device operation.
12-12
11-11
10-10
TMP_REG_L11_5
TMP_REG_L11_4
TMP_REG_L11_3
R/W
R/W
R/W
0h
1h
0h
Temporary register.
0 : Normal device operation.
Temporary register.
0 : Normal device operation.
Temporary register.
0 : Normal device operation.
9-9
8-3
TMP_REG_L11_2
RESERVED
R/W
R/W
1h
0h
Reserved. Do not change from default reset value.
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图7-29. Register 11 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Temporary register. Write 100b for normal device operation.
4 : Normal device operation.
2-0
TMP_REG_L11_1
R/W
2h
7.6.2.6 Register 12h (offset = 12h) [reset = Ah]
图7-30. Register 12h
15
14
13
12
11
10
2
9
1
8
RESERVED
R/W-0h
7
6
5
4
3
0
RESERVED
R/W-0h
XOR_EN
R/W-1h
DATA_WIDTH
R/W-1h
DATA_LANES
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-31. Register 12 Field Descriptions
Bit
Field
Type
Reset
Description
15-4
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Enables XOR function on ADC conversion result.
0 : XOR function is disabled
1 : Data output corresponding to ADC conversion result is
launched as {D[23:5] xor D[4], D[4]}
3-3
XOR_EN
R/W
1h
Select the output data frame width.
0 : 20-bit output frame. Use with 2-lane output mode
(DATA_LANES = 0). ADC A and ADC B data are output in
20-bit format on DOUTA and DOUTB respectively.
1 : 24-bit output frame. Use with 2-lane output mode
(DATA_LANES = 0). ADC A and ADC B data are output in
24-bit format on DOUTA and DOUTB respectively.
2 : 40-bit output frame. Use with 1-lane output mode
(DATA_LANES = 1). ADC A and ADC B data are output in
20-bit format.
2-1
DATA_WIDTH
R/W
1h
3 : 48-bit output frame. Use with 1-lane output mode
(DATA_LANES = 1). ADC A and ADC B data are output in
24-bit format.
Select number of LVDS output lanes
0 : 2-lane mode. ADC A data is output on DOUTA LVDS
pair and ADC B data is output on DOUTB LVDS pair.
1 : 1-lane mode. ADC A data followed by ADC B data are
output on DOUTA LVDS pair.
0-0
DATA_LANES
R/W
0h
7.6.2.7 Register 13h (offset = 13h) [reset = 0h]
图7-32. Register 13h
15
14
13
12
11
10
2
9
1
8
RESERVED
7
6
5
4
3
0
RAMP_INC_CH0
R/W-0h
TEST_PAT_MODE_CH0
TEST_PAT_EN
_CH0
RESERVED
R/W-0h
R/W-0h
R/W-0h
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LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-33. Register 13 Field Descriptions
Bit
Field
Type
Reset
Description
15-8
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Increment value for the ramp pattern output. The output
ramp will increment by N+1 where N is the value configured
in this register.
7-4
3-2
RAMP_INC_CH0
R/W
R/W
0h
0h
0 : Fixed pattern as configured in TEST_PAT0_CH0 register
1 : Fixed pattern as configured in TEST_PAT1_CH0 register
2 : Ramp output
3 : Alternate fixed pattern output as configured in
TEST_PAT0_CH0 and TEST_PAT1_CH0 registers
TEST_PAT_MOD
E_CH0
Enable digital test pattern for data for data corresponding to
channel 1, 2, 3, and 4.
TEST_PAT_EN_C
H0
0 : Normal operation. ADC data will be launched on the
data interface.
1 : Digital test pattern will be launched corresponding to
channels 1, 2, 3, and 4 on the data interface.
1-1
0-0
R/W
R/W
0h
0h
RESERVED
Reserved bit. Do not change from default reset value.
7.6.2.8 Register 14h (offset = 14h) [reset = 0h]
图7-34. Register 14h
15
14
13
12
11
10
2
9
1
8
0
TEST_PAT0_CH0[23:8]
R/W-0h
7
6
5
4
3
TEST_PAT0_CH0[23:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-35. Register 14 Field Descriptions
Bit
Field
Type
Reset
Description
TEST_PAT0_CH
0[23:8]
15-0
R/W
0h
Test pattern 0 for channel 0.
7.6.2.9 Register 15h (offset = 15h) [reset = 0h]
图7-36. Register 15h
15
14
13
12
11
10
2
9
1
8
0
TEST_PAT1_CH0[23:16]
R/W-0h
7
6
5
4
3
TEST_PAT0_CH0[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
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图7-37. Register 15 Field Descriptions
Bit
Field
Type
Reset
Description
TEST_PAT1_CH
0[23:16]
15-8
7-0
R/W
0h
Test pattern 1 for channel 0.
TEST_PAT0_CH
0[7:0]
R/W
0h
Test pattern 0 for channel 0.
7.6.2.10 Register 16h (offset = 16h) [reset = 0h]
图7-38. Register 16h
15
14
13
12
11
10
2
9
1
8
0
TEST_PAT1_CH0[15:0]
R/W-0h
7
6
5
4
3
TEST_PAT1_CH0[15:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-39. Register 16 Field Descriptions
Bit
Field
Type
Reset
Description
TEST_PAT1_CH
0[15:0]
15-0
R/W
0h
Test pattern 1 for channel 0.
7.6.2.11 Register 18h (offset = 18h) [reset = 0h]
图7-40. Register 18h
15
14
13
12
11
10
2
9
1
8
RESERVED
R/W-0h
7
6
5
4
3
0
RAMP_INC_CH1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
TEST_PAT_MODE_CH1
TEST_PAT_EN
_CH1
RESERVED
R/W-0h
R/W-0h
R/W-0h
图7-41. Register 18 Field Descriptions
Bit
Field
Type
Reset
Description
15-8
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Increment value for the ramp pattern output. The output
ramp will increment by N+1 where N is the value configured
in this register.
7-4
3-2
RAMP_INC_CH1
R/W
R/W
0h
0h
0 : Fixed pattern as configured in TEST_PAT0_CH1 register
1 : Fixed pattern as configured in TEST_PAT1_CH1 register
2 : Ramp output
3 : Alternate fixed pattern output as configured in
TEST_PAT0_CH1 and TEST_PAT1_CH1 registers
TEST_PAT_MOD
E_CH1
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Bit
图7-41. Register 18 Field Descriptions (continued)
Field
Type
R/W
R/W
Reset
Description
Enable digital test pattern for data corresponding to
channels 5, 6, 7, and 8.
0 : Normal operation. ADC data will be launched on the
data interface.
1 : Digital test pattern will be launched corresponding to
channels 5, 6, 7, and 8 on the data interface.
TEST_PAT_EN_C
H1
1-1
0-0
0h
RESERVED
0h
Reserved bit. Do not change from default reset value.
7.6.2.12 Register 19h (offset = 19h) [reset = 0h]
图7-42. Register 19h
15
14
13
12
11
10
2
9
1
8
0
TEST_PAT0_CH1[23:8]
R/W-0h
7
6
5
4
3
TEST_PAT0_CH1[23:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-43. Register 19 Field Descriptions
Bit
Field
Type
Reset
Description
TEST_PAT0_CH
1[23:8]
15-0
R/W
0h
Test pattern 0 for channel 1.
7.6.2.13 Register 1Ah (offset = 1Ah) [reset = 0h]
图7-44. Register 1Ah
15
14
13
12
11
10
2
9
1
8
0
TEST_PAT1_CH1[23:16]
R/W-0h
7
6
5
4
3
TEST_PAT0_CH1[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-45. Register 1A Field Descriptions
Bit
Field
Type
Reset
Description
TEST_PAT1_CH
1[23:16]
15-8
R/W
0h
Test pattern 1 for channel 1.
Test pattern 0 for channel 1.
TEST_PAT0_CH
1[7:0]
7-0
R/W
0h
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7.6.2.14 Register 1Bh (offset = 1Bh) [reset = 0h]
图7-46. Register 1Bh
15
7
14
6
13
5
12
11
10
2
9
1
8
0
TEST_PAT1_CH1[15:0]
R/W-0h
4
3
TEST_PAT1_CH1[15:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-47. Register 1B Field Descriptions
Bit
Field
Type
Reset
Description
TEST_PAT1_CH
1[15:0]
15-0
R/W
0h
Test pattern 1 for channel 1.
7.6.2.15 Register 33h (offset = 33h) [reset = 0h]
图7-48. Register 33h
15
14
13
12
11
10
9
8
0
RESERVED
TMP_REG_L33 TMP_REG_L33
RESERVED
_4
_3
R/W-0h
R/W-0h
R/W-0h
R/W-0h
2
7
6
5
4
3
1
RESERVED
TMP_REG_L33
_2
RESERVED
R/W-0h
TMP_REG_L33
_1
RESERVED
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-49. Register 33 Field Descriptions
Bit
Field
Type
Reset
Description
15-15
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register.
14-14
TMP_REG_L33_4
R/W
0h
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
1 : Use for 40-bit 1-lane, and 48-bit 1-lane modes.
Temporary register in the user address space.Write 1b to
this register for normal device operation.
0 : Not recommended
13-13
12-7
6-6
TMP_REG_L33_3
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
1 : Normal device operation
Reserved. Do not change from default reset value.
Temporary register in the user address space.Write 1b to
this register for normal device operation.
0 : Not recommended.
TMP_REG_L33_2
RESERVED
1 : Normal device operation.
5-4
Reserved. Do not change from default reset value.
Temporary register in the user address space.Write 1b to
this register for normal device operation.
0 : Not recommended.
3-3
TMP_REG_L33_1
RESERVED
1 : Normal device operation.
2-0
Reserved. Do not change from default reset value.
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7.6.2.16 Register 34h (offset = 34h) [reset = 0h]
图7-50. Register 34h
15
7
14
13
5
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
6
4
3
RESERVED
TMP_REG_L34
_3
RESERVED
R/W-0h
TMP_REG_L34 TMP_REG_L34
_2
_1
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-51. Register 34 Field Descriptions
Bit
Field
Type
Reset
Description
15-5
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register.
4-4
3-2
1-1
TMP_REG_L34_3
RESERVED
R/W
R/W
R/W
0h
0h
0h
0 : Not recommended.
1 : Recommended. Normal device operation.
Reserved. Do not change from default reset value.
Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
1 : Use for 48-bit 1-lane, and 40-bit 1-lane modes.
TMP_REG_L34_2
Temporary register.
0-0
TMP_REG_L34_1
R/W
0h
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
1 : Use for 40-bit 1-lane, and 48-bit 1-lane modes.
7.6.2.17 Register 50h (offset = 50h) [reset = 0h]
图7-52. Register 50h
15
14
13
12
11
10
9
8
RESERVED
R/W-0h
TMP_REG_L50_3
R/W-0h
TMP_REG_L50_2
R/W-0h
7
6
5
4
3
2
1
0
TMP_REG_L50_2
R/W-0h
TMP_REG_L50_1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-53. Register 50 Field Descriptions
Bit
Field
Type
Reset
Description
15-15
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register. Write 00000b for normal device
operation.
14-10
9-5
TMP_REG_L50_3
TMP_REG_L50_2
R/W
R/W
0h
0h
0 : Use for 20-bit 2-lane, 24-bit 2-lane, and 40-bit 1-lane
modes.
10 : Use for 48-bit 1-lane mode.
Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
6 : Use for 40-bit 1-lane mode, and 48-bit 1-lane modes.
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图7-53. Register 50 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Temporary register.
4-0
TMP_REG_L50_1
R/W
0h
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
4 : Use for 40-bit 1-lane mode, and 48-bit 1-lane modes.
7.6.2.18 Register 51h (offset = 51h) [reset = 0h]
图7-54. Register 51h
15
14
13
12
11
10
9
8
RESERVED
R/W-0h
TMP_REG_L51_3
R/W-0h
TMP_REG_L51_2
R/W-0h
7
6
5
4
3
2
1
0
TMP_REG_L51_2
R/W-0h
TMP_REG_L51_1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-55. Register 51 Field Descriptions
Bit
Field
Type
Reset
Description
15-15
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register.
14-10
9-5
TMP_REG_L51_3
TMP_REG_L51_2
TMP_REG_L51_1
R/W
R/W
R/W
0h
0h
0h
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
4 : Use for 40-bit 1-lane mode, and 48-bit 1-lane modes.
Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
4 : Use for 40-bit 1-lane mode, and 48-bit 1-lane modes.
Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
4 : Use for 40-bit 1-lane, and 48-bit 1-lane modes.
4-0
7.6.2.19 Register 52h (offset = 52h) [reset = 0h]
图7-56. Register 52h
15
14
13
12
11
10
9
8
RESERVED
R/W-0h
TMP_REG_L52_2
R/W-0h
7
6
5
4
3
2
1
0
TMP_REG_L52_2
R/W-0h
TMP_REG_L52_1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-57. Register 52 Field Descriptions
Bit
Field
Type
Reset
Description
15-10
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register. Write 00000b for normal device
operation.
9-5
TMP_REG_L52_2
R/W
0h
0 : Normal device operation.
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图7-57. Register 52 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Temporary register. Write 00000b for normal device
operation.
4-0
TMP_REG_L52_1
R/W
0h
0 : Normal device operation.
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7.6.2.20 Register C0h (offset = C0h) [reset = 0h]
图7-58. Register C0h
15
7
14
6
13
5
12
11
10
2
9
1
8
DCLK_CFG2
R/W-0h
DCLK_CFG4
R/W-0h
DCLK_CFG1
R/W-0h
RESERVED
R/W-0h
4
3
0
RESERVED
R/W-0h
PD_ADC
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-59. Register C0 Field Descriptions
Bit
Field
Type
Reset
Description
Data clock configuration 2.
1 : Normal device operation.
15-14
DCLK_CFG2
R/W
0h
Data clock configuration 4.
13-12
DCLK_CFG4
R/W
0h
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
1 : Use for 48-bit 1-lane, and 40-bit 1-lane modes.
Data clock configuration 1.
0 : Use for 40-bit 1-lane mode.
1 : Use for 24-bit 2-lane, 20-bit 2-lane, and 48-bit 1-lane
modes.
11-10
9-2
DCLK_CFG1
RESERVED
R/W
R/W
0h
0h
Reserved. Do not change from default reset value.
Power-down control for ADC channels
0 : Normal device operation.
1 : ADC A power down.
1-0
PD_ADC
R/W
0h
2 : ADC B power down.
3 : ADC A and ADC B power down.
7.6.2.21 Register C1h (offset = C1h) [reset = 0h]
图7-60. Register C1h
15
14
13
12
11
10
2
9
1
8
RESERVED
R/W-0h
PD_REF
R/W-0h
RESERVED
R/W-0h
DATA_RATE
R/W-0h
7
6
5
4
3
0
RESERVED
R/W-0h
RESERVED
R/W-0h
RESERVED
R/W-0h
RESERVED
R/W-0h
DCLK_CFG3
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-61. Register C1 Field Descriptions
Bit
Field
Type
Reset
Description
15-12
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
ADC reference selection
0 : Internal reference enabled
1 : Internal reference disabled. Connect external reference
at REFIO pin.
11-11
10-9
PD_REF
R/W
R/W
0h
0h
RESERVED
Reserved. Do not change from default reset value.
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图7-61. Register C1 Field Descriptions (continued)
Bit
8-8
7-4
3-0
Field
Type
R/W
R/W
R/W
Reset
Description
Select data rate for the data interface.
0 : Double Data Rate (DDR)
1 : Single Data Rate (SDR)
DATA_RATE
RESERVED
DCLK_CFG3
0h
0h
Reserved. Do not change from default reset value.
Data clock configuration 3.
8 : Use for 24-bit 2-lane, and 48-bit 1-lane modes.
9 : Use for 20-bit 2-lane, and 40-bit 1-lane modes.
0h
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7.6.3 Register Bank 2
图7-62. Register Bank 2 Map
ADD
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESERVED
TMP_RE
G_L1C_
1
RESERVED
1Ch
22h
33h
52h
53h
54h
56h
57h
60h
RESERVED
TMP_RE TMP_RE
G_L22_2 G_L22_1
RESERVED
RESERVED
TMP_RE
G_L33_1
RESERVED
RESERVED
TMP_RE TMP_RE
G_L52_2 G_L52_1
RESERVED
TMP_RE
G_L53_1
TMP_RE TMP_RE TMP_RE TMP_RE TMP_RE
G_L54_5 G_L54_4 G_L54_3 G_L54_2 G_L54_1
RESERVED
RESERV TMP_RE TMP_RE TMP_RE
RESERVED
ED
G_L56_3 G_L56_2 G_L56_1
RESERVED
TMP_RE
G_L57_1
RESERVED
TMP_RE
G_L60_1
RESERVED
7.6.3.1 Register 1Ch (offset = 1Ch) [reset = 0h]
图7-63. Register 1Ch
15
14
13
12
11
10
2
9
1
8
RESERVED
TMP_REG_L1C
_1
R/W-0h
4
R/W-0h
0
7
6
5
3
RESERVED
R/W-0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-64. Register 1C Field Descriptions
Bit
Field
Type
Reset
Description
15-9
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
TMP_REG_L1C_
1
8-8
7-0
R/W
R/W
0h
0h
RESERVED
Reserved. Do not change from default reset value.
7.6.3.2 Register 22h (offset = 22h) [reset = 0h]
图7-65. Register 22h
15
14
13
12
11
10
2
9
8
0
RESERVED
TMP_REG_L22 TMP_REG_L22
RESERVED
_2
_1
R/W-0h
6
R/W-0h
R/W-0h
R/W-0h
1
7
5
4
3
RESERVED
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图7-65. Register 22h (continued)
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-66. Register 22 Field Descriptions
Bit
Field
Type
Reset
Description
15-13
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register. Write 1b for normal device operation.
0 : Not recommended
12-12
TMP_REG_L22_2
R/W
0h
1 : Normal device operation
Temporary Register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
11-11
10-0
TMP_REG_L22_1
RESERVED
R/W
R/W
0h
0h
Reserved. Do not change from default reset value.
7.6.3.3 Register 33h (offset = 33h) [reset = 0h]
图7-67. Register 33h
15
14
13
12
11
10
9
1
8
0
RESERVED
TMP_REG_L33
_1
RESERVED
R/W-0h
R/W-0h
5
R/W-0h
2
7
6
4
3
RESERVED
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-68. Register 33 Field Descriptions
Bit
Field
Type
Reset
Description
15-11
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
10-10
9-0
TMP_REG_L33_1
RESERVED
R/W
R/W
0h
0h
Reserved. Do not change from default reset value.
7.6.3.4 Register 52h (offset = 52h) [reset = 0h]
图7-69. Register 52h
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
RESERVED
R/W-0h
TMP_REG_L52 TMP_REG_L52
_2
_1
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
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图7-70. Register 52 Field Descriptions
Bit
Field
Type
Reset
Description
15-2
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
1-1
TMP_REG_L52_2
R/W
R/W
0h
0h
Temporary register. Write 1b for normal device operation.
0 : Not recommended
0-0
TMP_REG_L52_1
1 : Normal device operation
7.6.3.5 Register 53h (offset = 53h) [reset = 0h]
图7-71. Register 53h
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
R/W-0h
R/W-0h
TMP_REG_L53
_1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-72. Register 53 Field Descriptions
Bit
Field
Type
Reset
Description
15-1
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register.
0-0
TMP_REG_L53_1
R/W
0h
0 : Normal device operation
1 : Not recommended
7.6.3.6 Register 54h (offset = 54h) [reset = 0h]
图7-73. Register 54h
15
14
13
12
11
10
2
9
8
0
TMP_REG_L54 TMP_REG_L54 TMP_REG_L54 TMP_REG_L54 TMP_REG_L54
RESERVED
_5
_4
_3
_2
_1
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
1
7
6
5
4
3
RESERVED
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-74. Register 54 Field Descriptions
Bit
Field
Type
Reset
Description
Temporary register.
15-15
TMP_REG_L54_5
R/W
0h
0 : Use for 24-bit 2-lane, and 48-bit 1-lane modes.
1 : Use for 40-bit 1-lane, and 20-bit 2-lane modes.
Temporary register. Write 0b for normal device operation.
0 : Normal device operation
14-14
TMP_REG_L54_4
R/W
0h
1 : Not recommended
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图7-74. Register 54 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Temporary register. Write 0b for normal device operation.
0 : Normal device operation
13-13
TMP_REG_L54_3
R/W
0h
1 : Not recommended
Temporary register.
12-12
TMP_REG_L54_2
R/W
0h
0 : Use for 24-bit 2-lane, and 48-bit 1-lane modes.
1 : Use for 40-bit 1-lane, and 20-bit 2-lane modes.
Temporary register.
11-11
10-0
TMP_REG_L54_1
RESERVED
R/W
R/W
0h
0h
0 : Use for 24-bit 2-lane, and 48-bit 1-lane modes.
1 : Use for 40-bit 1-lane, and 20-bit 2-lane modes.
Reserved. Do not change from default reset value.
7.6.3.7 Register 56h (offset = 56h) [reset = 0h]
图7-75. Register 56h
15
14
13
12
11
10
2
9
1
8
0
RESERVED
TMP_REG_L56 TMP_REG_L56 TMP_REG_L56
RESERVED
R/W-0h
_3
_2
_1
R/W-0h
7
R/W-0h
R/W-0h
R/W-0h
6
5
4
3
RESERVED
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-76. Register 56 Field Descriptions
Bit
Field
Type
Reset
Description
15-15
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
14-14
13-13
TMP_REG_L56_3
TMP_REG_L56_2
R/W
R/W
0h
0h
Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
12-12
11-0
TMP_REG_L56_1
RESERVED
R/W
R/W
0h
0h
Reserved. Do not change from default reset value.
7.6.3.8 Register 57h (offset = 57h) [reset = 0h]
图7-77. Register 57h
15
14
13
12
11
10
2
9
8
0
RESERVED
R/W-0h
TMP_REG_L57
_1
RESERVED
R/W-0h
3
R/W-0h
1
7
6
5
4
RESERVED
R/W-0h
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LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-78. Register 57 Field Descriptions
Bit
Field
Type
Reset
Description
15-12
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
11-11
10-0
TMP_REG_L57_1
RESERVED
R/W
R/W
0h
0h
Reserved. Do not change from default reset value.
7.6.3.9 Register 60h (offset = 60h) [reset = 0h]
图7-79. Register 60h
15
14
13
12
11
10
2
9
1
8
0
TMP_REG_L60
_1
RESERVED
R/W-0h
7
R/W-0h
3
6
5
4
RESERVED
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-80. Register 60 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
Temporary register. Write 1b for normal device operation.
0 : Not recommended
1 : Normal device operation
15-15
14-0
TMP_REG_L60_1
RESERVED
0h
0h
Reserved. Do not change from default reset value.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The integrated ADC driver, low-latency, high-speed, low AC and DC errors, and low temperature drift make the
ADS921x a high-performance solution for applications where precision measurements with low-latency are
required. The following section gives an example circuit and recommendations for using the ADS921x device
family in a data acquisition (DAQ) system.
8.2 Typical Applications
8.2.1 Data Acquisition (DAQ) Circuit for ≤20-kHz Input Signal Bandwidth
图 8-1 shows a 2-channel solution with minimum external components. This solution significantly reduces
solution size by driving the ADS921x with the 2-channel, fully differential amplifier (FDA) THS4552.
1 nF
270 pF
THS4552
Differential Source Single-ended Source
1 k
1 k
2.2
20
20
1 k
10
10
AINAP
AINAM
+
–
+
–
10 nF
ADC
VOCM
1 k
270 pF
2.2
2.2
1 nF
VOCM
ADS92XX
VCMOUT
1 nF
270 pF
Differential Source Single-ended Source
THS4552
1 k
20
20
1 k
10
10
AINBP
AINBM
+
–
+
–
10 nF
ADC
VOCM
1 k
1 k
1 nF
270 pF
2.2
图8-1. Data Acquisition (DAQ) Circuit for ≤20-kHz Input Signal Bandwidth
8.2.1.1 Design Requirements
表8-1 lists the parameters for this typical application.
表8-1. Design Parameters
PARAMETER
VALUE
≥92 dB
SNR
THD
≤–110 dB
≤20 kHz
Input signal frequency
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8.2.1.2 Detailed Design Procedure
The procedure discussed in this section can be used for any ADS921x application circuit.
• All ADS921x applications require the supply decoupling as given in the Power Supply Recommendations
section.
• The values given in this section must meet the maximum throughput and input signal frequency design
requirements given. A lower bandwidth solution can be used in cases where lower noise performance is
required.
8.2.1.3 Application Curves
图8-2 and 图8-3 show the SNR and INL performance for the circuit in 图8-1, respectively.
0
0.5
0.25
0
-44
-88
-132
-176
-220
-0.25
-0.5
0
8192 16384 24576 32768 40960 49152 57344 65535
Output Code
0
500
1000
1500
2000
2500
Frequency (kHz)
fIN = 2 kHz, INL = ±0.3 LSB
fIN = 2 kHz, SNR = 94.5 dB, THD = –120 dB
图8-3. Typical INL at 5 MSPS/Channel: ADS9217
图8-2. Typical FFT at 5 MSPS/Channel: ADS9217
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8.2.2 Data Acquisition (DAQ) Circuit for ≤100-kHz Input Signal Bandwidth
图 8-1 shows a 2-channel solution with minimum external components. This solution significantly reduces
solution size by driving the ADS921x with the 2-channel, fully differential amplifier (FDA) THS4552.
270 pF
47 pF
THS4552
Differential Source Single-ended Source
4.02 k
+
10
20
20
1 k
10
10
AINAP
AINAM
+
–
470 pF
ADC
VOCM
–
1 k
4.02 k
47 pF
47 pF
10
10
270 pF
VOCM
ADS92XX
VCMOUT
270 pF
THS4552
Differential Source Single-ended Source
4.02 k
20
20
1 k
10
10
AINBP
AINBM
+
–
+
470 pF
47 pF
ADC
VOCM
–
1 k
4.02 k
10
270 pF
图8-4. Data Acquisition (DAQ) Circuit for ≤100-kHz Input Signal Bandwidth
8.2.2.1 Design Requirements
表8-2 lists the parameters for this typical application.
表8-2. Design Parameters
PARAMETER
VALUE
≥91 dB
SNR
THD
≤–110 dB
≤100 kHz
Input signal frequency
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8.2.2.2 Application Curves
图8-5 and 图8-6 show the FFT plots for the circuit in 图8-4.
0
0
-44
-44
-88
-88
-132
-176
-220
-132
-176
-220
0
1000
2000
3000
4000
5000
0
500
1000
1500
2000
2500
Frequency (kHz)
Frequency (kHz)
fIN = 100 kHz, SNR = 92 dB, THD = –117 dB
fIN = 100 kHz, SNR = 92 dB, THD = –117 dB
图8-5. Typical FFT at 10 MSPS/Channel: ADS9218
图8-6. Typical FFT at 5 MSPS/Channel: ADS9217
8.2.3 Data Acquisition (DAQ) Circuit for ≤1-MHz Input Signal Bandwidth
图 8-1 shows a 2-channel solution with minimum external components. This solution significantly reduces
solution size by driving the ADS9218 with the THS4541, which enables low-distortion performance with low
power over wide signal bandwidth.
THS4541
50
1 k
22 pF
47 pF
Differential Source Single-ended Source
50
22 pF
10
10
20
200
10
AINAP
AINAM
+
–
+
–
270 pF
ADC
VOCM
20
10
200
50
1 k
47 pF
22 pF
50
22 pF
VOCM
ADS92XX
VCMOUT
THS4541
50
50
22 pF
47 pF
20
Differential Source Single-ended Source
22 pF
1 k
10
200
AINBP
AINBM
10
+
–
+
–
270 pF
ADC
VOCM
20
10
200
50
1 k
50
47 pF
22 pF
10
22 pF
图8-7. Data Acquisition (DAQ) Circuit for ≤1-MHz Input Signal Bandwidth
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8.2.3.1 Design Requirements
表8-3 lists the parameters for this typical application.
表8-3. Design Parameters
PARAMETER
SNR
VALUE
≥80 dB
THD
≤–100 dB
≤1 MHz
Input signal frequency
8.2.3.2 Application Curves
图8-8 and 图8-9 show the FFT plots for the circuit in 图8-7.
0
0
-40
-40
-80
-80
-120
-160
-200
-120
-160
-200
0
1000
2000
3000
4000
5000
0
500
1000
1500
2000
2500
Frequency (kHz)
Frequency (kHz)
fIN = 1 MHz, SNR = 90.6 dB, THD = –104 dB
fIN = 1 MHz, SNR = 90.5 dB, THD = –104.2 dB
图8-8. Typical FFT at 10 MSPS/Channel: ADS9218 图8-9. Typical FFT at 5 MSPS/Channel: ADS9217
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8.3 Power Supply Recommendations
The ADS921x has three independent power supplies, AVDD_5V, AVDD_1V8, and DVDD_1V8. The AVDD_5V
supply provides power to the ADC driver. The AVDD_1V8 provides power to the analog circuits. The DVDD_1V8
supply provides power to the digital interface. The AVDD_5, AVDD_1V8, and DVDD_1V8 supplies can be set
independently to voltages within the permissible range. 图8-10 shows how to decouple the power supplies.
1.8V
0.1 μF 1 μF
5V
AVDD_5V
(pin 1)
1 μF 0.1 μF
GND
(pin 2)
ADS92xx
AVDD_5V
(pin 10)
1 μF 0.1 μF
GND
(pin 9)
1.8V
0.1 μF 1 μF
图8-10. Power-Supply Decoupling
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8.4 Layout
8.4.1 Layout Guidelines
图 8-11 shows a board layout example for the ADS921x. Avoid crossing digital lines with the analog signal path
and keep the analog input signals and the reference signals away from noise sources. Use 0.1-μF ceramic
bypass capacitors in close proximity to the analog (AVDD_5V and AVDD_1V8), and digital (DVDD_1V8) power-
supply pins. Avoid placing vias between the power-supply pins and the bypass capacitors. Place the reference
decoupling capacitor close to the device REFIO and REFM pins. Avoid placing vias between the REFIO pin and
the bypass capacitors. Connect the GND and REFM pins to a ground plane using short, low-impedance paths.
8.4.2 Layout Example
图8-11. Example Layout
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9 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, REF70 2 ppm/°C Maximum Drift, 0.23 ppmp-p 1/f Noise, Precision Voltage Reference data
sheet
• Texas Instruments, THS4552 Dual-Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier data
sheet
• Texas Instruments, THS4541 Negative Rail Input, Rail-to-Rail Output, Precision, 850-MHz Fully Differential
Amplifier data sheet
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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10.1 Mechanical Data
PACKAGE OUTLINE
RHA0040C
VQFN - 1 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
0.5
0.3
PIN 1 INDEX AREA
6.1
5.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
4.7 0.1
2X 4.5
(0.2) TYP
11
20
36X 0.5
10
21
EXPOSED
THERMAL PAD
2X
41
SYMM
4.5
SEE TERMINAL
DETAIL
1
30
0.3
0.2
40X
40
31
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A B
SYMM
0.5
0.3
40X
4219053/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHA0040C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.7)
SYMM
40
31
40X (0.6)
1
30
40X (0.25)
4X
(1.35)
(
0.2) TYP
VIA
(0.75)
TYP
41
(5.8)
SYMM
4X
(1.5)
36X (0.5)
10
21
(R0.05)
TYP
11
(0.75) TYP
20
4X (1.5)
(5.8)
4X (1.35)
LAND PATTERN EXAMPLE
SCALE:12X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219053/A 09/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHA0040C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.5) TYP
9X ( 1.3)
(R0.05) TYP
40
31
40X (0.6)
1
30
40X (0.25)
41
(1.5)
TYP
SYMM
(5.8)
36X (0.5)
10
21
METAL
TYP
11
20
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
69% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
4219053/A 09/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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2-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PADS9218RHAT
ACTIVE
VQFN
RHA
40
250
TBD
Call TI
Call TI
-40 to 125
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
RHA 40
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
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