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ADS8318IBDRCT [TI]

16-BIT, 500-KSPS, SERIAL INTERFACE MICROPOWER, MINIATURE, SAR ANALOG-TO-DIGITAL CONVERTER; 16 - BIT ， 500 KSPS ，串行接口，微功耗，微型SAR模拟数字转换器
ADS8318IBDRCT
型号： ADS8318IBDRCT
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

16-BIT, 500-KSPS, SERIAL INTERFACE MICROPOWER, MINIATURE, SAR ANALOG-TO-DIGITAL CONVERTER
16 - BIT ， 500 KSPS ，串行接口，微功耗，微型SAR模拟数字转换器

转换器
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ADS8318  
www.ti.com ........................................................................................................................................................................................................ SLAS568–MAY 2008  
16-BIT, 500-KSPS, SERIAL INTERFACE MICROPOWER, MINIATURE,  
SAR ANALOG-TO-DIGITAL CONVERTER  
1
FEATURES  
DESCRIPTION  
•
•
•
•
•
500-kHz Sample Rate  
The ADS8318 is a 16-bit, 500-KSPS analog-to-digital  
converter. It operates with a 2.048-V to 5.5-V external  
reference. The device includes a capacitor based,  
SAR A/D converter with inherent sample and hold.  
16-Bit Resolution  
Zero Latency at Full Speed  
Unipolar, Differential Input, Range: –Vref to Vref  
The devices includes a 50-MHz SPI compatible serial  
interface. The interface is designed to support daisy  
chaining or cascading of multiple devices. Also a  
Busy Indicator makes it easy to synchronize with the  
digital host.  
SPI Compatible Serial Interface with Daisy  
Chain Option  
•
Excellent Performance:  
–
–
–
–
95.2dB SNR Typ at 10-kHz I/P  
–108dB THD Typ at 10-kHz I/P  
±1.0 LSB Max INL  
The ADS8318 unipolar differential input range  
supports a differential input swing of –Vref to +Vref with  
a common-mode of +Vref/2.  
±0.75 LSB Max DNL  
Device operation is optimized for very low power  
operation, and the power consumption directly scales  
with speed. This feature makes it attractive for lower  
speed applications.  
•
•
•
•
Low Power Dissipation: 18 mW Typ at 500  
KSPS  
Power Scales Linearly with Speed: 3.6 mW/100  
KSPS  
It is available in 10-pin MSOP and SON packages.  
Power Dissipation During Power-Down State:  
0.25 µW Typ  
+VBD  
+VA  
10-Pin MSOP and SON Packages  
O/P  
Drive  
SAR  
SDO  
APPLICATIONS  
•
•
•
•
•
Battery Powered Equipments  
Data Acquisition Systems  
Instrumentation and Process Control  
Medical Electronics  
IN+  
IN-  
I/P  
Shift  
Reg  
SDI  
CDAC  
COMP  
REFIN  
Conversion and I/O  
Control Logic  
SCLK  
Optical Networking  
ADS8318  
CONVST  
GND  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008, Texas Instruments Incorporated  
ADS8318  
SLAS568–MAY 2008........................................................................................................................................................................................................ www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION(1)  
MAXIMUM  
INTEGRAL  
LINEARITY  
(LSB)  
MAXIMUM  
DIFFERENTIAL  
LINEARITY  
(LSB)  
NO MISSING  
CODES AT  
RESOLUTION  
(BIT)  
TRANSPORT  
MEDIA  
QUANTITY  
PACKAGE  
TYPE  
PACKAGE  
DESIGNATOR  
TEMPERATURE  
RANGE  
PACKAGE  
MARKING  
ORDERING  
INFORMATION  
DEVICE  
ADS8318IDGST  
ADS8318IDGSR  
ADS8318IDRCT  
ADS8318IDRCR  
ADS8318IBDGST  
ADS8318IBDGSR  
ADS8318IBDRCT  
ADS8318IBDRCR  
250  
2500  
250  
10 Pin MSOP  
10 Pin SON  
10 Pin MSOP  
10 Pin SON  
DGS  
DRC  
DGS  
DRC  
CBC  
CBE  
CBC  
CBE  
ADS8318I  
±1.5  
±1.0  
±1  
16  
16  
–40°C to 85°C  
–40°C to 85°C  
2500  
250  
2500  
250  
ADS8318IB  
±0.75  
2500  
(1) For the most current specifications and ordering information, see the Package Option Addendum at the end of this document, or see the  
TI website at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range unless otherwise noted(1)  
VALUE  
–0.3 to +VA + 0.3  
±130  
UNIT  
V
+IN  
–IN  
mA  
V
–0.3 to +VA + 0.3  
±130  
mA  
V
+VA to AGND  
–0.3 to 7  
+VBD to BDGND  
–0.3 to 7  
V
Digital input voltage to GND  
Digital output to GND  
–0.3 to +VBD + 0.3  
–0.3 to +VBD + 0.3  
–40 to 85  
V
V
TA  
Operating free-air temperature range  
Storage temperature range  
Junction temperature (TJ max)  
°C  
°C  
°C  
°C  
°C/W  
Tstg  
–65 to 150  
150  
Power dissipation  
(TJMax – TA)/θJA  
180  
MSOP package  
θJA thermal impedance  
ADS8318 is rated to MSL2 260°C per the  
JSTD-020 specification  
Maximum MSOP reflow temperature  
SON package  
Power dissipation  
(TJMax – TA)/θJA  
θJA thermal impedance  
70  
°C/W  
ADS8318 is rated to MSL2 260°C per the  
JSTD-020 specification  
Maximum SON reflow temperature  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
2
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): ADS8318  
ADS8318  
www.ti.com ........................................................................................................................................................................................................ SLAS568–MAY 2008  
SPECIFICATIONS  
TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, Vref = 4 V, fSAMPLE = 500 kHz (unless otherwise noted)  
PARAMETER  
ANALOG INPUT  
Full-scale input span  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
(1)  
+IN – (–IN)  
+IN  
–Vref  
– 0.1  
– 0.1  
0
Vref  
Vref + 0.1  
Vref + 0.1  
Vref/2+0.1  
V
Operating input range  
–IN  
Input common-mode range  
Input capacitance  
Vref/2  
59  
V
+IN and -IN terminal to GND  
During acquisition  
pF  
pA  
Input leakage current  
1000  
SYSTEM PERFORMANCE  
Resolution  
16  
Bits  
Bits  
No missing codes  
16  
–1.5  
–1  
ADS8318I  
ADS8318IB  
ADS8318I  
ADS8318IB  
±0.65  
±0.65  
±0.4  
1.5  
1
INL  
Integral linearity(2)  
LSB(3)  
LSB(3)  
–1  
1
DNL  
Differential linearity  
At 16-bit level  
–0.75  
–1.5  
–0.03  
±0.4  
0.75  
1.5  
0.03  
EO  
EG  
Offset error(4)  
Gain error  
±0.3  
mV  
±0.003  
%FSR  
With common mode input signal = 200 mVp-p at 500  
kHz  
CMRR Common-mode rejection ratio  
78  
dB  
PSRR Power supply rejection ratio  
Transition noise  
At FFF0h output code  
80  
dB  
0.25  
LSB  
SAMPLING DYNAMICS  
+VBD = 5 V  
+VBD = 3 V  
+VBD = 5 V  
+VBD = 3 V  
1400  
1400  
tCONV  
Conversion time  
Acquisition time  
ns  
600  
600  
ns  
Maximum throughput rate with or  
without latency  
0.5  
MHz  
Aperture delay  
2.5  
6
ns  
ps  
ns  
ns  
Aperture jitter, RMS  
Step response  
600  
600  
Settling to 16-bit accuracy  
Overvoltage recovery  
(1) Ideal input span, does not include gain or offset error.  
(2) This is endpoint INL, not best fit.  
(3) LSB means least significant bit  
(4) Measured relative to actual measured reference.  
Copyright © 2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): ADS8318  
ADS8318  
SLAS568–MAY 2008........................................................................................................................................................................................................ www.ti.com  
SPECIFICATIONS (continued)  
TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, Vref = 4 V, fSAMPLE = 500 kHz (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
DYNAMIC CHARACTERISTICS  
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V  
VIN 0.4 dB below FS at 10 kHz, Vref = 5 V  
VIN 0.4 dB below FS at 100 kHz, Vref = 5 V  
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V  
VIN 0.4 dB below FS at 10 kHz, Vref = 5 V  
VIN 0.4 dB below FS at 100 kHz, Vref = 5 V  
–114  
–108  
–91.5  
96  
(5)  
THD  
Total harmonic distortion  
Signal-to-noise ratio  
dB  
95.2  
92.5  
SNR  
dB  
dB  
ADS8318IB VIN 0.4 dB below FS at 1 kHz, Vref = 5 V  
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V  
95.5  
96  
95  
SINAD Signal-to-noise + distortion  
VIN 0.4 dB below FS at 10 kHz, Vref = 5 V  
VIN 0.4 dB below FS at 100 kHz, Vref = 5 V  
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V  
VIN 0.4 dB below FS at 10 kHz, Vref = 5 V  
VIN 0.4 dB below FS at 100 kHz, Vref = 5 V  
89.5  
116  
109  
92  
SFDR  
Spurious free dynamic range  
–3dB Small signal bandwidth  
dB  
15  
MHz  
EXTERNAL REFERENCE INPUT  
Vref  
Input range  
2.048  
4.096  
250  
VDD+0.1  
V
(6)  
Reference input current  
During conversion  
µA  
POWER SUPPLY REQUIREMENTS  
+VBD  
2.375  
4.5  
3.3  
5
5.5  
5.5  
V
V
Power supply  
voltage  
+VA  
Supply current  
+VA  
500-kHz Sample rate  
+VA = 5 V, 500-kHz Sample rate  
+VA = 5 V  
3.6  
18  
50  
4.5  
mA  
mW  
nA  
PVA  
Power dissipation  
Device power-down current(7)  
22.5  
300  
IVApd  
LOGIC FAMILY CMOS  
VIH  
IIH = 5 µA  
+(0.7×VBD)  
–0.3  
+VBD+0.3  
+(0.3×VBD)  
+VBD  
V
V
V
V
VIL  
IIL = 5 µA  
Logic level  
VOH  
IOH = 2 TTL loads  
IOL = 2 TTL loads  
+VBD–0.3  
0
VOL  
0.4  
TEMPERATURE RANGE  
TA  
Operating free-air temperature  
–40  
85  
°C  
(5) Calculated on the first nine harmonics of the input frequency  
(6) Can vary ±20%  
(7) Device automatically enters power-down state at the end of every conversion, and continues to be in power-down state as long as it is  
in acquistion phase.  
4
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): ADS8318  
ADS8318  
www.ti.com ........................................................................................................................................................................................................ SLAS568–MAY 2008  
TIMING REQUIREMENTS  
All specifications typical at –40°C to 85°C, +VA = 5 V, +VBD ≥ 4.5 V  
PARAMETER  
REF FIGURE  
MIN  
TYP  
MAX UNIT  
SAMPLING AND CONVERSION RELATED  
tacq  
tcnv  
tcyc  
t1  
Acquisition time  
600  
ns  
Figure 46, Figure 48, Figure 50,  
Figure 52  
Conversion time  
1400  
ns  
ns  
ns  
ns  
Time between conversions  
Pulse duration, CONVST high  
Pulse duration, CONVST low  
2000  
10  
Figure 46, Figure 48  
t6  
Figure 50, Figure 52, Figure 54  
20  
I/O RELATED  
tclk  
tclkl  
tclkh  
t2  
SCLK Period  
20  
9
ns  
ns  
ns  
ns  
ns  
ns  
SCLK Low time  
Figure 46, Figure 48, Figure 50,  
Figure 52, Figure 54, Figure 56  
SCLK High time  
9
SCLK Falling edge to data remains valid  
SCLK Falling edge to next data valid delay  
Enable time, CONVST or SDI Low to MSB valid  
5
t3  
16  
15  
ten  
Figure 46, Figure 50  
Disable time, CONVST or SDI high or last SCLK falling edge Figure 46, Figure 48, Figure 50,  
tdis  
12  
ns  
to SDO 3-state (CS mode)  
Figure 52  
t4  
t5  
t7  
t8  
Setup time, SDI valid to CONVST rising edge  
Hold time, SDI valid from CONVST rising edge  
Setup time, SCLK valid to CONVST rising edge  
Hold time, SCLK valid from CONVST rising edge  
5
5
5
5
ns  
ns  
ns  
ns  
Figure 50, Figure 52  
Figure 54  
Copyright © 2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s): ADS8318  
ADS8318  
SLAS568–MAY 2008........................................................................................................................................................................................................ www.ti.com  
TIMING REQUIREMENTS  
All specifications typical at –40°C to 85°C, +VA = 5 V, +4.5 V > +VBD ≥ 2.375 V  
PARAMETER  
REF FIGURE  
MIN  
TYP  
MAX UNIT  
SAMPLING AND CONVERSION RELATED  
tacq  
tcnv  
tcyc  
t1  
Acquisition time  
600  
ns  
Figure 46, Figure 48, Figure 50,  
Figure 52  
Conversion time  
1400  
ns  
ns  
ns  
ns  
Time between conversions  
Pulse width CONVST high  
Pulse width CONVST low  
2000  
10  
Figure 46, Figure 48  
t6  
Figure 50, Figure 52, Figure 54  
20  
I/O RELATED  
tclk  
tclkl  
tclkh  
t2  
SCLK period  
30  
13  
13  
5
ns  
ns  
ns  
ns  
ns  
ns  
SCLK low time  
Figure 46, Figure 48, Figure 50,  
Figure 52, Figure 54, Figure 56  
SCLK high time  
SCLK falling edge to data remains valid  
SCLK falling edge to next data valid delay  
CONVST or SDI low to MSB valid  
t3  
24  
22  
ten  
Figure 46, Figure 50  
CONVST or SDI high or last SCLK falling edge to SDO  
3-state (CS mode)  
Figure 46, Figure 48, Figure 50,  
Figure 52  
tdis  
15  
ns  
t4  
t5  
t7  
t8  
SDI valid setup time to CONVST rising edge  
SDI valid hold time from CONVST rising edge  
SCLK valid setup time to CONVST rising edge  
SCLK valid hold time from CONVST rising edge  
5
5
5
5
ns  
ns  
ns  
ns  
Figure 50, Figure 52  
Figure 54  
500µA  
Iol  
From  
SDO  
1.4V  
20pF  
500µA  
Ioh  
Figure 1. Load Circuit for Digital Interface Timing  
0.7 VBD  
0.3 VBD  
tDELAY  
tDELAY  
2V  
0.8V  
2V  
0.8V  
Figure 2. Voltage Levels for Timing  
6
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): ADS8318  
ADS8318  
www.ti.com ........................................................................................................................................................................................................ SLAS568–MAY 2008  
PIN ASSIGNMENTS  
MSOP PACKAGE  
SON PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
2
3
4
5
10  
9
REFIN  
+VA  
IN+  
+VBD  
SDI  
1
2
3
4
5
10  
9
REFIN  
+VA  
IN+  
+VBD  
SDI  
SCLK  
SDO  
8
SCLK  
SDO  
8
7
IN-  
7
IN-  
CONVST  
6
GND  
CONVST  
6
GND  
Terminal Functions  
TERMINAL  
NO. NAME  
ANALOG PINS  
I/O  
DESCRIPTION  
1
REFIN  
I
Reference (positive) input. Decouple with GND pin using 0.1-µF bypass capacitor and 10-µF storage  
capacitor.  
3
4
+IN  
–IN  
I
I
Noninverting analog signal input  
Inverting analog signal input  
I/O PINS  
Convert input. It also functions as the CS input in 3-wire interface mode. Refer to Description and Timing  
Diagrams sections for more details.  
6
CONVST  
I
7
8
9
SDO  
SCLK  
SDI  
O
I
Serial data output.  
Serial I/O clock input. Data (on SDO o/p) is synchronized with this clock.  
I
Serial data input. The SDI level at the start of a conversion selects the mode of operation such as CS or daisy  
chain mode. It also serves as the CS input in 4-wire interface mode. Refer to Description and Timing  
Diagrmas sections for more details.  
POWER SUPPLY PINS  
2
5
+VA  
–
–
Analog power supply. Decoupled with GND pin.  
GND  
Device ground. Note this is a common ground pin for both analog power supply (+VA) and digital I/O supply  
(+VBD).  
10  
+VBD  
–
Digital I/O power supply. Decouple with GND pin.  
TYPICAL CHARACTERISTICS  
OFFSET ERROR  
vs  
SUPPLY VOLTAGE  
GAIN ERROR  
vs  
SUPPLY VOLTAGE  
OFFSET ERROR  
vs  
REFERENCE VOLTAGE  
-0.001  
-0.002  
-0.003  
0.35  
0.3  
0.4  
+VBD = 2.7 V,  
0.38  
0.36  
0.34  
0.32  
0.3  
Vref = 4.096 V,  
fs = 500 KSPS,  
TA = 30°C  
0.25  
-0.004  
-0.005  
0.2  
-0.006  
0.15  
0.28  
0.26  
-0.007  
-0.008  
+VA = 5 V  
+VBD = 2.7 V,  
fs = 500 KSPS,  
0.1  
0.05  
0
+VBD = 2.7 V,  
Vref = 4.096 V,  
fs = 500 KSPS,  
TA = 30°C  
0.24  
0.22  
0.2  
TA = 30°C  
-0.009  
-0.01  
4.5  
4.75  
5
5.25  
5.5  
4.5  
4.75  
5
5.25  
5.5  
2
2.5  
3
3.5  
4
4.5  
5
+VA - Supply Voltage - V  
Vref - Reference Voltage - V  
+VA - Supply Voltage - V  
Figure 3.  
Figure 4.  
Figure 5.  
Copyright © 2008, Texas Instruments Incorporated  
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7
Product Folder Link(s): ADS8318  
ADS8318  
SLAS568–MAY 2008........................................................................................................................................................................................................ www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
GAIN ERROR  
vs  
REFERENCE VOLTAGE  
OFFSET ERROR  
vs  
FREE-AIR TEMPERATURE  
GAIN ERROR  
vs  
FREE-AIR TEMPERATURE  
-0.001  
1
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.002  
0
+VA = 5 V  
+VBD = 2.7 V,  
Vref = 5 V,  
+VA = 5 V  
+VBD = 2.7 V,  
Vref = 5 V,  
-0.002  
-0.003  
fs = 500 KSPS  
fs = 500 KSPS  
-0.002  
-0.004  
-0.005  
-0.006  
-0.004  
-0.006  
-0.007  
-0.008  
+VA = 5 V  
+VBD = 2.7 V,  
fs = 500 KSPS,  
-0.008  
-0.01  
-0.009  
-0.01  
TA = 30°C  
0.1  
0
-40 -25 -10  
5
20 35  
50 65 80  
2
2.5  
3
3.5  
4
4.5  
5
-40 -25 -10  
5
20  
35 50 65  
80  
TA - Free-Air Temperature - °C  
TA - Free-Air Temperature - °C  
Vref - Reference Voltage - V  
Figure 6.  
Figure 7.  
Figure 8.  
DIFFERENTIAL NONLINEARITY  
vs  
GAIN ERROR DRIFT HISTOGRAM  
OFFSET ERROR DRIFT HISTOGRAM  
SUPPLY VOLTAGE  
20  
1
16  
14  
12  
10  
8
19  
15  
+VBD = 2.7 V,  
Vref = 4.096 V,  
+VA = 5 V  
+VBD = 2.7 V,  
Vref = 5 V,  
+VA = 5 V  
+VBD = 2.7 V,  
Vref = 5 V,  
18  
16  
14  
12  
10  
8
0.8  
0.6  
0.4  
17  
fs = 500 KSPS,  
DNLMAX  
TA = 30°C  
fs = 500 KSPS  
fs = 500 KSPS,  
TA = 30°C  
0.2  
0
9
8
8
-0.2  
-0.4  
-0.6  
-0.8  
6
DNLMIN  
6
4
4
2
0
2
2
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
-1  
4.5  
-0.5 -0.4 -0.3-0.2-0.1  
0 0.1 0.2 0.3 0.4 0.5  
-0.5-0.4-0.3-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6  
4.75  
5
5.25  
5.5  
ppm/°C  
ppm/°C  
+VA - Supply Voltage - V  
Figure 9.  
Figure 10.  
Figure 11.  
INTEGRAL NONLINEARITY  
vs  
DIFFERENTIAL NONLINEARITY  
vs  
INTEGRAL NONLINEARITY  
vs  
SUPPLY VOLTAGE  
REFERENCE VOLTAGE  
REFERENCE VOLTAGE  
1
1
1
0.8  
0.6  
0.4  
0.2  
0
0.8  
0.8  
0.6  
0.6  
0.4  
0.2  
0
INLMAX  
DNLMAX  
INLMAX  
0.4  
0.2  
0
+VA = 5 V  
+VBD = 2.7 V,  
fs = 500 KSPS,  
+VBD = 2.7 V,  
Vref = 4.096 V,  
+VA = 5 V  
+VBD = 2.7 V,  
fs = 500 KSPS,  
fs = 500 KSPS,  
TA = 30°C  
TA = 30°C  
DNLMIN  
-0.2  
-0.2  
TA = 30°C  
-0.2  
-0.4  
-0.6  
-0.4  
-0.4  
-0.6  
-0.8  
-1  
INLMIN  
-0.6  
-0.8  
-1  
INLMIN  
-0.8  
2
2
2.5  
3
3.5  
4
4.5  
5
2.5  
3
3.5  
4
4.5  
5
4.5  
4.75  
5
5.25  
5.5  
Vref - Reference Voltage - V  
Vref - Reference Voltage - V  
+VA - Supply Voltage - V  
Figure 12.  
Figure 13.  
Figure 14.  
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TYPICAL CHARACTERISTICS (continued)  
DIFFERENTIAL NONLINEARITY  
vs  
FREE-AIR TEMPERATURE  
INTEGRAL NONLINEARITY  
vs  
FREE-AIR TEMPERATURE  
EFFECTIVE NUMBER OF BITS  
vs  
SUPPLY VOLTAGE  
16  
+VBD = 2.7 V,  
15.9 Vref = 4.096 V,  
1
0.8  
0.6  
0.4  
0.2  
0
1
0.8  
0.6  
+VA = 5 V  
+VBD = 2.7 V,  
Vref = 5 V,  
fs = 500 KSPS,  
15.8  
fi = 1.9 kHz  
INLMAX  
DNLMAX  
fs = 500 KSPS  
15.7  
TA = 30°C  
0.4  
0.2  
15.6  
15.5  
+VA = 5 V  
+VBD = 2.7 V,  
Vref = 5 V,  
0
-0.2  
-0.4  
fs = 500 KSPS  
15.4  
15.3  
15.2  
15.1  
15  
-0.2  
-0.4  
-0.6  
-0.8  
-1  
DNLMIN  
INLMIN  
-0.6  
-0.8  
-1  
4.5  
4.75 5.25  
+VA - Supply Voltage - V  
5
5.5  
-40 -25 -10  
5
20 35 50 65 80  
-40 -25 -10  
5
20 35 50  
65 80  
TA - Free-Air Temperature - °C  
TA - Free-Air Temperature - °C  
Figure 15.  
Figure 16.  
Figure 17.  
EFFECTIVE NUMBER OF BITS  
vs  
EFFECTIVE NUMBER OF BITS  
vs  
FREE-AIR TEMPERATURE  
SPURIOUS FREE DYNAMIC RANGE  
vs  
REFERENCE VOLTAGE  
SUPPLY VOLTAGE  
16  
122  
16  
15.9  
15.8  
15.7  
+VA = 5 V,  
+VBD = 2.7 V,  
Vref = 5 V,  
+VA = 5 V  
+VBD = 2.7 V,  
fs = 500 KSPS,  
15.9  
15.8  
15.7  
121  
120  
119  
118  
117  
116  
115  
114  
fs = 500 KSPS,  
fi = 1.9 kHz  
fi = 1.9 kHz,  
TA = 30°C  
15.6  
15.5  
15.6  
15.5  
15.4  
15.3  
15.2  
15.1  
15  
15.4  
+VBD = 2.7 V,  
Vref = 4.096 V,  
15.3  
15.2  
15.1  
15  
fs = 500 KSPS,  
fi = 1.9 kHz  
TA = 30°C  
-40 -25 -10  
5
20 35 50 65 80  
4.5  
4.75  
5
+VA - Supply Voltage - V  
5.25  
5.5  
2
2.5  
3
3.5  
4
4.5  
5
Vref - Reference Voltage - V  
TA - Free-Air Temperature - °C  
Figure 18.  
Figure 19.  
Figure 20.  
SIGNAL-TO-NOISE + DISTORTION  
SIGNAL-TO-NOISE RATIO  
vs  
TOTAL HARMONIC DISTORTION  
vs  
vs  
SUPPLY VOLTAGE  
SUPPLY VOLTAGE  
SUPPLY VOLTAGE  
122  
121  
96.4  
96.4  
96.2  
96  
96.2  
96  
120  
119  
118  
117  
116  
115  
114  
95.8  
95.8  
95.6  
95.4  
95.6  
95.4  
+VBD = 2.7 V,  
Vref = 4.096 V,  
+VBD = 2.7 V,  
+VBD = 2.7 V,  
Vref = 4.096 V,  
Vref = 4.096 V,  
fs = 500 KSPS,  
fi = 1.9 kHz  
fs = 500 KSPS,  
fi = 1.9 kHz  
TA = 30°C  
fs = 500 KSPS,  
fi = 1.9 kHz  
TA = 30°C  
95.2  
95  
95.2  
95  
TA = 30°C  
4.5  
4.75  
+VA - Supply Voltage - V  
5
5.25  
5.5  
4.5  
4.75  
+VA - Supply Voltage - V  
5
5.25  
5.5  
4.5  
4.75  
5
5.25  
+VA - Supply Voltage - V  
5.5  
Figure 21.  
Figure 22.  
Figure 23.  
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TYPICAL CHARACTERISTICS (continued)  
SPURIOUS FREE DYNAMIC RANGE  
SIGNAL-TO-NOISE + DISTORTION  
SIGNAL-TO-NOISE RATIO  
vs  
REFERENCE VOLTAGE  
vs  
vs  
REFERENCE VOLTAGE  
REFERENCE VOLTAGE  
124  
96.5  
96  
96.5  
96  
123  
122  
121  
120  
119  
118  
117  
116  
95.5  
95  
95.5  
95  
+VA = 5 V  
+VBD = 2.7 V,  
fs = 500 KSPS,  
+VA = 5 V  
+VBD = 2.7 V,  
fs = 500 KSPS,  
+VA = 5 V  
+VBD = 2.7 V,  
fs = 500 KSPS,  
fi = 1.9 kHz,  
TA = 30°C  
fi = 1.9 kHz,  
TA = 30°C  
fi = 1.9 kHz,  
TA = 30°C  
94.5  
94.5  
94  
94  
115  
114  
93.5  
93.5  
2
2.5  
3
3.5  
4
4.5  
5
2
2.5  
3
3.5  
4
4.5  
5
2
2.5  
3
3.5  
4
4.5  
5
Vref - Reference Voltage - V  
Vref - Reference Voltage - V  
Vref - Reference Voltage - V  
Figure 24.  
Figure 25.  
Figure 26.  
TOTAL HARMONIC DISTORTION  
SPURIOUS FREE DYNAMIC RANGE  
SIGNAL-TO-NOISE + DISTORTION  
vs  
vs  
vs  
REFERENCE VOLTAGE  
FREE-AIR TEMPERATURE  
FREE-AIR TEMPERATURE  
118  
124  
123  
122  
121  
120  
119  
118  
117  
116  
96.5  
96.4  
96.3  
117.5  
117  
96.2  
116.5  
116  
+VA = 5 V  
+VBD = 2.7 V,  
fs = 500 KSPS,  
96.1  
96  
fi = 1.9 kHz,  
TA = 30°C  
115.5  
115  
95.9  
95.8  
+VA = 5 V,  
+VBD = 2.7 V,  
Vref = 5 V,  
+VA = 5 V,  
+VBD = 2.7 V,  
Vref = 5 V,  
114.5  
95.7  
95.6  
95.5  
fs = 500 KSPS,  
fi = 1.9 kHz  
fs = 500 KSPS,  
fi = 1.9 kHz  
114  
115  
114  
113.5  
-40 -25 -10  
5
20 35 50  
65 80  
-40 -25 -10  
5
20 35 50  
65 80  
2
2.5  
3
3.5  
4
4.5  
5
TA - Free-Air Temperature - °C  
TA - Free-Air Temperature - °C  
Vref - Reference Voltage - V  
Figure 27.  
Figure 28.  
Figure 29.  
SIGNAL-TO-NOISE RATIO  
vs  
FREE-AIR TEMPERATURE  
TOTAL HARMONIC DISTORTION  
vs  
TOTAL HARMONIC DISTORTION  
vs  
FREE-AIR TEMPERATURE  
INPUT FREQUENCY  
120  
96.5  
118  
SNR  
96.4  
96.3  
117.5  
115  
117  
110  
105  
THD @ -10 dB  
96.2  
116.5  
116  
96.1  
96  
100  
95  
115.5  
115  
THD @ -0.5 dB  
95.9  
95.8  
+VA = 5 V  
+VBD = 2.7 V,  
Vref = 5 V,  
+VA = 5 V,  
+VBD = 2.7 V,  
Vref = 5 V,  
+VA = 5 V,  
+VBD = 2.7 V,  
Vref = 5 V,  
90  
85  
114.5  
95.7  
95.6  
95.5  
fs = 500 KSPS,  
TA = 30°C  
fs = 500 KSPS,  
fi = 1.9 kHz  
fs = 500 KSPS,  
fi = 1.9 kHz  
114  
113.5  
80  
1
10  
100  
-40 -25 -10  
5
20 35 50  
65 80  
-40 -25 -10  
5
20 35 50  
65 80  
fi - Input frequency - kHz  
TA - Free-Air Temperature - °C  
TA - Free-Air Temperature - °C  
Figure 30.  
Figure 31.  
Figure 32.  
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TYPICAL CHARACTERISTICS (continued)  
SIGNAL-TO-NOISE + DISTORTION  
TOTAL HARMONIC DISTORTION  
vs  
DC HISTORAM OF ADC CLOSE TO  
CENTER CODE  
vs  
INPUT FREQUENCY  
SOURCE RESISTANCE  
117  
116  
115  
114  
250000  
99  
97  
0 pF  
+VA = 5 V,  
+VBD = 2.7 V,  
Vref = 5 V,  
216040  
100 pF  
SINAD @ -10 dB  
200000  
150000  
100000  
50000  
0
fs = 500 KSPS,  
TA = 30°C  
95  
SINAD @ -0.5 dB  
93  
91  
113  
112  
111  
110  
680 pF  
+VA = 5 V  
+VBD = 2.7 V,  
Vref = 5 V,  
+VA = 5 V,  
+VBD = 2.7 V,  
Vref = 5 V,  
89  
87  
85  
46104  
fs = 500 KSPS,  
TA = 30°C  
fs = 500 KSPS,  
TA = 30°C  
0
0
32760  
0
100  
200  
300  
400  
500  
1
10  
fi - Input frequency - kHz  
100  
32757  
32758  
32759  
Source Resistance - W  
Codes  
Figure 33.  
Figure 34.  
Figure 35.  
SUPPLY CURRENT  
vs  
SUPPLY VOLTAGE  
SUPPLY CURRENT  
vs  
FREE-AIR TEMPERATURE  
SUPPLY CURRENT  
vs  
SAMPLING FREQUENCY  
4
4.2  
4
3.8  
3.75  
3.7  
+VA = 5 V,  
+VBD = 2.7 V,  
Vref = 5 V,  
+VBD = 2.7 V,  
+VA = 5 V,  
+VBD = 2.7 V,  
Vref = 5 V,  
3.5  
Vref = 4.096 V,  
fs = 500 KSPS,  
TA = 30°C  
TA = 30°C  
3
2.5  
2
fs = 500 KSPS  
3.65  
3.8  
3.6  
3.4  
3.6  
3.55  
3.5  
1.5  
3.45  
1
0.5  
0
3.4  
3.2  
3
3.35  
3.3  
0
50 100 150 200 250 300 350 400 450 500  
-40 -25 -10  
5
20 35 50 65 80  
4.5  
4.75  
5
5.25  
5.5  
TA - Free-Air Temperature - °C  
fs - Sampling Frequency - KSPS  
+VA - Supply Voltage - V  
Figure 36.  
Figure 37.  
Figure 38.  
POWER DISSIPATION  
vs  
SAMPLING FREQUENCY  
POWERDOWN CURRENT  
vs  
POWERDOWN CURRENT  
vs  
FREE-AIR TEMPERATURE  
SUPPLY VOLTAGE  
500  
450  
500  
450  
20  
18  
+VA = 5 V,  
+VBD = 2.7 V,  
Vref = 5 V,  
+VBD = 2.7 V,  
Vref = 4.096 V,  
+VA = 5 V,  
+VBD = 2.7 V,  
Vref = 5 V,  
fs = 0.0 KSPS,  
TA = 30°C  
400  
16  
14  
12  
10  
8
400  
350  
300  
fs = 0.0 KSPS  
TA = 30°C  
350  
300  
250  
250  
200  
150  
100  
200  
150  
100  
50  
6
4
50  
0
2
0
0
4.5  
4.75  
5
5.25  
5.5  
0
50 100 150 200 250 300 350 400 450 500  
-40 -25 -10  
5
20  
35 50 65 80  
+VA - Supply Voltage - V  
fs - Sampling Frequency - KSPS  
TA - Free-Air Temperature - °C  
Figure 39.  
Figure 40.  
Figure 41.  
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TYPICAL CHARACTERISTICS (continued)  
DNL  
1
+VA = 5 V, +VBD = 2.7 V,  
0.8  
V
= 5 V, f = 500 KSPS,  
ref  
= 30°C  
s
0.6  
0.4  
0.2  
T
A
0
-0.2  
-0.4  
-0.6  
-0.8  
-1  
0
10000  
20000  
30000  
Codes  
40000  
50000  
60000  
Figure 42.  
INL  
1
+VA = 5 V, +VBD = 2.7 V,  
= 5 V, f = 500 KSPS,  
s
0.8  
0.6  
0.4  
V
ref  
T
= 30°C  
A
0.2  
0
-0.2  
-0.4  
-0.6  
-0.8  
-1  
0
10000  
20000  
30000  
40000  
50000  
60000  
Codes  
Figure 43.  
FFT  
0
+VA = 5 V,  
+VBD = 2.7 V,  
-20  
-40  
-60  
V
= 5 V,  
ref  
f
= 500 KSPS,  
= 1.9 kHz,  
= 30C  
s
-80  
f
i
-100  
T
A
-120  
-140  
-160  
-180  
-200  
200  
0
250  
50  
100  
150  
f - Frequency - kHz  
Figure 44.  
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DETAILED DESCRIPTIONS AND TIMING DIAGRAMS  
The ADS8318 is a high-speed, low power, successive approximation register (SAR) analog-to-digital converter  
(ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently  
includes a sample/hold function.  
The ADS8318 is a single channel device. The analog input is provided to two input pins: +IN and -IN. When a  
conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a  
conversion is in progress, both +IN and -IN inputs are disconnected from any internal function.  
The ADS8318 has an internal clock that is used to run the conversion, and hence the conversion requires a fixed  
amount of time. After a conversion is completed, the device reconnects the sampling capacitors to the +IN and  
–IN pins, and the device is in the acquisition phase. During this phase the device is powered down and  
conversion data can be read.  
The device digital output is available in SPI compatible format. It easily interfaces with microprocessors, DSPs, or  
FPGAs.  
This is a low pin count device; however, it offers six different options for the interface. They can be grossly  
classified as CS mode (3- or 4-wire interface) and daisy chain mode. In both modes it can either be with or  
without a busy indicator, where the busy indicator is a bit preceeding the 16-bit serial data.  
The 3-wire interface CS mode is useful for applications which need galvanic isolation on-board, where as 4-wire  
interface CS mode makes it easy to control an individual device while having multiple devices on-board. The  
daisy chain mode is provided to hook multiple devices in a chain like a shift register and is useful to reduce  
component count and the number signal traces on the board.  
CS MODE  
CS Mode is selected if SDI is high at the rising edge of CONVST. As indicated before there are four different  
interface options available in this mode, namely 3-wire CS mode without busy indicator, 3-wire CS mode with  
busy indicator, 4-wire CS mode without busy indicator, 4-wire CS mode with busy indicator. The following section  
discusses these interface options in detail.  
3-Wire CS Mode Without Busy Indicator  
Digital Host  
ADS8318  
CNV  
+VBD  
CONVST  
SDI  
CLK  
SDI  
SCLK  
SDO  
Figure 45. Connection Diagram, 3-Wire CS Mode without Busy Indicator (SDI = 1)  
The three wire interface option in CS mode is selected if SDI is tied to +VBD (see Figure 45). In the three wire  
interface option, CONVST acts like CS. As shown in Figure 46, the device samples the input signal and enters  
the conversion phase on the rising edge of CONVST, at the same time SDO goes to 3-state. Conversion is done  
with the internal clock and it continues irrespective of the state of CONVST. As a result it is possible to bring  
CONVST (acting as CS) low after the start of the conversion to select other devices on the board. But it is  
absolutely necessary that CONVST is high again before the minimum conversion time (tcnv in timing  
requirements table) is elapsed. A high level on CONVST at the end of the conversion ensures the device does  
not generate a busy indicator.  
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When the conversion is over, the device enters the acquisition phase and powers down. On the falling edge of  
CONVST, SDO comes out of three state, and the device outputs the MSB of the data. After this, the device  
outputs the next lower data bits on every falling edge of SCLK. SDO goes to 3-state after the 16th falling edge of  
SCLK or CONVST high, whichever occurs first. It is necessary that the device sees a minimum of 15 falling  
edges of SCLK during the low period of CONVST.  
tcyc  
t1  
CONVST  
tacq  
tcnv  
ACQUISITION  
CONVERSION  
ACQUISITION  
tclkl  
t2  
SCLK  
SDO  
1
2
16  
15  
tclkh  
ten  
tdis  
t3  
D14  
tclk  
D15  
D0  
D1  
Figure 46. Interface Timing Diagram, 3 Wire CS Mode Without Busy Indicator (SDI = 1)  
3 Wire CS Mode With Busy Indicator  
Digital Host  
ADS8318  
CONVST  
CNV  
SDI  
CLK  
SCLK  
SDO  
VBD  
+
SDI  
IRQ  
Figure 47. Connection Diagram, 3 Wire CS Mode With Busy Indicator  
The three wire interface option in CS mode is selected if SDI is tied to +VBD (see Figure 47). In the three wire  
interface option, CONVST acts like CS. As shown in Figure 48, the device samples the input signal and enters  
the conversion phase on the rising edge of CONVST, at the same time SDO goes to 3 state. Conversion is done  
with the internal clock and it continues irrespective of the state of CONVST. As a result it is possible to toggle  
CONVST (acting as CS) after the start of the conversion to select other devices on the board. But it is absolutely  
necessary that CONVST is low again before the minimum conversion time (tcnv in timing requirements table) is  
elapsed and continues to stay low until the end of maximum conversion time. A low level on the CONVST input  
at the end of a conversion ensures the device generates a busy indicator.  
When the conversion is over, the device enters the acquisition phase and powers down, and the device forces  
SDO out of three state and outputs a busy indicator bit (low level). The device outputs the MSB of data on the  
first falling edge of SCLK after the conversion is over and continues to output the next lower data bits on every  
subsequent falling edge of SCLK. SDO goes to three state after the 17th falling edge of SCLK or CONVST high,  
whichever occurs first. It is necessary that the device sees a minimum of 16 falling edges of SCLK during the low  
period of CONVST.  
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tcyc  
t1  
CONVST  
tacq  
tcnv  
ACQUISITION  
CONVERSION  
ACQUISITION  
tclkl  
t2  
1
SCLK  
SDO  
17  
tclkh  
2
3
16  
tclk  
D1  
t3  
D14  
tdis  
D15  
D0  
Figure 48. Interface Timing Diagram, 3 Wire CS Mode With Busy Indicator (SDI = 1)  
4 Wire CS Mode Without Busy Indicator  
CS1  
CS2  
CNV  
CONVST  
SDI  
CONVST  
SDI  
SDO  
SDO  
SDI  
SCLK  
SCLK  
CLK  
ADS8318#2  
ADS8318#1  
Digital Host  
Figure 49. Connection Diagram, 4 Wire CS Mode Without Busy Indicator  
As mentioned before for selecting CS mode it is necessary that SDI is high at the time of the CONVST rising  
edge. Unlike in three wire interface option, SDI is controlled by digital host and acts like CS. As shown in  
Figure 50, SDI goes to a high level before the rising edge of CONVST. The rising edge of CONVST while SDI is  
high selects CS mode, forces SDO to three state, samples the input signal, and the device enters the conversion  
phase. In the 4 wire interface option CONVST needs to be at a high level from the start of the conversion until all  
of the data bits are read. Conversion is done with the internal clock and it continues irrespective of the state of  
SDI. As a result it is possible to bring SDI (acting as CS) low to select other devices on the board. But it is  
absolutely necessary that SDI is high again before the minimum conversion time (tcnv in timing requirements  
table) is elapsed.  
When the conversion is over, the device enters the acquisition phase and powers down. SDI falling edge can  
occur after the maximum conversion time (tcnv in timing requirements table). Note that it is necessary that SDI is  
high at the end of the conversion, so that the device does not generate a busy indicator. The falling edge of SDI  
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brings SDO out of 3-state and the device outputs the MSB of the data. Subsequent to this the device outputs the  
next lower data bits on every falling edge of SCLK. SDO goes to three state after the 16th falling edge of SCLK or  
SDI (CS) high, whichever occurs first. As shown in Figure 49, it is possible to hook multiple devices on the same  
data bus. In this case the second device SDI (acting as CS) can go low after the first device data is read and  
device 1 SDO is in three state.  
Care needs to be taken so that CONVST and SDI are not low together at any time during the cycle.  
CONVST  
t
6
SDI (CS) #1  
t
4
t
t
5
SDI (CS) #2  
t
cnv  
acq  
t
en  
ACQUISITION  
CONVERSION  
ACQUISITION  
t
clkl  
t
2
SCLK  
SDO  
17  
t
1
2
16  
31  
32  
15  
18  
t
clkh  
t
t
dis  
en  
t
dis  
t
3
clk  
D15#1  
D14#1  
D1#1  
D0#1  
D15#2 D14#2  
D1#2  
D0#2  
Figure 50. Interface Timing Diagram, 4 Wire CS Mode Without Busy Indicator  
4 Wire CS Mode With Busy Indicator  
CS  
CNV  
SDI  
CONVST  
CLK  
+VBD  
SDO  
SDI  
IRQ  
ADS8318  
Digital Host  
Figure 51. Connection Diagram, 4 Wire CS Mode With Busy Indicator  
As mentioned before for selecting CS mode it is necessary that SDI is high at the time of the CONVST rising  
edge. Unlike in the three wire interface option, SDI is controlled by the digital host and acts like CS. As shown in  
Figure 52, SDI goes to a high level before the rising edge of CONVST. The rising edge of CONVST while SDI is  
high selects CS mode, forces SDO to three state, samples the input signal, and the device enters the conversion  
phase. In the 4 wire interface option CONVST needs to be at a high level from the start of the conversion until all  
of the data bits are read. Conversion is done with the internal clock and it continues irrespective of the state of  
SDI. As a result it is possible to toggle SDI (acting as CS) to select other devices on the board. But it is  
absolutely necessary that SDI is low before the minimum conversion time (tcnv in timing requirements table) is  
elapsed and continues to stay low until the end of the maximum conversion time. A low level on the SDI input at  
the end of a conversion ensures the device generates a busy indicator.  
When the conversion is over, the device enters the acquisition phase and powers down, forces SDO out of three  
state, and outputs a busy indicator bit (low level). The device outputs the MSB of the data on the first falling edge  
of SCLK after the conversion is over and continues to output the next lower data bits on every falling edge of  
SCLK. SDO goes to three state after the 17th falling edge of SCLK or SDI (CS) high, whichever occurs first.  
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Care needs to be taken so that CONVST and SDI are not low together at any time during the cycle.  
tcyc  
t6  
CNVST  
t5  
SDI (CS)  
t4  
tacq  
ACQUISITION  
tcnv  
ACQUISITION  
CONVERSION  
tclkh  
t2  
1
SCLK  
SDO  
17  
2
3
16  
tclkl  
tdis  
t3  
D14  
tclk  
D15  
D0  
D1  
Figure 52. Interface Timing Diagram, 4 Wire CS Mode With Busy Indicator  
Daisy Chain Mode  
Daisy chain mode is selected if SDI is low at the time of CONVST rising edge. This mode is useful to reduce  
wiring and hardware like digital isolators in the applications where multiple (ADC) devices are used. In this mode  
all of the devices are connected in a chain (SDO of one device connected to the SDI of the next device) and data  
transfer is analogous to a shift register.  
Like CS mode even this mode offers operation with or without a busy indicator. The following section discusses  
these interface options in detail.  
Daisy Chain Mode Without Busy Indicator  
CNV  
CONVST  
CONVST  
SDI  
SDO  
SDI  
SDO  
SDI  
SCLK  
SCLK  
CLK  
ADS8318#1  
ADS8318#2  
Digital Host  
Figure 53. Connection Diagram, Daisy Chain Mode Without Busy Indicator (SDI = 0)  
Refer to Figure 53 for the connection diagram. SDI for device 1 is tied to ground and SDO of device 1 goes to  
SDI of device 2 and so on. SDO of the last device in the chain goes to the digital host. CONVST for all of the  
devices in the chain are tied together. In this mode there is no CS signal. The device SDO is driven low when  
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SDI and CONVST are low together. The rising edge of CONVST while SDI is low selects daisy chain mode and  
the device samples the analog input and enters the conversion phase. It is necessary that SCLK is low at the  
rising edge of CONVST so that the device does not generate a busy indicator at the end of the conversion. In  
this mode CONVST continues to be high from the start of the conversion until all of the data bits are read. Once  
started, conversion continues irrespective of the state of SCLK.  
At the end of the conversion, every device in the chain initiates output of its conversion data starting with the  
MSB bit. Further the next lower data bit is output on every falling edge of SCLK. While every device outputs its  
data on the SDO pin, it also receives previous device data on the SDI pin (other than device #1) and stores it in  
the shift register. The device latches incoming data on every falling edge of SCLK. SDO of the first device in the  
chain goes low after the 16th falling edge of SCLK. All subsequent devices in the chain output the stored data  
from the previous device in MSB first format immediately following their own data word.  
It needs 16 × N clocks to read data for N devices in the chain.  
tcyc  
t
CONVST  
6
tacq  
ACQUISITION  
tcnv  
ACQUISITION  
t7  
CONVERSION  
t
clkl  
t2  
SCLK  
17  
16  
32  
1
2
18  
15  
31  
t8  
t
clkh  
t
clk  
#1-D0  
#1-D0  
#1-D15  
#1-D15  
#1-D14  
t3  
#1-D1  
#1-D1  
SDO #1, SDI #2  
#2-D1  
#2-D14  
#2-D0  
SDO #2  
#1-D14  
#2-D15  
Figure 54. Interface Timing Diagram, Daisy Chain Mode Without Busy Indicator  
Daisy Chain Mode With Busy Indicator  
CNV  
CONVST  
CONVST  
SCLK  
IRQ  
SDI  
SDI  
SDO  
SDI  
SDO  
SCLK  
CLK  
ADS8318#1  
ADS8318#2  
Digital Host  
Figure 55. Connection Diagram, Daisy Chain Mode With Busy Indicator (SDI = 0)  
Refer to Figure 55 for the connection diagram. SDI for device 1 is wired to it's CONVST and CONVST for all the  
devices in the chain are wired together. SDO of device 1 goes to SDI of device 2 and so on. SDO of the last  
device in the chain goes to the digital host. In this mode there is no CS signal. On the rising edge of CONVST,  
all of the device in the chain sample the analog input and enter the conversion phase. For the first device, SDI  
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and CONVST are wired together, and the setup time of SDI to rising edge of CONVST is adjusted so that the  
device still enters chain mode even though SDI and CONVST rise together. It is necessary that SCLK is high at  
the rising edge of CONVST so that the device generates a busy indicator at the end of the conversion. In this  
mode, CONVST continues to be high from the start of the conversion until all of the data bits are read. Once  
started, conversion continues irrespective of the state of SCLK.  
At the end of the conversion, all the devices in the chain generate busy indicators. On the first falling edge of  
SCLK following the busy indicator bit, all of the devices in the chain output their conversion data starting with the  
MSB bit. After this the next lower data bit is output on every falling edge of SCLK. While every device outputs its  
data on the SDO pin, it also receives the previous device data on the SDI pin (except for device #1) and stores it  
in the shift register. Each device latches incoming data on every falling edge of SCLK. SDO of the first device in  
the chain goes high after the 17th falling edge of SCLK. All subsequent devices in the chain output the stored  
data from the pervious device in MSB first format immediately following their own data word. It needs 16 × N + 1  
clock pulses to read data for N devices in the chain.  
t
cyc  
t
CONVST  
6
t
t
acq  
cnv  
ACQUISITION  
CONVERSION  
ACQUISITION  
t
t
clkl  
t
7
2
1
18  
17  
33  
2
3
19  
SCLK  
16  
32  
t
clk  
t
8
t
clkh  
#1-D15  
#1-D15  
#1-D14  
#1-D0  
SDO #1, SDI #2  
SDO #2  
#1-D1  
#1-D1  
t
3
#2-D1  
#1-D0  
#2-D14  
#2-D0  
#1-D14  
#2-D15  
Figure 56. Interface Timing Diagram, Daisy Chain Mode With Busy Indicator  
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APPLICATION INFORMATION  
ANALOG INPUT  
When the converter samples the input, the voltage difference between the +IN and -IN inputs is captured on the  
internal capacitor array. The voltage on the +IN and –IN inputs individually is limited between GND –0.1 V and  
Vref + 0.1 V; where as the differential signal range [(+IN) – (–IN)] is 2Vref (–Vref to +Vref) with a common mode of  
(Vref/2). This allows the input to reject small signals which are common to both the +IN and –IN inputs.  
The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input  
voltage, and source impedance. The current into the ADS8318 charges the internal capacitor array during the  
sample period. After this capacitance has been fully charged, there is no further input current. The source of the  
analog input voltage must be able to charge the input capacitance (59 pF) to a 18-bit settling level within the  
minimum acquisition time. When the converter goes into hold mode, the input impedance is greater than 1 GΩ.  
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN  
and -IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, converter  
linearity may not meet specifications.  
Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are  
matched. If this is not observed, the two inputs could have different settling times. This may result in an offset  
error, gain error, and linearity error which change with temperature and input voltage.  
Device in Hold Mode  
55 pF  
218 W  
+IN  
4 pF  
+VA  
AGND  
4 pF  
55 pF  
218 W  
-IN  
Figure 57. Input Equivalent Circuit  
DRIVER AMPLIFIER CHOICE  
The analog input to the converter needs to be driven with a low noise, op-amp like the THS4031, OPA211. An  
RC filter is recommended at the input pins to low-pass filter the noise from the source. Two resistors of 5Ω and a  
differential capacitor of 1nF is recommended. The input to the converter is a unipolar input voltage in the range 0  
V to Vref. The minimum –3dB bandwidth of the driving operational amplifier can be calculated as:  
f3db = (ln(2) × (n+2))/(2π × tACQ)  
where n is equal to 16, the resolution of the ADC (in the case of the ADS8318). When tACQ = 600 ns (minimum  
acquisition time), the minimum bandwidth of the driving circuit is ~3 MHz (including RC following the driver OPA).  
The bandwidth can be relaxed if the acquisition time is increased by the application.  
Typically a low noise OPA with ten times or higher bandwidth is selected. The driving circuit bandwidth is  
adjusted (to the required value) with a RC following the OPA. The OPA211 or THS4031 from Texas Instruments  
is recommended for driving high-resolution high-speed ADCs.  
DRIVER AMPLIFIER CONFIGURATIONS  
Configuration for Unipolar Differential Input  
It is better to use a unity gain, noninverting buffer configuration for a unipolar, differential input having a ±Vref  
signal range with Vref/2 common-mode. As explained before a RC following the OPA limits the input circuit  
bandwidth just enough for 16-bit settling. Note higher bandwidth reduces the settling time (beyond what is  
needed) but increases the noise in the ADC sampled signal, and hence the ADC output.  
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Figure 58. Unipolar Differential Input Drive Configuration  
Configuration for Bipolar Single-Ended Input  
The following circuit shows a way to convert a single-ended bipolar input to the unipolar differential input needed  
for for converter. Note that the higher values of the resistors at the input of the top OPA may reduce power  
consumption of the circuit but increase noise in the driving circuit. One can choose these components based on  
application needs.  
Vref  
_
+
R
Bipolar  
Analog  
Input  
5 E  
1 nF  
5 E  
R
100 E  
100 E  
+IN  
-IN  
Vref  
_
+
ADS8318  
Vref/2  
OPA Shown is THS4031 or OPA211  
Figure 59. Bipolar Single-Ended Input Drive Configuration  
REFERENCE  
The ADS8318 can operate with an external reference with a range from 2.048 V to VDD + 0.1 V. A clean, low  
noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A  
low noise band-gap reference like the REF5050 can be used to drive this pin as shown in Figure 60 and  
Figure 61. The capacitor should be placed as close as possible to the pins of the device.  
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50 W  
-
REF5050  
OUT  
+
10 mF  
+
-
OPA365  
47 mF,  
1.5 W ESR  
(High ESR)  
REFIN  
TRIM  
+
IN+  
IN-  
4.7 mF,  
Low ESR  
-
ADS8318  
Figure 60. External Reference Driving Circuit  
REF5050  
OUT  
+
-
47 mF,  
1.5 W ESR  
(High ESR)  
22 mF  
REFIN  
TRIM  
+
-
4.7 mF,  
Low ESR  
IN+  
IN-  
ADS8318  
Figure 61. Direct External Reference Driving Circuit  
POWER SAVING  
The ADS8318 has an auto power-down feature. The device powers down at the end of every conversion. The  
input signal is acquired on sampling capacitors while the device is in the power-down state, and at the same time  
the conversion results are available for reading. The device powers up by itself on the start of the conversion. As  
discussed before, the conversion runs on an internal clock and takes a fixed time. As a result, device power  
consumption is directly proportional to the speed of operation.  
DIGITAL OUTPUT  
As discussed before (in the DESCRIPTION and TIMING DIAGRAMS sections) the device digital output is SPI  
compatible. The following table lists the output codes corresponding to various analog input voltages.  
DESCRIPTION  
Full-scale range  
ANALOG VALUE (V)  
DIGITAL OUTPUT STRAIGHT BINARY  
2*Vref  
Least significant bit (LSB)  
Positive full scale  
Midscale  
2*Vref/65536  
+Vref – 1 LSB  
0 V  
BINARY CODE  
HEX CODE  
0111 1111 1111 1111  
0000 0000 0000 0000  
1111 1111 1111 1111  
1000 0000 0000 0000  
7FFF  
0000  
FFFF  
8000  
Midscale – 1 LSB  
Negative full scale  
0 – 1 LSB  
–Vref  
SCLK INPUT  
The device uses SCLK for serial data output. Data is read after the conversion is over and the device is in the  
acquisition phase. It is possible to use a free running SCLK for the device, but it is recommended to stop the  
clock during a conversion, as the clock edges can couple with the internal analog circuit and can affect  
conversion results.  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
29-Sep-2008  
PACKAGING INFORMATION  
Orderable Device  
ADS8318IBDGSR  
ADS8318IBDGST  
ADS8318IBDRCR  
ADS8318IBDRCT  
ADS8318IDGSR  
ADS8318IDGST  
ADS8318IDRCR  
ADS8318IDRCT  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
MSOP  
DGS  
10  
10  
10  
10  
10  
10  
10  
10  
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
MSOP  
SON  
DGS  
DRC  
DRC  
DGS  
DGS  
DRC  
DRC  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS &  
no Sb/Br)  
Call TI  
Level-3-260C-168 HR  
SON  
250 Green (RoHS &  
no Sb/Br)  
Call TI  
Level-3-260C-168 HR  
MSOP  
MSOP  
SON  
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS &  
no Sb/Br)  
Call TI  
Level-3-260C-168 HR  
SON  
250 Green (RoHS &  
no Sb/Br)  
Call TI  
Level-3-260C-168 HR  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
26-Sep-2008  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) W1 (mm)  
(mm) (mm) Quadrant  
ADS8318IBDGSR  
ADS8318IBDGST  
ADS8318IBDRCR  
ADS8318IBDRCT  
ADS8318IDGSR  
ADS8318IDGST  
ADS8318IDRCR  
ADS8318IDRCT  
MSOP  
MSOP  
SON  
DGS  
DGS  
DRC  
DRC  
DGS  
DGS  
DRC  
DRC  
10  
10  
10  
10  
10  
10  
10  
10  
2500  
250  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
5.3  
5.3  
3.3  
3.3  
5.3  
5.3  
3.3  
3.3  
3.4  
3.4  
3.3  
3.3  
3.4  
3.4  
3.3  
3.3  
1.4  
1.4  
1.1  
1.1  
1.4  
1.4  
1.1  
1.1  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
Q1  
Q1  
Q2  
Q2  
Q1  
Q1  
Q2  
Q2  
3000  
250  
SON  
MSOP  
MSOP  
SON  
2500  
250  
3000  
250  
SON  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
26-Sep-2008  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
ADS8318IBDGSR  
ADS8318IBDGST  
ADS8318IBDRCR  
ADS8318IBDRCT  
ADS8318IDGSR  
ADS8318IDGST  
ADS8318IDRCR  
ADS8318IDRCT  
MSOP  
MSOP  
SON  
DGS  
DGS  
DRC  
DRC  
DGS  
DGS  
DRC  
DRC  
10  
10  
10  
10  
10  
10  
10  
10  
2500  
250  
346.0  
346.0  
340.5  
340.5  
346.0  
346.0  
340.5  
340.5  
346.0  
346.0  
333.0  
333.0  
346.0  
346.0  
333.0  
333.0  
29.0  
29.0  
20.6  
20.6  
29.0  
29.0  
20.6  
20.6  
3000  
250  
SON  
MSOP  
MSOP  
SON  
2500  
250  
3000  
250  
SON  
Pack Materials-Page 2  
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designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated  
products in automotive applications, TI will not be responsible for any failure to meet such requirements.  
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:  
Products  
Applications  
Audio  
Automotive  
Broadband  
Digital Control  
Medical  
Amplifiers  
Data Converters  
DSP  
Clocks and Timers  
Interface  
amplifier.ti.com  
dataconverter.ti.com  
dsp.ti.com  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
www.ti.com/audio  
www.ti.com/automotive  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/medical  
www.ti.com/military  
Logic  
Military  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
microcontroller.ti.com  
www.ti-rfid.com  
Optical Networking  
Security  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
RF/IF and ZigBee® Solutions www.ti.com/lprf  
www.ti.com/wireless  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2008, Texas Instruments Incorporated  

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