ADS7961-Q1 [TI]
汽车类 8 位、1MSPS、16 通道单端微功耗、串行接口 ADC;
| 型号： | ADS7961-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 8 位、1MSPS、16 通道单端微功耗、串行接口 ADC |
| 文件： | 总55页 (文件大小：1521K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
ADS79xx-Q1 8 位，10 位和 12 位，1MSPS，4 通道，8 通道，12 通道和
16 通道，单端，微功耗，串行接口，模数转换器
1 特性
ADS79xx-Q1 器件在 2.7V 至 5.25V 的宽模拟电源范
围内运行。由于功耗极低，这些器件非常适合于电池供
电和隔离式电源供电的应用。
1
•
•
符合汽车应用要求
具有经 AEC-Q100 测试的下列结果：
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
4 通道和 8 通道器件采用 30 引脚 TSSOP 封装。 12
通道和 16 通道器件采用 38 引脚 TSSOP 封装。
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
H2
器件信息(1)
器件充电器件模型 (CDM) ESD 分类等级 C4B
器件名称
ADS7950-Q1
ADS7951-Q1
ADS7954-Q1
ADS7958-Q1
ADS7959-Q1
ADS7952-Q1
ADS7953-Q1
ADS7956-Q1
ADS7957-Q1
ADS7960-Q1
ADS7961-Q1
封装
封装尺寸
•
产品系列：
–
–
8 位，10 位和 12 位分辨率
TSSOP (30)
7.80mm × 4.40mm
4 通道、8 通道和 12 通道器件与 16 通道器件
均采用相同封装尺寸
•
•
•
•
1MHz 采样率串行器件
模拟电源范围：2.7V 至 5.25V
I/O 电源范围：1.7V 至 5.25V
两个软件可选单极、输入范围：
TSSOP (38)
9.70mm x 4.40mm
–
（0V 至 2.5V）或（0V 至 5V）
•
•
•
•
针对通道选择的自动和手动模式
每通道两个可编程警报级别
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
四个独立可配置通用输入输出 (GPIO) 接口
典型功率耗散值：1MSPS 下为 14.5mW (V(+VA)
5V，(+VBD) = 3V)
=
详细方框图
PGA Gain
Control
•
•
断电电流 (1μA)
High input
impedance PGA
(or non inverting
buffer such as
THS4031)
GPIO1
GPIO2
GPIO3
30 引脚和 38 引脚薄型小外形尺寸 (TSSOP) 封装
2 应用范围
MXO
AINP
GPIO0
high-alarm
low-alarm
•
•
•
•
车载系统
Ch0
Ch1
电源监控
Ch2
电池供电系统
高速、数据采集系统
To
Host
ADC
SDO
3 说明
SDI
SCLK
CS
ADS79xx-Q1 器件系列由多通道 8 位，10 位和 12 位
模数转换器 (ADC) 组成。 此器件包括一个基于电容器
的逐次逼近寄存器 (SAR) ADC，此 ADC 支持固有的
采样保持。 多特性和出色性能使得 ADS79xx-Q1 器件
可用于需要对多条通道进行监控的广泛应用。
(1)
Chn
REF
10 µF
REF5025
o/p
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SBAS652
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
www.ti.com.cn
目录
8.1 Overview ................................................................. 20
8.2 Functional Block Diagram ...................................... 20
8.3 Feature Description................................................. 21
8.4 Device Functional Modes........................................ 25
8.5 Digital Output Code................................................. 35
8.6 Programming: GPIO................................................ 36
Application and Implementation ........................ 40
9.1 Application Information............................................ 40
9.2 Typical Applications ................................................ 40
9.3 Do's and Don'ts....................................................... 42
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configurations and Functions....................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ..................................... 5
7.2 Handling Ratings....................................................... 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
9
10 Power-Supply Recommendations ..................... 42
11 Layout................................................................... 43
11.1 Layout Guidelines ................................................. 43
11.2 Layout Example .................................................... 43
12 器件和文档支持 ..................................................... 44
12.1 文档支持................................................................ 44
12.2 相关链接................................................................ 44
12.3 商标....................................................................... 44
12.4 静电放电警告......................................................... 44
12.5 术语表 ................................................................... 44
13 机械封装和可订购信息 .......................................... 44
7.5 Electrical Characteristics: ADS7950-Q1, ADS7951-
Q1, ADS7952-Q1, ADS7953-Q1 ............................... 6
7.6 Electrical Characteristics: ADS7954-Q1, ADS7956-
Q1, ADS7957-Q1....................................................... 8
7.7 Electrical Characteristics: ADS7958-Q1, ADS7959-
Q1, ADS7960-Q1, ADS7961-Q1 ............................... 9
7.8 Timing Requirements.............................................. 11
7.9 Typical Characteristics (All ADS79xx-Q1 Family
Devices) ................................................................... 12
7.10 Typical Characteristics (12-Bit Devices Only)....... 13
8
Detailed Description ............................................ 20
4 修订历史记录
Changes from Original (May 2014) to Revision A
Page
•
•
•
在器件信息表中添加了所有器件 ............................................................................................................................................. 1
Deleted Device Comparison Table footnote........................................................................................................................... 3
Changed entire Application and Implementation section .................................................................................................... 40
2
Copyright © 2014, Texas Instruments Incorporated
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
www.ti.com.cn
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
5 Device Comparison Table
RESOLUTION
10 BIT
NUMBER OF CHANNELS
12 BIT
8 BIT
4
8
ADS7950-Q1
ADS7951-Q1
ADS7952-Q1
ADS7953-Q1
ADS7954-Q1
—
ADS7958-Q1
ADS7959-Q1
ADS7960-Q1
ADS7961-Q1
12
16
ADS7956-Q1
ADS7957-Q1
6 Pin Configurations and Functions
DBT Package
TSSOP-30
(Top View)
1
30
29
28
27
26
25
GPIO2
GPIO3
REFM
REFP
GPIO1
1
30
29
28
27
26
25
GPIO2
GPIO3
GPIO1
GPIO0
2
GPIO0
+VBD
BDGND
SDO
2
3
3
REFM
REFP
+VBD
BDGND
SDO
4
4
5
+VA
AGND
MXO
5
+VA
AGND
MXO
6
SDI
6
SDI
7
24 SCLK
23 CS
7
24 SCLK
23 CS
ADS7950-Q1
ADS7954-Q1
ADS7958-Q1
AINP
AINM
8
AINP
AINM
8
ADS7951-Q1
ADS7959-Q1
9
22
AGND
9
22
AGND
10
21
AGND
+VA
10
21
AGND
+VA
NC 11
CH3 12
NC 13
20
19
CH0
NC
CH7 11
CH6 12
CH5 13
CH4 14
NC 15
20
19
CH0
CH1
18 CH1
17 NC
16 NC
18 CH2
17 CH3
16 NC
CH2 14
NC 15
NC = No internal connection
DBT Package
TSSOP-38
(Top View)
1
2
3
4
5
6
7
8
9
10
38
1
38
GPIO2
GPIO3
REFM
REFP
GPIO1
GPIO2
GPIO3
REFM
REFP
+VA
GPIO1
2
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
37
36
35
34
33
32
31
30
29
GPIO0
+VBD
BDGND
SDO
GPIO0
+VBD
3
4
BDGND
SDO
SDI
5
+VA
6
AGND
AGND
MXO
SDI
7
MXO
AINP
AINM
SCLK
CS
SCLK
CS
8
AINP
9
AINM
AGND
NC
AGND
+VA
AGND
ADS7952-Q1
ADS7956-Q1
ADS7953-Q1
ADS7957-Q1
ADS7961-Q1
10
11
12
13
14
15
16
17
18
19
AGND
CH15
CH14
+VA
11 ADS7960-Q1 28
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
12
13
14
15
16
17
18
19
27
26
25
24
23
22
21
20
NC
NC
CH13
CH12
CH11
CH10
CH9
NC
CH11
CH10
CH9
CH8
CH8
AGND
AGND
Copyright © 2014, Texas Instruments Incorporated
3
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
www.ti.com.cn
Pin Functions
PIN
NUMBER
I/O
DESCRIPTION
ADS7953-Q1, ADS7952-Q1,
ADS7957-Q1, ADS7956-Q1,
ADS7961-Q1 ADS7960-Q1
ADS7950-Q1,
ADS7954-Q1,
ADS7958-Q1
NAME
ADS7951-Q1,
ADS7959-Q1
ADC ANALOG INPUT
AINM
AINP
9
8
9
8
9
8
9
8
I
I
ADC input ground
Signal input to ADC
DIGITAL CONTROL SIGNALS
CS
31
32
33
34
31
32
33
34
23
24
25
26
23
24
25
26
I
I
Chip-select input
Serial clock input
Serial data input
Serial data output
SCLK
SDI
I
SDO
O
GENERAL PURPOSE INPUTS AND OUTPUTS(1)
GPIO0
I/O General-purpose input or output
37
37
29
29
High or low
alarm
Active high output indicating high alarm or low alarm, depending on
programming
O
GPIO1
Low alarm
GPIO2
Range
GPIO3
PD
I/O General-purpose input or output
Active high output indicating low alarm
I/O General-purpose input or output
Selects range: High → Range 2; Low → Range 1
I/O Genera-purpose input or output
38
1
38
1
30
1
30
1
O
I
2
2
2
2
I
Active low power-down input
MULTIPLEXER
Ch0
28
27
26
25
24
23
22
21
18
17
16
15
14
13
12
11
7
28
27
26
25
24
23
22
21
18
17
16
15
—
—
—
—
7
20
19
18
17
14
13
12
11
—
—
—
—
—
—
—
—
7
20
18
14
12
—
—
—
—
—
—
—
—
—
—
—
—
7
I
I
Ch1
Ch2
I
Ch3
I
Ch4
I
Ch5
I
Ch6
I
Ch7
I
Analog channels for multiplexer
Ch8
I
Ch9
I
Ch10
Ch11
Ch12
Ch13
Ch14
Ch15
MXO
I
I
I
I
I
I
O
Multiplexer output
NC PINS
—
11
12
13
14
—
—
15
16
—
—
—
—
11
13
15
16
17
19
NC
—
Pins internally not connected, do not float these pins
(1) These pins have programmable dual functionality. See Table 12 for functionality programming.
4
Copyright © 2014, Texas Instruments Incorporated
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
www.ti.com.cn
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
Pin Functions (continued)
PIN
NUMBER
ADS7953-Q1, ADS7952-Q1,
I/O
DESCRIPTION
ADS7950-Q1,
ADS7954-Q1,
ADS7958-Q1
NAME
ADS7951-Q1,
ADS7957-Q1, ADS7956-Q1,
ADS7961-Q1 ADS7960-Q1
ADS7959-Q1
POWER SUPPLY AND GROUND
6
6
6
6
10
10
19
20
30
35
5
10
22
—
—
27
5
10
22
—
—
27
5
AGND
19
20
30
35
5
—
Analog ground
BDGND
+VA
—
—
—
Digital ground
Analog power supply
Digital I/O supply
29
36
29
36
21
28
21
28
+VBD
REFERENCE
REFM
3
4
3
4
3
4
3
4
I
I
Reference ground
Reference input
REFP
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted).
MIN
MAX
UNIT
V
Supply voltage to ground
Signal input
+VA to AGND, +VBD to BDGND
AINP or CHn to AGND
To BDGND
–0.3
–0.3
–0.3
–0.3
7
V(+VA) + 0.3
7
V
Digital input
V
Digital output
To BDGND
V(+VA) + 0.3
150
V
Junction temperature, TJ
°C
(1) Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated as recommended operating conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
MIN
–65
–2
MAX
150
2
UNIT
°C
Tstg
Storage temperature range
Human-body model (HBM), per AEC Q100-002(1), level H2
kV
Corner pins
(1, 15, 16, and 30 for 30-pin packages
1, 19, 20, and 38 for 38-pin packages)
Electrostatic
discharge
V(ESD)
–750
–500
750
500
Charged-device model (CDM),
per AEC Q100-001, level C4B
V
All pins
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Copyright © 2014, Texas Instruments Incorporated
5
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
www.ti.com.cn
MAX UNIT
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
1.7
2
NOM
3.3
V(+VA)
V(+VBD)
V(REF)
ƒ(SCLK)
TA
Analog power-supply voltage
Digital I/O-supply voltage
Reference voltage
5.25
V(+VA)
3
V
V
3.3
2.5
V
SCLK frequency
20
MHz
°C
Operating temperature range
–40
125
7.4 Thermal Information
ADS79xx-Q1
THERMAL METRIC(1)
DBT (TSSOP)
38 PINS
83.6
DBT (TSSOP)
30 PINS
89.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
29.8
22.9
44.7
43.1
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.9
0.8
ψJB
44.1
42.5
RθJC(bot)
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics: ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1
V(+VA) = 2.7 V to 5.25 V, V(+VBD) = 1.7 V to V(+VA), Vref = 2.5 V ± 0.1 V, TA = –40°C to 125°C, ƒsample = 1 MHz (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Range 1
0
0
Vref
2 × Vref
V
V
V
Full-scale input span(1)
Absolute input range
Range 2 while 2 × Vref ≤ +VA
Range 1
–0.2
Vref + 0.2
2 × Vref
+
Range 2 while 2 × Vref ≤ +VA
–0.2
V
0.2
Input capacitance
15
61
ρF
Input leakage current
TA = 125°C
nA
SYSTEM PERFORMANCE
Resolution
12
Bits
Bits
1.5 LSB(2)
No missing codes
Integral linearity
Differential linearity
Offset error(3)
11
–1.5
–2
±0.75
±0.75
±1.1
±0.2
±0.2
±2
1.5
3.5
2
LSB
LSB
LSB
LSB
LSB
–3.5
–2
Range 1
Range 2
Gain error
TUE
Total unadjusted error
SAMPLING DYNAMICS
Conversion time
20-MHz SCLK
20-MHz SCLK
800
1
ns
ns
Acquisition time
325
Maximum throughput rate
Aperture delay
MHz
ns
5
150
150
Step response
ns
Over voltage recovery
ns
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least-significant bit.
(3) Measured relative to an ideal full-scale input
6
Copyright © 2014, Texas Instruments Incorporated
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
www.ti.com.cn
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
Electrical Characteristics: ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1 (continued)
V(+VA) = 2.7 V to 5.25 V, V(+VBD) = 1.7 V to V(+VA), Vref = 2.5 V ± 0.1 V, TA = –40°C to 125°C, ƒsample = 1 MHz (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
THD
Total harmonic distortion(4)
100 kHz
100 kHz
100 kHz
100 kHz
At –3 dB
–82
71.7
71.3
84
dB
dB
SNR
Signal-to-noise ratio
70
68
SINAD
SFDR
Signal-to-noise + distortion
Spurious-free dynamic range
Small signal bandwidth
dB
dB
47
MHz
Any off-channel with 100 kHz. Full-scale input to channel
being sampled with DC input (isolation crosstalk).
–95
–85
dB
dB
Channel-to-channel crosstalk
From previously sampled to channel with 100 kHz. Full-
scale input to channel being sampled with DC input
(memory crosstalk).
EXTERNAL REFERENCE INPUT
Vref
Rref
Reference voltage at REFP(5)
2
2.5
3
V
Reference resistance
100
kΩ
ALARM SETTING
Higher threshold range
0
0
FFC
FFC
Hex
Hex
Lower threshold range
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
VIH
0.7 ×
V(+VBD)
High logic-level input voltage
V
V(+VA) = 5 V
0.8
0.4
V
V
VIL
Low logic-level input voltage
High logic-level output voltage
V(+VA) = 3 V
VOH
At source current (IS) = 200 μA
V(+VBD)
–
V
V
0.2
VOL
Low logic-level output voltage
Data format MSB first
At Isink = 200 μA
0.4
MSB first
POWER SUPPLY REQUIREMENTS
V(+VA)
Analog power-supply voltage
Digital I/O-supply voltage
2.7
1.7
3.3
3.3
1.8
1.05
2.3
1.1
1
5.25
V
V(+VBD)
V(+VA)
V
At V(+VA) = 2.7 V to 3.6 V and 1-MHz throughput
At V(+VA) = 2.7 V to 3.6 V static state
mA
mA
mA
mA
μA
mA
µs
I(+VA)
Supply current (normal mode)
At V(+VA) = 4.7 V to 5.25 V and 1-MHz throughput
At V(+VA) = 4.7 V to 5.25 V static state
3
1.5
Power-down state supply current
Digital I/O-supply current
Power-up time
I(+VBD)
V(+VA) = 5.25 V, ƒsample = 1 MHz
1
1
1
Invalid conversions after power up or
reset
cycle
Latch-up
JESD78 class I
TEMPERATURE RANGE
Specified performance
–40
125
°C
(4) Calculated on the first nine harmonics of the input frequency.
(5) The device is designed to operate over Vref = 2 V to 3 V. However, lower noise performance can be expected at Vref < 2.4 V, because of
SNR degradation resulting from lowered signal range.
Copyright © 2014, Texas Instruments Incorporated
7
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
www.ti.com.cn
7.6 Electrical Characteristics: ADS7954-Q1, ADS7956-Q1, ADS7957-Q1
V(+VA) = 2.7 V to 5.25 V, V(+VBD) = 1.7 V to V(+VA), Vref = 2.5 V ± 0.1 V, TA = –40°C to 125°C, ƒsample = 1 MHz (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Range 1
0
0
Vref
2 × Vref
V
V
Full-scale input span(1)
Range 2 while 2 × Vref ≤ +VA
Range 1
–0.2
–0.2
Vref + 0.2
V
Absolute input range
Range 2 while 2 × Vref ≤ +VA
2 × Vref +0.2
V
Input capacitance
15
61
ρF
nA
Input leakage current
TA = 125°C
SYSTEM PERFORMANCE
Resolution
10
Bits
Bits
No missing codes
Integral linearity
Differential linearity
Offset error(3)
10
–0.5
–0.5
–1.5
–1
±0.2
±0.2
±0.5
±0.1
±0.1
0.5
0.5
1.5
1
LSB(2)
LSB
LSB
LSB
LSB
Range 1
Range 2
Gain error
SAMPLING DYNAMICS
Conversion time
Acquisition time
20-MHz SCLK
20-MHz SCLK
800
1
ns
ns
325
Maximum throughput rate
Aperture delay
MHz
ns
5
150
150
Step response
ns
Over voltage recovery
DYNAMIC CHARACTERISTICS
ns
THD
Total harmonic distortion(4)
100 kHz
100 kHz
100 kHz
100 kHz
At –3 dB
–80
dB
dB
SNR
Signal-to-noise ratio
60
60
SINAD
SFDR
Signal-to-noise + distortion
Spurious-free dynamic range
Full-power bandwidth
dB
82
47
dB
MHz
Any off-channel with 100 kHz. Full-scale input to channel
being sampled with dc input.
–95
–85
dB
dB
Channel-to-channel crosstalk
From previously sampled to channel with 100 kHz. Full-
scale input to channel being sampled with dc input.
EXTERNAL REFERENCE INPUT
Vref
Rref
Reference voltage at REFP
Reference resistance
2
2.5
3
V
100
kΩ
ALARM SETTING
Higher threshold range
000
000
FFC
FFC
Hex
Hex
Lower threshold range
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
High logic-level input voltage
VIH
0.7 ×
V(+VBD)
V
V(+VBD) = 5 V
0.8
0.4
V
V
VIL
Low logic-level input voltage
High logic-level output voltage
V(+VBD) = 3 V
VOH
At source current (IS) = 200 μA
V(+VBD)
–
V
V
0.2
VOL
Low logic-level output voltage
Data format MSB first
At Isink = 200 μA
0.4
MSB first
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least significant bit.
(3) Measured relative to an ideal full-scale input
(4) Calculated on the first nine harmonics of the input frequency.
8
Copyright © 2014, Texas Instruments Incorporated
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
www.ti.com.cn
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
Electrical Characteristics: ADS7954-Q1, ADS7956-Q1, ADS7957-Q1 (continued)
V(+VA) = 2.7 V to 5.25 V, V(+VBD) = 1.7 V to V(+VA), Vref = 2.5 V ± 0.1 V, TA = –40°C to 125°C, ƒsample = 1 MHz (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY REQUIREMENTS
V(+VA)
Analog power-supply voltage
Digital I/O-supply voltage
2.7
1.7
3.3
3.3
1.8
1.05
2.3
1.1
1
5.25
V
V(+VBD)
V(+VA)
V
At V(+VA) = 2.7 V to 3.6 V and 1-MHz throughput
At V(+VA) = 2.7 V to 3.6 V static state
mA
mA
mA
mA
μA
mA
μs
1
3
I(+VA)
Supply current (normal mode)
At V(+VA) = 4.7 V to 5.25 V and 1-MHz throughput
At V(+VA) = 4.7 V to 5.25 V static state
1.5
Power-down state supply current
Digital I/O-supply current
Power-up time
I(+VBD)
V(+VA) = 5.25 V, ƒsample = 1 MHz
1
1
1
Invalid conversions after power up or
reset
cycle
Latch-up
JESD78 class I
TEMPERATURE RANGE
Specified performance
–40
125
°C
7.7 Electrical Characteristics: ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
V(+VA) = 2.7 V to 5.25 V, V(+VBD) = 1.7 V to V(+VA), Vref = 2.5 V ± 0.1 V, TA = –40°C to 125°C, ƒsample = 1 MHz (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Range 1
0
0
Vref
V
V
Full-scale input span(1)
Absolute input range
Range 2 while 2 × Vref ≤ +VA
2 × Vref
Vref
+
Range 1
–0.20
–0.20
V
V
0.2
2 × Vref
+ 0.2
Range 2 while 2 × Vref ≤ +VA
Input capacitance
15
61
ρF
Input leakage current
TA = 125°C
nA
SYSTEM PERFORMANCE
Resolution
8
Bits
Bits
No missing codes
Integral linearity
Differential linearity
Offset error(3)
8
–0.3
–0.3
–0.5
–0.6
±0.1
±0.1
±0.2
±0.1
±0.1
0.3
0.3
0.5
0.6
LSB(2)
LSB
LSB
LSB
LSB
Range 1
Range 2
Gain error
SAMPLING DYNAMICS
Conversion time
20-MHz SCLK
20-MHz SCLK
800
1
ns
ns
Acquisition time
325
Maximum throughput rate
Aperture delay
MHz
ns
5
150
150
Step response
ns
Over voltage recovery
ns
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least significant bit.
(3) Measured relative to an ideal full-scale input
Copyright © 2014, Texas Instruments Incorporated
9
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
www.ti.com.cn
Electrical Characteristics: ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1 (continued)
V(+VA) = 2.7 V to 5.25 V, V(+VBD) = 1.7 V to V(+VA), Vref = 2.5 V ± 0.1 V, TA = –40°C to 125°C, ƒsample = 1 MHz (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
THD
Total harmonic distortion(4)
100 kHz
100 kHz
100 kHz
100 kHz
At –3 dB
–75
dB
dB
SNR
Signal-to-noise ratio
49
49
SINAD
SFDR
Signal-to-noise + distortion
Spurious-free dynamic range
Full-power bandwidth
dB
–78
47
dB
MHz
Any off-channel with 100 kHz. Full-scale input to channel being
sampled with dc input.
–95
–85
dB
dB
Channel-to-channel crosstalk
From previously sampled to channel with 100 kHz. Full-scale input
to channel being sampled with dc input.
EXTERNAL REFERENCE INPUT
Vref
reference voltage at REFP
Reference resistance
2
2.5
3
V
100
kΩ
ALARM SETTING
Higher threshold range
000
000
FF
FF
Hex
Hex
Lower threshold range
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
VIH
High logic-level input voltage
0.7 ×
V(+VBD)
V
V(+VBD) = 5 V
0.8
0.4
V
V
VIL
Low logic-level input voltage
High logic-level output voltage
V(+VBD) = 3 V
VOH
At source current (IS) = 200 μA
V(+VBD)
–
V
V
0.2
VOL
Low logic-level output voltage
Data format
At Isink = 200 μA
0.4
MSB first
POWER SUPPLY REQUIREMENTS
V(+VA)
Analog power-supply voltage
Digital I/O-supply voltage
2.7
1.7
3.3
3.3
1.8
1.05
2.3
1.1
1
5.25
V
V(+VBD)
V(+VA)
V
At V(+VA) = 2.7 V to 3.6 V and 1-MHz throughput
At V(+VA) = 2.7 V to 3.6 V static state
mA
mA
mA
mA
μA
mA
μs
I(+VA)
Supply current (normal mode)
At V(+VA) = 4.7 V to 5.25 V and 1-MHz throughput
At V(+VA) = 4.7 V to 5.25 V static state
3
1.5
Power-down state supply current
Digital I/O-supply current
Power-up time
I(+VBD)
V(+VA) = 5.25 V, ƒsample = 1 MHz
1
1
1
Invalid conversions after power up or
reset
cycle
Latch-up
JESD78 class I
–40
TEMPERATURE RANGE
Specified performance
125
°C
(4) Calculated on the first nine harmonics of the input frequency.
10
Copyright © 2014, Texas Instruments Incorporated
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
www.ti.com.cn
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
7.8 Timing Requirements
All specifications typical at –40°C to 125°C, V(+VA) = 2.7 V to 5.25 V (unless otherwise specified). See Figure 45, Figure 46,
Figure 47, and Figure 48.
PARAMETER(1)(2)
MIN
TYP
MAX
UNIT
SCLK
SCLK
SCLK
ns
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
V(+VBD) = 1.8 V
V(+VBD) = 3 V
V(+VBD) = 5 V
16
tc
Conversion time
16
16
40
40
40
Minimum quiet sampling time needed from bus Tri-state to
start of next conversion
tq
ns
ns
38
27
17
ns
td1
Delay time, CS low to first data (DO–15) out
Setup time, CS low to first rising edge of SCLK
Delay time, SCLK falling to SDO next data bit valid
Hold time, SCLK falling to SDO data bit valid
Delay time, 16th SCLK falling edge to SDO 3-state
Setup time, SDI valid to rising edge of SCLK
Hold time, rising edge of SCLK to SDI valid
Pulse duration CS high
ns
ns
8
6
4
ns
tsu1
ns
ns
35
27
17
ns
td2
ns
ns
7
5
3
ns
th1
ns
ns
26
22
13
ns
td3
ns
ns
2
3
ns
tsu2
ns
4
ns
12
10
6
ns
th2
ns
ns
20
20
20
ns
tw1
ns
ns
24
21
12
ns
td4
Delay time CS high to SDO 3-state
Pulse duration SCLK high
ns
ns
20
20
20
20
20
20
ns
twH
twL
ƒ(SCLK)
ns
ns
ns
Pulse duration SCLK low
ns
ns
20
20
20
MHz
MHz
MHz
Frequency SCLK
(1) 1.8-V specifications apply from 1.7 V to 1.9 V, 3-V specifications apply from 2.7 V to 3.6 V, 5-V specifications apply from 4.75 V to 5.25
V.
(2) With 50-pF load
Copyright © 2014, Texas Instruments Incorporated
11
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
www.ti.com.cn
7.9 Typical Characteristics (All ADS79xx-Q1 Family Devices)
1.5
1.4
3.5
3
1.3
1.2
1.1
1
2.5
2
1.5
1
0.9
2.7
3.4
4.1
Supply Voltage (V)
4.8
5.5
2.7
3.4
4.1
Supply Voltage (V)
4.8
5.5
ƒsample = 1 MSPS
TA = 25°C
ƒsample = 0 MSPS
TA = 25°C
Figure 1. Supply Current (I(+VA)) vs Supply Voltage (V(+VA)
)
Figure 2. Idle Supply Current (I(+VA)) vs Supply Voltage
(V(+VA)
)
1.115
3.4
3.2
1.11
1.105
1.1
3
1.095
1.09
1.085
1.08
2.8
2.6
2.4
2.2
2
1.075
1.07
-40
15
70
125
-40
15
70
125
Free-Air Temperature (°C)
Free-Air Temperature (°C)
ƒsample = 0 MSPS
V(+VBD) = 5.5 V
ƒsample = 1 MSPS
V(+VBD) = 5.5 V
Figure 4. Idle Supply Current (I(+VA)) vs
Free-Air Temperature
Figure 3. Supply Current (I(+VA)) vs Free-Air Temperature
2.5
2.5
5 V
5 V
2.7 V
2.7 V
2
2
1.5
1
1.5
1
0.5
0
0.5
0
0
100
200
300
Sample Rate (KSPS)
400
500
0
200
400
600
800
1000
Sample Rate (KSPS)
No power-down
With power-down mode enabled
TA = 25°C
TA = 25°C
Figure 6. Supply Current (I(+VA)) vs Sample Rate with
Power-Down Mode Enabled
Figure 5. Supply Current (I(+VA)) vs Sample Rate
12
Copyright © 2014, Texas Instruments Incorporated
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
www.ti.com.cn
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
7.10 Typical Characteristics (12-Bit Devices Only)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves.
1
0.8
0.6
0.4
0.2
1
DNL max
DNL min
INL max
INL min
0.8
0.6
0.4
0.2
0
-0.2
-0.4
0
-0.2
-0.4
-0.6
-0.6
-0.8
-1
-0.8
-1
2.7
3.2
3.7
4.2
4.7
5.2
5.5
2.7
3.2
4.2
Supply Voltage (V)
4.7
5.2
3.7
Supply Voltage (V)
ƒsample = 1 MSPS
TA = 25°C
ƒsample = 1 MSPS
TA = 25°C
Figure 8. Integral Nonlinearity vs Supply Voltage (V(+VA)
)
Figure 7. Differential Nonlinearity vs Supply Voltage (V(+VA)
)
1
1
DNL max
INL max
0.8
0.8
0.6
DNL min
INL min
0.6
0.4
0.2
0.4
0.2
0
0
-0.2
-0.2
-0.4
-0.6
-0.4
-0.6
-0.8
-1
-0.8
-1
-40
15
70
125
-40
15 70
Free-Air Temperature (°C)
125
Free-Air Temperature (°C)
ƒsample = 1 MSPS
V(+VA) = 5 V
V(+VBD) = 5 V
ƒsample = 1 MSPS
V(+VA) = 5 V
V(+VBD) = 5 V
Figure 10. Integral Nonlinearity vs Free-Air Temperature
Figure 9. Differential Nonlinearity vs Free-Air Temperature
2
2
1.8
1.6
1.8
1.6
1.4
1.4
1.2
1.2
1
1
0.8
0.6
0.4
0.2
0.8
0.6
0.4
0.2
0
0
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.5
Interace Supply (V)
2.7
3.4
4.1
Supply Voltage (V)
4.8
5.5
ƒsample = 1 MSPS
TA = 25°C
V(+VBD) = 1.8 V
ƒsample = 1 MSPS
TA = 25°C
V(+VA) = 5.5 V
Figure 11. Offset Error vs Supply Voltage (V(+VA)
)
Figure 12. Offset Error vs Interface Supply Voltage (V(+VBD)
)
Copyright © 2014, Texas Instruments Incorporated
13
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
www.ti.com.cn
Typical Characteristics (12-Bit Devices Only) (continued)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves.
1
0.8
0.6
0.4
0.2
1
0.8
0.6
0.4
0.2
0
0
-0.2
-0.4
-0.6
-0.2
-0.4
-0.6
-0.8
-1
-0.8
-1
2.7
3.4
4.1
Supply Voltage (V)
4.8
5.5
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.5
Interface Supply (V)
ƒsample = 1 MSPS
TA = 25°C
V(+VBD) = 1.8 V
ƒsample = 1 MSPS
TA = 25°C
V(+VA) = 5.5 V
Figure 13. Gain Error vs Supply Voltage (V(+VA)
)
Figure 14. Gain Error vs Interface Supply Voltage (V(+VBD))
2
1
0.9
0.8
0.7
0.6
0.5
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.3
0.2
0.4
0.2
0
0.1
0
-40
15
70
125
-40
15 70
Free-Air Temperature (°C)
125
Free-Air Temperature (°C)
ƒsample = 1 MSPS
V(+VA) = 5.5 V
V(+VBD) = 1.8 V
ƒsample = 1 MSPS
V(+VA) = 5.5 V
V(+VBD) = 1.8 V
Figure 16. Gain Error vs Free-Air Temperature
Figure 15. Offset Error vs Free-Air Temperature
72
72
71.5
71
71.5
71
70.5
70.5
70
70
69.5
69
69.5
69
2.7
3.4
4.1
4.8
5.5
2.7
3.4
4.1
4.8
5.5
Supply Voltage (V)
Supply Voltage (V)
ƒsample = 1 MSPS
ƒinput = 100 kHz
TA = 25°C
V(+VBD) = 3 V
ƒsample = 1 MSPS
ƒinput = 100 kHz
TA = 25°C
V(+VBD) = 3 V
Figure 18. Signal-to-Noise With Distortion vs Supply Voltage
(V(+VA)
Figure 17. Signal-to-Noise Ratio vs Supply Voltage (+VA)
)
14
Copyright © 2014, Texas Instruments Incorporated
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
www.ti.com.cn
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
Typical Characteristics (12-Bit Devices Only) (continued)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves.
90
89
88
87
86
85
84
83
82
81
80
-80
-81
-82
-83
-84
-85
-86
-87
-88
-89
-90
2.7
3.4
4.1
Supply Voltage (V)
4.8
5.5
2.7
3.4
4.1
4.8
5.5
Supply Voltage (V)
ƒsample = 1 MSPS
ƒinput = 100 kHz
TA = 25°C
V(+VBD) = 3 V
ƒsample = 1 MSPS
ƒinput = 100 kHz
TA = 25°C
V(+VBD) = 3 V
Figure 20. Spurious-Free Dynamic Range (SFDR) vs Supply
Voltage (V(+VA)
Figure 19. Total Harmonic Distortion (THD) vs Supply
Voltage (V(+VA)
)
)
72
72
71.5
71.5
71
70.5
70
71
70.5
70
69.5
69
69.5
69
-40
15
70
125
-40
15
70
125
Free-Air Temperature (°C)
Free-Air Temperature (°C)
ƒsample = 1 MSPS
ƒinput = 100 kHz
V(+VA) = 5 V
V(+VBD) = 3 V
ƒsample = 1 MSPS
ƒinput = 100 kHz
V(+VA) = 5 V
V(+VBD) = 3 V
Figure 21. Signal-to-Noise Ratio vs Free-Air Temperature
Figure 22. Signal-to-Noise With Distortion vs Free-Air
Temperature
90
-80
-81
89
88
87
86
85
84
83
82
-82
-83
-84
-85
-86
-87
-88
-89
-90
81
80
-40
15
70
Free-Air Temperature (°C)
-40
15
70
125
125
Free-Air Temperature (°C)
ƒsample = 1 MSPS
ƒinput = 100 kHz
V(+VA) = 5 V
V(+VBD) = 3 V
ƒsample = 1 MSPS
ƒinput = 100 kHz
V(+VA) = 5 V
V(+VBD) = 3 V
Figure 23. Total Harmonic Distortion vs Free-Air
Temperature
Figure 24. Spurious-Free Dynamic Range vs Free-air
Temperature
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15
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ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
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Typical Characteristics (12-Bit Devices Only) (continued)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves.
73
72.5
72
73
72.5
72
71.5
71.5
71
70.5
70
71
70.5
70
69.5
69
69.5
69
10
30
50
70
90
110 130 150
10
30
50
70
90
110 130 150
Input Frequency (KHz)
Input Frequency (KHz)
ƒsample = 1 MSPS
TA = 25°C
V(+VA) = 5 V
V(+VBD) = 3 V
MXO shorted to AINP
ƒsample = 1 MSPS
TA = 25°C
V(+VA) = 5 V
V(+VBD) = 3 V
MXO shorted to AINP
Figure 25. Signal-to-Noise Ratio vs Input Frequency
Figure 26. Signal-to-Noise With Distortion vs Input
Frequency
-70
-72
-74
100
95
90
85
80
-76
-78
-80
-82
-84
-86
-88
-90
75
70
10
30
50
70
90
110 130 150
10
30
50
70
Input Frequency (KHz)
90
110 130 150
Input Frequency (KHz)
ƒsample = 1 MSPS
TA = 25°C
V(+VA) = 5 V
V(+VBD) = 3 V
ƒsample = 1 MSPS
TA = 25°C
V(+VA) = 5 V
V(+VBD) = 3 V
MXO shorted to AINP
MXO shorted to AINP
Figure 27. Total Harmonic Distortion vs Input Frequency
Figure 28. Spurious-Free Dynamic Range vs Input
Frequency
72
71.5
71
-70
10 Ω
-72
100 Ω
500 Ω
-74
1000 Ω
-76
-78
70.5
-80
-82
70
-84
-86
10 Ω
69.5
69
100 Ω
500 Ω
1000 Ω
-88
-90
20
40
60
80
100
20
40
60
80
100
Input Frequency (KHz)
Input Frequency (KHz)
ƒsample = 1 MSPS
TA = 25°C
V(+VA) = 5 V
V(+VBD) = 5 V
ƒsample= 1 MSPS
TA = 25°C
V(+VA) = 5 V
V(+VBD) = 5 V
Buffer between MXO and AINP
Buffer between MXO and AINP
Figure 29. Signal-to-Noise With Distortion vs Input
Frequency (Across Different Source Resistance Values)
Figure 30. Total Harmonic Distortion vs Input Frequency
(Across Different Source Resistance Values)
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Typical Characteristics (12-Bit Devices Only) (continued)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves.
90
1
0.8
0.6
0.4
0.2
0
DNL max
DNL min
88
86
84
82
80
78
76
74
72
70
-0.2
-0.4
-0.6
-0.8
-1
10 Ω
100 Ω
500 Ω
1000 Ω
0
5
10
Channel Number
15
20
40
60
80
Input Frequency (KHz)
100
ƒsample = 1 MSPS
V(+VA) = 5 V
V(+VBD) = 5 V
ƒsample = 1 MSPS
TA = 25°C
V(+VA) = 5 V
V(+VBD) = 5 V
Buffer between MXO and AINP
Figure 32. Differential Nonlinearity Variation Across
Channels
Figure 31. Spurious-Free Dynamic Range vs Input
Frequency (Across Different Source Resistance Values)
1
1.6
INL max
0.8
0.6
0.4
0.2
INL min
1.4
1.2
1
0.8
0
-0.2
-0.4
-0.6
0.6
0.4
0.2
0
-0.8
-1
0
5
10
15
20
0
5
10
Channel Number
15
Channel Number
V(+VA) = 5 V
ƒsample = 1 MSPS
V(+VA) = 5 V
V(+VBD) = 5 V
ƒsample = 1 MSPS
V(+VBD) = 5 V
Figure 33. Integral Nonlinearity Variation Across Channels
Figure 34. Offset-Error Variation Across Channels
0.25
73
72.5
72
0.2
0.15
0.1
71.5
71
0.05
0
70.5
70
0
5
10
15
20
1 2 3 4 5 6 7 8 9 10 11 12 1314 15 16
Channel Number
Channel Number
V(+VA) = 5 V
ƒsample = 1 MSPS
V(+VA) = 5 V
V(+VBD) = 5 V
ƒsample = 1 MSPS
V(+VBD) = 5 V
Figure 36. Signal-to-Noise Ratio Variation Across Channels
Figure 35. Gain-Error Variation Across Channels
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Typical Characteristics (12-Bit Devices Only) (continued)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves.
120
73
100
72.5
80
60
40
72
71.5
71
20
0
Isolation
Memory
70.5
70
0
50
100
150
200
250
1
2 3 4 5 6 7 8 9 10 11 12 1314 15 16
Channel Number
Input Frequency (KHz)
ƒsample = 1 MSPS
V(+VA) = 5 V
V(+VBD) = 5 V
ƒsample = 1 MSPS
CH0, CH1
V(+VA) = 5 V
V(+VBD) = 5 V
Figure 37. Signal-to-Noise With Distortion Variation Across
Channels
Figure 38. Crosstalk vs Input Frequency
25
100
VI = 2.5 V
90
VI = 1.25 V
VI = 0 V
80
20
70
60
15
10
50
40
30
20
10
0
5
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
0.25 0.5 0.75
1
1.25 1.5 1.75
2
TUE Max (LSB)
Free-Air Temperature (°C)
V(+VA) = 5 V
V(+VBD) = 5 V
Figure 40. Total Unadjusted Error (TUE) Maximum
Figure 39. Input Leakage Current vs Free-Air Temperature
25
20
15
10
5
0
TUE Min (LSB)
Figure 41. Total Unadjusted Error (TUE) Minimum
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1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
1024
2048
3072
4096
Code
ƒsample = 1 MSPS
TA = 25°C
V(+VA) = 5 V
V(+VBD) = 5 V
Figure 42. Differential Linearity (DNL) Error
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
4096
1024
2048
3072
0
Code
ƒsample = 1 MSPS
V(+VA) = 5 V
V(+VBD) = 5 V
Figure 43. Integral Linearity (INL) Error
0
-20
-40
-60
-80
-100
-120
-140
-160
500000
0
200000
300000
400000
100000
Frequency (Hz)
ƒsample = 1 MSPS
ƒinput = 100 kHz
V(+VA) = 5 V
Npoints = 16,384
V(+VBD) = 5 V
Figure 44. Power Spectrum
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8 Detailed Description
8.1 Overview
The ADS79xx-Q1 device is a high-speed, low-power analog-to-digital converter (ADC) with an 8-bit, 10-bit, and
12-bit multichannel successive-approximation register (SAR). The architecture of the device is based on charge
redistribution, which includes a sample and hold function. The ADS79xx-Q1 device uses an external reference
and an external serial clock (SCLK) to run the conversion.
The analog input is provided to the CHn input channel. The output of the multiplexer can be shorted directly or
can be connected thorough a buffer to the AINP pin. Because the AINM pin is shorted to AGND, when a
conversion is initiated, the differential input between the AINP and AGND pins is sampled on the internal
capacitor array. Two input ranges are supported. Users can program the input range to either 0 V to Vref or 0 V to
2 × Vref using the mode-control register. The same register can program the input channel sequencing.
The ADS79xx-Q1 device also has four general-purpose input and output (GPIO) pins that can be programmed
independently as either general-purpose output (GPO) or general-purpose Input (GPI) pins. GPIOs also support
alarm function for which high and low thresholds are programmable per channel.
8.2 Functional Block Diagram
+VA
MXO
AINP
REFP
+VBD
CH0
CH2
CH3
ADC
SDO
Compare
Alarm
threshold
SDI
CHn(1)
Control logic
and
sequencing
SCLK
CS
AGND
AINM
REFM
GPIO
BDGND
(1) n is number of channels (4, 8, 12, or 16) depending on the device from the ADS79xx-Q1 device family.
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8.3 Feature Description
8.3.1 Device Operation
Figure 45, Figure 46, Figure 47, and Figure 48 illustrate device operation timing. Device operation is controlled
with the CS, SCLK, and SDI pins. The device outputs data on the SDO pin.
Frame n
Frame n + 1
CS
SCLK
SDO
1
3
5
7
9
11
13
15 16
1
3
5
7
9
11
13
15 16
Top 4 Bit
Top 4 Bit
12-Bit Conversion Result
12-Bit Conversion Result
SDI
16-Bit I/P Word
16-Bit I/P Word
Mux Chan Change
Analog I/P Settling After Chan Change
Mux Chan Change
MUX
Sampling
Instance
Acquisition
Acquisition Phase tacq
Conversion
GPO
Conversion Phase tcnv
Data Written (through SDI) in Frame n
Conversion Phase
Data Written (through SDI) in Frame n – 1
GPI
GPI status is latched in on CS falling
edge and transferred to SDO frame n
Figure 45. Device Operation Timing Diagram
Each frame begins with the falling edge of the CS pin. With the falling edge of the CS pin, the input signal from
the selected channel is sampled, and the conversion process is initiated. The device outputs data while the
conversion is in progress. The 16-bit data word contains a 4-bit channel address, followed by a 12-bit conversion
result in most-significant-bit (MSB) first format. The GPIO status can be read instead of the channel address (see
Table 1, Table 2, and Table 5).
The device selects a new multiplexer channel on the second SCLK falling edge. The acquisition phase begins on
the 14th SCLK rising edge. On the next CS falling edge the acquisition phase ends, and the device starts a new
frame.
There are four general-purpose IO (GPIO) pins. These pins can be individually programmed as GPO or GPI.
Using these pins for preassigned functions is also possible (see Table 11). GPO data can be written into the
device through the SDI line. The device refreshes the GPO data on the CS falling edge according to the SDI
data written in previous frame.
Similarly the device latches the GPI status on the CS falling edge and outputs the GPI data on the SDO line (if
GPI read is enabled by writing DI04 = 1 in the previous frame) in the same frame starting with the CS falling
edge.
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Feature Description (continued)
a
1/t Throughput (Single Frame)
CS
tw1
tsu1
SCLK
SDO
SDI
3
4
13
DO-3
DI-3
16
DO-0
DI-0
1
2
5
6
12
th1
td3
td1
td2
DO-
15
DO-11 DO-10
MSB-1
DO-4
LSB
DO-14 DO-13 DO-12
MSB
tsu2
tq
DI-15
DI-14
DI-13
DI-12
DI-11
DI-10
DI-4
th2
Figure 46. Serial Interface Timing Diagram for 8-Bit Devices
(ADS7958, ADS7959, ADS7960, and ADS7961)
a
1/t Throughput (Single Frame)
CS
SCLK
SDO
SDI
tw1
tsu1
3
4
15
DO-1
DI-1
16
DO-0
DI-0
1
2
5
6
14
th1
td3
td1
td2
DO-
15
DO-11 DO-10
MSB-1
DO-2
LSB
DO-14 DO-13 DO-12
MSB
tsu2
tq
DI-15
DI-14
DI-13
DI-12
DI-11
DI-10
DI-2
th2
Figure 47. Serial Interface Timing Diagram for 10-Bit Devices (ADS7954, ADS7956, and ADS7957)
a
1/t Throughput (Single Frame)
CS
tw1
tsu1
SCLK
SDO
SDI
3
4
15
16
1
2
5
6
14
th1
td3
td1
td2
DO-
15
DO-11 DO-10
MSB-1
DO-2 DO-1
LSB+2 LSB+1
DO-0
LSB
DO-14 DO-13 DO-12
MSB
tsu2
tq
DI-1
DI-0
DI-15
DI-14
DI-13
DI-12
DI-11
DI-10
DI-2
th2
Figure 48. Serial Interface Timing Diagram for 12-Bit Devices
(ADS7950, ADS7951, ADS7952, and ADS7953)
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Feature Description (continued)
The falling edge of the CS pin clocks out the DO-15 bit (the first bit of the four bit channel address), and
remaining address bits are clocked out on every falling edge of SCLK until the third falling edge. The conversion
result MSB is clocked out on the fourth SCLK falling edge and LSB on the 11th, 13th, or 15th falling edge
respectively for 8-bit, 10-bit, or 12-bit devices. On the 16th falling edge of the SCLK pin, the SDO pin enters tri-
state condition. The conversion ends on the 16th falling edge of SCLK.
While the device outputs data on the SDO pin, a 16-bit word is read on the SDI pin. The SDI data are latched on
every rising edge of the SCLK pin beginning with the first clock; see Figure 46, Figure 47, and Figure 48.
The CS pin can be asserted (pulled high) only after 16 clocks have elapsed.
The device has two (high and low) programmable alarm thresholds per channel. If the input crosses these limits
the device flags out an alarm on the GPIO0 or GPIO1 pin depending on the GPIO-program register settings (see
Table 11). The alarm is asserted (under the alarm conditions) on the 12th falling edge of the SCLK pin in the
same frame when a data conversion is in progress. The alarm output is reset on the tenth falling edge of the
SCLK pin in the next frame.
8.3.2 Device Power-up Sequence
Figure 49 illustrates the device power-up sequence. Manual mode is the default power-up channel-sequencing
mode and channel-0 is the first channel by default. As explained previously, these devices offer program
registers to configure user-programmable features (such as GPIO, alarm, and to preprogram the channel
sequence for the auto modes). At power up or on reset, these registers are set to the default values listed in
Table 1 to Table 11. Program these registers on power up or after reset. When configured, the device is ready to
use in any of the three channel sequencing modes: manual, auto-1, and auto-2.
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Feature Description (continued)
Device power up or
reset
Device operation in
CS
manual mode,
First frame
channel-0.
SDO pin is invalid in
the first frame
Auto-1 register
program (see note A.)
CS
CS
Auto-2 register
program (see note A.)
Alarm register program
(see note A.)
CS
CS
GPIO register program
(see note A.)
Operation in
manual mode
CS
Operation in
auto-1 mode
Operation in
auto-2 mode
CS
CS
A. The device continues operation in manual-mode channel 0 throughout the programming sequence and outputs valid conversion results.
Changing the channel, range, or GPIO is possible by inserting extra frames in between two programming blocks. Bypassing any
programming block is also possible if that feature in not intended for use.
B. Reprogramming the device at any time during operation, regardless of what mode the device is in, is possible. During programming, the
device continues operation in whatever mode it is in and outputs valid data.
Figure 49. Device Power-Up Sequence
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Feature Description (continued)
8.3.3 Analog Input
The ADS79x-Q1 device family offers 8-bit, 10-bit, and 12-bit ADCs with 4-channel, 8-channel, 12-channel, 16-
channel multiplexers for analog input. The multiplexer output is available on the MXO pin. The AINP pin is the
ADC input pin. The devices offers flexibility for a system designer as both MXO and AINP are accessible
externally.
Figure 50 shows the equivalent circuit at the input and output of the multiplexer and the input of the converter
during sampling. When the converter enters hold mode, the input impedance at AINP is greater than 1 GΩ.
80 ꢀ
MXO
Ch0
200 ꢀ
5 pF AINP
3 pF
3 pF
7 pF
Chn
20 Mꢀ
Ch0 assumed to be on
Chn assumed to be off
Figure 50. ADC and MUX Equivalent Circuit
When the converter samples an input, the voltage difference between the AINP and AGND pins is captured on
the internal capacitor array. The peak input current through the analog inputs depends upon a number of factors
including sample rate, input voltage, and source impedance. The current into the ADS79xx-Q1 device charges
the internal capacitor array during the sample period. After this capacitance is fully charged, there is no further
input current.
To maintain the linearity of the converter, the Ch0 through Chn and AINP inputs must be within the input range
limits specified. Outside of these ranges, converter linearity may not meet specifications.
8.3.4 Reference
The ADS79xx-Q1 device can operate with an external 2.5-V ±10-mV reference. A clean, low-noise, well-
decoupled reference voltage on the REF pin is required to ensure good performance from the converter. A low-
noise, band-gap reference (such as the REF5025 device) can be used to drive this pin. A 10-μF ceramic
decoupling capacitor is required between the REF and GND pins of the converter. Place the capacitor as close
as possible to the device pins.
8.3.5 Power Saving
The ADS79xx-Q1 device offers a power-down feature to save power when not in use. There are two ways to
power down the device. The device can be powered down by writing the DI05 bit equal to 1 in the mode control
register (see Table 1, Table 2, and Table 5). In this case, the device powers down on the 16th falling edge of the
SCLK pin in the next data frame. Another way to power down the device is through the GPIO pins. The GPIO3
pin can act as a PD input (see Table 11 for assigning this functionality to the GPIO3 pin) which is an
asynchronous and active-low input. The device powers down instantaneously after the GPIO3 pin (PD) equals 0.
The device powers up again on the CS falling edge when the DI05 bit equals 0 in the mode control register, and
the GPIO3 pin (PD) equals 1.
8.4 Device Functional Modes
8.4.1 Channel Sequencing Modes
There are three modes for channel sequencing, including manual mode, auto-1 mode, and auto-2 mode. Mode
selection occurs by writing into the control register (see Table 1, Table 2, and Table 5). A new multiplexer
channel is selected on the second falling edge of SCLK (as shown in Figure 45) in all three modes.
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Device Functional Modes (continued)
Manual mode: When configured to operate in manual mode, the next selected channel is programmed in each
frame and the device selects the programmed channel in the next frame. On power up or after
reset the default channel is channel-0 and the device is in manual mode.
Auto-1 mode: In this mode the device scans pre-programmed channels in ascending order. A new multiplexer
channel is selected every frame on the second falling edge of the SCLK pin. A separate program
register preprograms the channel sequence. Table 3 and Table 4 show auto-1 program register
settings.
When programmed, the device retains the program register settings until the device is powered down, reset,
or reprogrammed. The device is allowed to exit and reenter the auto-1 mode any number of times without
disturbing the program register settings.
The auto-1 program register is reset to F, FF, FFF, or FFFF (hex) for the 4-channel, 8-channel, 12-channel,
or 16-channel devices, respectively, upon device power up or reset (implying the device scans all channels in
ascending order).
Auto-2 mode: In this mode the user can configure the program register to select the last channel in the scan
sequence. The device scans all channels from channel-0 up to, and including, the last channel in
ascending order. The multiplexer channel is selected every frame on the second falling edge of the
SCLK pin. A separate program register preprograms the last channel in the sequence (multiplexer
depth). Table 6 lists the auto-2 program register settings for selection of the last channel in the
sequence.
When programmed, the device retains the program register settings until the device is powered down, reset,
or reprogrammed. The device is allowed to exit and re-enter auto-2 mode any number of times, without
disturbing the program register settings.
On power up or reset, bits D9 to D6 of the auto-2 program register are reset to 3, 7, B, or F (hex) 4-channel,
8-channel, 12-channel or 16-channel devices, respectively (implying the device scans all channels in
ascending order).
8.4.2 Device Programming and Mode Control
The following sections describe device programming and mode control. The ADS79xx-Q1 device feature two
types of registers to configure and operate the devices in different modes. These registers are referred as
configuration registers. The two types of configuration registers are mode control registers and program registers.
8.4.2.1 Mode Control Register
A mode control register is configured to operate the device in one of three channel sequencing modes, either
manual mode, auto-1 mode, or auto-2 mode. This register is also used to control user programmable features,
such as range selection, device power-down control, GPIO read control, and writing output data into the GPIO
pins.
8.4.2.2 Program Registers
The program registers are used for device-configuration settings and are typically programmed once on power
up or after device reset. There are different program registers including auto-1 mode programming for
preprogramming the channel sequence, auto-2 mode programming for selection of the last channel in the
sequence, alarm programming for all 16 channels (or 4, 8 , or 12 channels depending on the device), and GPIO
for individual pin configuration, such as GPI or GPO or a preassigned function.
8.4.3 Operating In Manual Mode
Figure 51 illustrates details regarding entering and running in manual channel-sequencing mode. Table 1 lists the
mode control register settings for manual mode in detail. Note that there are no program registers for manual
mode.
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ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
Device Functional Modes (continued)
Device operation in auto-1 or auto-2 mode
CS
Frame: n – 1
No
Change to Manual mode?
Yes
•
Sample: Samples and converts the channel selected in frame n – 1
•Mux: Selects the channel incremented from the previous frame as per auto sequence.
This channel is acquired in this frame and sampled at the start of frame n + 1
•Range: As programmed in frame n – 1. Applies to the channel selected for acquisition in the
current frame.
•SDI: Programming for frame n + 1
DI15 to DI12 = 0001 binary. Selects manual mode
DI11 = 1 enables the programming of range and GPIO
DI10 to DI7 = binary address of the channel
DI6 - As per the required range for the channel to be selected
DI5 = 0 - No power down
CS
Frame: n
Request
for manual
mode
DI4 to DI0 - As per GPIO settings
•
•
SDO: DO15 to DO0 address (or GPIO data) and conversion data of the channel
selected in frame n – 1
GPIO:
O/P: Latched on the CS pin falling edge as per DI3 to DI0 written in frame n – 1
I/P: Input status latched on the falling edge of CS and transferred serially on the
SDO pin in the same frame
•
Sample: Samples and converts the channel selected in frame n
•Mux: Selects the channel in frame n (manual mode). This channel is acquired in this frame and
sampled at the start of frame n + 2
•Range: As programmed in frame n. Applies to the channel selected for acquisition in the
current frame.
•SDI: Programming for frame n + 2
DI15 to DI12 = 0001 binary. To continue in manual mode
DI11 = 1 enables the programming of range and GPIO
DI10 to DI7 = binary address of the channel
DI6 - As per the required range for the channel to be selected
DI5 = 0 - No power down
CS
Frame:
n + 1
DI4 to DI0 - As per GPIO settings
Entry into
manual
mode
•
•
SDO: DO15 to DO0 address (or GPIO data) and conversion data of the channel
selected in frame n
GPIO:
O/P: Latched on the CS pin falling edge as per DI3 to DI0 written in frame n
I/P: Input status latched on the falling edge of CS and transferred serially on the
SDO pin in the same frame
•
Sample: Samples and converts the channel selected in frame n + 1
•Mux: Selects the channel programmed in frame n + 1 (manual mode). This channel is
acquired in this frame and sampled at the start of frame n +3
•Range: As programmed in frame n + 1. Applies to the channel selected for acquisition in
the current frame.
•SDI: Programming for frame n + 3
DI15 to DI12 = 0001 binary. Selects manual mode
DI11 = 1 enables the programming of range and GPIO
DI10 to DI7 = binary address of the channel
DI6 - As per the required range for the channel to be selected
DI5 = 0 - No power down
CS
Frame:
n + 2
Operation
in manual
mode
DI4 to DI0 - As per GPIO settings
•
•
SDO: DO15 to DO0 address (or GPIO data) and conversion data of the channel
selected in frame n + 1
GPIO:
O/P: Latched on the CS pin falling edge as per DI3 to DI0 written in frame n + 1
I/P: Input status latched on the falling edge of CS and transferred serially on the
SDO pin in the same frame
CS
Continue operation in manual mode
Figure 51. Entering and Running in Manual Channel-Sequencing Mode
Copyright © 2014, Texas Instruments Incorporated
27
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
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Device Functional Modes (continued)
Table 1. Mode-Control Register Settings for Manual Mode
DESCRIPTION
RESET
STATE
LOGIC
STATE
BITS
DI15-12
DI11
FUNCTION
0001
0001
Selects manual mode
0
1
0
Enables programming of bits DI06 through DI00
Device retains values of bits DI06 through DI00 from the previous frame
DI10-07
0000
This 4-bit data represents the address of the next channel to be selected in the next frame. DI10 = MSB and DI07
= LSB.
For example, 0000 represents channel-0, 0001 represents channel-1, and so on.
DI06
DI05
DI04
0
0
0
0
1
0
1
Selects 2.5-V input range (range 1)
Selects 5-V input range (range 2)
Device normal operation (no power down)
Device powers down on 16th SCLK falling edge
The SDO pin outputs the current channel address of the channel on bits DO15 through DO12
followed by a 12-bit conversion result on bits DO11 through DI00.
0
1
The GPIO3 through GPIO0 data (both input and output) is mapped onto bits DO15 through DO12 in
the order shown below. Lower data bits DO11 through DO00 represent the 12-bit conversion result
of the current channel.
DOI5
DOI4
DOI3
DOI2
GPIO3
GPIO2
GPIO1
GPIO0
DI03-00
0000
The GPIO data for the channels configured as an output. The device ignores the data for the channel which is
configured as input. The SDI bit and corresponding GPIO information is given below.
DI03
DI02
DI01
DI00
GPIO3
GPIO2
GPIO1
GPIO0
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8.4.4 Operating In Auto-1 Mode
Figure 52 shows a flowchart containing the details regarding entering and running in auto-1 channel-sequencing
mode. Table 2 lists the mode control register settings for auto-1 mode in detail.
Device operation in manual or auto-2 mode
CS
Frame: n – 1
No
Change to auto-1 mode?
Yes
•
Sample: Samples and converts the channel selected in frame n – 1
•Mux: Selects the channel incremented from the previous frame as per the auto-2 sequence, or
channel programmed in the previous frame in case of manual mode. This channel is only acquired
in this frame and sampled at the start of frame n + 1
•Range: As programmed in frame n – 1. Applies to the channel selected for acquisition in the
current frame.
•SDI: Programming for frame n + 1
DI15 to DI12 = 0001 binary. Selects auto-1 mode
DI11 = 1 enables the programming of range and GPIO
DI10 = x. The device automatically resets the channel to the lowest number in auto-1 sequence
DI6 - As per the required range for the channel to be selected
DI5 = 0 - No power down
CS
Frame: n
Request
for auto-1
mode
DI4 to DI0 - As per GPIO settings
•SDO: DO15 to DO0 address (or GPIO data) and conversion data of the channel
selected in frame n – 1
•
GPIO:
O/P: Latched on the CS pin falling edge as per DI3 to DI0 written in frame n – 1
I/P: Input status latched on the falling edge of CS and transferred serially on the
SDO pin in the same frame
•
Sample: Samples and converts the channel selected in frame n
•Mux: Selects the lowest channel number in auto-1 sequence. This channel is acquired in
this frame and sampled at the start of frame n + 2
•Range: As programmed in frame n. Applies to the channel selected for acquisition in the
current frame.
•SDI: Programming for frame n + 2
DI15 to DI12 = 0001 binary. To continue in auto-1 mode
DI11 = 1 enables the programming of range and GPIO
DI10 = 0, not to reset the channel sequence
DI6 - As per the required range for the channel to be selected
DI5 = 0 - No power down
CS
Frame:
n + 1
DI4 to DI0 - As per GPIO settings
Entry into
auto-1
mode
•SDO: DO15 to DO0 address (or GPIO data) and conversion data of the channel
selected in frame n
•
GPIO:
O/P: Latched on the CS pin falling edge as per DI3 to DI0 written in frame n
I/P: Input status latched on the falling edge of CS and transferred serially on the
SDO pin in the same frame
•
Sample: Samples and converts the channel selected in frame n + 1
(for example, the lowest channel number in the auto-1 sequence)
•Mux: Selects the next highest channel in auto-1 sequence. This channel is acquired in this frame
and sampled at the start of frame n + 3
•Range: As programmed in frame n + 1. Applies to the channel selected for acquisition in the
current frame.
•SDI: Programming for frame n + 3
DI15 to DI12 = 0001 binary. To continue in auto-1 mode
DI11 = 1 enables the programming of range and GPIO
DI10 = 0 not to reset the channel sequence
DI6 - As per the required range for the channel to be selected
DI5 = 0 - No power down
CS
Frame:
n + 2
Operation
in auto-1l
mode
DI4 to DI0 - As per GPIO settings
•SDO: DO15 to DO0 address (or GPIO data) and conversion data of the channel
selected in frame n + 1
•
GPIO:
O/P: Latched on the CS pin falling edge as per DI3 to DI0 written in frame n + 1
I/P: Input status latched on the falling edge of CS and transferred serially on the
SDO pin in the same frame
CS
Continue operation in auto-1 mode
Figure 52. Entering and Running in Auto-1 Channel-Sequencing Mode
Copyright © 2014, Texas Instruments Incorporated
29
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
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Table 2. Mode-Control Register Settings for Auto-1 Mode
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12
DI11
0001
0010
Selects auto-1 mode
0
1
Enables programming of bits DI10 through DI00
0
Device retains values of bits DI10 through DI00 from previous frame
DI10
0
1
The channel counter is reset to the lowest programmed channel in the auto-1 program register
The channel counter increments every conversion (no reset)
Do not care
0
DI09-07
DI06
000
0
xxx
0
Selects 2.5-V input range (range 1)
1
Selects 5-V input range (range 2)
DI05
DI04
0
0
0
Device normal operation (no powerdown)
1
Device powers down on the 16th SCLK falling edge
SDO outputs current channel address of the channel on DO15..12 followed by 12-bit conversion
result on DO11 through DO00.
0
1
The GPIO3 to GPIO0 data (both input and output) is mapped onto DO15 through DO12 in the order
shown below. Lower data bits DO11 through DO00 represent the 12-bit conversion result of the
current channel.
DO15
DO14
DO13
DO12
GPIO3
GPIO2
GPIO1
GPIO0
DI03-00
0000
The GPIO data for the channels configured as an output. The device ignores the data for the channel which is
configured as input. The SDI bit and corresponding GPIO information is given below
DI03
DI02
DI01
DI00
GPIO3
GPIO2
GPIO1
GPIO0
The auto-1 program register is programmed (once on power up or reset) to preselect the channels for the auto-1
sequence, as shown in Figure 53. The auto-1 program-register programming requires two CS frames for
complete programming. In the first CS frame, the device enters the auto-1 register programming sequence, and
in the second frame the device programs the auto-1 program register. For complete details see Table 2, Table 3,
and Table 4.
30
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ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
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ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
Device in any
operation mode
CS
No
Program auto 1
register?
Yes
SDI:
DI15 to DI12 = 1000
(The device enters
auto-1 programming
sequence)
CS
Entry into auto-1
register
programming
sequence
SDI: DI15 to DI0
(see note A.)
CS
Auto-1 register
programming
End of auto-1 register
programming
A. Per Table 3 and Table 4.
B. The device continues operation in the selected mode during programming. The SDO pin is valid, however changing the range or writing
the GPIO data into the device during programming is not possible.
Figure 53. Auto-1 Register Programming Flowchart
Table 3. Program Register Settings for Auto-1 Mode
DESCRIPTION
FUNCTION
RESET
STATE
BITS
LOGIC STATE
FRAME 1
DI15-12
NA
1000
The device enters auto-1 program sequence. Device programming occurs in the next
frame.
DI11-00
FRAME 2
DI15-00
NA
Do not care
All 1's
1 (individual bit)
A particular channel is programmed to be selected in the channel scanning sequence. The
channel numbers are mapped one-to-one with respect to the SDI bits.
For example, DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00
A particular channel is programmed to be skipped in the channel scanning sequence. The
channel numbers are mapped one-to-one with respect to the SDI bits.
For example, DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00
0 (individual bit)
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ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
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Table 4. Mapping of Channels to SDI Bits
DEVICE(1)
SDI BITS
DI15 DI14 DI13 DI12 DI11 DI10 DI09 DI08 DI07 DI06 DI05 DI04 DI03 DI02 DI01 DI00
4 Channel
8 Channel
12 Channel
16 Channel
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
X
X
X
X
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
(1) When operating in auto-1 mode, the device only scans the channels programmed to be selected.
8.4.5 Operating In Auto-2 Mode
Figure 54 illustrates the details regarding entering and running in auto-2 channel-sequencing mode. Table 5 lists
the mode-control register settings for auto-2 mode in detail.
Table 5. Mode-Control Register Settings for Auto-2 Mode
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12
DI11
0001
0011
Selects auto-2 mode
0
1
Enables programming of bits DI10 through DI00
The device retains values of DI10 through DI00 from the previous frame
The channel number is reset to Ch-00
0
DI10
0
1
0
The channel counter increments every conversion (no reset)
Do not care
DI09-07
DI06
000
0
xxx
0
Selects 2.5-V input range (range 1)
1
Selects 5-V input range (range 2)
DI05
DI04
0
0
0
Device normal operation (no powerdown)
The device powers down on the 16th SCLK falling edge
1
The SDO pin outputs the current channel address of the channel on bits DO15 through DO12
followed by the 12-bit conversion result on bits DO11 through DO00.
0
1
The GPIO3 to GPIO0 data (both input and output) is mapped onto bits DO15 through DO12 in the
order shown below. Lower data bits DO11 through DO00 represent the 12-bit conversion result of the
current channel.
DO15
DO14
DO13
DO12
GPIO3
GPIO2
GPIO1
GPIO0
DI03-00
0000
The GPIO data for the channels configured as an output. The device ignores data for the channel that is
configured as input. The SDI bit and corresponding GPIO information is given below.
DI03
DI02
DI01
DI00
GPIO3
GPIO2
GPIO1
GPIO0
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Device operation in manual or auto-1 mode
CS
Frame: n – 1
No
Change to auto-2 mode?
Yes
•
Sample: Samples and converts the channel selected in frame n – 1
•Mux: Selects the channel incremented from the previous frame as per the auto-1 sequence, or
channel programmed in the previous frame in case of manual mode. This channel is acquired
in this frame and sampled at the start of frame n + 1
•Range: As programmed in frame n – 1. Applies to the channel selected for acquisition in the
current frame.
•SDI: Programming for frame n + 1
DI15 to DI12 = 0001 binary. Selects auto-2 mode
DI11 = 1 enables the programming of range and GPIO
DI10 = x. The device automatically resets to channel-0
DI6 - As per the required range for the channel to be selected
DI5 = 0 - No power down
CS
Frame: n
Request
for auto-2
mode
DI4 to DI0 - As per GPIO settings
•SDO: DO15 to DO0 address (or GPIO data) and conversion data of the channel
selected in frame n – 1
•
GPIO:
O/P: Latched on the CS pin falling edge as per DI3 to DI0 written in frame n – 1
I/P: Input status latched on the falling edge of CS and transferred serially on the
SDO pin in the same frame
•
Sample: Samples and converts the channel selected in frame n
•Mux: Selects the channel0 in auto-1 sequenc. This channel is acquired in
this frame and sampled at the start of frame n + 2
•Range: As programmed in frame n. Applies to the channel selected for acquisition in the
current frame.
•SDI: Programming for frame n + 2
DI15 to DI12 = 0001 binary. To continue in auto-2 mode
DI11 = 1 enables the programming of range and GPIO
DI10 = 0, not to reset the channel sequence
DI6 - As per the required range for the channel to be selected
DI5 = 0 - No power down
CS
Frame:
n + 1
DI4 to DI0 - As per GPIO settings
Entry into
auto-2
mode
•SDO: DO15 to DO0 address (or GPIO data) and conversion data of the channel
selected in frame n
•
GPIO:
O/P: Latched on the CS pin falling edge as per DI3 to DI0 written in frame n
I/P: Input status latched on the falling edge of CS and transferred serially on the
SDO [om in the same frame
•
Sample: Samples and converts to channel-0
(for example, the lowest channel number in the auto-1 sequence)
•Mux: Selects the next highest channel in auto-2 sequence. This channel is acquired in this frame
and sampled at the start of frame n + 3
•Range: As programmed in frame n + 1. Applies to the channel selected for acquisition in the
current frame.
•SDI: Programming for frame n + 3
DI15 to DI12 = 0001 binary. To continue in auto-2 mode
DI11 = 1 enables the programming of range and GPIO
DI10 = 0 not to reset the channel sequence
DI6 - As per the required range for the channel to be selected
DI5 = 0 - No power down
CS
Frame:
n + 2
Operation
in auto-2
mode
DI4 to DI0 - As per GPIO settings
•SDO: DO15 to DO0 address (or GPIO data) and conversion data of the channel
selected in frame n + 1
•
GPIO:
O/P: Latched on the CS pin falling edge as per DI3 to DI0 written in frame n + 1
I/P: Input status latched on the falling edge of CS and transferred serially on the
SDO pin in the same frame
CS
Continue operation in auto-2 mode
Figure 54. Entering and Running in Auto-2 Channel-Sequencing Mode
Copyright © 2014, Texas Instruments Incorporated
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ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
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The auto-2 program register is programmed (once on power up or reset) to preselect the last channel (or
sequence depth) in the auto-2 sequence. Unlike auto-1 program-register programming, auto-2 program-register
programming requires only one CS frame for complete programming. Figure 55 and Table 6 provide complete
details.
Device in any
operation mode
CS
No
Program auto 2
register?
Yes
SDI:
DI15 to DI12 = 1001
DI9 to DI6 = binary
address of last channel
in the sequence
(see note A.)
CS
Auto 2 register
programming
End of auto-2 register
programming
A. See Table 6.
B. The device continues operation in the selected mode during programming. The SDO pin is valid, however changing the range or writing
the GPIO data into the device during programming is not possible.
Figure 55. Auto-2 Register Programming Flowchart
Table 6. Program Register Settings for Auto-2 Mode
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12
DI11-10
DI09-06
NA
1001
The auto-2 program register is selected for programming
NA
NA
Do not care
aaaa
This 4-bit data represents the address of the last channel in the scanning sequence. During device
operation in auto-2 mode, the channel counter begins at CH-00 and increments every frame until
the counter equals aaaa. The channel counter then rolls over to CH-00 in the next frame.
DI05-00
NA
Do not care
8.4.6 Continued Operation In A Selected Mode
When a device is programmed to operate in one of the modes, the user can continue to operate in the same
mode. Table 7 lists mode-control register settings to continue operating in a selected mode.
Table 7. Continued Operation in a Selected Mode
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12
0001
0000
The device continues to operate in the selected mode. In auto-1 and auto-2 modes the channel
counter increments normally, whereas in the manual mode the device continues with the last
selected channel. The device ignores data on bits DI11-DI00 and continues operating as per the
previous settings. This feature is provided so that the SDI pin can be held low when no changes are
required in the mode-control register settings.
DI11-00
All 0
The device ignores these bits when bit DI15-12 is set to 0000 logic state
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8.5 Digital Output Code
As discussed previously in the Device Operation section, the digital output of the ADS79xx-Q1 devices is SPI™
compatible. Table 8, Table 9, and Table 10 list the output codes corresponding to various analog input voltages.
Table 8. Ideal Input Voltages and Output Codes for 8-Bit Devices
(ADS7958, ADS7959, ADS7960, and ADS7961)
DIGITAL OUTPUT
STRAIGHT BINARY
DESCRIPTION
Full-scale range
ANALOG VALUE
BINARY CODE
HEX CODE
Range 1 → Vref
Vref / 256
Range 2 → 2 × Vref
—
—
—
Least-significant bit (LSB)
Full scale
2 × Vref / 256
2 × Vref – 1 LSB
Vref
—
Vref – 1 LSB
Vref / 2
1111 1111
1000 0000
0111 1111
0000 0000
FF
80
7F
00
Midscale
Midscale – 1 LSB
Zero
Vref / 2 – 1 LSB
0 V
Vref – 1 LSB
0 V
Table 9. Ideal Input Voltages and Output Codes for 10-Bit Devices
(ADS7958, ADS7959, ADS7960, and ADS7961)
DIGITAL OUTPUT
STRAIGHT BINARY
DESCRIPTION
ANALOG VALUE
BINARY CODE
HEX CODE
Full-scale range
Least-significant bit (LSB)
Full scale
Range 1 → Vref
Vref / 1024
Vref – 1 LSB
Vref / 2
Range 2 → 2 × Vref
—
—
2 × Vref / 1024
2 Vref – 1 LSB
Vref
—
—
11 1111 1111
10 0000 0000
01 1111 1111
00 0000 0000
3FF
200
1FF
000
Midscale
Midscale – 1 LSB
Zero
Vref / 2 – 1 LSB
0 V
Vref – 1 LSB
0 V
Table 10. Ideal Input Voltages and Output Codes for 12-Bit Devices
(ADS7950, ADS7951, ADS7952, and ADS7953)
DIGITAL OUTPUT
STRAIGHT BINARY
DESCRIPTION
ANALOG VALUE
BINARY CODE
HEX CODE
Full-scale range
Least-significant bit (LSB)
Full scale
Range 1 → Vref
Vref / 4096
Vref – 1 LSB
Vref / 2
Range 2 → 2 × Vref
—
—
—
2 × Vref / 4096
2 × Vref – 1 LSB
Vref
—
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
FFF
800
7FF
000
Midscale
Midscale – 1 LSB
Zero
Vref / 2 – 1 LSB
0 V
Vref – 1 LSB
0 V
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8.6 Programming: GPIO
8.6.1 GPIO Registers
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The device has four general-purpose input and output (GPIO) pins. Each of the four pins can be independently
programmed as general purpose output (GPO) or general purpose input (GPI). Using the GPIOs pins for some
preassigned functions (see Table 11) is possible. The GPO data can be written into the device through the SDI
line. The device refreshes the GPO data on every CS falling edge as per the SDI data written in the previous
frame. Similarly, the device latches the GPI status on the CS falling edge and outputs it on the SDO pin (if the
GPI pin is read-enabled by writing bit DI04 equal to 1 during the previous frame) in the same frame starting on
the CS falling edge.
Figure 56 shows the details regarding programming the GPIO registers. Table 11 lists the details regarding
GPIO-register programming settings.
Device in any
operation mode
CS
No
Program GPIO
register?
Yes
SDI:
DI15 to DI12 = 0100
(see note A.)
CS
GPIO register
programming
End of GPIO register
programming
A. See Table 12 for DI11 to DI00 data.
B. The device continues its operation in selected mode during programming. SDO is valid, however changing the range or writing GPIO data
into the device during programming is not possible.
Figure 56. GPIO Program-Register Programming Flowchart
36
Copyright © 2014, Texas Instruments Incorporated
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
www.ti.com.cn
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
Programming: GPIO (continued)
Table 11. GPIO Program-Register Settings
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12 NA
DI11-10 00
0100
00
The device selects GPIO program registers for programming.
Do not program these bits to any logic state other than 00.
DI09
0
1
The device resets all registers in the next CS frame to the reset state shown in the corresponding tables
(the device also resets itself).
0
Device normal operation.
DI08
DI07
0
0
1
The device configures the GPIO3 pin as the device power-down input.
The GPIO3 pin remains a general-purpose input or output.
The device configures the GPIO2 pin as a device-range input.
The GPIO2 pin remains a general-purpose input or output.
The GPIO1 and GPIO0 pins remain a general-purpose input or output.
0
1
0
DI06-04 000
000
xx1
The device configures the GPIO0 pin as a high-alarm or low-alarm output. This output is active high.
GPIO1 remains general-purpose input or output.
010
100
110
The device configures GPIO0 as a high-alarm output. This output is active high. The GPIO1 pin remains a
general-purpose input or output.
The device configures GPIO1 as a low-alarm output. This output is active high. The GPIO0 pin remains a
general-purpose input or output.
The device configures GPIO1 as a low-alarm output and the GPIO0 pin as a high-alarm output. These
outputs are active high.
Note: The following settings are valid for the GPIO pins that are not assigned a specific function through bits DI08 to DI04
DI03
DI02
DI01
DI00
0
0
0
0
1
0
1
0
1
0
1
0
The GPIO3 pin is configured as general-purpose output.
The GPIO3 pin is configured as general-purpose input.
The GPIO2 pin is configured as general-purpose output.
The GPIO2 pin is configured as general-purpose input.
The GPIO1 pin is configured as general-purpose output.
The GPIO1 pin is configured as general-purpose input.
The GPIO0 pin is configured as general-purpose output.
The GPIO0 pin is configured as general-purpose input.
8.6.2 Alarm Thresholds for GPIO Pins
Each channel has two alarm program registers, one for setting the high alarm threshold and the other for setting
the low alarm threshold. For ease of programming, two alarm programming registers per channel, corresponding
to four consecutive channels, are assembled into one group (a total of eight registers). There are four of these
groups for 16-channel devices, and one, two or three of these groups for the 12-, 8-, or 4-channel devices,
respectively. Table 12 lists the grouping of the various channels for each device in the ADS79xx-Q1 family.
Figure 57 illustrates the details regarding programming the alarm thresholds. Table 13 lists the details regarding
the alarm-program register settings.
Table 12. Grouping of Alarm Program Registers
GROUP
NUMBER
REGISTERS
APPLICABLE FOR DEVICE
0
High and low alarm for channel 0, 1, 2, and 3
ADS750, ADS7952, ADS7951, and ADS7953; ADS7954, ADS7956,
and ADS7957; ADS7958, ADS7959, ADS7960, and ADS7961
1
2
3
High and low alarm for channel 4, 5, 6, and 7
High and low alarm for channel 8, 9, 10, and 11
High and low alarm for channel 12, 13, 14, and 15
ADS7951, ADS7952, and ADS7953; ADS7956, and ADS7957;
ADS7959, ADS7960, and ADS7961
ADS7953 and ADS7952, ADS7957 and ADS7956, ADS7961 and
ADS7960
ADS7953, ADS7957, and ADS7961
Copyright © 2014, Texas Instruments Incorporated
37
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
www.ti.com.cn
Each alarm group requires nine CS frames for programming the respective alarm thresholds. In the first frame
the device enters the programming sequence and in each subsequent frame the device programs one of the
registers from the group. The device offers a feature to program less than eight registers in one programming
sequence. The device exits the alarm threshold programming sequence in the next frame after encountering the
first exit alarm program bit high.
Device in any operation
mode
CS
No
Program alarm
thresholds?
Yes
SDI:
DI15 to DI12 = 11xx
(see note A.)
Device enters alarm
register programming
sequence
CS
Entry into alarm-
register
programming
sequence
SDI: DI15 to 0
(see note B.)
CS
Alarm-register
programming
sequence
No
Yes
DI12 = 1?
Yes
Program
another group
of four channels?
No
End of alarm
programing
A. xx indicates a group of four channels (see Table 12).
B. Per Table 12.
C. The device continues operation in the selected mode during programming. The SDO pin is valid, however changing the range or writing
the GPIO data into the device during programming is not possible.
Figure 57. Alarm Program Register Programming Flowchart
38
Copyright © 2014, Texas Instruments Incorporated
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
www.ti.com.cn
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
Table 13. Alarm Program Register Settings
DESCRIPTION
BITS
RESET STATE
LOGIC
STATE
FUNCTION
FRAME 1
1100
1101
1110
1111
The device enters alarm programming sequence for group 0
The device enters alarm programming sequence for group 1
The device enters alarm programming sequence for group 2
The device enters alarm programming sequence for group 3
DI15-12 NA
Note: Bits DI15-12 = 11bb is the alarm programming request for group bb. Here, bb represents the alarm programming group number in
binary format.
DI11-14 NA
Do not care
FRAME 2 AND ONWARDS
cc
Where cc represents the lower two bits of the channel number in binary format. The device
programs the alarm for the channel represented by the binary number bbcc. Note that bb is
programmed in the first frame.
DI15-14 NA
1
0
0
1
High-alarm register selection
DI13
DI12
NA
NA
Low-alarm register selection
Continue alarm programming sequence in next frame
Exit alarm programming in the next frame. Note: If the alarm programming sequence is not
terminated using this feature then the device remains in the alarm programming sequence state
and all SDI data is treated as alarm thresholds.
DI11-10 NA
All ones for high
xx
Do not care
This 10-bit data represents the alarm threshold. The 10-bit alarm threshold is compared with the upper 10-bit
word of the 12-bit conversion result. The device sets off an alarm when the conversion result is higher (high
alarm) or lower (low alarm) than this number. For 10-bit devices, all 10 bits of the conversion result are
compared with the set threshold. For 8-bit devices, all 8 bits of the conversion result are compared with DI09
to DI02 and DI00 and DI01 are do not care.
alarm register
DI09-00
and all zeros for
low alarm register
Copyright © 2014, Texas Instruments Incorporated
39
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
9 Application and Implementation
9.1 Application Information
www.ti.com.cn
In general applications, when the internal multiplexer is updated, the previously converted channel charge is
stored in the 15-pF internal input capacitance that disturbs the voltage at the newly selected channel. This
disturbance is expected to settle to 1 LSB during sampling (acquisition) time to avoid degrading converter
performance. The initial absolute disturbance error at the channel input must be less than 0.5 V to prevent
source current saturation or slewing that causes significantly long settling times. Fortunately, significantly
reducing disturbance error is easy to accomplish by simply placing a large enough capacitor at the input of each
channel. Specifically, with a 150-pF capacitor, instantaneous charge distribution keeps disturbance error below
0.46 V because the internal input capacitance can only hold up to 75 pC (or 5 V × 15 pF). The remaining error
must be corrected by the voltage source at each input, with impedance low enough to settle within 1 LSB. The
following application examples explain the considerations for the input source impedance (RSOURCE).
9.2 Typical Applications
9.2.1 Unbuffered Multiplexer Output (MXO)
This application is the most typical application, but requires the lowest RSOURCE for good performance. In this
configuration, the 2xREF range allows larger source impedance than the 1xREF range because the 1xREF
range LSB size is smaller, thus making it more sensitive to settling error.
AINP
MXO
RSOURCE
GPIO 0
GPIO 1
Ch0
Ch1
Chn
150 pF
RSOURCE
GPIO 2
GPIO 3
To
Host
See
SDO
SDI
SCLK
150 pF
RSOURCE
Note A
ADC
CS
150 pF
REF
o/p
REF5025
10 PF
A. A restriction on the source impedance exists. RSOURCE ≤ 100 Ω for the 1xREF 12-bit settling at 1 MSPS or RSOURCE ≤ 250 Ω for the
1xREF 12-bit settling at 1 MSPS .
Figure 58. Application Diagram for an Unbuffered MXO
9.2.1.1 Design Requirements
The design is optimized to show the input source impedance (RSOURCE) between the 100 Ω to 10,000 Ω required
to meet the 1-LSB settling at 12-bit, 10-bit, and 8-bit resolutions at different throughput in 1xREF (2.5-V) and
2xREF (5-V) input ranges.
9.2.1.2 Detailed Design Procedure
Although the required input source impedance can be estimated assuming a 0.5-V initial error and exponential
recovery during sampling (acquisition) time, this estimation over-simplifies the complex interaction between the
converter and source, thus yielding inaccurate estimates. Thus, this design uses an iterative approach with the
converter itself to provide reliable impedance values.
To determine the actual maximum source impedance for a particular resolution and sampling rate, two
subsequent channels are set at least 95% of the full-scale range apart. With a 1xREF range and 2.5 Vref, the
channel difference is at least 2.375 V. With 2xREF and 2.5 Vref, the difference is at least 4.75 V. With a source
impedance between 100 Ω to 10,000 Ω, the conversion runs at a constant rate and a channel update is issued
that captures the first couple samples after the update. This process is repeated at least 100 times to remove
any noise and to show a clear settling error. The first sample after the channel update is then compared against
the second one. If the first and second samples are more than 1 LSB apart, throughput rate is reduced until the
settling error becomes 1 LSB, which then sets the maximum throughput for the selected impedance. The whole
process is repeated for nine different impedances between 100 Ω to 10,000 Ω.
40
Copyright © 2014, Texas Instruments Incorporated
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
www.ti.com.cn
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
Typical Applications (continued)
9.2.1.3 Application Curves
These curves show the RSOURCE for an unbuffered MXO.
1000
1000
900
800
700
600
500
400
300
200
100
0
12-bit
10-bit
12-bit
10-bit
8-bit
900
8-bit
800
700
600
500
400
300
200
100
0
100
1000
10000
100
1000
10000
Rsource (:)
Rsource (:)
D1001
D101
Figure 59. 2xREF Input Range Settling without an
MXO Buffer
Figure 60. 1xREF Input Range Settling without an
MXO Buffer
9.2.2 OPA192 Buffered Multiplexer Output (MXO)
The use of a buffer relaxes the RSOURCE requirements to an extent. Charge from the sample-and-hold capacitor
no longer dominates as a residual charge from a previous channel. Although having good performance is
possible with a larger impedance using the OPA192, the output capacitance of the MXO also holds the previous
channel charge and cannot be isolated, which limits how large the input impedance can finally be for good
performance. In this configuration, the 1xREF range allows slightly higher impedance because the OPA192
(20 V/µs) slews approximately 2.5 V in contrast to the 2xREF range that requires the OPA192 to slew
approximately 5 V.
5V
+
OPA192
-
100ꢀꢀ
150pF
AINP
MXO
RSOURCE
GPIO 0
GPIO 1
Ch0
Ch1
Chn
150 pF
RSOURCE
GPIO 2
GPIO 3
To
Host
See
SDO
SDI
SCLK
150 pF
RSOURCE
Note A
ADC
REF
CS
150 pF
REF5025
o/p
10 PF
A. Restriction on the source impedance exists. R(SOURCE) ≤ 500 Ω for a 12-bit settling at 1 MSPS with both 1xREF and 2xREF ranges.
Figure 61. Application Diagram for an OPA192 Buffered MXO
9.2.2.1 Design Requirements
The design is optimized to show the input source impedance (RSOURCE) between the 100 Ω to 10,000 Ω required
to meet a 1-LSB settling at 12-bit, 10-bit, and 8-bit resolutions at different throughput in 1xREF (2.5 V) and
2xREF (5 V) input ranges.
Copyright © 2014, Texas Instruments Incorporated
41
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
www.ti.com.cn
Typical Applications (continued)
9.2.2.2 Detailed Design Procedure
The design procedure is similar to the unbuffered-MXO application, but includes an operation amplifier in unity
gain as a buffer. The most important parameter for multiplexer buffering is slew rate. The amplifier must finish
slewing before the start of sampling (acquisition) to keep the buffer operating in small-signal mode during
sampling (acquisition) time. Also, between the buffer output and converter input (INP), there must be a capacitor
large enough to keep the buffer in small-signal operation during sampling (acquisition) time. Because 150 pF is
large enough to protect the buffer form hold charge from internal capacitors, this value selected along with the
lowest impedance that allows the op amp to remain stable.
The converter allows the MXO to settle approximately 600 ns before sampling. During this time, the buffer slews
and then enters small-signal operation. For a 5-V step change, slew rate stays constant during the first 4 V. The
last 1 V includes a transition from slewing and non-slewing. Thus, the buffer cannot be assumed to keep a
constant slew during the 600 ns available for MXO settling. Assuming that the last 1-V slew is reduced to half is
recommended. For this reason, slew is 10 V/µs or (5 Vref + 1 V) / 0.6 µs to account for the 1-V slow slew. The
OPA192 has a 20-V/us slew, and is capable of driving 150 pF with more than a 50° phase margin with a 50-Ω or
100-Ω Riso, making the OPA192 an ideal selection for the ADS79xx-Q1 family of converters.
9.2.2.3 Application Curves
These curves show the RSOURCE for an OPA192 buffered MXO.
1000
900
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
12-bit
10-bit
8-bit
12-bit
10-bit
8-bit
100
1000
10000
100
1000
10000
Rsource (:)
Rsource (:)
D102
D103
Figure 62. 2xREF Input Range Settling with an
OPA192 MXO Buffer
Figure 63. 1xREF Input Range Settling with an
OPA192 MXO Buffer
9.3 Do's and Don'ts
•
•
•
Use capacitors to decouple the dynamic current transients at each pins, including reference, supply, and input
signal.
Do not place capacitors on the MXO pin. This placement causes issues with the signal settling when the
multiplexer changes channels.
Depending on the PCB layout, there can be parasitic inductance on the SCLK trace that causes ringing. To
minimize ringing, do not place a capacitor at the SCLK pin. Instead, place a small resistor in series with the
SCLK pin to slow down the clock edges.
10 Power-Supply Recommendations
The devices are designed to operate from an analog supply voltage (V(+VA)) range between 2.7 V and 5.25 V and
a digital supply voltage (V(+VBD)) range between 1.7 V and 5.25 V. Both supplies must be well regulated. The
analog supply is always greater than or equal to the digital supply. A 1-µF ceramic decoupling capacitor is
required at each supply pin and must be placed as close as possible to the device.
42
Copyright © 2014, Texas Instruments Incorporated
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
www.ti.com.cn
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
11 Layout
11.1 Layout Guidelines
•
A copper fill area underneath the device ties the AGND, BDGND, AINM, and REFM pins together. This
copper fill area must also be connected to the analog ground plane of the PCB using at least four vias.
•
The power sources must be clean and properly decoupled by placing a capacitor close to each of the three
supply pins, as shown in Figure 64. To minimize ground inductance, ensure that each capacitor ground pin is
connected to a grounding via by a very short and thick trace.
•
•
The REFP pin requires a 10-μF ceramic capacitor to meet performance specifications. Place the capacitor
directly next to the device. This capacitor ground pin must be routed to the REFM pin by a very short trace,
as shown in Figure 64.
Do not place any vias between a capacitor pin and a device pin.
NOTE
The full-power bandwidth of the converter makes the ADC sensitive to high frequencies in
digital lines. Organize components in the PCB by keeping digital lines apart from the
analog signal paths. This design configuration is critical to minimize crosstalk. For
example, in Figure 64, input drivers are expected to be on the left of the converter and the
microcontroller on the right.
11.2 Layout Example
Analog Inputs
1 µF
10 µF
Pin 1
GPIO
Analog Ground
1 µF
+VBD
GPIO
SPI
1 µF
Analog Inputs
Figure 64. Layout Example
版权 © 2014, Texas Instruments Incorporated
43
ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1
ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1
ZHCSCF3A –MAY 2014–REVISED AUGUST 2014
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
REF5025 数据表，SBOS410
OPA192 数据表，SBOS620
12.2 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 14. 相关链接
部件
产品文件夹
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请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
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请单击此处
请单击此处
请单击此处
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ADS7950-Q1
ADS7951-Q1
ADS7952-Q1
ADS7953-Q1
ADS7954-Q1
ADS7956-Q1
ADS7957-Q1
ADS7958-Q1
ADS7959-Q1
ADS7960-Q1
ADS7961-Q1
12.3 商标
SPI is a trademark of Motorola Inc.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
44
版权 © 2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7950QDBTRQ1
ADS7951QDBTRQ1
ADS7952QDBTRQ1
ADS7953QDBTRQ1
ADS7954QDBTRQ1
ADS7956QDBTRQ1
ADS7957QDBTRQ1
ADS7958QDBTRQ1
ADS7959QDBTRQ1
ADS7960QDBTRQ1
ADS7961QDBTRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
30
30
38
38
30
38
38
30
30
38
38
2000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ADS7950Q
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ADS7951Q
ADS7952Q
ADS7953Q
ADS7954Q
ADS7956Q
ADS7957Q
ADS7958Q
ADS7959Q
ADS7960Q
ADS7961Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7950QDBTRQ1
ADS7951QDBTRQ1
ADS7952QDBTRQ1
ADS7953QDBTRQ1
ADS7954QDBTRQ1
ADS7956QDBTRQ1
ADS7957QDBTRQ1
ADS7958QDBTRQ1
ADS7959QDBTRQ1
ADS7960QDBTRQ1
ADS7961QDBTRQ1
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
30
30
38
38
30
38
38
30
30
38
38
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
6.95
6.95
6.9
8.3
8.3
1.6
1.6
1.8
1.8
1.6
1.8
1.8
1.6
1.6
1.8
1.8
8.0
8.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
10.2
10.2
8.3
12.0
12.0
8.0
6.9
6.95
6.9
10.2
10.2
8.3
12.0
12.0
8.0
6.9
6.95
6.95
6.9
8.3
8.0
10.2
10.2
12.0
12.0
6.9
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS7950QDBTRQ1
ADS7951QDBTRQ1
ADS7952QDBTRQ1
ADS7953QDBTRQ1
ADS7954QDBTRQ1
ADS7956QDBTRQ1
ADS7957QDBTRQ1
ADS7958QDBTRQ1
ADS7959QDBTRQ1
ADS7960QDBTRQ1
ADS7961QDBTRQ1
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
30
30
38
38
30
38
38
30
30
38
38
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBT0038A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.55
6.25
TYP
C
A
0.1 C
PIN 1 INDEX AREA
38 X 0.5
38
1
2X
9
9.75
9.65
NOTE 3
19
B
20
0.23
38 X
0.17
4.45
1.2 MAX
0.1
C A B
4.35
NOTE 4
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220221/A 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DBT0038A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
38 X (1.5)
SYMM
(R0.05) TYP
38
1
38 X (0.3)
38 X (0.5)
SYMM
19
20
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220221/A 05/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBT0038A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
38 X (1.5)
SYMM
(R0.05) TYP
38
1
38 X (0.3)
38 X (0.5)
SYMM
19
20
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220221/A 05/2020
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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