ADS5474-SP [TI]
耐辐射加固保障 (RHA)、QMLV、100krad、陶瓷、14 位、单通道、400MSPS ADC;
| 型号： | ADS5474-SP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 耐辐射加固保障 (RHA)、QMLV、100krad、陶瓷、14 位、单通道、400MSPS ADC |
| 文件： | 总28页 (文件大小：1426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5474-SP
www.ti.com.cn
ZHCSBJ5 –SEPTEMBER 2013
14 位，400 每秒百万次采样 (MSPS) 模数转换器
查询样品: ADS5474-SP
1
特性
•
•
•
•
400 MSPS 采样率
•
•
采用 84 引脚陶瓷绝缘分流条封装 (HFG)
14 位分辨率，10.9 位有效位数 (ENOB)
1.28GHz 输入带宽
军用温度范围：
-55°C 至 +125°C T外壳
(1)
•
•
可提供工程评估 (/EM) 样品
230MHz 和 400MSPS 时，无杂散动态范围
(SFDR) = 78dBc
与 12 位和 14 位系列引脚相似且兼容：
ADS5463-SP 和 ADS5444-SP
•
230MHz 和 400MSPS 时，信噪比 (SNR) =
69.8dBFS
应用范围
•
•
•
•
•
•
•
2.2 VPP差分输入电压
•
•
•
•
•
•
测试和测量仪器
兼容低压差分信令 (LVDS) 的输出
总功率耗散：2.5W
软件定义无线电
数据采集
断电模式：50mW
功率放大器线性化
通信仪器
偏移二进制输出格式
半速率输出时钟上升沿和下降沿的输出数据变换
片上模拟缓冲器、跟踪保持和基准电路
雷达
(1) 这些部件只用于工程评估。 它们的加工工艺为非兼容流程（例
如，无预烧过程等）并且只在 25°C 的温度额定值下测试。 这
些部件不适合于品质检定、生产、辐射测试或飞行使用。 不担
保完全军用额定温度
-55°C 至 125°C 范围内或使用寿命内的部件性能。
说明/订购信息
ADS5474 是一款 14 位，400MSPS 模数转换器 (ADC)，此转换器在提供 LVDS 兼容数字输出的同时，可由 5V 和
3V 电源供电运行。 这个 ADC 是 12，13，14 位 ADC 系列的一员，采样率在 210MSPS 至 500MSPS 之间。
ADS5474 输入缓冲器隔离了板上跟踪和保持 (T&H) 的内部开关，这样在提供一个高阻抗输入的同时，防止内部开
关干扰信号源。 还提供了一个内部基准发生器来简化系统设计。
在采样率为 400MSPS 时，针对超过 400MHz 的宽带宽信号的转换，设计使用 1.4GHz 输入带宽，ADS5474 在宽
输入频率范围内具有出色低噪声性能和无杂散动态范围。
ADS5474 采用 84 引脚陶瓷绝缘分流条封装 (HFG)。 此器件采用德州仪器 (TI) 互补双极工艺 (BiCom3) 制造，并
且在完全军用温度范围（-55°C 至 +125°C T外壳）内额定运行。
VIN
VIN
+
+
A1
TH1
TH2
A2
TH3
A3
ADC3
S
S
–
–
ADC1
DAC1
ADC2
DAC2
VREF
Reference
5
5
6
Digital Error Correction
CLK
CLK
Timing
OVR
OVR
DRY
DRY
D[13:0]
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLAS574
ADS5474-SP
ZHCSBJ5 –SEPTEMBER 2013
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
ADS5474-SP
UNIT
V
AVDD5 to GND
AVDD3 to GND
DVDD3 to GND
6
Supply voltage
5
V
5
–0.3 to (AVDD5 + 0.3)
–0.3 to (AVDD5 + 0.3)
±2.5
V
Analog input to GND
Clock input to GND
CLK to CLK
V
V
V
Digital data output to GND
–0.3 to (DVDD3 + 0.3)
–55 to +125
+150
V
Operating case temperature range, TC
Maximum junction temperature, TJ
Storage temperature range
°C
°C
°C
kV
–65 to +150
2
ESD, human-body model (HBM)
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime are available upon
request.
THERMAL CHARACTERISTICS(1)
PARAMETER
Junction-to-free-air thermal resistance
Junction-to-case thermal resistance
TEST CONDITIONS
TYP
21.81
0.849
UNIT
°C/W
°C/W
RθJA
RθJC
Junction-to-case thermal resistance
MIL-STD-883 Test Method 1012
(1) This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the bottom of the package.
To efficiently remove heat and provide a low-impedance ground path, a thermal land is required on the surface of the PCB directly
underneath the body of the package. During normal surface mount flow solder operations, the heat pad on the underside of the package
is soldered to this thermal land creating an efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it
that provide a thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat removal. TI
typically recommends an 11,9 mm2 board-mount thermal pad. This allows maximum area for thermal dissipation, while keeping leads
away from the pad area to prevent solder bridging. A sufficient quantity of thermal/electrical vias must be included to keep the device
within recommended operating conditions. This pad must be electrically at ground potential.
2
Copyright © 2013, Texas Instruments Incorporated
ADS5474-SP
www.ti.com.cn
ZHCSBJ5 –SEPTEMBER 2013
1000
100
10
1
80
90 100 110 120 130 140 150 160 170 180
Continuous Junction Temperature - °C
Figure 1. Operating Life Derating Chart, Electromigration Fail Mode
Copyright © 2013, Texas Instruments Incorporated
3
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ZHCSBJ5 –SEPTEMBER 2013
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RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLIES
AVDD5
AVDD3
DVDD3
Analog supply voltage
Analog supply voltage
Output driver supply voltage
4.75
3.1
3
5
3.3
3.3
5.25
3.6
V
V
V
3.6
ANALOG INPUT
Differential input range
Input common mode
2.2
3.1
VPP
V
VCM
DIGITAL OUTPUT (DRY, DATA, OVR)
Maximum differential output load
CLOCK INPUT (CLK)
10
pF
CLK input sample rate (sine wave)
Clock amplitude, differential sine wave(1)
20(1)
0.5
400 MSPS
5
60
VPP
%
(1)
Clock duty cycle
40
50
TC
Operating case temperature range
–55
+125
°C
(1) Parameters are assured by characterization, but not production tested.
ELECTRICAL CHARACTERISTICS
Typical values at TC = +25°C: minimum and maximum values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C,
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3 VPP differential clock, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
14
Bits
ANALOG INPUTS
Differential input range
2.2
3.1
VPP
V
Analog input common-mode voltage
Input resistance (dc)
Self-biased; see VCM specification below
Each input to VCM
500
7.4
Ω
Input capacitance
Each input to GND
pF
Analog input bandwidth (–3dB)
1.28
GHz
Common-mode signal < 50 MHz
(see Figure 28)
CMRR
Common-mode rejection ratio
100
dB
INTERNAL REFERENCE VOLTAGE
VREF
Reference voltage
2.4
3.1
V
V
With internal VREF. Provided as an output
via the VCM pin for dc-coupled
applications.
Analog input common-mode voltage
reference output
VCM
2.9
3.3
VCM temperature coefficient
–0.8
mV/°C
DYNAMIC ACCURACY
No missing codes
Assured
±0.7
DNL
INL
Differential linearity error
Integral linearity error
Offset error
fIN = 10 MHz
fIN = 10 MHz
–0.99
–7.0
–16
2.5
7.0
16
LSB
LSB
±1.5
mV
Offset temperature coefficient
Gain error
0.02
mV/°C
%FS
–5
5
Gain temperature coefficient
–0.02
%FS/°C
4
Copyright © 2013, Texas Instruments Incorporated
ADS5474-SP
www.ti.com.cn
ZHCSBJ5 –SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS (continued)
Typical values at TC = +25°C: minimum and maximum values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C,
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3 VPP differential clock, unless otherwise noted.
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IAVDD5
IAVDD3
5-V analog supply current
3.3-V analog supply current
338
185
75
380
210
85
mA
mA
VIN = full-scale, fIN = 70 MHz,
fS = 400 MSPS
3.3-V digital supply current
(includes LVDS)
IDVDD3
mA
Total power dissipation
Power-up time
2.5
50
2.835
W
From turn-on of AVDD5
μs
From PDWN pin switched from HIGH
(PDWN active) to LOW (ADC awake)
(see Figure 29)
Wake-up time
5
μs
Power-down power dissipation
PDWN pin = logic HIGH
50
75
90
350
mW
dB
Power-supply rejection ratio,
AVDD5 supply
PSRR
PSRR
PSRR
Power-supply rejection ratio,
AVDD3 supply
Without 0.1 μF board supply capacitors,
with < 1 MHz supply noise
dB
dB
Power-supply rejection ratio,
DVDD3 supply
110
DYNAMIC AC CHARACTERISTICS
fIN = 30 MHz
fIN = 70 MHz
fIN = 130 MHz
fIN = 230 MHz
fIN = 351 MHz
fIN = 451 MHz
fIN = 651 MHz
fIN = 751 MHz
fIN = 999 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 130 MHz
fIN = 230 MHz
fIN = 351 MHz
fIN = 451 MHz
fIN = 651 MHz
fIN = 751 MHz
fIN = 999 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 130 MHz
fIN = 230 MHz
fIN = 351 MHz
fIN = 451 MHz
fIN = 651 MHz
fIN = 751 MHz
fIN = 999 MHz
70.5
68.7
69.9
69.8
69.2
68.8
67.3
66.6
64.4
79.4
76.3
78.8
78
65
65
SNR
SFDR
HD2
Signal-to-noise ratio
dBFS
69
64.5
Spurious-free dynamic range
74.3
70.5
58.6
54.3
46
dBc
92
87
87
84
Second-harmonic
77
dBc
75
68
64
53
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5
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ZHCSBJ5 –SEPTEMBER 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS (continued)
Typical values at TC = +25°C: minimum and maximum values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C,
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3 VPP differential clock, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS (continued)
fIN = 30 MHz
81
86
fIN = 70 MHz
fIN = 130 MHz
fIN = 230 MHz
fIN = 351 MHz
fIN = 451 MHz
fIN = 651 MHz
fIN = 751 MHz
fIN = 999 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 130 MHz
fIN = 230 MHz
fIN = 351 MHz
fIN = 451 MHz
fIN = 651 MHz
fIN = 751 MHz
fIN = 999 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 130 MHz
fIN = 230 MHz
fIN = 351 MHz
fIN = 451 MHz
fIN = 651 MHz
fIN = 751 MHz
fIN = 999 MHz
80
80
HD3
Third-harmonic
76
dBc
72
60
56
48
93
91
91
88
Worst harmonic/spur
(other than HD2 and HD3)
87
dBc
87
91
87
80
77
73.5
74.9
74.9
71.3
68.4
57.8
53.6
45
THD
Total harmonic distortion
dBc
6
Copyright © 2013, Texas Instruments Incorporated
ADS5474-SP
www.ti.com.cn
ZHCSBJ5 –SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS (continued)
Typical values at TC = +25°C: minimum and maximum values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C,
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3 VPP differential clock, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS (continued)
fIN = 30 MHz
69.8
67.7
68.9
68.9
67.5
66.1
58.2
54.3
45.9
fIN = 70 MHz
fIN = 130 MHz
fIN = 230 MHz
fIN = 351 MHz
fIN = 451 MHz
fIN = 651 MHz
fIN = 751 MHz
fIN = 999 MHz
62.5
60.5
SINAD
Signal-to-noise and distortion
dBc
fIN1 = 69 MHz, fIN2 = 70 MHz,
each tone at –7 dBFS
84.2
98.5
82.5
99
fIN1 = 69 MHz, fIN2 = 70 MHz,
each tone at –16 dBFS
Two-tone SFDR
dBFS
fIN1 = 297.5 MHz, fIN2 = 302.5 MHz,
each tone at –7 dBFS
fIN1 = 297.5 MHz, fIN2 = 302.5 MHz,
each tone at –16 dBFS
fIN = 70 MHz
10.1
9.77
10.9
10.5
1.8
ENOB
Effective number of bits
RMS idle-channel noise
Bits
fIN = 230 MHz
Inputs tied to common-mode
LSB
LVDS DIGITAL OUTPUTS
VOD
VOC
Differential output voltage (±)
Common-mode output voltage
247
350
454
mV
V
1.115
1.375
DIGITAL INPUTS
VIH
VIL
IIH
High level input voltage
2.0
-1
V
Low level input voltage
High level input current
Low level input current
Input Capacitance
0.8
1
V
PWD (pin 33)
μA
μA
pF
IIL
CIN
2.2
Copyright © 2013, Texas Instruments Incorporated
7
ADS5474-SP
ZHCSBJ5 –SEPTEMBER 2013
www.ti.com.cn
TIMING INFORMATION
Sample
N–1
N+4
N+2
ta
N
N+1
N+3
N+5
tCLKH
tCLKL
CLK
CLK
Latency = 3.5 Clock Cycles
tDRY
DRY
DRY(1)
tDATA
D[13:0], OVR
N–1
N
N+1
D[13:0], OVR
(1) Polarity of DRY is undetermined. For further information, see the Digital Outputs section.
Figure 2. Timing Diagram
TIMING CHARACTERISTICS(1)
Typical values at TC = +25°C: minimum and maximum values over full temperature range TC,MIN = –55°C to TC,MAX = +125°C,
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3 VPP differential
clock, unless otherwise noted.
PARAMETER
Aperture delay
TEST CONDITIONS
MIN
TYP
200
103
3.5
MAX
UNIT
ps
ta
Aperture jitter, rms
Latency
Internal jitter of the ADC
fs
cycles
ns
tCLK
Clock period
2.5
1
50
tCLKH
tCLKL
tDRY
Clock pulse duration, high
Clock pulse duration, low
CLK to DRY delay(2)
ns
1
ns
Zero crossing, 10-pF parasitic loading to GND on each
output pin
700
1600
1600
0
2500
2600
700
ps
tDATA
tSKEW
CLK to DATA/OVR delay(2)
DATA to DRY skew
Zero crossing, 10-pF parasitic loading to GND on each
output pin
650
ps
ps
tDATA – tDRY, 10-pF parasitic loading to GND on each output
pin
-700
tRISE
tFALL
DRY/DATA/OVR rise time
DRY/DATA/OVR fall time
10-pF parasitic loading to GND on each output pin
10-pF parasitic loading to GND on each output pin
500
500
ps
ps
(1) Timing parameters are assured by characterization, but not production tested.
(2) DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation
delay.
8
Copyright © 2013, Texas Instruments Incorporated
ADS5474-SP
www.ti.com.cn
ZHCSBJ5 –SEPTEMBER 2013
PIN CONFIGURATION
HFG PACKAGE
(TOP VIEW)
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
AGND
DVDD3
GND
1
63
D5
2
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
D5
D4
D4
3
AVDD5
NC
4
5
D3
NC
6
D3
VREF
GND
7
D2
8
D2
AVDD5
GND
9
GND
DVDD3
D1
10
11
12
13
14
15
16
17
18
19
20
21
ADS5474-SP
CLK
CLK
D1
D0
GND
AVDD5
AVDD5
GND
D0
NC
NC
AIN+
NC
AIN–
NC
GND
OVR
OVR
AGND
AVDD5
GND
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
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ZHCSBJ5 –SEPTEMBER 2013
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Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
AIN
NO.
DESCRIPTION
17
18
Differential input signal (positive)
AIN
Differential input signal (negative)
4, 9, 14, 15, 20, 23,
25, 27, 29, 33
AVDD5
Analog power supply (5 V)
AVDD3
DVDD3
37, 39, 41
2, 54, 70
Analog power supply (3.3 V)
Digital and output driver power supply (3.3 V)
1,3, 8, 10, 13, 16,
19, 21, 22, 24, 26,
GND
28, 30, 32, 34, 36, Ground
38, 40, 42, 43, 55,
64, 69
CLK
11
12
Differential input clock (positive). Conversion is initiated on rising edge.
CLK
Differential input clock (negative)
D0, D0
50, 51
LVDS digital output pair, least-significant bit (LSB)
D1, D1,
D2–D5,
D6-D7,
D8-D12
52, 53,
56–63,
65–68,
71–82
LVDS digital output pairs
D13, D13
DRY, DRY
NC
81, 82
84, 83
LVDS digital output pair, most significant bit (MSB)
Data ready LVDS output pair
5, 6, 46, 47, 48, 49 No connect
Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale
range.
OVR, OVR
45, 44
Common-mode voltage output (3.1 V nominal). Commonly used in DC-coupled applications to set the
input signal to the correct common-mode voltage.
VCM
31
(This pin is not used on the ADS5463-SP and ADS5444-SP)
Power-down (active high). Device is in sleep mode when PDWN pin is logic HIGH. ADC converter is
awake when PDWN is logic LOW (grounded).
(This pin is not used on the ADS5463-SP and ADS5444-SP)
PDWN
VREF
35
7
Reference voltage input/output (2.4 V nominal)
10
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ADS5474-SP
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ZHCSBJ5 –SEPTEMBER 2013
TYPICAL CHARACTERISTICS
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SPECTRAL PERFORMANCE
FFT FOR 30 MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 70 MHz INPUT SIGNAL
0
±20
0
±20
SFDR = 79.4 dBc
SFDR = 76.3 dBc
SNR = 70.5 dBFS
SINAD = 69.8 dBFS
THD = 77 dBc
SNR = 68.7 dBFS
SINAD = 67.7 dBFS
THD = 73.5 dBc
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
20
40
60
80 100 120 140 160 180 200
0
20
40
60
80 100 120 140 160 180 200
Frequency ± MHz
Frequency ± MHz
C001
C002
Figure 3.
Figure 4.
SPECTRAL PERFORMANCE
FFT FOR 130 MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 230 MHz INPUT SIGNAL
0
±20
0
±20
SFDR = 78.8 dBc
SNR = 69.9 dBFS
SINAD = 68.9 dBFS
THD = 74.9 dBc
SFDR = 78 dBc
SNR = 69.8 dBFS
SINAD = 68.9 dBFS
THD = 74.9 dBc
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
20
40
60
80 100 120 140 160 180 200
0
20
40
60
80 100 120 140 160 180 200
Frequency ± MHz
Frequency ± MHz
C003
C004
Figure 5.
Figure 6.
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ZHCSBJ5 –SEPTEMBER 2013
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SPECTRAL PERFORMANCE
FFT FOR 351 MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 451 MHz INPUT SIGNAL
0
±20
0
±20
SFDR = 74.3 dBc
SFDR = 70.5 dBc
SND = 69.2 dBFS
SINAD = 67.5 dBFS
THD = 71.3 dBc
SNR = 68.8 dBFS
SINAD = 66.1 dBFS
THD = 68.4 dBc
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
20
40
60
80 100 120 140 160 180 200
0
20
40
60
80 100 120 140 160 180 200
Frequency ± MHz
Frequency ± MHz
C005
C006
Figure 7.
Figure 8.
SPECTRAL PERFORMANCE
FFT FOR 751 MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 999 MHz INPUT SIGNAL
0
±20
0
±20
SFDR = 54.3 dBc
SFDR = 46 dBc
SNR = 66.6 dBFS
SINAD = 54.3 dBFS
THD = 53.6 dBC
SNR = 64.4 dBFS
SINAD = 45.9 dBFS
THD = 45 dBc
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
20
40
60
80 100 120 140 160 180 200
0
20
40
60
80 100 120 140 160 180 200
Frequency ± MHz
Frequency ± MHz
C007
C008
Figure 9.
Figure 10.
12
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ZHCSBJ5 –SEPTEMBER 2013
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
TWO-TONE INTERMODULATION DISTORTION
TWO-TONE INTERMODULATION DISTORTION
(FFT for 297.5 MHz and 302.5 MHz at –7 dBFS)
(FFT for 69 MHz and 70 MHz at –7 dBFS)
0
-20
0
-20
fIN1 = 69 MHz, -7 dBFS
fIN2 = 70 MHz, -7 dBFS
fIN1 = 297.5 MHz, -7 dBFS
fIN2 = 302.5 MHz, -7 dBFS
IMD3 = 82.5 dBFS
IMD3 = 84.2 dBFS
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
20
40
60
80 100 120 140 160 180 200
Frequency - MHz
0
20
40
60
80 100 120 140 160 180 200
Frequency - MHz
C009
C010
Figure 11.
Figure 12.
TWO-TONE INTERMODULATION DISTORTION
(FFT for 69 MHz and 70 MHz at –16 dBFS)
TWO-TONE INTERMODULATION DISTORTION
(FFT for 297.5 MHz and 302.5 MHz at –16 dBFS)
0
-20
0
-20
fIN1 = 297.5 MHz, -16 dBFS
fIN2 = 302.5 MHz, -16 dBFS
fIN1 = 69 MHz, -16 dBFS
fIN2 = 70 MHz, -16 dBFS
IMD3 = 99 dBFS
IMD3 = 98.5 dBFS
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
20
40
60
80 100 120 140 160 180 200
Frequency - MHz
0
20
40
60
80 100 120 140 160 180 200
Frequency - MHz
C011
C012
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
NORMALIZED GAIN RESPONSE
vs
INPUT FREQUENCY
DIFFERENTIAL NONLINEARITY
0.5
0.4
5
0
fS = 400 MSPS
fIN = 70 MHz
0.3
±5
0.2
±10
±15
±20
±25
±30
±35
±40
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
fS = 400 MSPS
AIN = 0.38 VPP
0
2048 4096 6144 8192 10240 12288 14336 16384
Code
10M
100M
1G
5G
Frequency ± Hz
C013
Figure 15.
Figure 16.
INTEGRAL NONLINEARITY
NOISE HISTOGRAM WITH INPUTS SHORTED
2.0
1.5
25
20
15
10
5
fS = 400 MSPS
fS = 400 MSPS
fIN = VCM
fIN = 70 MHz
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
0
0
2048 4096 6144 8192 10240 12288 14336 16384
Code
Output Code
C016
Figure 17.
Figure 18.
14
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ZHCSBJ5 –SEPTEMBER 2013
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
AC PERFORMANCE
AC PERFORMANCE
vs
vs
INPUT AMPLITUDE (70 MHz Input Signal)
INPUT AMPLITUDE (230 MHz Input Signal)
100
80
120
100
80
fS = 400 MSPS
fIN = 70 MHz
fS = 400 MSPS
fIN = 230 MHz
60
60
40
40
20
20
0
0
SFDR (dBc)
SFDR (dBFS)
SNR (dBc)
SFDR (dBc)
SFDR (dBFS)
SNR (dBc)
±20
±40
±20
±40
SNR (dBFS)
SNR (dBFS)
0
0
±100 ±90 ±80 ±70 ±60 ±50 ±40 ±30 ±20 ±10
±100 ±90 ±80 ±70 ±60 ±50 ±40 ±30 ±20 ±10
Input Amplitude ± dBFS
Input Amplitude ± dBFS
C017
C018
Figure 19.
Figure 20.
TWO-TONE PERFORMANCE
vs
INPUT AMPLITUDE (f1 = 297.5 MHz and f2 = 302.5 MHz)
SFDR
vs
AVDD5 OVER TEMPERATURE
96
100
fIN1 = 297.5 MHz
fIN2 = 302.5 MHz
fS = 400 MSPS
fIN = 230 MHz
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
90
80
70
60
50
40
30
20
10
0
2F1-F2 (dBc)
±55C
25°C
2F2-F1 (dBc)
Worst Spur (dBc)
125°C
4.7
4.8
4.9
5.0
5.1
5.2
5.3
0
±100 ±90 ±80 ±70 ±60 ±50 ±40 ±30 ±20 ±10
AVDD5 Supply Volttage ± V
Input Amplitude ± dBFS
C020
C019
Figure 21.
Figure 22.
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www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SNR
SFDR
vs
vs
AVDD5 OVER TEMPERATURE
AVDD33 OVER TEMPERATURE
74
73
72
71
70
69
68
67
66
65
64
92
88
84
80
76
72
68
64
fS = 400 MSPS
fIN = 230 MHz
fS = 400 MSPS
fIN = 230 MHz
±55C
25°C
±55C
25°C
125°C
125°C
4.7
4.8
4.9
5.0
5.1
5.2
5.3
3.0
3.1
3.2
3.3
3.4
3.5
3.6
AVDD5 Supply Volttage ± V
AVDD33 Supply Volttage ± V
C021
C022
Figure 23.
Figure 24.
SNR
vs
SFDR
vs
AVDD33 OVER TEMPERATURE
DVDD18 OVER TEMPERATURE
74
72
70
68
66
64
92
88
84
80
76
72
68
64
fS = 400 MSPS
fIN = 230 MHz
fS = 400 MSPS
fIN = 230 MHz
±55C
25°C
±55C
25°C
125°C
125°C
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
AVDD33 Supply Volttage ± V
DVDD18 Supply Volttage ± V
C023
C024
Figure 25.
Figure 26.
16
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ZHCSBJ5 –SEPTEMBER 2013
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SNR
CMRR
vs
vs
DVDD18 OVER TEMPERATURE
COMMON-MODE INPUT FREQUENCY
0
±10
74
72
70
68
66
64
400 MSPS
fS = 400 MSPS
fIN = 230 MHz
±20
±30
±40
±50
±60
±70
±80
±90
±100
±110
±120
±130
±55C
25°C
125°C
100m
1
10
100
1k
10k
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Frequency (MHz)
DVDD18 Supply Volttage ± V
C026
C025
Figure 27.
Figure 28.
ADC WAKEUP TIME
75
Wake from PDWN
70
65
60
55
50
45
40
35
30
25
20
15
10
5
Wake from 5 V Supply
0
0
10
20
30
40
50
60
70
80
90 100
Time - ms
Figure 29.
Copyright © 2013, Texas Instruments Incorporated
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ZHCSBJ5 –SEPTEMBER 2013
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APPLICATIONS INFORMATION
Theory of Operation
The ADS5474 is a 14-bit, 400-MSPS, monolithic pipeline ADC. Its bipolar analog core operates from 5-V and
3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs. The conversion
process is initiated by the rising edge of the external input clock. At that instant, the differential input signal is
captured by the input track-and-hold (T&H), and the input sample is converted sequentially by a series of lower
resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling
clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in
a data latency of 3.5 clock cycles, after which the output data are available as a 14-bit parallel word, coded in
offset binary format.
Input Configuration
The analog input for the ADS5474 consists of an analog pseudo-differential buffer followed by a bipolar transistor
T&H. The analog buffer isolates the source driving the input of the ADC from any internal switching and presents
a high impedance that is easy to drive at high input frequencies, compared to an ADC without a buffered input.
The input common-mode is set internally through a 500-Ω resistor connected from 3.1 V to each of the inputs
(common-mode is ~2.4V on 12- and 13-bit members of this family). This configuration results in a differential
input impedance of 1 kΩ.
ADS5474-SP
AVDD5
~ 2.5 nH Bond Wire
Buffer
AIN
~ 200 fF
Bond Pad
CIN = 7.4 pF
500 W
1.6 pF
GND
VCM
AVDD5
1.6 pF
Buffer
GND
500 W
~ 2.5 nH Bond Wire
AIN
~ 200 fF
Bond Pad
CIN = 7.4 pF
GND
Figure 30. Analog Input Equivalent Circuit
For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings
symmetrically between (3.1 V + 0.55 V) and (3.1 V – 0.55 V). This range means that each input has a maximum
signal swing of 1.1 VPP for a total differential input signal swing of 2.2 VPP. Operation below 2.2 VPP is allowable,
with the characteristics of performance versus input amplitude demonstrated in Figure 19 and Figure 20. For
instance, for performance at 1.1 VPP rather than 2.2 VPP, refer to the SNR and SFDR at –6 dBFS (0 dBFS =
2.2 VPP). The maximum swing is determined by the internal reference voltage generator, eliminating the need for
any external circuitry for this purpose.
18
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ZHCSBJ5 –SEPTEMBER 2013
The ADS5474 performs optimally when the analog inputs are driven differentially. The circuit in Figure 31 shows
one possible configuration using an RF transformer with termination either on the primary or on the secondary of
the transformer. In addition, the evaluation module is configured with two back-to-back transformers, also
demonstrating good performance. If voltage gain is required, a step-up transformer can be used.
Z0
R0
50 W
50 W
AIN
R
200 W
ADS5474-SP
AC Signal
Source
AIN
Mini-Circuits
JTX-4-10T
Figure 31. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer
In addition to the transformer configurations, Texas Instruments offers a wide selection of single-ended
operational amplifiers that can be selected depending on the application. An RF gain-block amplifier, such as
Texas Instruments' THS9001, can also be used for high-input-frequency applications. For large voltage gains at
intermediate-frequencies in the 50 MHz to 400 MHz range, the configuration shown in Figure 32 can be used.
The component values can be tuned for different intermediate frequencies. The example shown in Figure 32 is
located on the evaluation module and is tuned for an IF of 170 MHz. More information regarding this
configuration can be found in the ADS5474 EVM User Guide (SLAU194) and the THS9001 50-MHz to 350-MHz
Cascadeable Amplifier data sheet (SLOS426), both available for download at www.ti.com.
1000 pF
1000 pF
THS9001
VIN
AIN
50 W
50 W
18 µH
39 pF
ADS5474-SP
0.1 µF
THS9001
VIN
AIN
1000 pF
1000 pF
Figure 32. Using the THS9001 IF Amplifier With the ADS5474
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For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier such
as the THS4509 (shown in Figure 33) provides good harmonic performance and low noise over a wide range of
frequencies.
VIN
100 W
348 W
From
50 W
Source
+5V
78.9 W
49.9 W
49.9 W
0.22 µF
AIN
ADS5474-SP
THS4509
CM
18 pF
100 W
VCM
AIN
49.9 W
78.9 W
49.9 W
0.22 µF
0.22 µF
0.1 µF
0.1 µF
348 W
Figure 33. Using the THS4509 or THS4520 With the ADS5474
In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5474 by utilizing the VCM output pin of
the ADC. The 50-Ω resistors and 18-pF capacitor between the THS4509 outputs and ADS5474 inputs (along
with the input capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (–3 dB). Input
termination is accomplished via the 78.9-Ω resistor and 0.22-μF capacitor to ground, in conjunction with the input
impedance of the amplifier circuit. A 0.22-μF capacitor and 49.9-Ω resistor are inserted to ground across the
78.9-Ω resistor and 0.22-μF capacitor on the alternate input to balance the circuit. Gain is a function of the
source impedance, termination, and 348-Ω feedback resistor. See the THS4509 data sheet for further
component values to set proper 50-Ω termination for other common gains. Because the ADS5474 recommended
input common-mode voltage is 3.1 V, the THS4509 operates from a single power-supply input with VS+ = 5 V and
VS– = 0 V (ground). This configuration has the potential to slightly exceed the recommended output voltage from
the THS4509 of 3.6V due to the ADC input common-mode of 3.1V and the +0.55V full-scale signal. This will not
harm the THS4509 but may result in a degradation in the harmonic performance of the THS4509. An amplifier
with a wider recommended output voltage range is the THS4520, which is optimized for low noise and low
distortion in the range of frequencies up to ~20 MHz. Applications that are not sensitive to harmonic distortion
could consider either device at higher frequencies.
20
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ZHCSBJ5 –SEPTEMBER 2013
Clock Inputs
The ADS5474 clock input can be driven with either a differential clock signal or a single-ended clock input. The
characterization of the ADS5474 is typically performed with a 3-VPP differential clock, but the ADC performs well
with a differential clock amplitude down to ~0.5 VPP, as shown in . The clock amplitude becomes more of a factor
in performance as the analog input frequency increases. In low-input-frequency applications, where jitter may not
be a big concern, the use of a single-ended clock could save cost and board space without much performance
tradeoff. When clocked with this configuration, it is best to connect CLK to ground with a 0.01-μF capacitor, while
CLK is ac-coupled with a 0.01-μF capacitor to the clock source, as shown in Figure 35.
ADS5474-SP
AVDD5
~ 2.5 nH Bond Wire
CLK
Parasitic
~ 200 fF
Bond Pad
CIN = 4 pF
GND
1000 W
~ 0.2 pF
Internal
Clock
Buffer
~ 2.4 V
AVDD5
GND
Parasitic
~ 0.2 pF
1000 W
~ 2.5 nH Bond Wire
CLK
~ 200 fF
Bond Pad
CIN = 4 pF
GND
S0292-04
Figure 34. Clock Input Circuit
Square Wave or
Sine Wave
CLK
0.01 µF
ADS5474-SP
CLK
0.01 µF
Figure 35. Single-Ended Clock
For jitter-sensitive applications, the use of a differential clock has some advantages at the system level. The
differential clock allows for common-mode noise rejection at the printed circuit board (PCB) level. With a
differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency applications
because the board level clock jitter is superior.
Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. In
the case of a sinusoidal clock, larger amplitudes result in higher clock slew rates and reduces the impact of clock
noise on jitter. At high analog input frequencies, the sampling process is sensitive to jitter. And at slow clock
frequencies, a small amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR
degradation. Figure 36 demonstrates a recommended method for converting a single-ended clock source into a
differential clock; it is similar to the configuration found on the evaluation board and was used for much of the
characterization. See also Clocking High Speed Data Converters (SLYT075) for more details.
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0.1 µF
Clock
Source
CLK
ADS5474-SP
CLK
Figure 36. Differential Clock
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors. It is
recommended to use ac coupling, but if this scheme is not possible, the ADS5474 features good tolerance to
clock common-mode variation. Additionally, the internal ADC core uses both edges of the clock for the
conversion process. Ideally, a 50% duty-cycle clock signal should be provided.
The ADS5474 is capable of achieving 69.2 dBFS SNR at 350 MHz of analog input frequency. In order to achieve
the SNR at 350 MHz the clock source rms jitter must be at least 144 fsec in order for the total rms jitter to be 177
fsec. A summary of maximum recommended rms clock jitter as a function of analog input frequency is provided
in Table 2. The equations used to create the table are also presented.
Table 2. Recommended RMS Clock Jitter
MAXIMUM CLOCK
INPUT FREQUENCY
(MHz)
MEASURED SNR
(dBc)
TOTAL JITTER
(fsec rms)
JITTER
(fsec rms)
30
70
69.3
69.1
69.1
68.8
68.2
67.4
65.6
63.7
1818
798
429
251
177
151
111
104
1816
791
417
229
144
110
42
130
230
350
450
750
1000
14
Equation 1 and Equation 2 are used to estimate the required clock source jitter.
SNR (dBc) = -20 ´ LOG10 (2 ´ p ´ fIN ´ jTOTAL
)
(1)
(2)
2
1/2
jTOTAL = (jADC2 + jCLOCK
)
where:
jTOTAL = the rms summation of the clock and ADC aperture jitter;
jADC = the ADC internal aperture jitter which is located in the data sheet;
jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and
fIN = the analog input frequency.
Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the
clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.
For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not
required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see
Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC
Devices, on the Texas Instruments web site. Recommended clock distribution chips (CDCs) are the TI
CDC7005, the CDCM7005-SP and CDCE72010. Depending on the jitter requirements, a band pass filter (BPF)
is sometimes required between the CDC and the ADC. If the insertion loss of the BPF causes the clock
amplitude to be too low for the ADC, or the clock source amplitude is too low to begin with, an inexpensive
amplifier can be placed between the CDC and the BPF.
22
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ZHCSBJ5 –SEPTEMBER 2013
Figure 37 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCM7005-SP
with the clock signal path optimized for maximum amplitude and minimum jitter. This type of conditioning might
generally be well-suited for use with greater than 150 MHz of input frequency. The jitter of this setup is difficult to
estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost
amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter
provided by the CDC is still not adequate. The total jitter at the CDCM7005-SP output depends largely on the
phase noise of the VCXO selected, as well as the CDCM7005-SP, and typically has 50–100 fs of rms jitter. If it is
determined that the jitter from the CDCM7005-SP with a VCXO is sufficient without further conditioning, it is
possible to clock the ADS5474 directly from the CDCM7005-SP using differential LVPECL outputs, as illustrated
in Figure 38 (see the CDCM7005-SP data sheet for the exact schematic). This scenario may be more suitable for
less than 150 MHz of input frequency where jitter is not as critical. A careful analysis of the required jitter is
recommended before determining the proper approach.
Low-Jitter Clock Distribution
AMP and/or BPF are Optional
Board Master
Reference Clock
(high or low jitter)
10 MHz
CLKIN
BPF
LVCMOS
AMP
XFMR
REF
CLKIN
400 MHz
ADC
800 MHz (to transmit DAC)
100 MHz (to DSP)
ADS5474-SP
LVPECL
or
LVCMOS
Low-Jitter Oscillator
800 MHz
200 MHz (to FPGA)
To Other
VCXO
CDC
(Clock Distribution Chip)
CDCM7005-SP
This is an example block diagram.
Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output
frequency and amplitude ranges.
Figure 37. Optimum Jitter Clock Circuit
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Low-Jitter Clock Distribution
400 MHz
Board Master
Reference Clock
(high or low jitter)
10 MHz
CLKIN
CLKIN
LVPECL
REF
ADC
800 MHz (to transmit DAC)
100 MHz (to DSP)
ADS5474-SP
LVPECL
or
LVCMOS
Low-Jitter Oscillator
800 MHz
200 MHz (to FPGA)
To Other
VCXO
CDC
(Clock Distribution Chip)
CDCM7005-SP
This is an example block diagram.
Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output
frequency and amplitude ranges.
Figure 38. Acceptable Jitter Clock Circuit
Digital Outputs
The ADC provides 14 LVDS-compatible, offset binary data outputs (D13 to D0; D13 is the MSB and D0 is the
LSB), a data-ready signal (DRY), and an over-range indicator (OVR). It is recommended to use the DRY signal
to capture the output data of the ADS5474. DRY is source-synchronous to the DATA/OVR outputs and operates
at the same frequency, creating a half-rate DDR interface that updates data on both the rising and falling edges
of DRY. It is recommended that the capacitive loading on the digital outputs be minimized. Higher capacitance
shortens the data-valid timing window. The values given for timing (see Figure 2) were obtained with a measured
10-pF parasitic board capacitance to ground on each LVDS line (or 5-pF differential parasitic capacitance). When
setting the time relationship between DRY and DATA at the receiving device, it is generally recommended that
setup time be maximized, but this partially depends on the setup and hold times of the device receiving the
digital data (like an FPGA or Field Programmable Field Array). Since DRY and DATA are coincident, it will likely
be necessary to delay either DRY or DATA such that setup time is maximized.
Referencing Figure 2, the polarity of DRY with respect to the sample N data output transition is undetermined
because of the unknown startup logic level of the clock divider that generates the DRY signal (DRY is a
frequency divide-by-two of CLK). Either the rising or the falling edge of DRY will be coincident with sample N and
the polarity of DRY could invert when power is cycled off/on or when the power-down pin is cycled. Data capture
from the transition and not the polarity of DRY is recommended, but not required. If the synchronization of
multiple ADS5474 devices is required, it might be necessary to use a form of the CLKIN signal rather than DRY
to capture the data.
The DRY frequency is identical on the ADS5474 and ADS5463 (where DRY equals ½ the CLK frequency), but
different than it is on the pin-similar ADS5444 (where DRY equals the CLK frequency). The LVDS outputs all
require an external 100-Ω load between each output pair in order to meet the expected LVDS voltage levels. For
long trace lengths, it may be necessary to place a 100-Ω load on each digital output as close to the ADS5474 as
possible and another 100-Ω differential load at the end of the LVDS transmission line to provide matched
impedance and avoid signal reflections. The effective load in this case reduces the LVDS voltage levels by half.
The OVR output equals a logic high when the 14-bit output word attempts to exceed either all 0s or all 1s. This
flag is provided as an indicator that the analog input signal exceeded the full-scale input limit of approximately
2.2 VPP (± gain error). The OVR indicator is provided for systems that use gain control to keep the analog input
signal within acceptable limits.
24
Copyright © 2013, Texas Instruments Incorporated
ADS5474-SP
www.ti.com.cn
ZHCSBJ5 –SEPTEMBER 2013
Power Supplies
The ADS5474 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5
and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power
supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched
supplies tend to generate more noise components that can be coupled to the ADS5474. The user may be able to
supply power to the device with a less-than-ideal supply and still achieve good performance. It is not possible to
make a single recommendation for every type of supply and level of decoupling for all systems. The power
consumption of the ADS5474 does not change substantially over clock rate or input frequency as a result of the
architecture and process.
Because there are two diodes connected in reverse between AVDD3 and DVDD3 internally, a power-up
sequence is recommended. When there is a delay in power up between these two supplies, the one that lags
could have current sinking through an internal diode before it powers up. The sink current can be large or small
depending on the impedance of the external supply and could damage the device or affect the supply source.
The best power up sequence is one of the following options (regardless of when AVDD5 powers up):
1) Power up both AVDD3 and DVDD3 at the same time (best scenario), OR
2) Keep the voltage difference less than 0.8V between AVDD3 and DVDD3 during the power up (0.8V is not a
hard specification - a smaller delta between supplies is safer).
If the above sequences are not practical then the sink current from the supply needs to be controlled or
protection added externally. The max transient current (on the order of μsec) for DVDD3 or AVDD3 pin is 500mA
to avoid potential damage to the device or reduce its lifetime.
Values for analog and clock input given in the Absolute Maximum Ratings are valid when the supplies are on.
When the power supplies are off and the clock or analog inputs are still alive, the input voltage and current needs
to be limited to avoid device damage. If the ADC supplies are off, the max/min continuous DC voltage is +/- 0.95
V and max DC current is 20 mA for each input pin (clock or analog), relative to ground.
Figure 39. PSRR vs Supply Injected Frequency
0
-10
-20
-30
-40
-50
AVDD3
AVDD5
-60
-70
-80
-90
DVDD3
-100
-110
-120
0.1
1
10
Frequency (MHz)
100
1000
Copyright © 2013, Texas Instruments Incorporated
25
ADS5474-SP
ZHCSBJ5 –SEPTEMBER 2013
www.ti.com.cn
DEFINITION OF SPECIFICATIONS
The injected frequency level is translated into dBFS,
the spur in the output FFT is measured in dBFS, and
the difference is the PSRR in dB. The measurement
calibrates out the benefit of the board supply
decoupling capacitors.
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low-frequency value.
Signal-to-Noise Ratio (SNR)
Aperture Delay
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and in the first five harmonics.
The delay in time between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs.
P
10
P
S
SNR + 10log
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
N
(4)
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
Clock Pulse Duration/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
duration) to the period of the clock signal, expressed
as a percentage.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding
dc.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1 LSB apart. DNL is the
deviation of any single step from this ideal value,
measured in units of LSB.
P
S
Common-Mode Rejection Ratio (CMRR)
SINAD + 10log
10
P
) P
CMRR measures the ability to reject signals that are
presented to both analog inputs simultaneously. The
injected common-mode frequency level is translated
into dBFS, the spur in the output FFT is measured in
dBFS, and the difference is the CMRR in dB.
N
D
(5)
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
Effective Number of Bits (ENOB)
ENOB is a measure in units of bits of converter
performance as compared to the theoretical limit
based on quantization noise:
Temperature Drift
Temperature drift (with respect to gain error and
offset error) specifies the change from the value at
ENOB = (SINAD – 1.76)/6.02
(3)
the nominal temperature to the value at TMIN or TMAX
.
It is computed as the maximum variation the
parameters over the whole temperature range divided
Gain Error
Gain error is the deviation of the ADC actual input
full-scale range from its ideal value, given as a
percentage of the ideal input full-scale range.
by TMIN – TMAX
.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS)
to the power of the first five harmonics (PD).
Integral Nonlinearity (INL)
INL is the deviation of the ADC transfer function from
a best-fit line determined by a least-squares curve fit
of that transfer function. The INL at each analog input
value is the difference between the actual transfer
function and this best-fit line, measured in units of
LSB.
P
10
P
S
THD + 10log
D
(6)
THD is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion (IMD3)
IMD3 is the ratio of the power of the fundamental (at
frequencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 – f2 or 2f2 – f1).
IMD3 is given in units of either dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
Offset Error
Offset error is the deviation of output code from mid-
code when both inputs are tied to common-mode.
Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of the ability to reject frequencies
present on the power supply.
26
Copyright © 2013, Texas Instruments Incorporated
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