ADS131A04IPBS [TI]
24 位 128kSPS 4 通道同步采样 Δ-Σ ADC | PBS | 32 | -40 to 125;
| 型号： | ADS131A04IPBS |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24 位 128kSPS 4 通道同步采样 Δ-Σ ADC | PBS | 32 | -40 to 125 |
| 文件： | 总92页 (文件大小：1854K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS131A02, ADS131A04
ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
ADS131A0x 双通道或四通道 24 位 128kSPS 同步采样 Δ-Σ ADC
1 特性
3 说明
1
•
双通道或四通道同步采样差分输入
数据速率：高达 128kSPS
高性能：
ADS131A02 和 ADS131A04 器件为双通道和四通道同
步采样 24 位 ΔΣ 模数转换器 (ADC)。ADS131A02 或
ADS131A04 具有宽动态范围、最高 128kSPS 的可扩
展数据速率以及内置故障监控器等特性，这使得它非常
适合能源监控、电网保护和控制等 应用。ADC 输入端
可以单独直接接入电阻分压器网络、电流互感器或
Rogowski 线圈，以测量电压或电流。这两款器件具有
灵活的电源选项（包括内部负电荷泵），可最大限度提
高有效分辨率，非常适合宽动态范围 应用。
•
•
–
单通道精度：在 10,000:1 动态范围内优于
0.1%
–
–
有效分辨率：20.6位 (8kSPS)
总谐波失真 (THD)：50Hz 和 60Hz 频率下为
-100dB
•
•
集成的负电荷泵 允许绝对输入电压低于接地值
灵活的模拟电源选项：
这两款器件提供异步和同步主从接口选项，可为多个器
件串联而成的单一系统灵活实施 ADC 配置。接口上配
有多种接口检查、ADC 启动检查和数据完整性检查功
能，可报告 ADC 中的错误以及数据传输期间的错误。
–
–
–
采用负电荷泵：3.0V 至 3.45V
单极电源：3.3V 至 5.5V
双极电源：±2.5V
•
•
•
•
•
数字电源：1.65V 至 3.6V
这种完整的模拟前端 (AFE) 解决方案采用 32 引脚
TQFP 封装，其额定工业温度范围为 -40°C 至 +125°
C。
低温漂内部基准电压：6ppm/°C
模数转换器 (ADC) 自检
通信时的循环冗余校验 (CRC) 和汉明码错误校正
多个 SPI数据接口模式：
器件信息(1)
–
–
异步中断
器件型号
ADS131A0x
封装
TQFP (32)
封装尺寸（标称值）
同步主从接口
5.00mm x 5.00mm
•
•
封装：32 引脚 TQFP
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
工作温度范围：
-40°C 至 +125°C
简化框图
AVDD
IOVDD
REFP REFN
REFEXT
2 应用
Reference
Mux
•
•
•
•
•
电源保护：断路器和继电器保护
Voltage
Reference
Out-of-Range
Detect
电能计量：单相、多相、电能质量
测试和测量
M[2:0]
RESET
AIN1N
AIN1P
AIN2N
AIN2P
AIN3N
AIN3P
AIN4N
AIN4P
电池测试系统
DS ADC
CS
Control and
Serial Interface
数据采集系统
SCLK
DIN
DOUT
DRDY
DS ADC
Watchdog
Timer
DONE
DS ADC
DS ADC
Data Integrity
CLK/XTAL
Negative
Charge
Pump
XTAL1/CLKIN
XTAL2
GND
VNCP
AVSS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS590
ADS131A02, ADS131A04
ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
www.ti.com.cn
目录
9.2 Functional Block Diagram ....................................... 25
9.3 Feature Description................................................. 26
9.4 Device Functional Modes........................................ 34
9.5 Programming........................................................... 36
9.6 Register Maps ........................................................ 55
10 Application and Implementation........................ 67
10.1 Application Information.......................................... 67
10.2 Typical Application ................................................ 74
10.3 Do's and Don'ts..................................................... 76
10.4 Initialization Set Up .............................................. 78
11 Power Supply Recommendations ..................... 80
11.1 Negative Charge Pump......................................... 80
11.2 Internal Digital LDO............................................... 80
11.3 Power-Supply Sequencing.................................... 80
11.4 Power-Supply Decoupling..................................... 81
12 Layout................................................................... 82
12.1 Layout Guidelines ................................................. 82
12.2 Layout Example .................................................... 83
13 器件和文档支持 ..................................................... 84
13.1 文档支持 ............................................................... 84
13.2 相关链接................................................................ 84
13.3 接收文档更新通知 ................................................. 84
13.4 社区资源................................................................ 84
13.5 商标....................................................................... 84
13.6 静电放电警告......................................................... 84
13.7 Glossary................................................................ 84
14 机械、封装和可订购信息....................................... 84
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 5
Pin Configuration and Functions......................... 5
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information.................................................. 8
7.5 Electrical Characteristics........................................... 9
7.6 Timing Requirements: Asynchronous Interrupt
Interface Mode ......................................................... 12
7.7 Switching Characteristics: Asynchronous Interrupt
Interface Mode ......................................................... 12
7.8 Timing Requirements: Synchronous Master Interface
Mode ........................................................................ 13
7.9 Switching Characteristics: Synchronous Master
Interface Mode ......................................................... 13
7.10 Timing Requirements: Synchronous Slave Interface
Mode ........................................................................ 14
7.11 Switching Characteristics: Synchronous Slave
Interface Mode ......................................................... 14
7.12 Typical Characteristics.......................................... 17
Parameter Measurement Information ................ 22
8.1 Noise Measurements .............................................. 22
Detailed Description ............................................ 25
9.1 Overview ................................................................. 25
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (November 2016) to Revision D
Page
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已更改 将文档标题从双通道或四通道 24 位同步采样 Δ-Σ ADC 更改为双通道或四通道 24 位 128kSPS 同步采样 Δ-Σ ADC 1
已更改 VAVDD 改为 AVDD，VAVSS 改为 AVSS，VGND 改为 GND，且 VIOVDD 改为 IOVDD（全文通改）............................... 1
已更改 特性部分...................................................................................................................................................................... 1
已更改 说明 部分中） ............................................................................................................................................................. 1
Deleted footnote 2 ................................................................................................................................................................. 6
Changed AVDD, AVSS, VNCP, and XTAL2 pin descriptions and footnote 1 for clarity ....................................................... 6
Changed CAP to GND Power supply voltage parameter specifications from GND – 0.3 V to 0.3 V for the minimum
specification and from GND + 2.0 V to 2.0 V for the maximum specification ........................................................................ 7
•
Changed Analog input voltage parameter descriptions from REFEXT to AVDD to REFEXT and from REFN input to
AVSS to REFN ....................................................................................................................................................................... 7
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Changed Digital input voltage parameter description to include the names of the digital input pins..................................... 7
Deleted CMRR footnote from Recommended Operating Conditions table............................................................................ 8
Added symbol to Reference input voltage parameter ............................................................................................................ 8
Changed Offset drift parameter typical specification from 1.2 µV/°C to 2.5 µV/°C and maximum specification from 3
µV/°C to 4 µV/°C..................................................................................................................................................................... 9
•
•
Changed Gain drift parameter typical specification from 0.25 ppm/°C to 0.5 ppm/°C .......................................................... 9
Deleted separate AVDD PSRR specification for the ADS131A02 ........................................................................................ 9
2
版权 © 2016–2018, Texas Instruments Incorporated
ADS131A02, ADS131A04
www.ti.com.cn
ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
修订历史记录 (接下页)
•
•
Changed Reference buffer offset parameter typical specification from 170 µV to 250 µV .................................................... 9
Changed Reference buffer offset drift parameter typical specification from 1.1 µV/°C to 4 µV/°C and maximum
specification from 4.3 µV/°C to 7 µV/°C ................................................................................................................................. 9
•
•
•
Changed Temperature drift parameter typical specification from 4 ppm/°C to 6 ppm/°C .................................................... 10
Deleted VNCP parameter minimum specification and changed typical specification from –1.95 V to –2 V........................ 10
Changed Electrical Characteristics table so all Power-Supply subsections are condensed to one Power-Supply
subsection............................................................................................................................................................................. 10
•
•
Changed free-air to ambient in condition statements of Timing Requirements tables......................................................... 12
Changed location of several interface timing parameters to the Timing Requirements and Switching Characteristics
tables from the Detailed Description section ....................................................................................................................... 12
•
•
Changed unit from ns to tCLKIN in tc(SC) and tw(SCHL) rows of Timing Requirements: Synchronous Master Interface
Mode table............................................................................................................................................................................ 13
Added DRDY Synchronization Timing for Synchronous Slave Mode (CLKSRC = 0) to RESET Pin and Command
Timing figures ....................................................................................................................................................................... 16
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Changed Clock section for clarification and changed setting of XTAL2 pin ........................................................................ 26
Changed Clock Mode Configurations figure to include load capacitors for clarity ............................................................... 27
Changed Analog Input section for clarity.............................................................................................................................. 28
Changed Equivalent Analog Input Circuitry figure................................................................................................................ 28
Changed Input Overrange and Underrange Detection section for clarity ............................................................................ 30
Changed location of Reference section .............................................................................................................................. 30
Changed External Reference Driver figure........................................................................................................................... 31
Changed Internal Reference figure ..................................................................................................................................... 31
Changed Digital Decimation Filter section for clarity............................................................................................................ 32
Deleted figure and table from Reset (RESET) section......................................................................................................... 35
Changed Fixed versus Dynamic-Frame Mode section for clarity......................................................................................... 36
Added Cyclic Redundancy Check (CRC) section for clarity................................................................................................. 39
Changed CRC with CRC_MODE = 0 and CRC Using the WREGS Command figures to using red shading instead of
//Zero .................................................................................................................................................................................... 39
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Changed Data Ready (DRDY) section for clarity ................................................................................................................. 43
Changed pulldown to pullup in bulleted list of ADC Frame Complete (DONE) section ...................................................... 47
Changed description of UNLOCK from POR or RESET section.......................................................................................... 52
Changed description of RREG: Read a Single Register section ......................................................................................... 52
Changed number of registers written plus one (n+1) to number of registers written minus one in WREGS: Write
Multiple Registers section..................................................................................................................................................... 54
•
•
•
•
Changed User Register Description section for clarity......................................................................................................... 56
Changed Unused Inputs and Outputs section for clarity...................................................................................................... 67
Changed title of Multiple Device Configuration section and changed description for clarity ............................................... 68
Changed first paragraph of First Device Configured in Asynchronous Interrupt Mode to condense data from last
three paragraphs into one ................................................................................................................................................... 68
•
•
Changed description of First Device Configured in Synchronous Master Mode section to condense all paragraphs
into one................................................................................................................................................................................. 70
Changed description of All Devices Configured in Synchronous Slave Mode section to condense all paragraphs into
one ....................................................................................................................................................................................... 72
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•
•
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•
Changed ADS131A0x Configuration Sequence figure......................................................................................................... 79
Changed GND to AVSS in VNCP pin description of Negative Charge Pump section......................................................... 80
Changed title of Internal Digital LDO section ....................................................................................................................... 80
Changed description of Power-Supply Sequencing section................................................................................................. 80
Changed Bipolar Analog Power Supply to Unipolar Analog Power Supply with Negative Charge Pump Enabled figures. 81
版权 © 2016–2018, Texas Instruments Incorporated
3
ADS131A02, ADS131A04
ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
www.ti.com.cn
修订历史记录 (接下页)
•
•
Changed first sentence of Layout Example section ............................................................................................................. 83
Changed ADS131A0x Layout Example figure to improve layout......................................................................................... 83
Changes from Revision B (September 2016) to Revision C
Page
•
•
•
•
•
•
已更改 将文档标题从用于电源监视、控制和保护的模拟前端更改为同步采样 Δ-Σ ADC......................................................... 1
已更改 将噪声性能特性 中第二个子项目符号从ENOB 更改为有效分辨率.............................................................................. 1
已更改 有效位数改为有效分辨率（说明部分 .......................................................................................................................... 1
Changed format of Absolute Maximum Ratings table; specification values did not change.................................................. 7
Changed title of Multiple Device Effective Resolution Histogram figure .............................................................................. 17
Changed Noise Measurements section ............................................................................................................................... 22
Changes from Revision A (March 2016) to Revision B
Page
•
•
将 ADS131A02 发布为生产数据 ............................................................................................................................................. 1
Changed AC Performance, PSRR, THD, and SFDR parameters in Electrical Characteristics table: added rows for
ADS131A02 and added ADS131A04 to rows specific to that device ................................................................................... 9
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Changed title of Figure 31 and Figure 32: added ADS131A04 ........................................................................................... 20
Added Figure 33 and Figure 34 ........................................................................................................................................... 21
Changed Noise Measurements section: changed Equation 1, Equation 2, Table 1, and Table 3 ...................................... 22
Added footnote to Figure 43 ................................................................................................................................................ 31
Changed R2 and R3 values in footnote of Figure 44 .......................................................................................................... 31
Changed Cyclic Redundancy Check (CRC) section ............................................................................................................ 39
Changed description of M2 pin functionality in Hamming Code Error Correction section ................................................... 40
Changed description of M0 pin functionality in SPI Interface section .................................................................................. 42
Changed first command status response value in RREGS: Read Multiple Registers section............................................. 52
Changed Table 15: changed register bits of row 00h, default setting and register bits of row 01h, and changed bits
2-0 of 11h, 12h, 13h, and 14h rows .................................................................................................................................... 55
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Changed ID_MSB: ID Control Register MSB and ID_LSB: ID Control Register LSB registers........................................... 56
Changed bits 2-0 of all ADCx: ADC Channel Digital Gain Configuration Registers ............................................................ 66
Changes from Original (March 2016) to Revision A
Page
•
将 ADS131A04 发布为生产数据 ............................................................................................................................................. 1
4
Copyright © 2016–2018, Texas Instruments Incorporated
ADS131A02, ADS131A04
www.ti.com.cn
ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
5 Device Comparison Table
PRODUCT
ADS131A02
ADS131A04
NO. OF ADC CHANNELS
MAXIMUM SAMPLE RATE (kSPS)
2
4
128
128
6 Pin Configuration and Functions
ADS131A02: PBS Package
32-Pin TQFP
ADS131A04: PBS Package
32-Pin TQFP
Top View
Top View
32 31 30 29 28 27 26 25
32 31 30 29 28 27 26 25
AIN1N
AIN1P
AIN2N
AIN2P
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC
AIN1N
AIN1P
AIN2N
AIN2P
AIN3N
AIN3P
AIN4N
AIN4P
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC
CS
CS
SCLK
DOUT
DIN
SCLK
DOUT
DIN
ADS131A02
ADS131A04
NC
DRDY
DONE
RESET
DRDY
DONE
RESET
NC
NC
9
10 11 12 13 14 15 16
9
10 11 12 13 14 15 16
Pin Functions
PIN
NO.
I/O
DESCRIPTION(1)
NAME
ADS131A02
ADS131A04
AIN1N
AIN1P
AIN2N
AIN2P
AIN3N
AIN3P
AIN4N
AIN4P
AVDD
AVSS
1
2
1
2
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Supply
Negative analog input 1
Positive analog input 1
Negative analog input 2
Positive analog input 2
Negative analog input 3
Positive analog input 3
Negative analog input 4
Positive analog input 4
3
3
4
4
—
—
—
—
9
5
6
7
8
9
Positive analog power supply. Connect a 1-µF capacitor to AVSS.
Negative analog power supply
10
10
Supply
Digital low-dropout (LDO) regulator output. Connect a 1-µF
capacitor to GND.
CAP
CS
28
23
28
23
Analog output
Digital input
Chip select; active low
(1) See the Unused Inputs and Outputs section for unused pin connections.
Copyright © 2016–2018, Texas Instruments Incorporated
5
ADS131A02, ADS131A04
ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
www.ti.com.cn
Pin Functions (continued)
PIN
NO.
I/O
DESCRIPTION(1)
NAME
ADS131A02
ADS131A04
DIN
20
18
21
20
18
21
Digital input
Digital output Communication done signal; active low
Digital output Serial data output. Connect a 100-kΩ pullup resistor to IOVDD.
Serial data input
DONE
DOUT
Digital
input/output
Data ready; active low; host interrupt and synchronization for multi-
devices
DRDY
GND
19
19
27
15
29
27
15
29
Supply
Digital ground
IOVDD
Supply
Digital I/O supply voltage. Connect a 1-µF capacitor to GND.
Serial peripheral interface (SPI) configuration mode.
IOVDD: Asynchronous interrupt mode
GND: Synchronous master mode
No connection: Synchronous slave mode; use for multi-device
mode
M0(2)
30
30
Digital input
Digital input
SPI word transfer size.
IOVDD: 32 bit
GND: 24 bit
M1(2)
31
32
31
32
No connection: 16 bit
Hamming code enable.
IOVDD: Hamming code word validation on
GND: Hamming code word validation off
No connection: reserved; do not use
M2(2)
Digital input
—
NC
NC
5-8
24
—
Leave floating or connect directly to AVSS.
24
Digital output No connection
Buffered external reference voltage input.
REFEXT
14
14
Analog input
Connect a 1-µF capacitor to AVSS when using the internal
reference.
REFN
REFP
13
12
13
12
Analog input
Negative reference voltage. Connect to AVSS.
Positive reference voltage output. Connect a 1-µF capacitor to
REFN.
Analog output
RESET
RESV
17
16
17
16
Digital input
Digital input
System reset; active low
Reserved pin; connect to IOVDD
Digital
input/output
SCLK
22
22
Serial data clock
Negative charge pump voltage output.
Connect a 270-nF capacitor to AVSS when enabling the negative
charge pump. Connect directly to AVSS if the negative charge
pump is unused.
VNCP
11
11
Analog output
XTAL1/CLKIN
XTAL2
25
26
25
26
Digital input
Master clock input, crystal oscillator buffer input
Crystal oscillator connection. Leave this pin unconnected if the
crystal oscillator is unused.
Digital output
(2) Mode signal states are latched following a power-on-reset (POR). Tie these pins high or low with a resistance less than 1-kΩ resistor.
6
Copyright © 2016–2018, Texas Instruments Incorporated
ADS131A02, ADS131A04
www.ti.com.cn
ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
7 Specifications
7.1 Absolute Maximum Ratings(1)
MIN
–0.3
MAX
3.6
UNIT
AVDD to AVSS (charge pump enabled)
AVDD to AVSS (charge pump disabled)
–0.3
6.0
IOVDD to GND
–0.3
3.9
Power supply voltage
AVSS to GND
–3.0
0.3
V
VNCP to AVSS
–2.5
0.3
VNCP to AVDD
–6.0
0.3
CAP to GND
–0.3
2.0
Analog input voltage (charge pump enabled)
AVSS – 1.65
AVSS – 0.3
AVSS – 0.3
AVSS – 0.05
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVSS + 0.05
Analog input voltage (charge pump disabled)
Analog input voltage
V
REFEXT
REFN
CS, DIN, DRDY, RESET, SCLK, XTAL1/CLKIN,
M0, M1, M2, RESV
Digital input voltage
Input current
GND – 0.3
–10
IOVDD + 0.3
V
Continuous, any pin except supply pins
Junction, TJ
10
mA
150
150
Temperature
°C
Storage, Tstg
–60
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2016–2018, Texas Instruments Incorporated
7
ADS131A02, ADS131A04
ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
Negative Charge Pump Enabled (VNCPEN(1) = 1)
AVDD to AVSS
3.0
3.0
3.3
3.3
0
3.45
3.45
0.05
3.6
Analog supply voltage
AVDD to GND
AVSS to GND
IOVDD to GND
V
V
–0.05
1.65
Digital supply voltage(2)
3.3
Negative Charge Pump Disabled (VNCPEN = 0)
AVDD to AVSS
AVDD to GND
AVSS to GND
IOVDD to GND
3.0
1.5
5.0
2.5
5.5
5.5
Analog supply voltage
V
V
–2.75
1.65
–2.5
3.3
0.05
3.6
Digital supply voltage(2)
ANALOG INPUTS
VIN
Differential input voltage
VIN = VAINxP – VAINxN
–VREF / Gain
AVSS
VREF / Gain
AVDD
V
V
V
V
VCM
Common-mode input voltage
VNCPEN = 0
VNCPEN = 1
AVSS
AVDD
VAINxP, VAINxN Absolute input voltage
AVSS – 1.5
AVDD
EXTERNAL REFERENCE
VREF
Reference input voltage
REFEXT – REFN
2.0
2.5 AVDD – 0.5
AVSS
VREFN + 2.0 VREFN + 2.5 AVDD – 0.5
V
V
V
VREFN
VREFEXT
Reference negative input
External reference positive input
EXTERNAL CLOCK SOURCE
IOVDD > 2.7 V
0.4
0.4
16.384
8.192
25
15.6
16.5
fCLKIN External clock input frequency
MHz
MHz
IOVDD ≤ 2.7 V
XTAL clock frequency(3)
SCLK input to derive fMOD
16.384
CLKSRC bit = 1, fSCLK = fICLK
IOVDD > 2.7 V
,
,
0.2
0.2
16.384
8.192
25
fSCLK
MHz
CLKSRC bit = 1, fSCLK = fICLK
IOVDD ≤ 2.7 V
15.6
DIGITAL INPUTS
Digital input voltage
GND
–40
IOVDD
125
V
TEMPERATURE
TA
Operating ambient temperature
°C
(1) VNCPEN is bit 7 of the A_SYS_CFG register.
(2) Tie IOVDD to the CAP pin if IOVDD ≤ 2.0 V.
(3) Set IOVDD > 3.0 V to use a crystal across the XTAL1/CLKIN and XTAL2 pins.
7.4 Thermal Information
ADS131A0x
PBS (TQFP)
32 PINS
77.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
19.0
30.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJB
30.0
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8
Copyright © 2016–2018, Texas Instruments Incorporated
ADS131A02, ADS131A04
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ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
7.5 Electrical Characteristics
Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C. All
specifications are at IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF
2.442 V, fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, and gain = 1 (unless otherwise noted).
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Cs
Zin
Input capacitance
3.5
pF
Differential input impedance
fMOD = 4.096 MHz
130
kΩ
ADC PERFORMANCE
Resolution
24
Bits
Gain
1, 2, 4, 8, 16
1
Data rate
fMOD = 4.096 MHz
128
kSPS
DC PERFORMANCE
105
111
115
dB
AVDD – AVSS = 5 V, VREF = 4 V, VNCPEN bit = 0
Dynamic range
See Noise Measurements
All other settings
Best fit
section
INL
Integral nonlinearity
Offset error
Offset drift
8
500
20
4
ppm
µV
2.5
µV/°C
% of FS
ppm/°C
Gain error
Excluding voltage reference and reference buffer error
Excluding voltage reference and reference buffer error
±0.03
0.5
Gain drift
2
AC PERFORMANCE
CMRR
Common-mode rejection ratio
fCM = 50 Hz or 60 Hz
100
80
dB
dB
dB
AVDD supply, fPS = 50 Hz and 60 Hz
IOVDD supply, fPS = 50 Hz and 60 Hz
fIN = 50 Hz and 60 Hz
PSRR
Power-supply rejection ratio
Crosstalk
105
–125
fIN = 50 Hz or 60 Hz, VREF = 2.442 V, VIN = –20 dBFS,
normalized
111
115
SNR
Signal-to-noise ratio
dB
fIN = 50 Hz or 60 Hz, VREF = 4.0 V, VIN = –20 dBFS,
normalized
fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS,
ADS131A02
–101.5
THD
Total harmonic distortion
Signal-to-noise + distortion
Spurious-free dynamic range
dB
dB
dB
fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS,
ADS131A04
–103.5
101
SINAD
SFDR
fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS
fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS,
ADS131A02
102.5
fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS,
ADS131A04
105
EXTERNAL REFERENCE
Reference buffer offset
TA = 25°C
250
4
µV
µV/°C
MΩ
Reference buffer offset drift
REFEXT input impedance
–40°C ≤ TA ≤ +125°C
7
50
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Electrical Characteristics (continued)
Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C. All
specifications are at IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF
2.442 V, fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, and gain = 1 (unless otherwise noted).
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE VOLTAGE (REFP – REFN)
VREF_4V bit = 0
2.442
4.0
VREF
Reference output voltage
V
VREF_4V bit = 1, AVDD – AVSS > 4.5 V
Accuracy
±0.1%
6
Temperature drift
Including reference buffer drift, –40°C ≤ TA ≤ +125°C
REFEXT = 1-µF to AVSS, settled to 1%
20 ppm/°C
0.2
Start-up time
REFEXT = 1-µF to AVSS, settled to 0.1%
REFEXT = 1-µF to AVSS, settled to 0.01%
1.2
ms
µA
250
100
REFP source capability
EXTERNAL CLOCK SOURCE
Internal ICLK frequency (SCLK output
fICLK
CLKSRC bit = 0
0.2
8.192
12.5
MHz
MHz
in master mode)
VNCPEN bit = 0
High-resolution mode
0.1
0.512
0.1
4.096
4.096
1.024
1.024
4.25
4.25
1.05
1.05
VNCPEN bit = 1
fMOD
ADC modulator frequency
VNCPEN bit = 0
Low-power mode
VNCPEN bit = 1
0.512
DIGITAL INPUT/OUTPUT
VIH
VIL
High-level input voltage
0.8 IOVDD
GND
IOVDD
V
V
Low-level input voltage
High-level output voltage
Low-level output voltage
Input current
0.2 IOVDD
VOH
VOL
IIN
IOH = 1 mA
0.8 IOVDD
V
IOL = –1 mA
0.2 IOVDD
10
V
0 V < VDigital Input < IOVDD
–10
μA
POWER-SUPPLY
VNCP Negative charge pump output voltage
–2
–1.65
V
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
3.2
ADS131A02, high-resolution
mode
Negative charge pump
disabled
3
4
4
3.75
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
AVDD current
mA
ADS131A04, high-resolution
mode
Negative charge pump
disabled
4.7
ADS131A02, low-power mode
ADS131A04, low-power mode
0.9
1.1
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
0.6
0.6
0.8
0.8
ADS131A02, high-resolution
mode
Negative charge pump
disabled
0.8
1.0
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
IOVDD current
mA
ADS131A04, high-resolution
mode
Negative charge pump
disabled
ADS131A02, low-power mode
ADS131A04, low-power mode
0.5
0.5
10
Copyright © 2016–2018, Texas Instruments Incorporated
ADS131A02, ADS131A04
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ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
Electrical Characteristics (continued)
Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C. All
specifications are at IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF
2.442 V, fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, and gain = 1 (unless otherwise noted).
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
12.5
ADS131A02, high-resolution
mode
Negative charge pump
disabled
17
15.8
22.7
4.6
21
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
ADS131A04, high-resolution
mode
Negative charge pump
disabled
26.8
Power dissipation
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
mW
ADS131A02, low-power
mode
Negative charge pump
disabled
6.5
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
5.3
ADS131A04, low-power
mode
Negative charge pump
disabled
7.2
2.6
Standby mode, fCLKIN = 16.384 MHz
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7.6 Timing Requirements: Asynchronous Interrupt Interface Mode
over operating ambient temperature range (unless otherwise noted)
1.65 V ≤ IOVDD ≤ 2.7 V
2.7 V < IOVDD ≤ 3.6 V
MIN
64
88
32
44
16
5
MAX
MIN
40
56
20
28
16
4
MAX
UNIT
Single device
tc(CLKIN)
External clock period
ns
Multiple device chaining
Single device
Pulse duration,
CLKIN high or low
tw(CP)
ns
Multiple device chaining
td(CSSC)
td(SCS)
Delay time, CS falling edge to first SCLK rising edge
Delay time, SCLK falling edge to CS falling edge
ns
ns
Single device
SCLK period
64
88
32
44
5
40
64
20
32
5
tc(SC)
ns
ns
Multiple device chaining
Single device
Pulse duration,
tw(SCHL)
SCLK high or low
Multiple device chaining
td(SCCS)
tsu(DI)
Delay time, final SCLK falling edge to CS rising edge
Setup time, DIN valid before SCLK falling edge
Hold time, DIN valid after SCLK falling edge
Pulse duration, CS high
ns
ns
ns
ns
ns
5
5
th(DI)
8
8
tw(CSH)
tw(RSL)
20
800
15
800
Pulse duration, RESET low
7.7 Switching Characteristics: Asynchronous Interrupt Interface Mode
over operating ambient temperature range (unless otherwise noted)
1.65 V ≤ IOVDD ≤ 2.7 V
2.7 V < IOVDD ≤ 3.6 V
MIN
MAX
MIN
MAX
UNIT
Propagation delay time,
first SCLK rising edge to DOUT driven
tp(SCDOD)
tp(SCDO)
28
26
15
ns
Propagation delay time,
SCLK rising edge to valid new DOUT
15
ns
HIZDLY = 00
6
8
30
37
43
47
33
39
44
48
6
8
20
27
43
47
21
27
32
36
HIZDLY = 01
HIZDLY = 10
HIZDLY = 11
DNDLY = 00
DNDLY = 01
DNDLY = 10
DNDLY = 11
Hold time, last SCLK falling edge
to DOUT 3-state
th(LSB)
ns
10
12
6
10
12
6
8
8
Propagation delay time, SCLK
falling edge to DONE falling edge
tp(DN)
ns
10
12
10
12
Propagation delay time,
CS rising edge to DONE rising edge
tp(CSDN)
tp(CSDR)
td(RSSC)
32
32
ns
tICLK
ms
Propagation delay time,
CS rising edge to DRDY rising edge
2.0
2.0
Delay time,
RESET rising edge to READY response
4.5
4.5
12
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ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
7.8 Timing Requirements: Synchronous Master Interface Mode
over operating ambient temperature range (unless otherwise noted)
1.65 V ≤ IOVDD ≤ 2.7 V
2.7 V < IOVDD ≤ 3.6 V
MIN
64
88
32
44
2
MAX
MIN
40
56
20
28
2
MAX
UNIT
Single device
tc(CLKIN)
External clock period
ns
Multiple device chaining
Single device
Pulse duration,
CLKIN high or low
tw(CP)
ns
Multiple device chaining
tc(SC)
SCLK period
tCLKIN
tCLKIN
ns
tw(SCHL)
tsu(DI)
th(DI)
Pulse duration, SCLK high or low
1
1
Setup time, DIN valid before SCLK falling edge
Hold time, DIN valid after SCLK falling edge
Pulse duration, RESET low
5
5
8
8
ns
tw(RSL)
800
800
ns
7.9 Switching Characteristics: Synchronous Master Interface Mode
over operating ambient temperature range (unless otherwise noted)
1.65 V ≤ IOVDD ≤ 2.7 V
2.7 V < IOVDD ≤ 3.6 V
MIN
MAX
MIN
MAX
UNIT
Propagation delay time,
first SCLK rising edge to DOUT driven
tp(SCDOD)
tp(SCDO)
tp(SDR)
28
15
15
ns
Propagation delay time,
SCLK rising edge to valid new DOUT
26
ns
ns
Propagation delay time,
SCLK falling edge to DRDY falling edge
31
20
HIZDLY = 00
6
8
30
37
43
47
33
39
44
48
6
8
20
27
43
47
21
27
32
36
HIZDLY = 01
HIZDLY = 10
HIZDLY = 11
DNDLY = 00
DNDLY = 01
DNDLY = 10
DNDLY = 11
Hold time, last SCLK falling edge
to DOUT 3-state
th(LSB)
ns
ns
10
12
6
10
12
6
8
8
Propagation delay time, SCLK
falling edge to DONE falling edge
tp(DN)
10
12
10
12
Propagation delay time,
CS rising edge to DONE rising edge
tp(CSDN)
tp(DRS)
32
17
32
15
ns
ns
Delay time,
last SCLK rising edge to DRDY rising edge
Delay time,
RESET rising edge to READY response
td(RSSC)
4.5
4.5
ms
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7.10 Timing Requirements: Synchronous Slave Interface Mode
over operating ambient temperature range (unless otherwise noted)
1.65 V ≤ IOVDD ≤ 2.7 V
2.7 V < IOVDD ≤ 3.6 V
MIN
64
88
32
44
6
MAX
MIN
40
56
20
28
4
MAX
UNIT
Single device
tc(CLKIN)
External clock period(1)
ns
Multiple device chaining
Single device
Pulse duration,
tw(CP)
ns
CLKIN high or low(1)
Multiple device chaining
td(SCS)
Delay time, SCLK falling edge to CS falling edge
Delay time, CS falling edge to first SCLK rising edge
ns
ns
td(CSSC)
16
64
88
32
44
5
16
40
64
20
32
5
Single device
SCLK period
tc(SC)
ns
ns
Multiple device chaining
Single device
Pulse duration,
SCLK high or low
tw(SCHL)
Multiple device chaining
tsu(DI)
th(DI)
Setup time, DIN valid before SCLK falling edge
Hold time, DIN valid after SCLK falling edge
Delay time, last SCLK falling edge to CS rising edge
ns
ns
ns
8
6
td(SCCS)
5
5
Setup time, DRDY falling edge to master clock falling
edge
tsu(sync)
10
10
ns
ns
th(sync)
tDATA
Hold time, DRDY low after master clock falling edge
Data rate period
10
10
Set by the CLK1 register and the CLK2 register
tw(RSL)
Pulse duration RESET low
800
800
ns
(1) Only valid if CLKSRC = 0
7.11 Switching Characteristics: Synchronous Slave Interface Mode
over operating ambient temperature range (unless otherwise noted)
1.65 V ≤ IOVDD ≤ 2.7 V
2.7 V < IOVDD ≤ 3.6 V
MIN
MAX
MIN
MAX
UNIT
Propagation delay time,
first SCLK rising edge to DOUT driven
tp(SCDOD)
tp(SCDO)
28
15
15
ns
Propagation delay time,
SCLK rising edge to valid new DOUT
26
ns
HIZDLY = 00
6
8
30
37
43
47
33
39
44
48
6
8
20
27
43
47
21
27
32
36
HIZDLY = 01
HIZDLY = 10
HIZDLY = 11
DNDLY = 00
DNDLY = 01
DNDLY = 10
DNDLY = 11
Hold time, last SCLK falling edge
to DOUT 3-state
th(LSB)
ns
10
12
6
10
12
6
8
8
Propagation delay time, SCLK
falling edge to DONE falling edge
tp(DN)
ns
10
12
10
12
Propagation delay time,
CS rising edge to DONE rising edge
tp(CSDN)
td(RSSC)
32
32
ns
Delay time,
RESET rising edge to READY response
4.5
4.5
ms
14
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ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
tw(CP)
tc(CLKIN)
CLKIN
DRDY
CS
tp(CSDR)
td(SCCS)
td(CSSC)
td(SCS)
tc(SC)
tw(CSH)
tw(SCHL)
SCLK
DIN
tsu(DI)
th(DI)
tp(SCDOD)
MSB
tp(SCDO)
th(LSB)
MSB - 1
LSB + 1
LSB
DOUT
NOTE: SPI settings are CPOL = 0 and CPHA = 1. CS transitions must take place when SCLK is low.
Figure 1. Asynchronous Interrupt Mode SPI Timing Diagram
tw(CP)
tc(CLKIN)
CLKIN
DRDY
tc(SC)
tp(SDR)
SCLK
tp(DRS)
tw(SCHL)
tsu(DI)
th(DI)
DIN
tp(SCDO)
tp(SCDOD)
MSB
th(LSB)
MSB - 1
LSB + 1
LSB
DOUT
NOTE: SPI settings are CPOL = 0 and CPHA = 1.
Figure 2. Synchronous Master Mode SPI Timing Diagram
tw(CP)
tc(CLKIN)
CLKIN
CS
td(CSSC)
tc(SC)
tp(SCCS)
td(SCS)
tw(SCHL)
SCLK
DIN
tsu(DI)
th(DI)
tp(SCDO)
tp(SCDOD)
MSB
th(LSB)
MSB - 1
LSB + 1
LSB
DOUT
NOTE: SPI settings are CPOL = 0 and CPHA = 1. CS can be tied directly to DRDY.
Figure 3. Synchronous Slave Mode SPI Timing Diagram
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Optional Pulse
Optional Pulse
tDATA
tDATA
DRDY
tsu(sync)
th(sync)
CLKIN
Figure 4. DRDY Synchronization Timing for Synchronous Slave Mode (CLKSRC = 0)
Optional Pulse
Optional Pulse
tDATA
tDATA
DRDY
tsu(sync)
th(sync)
SCLK
Figure 5. DRDY Synchronization Timing for Synchronous Slave Mode (CLKSRC = 1)
DONE
tp(CSDN)
CS
tp(DN)
SCLK
LSB + 1
LSB
DIN, DOUT
Figure 6. DONE Signal Timing
tw(RSL)
RESET
or
RESET
DIN
td(RSSC)
Ready
DOUT
Figure 7. RESET Pin and Command Timing
16
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ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
7.12 Typical Characteristics
at TA = 25°C, IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF = 2.442 V,
fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, HR mode, and gain = 1 (unless otherwise noted)
25
20
15
10
5
16000
14000
12000
10000
8000
6000
4000
2000
0
0
-5
-10
-15
-20
-25
-10
-5
0
5
10
0
1
2
3
4
5
6
7
8
D001
Input Referred Voltage (mV)
Time (s)
D008
Shorted inputs, 1 kSPS, 65536 points, offset removed
Shorted inputs, 65536 points
Figure 8. Input-Referred Noise vs Time
Figure 9. Single Device Noise Histogram
75
30000
25000
20000
15000
10000
5000
0
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
-20
-15
-10
-5
0
5
10
15
20
18
18.1
18.2
18.3
18.4
D001
D001
Input Referred Voltage (mV)
Effective Number of Bits
Shorted inputs, 8 kSPS, 262144 points, offset removed
Shorted inputs, 8 kSPS, 560 devices, multiple lots
Figure 10. Single Device Noise Histogram
Figure 11. Multiple Device Effective Resolution Histogram
0
0
-20
-40
-60
-80
-20
-40
-60
-80
-100
-100
-120
-140
-160
-180
-120
-140
-160
-180
0
500 1000 1500 2000 2500 3000 3500 4000
0
500 1000 1500 2000 2500 3000 3500 4000
Frequency (Hz)
Frequency (Hz)
D011
D012
fIN = 60 Hz, 32768 points
fIN = 60 Hz, 32768 points
Figure 12. THD FFT Plot at 8 kSPS and –0.5 dBFS
Figure 13. THD FFT Plot at 8 kSPS and –20 dBFS
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Typical Characteristics (continued)
at TA = 25°C, IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF = 2.442 V,
fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, HR mode, and gain = 1 (unless otherwise noted)
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Frequency (Hz)
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (Hz)
D001
D029
fIN = 60 Hz, 8 kSPS
fIN = 60 Hz, 32768 points
Figure 14. Low-Frequency FFT Plot
Figure 15. THD FFT Plot at 16 kSPS and –0.5 dBFS
-90
-95
0
-20
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-40
-60
-80
-100
-120
-140
-160
-180
0
500 1000 1500 2000 2500 3000 3500 4000
0
1000 2000 3000 4000 5000 6000 7000 8000
Input Frequency (Hz)
Frequency (Hz)
D001
D028
fIN = 60 Hz, 32768 points
Figure 17. THD vs Input Frequency
Figure 16. THD FFT Plot at 16 kSPS and –20 dBFS
4
3
5.4
5.2
5
Ta = -40
Ta = 25
Ta = 125
2
1
0
-1
-2
-3
-4
-5
-6
-7
4.8
4.6
4.4
Ch 1
Ch 2
Ch 3
Ch 4
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
-50
-25
0
25
50
75
100
125
Input Voltage (V)
Temperature (èC)
D001
D018
Figure 18. INL vs Temperature
Figure 19. Noise RMS vs Temperature
18
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ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
Typical Characteristics (continued)
at TA = 25°C, IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF = 2.442 V,
fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, HR mode, and gain = 1 (unless otherwise noted)
900
800
700
600
500
400
0.05
0.025
0
Ch 1
Ch 2
Ch 3
Ch 4
-0.025
Ch 1
Ch 2
Ch 3
Ch 4
-0.05
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D020
D021
Figure 20. Offset Error vs Temperature
Figure 21. Gain Error vs Temperature
2.448
2.446
2.444
2.442
2.44
112
111.5
111
110.5
110
109.5
109
108.5
108
Ta = -40èC
Ta = 25èC
Ta = 125èC
107.5
107
-50
-25
0
25
50
75
100
125
-120
-100
-80
-60
-40
-20
0
Temperature (èC)
Input Voltage (dBFS)
D013
D001
30 units, multiple lots
Figure 22. Internal VREF vs Temperature
Figure 23. Normalized SNR vs Amplitude
140
130
120
110
100
90
-100
-105
-110
-115
-120
-125
-130
-135
Ta = -40èC
Ta = 25èC
Ta = 125èC
Ta = -40 èC
Ta = 25 èC
Ta = 125 èC
-35
-30
-25
-20
-15
-10
-5
0
0
2000
4000
6000
8000
Input Voltage (dBFS)
Frequency (Hz)
D001
D009
Figure 24. Normalized THD vs Amplitude
Figure 25. CMRR vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF = 2.442 V,
fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, HR mode, and gain = 1 (unless otherwise noted)
120
40
35
30
25
20
15
10
5
Channel 1
Channel 2
Channel 3
Channel 4
100
80
60
40
20
0
AVDD
IOVDD
0
-135
-130
-125
-120
10 20
100
1000
10000 100000 1000000 1E+7
Frequency (Hz)
D001
Crosstalk (dB)
D019
Figure 27. Crosstalk Histogram
Figure 26. PSRR vs Frequency
141.3
141.2
141.1
141
7000
6500
6000
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
140.9
140.8
140.7
140.6
140.5
140.4
140.3
140.2
140.1
140
0
0
1000000
2000000
fMOD (Hz)
3000000
4000000
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D001
D001
Figure 28. Differential Input Impedance vs
Modulator Clock
Figure 29. Differential Input Impedance vs
Temperature at 4.096-MHz fMOD
564.5
564
4500
4000
3500
3000
2500
2000
1500
1000
500
563.5
563
562.5
562
561.5
561
560.5
560
ADS131A04 LPM
ADS131A04 HRM
559.5
559
0
-40
-20
0
20
40
60
80
100
120
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Temperature (èC)
fMOD (MHz)
D001
D001
LPM = low-power mode, HRM = high-resolution mode
Figure 30. Differential Input Impedance vs
Temperature at 1.024-MHz fMOD
Figure 31. ADS131A04 AVDD Current vs fMOD
20
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ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
Typical Characteristics (continued)
at TA = 25°C, IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF = 2.442 V,
fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, HR mode, and gain = 1 (unless otherwise noted)
900
800
700
600
500
400
300
200
100
0
3600
3300
3000
2700
2400
2100
1800
1500
1200
900
ADS131A04 LPM
ADS131A04 HRM
ADS131A02 HRM
ADS131A02 LPM
600
300
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
fMOD (MHz)
fMOD (MHz)
D001
D001
LPM = low-power mode, HRM = high-resolution mode
LPM = low-power mode, HRM = high-resolution mode
Figure 32. ADS131A04 IOVDD Current vs fMOD
Figure 33. ADS131A02 AVDD Current vs fMOD
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
ADS131A02 HRM
ADS131A02 LPM
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
fMOD (MHz)
D001
LPM = low-power mode, HRM = high-resolution mode
Figure 34. ADS131A02 IOVDD Current vs fMOD
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8 Parameter Measurement Information
8.1 Noise Measurements
Adjust the data rate and gain to optimize the ADS131A02 and ADS131A04 noise performance. When averaging
is increased by reducing the data rate, noise drops correspondingly. Table 1 and Table 2 summarize the
ADS131A0x noise performance with a 2.442-V reference and a 3.3-V analog power supply. Table 3 and Table 4
summarize the ADS131A02 and ADS131A04 noise performance with a 4.0-V reference and a 5-V analog power
supply (or using ±2.5-V bipolar analog power supplies). The data are representative of typical noise performance
at TA = 25°C when fMOD = 4.096 MHz. The data shown are typical results with the analog inputs shorted together
and taking an average of multiple readings across all channels. A minimum 1 second of consecutive readings are
used to calculate the RMS noise for each reading. The data are also representative of the ADS131A0x noise
performance when using a low-noise external reference, such as the REF5025 or REF5040. The effective
resolution data and dynamic range data in Table 1, Table 2, Table 3, and Table 4 are calculated using
Equation 1 and Equation 2. The μVrms noise numbers in the tables are input-referred.
≈
∆
«
’
÷
2ì VREF
Gainì VRMS ◊
Effective Resolution = log2
(1)
(2)
≈
’
VREF
Dynamic Range = 20ìlog
∆
∆
«
÷
÷
2 ìGainì VRMS ◊
22
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ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
Noise Measurements (continued)
Table 1. Dynamic Range, Effective Resolution, and Noise in μVrms at 3.3-V Analog Supply, and 2.442-V
Reference for Gain = 1, 2, and 4
GAIN
x1
x2
x4
fDATA AT
4.096-MHz
fMOD (kHz)
EFFECTIVE
RESOLUTION
(Bits)
EFFECTIVE
RESOLUTION
(Bits)
EFFECTIVE
RESOLUTION
(Bits)
OSR
SETTING
DYNAMIC
RANGE (dB)
DYNAMIC
RANGE (dB)
DYNAMIC
RANGE (dB)
μVrms
1.82
μVrms
1.82
μVrms
1.70
4096
2048
1024
800
768
512
400
384
256
200
192
128
96
1.000
2.000
119.49
116.47
113.85
112.93
112.90
110.73
109.74
109.53
107.74
106.48
106.28
104.05
101.90
97.63
21.35
20.85
20.41
20.26
20.25
19.89
19.73
19.70
19.40
19.19
19.16
18.78
18.43
17.72
16.88
15.62
113.49
110.97
107.91
106.72
106.69
104.83
103.69
103.65
101.67
100.55
100.17
97.98
20.35
19.94
19.43
19.23
19.22
18.91
18.72
18.72
18.39
18.20
18.14
17.78
17.44
16.72
15.89
14.62
108.08
105.22
101.77
101.05
100.76
98.75
97.76
97.58
95.72
94.54
94.11
92.00
89.90
85.52
80.59
73.02
19.46
18.98
18.41
18.29
18.24
17.91
17.74
17.71
17.40
17.21
17.13
16.78
16.43
15.71
14.89
13.61
2.58
2.44
2.36
4.000
3.49
3.47
3.52
5.120
3.88
3.98
3.82
5.333
3.90
3.99
3.95
8.000
5.01
4.95
4.97
10.240
10.667
16.000
20.480
21.333
32.000
42.667
64.000
85.333
128.000
5.61
5.64
5.58
5.75
5.66
5.69
7.07
7.11
7.06
8.17
8.09
8.08
8.36
8.45
8.49
10.81
13.85
22.64
40.50
96.82
10.88
13.74
22.64
40.22
97.12
10.82
13.79
22.83
40.26
97.51
95.95
64
91.61
48
92.58
86.62
32
85.12
78.96
Table 2. Dynamic Range, Effective Resolution, and Noise in μVrms at 3.3-V Analog Supply, and 2.442-V
Reference for Gain = 8 and 16
GAIN
x8
x16
fDATA AT 4.096-MHz
fMOD (kHz)
DYNAMIC RANGE
(dB)
EFFECTIVE
RESOLUTION (Bits)
DYNAMIC RANGE
(dB)
EFFECTIVE
RESOLUTION (Bits)
OSR SETTING
μVrms
1.77
μVrms
1.82
4096
2048
1024
800
768
512
400
384
256
200
192
128
96
1.000
2.000
101.72
98.88
95.97
95.03
94.63
92.75
91.84
91.52
89.57
88.44
88.26
86.02
83.91
79.52
74.60
66.93
18.40
17.93
17.44
17.29
17.22
16.91
16.76
16.70
16.38
16.19
16.16
15.79
15.44
14.71
13.89
12.62
95.45
93.07
89.82
88.66
88.41
87.00
85.62
85.50
83.58
82.45
82.12
79.80
77.72
73.45
68.47
60.97
17.36
16.96
16.42
16.23
16.19
15.95
15.72
15.70
15.38
15.20
15.14
14.76
14.41
13.70
12.87
11.61
2.45
2.39
4.000
3.43
3.48
5.120
3.82
3.98
5.333
4.00
4.09
8.000
4.96
4.81
10.240
10.667
16.000
20.480
21.333
32.000
42.667
64.000
85.333
128.000
5.51
5.64
5.72
5.72
7.16
7.14
8.16
8.12
8.32
8.44
10.77
13.74
22.78
40.14
97.05
11.02
14.00
22.92
40.66
97.61
64
48
32
Copyright © 2016–2018, Texas Instruments Incorporated
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www.ti.com.cn
Table 3. Dynamic Range, Effective Resolution, and Noise in μVrms at ±2.5-V Analog Supply, and 4.0-V
Reference for Gain = 1, 2, and 4
GAIN
x1
x2
x4
fDATA AT
4.096-MHz
fMOD (kHz)
EFFECTIVE
RESOLUTION
(Bits)
EFFECTIVE
RESOLUTION
(Bits)
EFFECTIVE
RESOLUTION
(Bits)
OSR
SETTING
DYNAMIC
RANGE (dB)
DYNAMIC
RANGE (dB)
DYNAMIC
RANGE (dB)
μVrms
1.66
μVrms
1.64
μVrms
1.71
4096
2048
1024
800
768
512
400
384
256
200
192
128
96
1.000
2.000
124.55
121.47
118.44
117.58
116.75
115.16
114.15
113.88
112.09
110.71
110.13
106.93
104.17
98.84
22.19
21.68
21.18
21.03
20.89
20.63
20.46
20.42
20.12
19.89
19.79
19.26
18.80
17.92
17.00
15.64
118.69
114.98
112.48
111.46
110.88
109.23
108.33
107.83
105.76
104.65
104.10
100.76
98.18
21.22
20.60
20.18
20.02
19.92
19.65
19.50
19.41
19.07
18.88
18.79
18.24
17.81
16.91
16.03
14.60
112.32
109.58
106.31
105.29
105.06
103.10
102.28
101.70
99.83
20.16
19.70
19.16
18.99
18.95
18.63
18.49
18.39
18.08
17.84
17.78
17.21
16.78
15.87
15.01
13.67
2.38
2.51
2.34
4.000
3.37
3.36
3.41
5.120
3.72
3.77
3.84
5.333
4.10
4.03
3.94
8.000
4.93
4.88
4.94
10.240
10.667
16.000
20.480
21.333
32.000
42.667
64.000
85.333
128.000
5.53
5.41
5.43
5.71
5.73
5.80
7.02
7.27
7.19
8.22
8.27
98.37
8.51
8.79
8.80
97.99
8.90
12.72
17.47
32.27
61.06
156.92
12.94
17.41
32.58
59.91
160.84
94.59
13.15
17.74
33.40
60.74
153.69
92.00
64
92.74
86.50
48
93.30
87.45
81.31
32
85.10
78.87
73.35
Table 4. Dynamic Range, Effective Resolution, and Noise in μVrms at ±2.5-V Analog Supply, and 4.0-V
Reference for Gain = 8 and 16
GAIN
x8
x16
fDATA AT 4.096-MHz
fMOD (kHz)
DYNAMIC RANGE
(dB)
EFFECTIVE
RESOLUTION (Bits)
DYNAMIC RANGE
(dB)
EFFECTIVE
RESOLUTION (Bits)
OSR SETTING
μVrms
1.70
μVrms
1.63
4096
2048
1024
800
768
512
400
384
256
200
192
128
96
1.000
2.000
106.35
103.40
100.46
99.53
99.19
97.31
96.23
95.84
93.87
92.70
92.10
88.58
86.27
80.60
75.29
67.06
19.17
18.68
18.19
18.04
17.98
17.67
17.49
17.42
17.09
16.90
16.80
16.22
15.83
14.89
14.01
12.64
100.66
97.37
94.59
93.28
93.09
91.08
90.16
89.85
87.73
86.43
85.68
82.42
80.00
74.48
69.10
61.17
18.22
17.68
17.21
17.00
16.97
16.63
16.48
16.43
16.07
15.86
15.73
15.19
14.79
13.87
12.98
11.64
2.38
2.39
4.000
3.35
3.29
5.120
3.72
3.83
5.333
3.87
3.91
8.000
4.81
4.93
10.240
10.667
16.000
20.480
21.333
32.000
42.667
64.000
85.333
128.000
5.45
5.48
5.70
5.68
7.15
7.25
8.18
8.41
8.77
9.17
13.14
17.15
32.92
60.68
156.51
13.36
17.64
33.31
61.90
156.32
64
48
32
24
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ADS131A02, ADS131A04
www.ti.com.cn
ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
9 Detailed Description
9.1 Overview
The ADS131A02 and ADS131A04 are low-power, two- and four-channel, simultaneous-sampling, 24-bit, delta-
sigma (ΔΣ), analog-to-digital converters (ADCs) with an integrated low-drift internal reference voltage. Data rate
flexibility, wide dynamic range, and interface options make these devices good choices when designing for
smart-grid and other industrial power monitor, control, and protection applications. The ADC interface data
integrity features provide for a very low rate of transmission errors. Throughout this document, the ADS131A02
and ADS131A04 are referred to as the ADS131A0x.
The ADS131A0x has very flexible power-supply options. A 5-V single-supply (or ±2.5-V bipolar-supply) operation
is available to support up to a 4.5-V external reference to maximize the dynamic range of the converter.
Alternatively, a negative charge pump can be enabled to accept absolute input signals down to –1.5 V below
ground when powered from a single 3.3-V supply. Five gain options are available to help maximize the ADC
code range and 16 selectable oversampling ratio (OSR) options are selectable to optimize the converter for a
specific data rate. The low-drift internal reference can be programmed to either 2.442 V or 4 V. Input signal out-
of-range detection can be accomplished by using the integrated comparators, with programmable trigger-point
settings. A detailed diagram of the ADS131A0x is shown in the Functional Block Diagram section.
The device offers multiple serial peripheral interface (SPI) communication options to provide flexibility for
interfacing to microprocessors or field-programmable gate arrays (FPGAs). Synchronous real-time and
asynchronous interrupt communication modes are available using the SPI-compatible interface. Multiple devices
can share a common SPI port and are synchronized by using the DRDY signal. Device communication is
specified through configuration of the M0 interface mode pin and chaining of the DONE signal. Optional cyclic
redundancy check (CRC) and hamming code correction on the interface enhance communication integrity.
9.2 Functional Block Diagram
AVDD
IOVDD
REFP REFN
REFEXT
Reference
Mux
Voltage
Reference
Out-of-Range
Detect
M[2:0]
RESET
AIN1N
AIN1P
AIN2N
AIN2P
AIN3N
AIN3P
AIN4N
AIN4P
DS ADC
CS
Control and
Serial Interface
SCLK
DIN
DOUT
DRDY
DS ADC
Watchdog
Timer
DONE
DS ADC
DS ADC
Data Integrity
CLK/XTAL
Negative
Charge
Pump
XTAL1/CLKIN
XTAL2
GND
VNCP
AVSS
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ADS131A02, ADS131A04
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www.ti.com.cn
9.3 Feature Description
This section contains details of the ADS131A0x internal feature elements. The ADC clocking is discussed first,
followed by the analog blocks and the digital filter.
9.3.1 Clock
Multiple clocks are created from one external master clock source in the ADS131A0x to create device
configuration flexibility. The ADC operates from the internal system clock, ICLK, which is provided in one of three
ways.
•
•
•
An external master clock, CLKIN, can be applied directly to the XTAL1/CLKIN pin to be divided down to
generate ICLK using the CLK_DIV[2:0] bits in the CLK1 register. In this case, leave the XTAL2 pin floating.
A crystal oscillator can be applied between XTAL1/CLKIN and XTAL2, generating a master clock to be
divided down using the CLK_DIV[2:0] bits in the CLK1 register to generate ICLK.
A free-running SCLK can be internally routed to be set as ICLK. This mode is only available in synchronous
slave interface mode. Tie the CLKIN/XTAL1 pin to GND. Leave the XTAL2 pin unconnected.
The system ICLK is passed through a second 3-bit clock divider (ICLK_DIV[2:0] in the CLK2 register) to create
the modulator clock, MODCLK. MODCLK is used for timing of the delta-sigma (ΔΣ) modulator sampling and
digital filter.
The interface operation mode determines the options for sourcing ICLK. When in asynchronous interrupt or
synchronous master mode, generate ICLK by applying a direct external master clock signal to the XTAL1/CLKIN
pin or by using a crystal oscillator across the XTAL1/CLKIN and XTAL2 pins. If directly applying a master clock to
the XTAL1/CLKIN pin, leave XTAL2 floating. In synchronous slave mode, a free-running SCLK line can be
connected directly into the ICLK_DIV block in place of the divided XTAL or CLKIN source. Use the CLKSRC bit
in the CLK1 register to select between the XTAL1/CLKIN or SCLK input as the master clock source for the ADC.
The CLKSRC bit must be set prior to powering up the ADC channels. Using SCLK as ICLK is useful in galvanic
isolated applications to limit the digital I/O lines crossing the isolation barrier. Figure 35 shows the clock dividers
and clocking names.
AINxP
ADC
Sinc3 LPF
CS
AINxN
DONE
DIN
DOUT
CLKSRC
M
XTAL1/CLKIN
XTAL2
fCLKIN
fICLK
X
CLK_DIV
[2:0]
ICLK_DIV
[2:0]
OSR
[3:0]
SPI
+
fDATA
fMOD
Ctrl
DRDY
SCLK
sync
M0
Figure 35. ADC Clock Generation
26
Copyright © 2016–2018, Texas Instruments Incorporated
ADS131A02, ADS131A04
www.ti.com.cn
ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
Feature Description (continued)
9.3.1.1 XTAL1/CLKIN and XTAL2
XTAL1/CLKIN is the external clock input to the ADC and can be supplied from a clock source or by using a
crystal (along with the XTAL2 pin). Figure 36 shows the configuration for the two clock input options.
XTAL1/CLKIN
XTAL2
XTAL2
XTAL1/CLKIN
16.384-MHz
Clock
50 Ω
a) External Clock Mode
b) Crystal Oscillator Mode
Figure 36. Clock Mode Configurations
Input the clock directly to the XTAL1/CLKIN pin and leave the XTAL2 pin floating when using a direct clock
source.
Connect the crystal and load capacitors as shown in Figure 36b to the XTAL1/CLKIN and XTAL2 pins. Place the
crystal and crystal load capacitors close to the ADC pins using short, direct traces. Connect the load capacitors
to the digital ground. Do not connect any other external circuit to the crystal oscillator. Table 5 lists recommended
crystals for use with the ADS131A0x. The crystal oscillator start-up time is typically 5 ms, but can be longer
depending on the crystal characteristics.
Table 5. Recommended Crystals
OPERATING TEMPERATURE
MANUFACTURER
Abracon
FREQUENCY
16.384 MHz
16.384 MHz
16.384 MHz
RANGE
PART NUMBER
–40°C to +125°C
–40°C to +85°C
–40°C to +85°C
ABLS-16.384MHZ-L4Q-T
ABM3C-16.384MHZ-D4Y-T
ECS-163-18-5PXEN-TR
Abracon
ECS
9.3.1.2 ICLK
ICLK is the internal system clock to the ADC. ICLK is derived from CLKIN set through the CLK_DIV[2:0] bits in
the CLK1 register or is set as SCLK when operating in synchronous slave mode. ICLK is used as the SCLK
output when operating in synchronous master mode in addition to being used for the internal ADC clock timing.
Use the CLKSRC bit to set the source for ICLK.
9.3.1.3 MODCLK
MODCLKis the modulator clock used for the ADC sampling. MODCLK is derived from ICLK set through the
ICLK_DIV[2:0] bits in the CLK2 register. Verify that the fMOD minimum and maximum limits are met in the
Electrical Characteristics table by adjusting the CLK_DIV[2:0] and ICLK_DIV[2:0] clock dividers.
9.3.1.4 Data Rate
The data rate is the rate at which conversion results are generated by the ADC. In a delta-sigma ADC, the
oversampling ratio (OSR) is the ratio between the modulator frequency and the output data rate. The OSR[3:0]
bits in the CLK2 register set the OSR on the ADS131A0x. The output data rate is the frequency of MODCLK
(fMOD) divided by the OSR.
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9.3.2 Analog Input
The ADS131A0x analog inputs are directly connected to the switched-capacitor sampling network of the ΔΣ
modulator without a multiplexer or integrated buffer. The device inputs are measured differentially (VIN = VAINxP
–
VAINxN) and can span from –VREF / Gain to VREF / Gain. Figure 38 shows a conceptual diagram of the modulator
circuit charging and discharging the sampling capacitor through switches, although the actual implementation is
slightly different. The timing for switches S1 and S2, as shown in Figure 37, are 180 degrees out-of-phase of one
another.
tMOD = 1 / fMOD
On
S1
Off
On
S2
Off
Figure 37. S1 and S2 Switch Timing
Electrostatic discharge (ESD) circuitry protects the inputs. Figure 38 shows a simplified representation of the
ESD circuit. Protection for input voltages exceeding AVDD can be modeled as a simple diode.
The negative charge pump voltage, VNCP, controls the voltage at which the low-side protection devices begin
conducting. Tie VNCP to AVSS if the charge pump is not used to ensure the clamping voltage is properly set.
The charge pump cannot provide a large amount of current. The mechanism shown in Figure 38 ensures current
provided by the charge pump is limited in the case of an overvoltage event.
AVDD
VNCP
AINxP
S1
S2
Cs
2
AINxN
S1
VNCP
AVDD
Figure 38. Equivalent Analog Input Circuitry
To prevent the ESD diodes from being enabled, the absolute voltage on any input must stay within the range
provided by Equation 3 when the internal charge pump is disabled and within the range in Equation 4 when the
internal charge pump is enabled:
AVSS – 0.3 V < VAINxP or VAINxN < AVDD + 0.3 V
AVSS – 1.65 V < VAINxP or VAINxN < AVDD + 0.3 V
(3)
(4)
If the voltages on the input pins have any potential to violate these conditions, external clamp diodes or series
resistors may be required to limit the input currents to safe values (see the Absolute Maximum Ratings table).
The charging of the input capacitors draws a transient current from the sensor driving the ADS131A0x inputs.
The average value of this current can be used to calculate an effective impedance of ZIN, where ZIN = VIN
/
IAVERAGE. This effective input impedance is a function of the modulator sampling frequency and Equation 5 can
be used to calculate an estimate value. When using fMOD = 4.096 MHz, the input impedance is approximately
130 kΩ.
2
Zin
=
fMOD ì Cs
where
•
•
fMOD = modulator clock and
CS = 3.5 pF
(5)
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There are two general methods of driving the ADS131A0x analog inputs, as shown in Figure 39: pseudo-
differential or fully-differential.
-VREF / Gain
to
VREF / Gain
VREF / Gain
Peak-to-Peak
Device
Device
Common
Voltage
VREF / Gain
Peak-to-Peak
Common
Voltage
a) Psuedo-Differential Input
b) Differential Input
Figure 39. Pseudo-Differential and Fully-Differential Inputs
To apply a pseudo-differential signal to the fully-differential inputs, apply a dc voltage to AINxN, preferably to the
analog mid-supply [(AVDD + AVSS) / 2] or [(AVDD + VNCP) / 2] when the negative charge pump is enabled.
The AINxP pins can swing between –VREF / Gain to VREF / Gain (as shown in Figure 40) around the common
voltage. The common-mode voltage, VCM, changes with VAINxP
.
Configure the signals at AINxP and AINxN to be 180° out-of-phase centered around a common-mode voltage to
use a fully-differential input method. Both the AINxP and AINxN inputs swing from VCM +½ VREF / Gain to VCM –½
VREF / Gain, as shown in Figure 41. The differential voltage at the maximum and minimum points is equal to VREF
/ Gain to –VREF / Gain, respectively. The VCM voltage remains fixed when AINxP and AINxN swing. Use the
ADS131A0x in a differential configuration to maximize the dynamic range of the data converter. For optimal
performance, the VCM is recommended to be set at the midpoint of the analog supplies.
Tie any unused analog input channels directly to AVSS.
AINxP
AINxP
VCM
VCM
AINxN
AINxN
Figure 40. Pseudo-Differential Input Mode
Figure 41. Fully-Differential Input Mode
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9.3.3 Input Overrange and Underrange Detection
Each ADS131A0x channel has two integrated comparators to detect overrange and underrange conditions on
the input signals. Use the COMP_TH[2:0] bits in the A_SYS_CFG register to set a high and low threshold level
using a 3-bit digital-to-analog converter (DAC). This threshold voltage is compared to the voltage on the input
pins. The voltage monitor triggers an alarm by setting the F_ADCIN bit of the STAT_1 register when the
individual voltage on AINxP or AINxN exceeds the threshold set by the COMP_TH[2:0] bits. When the F_ADCIN
bit of the STAT_1 register is set, indicating an out-of-range event, read the STAT_P register or STAT_N register
to determine exactly which input pin exceeded the set threshold. Figure 42 shows an input overrange and
underrange detection block diagram.
COMP_TH[2:0]
œ
+
Latch
S
Q
Q
œ
R
Conversion
Start Reset
COMP_TH[2:0]
+
DOUT Data Frame
AINxP
AINxN
Channel 1 Channel 2 Channel 3 Channel 4
Status
CRC
C
A D
Digital
Filter
ADC
Data
Data
Data
Data
COMP_TH[2:0]
COMP_TH[2:0]
œ
+
Latch
S
Q
Q
œ
R
Conversion
Start Reset
+
Figure 42. ADC Out-of-Range Detection Monitor
9.3.4 Reference
The ADS131A0x offers an integrated low-drift, 2.442-V or 4.0-V reference option. For applications that require a
different reference voltage, the device offers a reference input option for use with an external reference voltage.
The reference source is selected by the INT_REFEN bit in the A_SYS_CFG register. By default, the external
reference is selected (INT_REFEN = 0). The internal voltage reference requires 0.2 ms to settle to 1% and 250
ms to fully settle to 0.01% when switching from an external reference source to the internal reference (using the
recommended bypass capacitor values). The external reference input is internally buffered to increase input
impedance. Therefore, additional reference buffers are usually not required when using an external reference.
Connect the reference voltage to the REFEXT pin when using an external reference.
External band-limiting capacitors determine the amount of reference noise contribution. For high-end systems,
choose capacitor values such that the bandwidth is limited to less than 10 Hz so that the reference noise does
not dominate the system noise. In systems with strict ADC power-on requirements, using a large capacitor on the
reference increases the time for the voltage to meet the desired value, thus increasing system power-on time.
Figure 43 illustrates a typical external reference drive circuitry with recommended filtering options.
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1 µF
5 V
VOUT
AVDD
100 Ω
AVSS
REF50xx
10 µF
AVSS
GND
REFEXT
AVSS
+
REFP
R2
1 µF
R3
REFN
AVSS
To ADC
NOTE: R2 = 62.3 kΩ, R3 = 97.5 kΩ.
Figure 43. External Reference Driver
Set the INTREF_EN bit to 1 in the A_SYS_CFG register to use the internal reference. When the internal
reference is selected, use the VREF_4V bit to select between a 2.442-V or 4.0-V reference. By default, the
device is set to use the 2.442-V reference. The VREF_4V bit has no function when set to use the external
reference. When enabling the negative charge pump with a 3.0-V to 3.45-V analog supply, the internal reference
must be set to 2.442 V. Figure 44 shows a simplified block diagram of the internal ADS131A0x reference. The
reference voltage is generated with respect to AVSS requiring a direct connection between REFN and AVSS.
1 µF
AVSS
REFEXT
R1
Bandgap
+
REFP
INT_REFEN = 1
VREF_4V = 0
R2
VREF_4V = 1
1 µF
R3
REFN
AVSS
To ADC
NOTE: R1 = 20 kΩ, R2 = 62.3 kΩ, R3 = 97.5 kΩ.
Figure 44. Internal Reference
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9.3.5 ΔΣ Modulator
The ADS131A0x is a multichannel, simultaneous sampling ΔΣ ADC where each channel has an individual
modulator and digital filter. The modulator samples the input signal at the rate of fMOD derived as a function of the
ADC operating clock, fICLK. As in the case of any ΔΣ modulator, the ADS131A0x noise is shaped until fMOD / 2.
The modulator converts the analog input voltage into a pulse-code modulated (PCM) data stream. The on-chip
digital decimation filters take this bitstream and provide attenuation to the now shaped, higher frequency noise.
This ΔΣ sample and conversion process drastically reduces the complexity of the analog antialiasing filters
typically required with nyquist ADCs.
9.3.6 Digital Decimation Filter
The digital filter receives the modulator output and decimates the data stream to create the final conversion
result. The digital filter on each channel consists of a third-order sinc filter. The oversampling ratio (OSR)
determines the number of samples taken to create the output data word, and is set by the modulator rate divided
by the data rate (fMOD / fDATA). The OSR of the sinc filters is adjusted by the OSR[3:0] bits in the CLK2 register.
The OSR setting is a global setting that affects all channels and, therefore, all channels operate at the same data
rate in the device. By adjusting the OSR, tradeoffs can be made between noise and data rate to optimize the
signal chain: filter more for lower noise (thus creating lower data rates), filter less for higher data rates.
The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the
filter from the modulator at the rate of fMOD. Equation 6 shows the scaled sinc3 filter Z-domain transfer function.
As shown in Table 6, the integer N is the set OSR and the integer K is a scaling factor for OSR values that are
not an integer power of 2.
3
1- Z-N
(
)
H z = K ì
( )
Nì 1- Z-1
(6)
Equation 7 shows the sinc filter frequency domain transfer function. As shown in Table 6, the integer N is the set
OSR and the integer K is a scaling factor for OSR values that are not an integer power of 2.
3
»
…
ÿ
Ÿ
⁄
Npf
fMOD
sin
H f = K ì
( )
»
…
ÿ
Ÿ
⁄
pf
fMOD
Nì sin
where:
N = oversampling ratio
(7)
Table 6. K Scaling Factor
OSR (N)
K SCALING VALUE
0.9983778
1.0
800, 400, 200
4096, 2048, 1024, 512, 256, 128, 64, 32
768, 384, 192, 96, 48
1.00195313
The sinc3 filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these
frequencies, the filter has infinite attenuation. Figure 45 and Figure 46 illustrate the digital filter frequency
response out to a normalized input frequency (fIN / fDATA) of 5 and 0.5, respectively. Figure 47, Figure 48, and
Figure 49 illustrate the frequency response for OSR = 32, OSR = 512, and OSR = 4096 up to fMOD, respectively.
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0
-10
0
-2
-20
-4
-30
-40
-6
-50
-8
-60
-70
-10
-12
-14
-16
-18
-20
-80
-90
-100
-110
-120
-130
-140
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency (fIN/fDATA
)
Normalized Frequency (fIN/fDATA
)
D001
D002
Figure 45. Sinc3 Filter Frequency Response
Figure 46. Sinc3 Filter Roll-Off
0
-10
0
-20
-40
-20
-30
-40
-60
-50
-60
-80
-70
-100
-120
-140
-160
-180
-80
-90
-100
-110
-120
-130
-140
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
0
60
120
180
240
300
360
420
480
Normalized Frequency (fIN/fDATA
)
Normalized Frequency (fIN/fDATA)
D003
D004
Figure 47. Sinc3 Filter Frequency Response (OSR 32)
Figure 48. Sinc3 Filter Frequency Response (OSR 512)
0
-25
-50
-75
-100
-125
-150
-175
-200
-225
-250
0
400 800 1200 1600 2000 2400 2800 3200 3600 4000
Normalized Frequency (fIN/fDATA
)
D005
Figure 49. Sinc3 Filter Frequency Response (OSR 4096)
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The K scaling factor for OSR values that are not an integer power of two adds a non-integer gain factor to the
sinc3 frequency response across all frequencies. The host must account for the K scaling factor to obtain the
ADC gain error given in the Electrical Characteristics table. Figure 50 overlays the digital filter frequency
response for the three K scaling options in Table 6. Graph scaling is set to a narrow limit to show the small gain
variation between OSR values.
0.05
OSR 512
OSR 768
0
OSR 800
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
-0.4
-0.45
-0.5
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Normalized Frequency (fIN/fDATA
)
D006
Figure 50. Non-Binary OSR Sinc3 Filter Frequency Response
The ADS131A0x immediately begins outputting conversion data when powered up and brought out of standby
mode using the WAKEUP command. The sinc3 digital filter requires three conversion cycles to provide a settled
conversion result, assuming the analog input has settled to its final value (tSETTLE). The output data are not gated
when the digital filter settles, meaning that the first two conversion results show unsettled data from the filter path
before settled data are available on the third conversion cycle. The first two unsettled conversion cycles, though
unsettled, can be used for diagnostic purposes to ensure the ADC is coming out of standby as expected.
Figure 51 shows the new data ready behavior and time needed for the digital filter coming out of standby.
ADC_ENA
WAKEUP
DIN
tSETTLE
DRDY
1
2
3
Figure 51. Sinc3 Filter Settling
The digital filter uses a multiple stage linear-phase digital filter. Linear -phase filters exhibit constant delay time
across all input frequencies (also know as constant group delay). This behavior results in zero-phase error when
measuring multi-tone signals. For more information about group delay in delta-sigma ADCs, see the Accounting
for delay from multiple sources in delta-sigma ADCs white paper.
9.3.7 Watchdog Timer
The ADS131A0x offers an integrated watchdog timer to protect the device from entering any unresponsive state.
The watchdog timer is a 16-bit counter running on an internal 50-kHz clock. The timer resets with each data
frame when the CS signal transitions from high to low. If a timer reset does not take place and the watchdog
timer expires after 500 ms, the device assumes that an unresponsive state has occurred and issues a watchdog
timer reset. Following the reset, the device enters the power-up state (see the Power-Up section), sets the
F_WDT bit in the STAT_1 register, and indicates that a watchdog timer reset has taken place. Enable the
watchdog timer by setting the WDT_EN bit in the D_SYS_CFG register.
9.4 Device Functional Modes
9.4.1 Low-Power and High-Resolution Mode
The ADS131A0x offers two modes of operation: high-resolution and low-power mode. High-resolution mode
enables a faster modulator clock, up to fMOD = 4.25 MHz, to maximize performance at higher data rates. Low-
power mode scales the analog and digital currents and restricts the maximum fMOD to 1.05 MHz. Select the
operating mode using the HRM bit in the A_SYS_CFG register.
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Device Functional Modes (continued)
9.4.2 Power-Up
After all supplies are established and the RESET pin goes high, an internal power-on-reset (POR) is performed.
As part of the POR process, all registers are initialized to the default states, the state of the Mx pins are latched,
the interface is placed in a locked state, and the device enters standby mode. POR can take up to 4.5 ms to
complete. When the host communicates with the ADS131A0x, the SPI interface outputs a READY status word
indicating that the power-on cycle is completed and the device is ready to accept commands. The STAT_S
register indicates if the ADC powered up properly or if any fault occurred during the initialization of the device.
Send an UNLOCK command to enable the interface and begin communicating with the device. See Table 14 for
more information on the READY status word and the UNLOCK from POR or RESET or RESET: Reset to POR
Values sections for more information on bringing the device out of POR.
9.4.3 Standby and Wake-Up Mode
After being unlocked from POR or after reset, the device enters a low-power standby mode with all ADC
channels powered down. After the registers are properly configured, enable all the ADC channels together by
writing to the ADC_ENA register and issue a WAKEUP command to start conversions. To enter standby mode
again, send the STANDBY command and disable all ADC channels by writing to the ADC_ENA register. The
ADS131A0x requires using the WAKEUP and STANDBY commands together with writing to the ADC_ENA
register to disable or enable ADC channels to start and stop conversions.
9.4.4 Conversion Mode
The device runs in continuous conversion mode. When a conversion completes, the device places the result in
the output buffer and immediately begins another conversion. Data are available at the next data-ready indicator,
although data may not be fully settled through the digital filter (see the Digital Decimation Filter section for more
information on settled data).
9.4.5 Reset (RESET)
There are two methods to reset the ADS131A0x: pull the RESET pin low for at least tw(RSL) or send the RESET
command. The RESET pin must be tied high if the RESET command is used. The RESET command takes effect
at the completion of the command. As part of the reset process, all registers are initialized to the default states,
the status of M0, M1, and M2 pins are latched, the interface is placed in a locked state, and the device enters
standby mode. Reset can take up to 4.5 ms to complete. The device outputs a READY status word indicating
that the reset is completed and the device is ready to accept commands. Send an UNLOCK command to enable
the interface and begin communicating with the device. See Table 13 for more information on the READY status
word, the UNLOCK from POR command, and the RESET command. Figure 7 illustrates the critical timing
relationship of taking the ADS131A0x into reset and bringing the device out of reset.
There are two methods to reset the ADS131A0x: pull the RESET pin low, or send the RESET command. When
using the RESET pin, driving the pin low forces the device into reset. Follow the minimum pulse duration timing
specifications before taking the RESET pin back high. The RESET command takes effect at the completion of
the command (see the RESET: Reset to POR Values section for more information). After the device is reset, 4.5
ms are required to complete initialization of the configuration registers to the default states and for the device to
be ready for normal operation.. Figure 7 illustrates the critical timing relationship of taking the ADS131A0x into
reset and bringing the device out of reset. Tie the RESET pin high if the RESET command is used to reset the
device.
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9.5 Programming
9.5.1 Interface Protocol
The ADS131A0x is designed with an interface protocol that expands the capability of outputting more ADC
system monitors without disrupting data flow. This protocol communicates through standard serial peripheral
interface (SPI) methods, using allocated device words within a single data transmission frame to pass
information. A single data frame starts when the interface is enabled, typically done by pulling the CS line low.
The duration of a data frame is made up of several device words with programmable bit lengths. A visual
representation showing how a data frame is made up of multiple device words is shown in Figure 52.
Data Frame
SCLK
Device Word 1
Device Word 2 Device Word 3
DIN
DIN, DOUT
Device word is length set by M1: 16, 24, or 32 bits.
b) Single Device Word
Device Word 1 Device Word 2 Device Word 3
a) Frame
DOUT
Figure 52. Data Frame and Device Word
9.5.1.1 Device Word Length
The interface is full duplex, allowing the device to be read to and written from within the same data frame. The
length of the individual device words is programmable through the state of the M1 pin. This pin must be set to
one of three states at power-up. The pin state is latched at power-up and changing the pin state after power-up
has no effect. Table 7 lists the modes associated with the M1 pin state. The M1 pin must be tied high to IOVDD
through a < 1-kΩ resistor, low to GND through a < 1-kΩ resistor, or left floating.
Table 7. M1 Pin Setting
M1 STATE
IOVDD
GND
DEVICE WORD LENGTH (Bits)
32
24
16
Float
9.5.1.2 Fixed versus Dynamic-Frame Mode
The device has two data frame size options to set the number of device words per frame: fixed and dynamic-
frame mode, controlled by the FIXED bit in the D_SYS_CFG register. By default, the ADS131A0x powers up in
dynamic-frame mode.
In fixed-frame mode, there are always six device words for each data frame for the ADS131A0x. The first device
word is reserved for the status word, the next four device words are reserved for the conversion data for each of
the four channels, and the last word is reserved for the cyclic redundancy check (CRC) data word.
In dynamic-frame mode, the number of device words per data frame is dependent on if the ADCs are enabled
and if CRC data integrity is enabled. When the ADCs are powered down in standby mode, the number of device
words per data frame is either one or two depending if CRC data integrity is enabled. In normal operation with
the ADC channels powered up, the number of device words per data frame depends on if CRC is enabled. When
CRC data integrity is disabled in dynamic-frame mode, the sixth device word for the ADS131A0x is removed
from the data frame. If CRC data integrity remains enabled, the device word count remains at six.
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Figure 53 shows the fixed-frame and dynamic-frame modes for the ADS131A04 in standby mode with CRC data
integrity enabled and disabled. Figure 54 shows the fixed-frame and dynamic-frame modes for the ADS131A04
with ADC channels and CRC data integrity enabled and disabled.
Data Frame
Data Frame
DIN
Command
Status
00
00
00
00
00
00
00
00
00
00
DIN
Command
Status
DOUT
DOUT
a) Fixed-Frame Size (CRC Disabled)
b) Dynamic Frame Size (CRC Disabled)
Data Frame
Data Frame
DIN
Command
Status
00
00
00
00
00
00
00
00
CRC
DIN
Command
Status
CRC
CRC
DOUT
CRC
DOUT
c) Fixed-Frame Size (CRC Enabled)
d) Dynamic Frame Size (CRC Enabled)
Figure 53. Fixed versus Dynamic-Frame Modes in Standby Mode
Data Frame
Data Frame
DIN
Command
00
00
00
00
00
00
DIN
Command
Status
00
00
00
00
Channel 1 Channel 2 Channel 3 Channel 4
Data Data Data Data
Channel 1 Channel 2 Channel 3 Channel 4
Data Data Data Data
DOUT
Status
DOUT
a) Fixed-Frame Size (CRC Disabled)
b) Dynamic Frame Size (CRC Disabled)
Data Frame
Data Frame
DIN
Command
Status
00
00
00
00
CRC
CRC
DIN
Command
Status
00
00
00
00
CRC
CRC
Channel 1 Channel 2 Channel 3 Channel 4
Data Data Data Data
Channel 1 Channel 2 Channel 3 Channel 4
Data Data Data Data
DOUT
DOUT
c) Fixed-Frame Size (CRC Enabled)
d) Dynamic Frame Size (CRC Enabled)
NOTE: CMND = Command.
Figure 54. Fixed versus Dynamic-Frame Modes With ADCs Enabled
9.5.1.3 Command Word
The command word is the first device word on every DIN data frame. This frame is reserved for sending user
commands to write or read from registers (see the SPI Command Definitions section). The commands are stand-
alone, 16-bit words that appear in the 16 most significant bits (MSBs) of the first device word of the DIN data
frame. Write zeroes to the remaining unused least significant bits (LSBs) when operating in either 24-bit or 32-bit
word size modes.
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9.5.1.4 Status Word
The status word is the first device word in every DOUT data frame. The status word either provides a status
update of the ADC internal system monitors or functions as a status response to an input command; see the SPI
Command Definitions section. The contents of the status word are always 16 bits in length with the remaining
LSBs set to zeroes depending on the device word length; see Table 7.
9.5.1.5 Data Words
The data words follow the status word. The device shifts individual channel data in separate data words. The
ADS131A0x converter is 24-bit resolution regardless of the device word length; see Table 7. The output data are
truncated to 16 bits when using the 16-bit device word length setting (or when enabling hamming code with a 24-
bit device word length setting). The output data are extended to 32 bits with eight zeroes (00000000) added to
the least significant bits when using the 32-bit device word length setting (when hamming code is disabled).
Use the device word length (see Table 7) to set the output resolution of the ADS131A0x. When placing the
hardware M1 pin in a floating state, the interface operates in 16-bit device word length mode by removing the
eight least significant bits. The 16 bits of data per channel are sent in binary twos complement format, MSB first.
The size of one code (LSB) is calculated using Equation 8:
1 LSB = (2 × VREF / Gain) / 216 = FS / 215
(8)
A positive full-scale input [VIN ≥ (FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFh and a
negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 8000h. The output clips at these
codes for signals that exceed full-scale.
Table 8 summarizes the ideal output codes for different input signals.
Table 8. 16-Bit Ideal Output Code versus Input Signal
INPUT SIGNAL, VIN
IDEAL OUTPUT CODE(1)
VAINxP - VAINxN
≥ FS (215 – 1) / 215
7FFFh
0001h
0000h
FFFFh
8000h
FS / 215
0
–FS / 215
≤ –FS
(1) Excludes the effects of noise, INL, offset, and gain errors.
Pull the M1 pin to IOVDD (through a < 1-kΩ resistor) or GND (through a < 1-kΩ resistor) to set the device either
to a 24-bit or 32-bit device word length. In either setting, the ADS131A0x outputs 24 bits of data per channel in
binary twos complement format, MSB first. The size of one code (LSB) is calculated using Equation 9:
1 LSB = (2 × VREF / Gain) / 224 = FS / 223
(9)
A positive full-scale input [VIN ≥ (FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFFFh and
a negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 800000h. The output clips at
these codes for signals that exceed full-scale.
Table 9 summarizes the ideal output codes for different input signals.
Table 9. 24-Bit Ideal Output Code versus Input Signal
INPUT SIGNAL, VIN
VAINxP - VAINxN
≥ FS (223 – 1) / 223
FS / 223
IDEAL OUTPUT CODE(1)
7FFFFFh
000001h
0
000000h
–FS / 223
FFFFFFh
≤ –FS
800000h
(1) Excludes the effects of noise, INL, offset, and gain errors.
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9.5.1.6 Cyclic Redundancy Check (CRC)
The CRC word is the last device word in the DIN and DOUT data frame. The CRC device word is optional and is
enabled by the CRC_EN control bit in the D_SYS_CFG register. When enabled, a 16-bit CRC data check word
is present in the 16 most significant bits of the last device word in the data frame on both DIN and DOUT. Use
the CRC to provide detection of single and multiple bit errors during data transmission.
The ADS131A0x implements a standard CRC16-CCITT algorithm using a polynomial of 11021h and an initial
remainder of FFFFh.
The CRC on all DIN commands is verified by the device prior to command execution except for the WREGS
command; see the WREGS: Write Multiple Registers section. The WREGS command does not check the CRC
prior to writing registers but does indicate if an error occurred. If the CRC on DIN is incorrect, F_CHECK in the
STAT_1 register is set to 1 and the input command does not execute (for all commands except WREGS). Fill the
unused device words on DIN with zeroes, placing the CRC word in the last device word.
The number of input CRC errors is counted and stored in the error count register. The register counts errors up
to 255 before rolling over to 0. The counter is cleard by reading the ERROR_CNT register.
The CRC is calculated using specific device words in the data frame determined by the CRC_MODE and FIXED
bits in the D_SYS_CFG register. For DIN, when the FIXED bit is 0, all device words are calculated into the CRC.
When the FIXED bit is 1 and the CRC_MODE bit is 1, all device words are used for calculating the CRC on DIN.
When the FIXED bit is 1 and the CRC_MODE bit is 0, only the command word and device words are used for
the CRC calculation on DIN.
For DOUT, when the FIXED bit is 0, all device words in the data frame are included in the CRC calculation.
When the FIXED bit is 1 and CRC_MODE is 1, all device words in the data frame are included in the DOUT CRC
calculation. When the FIXED bit is 1 and CRC_MODE is 0, only the command, status word, and active device
words are included in the DOUT CRC calculation. When hamming codes are enabled, the hamming byte of each
word is omitted in the CRC calculation.
Figure 55 and Figure 56 show which device words are included in the CRC calculation on DIN and DOUT under
various CRC settings. In the following examples, the device words that are not checked are highlighted in red.
Data Frame
DIN
Command
Status
Zero
Zero
Zero
Zero
CRC
CRC
Channel 1 Channel 2 Channel 3 Channel 4
Data Data Data Data
DOUT
NOTE: CRC_MODE = 1.
Figure 55. CRC with CRC_MODE = 1
Data Frame
DIN
Command
Status
Zero
Zero
Zero
Zero
CRC
CRC
Channel 1 Channel 2 Channel 3 Channel 4
Data Data Data Data
DOUT
NOTE: CRC_MODE = 0.
Figure 56. CRC with CRC_MODE = 0
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The WREGS command causes the data frame to extend until the last register is written (see the WREGS: Write
Multiple Registers section for more details), thus requiring the CRC to be placed on DIN after the data frame
extension. The ADS131A0x places the CRC word on DOUT at the end of all ADC data. When sending the
WREGS command, the device words following the CRC on DOUT are padded with zeroes and are not included
in the CRC calculation; see Figure 57. The device words that are not checked are highlighted in red.
Data Frame
Registers Registers Registers Registers Registers
DIN
WREGS
Status
CRC
Zero
1, 2
3, 4
5, 6
7, 8
9, 10
Channel 1 Channel 2 Channel 3 Channel 4
Data Data Data Data
DOUT
CRC
Figure 57. CRC Using the WREGS Command
9.5.1.6.1 Computing the CRC
The CRC byte is the 16-bit remainder of the bitwise exclusive-OR (XOR) operation of the data bytes by a CRC
polynomial. The CRC is based on the CRC-CCITT polynomial X16 + X12 + X5 + 1.
The binary coefficients of the polynomial are: 10001000 00010001. Calculate the CRC by dividing the data bytes
(with the XOR operation, thus excluding the CRC) with the polynomial and compare the calculated CRC values
to the provided CRC value. If the values do not match, then a data transmission error has occurred. In the event
of a data transmission error, read or write the data again.
The following list shows a general procedure to compute the CRC value. Assume the shift register is 16 bits
wide:
1. Set the polynomial value to 1021h
2. Set the shift register to FFFFh
3. For each byte in the data stream:
–
Shift the next data byte left by eight bits and XOR the result with the shift register, placing the result into
the shift register
–
Do the following eight times:
1. If the most significant bit of the shift register is set, shift the register left by one bit and XOR the result
with the polynomial, placing the result into the shift register
2. If the most significant bit of the shift register is not set, shift the register left by one bit
4. The result in the shift register is the CRC check value
NOTE
The CRC algorithm used here employs an assumed set X16 bit. This bit is divided out by
left-shifting it 16 times out of the register prior to XORing with the polynomial register. This
process makes the CRC calculable with a 16-bit word size.
9.5.1.7 Hamming Code Error Correction
Hamming code is an optional data integrity feature used to correct for single-bit errors and detect multiple-bit
errors in each device word. Enable hamming code with M2 pin settings (see Table 10 for details). Tie the M2 pin
to IOVDD through a < 1-kΩ resistor to enable hamming code, or tie the M2 pin to GND through a < 1-kΩ resistor
to disable hamming code.
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Hamming code is only supported in 24-bit and 32-bit device word sizes. The ADS131A0x outputs 24 bits of
conversion data and an 8-bit hamming code per channel when operating in 32-bit word size. The ADS131A0x
outputs 16 bits of conversion data and an 8-bit hamming code per channel when operating in 24-bit word size.
Table 10 lists the configuration options of the M1 and M2 hardware pins and the associated device word size.
The status and command words are always 16 bits in length, reserving the eight least significant bits for
hamming code.
Table 10. M2 Pin Setting Options
M2 STATE
M1 STATE
IOVDD
GND
DEVICE WORD SIZE
32 bits
CONVERSION DATA
24 bits
HAMMING DATA
On: 8 bits
On: 8 bits
Not available
Off
IOVDD
24 bits
16 bits
Float
Not available
32 bits
Not available
24 bit + 8 zeroes
24 bit
IOVDD
GND
GND
Float
24 bits
Off
Float
16 bits
16 bit
Off
N/A
Not available
Not available
Not available
When enabled, the hamming code byte is an additional 8-bits appended to the end of each device word on both
the input and output, as shown in Figure 58. This additional eight bits are a combination of five hamming code
(Hamming) bits, two checksum (ChS) bits, and one zero bit, as shown in Figure 59.
32-Bit Command, Status
16 Command, Status Bits
00h
8 HC Bits
8 HC Bits
8 HC Bits
8 HC Bits
Device Word
24-Bit Command, Status
Device Word
16 Command, Status Bits
24 Data Bits
32-Bit ADC Data
Device Word
24-Bit ADC Data
Device Word
16 Data Bits
32-Bit CRC
Device Word
16 CRC Bits
00h
8 HC Bits
8 HC Bits
24-Bit CRC
Device Word
16 CRC Bits
Figure 58. Hamming Code on Each Device Word
2 ChS
Bits
Bits
5 Hamming Bits
0
Figure 59. Hamming Code Bit Allocation
CRC can be used with the hamming code error correction enabled. When the hamming code error correction is
enabled with CRC, the 8-bit hamming data per device word is not protected by the CRC and is ignored in the
calculation. For example, if the 32-bit word size is used with hamming code enabled, the CRC check only uses
the most significant 24 bits of each device word and ignores the last eight bits used for the hamming code. The
CRC considers each device word as being 24 bits.
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Table 11 shows the hamming bit coverage for 24-bit data. The encoded data bit 00 corresponds to the LSB of
the data and bit 23 is the MSB of the data. The hamming code bits are interleaved within the data bits. H0 is the
least significant bit of the hamming code and H4 is the most significant bit.
Table 11. ADS131A0x Hamming Codes
HAMMING OR
DATA
D
D
D
D
D
D
D
D
D
D
D
D
D
H
D
D
D
D
D
D
D
H
D
D
D
H
D
H
H
Encoded data
bits
00 01 02 03 04 05 06 07 08 09 10 11 12 04 13 14 15 16 17 18 19 03 20 21 22 02 23 01 00
H0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
H1
H2
H3
H4
x
x
x
x
x
x
x
x
x
x
x
x
x
Parity bit
coverage
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
9.5.2 SPI Interface
The device SPI-compatible serial interface is used to read conversion data, read and write the device
configuration registers, and control device operation. Only CPOL = 0 and CPHA = 1 are supported. The interface
consists of five control lines (CS, SCLK, DIN, DOUT, and DRDY) but can be used with only four signals as well.
Three interface configurations are selectable in the ADS131A0x by M0 pin settings, as shown in Table 12:
asynchronous interrupt mode, synchronous master mode, and synchronous slave mode.
The M0 pin settings (listed in Table 12) are latched on power-up to set the interface. The same communication
lines are used for all three interface modes: SCLK, DIN, DOUT, and DRDY, with CS as an option in 5-wire mode.
An optional sixth signal (DONE) is available for use when chaining multiple devices, as discussed in the ADC
Frame Complete (DONE) section. Tie the M0 pin high to IOVDD through a < 1-kΩ resistor, low to GND through a
< 1-kΩ resistor, or leave the M0 pin floating.
Table 12. M0 Pin Settings
M0 STATE
IOVDD
GND
INTERFACE MODE
Asynchronous interrupt mode
Synchronous master mode
Synchronous slave mode
Float
9.5.2.1 Asynchronous Interrupt Mode
The SPI uses five interface signals: CS, SCLK, DIN, DOUT, and DRDY in asynchronous interrupt mode. Use the
four interface lines, CS, SCLK, DIN, and DOUT to read conversion data, read and write registers, and send
commands to the ADS131A0x. Use the DRDY output as a status signal to indicate when new conversion data
are ready. Figure 60 shows typical device connections for the ADS131A0x to a host microprocessor or digital
signal processor (DSP) in asynchronous interrupt mode.
IOVDD
IOVDD
Device
MPU, DSP
CS
SCLK
DIN
CS
M0
SCLK
MOSI
MISO
IRQ
DOUT
DRDY
DONE
Master
CLK
CLKIN
Master
Slave
Figure 60. Asynchronous Interrupt Mode Device Connections
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9.5.2.1.1 Chip Select (CS)
Chip select (CS) is an active-low input that selects the device for SPI communication and controls the beginning
and end of a data frame in asynchronous interrupt mode. CS must remain low for the entire duration of the serial
communication to complete a command or data readback. When CS is taken high, the serial interface (including
the data frame) is reset, SCLK and DIN are ignored, and DOUT enters a high-impedance state. DRDY transitions
low when data conversion is complete, regardless of whether CS is high or low.
9.5.2.1.2 Serial Clock (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input and is used to clock data into and out of the device on
DIN and DOUT, respectively. SCLKs can be sent continuously or in byte increments to the ADC. Even though
the input has hysteresis, keeping the SCLK signal as clean as possible is recommended to prevent glitches from
accidentally shifting data. When the serial interface is idle, hold SCLK low.
9.5.2.1.3 Data Input (DIN)
Use the data input (DIN) pin and SCLK to communicate with the ADS131A0x (user commands and register
data). The device latches data on DIN on the SCLK falling edge. The command or register write takes effect
following completion of the data frame.
9.5.2.1.4 Data Output (DOUT)
Use the data output (DOUT) pin with SCLK to read conversion and register data from the ADS131A0x. Data on
DOUT are shifted out on the SCLK rising edge. DOUT goes to a high-impedance state when CS is high or after
the least significant bit is shifted from the output shift register (see the th(LSB) specification in the Switching
Characteristics: Asynchronous Interrupt Interface Mode table).
9.5.2.1.5 Data Ready (DRDY)
DRDY indicates when a new conversion result is ready for retrieval. When DRDY transitions from high to low,
new conversion data are ready. The DRDY signal remains low for the duration of the data frame and returns high
either when CS returns high (signaling the completion of the frame), or prior to new data being available. The
high-to-low DRDY transition occurs at the set data rate regardless of the CS state. If data are not completely
shifted out when new data are ready, the DRDY signal toggles high for a duration of 0.5 × tMOD and back low.
The device sets the F_DRDY bit in the STAT_1 register indicating that the DOUT output shift register is not
updated with the new conversion result. Figure 61 shows an example of new data being ready before previous
data are shifted out, causing the new conversion result to be lost. The DRDY pin is always actively driven, even
when CS is high.
fDATA
DRDY
New data are lost,
F_DRDY = 1.
CS
Channel 1
Data
Channel 2
Data
Channel 3
Data
DOUT
Status
Figure 61. Asynchronous Interrupt Mode Conversion Update During a Read Operation
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9.5.2.1.6 Asynchronous Interrupt Mode Data Retrieval
Figure 62 shows the relationship between DRDY, CS, SCLK, DIN, and DOUT during data retrieval. The high-to-
low DRDY transition indicates that new data are available. Transition CS from high to low to begin a data frame.
At the end of the data frame, CS returns high and brings DRDY high.
DRDY
CS
SCLK
DIN
DOUT
Figure 62. DRDY Behavior with Data Retrieval in Asynchronous Interrupt Mode
9.5.2.2 Synchronous Master Mode
The SPI uses four interface signals: SCLK, DIN, DOUT, and DRDY in synchronous master mode. Connect the
CS signal to the DONE signal when using a single device in synchronous master mode. The SCLK, DRDY, and
DOUT signals are outputs from the device. Provide DIN from the microprocessor (MPU) or DSP using the SCLK
edge timing of the ADS131A0x. Figure 63 shows typical device connections for the ADS131A0x in synchronous
master mode to a host microprocessor or DSP.
IOVDD
Device
MPU, DSP
CS
SCLK
CS
M0
SCLK
MOSI
MISO
IRQ
DIN
DOUT
DRDY
DONE
Master
CLK
CLKIN
Slave
Master
Figure 63. Synchronous Master Mode Device Connections
9.5.2.2.1 Serial Clock (SCLK)
SCLK is the serial peripheral interface (SPI) serial clock. Use SCLK to shift in commands and shift out data from
the device, similar to the description provided in the Asynchronous Interrupt Mode section. The SCLK output
equals the ICLK derived from the input clock, CLKIN, using the clock divider control in the CLK1 register. SCLKs
continuously output at the ICLK rate with the beginning of a data frame set by a DRDY falling edge.
9.5.2.2.2 Data Input (DIN)
Use the data input (DIN) pin and SCLK to communicate with the ADS131A0x (user commands and register
data). The device latches data on DIN on the SCLK falling edge. The command or register write takes effect
following completion of the data frame.
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9.5.2.2.3 Data Output (DOUT)
Use the data output pin (DOUT) with SCLK to read conversion and register data from the ADS131A0x. Data on
DOUT are shifted out on the SCLK rising edge. DOUT goes to a high impedance state when CS is high or after
the least significant bit is shifted from the output shift register (see the th(LSB) specification in the Switching
Characteristics: Asynchronous Interrupt Interface Mode table).
9.5.2.2.4 Data Ready (DRDY)
The DRDY signal is an output that functions as a new data ready indicator and as the control for the start and
stop of a data frame. A high-to-low transition of DRDY from the ADC indicates that the output shift register is
updated with new data and begins a new data frame. Subsequent SCLKs shift out the first device word on
DOUT.
9.5.2.2.5 Chip Select (CS)
For single device operation in synchronous master mode, tie the CS line to the DONE output signal.
9.5.2.2.6 Synchronous Master Mode Data Retrieval
Figure 64 shows the relationship between DRDY, DOUT, DIN, and SCLK during data retrieval in synchronous
master mode. The high-to-low DRDY transition from the ADS131A0x starts a data frame and indicates that new
data are available. DIN and DOUT transition on the SCLK rising edge. After the LSB is shifted out DRDY returns
high, completing the data frame. The ICLK speed must be fast enough to shift out the required bits before new
data are available because ICLK determines the SCLK output rate, as described in the Serial Clock (SCLK)
section. Tie the CS signal to the DONE signal in single device synchronous master mode.
DRDY
SCLK
DIN
DOUT
Figure 64. Data Retrieval in Synchronous Master Mode
9.5.2.3 Synchronous Slave Mode
The SPI uses five interface signals: CS, SCLK, DIN, DOUT, and DRDY in synchronous slave mode. The CS,
SCLK, DIN, and DRDY signals are inputs to the device and the DOUT signal is an output. DRDY can be tied
directly to CS (for a total of four interface lines) or can be used independently as a fourth input signal for
synchronization to an external event; see the Data Ready (DRDY) section for more information on using the
DRDY line for synchronization. Figure 65 shows typical device connections for the ADS131A0x in synchronous
slave mode to a host microprocessor or DSP.
IOVDD
Device
MPU, DSP
CS
SCLK
CS
Float
M0
SCLK
MOSI
MISO
nIRQ
DIN
DOUT
DRDY
DONE
Master
CLK
CLKIN
Master
Slave
Figure 65. Synchronous Slave Mode Device Connections
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9.5.2.3.1 Chip Select (CS)
Chip select (CS) is an active-low input that selects the device for SPI communication and controls the beginning
and end of a data frame in synchronous slave mode. CS must remain low for the entire duration of the serial
communication to complete a command or data readback. When CS is taken high, the serial interface (including
the data frame) is reset, SCLK and DIN are ignored, and DOUT enters a high-impedance state. Tie CS directly to
the DRDY input signal to minimize communication lines as long as the synchronization timing in Figure 5 is met.
Otherwise, the CS line can be used independent of DRDY.
9.5.2.3.2 Serial Clock (SCLK)
SCLK is the SPI serial clock. Use SCLK to shift in commands on DIN and shift out data from the device on
DOUT, similar to the description in the Asynchronous Interrupt Mode section.
If the SCLK source is free-running, the SCLK input signal can be set as the ADC ICLK, removing the need of a
separate CLKIN. The CLKSRC bit in the CLK1 register controls the source for the ADC ICLK. The modulator
clock is derived from the ICLK using the ICLK_DIV[2:0] bits in the CLK2 register; see Figure 35 for a diagram of
how SCLK is routed into the device when serving as the ICLK. Setting SCLK as the internal ICLK requires that
clocks are sent continuously without any delay or stop periods. Care must be taken to prevent glitches on SCLK
at all times.
9.5.2.3.3 Data Input (DIN)
Use the data input pin (DIN) along with SCLK to communicate with the ADS131A0x (user commands and
register data). The device latches data on DIN on the SCLK falling edge. The command or register write takes
effect following the completion of the data frame.
9.5.2.3.4 Data Output (DOUT)
Use the data output pin (DOUT) with SCLK to read conversion and register data from the ADS131A0x. Data on
DOUT are shifted out on the SCLK rising edge. DOUT goes to a high impedance state when CS is high or after
the least significant bit is shifted from the output shift register (see the th(LSB) specification in the Switching
Characteristics: Asynchronous Interrupt Interface Mode table).
9.5.2.3.5 Data Ready (DRDY)
In synchronous slave mode, DRDY is an input signal that must be pulsed at the device set data rate. The DRDY
input signal is compared to an internally-generated data update signal to verify that these two signals are
synchronized. A high-to-low DRDY transition is expected at the programmed data rate or at multiples thereof. In
the event of an unexpected DRDY input pulse, the F_RESYNC bit flags in the STAT_1 register and the ADC
digital filter resets. Use the DRDY input signal as a synchronization method to align new data ready with an
external event or with a second ADS131A0x device. See the Timing Requirements: Synchronous Slave Interface
Mode table for the timing requirements of the DRDY input in synchronous slave mode.
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9.5.2.3.6 Synchronous Slave Mode Data Retrieval
Figure 66 shows the relationship between DRDY, CS, SCLK, DIN, and DOUT during data retrieval in
synchronous slave mode. In synchronous slave mode, the high-to-low DRDY transition sent from the processor
must be synchronized with the data rate programmed, or multiples thereof, to avoid a digital filter reset. The data
frame begins with a high-to-low CS transition with or after DRDY transitions low. The DIN and DOUT signals
transition on the SCLK rising edge. DRDY can return high at any point but must maintain a high-to-low transition
at the set data rate to avoid a resynchronization event. To minimize interface lines, the CS signal can be tied
directly to the DRDY signal; the timing specifications in the Timing Requirements: Synchronous Slave Interface
Mode table are still maintained.
tDATA
DRDY
CS
SCLK
DIN
DOUT
Figure 66. Data Retrieval in Synchronous Slave Mode
9.5.2.4 ADC Frame Complete (DONE)
The DONE output signal is an optional interface line that enables chaining multiple devices together to increase
channel count. Connect the DONE signal to the CS of the next chained data converter in the system to control
the start and stop of the subsequent converter interface. The DONE signal transitions from high to low following
the LSB being shifted out. The delay time from the SCLK falling edge shifting out the LSB to the high-to-low
DONE transition is configured using the DNDLY[1:0] bits in the D_SYS_CFG register. See Figure 6 for details of
the signals and timings of the DONE signal.
For single device operation, configure DONE in the following ways:
•
In asynchronous slave mode, either float the DONE output signal or pull the DONE output signal to IOVDD
through a 100-kΩ pullup resistor.
•
•
In synchronous master mode, tie the DONE output signal to the CS input line.
In synchronous slave mode, either float the DONE output signal or pull the DONE output signal to IOVDD
through a 100-kΩ pullup resistor.
See the Multiple Device Configuration section for more information on using the DONE signal for multiple device
chaining.
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9.5.3 SPI Command Definitions
The ADS131A0x device operation is controlled and configured through ten commands. Table 13 summarizes the
available commands. The commands are stand-alone, 16-bit words and reside in the first device word of the data
frame. Write zeroes to the remaining LSBs when operating in either 24-bit or 32-bit word sizes because each
command is 16-bits in length. The commands are decoded following the completion of a data frame and take
effect immediately. Each recognized command is acknowledged with a status output in the first device word of
the next data frame.
Table 13. Command Definitions
COMMAND
ADDITIONAL
STATUS
COMMAND
DESCRIPTION
DEVICE WORD
DEVICE WORD
RESPONSE
SYSTEM COMMANDS
NULL
Null command
Software reset
0000h
0011h
0022h
0033h
STATUS
READY
RESET
STANDBY
WAKEUP
Enter low-power standby mode
Wake-up from standby mode
ACK = 0022h
ACK = 0033h
Places the interface in a locked state and
ignores all commands except NULL, RREGS,
and UNLOCK
LOCK
0555h
0655h
ACK = 0555h
ACK = 0655h
Brings the device out of an unconfigured POR
state or a locked state
UNLOCK
REGISTER WRITE AND READ COMMANDS
(001a aaaa nnnn
nnnn)b
RREG
Read a single register
REG
Read (nnnn nnnn + 1) registers starting at
address a aaaa
(001a aaaa nnnn
nnnn)b
RREGS
WREG
RREGS
Write a single register at address a aaaa with
data dddd dddd
(010a aaaa dddd
dddd)b
REG (updated
register)
Write (nnnn nnnn + 1) registers beginning at
address a aaaa. Additional device words are
required to send data (dddd dddd) to register
address (a) and data (eeee eeee) to register
address (a+1). Each device word contains data
for two registers.
ACK =
(010a_aaaa_nnnn_n
nnn)b
(011a aaaa nnnn
nnnn)b
(dddd dddd eeee
eeee)b
WREGS
The data frame size is extended by (n / 2) device
words to allow for command completion.
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A command status response is 16 bits in length, located in the MSBs of the first device word in the DOUT data
frame. The response indicates that the command in the previous data frame is executed. When operating in 24-
bit or 32-bit word size modes, the remaining LSBs of the command status response device word read back as
zero unless hamming code is used. An example showing the acknowledgment to a user input command is
shown in Figure 67.
Data Frame
User Command
Status Response
User Command
Status Response
DIN
Channel Data
Channel Data
DOUT
Figure 67. User Command Status Response
Some user commands require multiple data words over multiple device frames. This section describes the
commands and details which commands require multiple data words.
The command status responses to the user commands are listed in Table 14. Every data frame begins with one
of the listed command status responses on DOUT.
Table 14. Command Status Responses
ADDITIONAL
RESPONSE
DESCRIPTION
DEVICE WORD
(FFdd)h
DEVICE WORD
SYSTEM RESPONSE
Fixed-status word stating that the device is in a power-up ready
state or standby mode and is ready for use. The least significant
byte of the device word indicates the address 0 hardware device ID
code (dd). In the READY state, the device transmits only one word,
allowing a 1-word command to be received. An UNLOCK command
must be issued before the device responds to other commands.
READY
—
Acknowledgment response. The device has received and executed
the command and repeats the received command (cccc) as the
command status response. (A NULL input does not result in an ACK
response).
ACK
(cccc)h
—
—
Status byte update. Register address a aaaa contains data dddd
dddd. This command status response is the response to a
recognized RREGS or WREG command.
An automatic status update of register address (02h) is sent when
the NULL command is sent.
(001a aaaa dddd
dddd)b
STATUS/REG
Response for read (nnnn nnnn + 1) registers starting at address a
aaaa. Data for two registers are output per device word. If the
resulting address extends beyond the usable register space, zeroes
are returned for remaining non-existent registers. During an RREGS
response, any new input commands are ignored until the RREGS
status response completes.
(011a aaaa nnnn
nnnn)b
(dddd dddd eeee
eeee)b
RREGS
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9.5.3.1 NULL: Null Command
The NULL command has no effect on ADC registers or data. Rather than producing an ACK response on DOUT,
the command issues a register readback of the STAT_1 register to monitor for general fault updates. An example
of the response to a NULL command is shown in Figure 68.
Data Frame
NULL (0000h)
User Command
DIN
Status Response
Channel Data
REG(STAT_1)
Channel Data
DOUT
Figure 68. NULL Command Status Response
9.5.3.2 RESET: Reset to POR Values
The RESET command places the ADC into a power-on reset (POR) state, resetting all user registers to the
default states. The reset begins following the completion of the frame. When reset completes, the ADC enters a
reset locked state and outputs the READY status response on DOUT as the command status response. An
example of the response to a RESET command is shown in Figure 69.
Data Frame
RESET (0011h)
Status Response
NULL
DIN
Channel Data
READY (FFxx)
Locked State
DOUT
Reset Delay
Figure 69. RESET Command Status Response
9.5.3.3 STANDBY: Enter Standby Mode
The STANDBY command places the ADC in a low-power standby mode, halting conversions. The digital
interface remains powered, allowing all registers to retain the previous states. When in standby mode, writing
and reading from registers is possible and any programmable bits that activate circuitry take effect in the device
after the WAKEUP command is issued. The command status response following a STANDBY command is
0022h. In standby mode, the command status response is dependent on the user command that is sent. All ADC
channels must be disabled (by writing to the ADCx registers) prior to entering standby mode to reduce current
consumption. An example for the response to the STANDBY command and behavior when in standby mode is
shown in Figure 70.
Data Frame
STANDBY
(0022h)
WAKEUP
(0033h)
User Command
NULL
DIN
Status
Response
Status
Response
REG
(STAT_1)
Channel Data
ACK (0022h)
Standby
DOUT
Standby
Standby
Figure 70. STANDBY Command Status Response
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9.5.3.4 WAKEUP: Exit STANDBY Mode
The WAKEUP command brings the ADC out of standby mode. The ADC channels must be enabled (by writing to
the ADCx registers) before bringing the device out of standby mode. Allow enough time for all circuits in standby
mode to power-up (see the Electrical Characteristics table for details). The command status response following a
WAKEUP command is 0033h. An example showing the response to exiting standby mode using the WAKEUP
command is shown in Figure 71.
Data Frame
NULL
WAKEUP (0033h)
DIN
RREG (STAT_1)
Standby
RREG (STAT_1)
Standby
ACK (0033h)
Normal
Data
DOUT
Figure 71. WAKEUP Command Status Response
9.5.3.5 LOCK: Lock ADC Registers
The LOCK command places the converter interface in a locked state where the interface becomes unresponsive
to most input commands. The UNLOCK, NULL, RREG, and RREGS commands are the only commands that are
recognized when reading back data. Following the LOCK command, the first DOUT status response reads 0555h
followed by the command status response of a NULL command (by reading the STAT_1 register). An example
showing the response to sending a LOCK command and entering a register locked state is shown in Figure 72.
Data Frame
LOCK (0555h)
NULL
NULL
DIN
Status Response
Data
ACK (0555h)
Locked
Data
ACK (STAT_1)
Locked
Data
DOUT
Figure 72. LOCK Command Status Response
9.5.3.6 UNLOCK: Unlock ADC Registers
The UNLOCK command brings the converter out of the locked state, allowing all registers to be accessed in the
next data frame. The command status response associated with the UNLOCK command is 0655h. An example
of bringing the interface out of the locked state using the UNLOCK command is shown in Figure 73.
Data Frame
NULL
UNLOCK (0655h)
User Command
DIN
ACK (STAT_1)
Locked
Data
ACK (STAT_1)
Locked
Data
ACK (0655h)
Unlocked
Data
DOUT
Figure 73. UNLOCK Command Status Response
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9.5.3.6.1 UNLOCK from POR or RESET
When powering up the device or coming out of a power-on reset (POR) state, the ADC does not accept any
commands. During this time, the jost can poll the ADC until the command status response reads back FFDDh
(DD denotes the channel count defined by the NU_CH[3:0] bits in the ID_MSB register), indicating that the ADC
power-on reset cycle is complete and that the ADC is ready to accept commands. Use the UNLOCK command
to enable the SPI interface and begin communication with the device. The command status response associated
with the UNLOCK command is 0655h. Figure 74 shows an example of unlocking the device after POR using the
UNLOCK command.
POR_EVENT
Data Frame
POR_EVENT
DIN
NULL
UNLOCK (0655h)
User Command
POR_EVENT
DOUT
READY (FFxx)
Locked
READY (FFxx)
Locked
ACK (0655h)
Unlocked
Data
Figure 74. UNLOCK from a POR Command Status Response
9.5.3.7 RREG: Read a Single Register
The RREG command reads register data from the ADC. RREG is a 16-bit command containing the command,
the register address, and the number of registers to be to read. The command details are shown below:
First byte: 001a aaaa, where a aaaa is the register address
Second byte: 00h
The ADC executes the command upon completion of the data frame and the register data transmission begins
on the first device word of the following data frame. The response contains an 8-bit acknowledgement byte with
the register address and an 8-bit data byte with the register content. Figure 75 shows an example command
response to a single register read.
Data Frame
RREG REG(a)
RREG REG(b)
NULL
DIN
Status Word
Data
REG(a)
Data
REG(b)
Data
DOUT
Figure 75. RREGS Command Status Response (Single Register Read)
9.5.3.8 RREGS: Read Multiple Registers
For a multiple register read back, the command status response exceeds the 16-bit reserved device word space,
causing an overflow to additional command status words. The first command status response is an
acknowledgment of multiple registers to be read back and the additional command status responses shift out
register data. The command status response details are shown below:
First command status response: 001a aaaa nnnn nnnn, where a aaaa is the starting register address and
nnnn nnnn is the number of registers to read minus one (n-1).
Additional command status responses: dddd dddd eeee eeee , where dddd dddd is the register data from the
first register read back and eeee eeee is the register data from the second read back register.
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The number of additional command status responses across multiple frames is dependent on the number of
registers to be read back. During a RREGS command status response, any new input commands are ignored
until the command completes by shifting out all necessary command status responses. If the resulting address
extends beyond the usable register space, zeroes are returned for any remaining non-existent registers. An
example of the command response to reading four registers using a RREGS command is shown in Figure 76.
Data Frame
RREGS (2003h)
NULL
NULL
NULL
DIN
REG (02h+03h)
Status Word
Data
Ack (RREGS)
Data
REG (00h+01h)
Data
Data
DOUT
Figure 76. RREGS Command Status Response (Multiple Register Read)
9.5.3.9 WREG: Write Single Register
The WREG command writes data to a single register. The single register write command is a two-byte command
containing the address and the data to write to the address. The command details are shown below:
First byte: 010a aaaa, where a aaaa is the register address.
Second byte: dddd dddd, where dddd dddd is the data to write to the address.
The resulting command status response is a register read back from the updated register. An example of a
single register write and response is shown in Figure 77.
Data Frame
WREG REG(a)
WREG REG(b)
NULL
DIN
Status Response
Data
REG(a)
Data
REG(b)
Data
DOUT
Figure 77. WREG Command Status Response (Single Register Write)
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9.5.3.10 WREGS: Write Multiple Registers
The WREGS command writes data to multiple registers. The command steps through each register
incrementally, thus allowing the user to incrementally write to each register. This process extends the data frame
by (n) device words to complete the command. If the resulting address extends beyond the usable register
space, any following data for non-existent registers are ignored. The 16 bits contained in the first device word
contain the command, the starting register address, and the number of registers to write, followed by additional
device words for the register data. The command details are shown below:
First user command device word: 011a aaaa nnnn nnnn, where a aaaa is the starting register address and
nnnn nnnn is the number of registers to write minus one (n-1).
Additional user command device words: dddd dddd eeee eeee, where dddd dddd is the data to write to the
first register and eeee eeee is the register data for the second register.
The user command device word uses the 16 MSBs regardless of word length (that is, only the 16 MSBs are
used in 16-bit, 24-bit, or 32-bit word lengths). When additional command device words are required, only a
maximum of two 8-bit registers can be written per command and any additional LSBs beyond 16 bits are ignored.
The command status response for the WREGS command is 010a aaaa nnnn nnnn, where a aaaa is the starting
register address and nnnn nnnn is the number of registers written minus one. An example of a multiple register
write and the command status response is shown in Figure 78.
Data Frame
WREGS
Command
REG (a+b)
REG (c+d)
REG (m+n)
NULL
DIN
WREGS
Response
Status Response Channel 1 Data Channel 2 Data
Data
00h
Data
DOUT
Figure 78. WREGS Command Status Response (Multiple Register Write)
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9.6 Register Maps
Table 15. Register Map
REGISTER BITS
ADDRESS
(Hex)
DEFAULT
SETTING
REGISTER NAME
7
6
5
4
3
2
1
0
Read Only ID Registers
00h
ID_MSB
xxh
xxh
NU_CH[7:0]
REV_ID[7:0]
01h
ID_LSB
Status Registers
02h
03h
04h
05h
06h
07h
08h
09h
STAT_1
STAT_P
00h
00h
00h
00h
00h
xxh
00h
00h
0
0
0
0
F_OPC
F_SPI
F_ADCIN
F_WDT
F_IN4P
F_IN4N
0
F_RESYNC
F_IN3P
F_DRDY
F_IN2P
F_IN2N
F_CS
F_CHECK
F_IN1P
0
0
0
0
0
0
0
0
0
STAT_N
F_IN3N
F_IN1N
STAT_S
F_STARTUP
F_FRAME
ERROR_CNT
STAT_M2
Reserved
Reserved
ER[7:0]
0
0
0
0
0
0
M2PIN[1:0]
M1PIN[1:0]
M0PIN[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
User Configuration Registers
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
Reserved
A_SYS_CFG
D_SYS_CFG
CLK1
00h
60h
3Ch
08h
86h
00h
00h
00h
00h
00h
00h
0
0
0
1
0
0
0
0
0
VNCPEN
WDT_EN
CLKSRC
HRM
VREF_4V
DNDLY[1:0]
INT_REFEN
COMP_TH[2:0]
FIXED
CRC_MODE
HIZDLY[1:0]
CLK_DIV[2:0]
OSR[3:0]
ENA[3:0]
CRC_EN
0
0
0
0
0
0
0
0
0
0
0
CLK2
ICLK_DIV[2:0]
ADC_ENA
Reserved
ADC1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GAIN1_[2:0]
GAIN2_[2:0]
GAIN3_[2:0]
GAIN4_[2:0]
ADC2
ADC3(1)
ADC4(1)
(1) This register is for the ADS131A04 only. This register is reserved for the ADS131A02.
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9.6.1 User Register Description
9.6.1.1 ID_MSB: ID Control Register MSB (address = 00h) [reset = xxh]
This register is programmed during device manufacture to indicate device characteristics.
Figure 79. ID_MSB Register
7
6
5
4
3
2
1
0
NU_CH[7:0]
R-xxh
LEGEND: R = Read only; -n = value after reset
Table 16. ID_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
NU_CH[7:0]
R
xxh
Channel count identification bits.
These bits indicate the device channel count.
02h : 2-channel device
04h : 4-channel device
9.6.1.2 ID_LSB: ID Control Register LSB (address = 01h) [reset = xxh]
This register is reserved for future use.
Figure 80. ID_LSB Register
7
6
5
4
3
2
1
0
REV_ID[7:0]
R-xxh
LEGEND: R = Read only; -n = value after reset
Table 17. ID_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
REV_ID[7:0]
R
xxh
Reserved.
These bits indicate the revision of the device and are subject to change
without notice.
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9.6.1.3 STAT_1: Status 1 Register (address = 02h) [reset = 00h]
This register contains general fault updates. This register is automatically transferred on the command status
response when the NULL command is sent.
Figure 81. STAT_1 Register
7
0
6
5
4
3
2
1
0
F_OPC
R-0h
F_SPI
R-0h
F_ADCIN
R-0h
F_WDT
R-0h
F_RESYNC
R-0h
F_DRDY
R-0h
F_CHECK
R-0h
R-0h
LEGEND: R = Read only; -n = value after reset
Table 18. STAT_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
R
0h
Reserved.
Always read 0.
6
F_OPC
R
0h
Command fault.
This bit indicates that a received command is not recognized as valid and
the command is ignored. This bit auto-clears on a STAT_1 data transfer,
unless the condition remains.
When in a locked state, this bit is set if any command other than LOCK,
UNLOCK, NULL, or RREGS is written to the device.
0 : No fault has occurred
1 : Possible invalid command is ignored
5
4
F_SPI
R
R
0h
0h
SPI fault.
This bit indicates that one of the status bits in the STAT_S register is set.
Read the STAT_S register to clear the bit.
0 : No fault has occurred
1 : A bit in the STAT_S register is set high
F_ADCIN
ADC input fault.
This bit indicates that one of the ADC input fault detection bits in the
STAT_P or STAT_N register is set. Read the STAT_P and STAT_N
registers to clear the bit.
0 : No fault has occurred
1 : A bit in the STAT_P or STAT_N register is set high
3
2
F_WDT
R
R
0h
0h
Watchdog timer timeout.
This bit indicates if the watchdog timer times out before a new data frame
transfer occurs.
0 : No fault has occurred
1 : Timer has run out (resets following register read back)
F_RESYNC
Resynchronization fault.
This bit is set whenever the signal path is momentarily reset resulting from
a DRDY synchronization event. This fault is only possible in synchronous
slave mode.
0 : Devices are in sync
1 : Signal path is momentarily reset to maintain synchronization
1
0
F_DRDY
R
R
0h
0h
Data ready fault.
This bit is set if data shifted out from the previous result are not complete
by the time new ADC data are ready. The ADC DRDY line pulses,
indicating that new data are available and overwrite the current data. This
bit auto-clears on a STAT_1 transfer, unless the condition remains.
0 : Data read back complete before new data update
1 : New data update during DOUT data transmission
F_CHECK
DIN check fault.
This bit is set if either of the following conditions are detected:
•
Uncorrectable hamming error correction state is determined for any
DIN word transfer when hamming code is enabled.
•
CRC check word on DIN fails. The input command that triggered this
error is ignored.
This bit auto-clears on a STAT_S transfer, unless the condition remains.
0 : No error in DIN transmission
1 : DIN transmission error
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9.6.1.4 STAT_P: Positive Input Fault Detect Status Register (address = 03h) [reset = 00h]
This register stores the status of whether the positive input on each channel exceeds the threshold set by the
COMP_TH[2:0] bits; see the Input Overrange and Underrange Detection section for details.
Figure 82. STAT_P Register
7
0
6
0
5
0
4
0
3
2
1
0
F_IN4P
R-0h
F_IN3P
R-0h
F_IN2P
R-0h
F_IN1P
R-0h
R-0h
R-0h
R-0h
R-0h
LEGEND: R = Read only; -n = value after reset
Table 19. STAT_P Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
Reserved
R
0h
Reserved.
Always read 0h.
3
2
1
0
F_IN4P(1)
F_IN3P(1)
F_IN2P
R
R
R
R
0h
0h
0h
0h
AIN4P threshold detect.
0 : The channel 4 positive input pin does not exceed the set threshold
1 : The channel 4 positive input pin exceeds the set threshold
AIN3P threshold detect.
0 : The channel 3 positive input pin does not exceed the set threshold
1 : The channel 3 positive input pin exceeds the set threshold
AIN2P threshold detect.
0 : The channel 2 positive input pin does not exceed the set threshold
1 : The channel 2 positive input pin exceeds the set threshold
F_IN1P
AIN1P threshold detect.
0 : The channel 1 positive input pin does not exceed the set threshold
1 : The channel 1 positive input pin exceeds the set threshold
(1) This bit is not available in the ADS131A02 and always read 0.
9.6.1.5 STAT_N: Negative Input Fault Detect Status Register (address = 04h) [reset = 00h]
This register stores the status of whether the negative input on each channel exceeds the threshold set by the
COMP_TH[2:0] bits; see the Input Overrange and Underrange Detection section for details.
Figure 83. STAT_N Register
7
0
6
0
5
0
4
0
3
2
1
0
F_IN4N
R-0h
F_IN3N
R-0h
F_IN2N
R-0h
F_IN1N
R-0h
R-0h
R-0h
R-0h
R-0h
LEGEND: R = Read only; -n = value after reset
Table 20. STAT_N Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
Reserved
R
0h
Reserved.
Always read 0h.
3
2
1
0
F_IN4N(1)
F_IN3N(1)
F_IN2N
R
R
R
R
0h
0h
0h
0h
AIN4N threshold detect.
0 : The channel 4 negative input pin does not exceed the set threshold
1 : The channel 4 negative input pin exceeds the set threshold
AIN3N threshold detect.
0 : The channel 3 negative input pin does not exceed the set threshold
1 : The channel 3 negative input pin exceeds the set threshold
AIN2N threshold detect.
0 : The channel 2 negative input pin does not exceed the set threshold
1 : The channel 2 negative input pin exceeds the set threshold
F_IN1N
AIN1N threshold detect.
0 : The channel 1 negative input pin does not exceed the set threshold
1 : The channel 1 negative input pin exceeds the set threshold
(1) This bit is not available in the ADS131A02 and always read 0.
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9.6.1.6 STAT_S: SPI Status Register (address = 05h) [reset = 00h]
This register indicates the detection of SPI fault conditions.
Figure 84. STAT_S Register
7
0
6
0
5
0
4
0
3
0
2
1
0
F_STARTUP
R-0h
F_CS
R-0h
F_FRAME
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
LEGEND: R = Read only; -n = value after reset
Table 21. STAT_S Register Field Descriptions
Bit
Field
Type
Reset
Description
7:3
Reserved
R
00h
Reserved.
Always read 00h.
2
1
0
F_STARTUP
R
R
R
0h
0h
0h
ADC startup fault.
This bit indicates if an error is detected during power-up. This bit clears
only when power is recycled.
0 : No fault has occurred
1 : A fault has occurred
F_CS
Chip-select fault.
This bit is set if CS transitions when the SCLK pin is high. This bit auto-
clears on a STAT_S transfer, unless the condition remains.
0 : CS is asserted or deasserted when SCLK is low
1 : CS is asserted or deasserted when SCLK is high
F_FRAME
Frame fault.
This bit is set if the device detects that not enough SCLK cycles are sent in
a data frame for the existing mode of operation. This bit auto-clears on a
STAT_S transfer, unless the condition remains.
0 : Enough SCLKs are sent per frame
1 : Not enough SCLKs are sent per frame
9.6.1.7 ERROR_CNT: Error Count Register (address = 06h) [reset = 00h]
This register counts the hamming and CRC errors. This register is cleared when read.
Figure 85. ERROR_CNT Register
7
6
5
4
3
2
1
0
ER7
R-0h
ER6
R-0h
ER5
R-0h
ER4
R-0h
ER3
R-0h
ER2
R-0h
ER1
R-0h
ER0
R-0h
LEGEND: R = Read only; -n = value after reset
Table 22. ERROR_CNT Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
ER[7:0]
R
00h
Error tracking count.
These bits count the number of hamming and CRC errors on the input. The
counter saturates if the number of errors exceeds 255, FFh. This register is
cleared when read.
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9.6.1.8 STAT_M2: Hardware Mode Pin Status Register (address = 07h) [reset = xxh]
This register indicates detection of the captured states of the hardware mode pins.
Figure 86. STAT_M2 Register
7
0
6
0
5
4
3
2
1
0
M2PIN[1:0]
R-xh(1)
M1PIN[1:0]
R-xh(1)
M0PIN[1:0]
R-xh(1)
R-0h
R-0h
LEGEND: R = Read only; -n = value after reset
(1) Reset values are dependent on the state of the hardware pin.
Table 23. STAT_M2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
Reserved
R
0h
Reserved.
Always read 0h.
5:4
3:2
1:0
M2PIN[1:0]
M1PIN[1:0]
M0PIN[1:0]
R
R
R
xh(1)
xh(1)
xh(1)
M2 captured state.
These bits indicate the captured state of the M2 hardware control pin.
00 : GND (hamming code word validation off)
01 : IOVDD (hamming code word validation on)
10 : No connection
11 : Reserved
M1 captured state.
These bits indicate the captured state of the M1 hardware control pin.
00 : GND (24-bit device word)
01 : IOVDD (32-bit device word)
10 : No connection (16-bit device word)
11 : Reserved
M0 captured state.
These bits indicate the captured state of the M0 hardware control pin.
00 : GND (synchronous master mode)
01 : IOVDD (asynchronous slave mode )
10 : No connection (synchronous slave mode )
11 : Reserved
(1) Reset values are dependent on the state of the hardware pin.
9.6.1.9 Reserved Registers (address = 08h to 0Ah) [reset = 00h]
This register is reserved for future use.
Figure 87. Reserved Registers
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
LEGEND: R = Read only; -n = value after reset
Table 24. Reserved Registers Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R
00h
Reserved.
Always read 00h.
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9.6.1.10 A_SYS_CFG: Analog System Configuration Register (address = 0Bh) [reset = 60h]
This register configures the analog features in the ADS131A0x.
Figure 88. A_SYS_CFG Register
7
6
5
1
4
3
2
1
0
VNCPEN
R/W-0h
HRM
VREF_4V
R/W-0h
INT_REFEN
R/W-0h
COMP_TH[2:0]
R/W-0h
R/W-1h
R/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 25. A_SYS_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
VNCPEN
R/W
0h
Negative charge pump enable.
This bit enables the negative charge pump when using a 3.0-V to 3.45-V
unipolar power supply.
0 : Negative charge pump powered down
1 : Negative charge pump enabled
6
HRM
R/W
1h
High-resolution mode.
This bit selects between high-resolution and low-power mode.
0 : Low-power mode
1 : High-resolution mode
5
4
Reserved
VREF_4V
R/W
R/W
1h
0h
Reserved.
Always write 1h.
REFP reference voltage level.
This bit determines the REFP reference voltage level when using the
internal reference.
0 : REFP is set to 2.442 V
1 : REFP is set to 4.0 V
3
INT_REFEN
R/W
R/W
0h
0h
Internal reference enable.
This bit connects the internal reference voltage to the reference buffer to
use the internal reference
0 : External reference voltage selected
1 : Internal reference voltage enabled and selected
2:0
COMP_TH[2:0]
Fault detect comparator threshold.
These bits determine the fault detect comparator threshold level settings;
see the
Input Overrange and Underrange Detection section for details.
Table 26 lists the bit settings for the high- and low-side thresholds. Values
are approximate and are referenced to the device analog supply range.
When VNCPEN = 0, AVDD and AVSS are used for the high and low
threshold.
When VNCPEN = 1, AVDD is used for the high threshold value. A –1.5-V
supply, generated from the negative charge pump, is used for the low
threshold value.
Table 26. COMP_TH[2:0] Bit Settings
COMPARATOR HIGH-SIDE THRESHOLD
(%)
COMPARATOR LOW-SIDE THRESHOLD
(%)
COMP_TH[2:0]
000
001
010
011
100
101
110
111
95
92.5
90
5
7.5
10
87.5
85
12.5
15
80
20
75
25
70
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9.6.1.11 D_SYS_CFG: Digital System Configuration Register (address = 0Ch) [reset = 3Ch]
This register configures the digital features in the ADS131A0x.
Figure 89. D_SYS_CFG Register
7
6
5
4
3
2
1
0
WDT_EN
R/W-0h
CRC_MODE
R/W-0h
DNDLY[1:0]
R/W-3h
HIZDLY[1:0]
R/W-3h
FIXED
R/W-0h
CRC_EN
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 27. D_SYS_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
WDT_EN
R/W
0h
Watchdog timer enable.
This bit enables the watchdog timeout counter when set.
Issue a hardware or software reset when disabling the watchdog timer for
internal device synchronization; see the Watchdog Timer section.
0 : Watchdog disabled
1 : Watchdog enabled
6
CRC_MODE
DNDLY[1:0]
R/W
R/W
0h
3h
CRC mode select.
This bit determines which bits in the frame the CRC is valid for; see the
Cyclic Redundancy Check (CRC) section.
0 : CRC is valid on only the device words being sent and received
1 : CRC is valid on all bits received and transmitted
5:4
DONE delay.
These bits configure the time before the device asserts DONE after the
LSB is shifted out.
00 : ≥ 6-ns delay
01 : ≥ 8-ns delay
10 : ≥ 10-ns delay
11 : ≥ 12-ns delay
3:2
HIZDLY[1:0]
R/W
3h
Hi-Z delay.
These bits configure the time that the device asserts Hi-Z on DOUT after
the LSB of the data frame is shifted out.
00 : ≥ 6-ns delay
01 : ≥ 8-ns delay
10 : ≥ 10-ns delay
11 : ≥ 12-ns delay
1
0
FIXED
R/W
R/W
0h
0h
Fixed word size enable.
This bit sets the data frame size.
0 : Device words per data frame depends on whether the CRC and ADCs
are enabled
1 : Fixed six device words per frame for the ADS131A04 or fixed four
device words per data frame for the ADS131A02
CRC_EN
Cyclic redundancy check enable.
This bit enables the CRC data word for both the DIN and DOUT data frame
transfers. When enabled, DIN commands must pass the CRC checks to be
recognized by the device.
0 : CRC disabled
1 : CRC enabled
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9.6.1.12 CLK1: Clock Configuration 1 Register (address = 0Dh) [reset = 08h]
This register configures the ADC clocking and sets the internal clock dividers.
Figure 90. CLK1 Register
7
6
0
5
0
4
0
3
2
1
0
0
CLKSRC
R/W-0h
CLK_DIV[2:0]
R/W-4h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 28. CLK1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CLKSRC
R/W
0h
ADC clock source.
This bit selects the source for ICLK; see the Clock section for more
information on ADC clocking.
0 : XTAL1/CLKIN pin or XTAL1/CLKIN and XTAL2 pins
1 : SCLK pin
6:4
3:1
Reserved
R/W
R/W
0h
4h
Reserved.
Always write 0h.
CLK_DIV[2:0]
CLKIN divider ratio.
These bits set the CLKIN divider ratio to generate the internal fICLK
frequency. ICLK is used as the fSCLK output when the ADC is operating in
synchronous master mode.
000 : Reserved
001 : fICLK = fCLKIN / 2
010 : fICLK = fCLKIN / 4
011 : fICLK = fCLKIN / 6
100 : fICLK = fCLKIN / 8
101 : fICLK = fCLKIN / 10
110 : fICLK = fCLKIN / 12
111 : fICLK = fCLKIN / 14
0
Reserved
R/W
0h
Reserved.
Always write 0.
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9.6.1.13 CLK2: Clock Configuration 2 Register (address = 0Eh) [reset = 86h]
This register configures the ADC modulator clock and oversampling ratio for the converter.
Figure 91. CLK2 Register
7
6
5
4
0
3
2
1
0
ICLK_DIV[2:0]
R/W-4h
OSR[3:0]
R/W-6h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 29. CLK2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
ICLK_DIV[2:0]
R/W
4h
ICLK divider ratio.
These bits set the divider ratio to generate the ADC modulator clock, fMOD
,
from the fICLK signal.
000 : Reserved
001 : fMOD = fICLK / 2
010 : fMOD = fICLK / 4
011 : fMOD = fICLK / 6
100 : fMOD = fICLK / 8
101 : fMOD = fICLK / 10
110 : fMOD = fICLK / 12
111 : fMOD = fICLK / 14
4
Reserved
OSR[3:0]
R/W
R/W
0h
6h
Reserved.
Always write 0h.
3:0
Oversampling ratio.
These bits set the OSR to create the ADC output data rate, fDATA; see
Table 30 for more details.
0000 : fDATA = fMOD / 4096
0001 : fDATA = fMOD / 2048
0010 : fDATA = fMOD / 1024
0011 : fDATA = fMOD / 800
0100 : fDATA = fMOD / 768
0101 : fDATA = fMOD / 512
0110 : fDATA = fMOD / 400
0111 : fDATA = fMOD / 384
1000 : fDATA = fMOD / 256
1001 : fDATA = fMOD / 200
1010 : fDATA = fMOD / 192
1011 : fDATA = fMOD / 128
1100 : fDATA = fMOD / 96
1101 : fDATA = fMOD / 64
1110 : fDATA = fMOD / 48
1111 : fDATA = fMOD / 32
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Table 30. Data Rate Settings
fDATA AT 2.048-MHz fMOD fDATA AT 4.096-MHz fMOD
fDATA AT 4-MHz fMOD
(kHz)
OSR[3:0]
OSR
(kHz)
0.500
1.000
2.000
2.560
2.667
4.000
5.120
5.333
8.000
10.240
10.667
16.000
21.333
32.000
42.667
64.000
(kHz)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4096
2048
1024
800
768
512
400
384
256
200
192
128
96
1.000
0.977
1.953
2.000
4.000
3.906
5.120
5.000
5.333
5.208
8.000
7.813
10.240
10.667
16.000
20.480
21.333
32.000
42.667
64.000
85.333
128.000
10.000
10.417
15.625
20.000
20.833
31.250
41.667
62.500
83.333
125.000
64
48
32
9.6.1.14 ADC_ENA: ADC Channel Enable Register (address = 0Fh) [reset = 00h]
This register controls the enabling of ADC channels.
Figure 92. ADC_ENA Register
7
0
6
0
5
0
4
0
3
2
1
0
ENA[3:0]
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 31. ADC_ENA Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
Reserved
R/W
0h
Reserved.
Always write 0h.
3:0
ENA[3:0]
R/W
0h
Enable ADC channels.
These bits power-up or power-down the ADC channels. This setting is
global for all channels.
0000 : All ADC channels powered down
1111 : All ADC channels powered up
All other settings: Do not use
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9.6.1.15 Reserved Register (address = 10h) [reset = 00h]
This register is reserved for future use.
Figure 93. Reserved Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R = Read only; -n = value after reset
Table 32. Reserved Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R/W
00h
Reserved.
Always write 00h.
9.6.2 ADCx: ADC Channel Digital Gain Configuration Registers (address = 11h to 14h) [reset = 00h]
These registers control the digital gain setting for the individual ADC channel (x denotes the ADC channel).
For the ADS131A02, these registers are reserved.
Figure 94. ADCx Register
7
0
6
0
5
0
4
0
3
0
2
1
0
GAINx_[2:0]
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 33. ADCx Registers Field Descriptions
Bit
Field
Type
Reset
Description
7:3
Reserved
R/W
00h
Reserved.
Always write 00h.
2:0
GAINx_[2:0]
R/W
0h
Gain control (digital scaling).
These bits determine the digital gain of the ADC output.
000 : Gain = 1
001 : Gain = 2
010 : Gain = 4
011 : Gain = 8
100 : Gain = 16
101, 110, 111 : Reserved
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Unused Inputs and Outputs
To minimize leakage currents on the analog inputs, leave any unused analog inputs floating or connected to
AVSS. For the ADS131A02, the NC pins (pins 5-8) can be left floating or tied directly to AVSS.
Pin 24 is a digital output unconnected (NC) pin. Leave pin 24 floating or tied to GND through a 10-kΩ pulldown
resistor.
Do not float unused digital inputs because excessive power-supply leakage current can result. Tie all unused
digital inputs to the appropriate levels, IOVDD or DGND, even when in power-down mode.
If the DONE or DRDY outputs are not used, leave these pins (pins 18 and 19, respectively) unconnected or tie
these pins to IOVDD using a weak pullup resistor. Current consumed by the pullup resistor flows into the device
and therefore increases power consumption.
10.1.2 Power Monitoring Specific Applications
Each channel of the ADS131A0x is identical, giving designers the flexibility to sense voltage or current with any
channel. Simultaneous sampling allows the application to calculate instantaneous power for any simultaneous
voltage and current measurement. Figure 95 shows an example system that measures voltage and current
simultaneously.
Phase B Phase A
2.5 V
AVDD
R1
RFILT
AIN1P
AIN1N
R2
R2
CFILT
R1
RFILT
CFILT
Device
RFILT
CT
AIN2P
AIN2N
R3
CFILT
AVSS
-2.5 V
Figure 95. Example Power-Monitoring System
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Application Information (continued)
In Figure 95, channel 1 is dedicated to measuring the voltage between phase A and phase B and channel 2 is
dedicated to measuring the current on phase A.
The resistors R1 and R2 form a voltage divider that steps the line voltage down to within the measurement range
of the ADC. R1 can be formed by multiple resistors in series to dissipate power across several components. This
configuration is also valid if the voltage is measured with respect to neutral instead of between phases.
Channel 2 is dedicated to measuring current that flows on phase A. Resistor R3 serves as a burden resistor that
shunts the current flowing across the secondary coil of the current transformer (CT). Current can also be
measured using a Rogowski coil and an analog integrator or by performing integration digitally after a
conversion.
The RC filters formed by RFILT and CFILT serve as antialiasing filters for the converter. If an application requires a
steeper filter roll-off, a second-order RC filter can be used.
10.1.3 Multiple Device Configuration
The ADS131A0x allows the designer to add channels to the system by placing an additional device on the SPI
bus. The first device in the chain of devices can be configured using any of the interface modes. All subsequent
devices must be configured in synchronous slave mode. In all cases, however, the chain of ADS131A0x devices
appear to the host as a single device with extra channels with the exception that each device sends individual
status and data integrity words. In this manner, no additional pins on the host are required for more devices on
the chain. There are no special provisions that must be made in the interface except for extending the frame to
the appropriate length.
10.1.3.1 First Device Configured in Asynchronous Interrupt Mode
Figure 96 illustrates a multiple device configuration where the first device is configured in asynchronous interrupt
mode as indicated by the state of the M0 pin. The second ADS131A0x device and any additional devices are
configured in synchronous slave mode. The DONE pin of each device connects to the CS of the subsequent
device. In each case, after a device shifts out all of its data, the device deasserts DONE, selecting the
subsequent device for communication. The DOUT of a device whose contents are already shifted out assumes a
high-impedance state, allowing the DOUT pins of all devices to be tied together. To send commands to specific
devices, send the respective command of the device when that device is selected for communication. The DRDY
output of the first device serves as the DRDY input to all other devices to synchronize conversions. Figure 97
illustrates an example interface timing diagram for this configuration.
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Application Information (continued)
IOVDD
MCU/DSP/FPGA
IOVDD
CS
SCLK
DIN
CS
ADS131A0x
Device 1
SCLK
MOSI
MISO
IRQ
M0
Asynchronous
Interrupt Mode
DOUT
DRDY
DONE
CLK
CLKIN
CS
SCLK
DIN
M0
Float
ADS131A0x
Device 2
DOUT
DRDY
DONE
Synchronous
Slave Mode
CLKIN
To Next Device
Figure 96. Multiple Device Configuration Using Asynchronous Interrupt Mode
DRDY
CS(1)
SCLK
DIN
MSB(1)
LSB(1) MSB(2)
LSB(N)
DOUT
DONE(1), CS(2)
NOTE: (1) denotes device 1, (2) denotes device 2, and (N) denotes device N.
Figure 97. Multiple Device Configuration Timing Diagram when Using Asynchronous Interrupt Mode
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Application Information (continued)
10.1.3.2 First Device Configured in Synchronous Master Mode
Figure 98 shows a multiple device configuration where the first device is configured in synchronous master mode
as indicated by the state of the M0 pin. The second ADS131A0x device and any additional devices are
configured in synchronous slave mode. The DONE pin of each device connects to the CS pin of the subsequent
device. In each case, after a device shifts out all of its data, the device deasserts DONE, selecting the
subsequent device for communication. Tie the DONE pin of the last device to the CS pin of the first device to
allow for an immediate second read back of conversion data in the case a data integrity test failed. The DOUT of
a device whose contents are already shifted out assumes a high-impedance state, allowing the DOUT pins of all
devices to be tied together. To send commands to specific devices, send the respective command of the device
when that device is selected for communication. The DRDY output of the first device serves as the DRDY input
to all other devices to synchronize conversions. DRDY also serves as the chip-select or frame sync signal for the
host. SCLK is free running with the same frequency as ICLK in this configuration.Figure 99 illustrates an example
interface timing diagram for this configuration.
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Application Information (continued)
IOVDD
MCU/DSP/FPGA
SCLK
CS
SCLK
DIN
ADS131A0x
Device 1
M0
MISO
Synchronous
Master Mode
DOUT
DRDY
DONE
MOSI
CS, FSYNC
CLK
CLKIN
CS
SCLK
DIN
ADS131A0x
Device 2
Float
M0
Synchronous
Slave Mode
DOUT
DRDY
DONE
CLKIN
Devices 3
through N-1
CS
ADS131A0x
Device N
SCLK
DIN
Float
M0
Synchronous
Slave Mode
DOUT
DRDY
DONE
CLKIN
Figure 98. Multiple Device Configuration Using Synchronous Master Mode
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Application Information (continued)
DRDY
SCLK
DIN
MSB(1)
LSB(1) MSB(2)
LSB(N)
DOUT
DONE(1), CS(2)
NOTE: (1) denotes device 1, (2) denotes device 2, and (N) denotes device N.
Figure 99. Multiple Device Configuration Timing Diagram When Using Synchronous Master Mode
10.1.3.3 All Devices Configured in Synchronous Slave Mode
Figure 100 illustrates a multiple device configuration where all devices are configured in synchronous slave
mode. Figure 100 illustrates an external clock at the CLKIN pin, but a free-running SCLK can also be used as the
conversion clock in this mode. SCLK must be free-running if the modulator clock is derived from the serial clock
(CLKSRC = 1). See the Synchronous Slave Mode section for more information about clocking the device using
SCLK. The DONE pin of each device connects to the CS pin of the subsequent device for communication. The
DOUT pin of a device whose contents are already shifted out assumes a high-impedance state, allowing the
DOUT pins of all devices to be tied together. To send commands to specific devices, send the respective
command to the device when that device is selected for communication. In this configuration, conversions must
be synchronized by the master. Synchronization is accomplished by tying the chip select or frame sync output of
the host to the DRDY input of each device. See the Synchronous Slave Mode section for more information about
conversion synchronization using slave mode. Figure 101 illustrates an example interface timing diagram for this
configuration.
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Application Information (continued)
IOVDD
MCU/DSP/FPGA
CS, FSYNC
SCLK
CS
SCLK
DIN
ADS131A0x
Device 1
Float
M0
MOSI
Synchronous
Slave Mode
DOUT
DRDY
DONE
MISO
CLK
CLKIN
CS
SCLK
DIN
ADS131A0x
Device 2
Float
M0
Synchronous
Slave Mode
DOUT
DRDY
DONE
CLKIN
To Next Device
Figure 100. Multiple Device Configuration Using Synchronous Slave Mode
DRDY, CS(1)
SCLK
DIN
MSB(1)
LSB(1) MSB(2)
LSB(N)
DOUT
DONE(1), CS(2)
NOTE: (1) denotes device 1, (2) denotes device 2, and (N) denotes device N.
Figure 101. Multiple Device Configuration Timing Diagram When Using Synchronous Slave Mode
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10.2 Typical Application
Figure 102 shows an ADS131A0x device used as part of a power-metering application. The ADS131A0x device
is ideal because this device allows for simultaneous sampling of voltage and current. The upper channel is used
to measure voltage, accomplished by stepping down the line voltage with a voltage divider. The lower channel
measures current directly from the line by measuring voltage across the burden resistors R4.
2.5 V
R3
R3
R1
R1
R1
AVDD
Line
INxP
INxN
R2
C1
Neutral
ADS131A04
R3
R3
2000:1
INxP
INxN
Line Current IN
R4
R4
C1
Line Current OUT
AVSS
-2.5 V
Figure 102. Typical Power Metering Connections
Table 34. Power Metering Design Requirements
10.2.1 Design Requirements
DESIGN PARAMETER
VALUE
230 VRMS at 50 Hz
Voltage input
Current input range
0.05 ARMS to 100 ARMS
< 0.2%
Active power measurement error
74
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ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
10.2.2 Detailed Design Procedure
In this configuration, line voltage is measured as a single-ended input. The 230-VRMS signal must be stepped
down such that the signal peaks fall within the measurement range of the ADS131A04 when using the internal
2.442-V reference. A voltage divider using the series combination of multiple R1 resistors and the R2 resistor
steps the input to within an acceptable range. Using multiple R1 resistors along with proper spacing disperses
energy among several components and provides a line of defense against short-circuits caused when one
resistor fails. The output of this voltage divider can be calculated using Equation 10:
≈
∆
«
’
÷
◊
R2
V
= VLINE
IN
3ìR1 + R2
(10)
If R1 and R2 are chosen as 330 kΩ and 3.9 kΩ, respectively, the voltage at the input of the ADS131A0x is 0.9025
VRMS, corresponding to a 1.276 Vpeak that is within the measurement range of the ADC.
Line current is measured by stepping the input current down through a current transformer (CT) then shunting
the current on the secondary side through burden resistors. Then, the voltage is measured across the resistors
and current is back calculated in the processor. The voltage across the burden resistors R4 is measured
differentially by grounding the node between the two resistors. Equation 11 relates the voltage at the input to the
ADS131A0x to the line current.
2ìILINE ìR4
≈
’
V
=
IN
∆
«
÷
◊
N
(11)
If a CT with a 2000:1 turns ratio is used and R4 is chosen to be 8.2 Ω, then 100 ARMS of line current corresponds
to 0.82 VRMS (1.16 Vpeak) at the input to the ADS131A0x. The design minimum line current of 50 mARMS
corresponds to 0.41 mVRMS (0.58 mVpeak).
The combination of R3 and C1 on each line serves as an antialiasing filter. Having C1 populated differentially
between the inputs helps improve common-mode rejection because the tolerance of the capacitor is shared
between the inputs. The half-power frequency of this filter can be calculated according to Equation 12:
≈
∆
«
’
÷
◊
1
f-3dB
=
4ì pìR3 ìC1
(12)
A filter with R3 populated as 100 Ω and C1 as 2.7 nF gives a cutoff frequency of approximately 295 kHz. This
filter provides nearly 17 dB of attenuation at the modulator frequency when the ADS131A04 modulator frequency
is set to 2.048 MHz. R3 must be kept relatively low because large series resistance degrades THD.
To get an accurate picture of instantaneous power, the phase delay of the current transformer must be taken into
account. Many kinds of digital filters can be implemented in the application processor to delay the current
measurement to better align with the input voltage.
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10.2.3 Application Curve
Figure 103 shows the active power measurement accuracy for the ADS131A0x across varying currents. Data
was taken for a 0.5 lead, 0.5 lag, and unity power factors. For this test, the external 16.384-MHz crystal
frequency was divided to give a modulator frequency of 2.048 MHz. Finally, an OSR of 256 was chosen to give
the ADS131A04 an output data rate of 8 kSPS.
0.5
Power Factor
0.4
Unity
0.5 Lead
0.5 Lag
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
10
20
30
40
50
60
70
80
90 100
Current Magnitude (A)
D007
Figure 103. Active Power Measurement Error
10.3 Do's and Don'ts
•
Do partition the analog, digital, and power-supply circuitry into separate sections on the printed circuit board
(PCB).
•
•
•
•
•
•
•
Do use a single ground plane for analog and digital grounds.
Do place the analog components close to the ADC pins using short, direct connections.
Do keep the SCLK pin free of glitches and noise.
Do verify that the analog input voltages are within the specified voltage range under all input conditions.
Do tie unused analog input pins to GND.
Do provide current limiting to the analog inputs in case overvoltage faults occur.
Do use a low-dropout (LDO) regulator to reduce ripple voltage generated by switch-mode power supplies.
This reduction is especially true for AVDD where the supply noise can affect performance.
•
•
•
Do keep the input series resistance low to maximize THD performance.
Do not cross analog and digital signals.
Do not allow the analog power supply voltages (AVDD – AVSS) to exceed 3.6 V under any conditions,
including during power-up and power-down when the negative charge pump is enabled.
•
•
Do not allow the analog power supply voltages (AVDD – AVSS) to exceed 6 V under any conditions,
including during power-up and power-down when the negative charge pump is disabled.
Do not allow the digital supply voltage to exceed 3.9 V under any conditions, including during power-up and
power-down.
Figure 104 and Figure 105 illustrate correct and incorrect ADC circuit connections.
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ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
Do's and Don'ts (continued)
3.3 V
3.3 V
2.5 V
5 V
CORRECT
CORRECT
AVDD
IOVDD
Device
AVDD
IOVDD
Device
24-Bit
ûꢀ ADC
24-Bit
ûꢀ ADC
AVSS
-2.5 V
GND
AVSS
GND
Low-impedance supply connections.
Low-impedance supply connections.
3.3 V
3.3 V
5 V
5 V
INCORRECT
INCORRECT
AVDD
IOVDD
AVDD
IOVDD
Device
Device
24-Bit
ûꢀ ADC
24-Bit
ûꢀ ADC
AVSS
GND
AVSS
GND
Inductive supply or ground connections.
AGND, DGND isolation.
INCORRECT
Device
CORRECT
Device
5 V
5 V
AVDD
AVDD
24-Bit
ûꢀ ADC
24-Bit
ûꢀ ADC
VNCPEN = 1
VNCPEN = 0
AVSS
AVSS
Charge pump enabled with unipolar analog supply,
AVDD > 3.6 V.
Charge pump disabled with unipolar analog supply,
AVDD > 3.6 V.
CORRECT
3.3 V
AVDD
Device
24-Bit
ûꢀ ADC
VNCPEN = 1
AVSS
Charge pump enabled with unipolar analog supply,
AVDD < 3.6 V.
Figure 104. Correct and Incorrect Circuit Connections
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Do's and Don'ts (continued)
INCORRECT
Device
CORRECT
Device
2.5 V
2.5 V
AVDD
AVDD
24-Bit
24-Bit
ûꢀ ADC
ûꢀ ADC
VNCPEN = 1
VNCPEN = 0
AVSS
-2.5 V
AVSS
-2.5 V
Charge pump is enabled with a bipolar analog supply.
Charge pump is disabled with a bipolar analog supply.
INCORRECT
CORRECT
3.3 V
3.3 V
AVDD
Device
AVDD
Device
AINxP
AINxN
AIN1P
AIN1N
24-Bit
ûꢀ ADC
24-Bit
ûꢀ ADC
+
+
-1 V
-1 V
VNCPEN = 0
VNCPEN = 1
AVSS
AVSS
œ
œ
Input swings below ground, charge pump is disabled.
Input swings below ground, charge pump is enabled.
Figure 105. Correct and Incorrect Circuit Connections, Continued
10.4 Initialization Set Up
Figure 106 illustrates a general procedure to configure the ADS131A0x to collect data.
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ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
Initialization Set Up (continued)
Power Off
// Pull up, pull down or float the M0 pin
Set M0 mode pin
// Analog and Digital supply can come up together
// RESET can come up with Power Supply
Power up
Analog + Digital Supply
SET
RESET = 1
N
// Monitor serial output for 0xFF02 (ADS131A02) or 0xFF04
(ADS131A04)
Wait
Receive READY Word?
Y
// Send UNLOCK command 0x0655
// Receive Command Status Response 0x0655
Unlock Device
// Configure Int/Ext reference, CLK dividers, OSR, comparator
threshold, negative charge pump, and power mode setting
Configure Device
Write Registers
// Use the WREG or WREGS commands
// Verify registers are written successfully
// Device Data Frame or Data Rate may change if coresponding
register is changed
Receive Command Status
Response
Y
Write another register?
N
// Write 0Fh to the ADC_ENA register to enable ADCs
Enable ADCs
Wakeup Device
Lock Registers
// Send WAKEUP command 0x0033
// Start conversions
// Send LOCK command 0x0555
// Use DRDY indicator to indicate new data is available
Capture Data
Figure 106. ADS131A0x Configuration Sequence
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11 Power Supply Recommendations
The device requires two power supplies: analog (AVDD, AVSS) and digital (IOVDD, GND). The analog power
supply can be bipolar (for example, AVDD = 2.5 V, AVSS = –2.5 V), unipolar (for example, AVDD = 5 V, AVSS =
0 V), or unipolar using the negative charge pump (for example, AVDD = 3.3 V, AVSS = VNCP), and is
independent of the digital power supply. The digital supply range sets the digital I/O levels.
11.1 Negative Charge Pump
An optional negative charge pump is available to power AVSS with an operating voltage of –1.95 V. Enabling the
negative charge pump allows for input signals below analog ground when using a unipolar analog supply (for
example, AVDD = 3.3 V, AVSS = 0 V). The VNCPEN bit in the A_SYS_CFG register must be set high by the
user to enable the negative charge pump. The VNCP pin outputs the nominal –1.95-V negative charge pump
output and requires a capacitor to AVSS in the range of 220 pF to 470 pF. The charge pump operates at a
switching frequency of 2fMOD. The minimum ADC absolute input voltage range is –1.5 V with the negative charge
pump enabled. The maximum analog supply limit (AVDD – AVSS) is restricted to 3.6 V maximum. Exceeding this
limit can permanently damage the device.
The negative charge pump is internally activated when the VNCPEN bit is set to 1 and the device is in wake-up
mode with all ADC channels enabled (ADC_ENA = 0Fh).
Connect VNCP directly to AVSS when not using the negative charge pump.
11.2 Internal Digital LDO
The ADS131A0x digital core voltage operates from 1.8 V, created from an internal LDO from IOVDD. The CAP
pin outputs the LDO voltage created from the IOVDD supply and requires an external bypass capacitor. When
operating from VIOVDD > 2 V, place a 1-µF capacitor on the CAP pin to GND. If VIOVDD ≤ 2 V, tie the CAP pin
directly to the IOVDD pin and decouple both pins using a 1-µF capacitor to GND.
11.3 Power-Supply Sequencing
The power supplies can be sequenced in any order but the analog or digital inputs must never exceed the
respective analog or digital power-supply voltage limits.
80
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11.4 Power-Supply Decoupling
Good power-supply decoupling is important to achieve optimum performance. AVDD, AVSS (when using a
bipolar supply), and IOVDD must be decoupled with at least a 1-µF capacitor, as shown in Figure 107,
Figure 108, and Figure 109. A 270-nF capacitor is required on the VNCP pin when using the negative charge
pump. Place the bypass capacitors as close to the power-supply pins of the device as possible with low-
impedance connections. Using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics are recommended for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins can offer superior noise immunity. The use of multiple vias in parallel lowers the
overall inductance and is beneficial for connections to ground planes. The analog and digital ground are
recommended to be connected together as close to the device as possible.
2.5 V 3.3 V
5 V
3.3 V
1 mF
1 mF
1 mF
1 mF
1 mF
-2.5 V
1 mF
AVDD IOVDD
RESV CAP1
AVDD IOVDD
RESV CAP1
CAP2
CAP2
10 pF
REFEXT
REFEXT
10 pF
TI Device
TI Device
1 mF
-2.5 V
1 mF
-2.5 V
1 mF
REFP
REFP
1 mF
REFN
GND
REFN
GND
AVSS
-2.5 V
VNCP
AVSS
VNCP
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
Figure 108. Unipolar Analog Power Supply
Figure 107. Bipolar Analog Power Supply
3.3 V
3.3 V
1 mF
1 mF
1 mF
AVDD
IOVDD
RESV CAP1
CAP2
10 pF
REFEXT
TI Device
1 mF
REFP
1 mF
REFN
GND
AVSS
VNCP
270 nF
Copyright © 2017, Texas Instruments Incorporated
Figure 109. Unipolar Analog Power Supply with Negative Charge Pump Enabled
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12 Layout
12.1 Layout Guidelines
Use a low-impedance connection for ground so that return currents flow undisturbed back to the respective
sources. For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal
traces on this layer. Keep connections to the ground plane as short and direct as possible. When using vias to
connect to the ground layer, use multiple vias in parallel to reduce impedance to ground. Figure 110 shows the
proper component placement for the system.
A mixed-signal layout sometimes incorporates separate analog and digital ground planes that are tied together at
one location; however, separating the ground planes is not necessary when analog, digital, and power-supply
components are properly placed. Proper placement of components partitions the analog, digital, and power-
supply circuitry into different PCB regions to prevent digital return currents from coupling into sensitive analog
circuitry. If ground plane separation is necessary, then make the connection at the ADC. Connecting individual
ground planes at multiple locations creates ground loops, and is not recommended. A single ground plane for the
analog and digital grounds avoids ground loops.
Bypass the supply pins with a low-ESR ceramic capacitor. The placement of the bypass capacitors must be as
close as possible to the supply pins using short, direct traces. For optimum performance, the ground-side
connections of the bypass capacitors must also be made with low-impedance connections. The supply current
flows through the bypass capacitor pin first and then to the supply pin to make the bypassing most effective (also
known as a Kelvin connection). If multiple ADCs are on the same PCB, use wide power-supply traces or
dedicated power-supply planes to minimize the potential of crosstalk between ADCs.
If external filtering is used for the analog inputs, use C0G-type ceramic capacitors when possible. C0G
capacitors have stable properties and low-noise characteristics. Ideally, route differential signals as pairs to
minimize the loop area between the traces. Route digital circuit traces (such as clock signals) away from all
analog pins. Note that the internal reference output return shares the same pin as the AVSS power supply. To
minimize coupling between the power-supply trace and reference return trace, route the two traces separately;
ideally, as a star connection at the AVSS pin.
Treat the AVSS pin as a sensitive analog signal and connect directly to the supply ground with proper shielding.
Leakage currents between the PCB traces can exceed the input bias current of the ADS131A0x if shielding is not
implemented. Keep digital signals as far as possible from the analog input signals on the PCB.
The SCLK input of the serial interface must be free from noise and glitches when this device is configured in a
slave mode. This configuration is especially true when SCLK is used as the master clock for this device. Even
with relatively slow SCLK frequencies, short digital signal rise and fall times can cause excessive ringing and
noise. For best performance, keep the digital signal traces short, using termination resistors as needed, and
make sure all digital signals are routed directly above the ground plane with minimal use of vias.
Ground Fill or
Ground Plane
Ground Fill or
Ground Plane
Supply
Generation
Signal
Conditioning
(RC Filters
and
Interface
Transceiver
Device
Microcontroller
Connector
or Antenna
Amplifiers)
Ground Fill or
Ground Plane
Ground Fill or
Ground Plane
Figure 110. System Component Placement
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ADS131A02, ADS131A04
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ZHCSEV8D –MARCH 2016–REVISED JANUARY 2018
12.2 Layout Example
Figure 111 is an example layout of the ADS131A0x. This example shows the device supplied with a bipolar
supply, though the layout can be replicated for a unipolar case. In general, analog signals and planes are
partitioned to the left and digital signals and planes to the right.
+3.3 V
Via to corresponding
voltage plane or pour
Via to ground plane
or pour
+3.3 V
24: NC
23: CS
1: AIN1N
2: AIN1P
3: AIN2N
4: AIN2P
5: AIN3N
22: SCLK
21:DOUT
Device
20:DIN
6: AIN3P
7: AIN4N
8: AIN4P
19: DRDY
18: DONE
17: RESET
Long digital input lines
terminated with resistors to
prevent reflection
+3.3 V
Inputs filtered with
differential capacitors
-2.5 V
+2.5 V
-2.5 V
Reference, CAP, and power
supply decoupling capacitors
close to pins
-2.5 V
Figure 111. ADS131A0x Layout Example
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13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
请参阅如下相关文档：
•
•
•
《REF50xx 低噪声、极低漂移、高精度电压基准》（文献编号：SBOS410）
《THS4531A 超低功耗、轨到轨输出、全差分放大器》 （文献编号：SLOS823）
《REF60xx 集成 ADC 驱动器缓冲器的高精度电压基准》（文献编号：SBOS708）
13.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即购买的快速链接。
表 35. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
ADS131A02
ADS131A04
13.3 接收文档更新通知
如需接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收
产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS131A02IPBS
ADS131A02IPBSR
ADS131A04IPBS
ADS131A04IPBSR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TQFP
TQFP
TQFP
TQFP
PBS
PBS
PBS
PBS
32
32
32
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
131A02
1000 RoHS & Green
250 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
131A02
131A04
131A04
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS131A02IPBSR
ADS131A04IPBSR
TQFP
TQFP
PBS
PBS
32
32
1000
1000
330.0
330.0
16.4
16.4
7.2
7.2
7.2
7.2
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS131A02IPBSR
ADS131A04IPBSR
TQFP
TQFP
PBS
PBS
32
32
1000
1000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
ADS131A02IPBS
ADS131A04IPBS
PBS
PBS
TQFP
TQFP
32
32
250
250
10 X 25
10 X 25
150
150
315 135.9 7620 12.2
315 135.9 7620 12.2
11.1 11.25
11.1 11.25
Pack Materials-Page 3
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