ADS1284IRHFT [TI]
用于地震监测和地球空间探测且具有 PGA 和低功耗模式的超高分辨率 4kSPS 2 通道 ADC | RHF | 24 | -40 to 85;
| 型号： | ADS1284IRHFT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于地震监测和地球空间探测且具有 PGA 和低功耗模式的超高分辨率 4kSPS 2 通道 ADC | RHF | 24 | -40 to 85 转换器 |
| 文件： | 总67页 (文件大小：2289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS1284
ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
ADS1284 高分辨率模数转换器
1 特性
3 说明
1
•
•
可选择工作模式
低功耗模式：
ADS1284 是一款高性能、单芯片模数转换器 (ADC)。
该器件包括一个低噪声可编程增益放大器 (PGA)、Δ-Σ
调制器和数字滤波器。该 ADC 支持两种运行模式，可
在功耗与分辨率之间实现最佳平衡。
–
–
12mW（PGA = 1、2、4 和 8）
127dB SNR（250 SPS，PGA = 1）
•
高分辨率模式：
双通道多路复用器具有用于信号测量和 ADC 信号测试
的输入。具有使输入电路短路和测试内部噪声的模式。
PGA 具有高输入阻抗和低噪声，可与地震检波器和水
听器传感器直接连接。
–
–
18mW（PGA = 1、2、4 和 8）
130dB SNR（250 SPS，PGA = 1）
•
•
•
•
•
•
THD：–122dB
CMRR：110dB
四阶固有稳定性调制器可提供出色的低噪声和线性性
能。调制器输出由片上数字滤波器进行过滤和抽取，以
生成 ADC 转换结果。
双通道多路复用器
固有稳定性调制器
快速响应超范围检测器
灵活的数字滤波器：
数字滤波器提供 250 至 4000 SPS 的数据速率。高通
滤波器 (HPF) 具有可编程转角频率。片上增益和偏移
调节寄存器支持系统校准。
–
正弦 + 有限脉冲响应 (FIR) + 无限脉冲响应
(IIR)（可选）
–
–
线性或最小相位选项
可编程高通滤波器
同步输入控制 ADC 转换的时序。关断输入使 ADC 进
入关断模式。
•
•
•
•
偏移和增益校准
ADS1284 采用紧凑的 24 引线 5mm x 4mm VQFN 封
装，完整额定工作温度为 –40°C 至 +85°C，最大工作
温度范围为 –50°C 至 +125°C。
SYNC 输入
模拟电源：5V 或 ±2.5V
数字电源：1.8V 至 3.3V
器件信息
2 应用
器件型号
ADS1284
封装
VQFN (24)
封装尺寸（标称值）
•
•
•
能量勘探
5.00mm × 4.00mm
地震监测
(1) 要了解所有可用封装，请参阅数据表末尾的封装选项附录。
高精度仪器
简化原理图
AVDD
VREFN
DVDD
VREFP
ADS1284
CLK
CS
Input 1
Input 2
SCLK
DOUT
Serial
Interface
4th-Order
ûꢀ Modulator
Programmable
Digital Filter
Calibration
PGA
DIN
VCOM
DRDY
SYNC
RESET
PWDN
Over-Range
Control
AVSS
DGND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS943
ADS1284
ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
www.ti.com.cn
目录
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 33
8.5 Programming........................................................... 45
8.6 Register Maps......................................................... 49
Application and Implementation ........................ 53
9.1 Application Information............................................ 53
9.2 Typical Applications ................................................ 53
9.3 Initialization Set Up ................................................. 56
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings .................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements............................................... 8
6.7 Switching Characteristics.......................................... 8
6.8 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 15
7.1 Noise Performance ................................................. 15
Detailed Description ............................................ 17
9
10 器件和文档支持 ..................................................... 57
10.1 接收文档更新通知 ................................................. 57
10.2 社区资源................................................................ 57
10.3 商标....................................................................... 57
10.4 静电放电警告......................................................... 57
10.5 Glossary................................................................ 57
11 机械、封装和可订购信息....................................... 58
7
8
4 修订历史记录
Changes from Original (September 2018) to Revision A
Page
•
已更改 将文档更改为面向 Web 的完整发布版........................................................................................................................ 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
ADS1284
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ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
5 Pin Configuration and Functions
RHF Package
5-mm × 4-mm 24-Pin VQFN
Top View
DRDY
DOUT
DIN
1
2
3
4
5
6
7
19
18
17
16
15
14
13
RESET
PWDN
VREFP
VREFN
AVSS
Thermal
Pad
CS
SYNC
MFLAG
DGND
AVDD
AINN1
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
AINN1
AINN2
AINP1
AINP2
AVDD
AVSS
BYPAS
CAPN
CAPP
CLK
NO.
13
11
12
10
14
15
22
8
Analog input
Analog input
Analog input
Analog input
Analog supply
Analog supply
Analog
Negative analog input 1
Negative analog input 2
Positive analog input 1
Positive analog input 2
Positive analog power supply
Negative analog power supply
1.8-V sub-regulator output: connect 1-μF capacitor to DGND
PGA output: connect 10-nF capacitor from CAPP to CAPN
PGA output: connect 10-nF capacitor from CAPP to CAPN
Master clock input (4.096 MHz)
Analog
9
Analog
23
4
Digital input
Digital input
Ground
CS
Serial interface chip select, active low
Digital ground (tie to digital ground plane)
Digital ground (tie to digital ground plane)
Serial interface data input
DGND
DGND
DIN
7
21
3
Ground
Digital input
Digital output
Digital output
Digital supply
Digital output
Digital input
Digital input
Digital input
Digital input
Analog input
Analog input
DOUT
DRDY
DVDD
MFLAG
PWDN
RESET
SCLK
SYNC
VREFN
VREFP
2
Serial Interface data output
1
Data ready output: active low
20
6
Digital power supply. If DVDD < 2.25 V, connect DVDD and BYPAS pins together.
Modulator overrange flag: 0 = normal, 1 = modulator overrange
Power-down input, active low
18
19
24
5
Reset input, active low
Serial interface shift clock input
Synchronize input, rising edge active
Negative reference input
16
17
Positive reference input
Do not electrically connect the thermal pad. The thermal pad must be soldered to PCB.
Thermal pad vias are optional and can be removed.
Thermal pad
Copyright © 2018–2019, Texas Instruments Incorporated
3
ADS1284
ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
Over operating free-air temperature range (unless otherwise noted).
MIN
–0.3
MAX
UNIT
V
AVDD to AVSS
5.5
AVSS to DGND
–2.8
0.3
3.9
V
DVDD to DGND
–0.3
V
Analog input voltage
Digital input voltage to DGND
Input current, continuous
Operating temperature
Junction temperature
Storage temperature, Tstg
AVSS – 0.3
–0.3
AVDD + 0.3
DVDD + 0.3
10
V
V
–10
mA
°C
°C
°C
–50
125
150
–60
150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
POWER SUPPLY
AVSS
AVDD
DVDD
Negative analog supply (relative to DGND)
–2.6
AVSS + 4.75
1.65
0
AVSS + 5.25
3.6
V
V
V
Positive analog supply (relative to AVSS)
Digital supply (relative to DGND)
ANALOG INPUTS
FSR
Full-scale input voltage range (VIN = AINP – AINN)
±VREF / (2 × PGA)
V
Calibration margin(1)
106
%FSR
AINP or
AINN
Absolute input voltage range
AVSS + 0.7
AVDD – 1.25
V
VOLTAGE REFERENCE INPUTS
Reference input voltage (VREF = VREFP – VREFN)
Negative reference input
Positive reference input
1
AVSS – 0.1
VREFN + 1
5
AVDD – AVSS + 0.2
VREFP – 1
V
V
V
VREFN
VREFP
AVDD + 0.1
DIGITAL INPUTS
VIH
High-level input voltage
0.8 × DVDD
DVDD
0.2 × DVDD
4.096
V
VIL
Low-level input voltage
Clock input
DGND
1
V
fCLK
fSCLK
MHz
MHz
Serial clock rate
fCLK / 2
TEMPERATURE
Specified temperature
–40
85
°C
(1) Calibration margin is the maximum allowable input voltage after user calibration of offset and gain errors.
4
Copyright © 2018–2019, Texas Instruments Incorporated
ADS1284
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ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
6.4 Thermal Information
ADS1284
THERMAL METRIC(1)
RHF (VQFN)
24 PINS
30.2
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
27.5
8.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
8.6
RθJC(bot)
1.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
maximum and minimum specifications over –40°C to +85°C; typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V,
fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, High-Resolution and Low-Power modes,
Offset enabled (75 mV), Chop enable, and fDATA = 1000 SPS (unless otherwise noted)
PARAMETER
ANALOG INPUTS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low-power mode
7.5
5
PGA input voltage noise density
Differential input impedance(1)
nV/√Hz
GΩ
High-resolution mode
CHOP enabled
1
CHOP disabled
100
1
Common-mode input impedance
Input bias current
GΩ
nA
dB
Ω
IIB
1
Crosstalk
f = 31.25 Hz
Each switch
–135
30
Mux switch on-resistance
PGA OUTPUT (CAPP, CAPN)
Absolute output range
AVSS + 0.4
AVDD – 0.4
100
V
PGA output impedance
Differential
600
±10%
10
Ω
Output impedance tolerance
External bypass capacitance
nF
Low-power mode
110
55
Modulator input impedance
kΩ
High-resolution mode
AC PERFORMANCE
Low-power mode
High-resolution mode
Low-power mode
PGA = 1, 2, 4, 8, 16
PGA = 32
117
120
121
124
SNR
Signal-to-noise ratio(2)
dB
dB
–122
–117
–114
-114
-108
PGA = 64
THD
Total harmonic distortion(3)
Spurious-free dynamic range
High-resolution mode
PGA = 1, 2, 4, 8, 16
PGA = 32
-122
-117
-114
123
-114
-110
dB
dB
PGA = 64
SFDR
(1) PGA chop mode is controlled by register setting.
(2) Inputs shorted; see Table 1 through Table 4 for more details.
(3) Input signal = 31.25 Hz, –0.5 dBFS.
Copyright © 2018–2019, Texas Instruments Incorporated
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ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
www.ti.com.cn
Electrical Characteristics (continued)
maximum and minimum specifications over –40°C to +85°C; typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V,
fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, High-Resolution and Low-Power modes,
Offset enabled (75 mV), Chop enable, and fDATA = 1000 SPS (unless otherwise noted)
PARAMETER
DC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
31
250
Bits
FIR filter mode
4000
128,000
±200
fDATA
Data rate
SPS
Sinc filter mode
Offset disabled
8000
±50
300
µV
Offset and Chop disabled
75 mV offset
Offset(4)
70 / PGA
95 / PGA
75 / PGA
100 / PGA
1
80 / PGA
mV
μV
100 mV offset
105 / PGA
Offset after calibration(5)
Offset drift
0.03
μV/°C
CHOP disabled
0.5
Low-power mode
High-resolution mode
-1%
-0.5%
–1.0%
0.0002%
2
0%
Gain error(6)
–1.5%
–0.5%
Gain error after calibration(5)
Gain drift
PGA = 1
ppm/°C
PGA = 16
9
Gain matching(7)
0.3%
110
0.8%
(8)
CMR
PSR
Common-mode rejection
fCM = 60 Hz, 1.25 VPP
95
80
90
dB
dB
AVDD, AVSS
DVDD
90
fPS = 60 Hz,
Power-supply rejection
(8)
100 mVPP
115
VOLTAGE REFERENCE INPUTS
Low-power mode
170
85
Reference input impedance
kΩ
High -resolution mode
DIGITAL FILTER RESPONSE
Pass-band ripple
±0.003
10
dB
Hz
Hz
Hz
dB
Hz
Pass band (–0.01dB)
Bandwidth (–3dB)
0.375 × fDATA
0.413 × fDATA
High-pass filter corner
Stop band attenuation(9)
Stop band
0.1
135
0.500 × fDATA
5 / fDATA
Minimum phase filter(10)
Linear phase filter
Group delay
s
s
31 / fDATA
62 / fDATA
62 / fDATA
Minimum phase filter
Linear phase filter
Settling time (latency)
(4) Offset specification is input referred. The offset scales by the reference voltage (VREF).
(5) Calibration accuracy is on the level of noise reduced by four (calibration averages 16 readings).
(6) The PGA output impedance and the modulator input impedance results in systematic gain error.
(7) Gain match relative to gain = 1.
(8) fCM is the input common-mode frequency. fPS is the power-supply frequency.
(9) Input frequencies in the range of N · fCLK / 1024 ± fDATA / 2 (where N = 1, 2, 3...) can intermodulate with the modulator chopper clock
(and N multiples). At these frequencies, intermodulation = –120 dB, typ.
(10) At dc; see Figure 50.
6
Copyright © 2018–2019, Texas Instruments Incorporated
ADS1284
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ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
Electrical Characteristics (continued)
maximum and minimum specifications over –40°C to +85°C; typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V,
fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, High-Resolution and Low-Power modes,
Offset enabled (75 mV), Chop enable, and fDATA = 1000 SPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS/OUTPUTS
VOH
VOL
Ilkg
High-level output voltage
Low-level output voltage
Input leakage
IOH = 1 mA
0.8 × DVDD
V
V
IOL = 1 mA
0.2 × DVDD
±10
0 < VDIGITAL IN < DVDD
μA
POWER SUPPLY
Low-power mode
PGA = 1, 2, 4, 8
PGA = 16, 32, 64
High-resolution mode
PGA = 1, 2, 4, 8
PGA = 16, 32, 64
Standby mode
2
3.4
3.8
mA
2.5
IAVDD
IAVSS
Analog supply current
3.2
4
5.5
6
mA
μA
1
15
15
0.7
0.8
50
15
Power-down mode
Low-power mode
High-resolution mode
Standby mode
Power-down mode(11)
Low-power mode
PGA = 1, 2, 4, 8
PGA = 16, 32, 64
High-resolution mode
PGA = 1, 2, 4, 8
PGA = 16, 32, 64
Standby mode
1
0.5
0.6
25
1
mA
μA
IDVDD
Digital supply current
12
14
20
22
mW
PD
Power dissipation
18
22
90
10
30
33
mW
250
125
μW
Power-down mode
(11) CLK input stopped.
Copyright © 2018–2019, Texas Instruments Incorporated
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6.6 Timing Requirements
at TA = –40°C to +85°C and DVDD = 1.65 V to 3.6 V (unless otherwise noted)
MIN
40
MAX
UNIT
ns
tCSSC
tSCLK
tSPWH, L
tDIST
CS low to SCLK high: setup time
SCLK period
SCLK pulse duration, high and low(1)
DIN valid to SCLK high: setup time
Valid DIN to SCLK high: hold time
CS high pulse
2
16
10
1 / fCLK
1 / fCLK
ns
0.8
50
tDIHD
50
ns
tCSH
100
24
ns
tSCCS
SCLK high to CS high
1/fCLK
(1) Holding SCLK low for 64 DRDY falling edges resets the serial interface.
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
60
UNIT
CS low to DOUT driven: propagation
delay
tCSDOD
tDOPD
ns
SCLK low to valid new DOUT:
propagation delay
Load on DOUT = 20 pF || 100 kΩ
100
ns
SCLK low to DOUT invalid: hold
time
tDOHD
0
ns
ns
tCSDOZ
CS high to DOUT tristate
40
tSPWH
tSCLK
tCSH
CS
tSPWL
tCSSC
tSCCS
SCLK
tDIST
B7
DIN
B6
tDIHD
B5
B4
B3
B2
B1
B0
tDOPD
DOUT
B7
tDOHD
tCSDOD
tCSDOZ
Figure 1. Serial Interface Timing Diagram
8
Copyright © 2018–2019, Texas Instruments Incorporated
ADS1284
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ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
6.8 Typical Characteristics
At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, High-Resolution
Mode, OFFSET enabled, CHOP enabled, and fDATA = 1000 SPS (unless otherwise noted).
0
0
Low-Power Mode
8192-Point FFT
Shorted Input
PGA = 1
8192-Point FFT
Shorted Input
PGA = 1
-20
-40
œ20
œ40
SNR = 123.7 dB
SNR = 121.1 dB
-60
œ60
-80
œ80
-100
-120
-140
-160
-180
œ100
œ120
œ140
œ160
œ180
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
0
50 100 150 200 250 300 350 400 450 500
D027
Frequency (Hz)
C002
Figure 3. Output Spectrum (Low-Power mode)
Figure 2. Output Spectrum
0
0
-20
8192-Point FFT
Shorted Input
PGA = 8
Low-Power Mode
8192-Point FFT
Shorted Input
PGA = 8
œ20
œ40
-40
SNR = 121.1 dB
SNR = 118.5 dB
œ60
-60
œ80
-80
œ100
œ120
œ140
œ160
œ180
-100
-120
-140
-160
-180
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
Frequency (Hz)
C003
D028
Figure 4. Output Spectrum
Figure 5. Output Spectrum (Low-Power Mode)
0
œ20
0
-20
Low-Power Mode
8192-Point FFT
Shorted Input
PGA = 1
CHOP Disabled
SNR = 120.9 dB
8192-Point FFT
Shorted Input
PGA = 1
CHOP DIsabled
SNR = 123.5 dB
œ40
-40
œ60
-60
œ80
-80
œ100
œ120
œ140
œ160
œ180
-100
-120
-140
-160
-180
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
Frequency (Hz)
C004
D029
Figure 6. Output Spectrum
Figure 7. Output Spectrum (Low-Power Mode)
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Typical Characteristics (continued)
At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1,
High-Resolution Mode, OFFSET enabled, CHOP enabled, and fDATA = 1000 SPS (unless otherwise noted).
0
0
8192-Point FFT
Shorted Input
PGA = 8
CHOP Disabled
SNR = 117.5 dB
Low-Power Mode
8192-Point FFT
Shorted Input
PGA = 8
CHOP Disabled
SNR = 116.3 dB
œ20
-20
œ40
-40
œ60
-60
œ80
-80
œ100
œ120
œ140
œ160
œ180
-100
-120
-140
-160
-180
0
0
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
Frequency (Hz)
C005
D030
Figure 8. Output Spectrum
Figure 9. Output Spectrum (Low-Power Mode)
0
œ20
0
-20
Low-Power Mode
8192-Point FFT
VIN = 31.25 Hz, -0.5 dBFS
PGA = 1
8192-Point FFT
V IN = 31.25 Hz, -0.5 dBFS
PGA = 1
œ40
-40
THD = -124 dB
THD = -122 dB
œ60
-60
œ80
-80
œ100
œ120
œ140
œ160
œ180
-100
-120
-140
-160
-180
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
Frequency (Hz)
C002
D031
Figure 10. Output Spectrum
Figure 11. Output Spectrum (Low-Power Mode)
0
œ20
0
-20
Low-Power Mode
8192-Point FFT
VIN = 31.25 Hz, -0.5 dBFS
PGA = 8
8192-Point FFT
V IN = 31.25 Hz, -0.5 dBFS
PGA = 8
œ40
-40
THD = -125 dB
THD = -122 dB
œ60
-60
œ80
-80
œ100
œ120
œ140
œ160
œ180
-100
-120
-140
-160
-180
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
Frequency (Hz)
C002
D0312
Figure 12. Output Spectrum
Figure 13. Output Spectrum (Low-Power Mode)
10
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Typical Characteristics (continued)
At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1,
High-Resolution Mode, OFFSET enabled, CHOP enabled, and fDATA = 1000 SPS (unless otherwise noted).
0
0
8192-Point FFT
V IN = 31.25 Hz, -20 dBFS
PGA = 1
8192-Point FFT
V IN = 31.25 Hz, -20 dBFS
PGA = 8
œ20
œ20
œ40
œ40
THD = -122 dB
THD = -121 dB
œ60
œ60
œ80
œ80
œ100
œ120
œ140
œ160
œ180
œ100
œ120
œ140
œ160
œ180
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
Frequency (Hz)
C002
C002
Figure 14. Output Spectrum
Figure 15. Output Spectrum
œ100
œ105
œ110
œ115
œ120
œ125
œ130
-100
-105
-110
-115
-120
-125
-130
PGA = 1
PGA = 1
VIN = 31.25 Hz, -0.5 dBFS
Low-Power Mode
PGA = 4
PGA = 4
PGA = 16
PGA = 64
VIN = 31.25 Hz, -0.5 dBFS
PGA = 16
PGA = 64
œ55 œ35 œ15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (°C)
C007
D025
Figure 16. THD vs Temperature
Figure 17. THD vs Temperature (Low-Power Mode)
140
œ100
œ105
œ110
œ115
œ120
œ125
œ130
PGA = 1
V IN = -0.5 dBFS
PGA = 4
PGA = 16
PGA = 64
130
120
110
100
90
80
PGA = 1
PGA = 8
70
0
10 20 30 40 50 60 70 80 90 100 110 120
Signal Frequency (Hz)
10
100
1000
10000
100000
1000000
Common Mode Frequency (Hz)
C002
C007
Figure 18. THD vs Signal Frequency
Figure 19. CMR vs Common-Mode Frequency
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Typical Characteristics (continued)
At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1,
High-Resolution Mode, OFFSET enabled, CHOP enabled, and fDATA = 1000 SPS (unless otherwise noted).
100
90
80
70
60
50
40
30
20
10
0
140
120
100
80
30 Units
OFFSET Enabled
PGA = 1
60
40
DVDD
AVDD
AVSS
20
0
10
100
1000
10000
100000
1000000
Power Supply Frequency (Hz)
C007
Offset (mV)
C010
C010
C010
Figure 20. PSR vs Power-Supply Frequency
Figure 21. Offset-Voltage Histogram
100
90
80
70
60
50
40
30
20
10
0
120
110
100
90
80
70
60
50
40
30
20
10
0
PGA = 1
PGA = 8
30 Units
PGA = 1
30 units based on
20 •C intervals
over the range
-40•C to +85 •C
Offset Drift (nV/°C)
Gain Error (%)
C010
Figure 22. Offset-Voltage Drift Histogram
Figure 23. Gain-Error Histogram
150
140
130
120
110
100
90
120
110
100
90
80
70
60
50
40
30
20
10
0
30 units based on 20•C intervals
over the range -40°C to +85°•C
PGA = 1,2,4
PGA = 16
Worst case gain match
30 units, relative PGA = 1
over -40 °C to +85°C range
PGA = 8,32,64
80
70
60
50
40
30
20
10
0
Gain Drift (ppm/°C)
Gain Match (%)
C010
Figure 24. Gain-Error Drift Histogram
Figure 25. Gain-Match Histogram
12
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Typical Characteristics (continued)
At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1,
High-Resolution Mode, OFFSET enabled, CHOP enabled, and fDATA = 1000 SPS (unless otherwise noted).
125
120
115
110
105
100
95
125
120
115
110
105
100
95
PGA = 1
PGA = 4
PGA = 16
PGA = 64
PGA = 1
PGA = 4
PGA = 16
PGA = 64
Low-Power Mode
Shorted Input
Shorted Input
85 105 125
90
90
-55
œ55 œ35 œ15
5
25
45
65
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (°C)
C008
D026
Figure 26. SNR vs Temperature
Figure 27. SNR vs Temperature (Low-Power Mode)
0
œ20
25
8192-Point FFT (IN1)
IN1: Shorted
IN2: 31.25 Hz, -0.5 dBFS
PGA = 8
20
15
10
5
œ40
œ60
œ80
œ100
œ120
œ140
œ160
œ180
High-Resolution Mode, PGA = 1, 2, 4, 8
High-Resolution Mode, PGA = 16, 32, 64
Low-Power Mode, PGA = 1, 2, 4, 8
Low-Power Mode, PGA = 16, 32, 64
0
0
50 100 150 200 250 300 350 400 450 500
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Frequency (Hz)
C005
D009
Figure 28. Crosstalk Output Spectrum
Figure 29. Power vs Temperature
2.0
1.5
2.0
1.5
P Input, T = 25°C
P Input, T = 25°C
CHOP Enabled
PGA = 1
CHOP Disabled
PGA = 1
N Input, T = 25°C
P Input, T = 85°C
N Input, T = 85°C
N Input, T = 25°C
P Input, T = 85°C
N Input, T = 85°C
1.0
1.0
0.5
0.5
0.0
0.0
œ0.5
œ1.0
œ1.5
œ2.0
œ0.5
œ1.0
œ1.5
œ2.0
œ2.5 œ2.0 œ1.5 œ1.0 œ0.5 0.0 0.5 1.0 1.5 2.0 2.5
œ2.5 œ2.0 œ1.5 œ1.0 œ0.5 0.0 0.5 1.0 1.5 2.0 2.5
Differential Input Voltage (V)
Differential Input Voltage (V)
C002
C002
Figure 30. Input Bias Current vs Input Voltage
Figure 31. Input Bias Current vs Input Voltage
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Typical Characteristics (continued)
At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1,
High-Resolution Mode, OFFSET enabled, CHOP enabled, and fDATA = 1000 SPS (unless otherwise noted).
86
84
82
80
78
76
74
72
180
176
172
168
164
160
156
152
ã High-Resolution Mode
Low-Power Modeç
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
D024
Figure 32. Reference Input Impedance vs Temperature
14
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7 Parameter Measurement Information
7.1 Noise Performance
The ADS1284 offers outstanding signal-to-noise ratio (SNR). SNR depends on data rate, gain and mode of
operation (high resolution or low power). As the bandwidth is reduced by decreasing the data rate, SNR
improves correspondingly. Similarly, as gain is increased, the input-referred noise decreases. The low power
mode decreases the oversampling ratio of the modulator and reduces the bias current of the PGA. As a
consequence, low-power mode reduces the operating power but also results in increased conversion noise. The
ADC incorporates a chop mode to remove 1/f noise from the PGA. Chop mode results in increased input current
and as a result, chop mode may not be compatible with certain types of hydrophone sensors.
Input-referred noise is related to SNR by Equation 1:
FSRRMS
SNR = 20log
NRMS
where
•
•
FSRRMS = Full-scale range RMS = VREF / (2 × √2 × PGA)
NRMS = Noise (RMS, input-referred)
(1)
Table 1 summarizes SNR and input-referred noise performance in low-power mode (chop enabled). Table 2
summarizes SNR and input-referred noise performance in low-power mode (chop disabled).
Table 1. Low-Power Mode SNR (dB) and Input Referred Noise (µVRMS), Chop Enabled
PGA (SNR, dB)(1)
PGA (Input-Referred Noise, µV RMS)
DATA RATE
(SPS)
1
2
4
8
16
32
64
1
2
4
8
16
32
64
250
500
127
124
121
118
115
127
124
121
118
114
126
123
120
117
114
124
121
118
115
112
122
119
116
113
110
116
113
110
107
104
111
108
105
102
99
0.79
1.13
1.60
2.27
3.27
0.41
0.58
0.82
1.16
1.68
0.22
0.31
0.44
0.63
0.90
0.14
0.19
0.27
0.39
0.56
0.09
0.13
0.18
0.26
0.37
0.09
0.12
0.17
0.24
0.34
0.08
0.11
0.16
0.22
0.32
1000
2000
4000
(1) Typical values at TA = 25°C. SNR data rounded to the nearest dB. Measurement bandwidth: 0.1 Hz to 0.413 × data rate.
Table 2. Low-Power Mode SNR (dB) and Input Referred Noise (µVRMS), Chop Disabled
PGA (SNR, dB)(1)
PGA (Input-Referred Noise, µV RMS)
DATA RATE
(SPS)
1
2
4
8
16
32
64
102
101
100
99
1
2
4
8
16
32
64
250
500
127
124
121
118
115
126
123
120
118
114
122
121
119
116
114
119
117
116
114
111
114
113
112
110
108
107
107
106
104
102
0.82
1.16
1.61
2.28
3.29
0.47
0.63
0.85
1.19
1.70
0.34
0.38
0.50
0.68
0.94
0.25
0.30
0.37
0.47
0.62
0.22
0.25
0.29
0.35
0.43
0.24
0.25
0.29
0.35
0.43
0.23
0.25
0.27
0.32
0.40
1000
2000
4000
97
(1) Typical values at TA = 25°C. SNR data rounded to the nearest dB. Measurement bandwidth: 0.1 Hz to 0.413 × data rate.
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Table 3 summarizes SNR and input-referred noise performance in high-resolution mode (chop enabled). Table 4
summarizes SNR and input-referred noise performance in high-resolution mode (chop disabled).
Table 3. High-Resolution Mode SNR (dB) and Input Referred Noise (µVRMS), Chop Enabled
PGA (SNR, dB)(1)
PGA (Input-Referred Noise, µV RMS)
DATA RATE
(SPS)
1
2
4
8
16
32
64
1
2
4
8
16
32
64
250
500
130
127
124
121
117
129
126
123
120
117
129
126
123
120
117
127
124
121
118
115
125
122
119
116
113
119
116
113
110
107
114
111
108
105
102
0.59
0.84
1.19
1.68
2.40
0.30
0.43
0.60
0.86
1.22
0.16
0.23
0.32
0.46
0.66
0.10
0.14
0.20
0.28
0.40
0.07
0.09
0.13
0.18
0.26
0.06
0.09
0.12
0.17
0.25
0.06
0.08
0.11
0.16
0.23
1000
2000
4000
(1) Typical values at TA = 25°C. SNR data rounded to the nearest dB. Measurement bandwidth: 0.1 Hz to 0.413 × data rate.
Table 4. High-Resolution Mode SNR (dB) and Input Noise (µVRMS), Chop Disabled
PGA (SNR, dB)(1)
PGA (Input-Referred Noise, µV RMS)
DATA RATE
(SPS)
1
2
4
8
16
32
64
1
2
4
8
16
32
64
250
500
129
126
123
120
117
128
125
123
120
117
125
123
121
119
116
120
119
117
116
114
116
114
114
112
111
110
108
108
107
105
104
103
102
101
99
0.63
0.87
1.20
1.69
2.41
0.37
0.47
0.65
0.91
1.24
0.26
0.31
0.39
0.51
0.70
0.21
0.25
0.30
0.37
0.46
0.18
0.21
0.22
0.26
0.33
0.17
0.21
0.22
0.25
0.31
0.18
0.20
0.22
0.25
0.30
1000
2000
4000
(1) Typical values at TA = 25°C. SNR data rounded to the nearest dB. Measurement bandwidth: 0.1 Hz to 0.413 × data rate.
16
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8 Detailed Description
8.1 Overview
The ADS1284 is a high-performance analog-to-digital converter (ADC) designed for energy exploration, seismic
monitoring, laboratory instrumentation, and other exacting performance applications. The converter provides 31-
bit resolution in data rates from 250 SPS to 4000 SPS. See the Functional Block Diagram section for a block
diagram of the ADS1284.
The ADS1284 provides two modes of operation, high resolution and low power. The modes offer a tradeoff
between power consumption and SNR performance. For most ADC configurations, low-power mode reduces
power consumption 6 mW but results in an average 3 dB decrease of SNR. The operating mode is programmed
by the MODE register bit (see Figure 71).
The two-channel, differential-input multiplexer allows several measurement configurations:
1. Input 1 (AINP1 - AINN1)
2. Input 2 (AINP2 - AINN2)
3. All inputs disconnected. PGA internally shorted to VCOM via 400-Ω resistors for ADC noise test.
4. Input 1 and input 2 connected together to the PGA for measurement
5. PGA inputs connected to AINN2 for common-mode test.
The input multiplexer is followed by a continuous-time PGA featuring very low noise. The gain of the PGA is
programmed by register settings (gains 1 to 64). A external 10-nF C0G capacitor connected to CAPP and CAPN
provides the ADC antialias filter.
The inherently-stable, fourth-order, delta-sigma modulator measures the differential input signal (VIN = AINP –
AINN) against the differential reference (VREF = (VREFP – VREFN) / 2) to yield differential input voltage range =
±2.5 V (PGA = 1). A digital output (MFLAG) indicates the modulator is in overload as a result of an overdrive
condition. The modulator digital output data is routed to the digital filter to provide the conversion output data.
The digital filter consists of a variable decimation rate, fifth-order sinc filter, followed by a variable phase, fixed-
decimation, finite-impulse response (FIR) low-pass filter with programmable phase. The last filter stage is an
adjustable high-pass filter for dc and low frequency signal removal. The output of the digital filter can be taken
from the sinc or the FIR filter stages, with the option of the FIR plus high-pass filter stages.
Gain and offset registers scale the output of the digital filter to produce the final output conversion data. The
scaling feature can be used for calibration and sensor gain matching.
The SYNC input resets the operation of both the digital filter and the modulator, synchronizing the conversions of
multiple ADCs to an external timing event. The SYNC input supports a continuous input mode that accepts an
external data frame clock that is locked to the conversion rate. Automatic synchronization occurs when the
periods are mismatched.
The RESET input resets the register settings and also restarts the conversion process.
The PWDN input sets the device into power down. Note that register settings are not retained in PWDN mode.
Use the STANDBY command for software power down (the quiescent current in standby mode is slightly higher).
Noise-immune Schmitt-trigger and clock-qualified inputs (RESET and SYNC) increase reliability in high-noise
environments. The SPI™-compatible serial interface is used to read conversion data, in addition to reading from
and writing to the configuration registers.
The device supports either unipolar (+5 V) or bipolar (±2.5 V) supply operation. The digital supply range 1.8 V to
3.3 V.
An internal subregulator powers the digital core from the DVDD supply. BYPAS (pin 28), is the subregulator
output and requires a 1-μF capacitor for noise reduction. Note that the regulated output voltage on BYPAS is not
available to drive external circuitry.
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8.2 Functional Block Diagram
AVDD
BYPAS DVDD
CLK
+1.8 V
(Digital core)
LDO
AINP2
AINN2
AINP1
AINN1
300
300
W
W
CS
4th-Order
ûꢀ
Modulator
SCLK
DIN
Programmable
Digital Filter
Serial
PGA
Calibration
Interface
DOUT
Overrange
Detection
DRDY
SYNC
400 Ω
400 Ω
Control
RESET
PWDN
AVDD + AVSS
2
AVSS
MFLAG
DGND
8.3 Feature Description
8.3.1 Analog Inputs and Multiplexer
A diagram of the input multiplexer is shown in Figure 33.
AVDD
S1
S2
AINP1
ESD Diodes
AINP2
(+)
400W
S3
S7
AVSS
To PGA
AVDD + AVSS
AVDD
2
400W
S4
S5
S6
AINN1
AINN2
(-)
ESD Diodes
AVSS
Figure 33. Analog Inputs and Multiplexer
ESD diodes protect the multiplexer inputs. If either input is taken below AVSS – 0.3 V, or above AVDD + 0.3 V,
the ESD protection diodes can turn on. If these conditions are possible, use external clamp diodes, series
resistors, or both to limit the input current to safe values (see the Absolute Maximum Ratings table).
18
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Feature Description (continued)
Overdriving one unused input can affect the conversions of the other input. If an overdriven input interacts with
the measured input, clamp the overdriven signal with external Schottky diodes.
The specified input operating range of the PGA is shown in Equation 2:
AVSS + 0.7V < (AINN or AINP) < AVDD - 1.25V
(2)
For best operation, maintain absolute input levels (input signal level and common-mode level) within these limits.
The multiplexer connects one of the two external differential inputs to the preamplifier inputs, in addition to
internal connections for various self-test modes. Table 5 summarizes the multiplexer configurations for Figure 33.
Table 5. Multiplexer Modes
MUX[2:0]
000
SWITCHES
S1, S5
DESCRIPTION
AINP1 and AINN1 connected to preamplifier
001
S2, S6
AINP2 and AINN2 connected to preamplifier
010
S3, S4
Preamplifier inputs shorted together through 400-Ω internal resistors
AINP1, AINN1 and AINP2, AINN2 connected together and to the preamplifier
External short, preamplifier inputs shorted to AINN2 (common-mode test)
011
S1, S5, S2, S6
S6, S7
100
The typical value of multiplexer on-resistance is 30 Ω (each switch). When the multiplexer is used to drive an
external load connected to one channel by a signal generator connected to the other channel, on-resistance and
on-resistance variation can lead to measurement errors. Figure 34 shows THD versus load resistance and
amplitude (PGA gain). In this configuration, THD performance improves when used with high-impedance loads
and low amplitude drive signals. The data are measured with the circuit from Figure 35 with the channel
connected to each other for measurement (MUX[2:0] = 011).
0
PGA = 1
PGA = 2
PGA = 4
PGA = 8
-20
-40
PGA = 16
PGA = 32
PGA = 64
-60
-80
-100
-120
-140
0.1k
1k
10k
100k
1M
10M
RLOAD (W)
Figure 34. THD vs External Load and Signal Magnitude (PGA); See Figure 35
500 Ω
Input 1
Test Signal
500 W
Input 2
RLOAD
Figure 35. Driving an External Load Through the Multiplexer
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8.3.2 Programmable Gain Amplifier (PGA)
The PGA of the ADS1284 is a low-noise, continuous-time, differential-in and differential-out CMOS amplifier. The
gain is set by register bits PGA[2:0], programmable from 1 to 64. The PGA differentially drives the modulator of
the ADC through 300-Ω internal resistors. The effect of the internal resistors and the modulator input impedance
results in gain error that changes with operating mode (see Electrical Characteristics). A PGA output filter
capacitor (10-nF C0G or film dielectric) must be connected to CAPP and CAPN in order to filter modulator
sampling glitches. The external capacitor also serves as the antialias filter. The corner frequency of the filter is
given in Equation 3:
1
fP =
6.3 ´ 600 ´ C
(3)
The PGA incorporates chopper stabilization. As shown in Figure 36, amplifiers A1 and A2 are chopper stabilized
to remove the offset, offset drift, and 1/f noise. Chopper stabilization (or chopping) moves the offset and noise to
fCLK / 1024 (4 kHz, fCLK = 4.096 MHz ), which is located safely out of the pass-band frequency range. Chopping
can be disabled by setting the CHOP bit = 0. When chopping is disabled, the PGA input impedance increases
(see Differential Input Impedance parameter in the Electrical Characteristics). As shown in Figure 37, chopper
stabilization provides flat noise density, leaving the noise spectrum white. However, if chopper stabilization is
disabled, the PGA input noise results in a rising 1/f noise profile. The effect of 1/f noise to the conversion data is
most noticeable at high PGA gain setting.
AVDD
MUX (+)
300W
A1
CAPP
CHOP
Gain Control
10nF
PGA[2:0] Bits
(55kW, typ
Modulator
Effective
Impedance
)
CAPN
300W
A2
MUX (-)
Chopping Control CHOP Bit
AVSS
(1) Modulator impedance depends on operating mode. High-resolution mode modulator impedance is 55 kΩ. Low-power
mode modulator impedance is 110 kΩ.
Figure 36. PGA Block Diagram
100
PGA CHOP Off
10
PGA CHOP On
1
1
10
100
Frequency (Hz)
1k
Figure 37. PGA Noise (High-resolution Mode)
20
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As a result of charges stored on stray capacitance of the input chopping switches, low-level transient currents
flow through the inputs when chopper stabilization is enabled. The average value of the transient currents results
in an effective input impedance. The effective input impedance depends on the PGA gain, as shown in Table 6.
Despite the relatively high input impedance, evaluate applications that use high-impedance sensors or high-
impedance termination resistors. In some cases, ADC performance may be improved by disabling chopper
stabilization.Table 6 shows the PGA differential input impedance with chopper stabilization enabled.
Table 6. Differential Input Impedance (CHOP Enabled)
PGA
1
DIFFERENTIAL INPUT IMPEDANCE (GΩ)
7
7
2
4
4
8
3
16
32
64
2
1
0.5
The PGA provides programmable gains from 1 to 64. Table 7 shows the register bit setting for the PGA and
resulting full-scale differential range.
Table 7. PGA Gain Settings
DIFFERENTIAL INPUT RANGE
PGA[2:0]
000
GAIN
1
(V)(1)
±2.5
001
2
±1.25
010
4
±0.625
±0.312
±0.156
±0.078
±0.039
011
8
100
16
32
64
101
110
(1) VREF = 5 V. The input range scales with VREF
.
The specified range of the PGA output is shown in Equation 4:
AVSS + 0.4V < (CAPN or CAPP) < AVDD - 0.4V
(4)
For best performance, maintain PGA output levels (signal plus common mode voltage) within these limits.
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8.3.3 Analog-to-Digital Converter (ADC)
The ADC of the ADS1284 consists of two sections to yield the conversion data result: a low-noise modulator and
a programmable digital filter.
8.3.3.1 Modulator
The low-noise modulator is an inherently-stable, fourth-order, ΔΣ, 2 + 2 pipelined structure, as Figure 38 shows.
The modulator shifts the quantization noise to a higher frequency (out of the passband), where the noise is
removed by the digital filter. The modulator data can either be completely filtered by the on-chip digital filter or
partially filtered by use of the sinc filter section alone. Partial filtering provided by the sinc filter section is intended
for use with an external FIR filter.
fCLK/4
fMOD =
1st-Stage
(2nd-Order ûꢀ)
Analog
Signal
Digital
Filter
Math
Block
2nd-Stage
(2nd-Order
ûꢀ)
Figure 38. ADS1284 Fourth-Order Modulator
Modulator performance is optimized for input signal frequencies over the range dc to 2 kHz. As Figure 39 shows,
the effect of PGA and modulator chop result in spectral artifacts occurring at the chop frequency (4 kHz) and
harmonics related of the chop frequency. When using the sinc filter output in conjunction with an external post-
decimation filter, design the external filter to suppress the modulator chopping artifacts.
0
œ20
œ40
œ60
œ80
œ100
œ120
œ140
œ160
œ180
0
4000 8000 12000 16000 20000 24000 28000 32000
Frequency (Hz)
C001
Figure 39. Sinc Output FFT (64 kSPS)
8.3.3.1.1 Modulator Overrange
The modulator is inherently stable, and therefore, has predictable recovery behavior resulting from an input
overdrive condition. The modulator does not exhibit self-reset cycles, which often results in an unstable output
data stream. The ADS1284 modulator outputs a data stream with 90% duty cycle of ones-to-zeroes density with
the positive full-scale input signal applied (10% duty cycle with the negative full-scale signal). If the input is
overdriven to exceed 10% or 90% modulation, but not saturated, the modulator remains stable and continues to
output the 1s density data stream. The digital filter may or may not clip the output codes to +FS or –FS,
depending on the duration of the overdrive. When the input returns to the normal range from a long-duration
overdrive (worst case), the modulator returns immediately to the normal range, but the group delay of the digital
filter delays the return of the conversion data to within the linear range (31 readings for linear phase FIR). An
additional 31 readings (62 total) are required for completely settled data.
22
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If the inputs are overdriven sufficiently to drive the modulator to full duty cycle (that is, all 1s or all 0s), the
modulator is saturated. The digital output code may clip to +FS or –FS, again depending on the duration of the
overdrive. A small-duration overdrive may not always clip the output code. When the input returns to the normal
range, the modulator requires up to 12 modulator clock cycles (fMOD) to exit saturation and return to linear
operation. The digital filter requires an additional 62 conversions for fully-settled data (linear-phase FIR).
In the extreme case of input overrange (where either overdriven input exceeds the voltage of the analog supply
voltage plus the input protection diode drop), the protection diodes begin to conduct, thus clipping the input
signal. When the input overdrive is removed, the diodes recover quickly. Make sure to limit the input current to 10
mA (continuous duty) if an overvoltage input signals are possible.
8.3.3.1.2 Modulator Input Impedance
The modulator samples the buffered input voltage through an internal capacitor to perform the ADC conversion.
The charging of the input sampling capacitor draws a transient current from the PGA output. Use the average
value of the current to calculate an effective input impedance, as shown in Equation 5:
REFF = 1 / (fMOD × CS)
where
•
•
fMOD = Modulator sample frequency = CLK / 4 ( CLK / 8 for low-power mode)
CS = Input sampling capacitor = 17 pF (typ)
(5)
The resulting modulator input impedance is 55 kΩ (110 kΩ low-power mode). The modulator input impedance
and the PGA output resistors result in systematic gain errors. The modulator sampling capacitor and PGA output
resistors can each vary up to ±20% over production lots, affecting the nominal gain error.
8.3.3.1.3 Modulator Overrange Detection (MFLAG)
The ADS1284 has a fast-responding, overrange detection that indicates when the differential input exceeds
100% or –100% full-scale. The threshold tolerance is ±2.5%.The MFLAG output pin asserts high when in an
overrange condition. As Figure 40 and Figure 41 illustrate, the absolute differential input is compared to 100% of
range. The output of the comparator is sampled at the rate of fMOD / 2, yielding the MFLAG output. The minimum
detectable MFLAG pulse duration is fMOD / 2.
AINP
å
IABSI
P
100% FS
AINN
Q
MFLAG
Pin
fMOD/2
Figure 40. Modulator Overrange Block Diagram
+100
(AINP - AINN)
0
Time
-100
MFLAG
Pin
Figure 41. Modulator Overrange Flag Operation
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8.3.3.1.4 Offset
The modulator can produce low-level idle tones that appear in the conversion data when there is no signal input
or when low-level signal inputs are present to the ADC. The ADC provides an optional dc offset voltage designed
to shift the idle tones to the stop band of digital filter response, where the idle tones are reduced. The internal
offset is applied at the modulator input; therefore, the offset voltage is independent of PGA gain. Two offset
voltage options are provided, 75 mV and 100 mV. The 75-mV offset is more effective to reduce idle tones under
various gain, data rate, and chop mode settings.
The offset is enabled by the OFFSET1 and OFFSET0 bits (default is off). The offset voltage reduces the total
available input range 4% (3% for the 75 mV value) before the onset of clipped conversion results. To restore the
full range of the ADC, calibrate the offset voltage by the digital offset calibration register (OFC[2:0]). See Offset
and Full-Scale Calibration Registers and Calibration Commands (OFSCAL and GANCAL) sections for details.
8.3.3.1.5 Voltage Reference Inputs (VREFP, VREFN)
The voltage reference of the ADS1284 is the differential voltage applied between pins VREFP and VREFN:
VREF = VREFP – VREFN
(6)
The reference inputs use a structure similar to that of the analog inputs with the circuitry of the reference inputs
shown in Figure 42. The average load presented by the switched-capacitor reference input can be modeled with
an effective differential impedance of:
REFF = tSAMPLE / CIN (tSAMPLE = 1 / fMOD).
(7)
Note that the effective impedance of the reference inputs loads the external reference.
AVDD
fMOD = fCLK/4
ESD
Diodes
1
REFF
=
f
MOD x 11.5 pF
VREFP
VREFN
REFF : 85 kΩ
11.5pF
ESD
Diodes
AVSS
REFF shown for high-resolution mode operation. REFF for low-power mode operation is 170 kΩ
Figure 42. Simplified Reference Input Circuit
Place a 0.1-µF ceramic capacitor directly between the ADC VREFP and VREFN pins. Multiple ADC applications
can share a single voltage reference, but must have individual capacitors placed at each ADC.
The ADS1284 reference inputs are protected by ESD diodes. In order to prevent these diodes from turning on,
the voltage on either input must stay within the range shown in Equation 8:
AVSS - 300mV < (VREFP or VREFN) < AVDD + 300mV
(8)
The minimum operational input range for VREFN is AVSS – 0.1 V, and the maximum operational range for
VREFP is AVDD + 0.1 V.
To achieve the best ADC performance, use a low-noise 5-V voltage reference. A 4.096-V or 4.5-V reference
voltage can be used; however, these lower reference voltages reduce the signal input range and corresponding
decrease SNR. Noise and drift on the reference degrade overall system performance. To achieve optimum
performance, give attention to the circuitry providing the reference voltage including possible use of noise
filtering. See the Application Information section for reference recommendations.
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8.3.3.2 Digital Filter
The digital filter receives the modulator output data stream and decimates and filters the data. By adjusting the
amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter
less for higher data rate.
The digital filter is comprised of three filter sections: a variable-decimation, fifth-order sinc filter; a fixed-
decimation FIR, low-pass filter (LPF) with selectable phase; and a programmable, first-order, high-pass filter
(HPF), as shown in Figure 43.
Filter Mode
(Register Select)
Filter
MUX
To Output Register
Sinc Filter
(Decimate by
8 to 128)
Coefficient Filter
(FIR)
(Decimate by 32)
High-Pass Filter
(IIR)
Code
Clip
CAL
Block
From Modulator
Figure 43. Digital Filter and Output Code Processing
The output can be taken from one of the three filter sections, as Figure 43 shows. For partial filtering of the
conversion data, select the sinc filter mode. The sinc filter mode is intended for use in conjunction with an
external FIR filter. For complete on-chip filtering, select the sinc + FIR mode. With sinc + FIR filter mode active,
the HPF can be included to remove dc and low frequencies from the data. Table 8 shows the filter mode options.
Table 8. Digital Filter Selection
FILTR[1:0] BITS
DIGITAL FILTER MODE
Reserved (not used)
Sinc
00
01
10
11
Sinc + FIR
Sinc + FIR + HPF
8.3.3.2.1 Sinc Filter Section (sinx / x)
The sinc filter is a variable decimation rate, fifth-order, low-pass filter. Data are supplied to this section of the filter
from the modulator at the rate of fMOD = fCLK / 4 (high-resolution mode) or fMOD = fCLK / 8 (low-power mode). The
sinc filter attenuates high-frequency noise produced by the modulator and also reduces the data rate (decimation
ratio) in proportion to the amount of filtering. The decimation ratio of the sinc filter effects the overall data rate of
the converter. The sinc and sinc + FIR filter mode data rates are programmed by the DR[2:0] register bits. The
sinc filter mode data rates are shown in Table 9.
Table 9. Sinc Filter Mode Data Rates
DECIMATION RATIO (N)
DR[2:0] REGISTER
HIGH-RESOLUTION MODE
LOW-POWER MODE
DATA RATE (SPS)
8,000
000
001
010
011
100
128
64
32
16
8
64
32
16
8
16,000
32,000
64,000
4
128,000
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Equation 9 shows the scaled Z-domain transfer function of the sinc filter.
5
-N
1 - Z
-1
N(1 - Z )
H(Z) =
where
•
N = decimation ratio
(9)
Equation 10 shows the frequency domain transfer function of the sinc filter.
5
pN ´ f
sin
fMOD
½H(f)½ =
p ´ f
N sin
fMOD
where
•
•
N = decimation ratio (see Table 9)
fMOD = fCLK /4 (high-resolution mode) or fCLK / 8 (low-power mode)
(10)
The sinc filter has notches (or zeros) that occur at the output data rate and multiples thereof. At these
frequencies, the filter has zero gain. Figure 44 shows the frequency response of the sinc filter and Figure 45
shows the roll-off of the sinc filter.
0
-20
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-40
-60
-80
-100
-120
-140
0
1
2
3
4
5
0
0.05
0.10
0.15
0.20
Normalized Frequency (fIN/fDATA
)
Normalized Frequency (fIN/fDATA
)
Figure 44. Sinc Filter Frequency Response
Figure 45. Sinc Filter Roll-Off
8.3.3.2.2 FIR Section
The second section of the digital filter is an FIR low-pass filter. Data are supplied to this section from the sinc
filter. The FIR stage is segmented into four subsections, as shown in Figure 46.
FIR Stage 1
Decimate by 2
FIR Stage 2
Decimate by 2
FIR Stage 3
Decimate by 4
FIR Stage 4
Decimate by 2
Sinc
Filter
Output
Coefficients
Linear
Minimum
PHASE Select
Figure 46. FIR Filter
26
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The first two subsections are half-band filters with fixed decimation ratios of two. The third subsection of the FIR
filter decimates by four (fixed), and the fourth subsection decimates by two (fixed). The overall decimation ratio of
the entire FIR section is 32. Two coefficient sets are used for the third and fourth subsections, sets for linear
phase mode and minimum phase mode (programmable). Table 10 lists the data rate programming and overall
decimation ratio of the FIR stage. See Table 11 for the FIR filter coefficients.
Table 10. FIR Filter Data Rates
OVERALL DECIMATION RATIO (COMBINED SINC + FIR)
DR[2:0]
REGISTER
000
HIGH-RESOLUTION MODE
LOW-POWER MODE
FIR DATA RATE (SPS)
4096
2048
1024
512
2048
1024
512
250
500
001
010
1000
2000
4000
011
256
100
256
128
Table 11. FIR Stage Coefficients
SECTION 1
SECTION 2
SECTION 3
SECTION 4
SCALING = 1 / 134217728
SCALING = 1 / 134217728
LINEAR PHASE
SCALING =
1 / 512
LINEAR PHASE
SCALING =
1 / 8388608
LINEAR
PHASE
MINIMUM
PHASE
LINEAR
PHASE
MINIMUM
PHASE
COEFFICIENT
b0
b1
3
0
–10944
0
0
819
–132
–432
11767
133882
0
8211
b2
–25
0
103807
0
–73
44880
–75
769961
b3
–874
174712
2481
2940447
8262605
17902757
30428735
40215494
39260213
23325925
–1757787
–21028126
–21293602
–3886901
14396783
16314388
1518875
–12979500
–11506007
2769794
12195551
6103823
–6709466
–9882714
–353347
8629331
5597927
–4389168
–7594158
–428064
b4
150
256
150
0
–507903
0
–4648
536821
6692
b5
–16147
–41280
–80934
–120064
–118690
–18203
224751
580196
893263
891396
293598
–987253
–2635779
–3860322
–3572512
–822573
4669054
12153698
19911100
25779390
27966862
25779390
19911100
12153698
4669054
1372637
3012996
5788605
9852286
14957445
20301435
24569234
26260385
24247577
18356231
9668991
327749
7419
b6
2512192
4194304
2512192
0
–266
b7
–10663
–8280
10620
22008
348
b8
–25
0
b9
b10
b11
b12
b13
b14
b15
b16
b17
b18
b19
b20
b21
b22
b23
b24
b25
b26
b27
b28
b29
3
–507903
0
103807
0
–34123
–25549
33460
61387
–7546
–94192
–50629
101135
134826
–56626
–220104
–56082
263758
231231
–215231
–430178
34715
580424
–10944
–7171917
–10926627
–10379094
–6505618
–1333678
2972773
5006366
4566808
2505652
126331
–1496514
–1933830
–1410695
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Table 11. FIR Stage Coefficients (continued)
SECTION 1
SECTION 2
SECTION 3
SECTION 4
SCALING = 1 / 134217728
SCALING = 1 / 134217728
LINEAR PHASE
SCALING =
1 / 512
LINEAR PHASE
SCALING =
1 / 8388608
LINEAR
PHASE
MINIMUM
PHASE
LINEAR
PHASE
MINIMUM
PHASE
COEFFICIENT
b30
b31
b32
b33
b34
b35
b36
b37
b38
b39
b40
b41
b42
b43
b44
b45
b46
b47
b48
b49
b50
b51
b52
b53
b54
b55
b56
b57
b58
b59
b60
b61
b62
b63
b64
b65
b66
b67
b68
b69
b70
b71
b72
b73
b74
–822573
–3572512
–3860322
–2635779
–987253
293598
891396
893263
580196
224751
–18203
–118690
–120064
–80934
–41280
–16147
–4648
–502731
245330
565174
492084
231656
–9196
–125456
–122207
–61813
–4445
22484
22245
10775
940
283878
–588382
–693209
366118
6566217
4024593
–3679749
–5572954
332589
1084786
132893
5136333
2351253
–3357202
–3767666
1087392
3847821
919792
–1300087
–878642
1162189
1741565
–522533
–2490395
–688945
2811738
2425494
–2338095
–4511116
641555
–2918303
–2193542
1493873
2595051
–79991
–2953
–2599
–1052
–43
–874
–2260106
–963855
1482337
1480417
–586408
–1497356
–168417
1166800
644405
–73
214
6661730
2950811
–8538057
–10537298
9818477
41426374
56835776
41426374
9818477
–10537298
–8538057
2950811
6661730
641555
0
132
0
33
0
0
–675082
–806095
211391
740896
141976
–527673
–327618
278227
–4511116
–2338095
2425494
2811738
–688945
–2490395
–522533
1741565
1162189
–878642
–1300087
132893
363809
–70646
–304819
–63159
205798
124363
–107173
–131357
31104
107182
1084786
15644
28
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Table 11. FIR Stage Coefficients (continued)
SECTION 1
SECTION 2
SECTION 3
SECTION 4
SCALING = 1 / 134217728
SCALING = 1 / 134217728
LINEAR PHASE
SCALING =
1 / 512
LINEAR PHASE
SCALING =
1 / 8388608
LINEAR
PHASE
MINIMUM
PHASE
LINEAR
PHASE
MINIMUM
PHASE
COEFFICIENT
b75
366118
–693209
–588382
283878
580424
34715
–430178
–215231
231231
263758
–56082
–220104
–56626
134826
101135
–50629
–94192
–7546
61387
33460
–25549
–34123
348
–71728
–36319
38331
38783
–13557
–31453
–1230
20983
7729
–11463
–8791
4659
7126
–732
–4687
–976
2551
1339
–1103
–1085
314
b76
b77
b78
b79
b80
b81
b82
b83
b84
b85
b86
b87
b88
b89
b90
b91
b92
b93
b94
b95
b96
681
b97
16
b98
22008
10620
–8280
–10663
–266
–349
–96
b99
b100
b101
b102
b103
b104
b105
b106
b107
b108
b109
144
78
–46
7419
–42
6692
9
2481
16
–75
0
–432
–4
–132
0
0
0
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As shown in Figure 47, the frequency response of the FIR filter is minimum ripple, flat to 0.375 of the data rate
(±0.003 dB pass-band ripple until 0.375 · fDATA) and is fully attenuated at the Nyquist frequency. Figure 48 shows
the transition from pass band to stop band.
2.0
1.5
20
0
-20
1.0
-40
0.5
-60
0
-80
-0.5
-1.0
-1.5
-2.0
-100
-120
-140
-160
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
Normalized Input Frequency (fIN/fDATA
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Normalized Input Frequency (fIN/fDATA
)
)
Figure 48. FIR Transition Band Magnitude Response
Figure 47. FIR Pass-Band Magnitude Response
Although not shown in Figure 48, the pass-band response repeats at multiples of the modulator frequency (N ·
fMOD – f0 and N · fMOD + f0, where N = 1, 2, and so on, and f0 = pass band). These image frequencies, if present
in the signal and not filtered before the analog-to-digital conversion process, fold back (or alias) into the pass
band and cause errors. A low-pass signal filter reduces the amplitude of the aliasing frequencies. Often, the RC
low-pass filter provided by the PGA output resistance and the external capacitor connected to CAPP and CAPN
provide sufficient anti-alias attenuation.
8.3.3.2.3 Group Delay and Step Response
The FIR block is implemented as a multistage FIR structure with selectable linear or minimum phase response.
The pass band, transition band, and stop band responses of the filters are nearly identical but differ in the
respective phase responses.
8.3.3.2.3.1 Linear Phase Response
Linear phase filters exhibit constant delay time versus input frequency (that is, constant group delay). Linear
phase filters have the property that the time delay is constant from any instant of the input signal to the same
instant of the output data, and is independent of the signal frequency. This filter behavior results in essentially
zero phase error when analyzing multi-tone signals. However, the group delay is longer than the minimum phase
filter, as shown in Figure 49.
1.4
Minimum Phase Filter
1.2
1.0
0.8
0.6
0.4
0.2
Linear Phase Filter
0
-0.2
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Time Index (1/fDATA
)
Figure 49. FIR Step Response
30
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8.3.3.2.3.2 Minimum Phase Response
The minimum phase filter provides a short delay from the arrival of an input signal to the output of conversion
data, but the phase relationship is not constant versus frequency, as shown in Figure 50. The filter phase is
selected by the PHS bit, as Table 12 shows.
35
Linear Phase Filter
30
25
20
15
10
Minimum Phase Filter
5
0
20
40
60
80 100 120 140 160 180 200
Frequency (Hz)
Figure 50. FIR Group Delay (fDATA = 500Hz)
Table 12. FIR Filter Phase Selection
PHS BIT
FILTER PHASE
Linear
0
1
Minimum
8.3.3.2.4 HPF Section
The last section of the digital filter is a first-order HPF implemented as an IIR structure. This filter stage blocks dc
signals, and rolls-off low frequency components below the cutoff frequency. The transfer function for the filter is
shown in Equation 11:
2 - a
-1
1 - Z
HPF(Z) =
´
-1
2
1 - bZ
where
•
b is calculated as shown in Equation 12
(11)
(12)
1 + (1 - a)2
b =
2
The high-pass corner frequency is programmed by registers HPF[1:0], in hexadecimal. Equation 13 is used to set
the high-pass corner frequency. Table 13 lists example values for the high-pass filter.
cos wN + sin wN - 1
HPF[1:0] = 65,536 1 -
1 - 2
cos wN
where
•
•
•
•
HPF[1:0] = High-pass filter register value (converted to hexadecimal)
ωN = 2πfHP / fDATA (normalized frequency, radians)
fHP = High-pass corner frequency (Hz)
fDATA = Data rate (Hz)
(13)
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Table 13. High-Pass Filter Value Examples
fHP (Hz)
0.5
DATA RATE (SPS)
HPF[1:0]
0337h
250
500
1.0
0337h
1.0
1000
019Ah
The HPF causes a small gain error, in which case the magnitude of the error depends on the ratio of fHP / fDATA
.
For many common values of (fHP / fDATA), the gain error is negligible. Figure 51 shows the gain error of the HPF.
0
-0.10
-0.20
-0.30
-0.40
-0.50
0.0001
0.001
0.01
0.1
Frequency Ratio (fHP/fDATA
)
Figure 51. HPF Gain Error
The gain error factor is calculated in Equation 14:
cos wN + sin wN - 1
1 +
1 - 2
cos wN
HPF Gain =
cos wN + sin wN - 1
cos wN
2 -
(14)
Figure 52 shows the first-order amplitude and phase response of the HPF. In the case of applying step inputs
(changing gains or inputs) or synchronizing, make sure to take the settling time of the filter into account.
0
90
75
60
45
30
-7.5
-15.0
-22.5
-30.0
-37.5
-45.0
Amplitude
Phase
15
0
0.01
0.1
1
10
100
Normalized Frequency (f/fC)
Figure 52. HPF Amplitude and Phase Response
32
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8.4 Device Functional Modes
8.4.1 Synchronization (SYNC PIN and SYNC Command)
The ADS1284 can be synchronized to an external event, as well as synchronizing multiple ADS1284 devices
together if the synchronization pulse is applied simultaneously.
The ADS1284 has two methods of synchronization: the SYNC input pin and the SYNC command. In addition,
there are two synchronization modes: pulse-sync and continuous-sync. In pulse-sync mode, the ADS1284
synchronizes unconditionally at each synchronization event. In continuous-sync mode, the first synchronization is
unconditional, thereafter the ADC re-synchronizes only when the next SYNC pin edge does not occur at an
integer multiple of the data rate. Typically, a synchronization clock is applied to the SYNC pin with a period equal
to an integer multiple of the data rate. When the periods of the SYNC input and the DRDY output do not match
due to system glitch or clock noise event, the ADC re-synchronizes.
8.4.1.1 Pulse-Sync Mode
In pulse-sync mode, the ADS1284 unconditionally synchronizes by stopping and restarting the conversion
process. Synchronization is possible by pin or command in this mode. At synchronization, the device resets the
internal filter memory, DRDY goes high, and after the digital filter has settled, new conversion data are available
as shown in Figure 53 and Table 14 (Pulse-sync mode).
tCSDL
CLK
tDR
SYNC
tSPWH
tSPWL
New Data Ready
DRDY
(Pulse-sync mode)
DOUT
(Pulse-sync mode)
New Data Ready
DRDY
(Continuous-sync mode)
DOUT
(Continuous-sync mode)
Figure 53. Pulse-Sync and Continuous-Sync Timing With Single Synchronization
Table 14. Pulse-Sync Timing for Figure 53 and Figure 54
PARAMETER
CLK rising edge to SYNC rising edge(1)
SYNC clock period(2)
MIN
30
1
MAX
–30
UNIT
ns
tCSDL
tSYNC
Infinite
n / fDATA
1 / fCLK
tSPWH, L
SYNC pulse width, high or low
Time for data ready (SINC filter)
Time for data ready (FIR filter)
2
See Table 15
tDR
62.98046875 / fDATA + 468 / fCLK
(1) CLK rising edge to SYNC rising edge timing must not occur within the specified time window.
(2) Continuous-sync mode; a free-running clock applied to the SYNC input without causing resynchronization. See Figure 54
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Table 15. tDR Time for Data Ready (Sinc Filter)
fDATA (kSPS)
fCLK CYCLES(1)
128
64
32
16
8
440
616
968
1672
2824
(1) For SYNC and WAKEUP commands, number of fCLK cycles from next rising CLK edge directly after
eighth rising SCLK edge to DRDY falling edge. For WAKEUP command only, subtract two fCLK cycles.
Table 15 is referenced by Table 14 and Table 17.
Observe the timing restriction of SYNC rising edge to CLK rising edge as shown in Figure 53 and Table 14.
Synchronization occurs on the next rising CLK edge after the rising edge of the SYNC, or after the eighth rising
SCLK edge when synchronized by command. To synchronize multiple ADCs by the sync command, broadcast
the command to the ADCs simultaneously.
8.4.1.2 Continuous-Sync Mode
In continuous-sync mode, either a single synchronization pulse or a continuous synchronization clock may be
applied. Use the SYNC pin in this mode. When a single sync pulse is applied (rising edge), the device
resynchronizes the same way as pulse-sync mode. ADC re-synchronization occurs only when the time between
SYNC rising edges is not an integer multiple of the conversion period. When resynchronization occurs, DRDY
continues to toggle at the period of the date rate, and the DOUT output is held low until data are ready (63 DRDY
periods later). At the 63rd reading, conversion data are valid, as shown in Figure 53.
If an additional pulse is applied to the SYNC pin, the elapsed time from the previous pulse must be an integral
multiple of the output data rate otherwise re-synchronization results.
If a synchronization clock is applied to the SYNC pin, the device resynchronizes only under the condition tSYNC
≠
N / fDATA, where N = 1, 2, 3, and so on. When re-synchronized, DRDY continues to strobe, but the data on DOUT
is held low until new data are valid after filter reset. If the period of the synchronizing clock matches an integral
multiple of the data rate, the ADC does not re-synchronize. Note that the phase of the applied clock and output
data rate (DRDY) is not aligned because of the initial delay of DRDY after the SYNC clock is first applied.
Figure 54 shows the timing for continuous-sync mode.
tCSDL
CLK
tSPWH
SYNC
tSPWL
tSYNC
DRDY
1/fDATA
Figure 54. Continuous-Sync Timing With SYNC Clock
Apply the synchronization clock after the continuous-sync mode is programmed. The first rising edge of SYNC
then results in synchronization. Note that subsequent writes to any ADC register results in re-synchronization at
the time of the register write operation. The re-synchronization leads to loss of the previous synchronization.
Send the STANDBY command followed by the WAKEUP command to re-establish the previous synchronization.
Re-synchronization occurs is valid as long as the time between the STANDBY and WAKEUP commands is not a
multiple integer of the conversion period by at least one clock cycle.
34
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8.4.2 Reset (RESET Pin and Reset Command)
Reset the ADC in three ways: cycle the power supplies, toggle the RESET pin low, or send a RESET command.
When using the RESET pin, take it low and hold for at least 2 / fCLK to force a reset. The ADS1284 is held in
reset until the pin is released. By reset command, reset takes effect on the next rising edge of fCLK after the
eighth rising edge of SCLK of the command. In order to make certain that the RESET command functions, the
SPI interface may need to be reset; see the Serial Interface section.
When the ADS1284 is reset, registers are set to default and the conversions are synchronized on the next rising
edge of CLK. New conversion data are available, as shown in Figure 55 and Table 16.
Settled
Data
DRDY
tDR
tCRHD
System Clock
(fCLK)
tRCSU
tRST
RESET Pin
or
RESET Command
Figure 55. Reset Timing
Table 16. Reset Timing for Figure 55
PARAMETER
MIN
UNIT
ns
tCRHD
tRCSU
tRST
CLK to RESET hold time
RESET to CLK setup time
RESET low
10
10
ns
2
1 / fCLK
s
tDR
Time for data ready
62.98046875 / fDATA + 468 / fCLK
8.4.3 Master Clock Input (CLK)
The ADS1284 requires a clock for operation. The specified clock frequency is 4.096 MHz and is applied to the
CLK pin. The ADC data rates scale with clock frequency, however there is no benefit in noise reduction by
reducing clock frequency; select a slower data to reduce noise.
As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance.
Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock
input; keep the clock trace as short as possible and use a 50-Ω series resistor close to the clock source.
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8.4.4 Power-Down (PWDN Pin and STANDBY Command)
Power-down the ADS1284 in two ways: take the PWDN pin low, or send a STANDBY command. When the
PWDN pin is pulled low, the internal circuitry is disabled to minimize power and the contents of the register
settings are reset.
When in the power-down state, the device outputs remain active and the device inputs must not float. When the
STANDBY command is sent, the SPI port and the configuration registers are kept active. Figure 56 and Table 17
show the timing. Standby mode is cancelled when CS is taken high.
PWDN Pin
Wakeup
Command
DRDY
tDR
Figure 56. PWDN Pin and Wake-Up Command Timing
(Table 17 shows tDR
)
Table 17. Power-On, PWDN Pin, and Wake-Up Command Timing for New Data
PARAMETER
FILTER MODE
See Table 15
SINC(1)
Time for data ready 216 CLK cycles after power-on;
and new data ready after PWDN pin or WAKEUP command
tDR
62.98046875 / fDATA + 468 / fCLK
FIR
(2)
(1) Supply power-on and PWDN pin default is 1000 SPS FIR.
(2) Subtract two CLK cycles for the WAKEUP command. The WAKEUP command is timed from the next rising edge of CLK to after the
eighth rising edge of SCLK during command to DRDY falling.
8.4.5 Power-On Sequence
The ADS1284 has three power supplies: AVDD, AVSS, and DVDD. Figure 57 shows the power-on sequence of
the ADS1284. The power supplies can be sequenced in any order. The supplies [the difference of AVDD –
AVSS, and DVDD] generate signals that are ANDed together to generate reset. After the supplies have crossed
the power-on reset thresholds, 216 fCLK cycles are counted before releasing the internal reset. After the internal
reset is released, new conversion data are available, as shown in Figure 57 and Table 17.
3.5V nom
AVDD - AVSS
1V nom
DVDD
CLK
16
2
fCLK
Internal Reset
DRDY
tDR
Figure 57. Power-On Sequence
36
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8.4.6 DVDD Power Supply
The DVDD supply operates over the range of 1.65 V to 3.6 V. If operating DVDD at less than 2.25 V, connect the
DVDD pin directly to the BYPAS pin. Figure 58 shows the required connection if DVDD < 2.25 V. Otherwise if
operating DVDD > 2.25 V, do not connect the pins together.
1.65 V to 3.6 V
DVDD
1 µF
Connect DVDD to BYPAS if DVDD is < 2.25 V.
Otherwise, do not connect these pins together.
BYPAS
1 µF
Figure 58. DVDD Power
8.4.7 Serial Interface
A serial interface is used to read both the conversion data and to access the configuration registers. The
interface is SPI-compatible and consists of four signals: CS, SCLK, DIN, and DOUT. Up to 15 ADCs converting
at 4 kSPS can share a common serial bus when operating SCLK at 2.048 MHz.
8.4.7.1 Chip Select (CS)
Chip select (CS) is an active-low input that enables the ADC serial interface for data transfer. CS low enables
communication. CS high disables communication. When communication is disabled, DOUT (output data pin) is
high impedance (tristate mode). Additionally, SCLK activity is ignored, and data transfers or commands in
progress are reset. CS must remain low for the duration of the data transfer with the ADC. CS can be tied low,
which permanently enables the ADC serial interface. When CS goes high, the ADC idle mode (STANDBY) and
stop read data continuous (SDATAC) modes are cancelled. See the SDATAC Requirements section for more
information about SDATAC mode.
8.4.7.2 Serial Clock (SCLK)
The serial clock (SCLK) is a digital input that is used to clock data into (DIN) and out of (DOUT) the ADC. SCLK
is a Schmitt-trigger input that has a high degree of noise immunity. However, keep the SCLK signal as clean as
possible to prevent possible glitches from inadvertently shifting the data. Data are shifted into DIN on the rising
edge of SCLK and data are shifted out of DOUT on the falling edge of SCLK. Keep SCLK low when not active.
SCLK is ignored when CS is high.
8.4.7.3 Data Input (DIN)
The data input pin (DIN) is used to input register data and commands to the ADS1284. Keep DIN low when
reading conversion data in the read-data-continuous mode (except when issuing a SDATAC command). Data on
DIN are shifted into the converter on the rising edge of SCLK.
8.4.7.4 Data Output (DOUT)
The data output pin (DOUT) is used to output data from the ADS1284. Data are shifted out on the falling edge of
SCLK. When CS is high, the DOUT pin is in tristate.
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8.4.7.5 Serial Port Auto Timeout
The serial interface is reset each time CS is taken high. However, for applications that tie CS low, the serial port
cannot be reset by taking CS high. The ADS1284 provides a feature that automatically recovers the interface
when a transmission is stopped or interrupted, or if a noise glitch appears on SCLK. To reset the serial interface
remotely, hold SCLK low for 64 DRDY cycles. The reset of the serial interface results in termination of data
transfer or commands in progress. After serial interface reset occurs, the next SCLK pulse starts a new
communication cycle. To prevent remote reset of the interface, pulse SCLK at least once for every 64 DRDY
pulses.
8.4.7.6 Data Ready (DRDY)
DRDY is an output that is driven low when new conversion data are ready fir retrieval, as shown in Figure 59.
When reading data in continuous mode, the read operation must be completed before four CLK periods before
the next falling DRDY goes low again, or the data are overwritten with new conversion data. When reading data
in command mode, the read operation can overlap the occurrence of the next DRDY without data corruption.
DRDY
DOUT
SCLK
Bit 31
Bit 30
Bit 29
Figure 59. DRDY With Data Retrieval
DRDY resets high on the first falling edge of SCLK. Figure 59 and Figure 60 show the function of DRDY with and
without data readback, respectively.
If data are not retrieved (no SCLK provided), DRDY pulses high for four fCLK periods during the update time, as
shown in Figure 60.
DRDY remains active when CS is high.
Data Updating
4/fCLK
DRDY
Figure 60. DRDY With No Data Retrieval
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8.4.8 Data Format
The ADS1284 output data is 32-bits in binary twos complement format, as shown in Table 18. The LSB of the
data is a redundant sign bit: 0 for positive numbers and 1 for negative numbers. However, when the output is
clipped to +FS, the LSB = 1, and when the output is clipped to –FS, the LSB = 0. If desired, the data readback
can be stopped at 24 bits. Note that in sinc-filter mode, the output data are scaled by ½.
Table 18. Ideal Output Code Versus Input Signal
32-BIT IDEAL OUTPUT CODE(1)
INPUT SIGNAL VIN
(AINP – AINN)
FIR FILTER
SINC FILTER(2)
VREF
(3)
>
7FFFFFFFh
See note
2 x PGA
VREF
2 x PGA
7FFFFFFEh
3FFFFFFFh
VREF
2PGA ´ (230 - 1)
00000002h
00000000h
FFFFFFFFh
00000001h
00000000h
FFFFFFFFh
0
-VREF
2PGA ´ (230 - 1)
230
-VREF
´
80000001h
80000000h
C0000000h
230 - 1
2PGA
230
-VREF
(3)
<
´
See note
230 - 1
2PGA
(1) Excludes effects of noise, linearity, offset, and gain errors.
(2) Due to the reduction in oversampling ratio (OSR) related to high data rates, full 32-bit resolution is not be available in sinc filter mode.
(3) In sinc-filter mode, the output does not clip at corresponding positive or negative code when the full-scale range is exceeded.
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8.4.9 Reading Data
The ADS1284 provides two modes to read conversion data: read-data-continuous mode and read-data-by-
command mode.
8.4.9.1 Read-Data-Continuous Mode
In the read-data-continuous mode, conversion data are read from the ADC without need for the read command.
This mode is the default mode at power-on. This mode is also enabled by the RDATAC command. When DRDY
goes low, indicating that new data are available, the MSB of data is placed on DOUT, as shown in Figure 61.
The data are read (latched) by the user on the rising edges of SCLK. At the first falling edge of SCLK, DRDY
returns high. After 32 bits of data have been read, further SCLK transitions cause DOUT to go low. If desired, the
read operation may be stopped at 24 bits. The entire data shift operation must be completed within four CLK
periods before DRDY falls again or the data may be corrupted.
When a SDATAC command is issued, the DRDY output is blocked but the ADS1284 continues conversions. In
stop continuous mode, the data is read by command.
CS(1)
DRDY
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 25 26 27 28 29 30 31 32
SCLK
DOUT(2)
DIN
Data Byte 1 (MSB)
tDDPD
Data Byte 2 (MSB - 1)
Data Byte 4 (LSB)
(1) DOUT is in tristate when CS is high. CS can be tied low. See Figure 1 for CS low to valid DOUT propagation time.
Figure 61. Read Data Continuous
Table 19. Timing Data for Figure 61
PARAMETER
MIN
TYP
MAX
UNIT
tDDPD
DRDY to valid MSB on DOUT propagation delay(1)
100
ns
(1) DOUT is in tristate when CS is high. Load on DOUT = 20 pF || 100 kΩ.
8.4.9.2 Read-Data-By-Command Mode
Read-data-continuous mode is stopped by the SDATAC command and then places the ADC into read-data-by-
command mode. In read-data-by-command mode, an RDATA command is sent to the device in order to read
each new conversion data (as shown in Figure 62). When the read data command is received (on the eighth
SCLK rising edge), data are available to read only when DRDY subsequently goes low (tDR). When DRDY goes
low, conversion data appear on DOUT. The data may be read on the rising edge of SCLK.
CS(1)
DRDY
tDR
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 33 34 35 36 37 38 39 40
SCLK
DOUT(2)
DIN
Don't Care
Command Byte (0001 0010)
Data Byte 1 (MSB)
tDDPD
Date Byte 4 (LSB)
(1) DOUT is in tristate when CS is high.CS can be tied low. See Figure 1 for CS low to SCLK rising edge time.
Figure 62. Read Data By Command, RDATA (tDDPD timing is given in Table 19)
Table 20. Read Data Timing for Figure 62
PARAMETER
MIN
TYP
MAX
UNIT
tDR
Time for new data after data read command
0
1
fDATA
40
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8.4.10 One-Shot Operation
The ADS1284 can perform very power-efficient, one-shot conversions using the STANDBY command while
under software control. Figure 63 shows this sequence. First, issue the STANDBY command to set the standby
mode.
When ready to make a measurement, issue the WAKEUP command. When DRDY goes low, the fully-settled
conversion data are ready and can be read directly in read-data-continuous mode. Afterwards, issue another
STANDBY command. When ready for the next measurement, repeat the cycle starting with another WAKEUP
command.
ADC Status
Standby
Performing One-Shot Conversion
Standby
CS
DRDY
(1)
STANDBY
WAKEUP
DIN
STANDBY
DOUT
Settled
Data
See Figure 56 and Table 17 for time to new data.
Figure 63. One-Shot Conversions Using the STANDBY Command
8.4.11 Offset and Full-Scale Calibration Registers
The conversion data can be scaled for offset and gain before yielding the final output code. As shown in
Figure 64, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the
full-scale register (FSC). Equation 15 shows the scaling:
FSC[2:0]
Final Output Data = (Input - OFC[2:0]) ´
400000h
(15)
The values of the offset and full-scale registers are set by writing to them directly, or they are set automatically
by the calibration commands.
The offset and full-scale calibrations apply to specific PGA settings. When the PGA is changed, these registers
generally require recalculation. Calibration is bypassed in the sinc filter mode.
AINP
AINN
+
Output Data
Clipped to 32 Bits
Digital
Filter
´
Final Output
S
Modulator
-
OFC
Register
FSC Register
400000h
Figure 64. Calibration Block Diagram
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8.4.11.1 OFC[2:0] Registers
The 24-bit offset calibration word is composed of three 8-bit registers, as shown in Table 21. The offset register
is left-justified to align with the 32 bits of conversion data. The offset is in twos complement format with a
maximum positive value of 7FFFFFh and a maximum negative value of 800000h. This value is subtracted from
the conversion data. A register value of 00000h has no offset correction (default value).
Table 21. Offset Calibration Word
REGISTER
OFC0
BYTE
LSB
BIT ORDER
B7
B15
B6
B5
B4
B3
B2
B1
B9
B0 (LSB)
B8
OFC1
MID
B14
B22
B13
B21
B12
B20
B11
B19
B10
B18
OFC2
MSB
B23 (MSB)
B17
B16
Although the offset calibration register value can correct offsets ranging from –FS to +FS (as shown in Table 22),
in order to avoid input overload, do not exceed the maximum input voltage range of 106% FSR (including
calibration).
Table 22. Offset Calibration Values
OFC REGISTER
7FFFFFh
FINAL OUTPUT CODE(1)
80000000h
000001h
FFFFFF00h
000000h
00000000h
FFFFFFh
800000h
00000100h
7FFFFF00h
(1) Full 32-bit final output code with zero code input.
8.4.11.2 FSC[2:0] Registers
The full-scale calibration is a 24-bit word, composed of three 8-bit registers, as shown in Table 23. The full-scale
calibration value is 24-bit, straight offset binary, normalized to 1.0 at code 400000h.
Table 23. Full-Scale Calibration Word
REGISTER
FSC0
BYTE
LSB
BIT ORDER
B7
B15
B6
B5
B4
B3
B2
B1
B9
B0 (LSB)
B8
FSC1
MID
B14
B22
B13
B21
B12
B20
B11
B19
B10
B18
FSC2
MSB
B23 (MSB)
B17
B16
Table 24 summarizes the scaling of the full-scale register. A register value of 400000h (default value) has no
gain correction (gain = 1). Although the full-scale calibration register value corrects gain errors above one (gain
correction < 1), the full-scale range of the analog inputs must not exceed 106% FSR (including calibration) in
order to avoid input overload.
Table 24. Full-Scale Calibration Register Values
FSC REGISTER
800000h
GAIN CORRECTION
2.0
1.0
0.5
0
400000h
200000h
000000h
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8.4.12 Calibration Commands (OFSCAL and GANCAL)
Use the calibration commands (OFSCAL or GANCAL) to calibrate the conversion data. The values of the offset
and gain calibration registers are internally written to perform calibration. The appropriate input signals must be
applied to the ADS1284 inputs before sending the commands. Use slower data rates to achieve more consistent
calibration results; this effect is a byproduct of the lower noise that these data rates provide. Also, if calibrating at
power-on, be sure the reference voltage is fully settled.
Figure 65 shows the calibration command sequence. After the analog input voltage (and reference) have
stabilized, send the SDATAC command, followed by the SYNC and RDATAC commands. DRDY goes low after
64 data periods. After DRDY goes low, send the SDATAC command, then the calibrate command (OFSCAL or
GANCAL), followed by the RDATAC command. After 16 data periods, calibration is complete and conversion
data can be read at this time. The SYNC input must remain high during the calibration sequence.
VIN
Fully stable input and reference voltage.
OFSCAL or
Commands
SDATAC
SYNC
RDATAC
SDATAC
RDATAC
GANCAL
Calibration
Complete
16 Data
Periods
DRDY
SYNC
64 Data Periods
Figure 65. Offset and Gain Calibration Timing
The calibration commands apply to specific PGA settings. If the PGA is changed, recalibration is necessary.
Calibration is bypassed in the sinc filter mode.
8.4.12.1 OFSCAL Command
The OFSCAL command performs an offset calibration. Before sending the OFSCAL command sequence
(Figure 65), a zero input signal must be applied to the ADS1284 and the inputs allowed to stabilize. When the
command sequence (Figure 65) is sent, the ADS1284 averages 16 readings, and then writes this value to the
OFC register. The contents of the OFC register can be subsequently read or written. During offset calibration, the
full-scale correction is bypassed. Use the OFSCAL command to calibrate the optional 100-mV offset.
8.4.12.2 GANCAL Command
The GANCAL command performs a gain calibration. Before sending the GANCAL command sequence
(Figure 65), a dc input must be applied (typically full-scale input, but not to exceed 106% full-scale). After the
signal has stabilized, the command sequence can be sent. The ADS1284 averages 16 readings, then computes
a gain value that scales the applied calibration voltage to full-scale. The gain value is written to the FSC register,
where the contents are subsequently read or written.
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8.4.13 User Calibration
System calibration of the ADS1284 can be performed without using the calibration commands. This procedure
requires the calibration values to be externally calculated and then written to the calibration registers. The steps
for this procedure are:
1. Set the OFSCAL[2:0] register = 0h, and GANCAL[2:0] = 400000h. These values set the offset and gain
registers to 0 and 1, respectively.
2. Apply a zero differential input to the input of the system. Wait for the system to settle and then average the
output readings. Higher numbers of averaged readings result in more consistent calibration. Write the
averaged value to the OFC register.
3. Apply a differential dc signal, or an ac signal (typically full-scale, but do not exceed 106% FSR). Wait for the
system to settle and then average the output readings.
The value written to the FSC registers is calculated by Equation 16 or Equation 17.
DC-signal calibration is shown in Equation 16. The expected output code is based on 31-bit output data.
Expected Output Code
FSC[2:0] = 400000h ´
Actual Output Code
(16)
For ac-signal calibration, use an RMS value of collected data, as shown in Equation 17:
Expected RMS Value
FSC[2:0] = 400000h ´
Actual RMS Value
(17)
44
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8.5 Programming
8.5.1 Commands
The commands listed in Table 25 control the operation of the ADS1284. Most commands are stand-alone (that
is, one byte in length); the register read and write commands are two bytes long in addition to the actual register
data bytes.
Table 25. Command Descriptions
COMMAND
WAKEUP
STANDBY
SYNC
TYPE
Control
Control
Control
Control
Control
Control
Data
DESCRIPTION
Wake-up from standby mode
1st COMMAND BYTE(1)(2)
0000 000X (00h or 01h)
0000 001X (02h or 03h)
0000 010X (04h or 5h)
0000 011X (06h or 07h)
0001 0000 (10h)
2nd COMMAND BYTE(3)
Enter standby mode
Synchronize the analog-to-digital conversion
Reset registers to default values
Enter read data continuous mode
Stop read data continuous mode
Read data by command(4)
RESET
RDATAC
SDATAC
RDATA
0001 0001 (11h)
0001 0010 (12h)
RREG
Register
Register
Read nnnnn register(s) at address rrrrr(4)
001r rrrr (20h + 000r rrrr)
010r rrrr (40h + 000r rrrr)
0110 0000 (60h)
000n nnnn (00h + n nnnn)
000n nnnn (00h + n nnnn)
WREG
Write nnnnn register(s) at address rrrrr
OFSCAL
GANCAL
Calibration Offset calibration
Calibration Gain calibration
0110 0001 (61h)
(1) X = don't care.
(2) rrrrr = starting address for register read and write commands.
(3) nnnnn = number of registers to be read from or written to – 1. For example, to read from or write to three registers, set nnnnn = 2
(00010).
(4) Required to cancel read-data-continuous mode before sending a command.
CS must remain low for duration of the command-byte sequence. A delay of 24 fCLK cycles between commands
and between bytes within a command is required, starting from the last SCLK rising edge of one command to the
first SCLK rising edge of the following command. The required delay is shown in Figure 66.
CS
Command
Byte
Command
Byte
DIN
SCLK
(1)
(1)
tSCLKDLY
tSCLKDLY
(1) tSCLKDLY = 24 / fCLK (min).
Figure 66. Consecutive Commands
8.5.1.1 SDATAC Requirements
In read-data-continuous mode, the ADS1284 places conversion data on the DOUT pin as SCLK is applied. As a
result of the potential conflict between conversion data and register data placed on DOUT resulting from a RREG
or RDATA operation, it is necessary to send a stop-read-data-continuous (SDATAC) command before a RREG
or RDATA command. The SDATAC command disables the direct output of conversion data on the DOUT pin.
CS = 1 cancels SDATAC mode; therefore, keep CS held low after sending the SDATAC command to the next
RREG or RDATA command.
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8.5.1.2 WAKEUP: Wake-Up From Standby Mode
The WAKEUP command is used to exit the standby mode. After sending this command, the time for the first data
to be ready is illustrated in Figure 56 and Table 18. Sending this command during normal operation has no
effect; for example, reading data by the read-data-continuous mode with DIN held low.
8.5.1.3 STANDBY: Standby Mode
The STANDBY command places the ADS1284 into standby mode. In standby, the device enters a reduced
power state where a low quiescent current remains to keep the register settings and serial interface active. The
ADC remains in standby mode until CS is taken high or the WAKEUP command is sent. For complete device
shutdown, take the PWDN pin low (register settings are not saved). The operation of standby mode is shown in
Figure 67.
0000 001X
(STANDBY)
0000 000X
(WAKEUP)
DIN
SCLK
Operating
Standby Mode
Operating
Figure 67. STANDBY Command Sequence
8.5.1.4 SYNC: Synchronize the Analog-to-Digital Conversion
The SYNC command synchronizes the analog-to-digital conversion. Upon receiving the command, the reading in
progress is cancelled and the conversion process is restarted. In order to synchronize multiple ADS1284s, the
command must be sent simultaneously to all devices. The SYNC pin must be held high during this command.
8.5.1.5 RESET: Reset the Device
The RESET command resets the registers to default values, enables read-data-continuous mode, and restarts
the conversion process. The RESET command is functionally equivalent to taking the RESET pin low. See
Figure 55 for the RESET command timing.
8.5.1.6 RDATAC: Read Data Continuous
The RDATAC command enables read-data-continuous mode (default mode). In this mode, conversion data is
read from the device directly without the need to supply a data read command. Each time DRDY falls low, new
data are available to read. See the Read-Data-Continuous Mode section for more details.
8.5.1.7 SDATAC: Stop Read Data Continuous
The SDATAC command stops read-data-continuous mode. Exit read-data-continuous mode before sending
register and data read commands. The SDATAC command suppresses the DRDY output, but the ADS1284
continues conversions. Take CS high to cancel SDATAC mode.
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8.5.1.8 RDATA: Read Data by Command
The RDATA command reads the conversion data. See the Read-Data-By-Command Mode section for more
details.
8.5.1.9 RREG: Read Register Data
The RREG command is used to read single- or multiple-register data. The command consists of a two-byte
opcode argument, followed by the output of register data. The first byte of the opcode includes the starting
address, and the second byte specifies the number of registers to read minus one.
First command byte: 001r rrrr, where rrrrr is the starting address of the first register.
Second command byte: 000n nnnn, where nnnnn is the number of registers to read minus one.
Starting with the 16th falling edge of SCLK, the register data appear on DOUT. Read the data on the 17th SCLK
rising edge.
The RREG command is illustrated in Figure 68.
A delay of 24 fCLK cycles is required between each byte transaction.
CS(1)
tDLY
tDLY
tDLY
25 26
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24
SCLK
DIN
Command Byte 1
Command Byte 2
DOUT(2)
Don't Care
Register Data 5
Register Data 6
Example: Read six registers, starting at register 05h (OFC0)
Command Byte 1 = 0010 0101
Command Byte 2 = 0000 0101
(1) DOUT is in tristate when CS is high. CS can be tied low. See Figure 1 for CS low to SCLK rising edge time.
Figure 68. Read Register Data (Table 26 shows tDLY
)
Table 26. tDRY Value
PARAMETER
MIN
tDLY
24 / fCLK
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8.5.1.10 WREG: Write to Register
The WREG command writes single- or multiple-register data. The command consists of a two-byte op-code
argument followed by the input of register data. The first byte of the op-code contains the starting address and
the second byte specifies the number of registers to write minus one.
First command byte: 010r rrrr, where rrrrr is the starting address of the first register.
Second command byte: 000n nnnn, where nnnnn is the number of registers to write minus one.
Data byte(s): one or more register data bytes, depending on the number of registers specified.
Figure 69 illustrates the WREG command.
A delay of 24 fCLK cycles is required between each byte transaction.
CS(1)
tDLY
tDLY
tDLY
25 26
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24
SCLK
DIN
Register Data 6
Command Byte 1
Command Byte 2
Register Data 5
Example: Write six registers, starting at register 05h (OFC0)
Command Byte 1 = 0100 0101
Command Byte 2 = 0000 0101
(1) CS can be tied low. See Figure 1 for CS low to SCLK rising edge time.
Figure 69. Write Register Data (Table 26 shows tDLY
)
8.5.1.11 OFSCAL: Offset Calibration
The OFSCAL command performs an offset calibration. The inputs to the converter (or the inputs to the external
preamplifier) should be zeroed and allowed to stabilize before sending this command. The offset calibration
register updates after this operation. See the Calibration Commands section for more details.
8.5.1.12 GANCAL: Gain Calibration
The GANCAL command performs a gain calibration. The inputs to the converter should have a stable dc input
(typically full-scale, but not to exceed 106% full-scale). The gain calibration register updates after this operation.
See the Calibration Commands section for more details.
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8.6 Register Maps
Collectively, the registers contain all the information needed to configure the device, such as data rate, filter
selection, calibration, and more. The registers are accessed by the RREG and WREG commands. The registers
can be accessed individually or as a block of registers by sending or receiving consecutive bytes. After a register
write operation, the ADC resets, resulting in an interruption of 63 readings.
Table 27. Register Map
RESET
ADDRESS
00h
REGISTER
ID_CFG
CONFIG0
CONFIG1
HPF0
VALUE
X0h
52h
08h
32h
03h
00h
00h
00h
00h
00h
40h
BIT 7
ID3
BIT 6
ID2
BIT 5
ID1
BIT 4
ID0
BIT 3
0
BIT 2
0
BIT 1
OFFSET1
FILTR1
PGA1
BIT 0
OFFSET0
FILTR0
PGA0
01h
SYNC
0
MODE
MUX2
HPF06
HPF14
OFC06
OFC14
OFC22
FSC06
FSC14
FSC22
DR2
DR1
DR0
PHASE
PGA2
HPF02
HPF10
OFC02
OFC10
OFC18
FSC02
FSC10
FSC18
02h
MUX1
HPF05
HPF13
OFC05
OFC13
OFC21
FSC05
FSC13
FSC21
MUX0
HPF04
HPF12
OFC04
OFC12
OFC20
FSC04
FSC12
FSC20
CHOP
HPF03
HPF11
OFC03
OFC11
OFC19
FSC03
FSC11
FSC19
03h
HPF07
HPF15
OFC07
OFC15
OFC23
FSC07
FSC15
FSC23
HPF01
HPF09
OFC01
OFC09
OFC17
FSC01
FSC09
FSC17
HPF00
HPF08
OFC00
OFC08
OFC16
FSC00
FSC08
FSC16
04h
HPF1
05h
OFC0
06h
OFC1
07h
OFC2
08h
FSC0
09h
FSC1
0Ah
FSC2
8.6.1 Register Descriptions
8.6.1.1 ID_CFG: ID_Configuration Register (address = 00h) [reset =x0h]
Figure 70. ID_CFG Register
7
6
5
4
3
0
2
0
1
0
ID3
R-xh
ID2
R-xh
ID1
R-xh
ID0
R-xh
OFFSET1
R/W-0h
OFFSET0
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit[7:4]
ID[3:0]
Factory-programmed identification bits (read-only). The ID bits are subject to change
without notification.
Bit[3:2]
Bit[1:0]
Reserved
Always write 00
OFFSET[1:0] (see Offset section)
00: Offset disabled (default)
01: Reserved
10: Offset = 100/PGA mV
11: Offset = 75/PGA mV
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8.6.1.2 CONFIG0: Configuration Register 0 (address = 01h) [reset = 52h]
Figure 71. CONFIG0 Register
7
6
5
4
3
2
1
0
SYNC
R/W-0h
MODE
R/W-1h
DR2
DR1
DR0
PHASE
R/W-0h
FILTR1
R/W -1h
FILTR0
R/W-0h
R/W-0h
R/W-1h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit[7]
SYNC
Synchronization mode bit.
0: Pulse-sync mode (default)
1: Continuous-sync mode
Bit[6]
MODE
Mode Control
0: Low-power mode
1: High-resolution mode (default)
Bit[5:3]
DR[2:0]
Data rate select bits.
000: 250 SPS
001: 500 SPS
010: 1000 SPS (default)
011: 2000 SPS
100: 4000 SPS
Bit[2]
PHASE
FIR phase response bit.
0: Linear phase (default)
1: Minimum phase
Bit[1:0]
FILTR[1:0]
Digital filter configuration bits.
00: Reserved
01: Sinc filter block only
10: Sinc + LPF filter blocks (default)
11: Sinc + LPF + HPF filter blocks
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8.6.1.3 CONFIG1: Configuration Register 1 (address = 02h) [reset = 08h]
Figure 72. CONFIG1 Register
7
0
6
5
4
3
2
1
0
MUX2
R/W-0h
MUX1
R/W-0h
MUX0
R/W-0h
CHOP
R/W-1h
PGA2
R/W-0h
PGA1
R/W-0h
PGA0
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit[7]
Reserved
Always write 0
MUX[2:0]
Bit[6:4]
MUX select bits.
000: AINP1 and AINN1 (default)
001: AINP2 and AINN2
010: Internal short through 400-Ω resistor
011: AINP1 and AINN1 connected to AINP2 and AINN2
100: External short to AINN2
Bit[3]
CHOP
PGA chopping enable bit.
0: PGA chopping disabled
1: PGA chopping enabled (default)
Bit[2:0]
PGA[2:0]
PGA gain select bits.
000: G = 1 (default)
001: G = 2
010: G = 4
011: G = 8
100: G = 16
101: G = 32
110: G = 64
8.6.1.4 HPF0 and HPF1 Registers
These two bytes (high-byte and low-byte, respectively) set the corner frequency of the high-pass filter.
8.6.1.4.1 HPF0: High-Pass Filter Corner Frequency, Low Byte (address = 03h) [reset = 32h]
Figure 73. HPF0 Register
7
6
5
4
3
2
1
0
HPF07
R/W-0h
HPF06
R/W-0h
HPF05
R/W-1h
HPF04
R/W-1h
HPF03
R/W-0h
HPF02
R/W-0h
HPF01
R/W-1h
HPF00
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.1.4.2 HPF1: High-Pass Filter Corner Frequency, High Byte (address = 04h) [reset = 03h]
Figure 74. HPF1 Register
7
6
5
4
3
2
1
0
HPF15
R/W-0h
HPF14
R/W-0h
HPF13
R/W-0h
HPF12
R/W-0h
HPF11
R/W-0h
HPF10
R/W-0h
HPF09
R/W-1h
HPF08
1R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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8.6.1.5 OFC0, OFC1, OFC2 Registers
These three bytes set the offset calibration value.
8.6.1.5.1 OFC0: Offset Calibration, Low Byte (address = 05h) [reset = 00h]
Figure 75. OFC0 Register
7
6
5
4
3
2
1
0
OFC07
R/W-0h
OFC06
R/W-0h
OFC05
R/W-0h
OFC04
R/W-0h
OFC03
R/W-0h
OFC02
R/W-0h
OFC01
R/W-0h
OFC00
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.1.5.2 OFC1: Offset Calibration, Mid Byte (address = 06h) [reset = 00h]
Figure 76. OFC1 Register
7
6
5
4
3
2
1
0
OFC15
R/W-0h
OFC14
R/W-0h
OFC13
R/W-0h
OFC12
R/W-0h
OFC11
R/W-0h
OFC10
R/W-0h
OFC09
R/W-0h
OFC08
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.1.5.3 OFC2: Offset Calibration, High Byte (address = 07h) [reset = 00h]
Figure 77. OFC2 Register
7
6
5
4
3
2
1
0
OFC23
R/W-0h
OFC22
R/W-0h
OFC21
R/W-0h
OFC20
R/W-0h
OFC19
R/W-0h
OFC18
R/W-0h
OFC17
R/W-0h
OFC16
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.1.6 FSC0, FSC1, FSC2 Registers
These three bytes set the full-scale calibration value.
8.6.1.6.1 FSC0: Full-Scale Calibration, Low Byte (address = 08h) [reset = 00h]
Figure 78. FSC0 Register
7
6
5
4
3
2
1
0
FSC07
R/W-0h
FSC06
R/W-0h
FSC05
R/W-0h
FSC04
R/W-0h
FSC03
R/W-0h
FSC02
R/W-0h
FSC01
R/W-0h
FSC00
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.1.6.2 FSC1: Full-Scale Calibration, Mid Byte (address = 09h) [reset = 00h]
Figure 79. FSC1 Register
7
6
5
4
3
2
1
0
FSC15
R/W-0h
FSC14
R/W-0h
FSC13
R/W-0h
FSC12
R/W-0h
FSC11
R/W-0h
FSC10
R/W-0h
FSC09
R/W-0h
FSC08
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.1.6.3 FSC2: Full-Scale Calibration, High Byte (address = 0Ah) [reset = 40h]
Figure 80. FSC2 Register
7
6
5
4
3
2
1
0
FSC23
R/W-0h
FSC22
R/W-1h
FSC21
R/W-0h
FSC20
R/W-0h
FSC19
R/W-0h
FSC18
R/W-0h
FSC17
R/W-0h
FSC16
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ADS1284 is a very high-resolution ADC with two modes of operation that provide tradeoffs between power
consumption and SNR performance. Optimal performance requires giving special attention to the support
circuitry and printed circuit board (PCB) design. Locate noisy digital components (such as microcontrollers,
oscillators, and so on) in an area of the PCB away from the converter and front-end components. Keep the digital
current path short and separate from sensitive analog components by placing the digital components close to the
power-entry point.
9.2 Typical Applications
9.2.1 Geophone Interface
A typical geophone front-end application is shown in Figure 81. The application diagram shows the ADS1284
operation with dual ±2.5-V analog supplies. The ADS1284 can also operate with a single 5-V analog supply.
+2.5V
-
2.5V
1 mF
AVDD
AVSS
AINP2
AINN2
Test
Signal
+2.5V
(1)
R1
R3
100 Ω
100 Ω
AINP1
AINN1
C2
R5
C4
10nF
C0G
1 nF, C0G
20 kΩ
Geophone
R6
R2
R4
C3
20 kΩ 100 Ω
100 Ω
1 nF, C0G
ADC
-2.5V
CAPP
CAPN
C6
10 nF
C0G
+3.3V
R7
1 kΩ
(2)
1 mF
VREFP
VREFN
REF5050
+
NR
C5
100 mF
C7
0.1 mF
1 mF
1 mF
DGND
-
2.5V
(1) Optional external diode clamps.
(2) Optional reference noise filter.
Figure 81. Geophone Interface Application
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Typical Applications (continued)
The geophone input signal is filtered by both a differential filter (components C4 and R1 to R4) and by common-
mode filters (components C2, C3 and R1, R2). The differential filter removes high-frequency normal-mode
components from the input signal. The common-mode filters remove high-frequency components that are
common to both input leads. The input filters are not required for all applications; check the system requirements
for each application.
Resistors R5 and R6 bias the signal input to the midsupply point (ground). For single-supply operation, set the
bias to a low impedance midsupply point (AVDD / 2 = 2.5 V).
Optional diode clamps protect the ADS1284 inputs from high-level voltage transients and overloads. The diodes
provide additional protection if possible high-level input transients and surges exceed the ADC internal ESD
diode rating.
The REF5050 5-V reference provides the reference to the ADC. An optional filter network ®7 and C5) reduces
the in-band reference noise for improved dynamic performance. However, the RC filter network increases the
filter settling-time (from seconds to possibly minutes) depending on the dielectric absorption properties of
capacitor C5. Capacitor C7 is mandatory and provides high-frequency bypassing of the reference inputs; place C7
as close as possible to the ADS1284 pins. Resistor R7 (1 kΩ) results in a 1% systematic gain error. Multiple
ADCs can share a single reference, but if shared, use independent reference filters for each ADC.
As an alternative, the REF5045 (4.5 V) reference can be used. The REF5045 reference has the advantage of
operating directly from the 5-V (total) power supply; however, the 4.5-V reference reduces signal range by 10%
and results in a 1-dB loss of SNR.
Capacitor C6 (10 nF) filters the PGA output glitches caused by sampling of the modulator. This capacitor also
forms an antialias filter with a low-pass cutoff frequency of 26 kHz.
54
Copyright © 2018–2019, Texas Instruments Incorporated
ADS1284
www.ti.com.cn
ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
Typical Applications (continued)
9.2.2 Digital Interface
Figure 82 shows the digital connection to a controller (field programmable gate array or microcontroller). In this
example, two ADCs are shown connected to one controller. The ADCs share the same serial interface (SCLK,
DIN, and DOUT). The ADC is selected for communication by strobing each CS low. The DRDY output from both
ADCs can be used; however, when the devices are synchronized, the DRDY output from only one device is
sufficient.
Clock
ADC #1
Controller
47 Ω
(1)
+3.3V
DVDD
CLK
CLK (input)
47 Ω
47 Ω
RESET (output)
1 µF
1 µF
RESET
SYNC
SYNC (output)
SS1 (output)
47 Ω
47 Ω
47 Ω
BYPAS
CS
SCLK (output)
SCLK
DIN
DOUT
MOSI (output)
MISO (input)
47 Ω
47 Ω
47 Ω
MFLAG
MFLAG1 (input)
MFLAG2 (input)
DGND
ADC #2
47 Ω
47 Ω
SS2 (output)
DRDY (input)
(1)
DVDD
CLK
RESET
SYNC
+3.3V
1 µF
1 µF
BYPAS
CS
SCLK
DIN
DOUT
MFLAG
DRDY
DGND
(1) For DVDD < 2.25 V, tie DVDD and BYPASS together. see the DVDD Power Supply section.
Figure 82. Controller Interface with Dual ADCs
The modulator overrange flag (MFLAG) from each device ties to the controller input. For synchronization,
connect all ADCs to the same SYNC signal. For reset, either connect all ADCs to the same RESET signal or
connect the ADCs to individual RESET signals.
Avoid ringing on the digital inputs to the ADCs. Place 47-Ω resistors in series with the digital traces to help
reduce ringing by controlling impedances. Place the resistors at the source (driver) end of the trace. Do not float
unused digital inputs; tie them to DVDD or GND.
Copyright © 2018–2019, Texas Instruments Incorporated
55
ADS1284
ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
www.ti.com.cn
9.3 Initialization Set Up
After reset or power-on, configure the registers using the following procedure:
1. Reset the serial interface. Before using the serial interface, it may be necessary to recover the serial
interface (undefined I/O power-up sequencing may cause a false SCLK to occur). To reset the interface,
toggle the CS pin high then low, or toggle the RESET pin high then low, or when in read-data-continuous
mode, hold SCLK low for 64 DRDY periods.
2. Configure the registers. The registers are configured by either writing to them individually or as a group,
and can be configured in either mode. To cancel read-data-continuous mode, send the SDATAC command
before register read and write operations .
3. Verify register data. For verification of device communications, read back the register.
4. Set the data mode. After register configuration, configure the device for read-data-continuous mode by
executing the RDATAC command, or configure for read-data-by-command mode (set in step 2, by the
SDATAC command).
5. Synchronize readings. Whenever SYNC is high, the ADS1284 freely runs the data conversions. To
resynchronize the conversions in pulse-sync mode, take SYNC low and then high. In continuous-sync mode,
apply the synchronizing clock to the SYNC pin with a clock period equal to multiples of the ADC conversion
period.
6. Read data. If read-data-continuous mode is active, the data are read directly after DRDY falls by applying
SCLK pulses. If the read-data-continuous mode is inactive, the data can only be read by executing the
RDATA command. The RDATA command must be sent in this mode to read each conversion result.
56
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ADS1284
www.ti.com.cn
ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
10 器件和文档支持
10.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.3 商标
E2E is a trademark of Texas Instruments.
SPI is a trademark of Motorola Inc.
All other trademarks are the property of their respective owners.
10.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
10.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2018–2019, Texas Instruments Incorporated
57
ADS1284
ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
www.ti.com.cn
11 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
58
版权 © 2018–2019, Texas Instruments Incorporated
ADS1284
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ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
版权 © 2018–2019, Texas Instruments Incorporated
59
ADS1284
ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
www.ti.com.cn
60
版权 © 2018–2019, Texas Instruments Incorporated
ADS1284
www.ti.com.cn
ZHCSIU4A –SEPTEMBER 2018–REVISED AUGUST 2019
版权 © 2018–2019, Texas Instruments Incorporated
61
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS1284IRHFR
ADS1284IRHFT
ACTIVE
VQFN
VQFN
RHF
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
ADS
1284
ACTIVE
RHF
NIPDAU
ADS
1284
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
RHF0024A
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
0.5
0.3
5.1
4.9
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.65 0.1
2X 2
(0.1) TYP
12
EXPOSED
8
THERMAL PAD
20X 0.5
7
13
3.65 0.1
2X
3
25
SYMM
SEE TERMINAL
DETAIL
19
1
0.30
0.18
24X
0.1
C B A
PIN 1 ID
(OPTIONAL)
24
20
SYMM
0.05
0.5
0.3
24X
4219064 /A 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHF0024A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.65)
SYMM
20
24
24X (0.6)
1
19
24X (0.24)
(3.65)
(1.575)
20X (0.5)
25
SYMM
(4.8)
(0.62)
TYP
(R0.05)
TYP
13
7
(
0.2) TYP
VIA
8
12
(1.025)
TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219064 /A 04/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHF0024A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
6X (1.17)
(0.685) TYP
20
24
24X (0.6)
1
19
24X (0.24)
(1.24)
TYP
20X (0.5)
SYMM
(4.8)
25
6X (1.04)
13
(R0.05) TYP
7
METAL
TYP
12
8
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219064 /A 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
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