ADS124S08IRHBT [TI]
适用于传感器测量且具有 PGA 和电压基准的 24 位、4kSPS、12 通道 Δ-Σ ADC | RHB | 32 | -50 to 125;
| 型号： | ADS124S08IRHBT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于传感器测量且具有 PGA 和电压基准的 24 位、4kSPS、12 通道 Δ-Σ ADC | RHB | 32 | -50 to 125 传感器 |
| 文件： | 总114页 (文件大小：3258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS124S06, ADS124S08
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
ADS124S0x具有 PGA 和电压基准的低功耗、低噪声、高集成度 6 通道及
12 通道
4kSPS、24 位 Δ-Σ ADC
1 特性
3 说明
1
•
•
低功耗：低至 280µA
ADS124S06 和 ADS124S08 均为高精度 24 位 Δ-Σ 模
数转换器 (ADC)，兼具低功耗特性与多种集成 特性，
能够降低系统成本并减少小型传感器信号测量 应用 中
的组件数。
低噪声可编程增益放大器 (PGA)：19nVRMS（增益
= 128 时）
•
•
•
可编程增益：1 至 128
可编程数据传输速率：2.5SPS 至 4kSPS
这两款 ADC 均配有可配置的数字滤波器，能够在嘈杂
的工业环境中提供低延迟转换结果和 50Hz 或
60Hz 噪声抑制。可编程增益放大器 (PGA) 具备低噪
声特性，并且可提供 1 到 128 的增益，能够为电阻桥
或热电偶应用放大低幅值 信号，SN65HVD101 和
'HVD102 采用 20 引脚 RGB 封装 (4 mm × 3.5 mm
QFN)。此外，这两款器件还集成有一个低漂移 2.5V
电压基准，减小了印刷电路板 (PCB) 面积。最后还有
两个可编程的激励电流源 (IDAC)，便于提供准确的电
阻式温度检测器 (RTD) 偏置。
采用低延迟数字滤波器，在
≤ 20SPS 时实现 50Hz 和 60Hz 同步抑制
•
•
具有 12 路 (ADS124S08) 或 6 路 (ADS124S06) 独
立可选输入的模拟多路复用器
两个匹配且可编程的传感器激励电流源：10μA 至
2000µA
•
•
•
•
•
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•
内部基准：2.5V，最大漂移为 10ppm/°C
内部振荡器：4.096MHz，精度为 1.5%
内部温度传感器
扩展型故障检测电路
自偏移校准与系统校准
输入多路复用器支持适用于 ADS124S08 的 12 路输入
和适用于 ADS124S06 的 6 路输入。这些输入能够以
任意组合形式连接到 ADC，从而提高设计灵活性。此
外，这两款器件还 包含 传感器烧毁检测、热电偶电压
偏置和系统监视等功能以及四个通用 I/O。
4 个通用 I/O
串行外设接口 (SPI) 兼容接口，可选用循环冗余校
验 (CRC)
•
•
•
模拟电源：单极（2.7V 到 5.25V）或双极 (±2.5V)
数字电源：2.7V 到 3.6V
这两款器件采用超薄四方扁平无引线 (VQFN)-32 或薄
型四方扁平 (TQFP)-32 封装。
工作温度：-50°C 至 +125°C
2 应用
器件信息
•
传感器和变送器：
温度、压力、应力，流量
订货编号
ADS124S0x
封装（引脚）
TQFP (32)
VQFN (32)
封装尺寸
5.0mm × 5.0mm
5.0mm × 5.0mm
•
可编程逻辑控制器 (PLC) 和分布式控制系统 (DCS)
模拟输入模块
•
•
温度控制器
人工气候室，工业烘箱
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS660
REFN0 REFP0 REFCOM REFOUT
DVDD IOVDD
ADS124S06, ADS124S08
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
www.ti.com.cn
功能方框图
AVSS-SW
AVDD
Burnout
Detect
2.5-V
Reference
ADS124S06
ADS124S08
Reference
Mux
Excitation
Current
AINCOM
AIN0
Sources
Reference
Detection
AIN1
Reference
Buffers
AIN2
VBIAS
START/SYNC
RESET
CS
AIN3
AIN4
Configurable
Digital
Filter
Serial
Interface
and
24-Bit ûꢀ
ADC
Input
Mux
PGA
AIN5
SCLK
AIN6 / REFP1
AIN7 / REFN1
AIN8 / GPIO0
AIN9 / GPIO1
Control
DIN
PGA Rail
Detection
DOUT/DRDY
DRDY
System-, Self-
Calibration
Power Supplies
AIN10 / GPIO2
AIN11 / GPIO3
Temperature
Sensor
4.096-MHz
Oscillator
CLK
ADS124S08
only
Burnout
Detect
AVSS
DGND
Copyright © 2016, Texas Instruments Incorporated
2
版权 © 2016–2017, Texas Instruments Incorporated
ADS124S06, ADS124S08
www.ti.com.cn
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
目录
9.6 Register Map........................................................... 72
10 Application and Implementation........................ 86
10.1 Application Information.......................................... 86
10.2 Typical Application ................................................ 91
10.3 Do's and Don'ts..................................................... 95
11 Power Supply Recommendations ..................... 98
11.1 Power Supplies ..................................................... 98
11.2 Power-Supply Sequencing.................................... 98
11.3 Power-On Reset.................................................... 98
11.4 Power-Supply Decoupling..................................... 98
12 Layout................................................................... 99
12.1 Layout Guidelines ................................................. 99
12.2 Layout Example .................................................. 100
13 器件和文档支持 ................................................... 101
13.1 器件支持.............................................................. 101
13.2 文档支持.............................................................. 101
13.3 相关链接.............................................................. 101
13.4 接收文档更新通知 ............................................... 101
13.5 社区资源.............................................................. 101
13.6 商标..................................................................... 101
13.7 静电放电警告....................................................... 101
13.8 Glossary.............................................................. 101
14 机械、封装和可订购信息..................................... 102
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
Device Family Comparison Table ........................ 5
Pin Configuration and Functions......................... 5
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ..................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information.................................................. 8
7.5 Electrical Characteristics........................................... 9
7.6 Timing Characteristics............................................. 14
7.7 Switching Characteristics........................................ 14
7.8 Typical Characteristics............................................ 17
Parameter Measurement Information ................ 24
8.1 Noise Performance ................................................. 24
Detailed Description ............................................ 29
9.1 Overview ................................................................. 29
9.2 Functional Block Diagram ....................................... 30
9.3 Feature Description................................................. 31
9.4 Device Functional Modes........................................ 58
9.5 Programming........................................................... 62
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (November 2016) to Revision C
Page
•
•
Added note to Pin Configuration and Functions section ........................................................................................................ 5
Added TQFP package to test conditions of first row and added second row to Internal Voltage Reference, Accuracy
parameter ............................................................................................................................................................................. 11
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changed typical specification of Reference noise parameter from 17.5 µVPP to 9 µVPP ..................................................... 11
已更改 DRDY trace of START Command Timing Requirements figure............................................................................... 16
已更改 Typical Characteristics section ................................................................................................................................. 17
已更改 values in Table 1....................................................................................................................................................... 24
已更改 values in Table 3....................................................................................................................................................... 25
已添加 footnote 1 to Table 5................................................................................................................................................. 26
已更改 values in Table 5....................................................................................................................................................... 26
已添加 footnote 1 to Table 5 and Table 6 ........................................................................................................................... 26
已更改 values in Table 7....................................................................................................................................................... 27
已添加 last paragraph to PGA Input-Voltage Requirements section.................................................................................... 34
已添加 when the internal reference voltage is enabled to fifth sentence of Internal Reference section.............................. 36
已添加 last paragraph to Low-Latency Filter Frequency Response section ....................................................................... 38
已更改 footnotes 1 and 3 of Table 13................................................................................................................................... 42
已添加 link to ADS1x4S0x design calculator to Sinc3 Filter Frequency Response section ................................................. 43
已更改 footnotes 1 and 3 of Table 15 .................................................................................................................................. 45
已更改 footnotes 1 and 3 of Table 18................................................................................................................................... 48
已更改 footnotes 1 and 3 of Table 19................................................................................................................................... 49
已更改 IDAC routing description in IDAC Block Diagram figure........................................................................................... 50
版权 © 2016–2017, Texas Instruments Incorporated
3
ADS124S06, ADS124S08
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
www.ti.com.cn
修订历史记录 (接下页)
•
•
•
•
已添加 last sentence to first paragraph of PGA Output Voltage Rail Monitors section ....................................................... 53
已更改 third sentence in last paragraph of WREG section for clarity................................................................................... 68
已添加 footnote 1 to GPIO Configuration Register section .................................................................................................. 85
已更改 cross-reference in last paragraph of External Reference and Ratiometric Measurements section to point to
the Typical Application section ............................................................................................................................................. 88
•
•
•
已添加 last sentence to second paragraph of Unused Inputs and Outputs section............................................................. 89
已添加 Send the RDATA command; to Pseudo Code Example section ............................................................................. 90
已更改 Internal Reference block text to 2.5-V Reference and deleted connection dot from AVSS-SW pin in 3-Wire
RTD Application figure.......................................................................................................................................................... 91
•
•
•
•
已更改 3-Wire RTD Measurement with Lead-Wire Compensation section title to Register Settings................................... 94
已添加 on all other analog inputs to first sentence of sixth bullet in Do's and Don'ts section.............................................. 96
已更改 second sentence of Power-Supply Decoupling section for clarity............................................................................ 98
已添加 器件支持 部分 ......................................................................................................................................................... 101
Changes from Revision A (August 2016) to Revision B
Page
•
已发布为量产数据................................................................................................................................................................... 1
4
Copyright © 2016–2017, Texas Instruments Incorporated
ADS124S06, ADS124S08
www.ti.com.cn
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
5 Device Family Comparison Table
PRODUCT
ADS124S08
ADS124S06
ADS114S08
ADS114S06
RESOLUTION (Bits)
NUMBER OF INPUTS
12 analog inputs
6 analog inputs
24
24
16
16
12 analog inputs
6 analog inputs
6 Pin Configuration and Functions
RHB Package
32-Pin VQFN
Top View
PBS Package
32-Pin TQFP
Top View
AINCOM
AIN5
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
REFCOM
AINCOM
AIN5
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
REFCOM
REFOUT
REFOUT
AIN4
GPIO0/AIN8
GPIO1/AIN9
GPIO2/AIN10
GPIO3/AIN11
RESET
AIN4
GPIO0/AIN8
GPIO1/AIN9
GPIO2/AIN10
GPIO3/AIN11
RESET
AIN3
AIN3
Thermal
Pad
AIN2
AIN2
AIN1
AIN1
AIN0
AIN0
START/SYNC
CLK
START/SYNC
CLK
Not to scale
Not to scale
NOTE: The analog input functions (AIN6–AIN11) are not available on pins 19 to 22, 31, and 32 for the ADS124S06.
Copyright © 2016–2017, Texas Instruments Incorporated
5
ADS124S06, ADS124S08
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
www.ti.com.cn
Pin Functions
PIN
NO.
NAME
AINCOM
AIN5
FUNCTION
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Digital input
Digital input
Digital input
Digital input
Digital output
Digital output
Digital ground
DESCRIPTION(1)
1
2
3
4
5
6
7
8
9
Common analog input for single-ended measurements
Analog input 5
AIN4
Analog input 4
AIN3
Analog input 3
AIN2
Analog input 2
AIN1
Analog input 1
AIN0
Analog input 0
START/SYNC
CS
Start conversion
Chip select; active low
Serial data input
10
11
12
13
14
DIN
SCLK
Serial clock input
DOUT/DRDY
DRDY
DGND
Serial data output combined with data ready; active low
Data ready; active low
Digital ground
Digital I/O power supply. In case IOVDD is not tied to DVDD, connect a 100-nF (or larger) capacitor to
DGND.
15
IOVDD
Digital supply
16
17
18
19
20
21
22
DVDD
CLK
Digital supply
Digital input
Digital core power supply. Connect a 100-nF (or larger) capacitor to DGND.
External clock input. Connect to DGND to use the internal oscillator.
Reset; active low
General-purpose I/O(2); analog input 11 (ADS124S08 only)
General-purpose I/O(2); analog input 10 (ADS124S08 only)
General-purpose I/O(2); analog input 9 (ADS124S08 only)
General-purpose I/O(2); analog input 8 (ADS124S08 only)
RESET
Digital input
GPIO3/AIN11
GPIO2/AIN10
GPIO1/AIN9
GPIO0/AIN8
Analog input/output
Analog input/output
Analog input/output
Analog input/output
Positive voltage reference output. Connect a 1-µF to 47-µF capacitor to REFCOM if the internal
voltage reference is enabled.
23
REFOUT
Analog output
24
25
26
27
28
29
30
31
32
REFCOM
NC
Analog output
—
Negative voltage reference output. Connect to AVSS.
Leave unconnected or connect to AVSS
AVDD
Analog supply
Analog supply
Analog supply
Analog input
Analog input
Analog input
Analog input
—
Positive analog power supply. Connect a 330-nF (or larger) capacitor to AVSS.
Negative analog power supply
AVSS
AVSS-SW
REFN0
Negative analog power supply; low-side switch. Connect to AVSS.
Negative external reference input 0
REFP0
Positive external reference input 0
REFN1/AIN7
REFP1/AIN6
Thermal pad
Negative external reference input 1; analog input 7 (ADS124S08 only)
Positive external reference input 1; analog input 6 (ADS124S08 only)
RHB package only. Thermal power pad. Connect to AVSS.
(1) See the Unused Inputs and Outputs section for details on how to connect unused pins.
(2) General-purpose inputs and outputs use logic levels based on the analog supply.
6
Copyright © 2016–2017, Texas Instruments Incorporated
ADS124S06, ADS124S08
www.ti.com.cn
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
7 Specifications
7.1 Absolute Maximum Ratings(1)
MIN
–0.3
MAX
5.5
UNIT
AVDD to AVSS
AVSS to DGND
Power-supply voltage
–2.8
0.3
V
DVDD to DGND
–0.3
3.9
IOVDD to DGND
–0.3
5.5
Analog input voltage
Digital input voltage
AINx, GPIOx, REFPx, REFNx, REFCOM
AVSS – 0.3
AVDD + 0.3
V
V
CS, SCLK, DIN, DOUT/DRDY, DRDY,
START, RESET, CLK
DGND – 0.3
IOVDD + 0.3
Continuous, AVSS-SW, REFN0, REFOUT
Continuous, all other pins except power-supply pins
Junction, TJ
–100
–10
100
10
Input current
Temperature
mA
°C
150
150
Storage, Tstg
–60
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2016–2017, Texas Instruments Incorporated
7
ADS124S06, ADS124S08
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
AVDD to AVSS
2.7
–2.625
1.5
5.25
0.05
5.25
3.6
Analog power supply
AVSS to DGND
AVDD to DGND
DVDD to DGND
IOVDD to DGND
0
V
Digital core power supply
Digital IO power supply
2.7
V
V
DVDD
5.25
ANALOG INPUTS(1)
PGA bypassed
AVSS – 0.05
AVDD + 0.05
AVSS + 0.15 +
|VINMAX|·(Gain – 1) / 2
AVDD – 0.15 –
|VINMAX|·(Gain –1) / 2
PGA enabled, gain = 1 to 16
V(AINx)
Absolute input voltage(2)
Differential input voltage
V
AVSS + 0.15 +
AVDD – 0.15 –
15.5·|VINMAX|
PGA enabled, gain = 32 to 128
VIN = VAINP – VAINN
15.5·|VINMAX
|
VIN
–VREF / Gain
VREF / Gain
V
V
VOLTAGE REFERENCE INPUTS(3)
Differential reference input
voltage
VREF
VREF = V(REFPx) – V(REFNx)
0.5
AVDD – AVSS
Negative reference buffer disabled
Negative reference buffer enabled
Positive reference buffer disabled
Positive reference buffer enabled
AVSS – 0.05
AVSS
V(REFPx) – 0.5
V(REFPx) – 0.5
AVDD + 0.05
AVDD
V
V
V
V
Absolute negative reference
V(REFNx)
voltage
V(REFNx) + 0.5
V(REFNx) + 0.5
Absolute positive reference
V(REFPx)
voltage
EXTERNAL CLOCK SOURCE(4)
fCLK
External clock frequency
Duty cycle
2
4.096
50%
4.5
MHz
40%
60%
GENERAL-PURPOSE INPUTS (GPIOs)
Input voltage
AVSS – 0.05
DGND
AVDD + 0.05
IOVDD
V
V
DIGITAL INPUTS (Other than GPIOs)
Input voltage
TEMPERATURE RANGE
TA
Operating ambient temperature
–50
125
°C
(1) AINP and AINN denote the positive and negative inputs of the PGA. Any of the available analog inputs (AINx) can be selected as either
AINP or AINN by the input multiplexer.
(2) VINMAX denotes the maximum differential input voltage, VIN, that is expected in the application. |VINMAX| can be smaller than VREF / Gain.
(3) REFPx and REFNx denote one of the two available external differential reference input pairs.
(4) An external clock is not required when the internal oscillator is used.
7.4 Thermal Information
ADS124S06, ADS124S08
THERMAL METRIC(1)
VQFN (RHB)
32 PINS
45.2
TQFP (PBS)
32 PINS
75.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
28.3
17.1
15.8
28.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
0.4
ψJB
15.7
28.3
RθJC(bot)
2.3
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8
Copyright © 2016–2017, Texas Instruments Incorporated
ADS124S06, ADS124S08
www.ti.com.cn
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
7.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –50°C to +125°C; Typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal
oscillator, all data rates, and global chop disabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
PGA bypassed,
AVSS + 0.1 V ≤ V(AINx) ≤ AVDD – 0.1 V
0.5
0.1
2
Absolute input current
nA
PGA enabled, all gains,
–2
2
V(AINx)MIN ≤ V(AINx) ≤ V(AINx)MAX
PGA bypassed,
AVSS + 0.1 V ≤ V(AINx) ≤ AVDD – 0.1 V
Absolute input current drift
Differential input current
Differential input current drift
pA/°C
PGA enabled, all gains,
2
V(AINx)MIN ≤ V(AINx) ≤ V(AINx)MAX
PGA bypassed,
VCM = AVDD / 2, –VREF ≤ VIN ≤ VREF
1
nA/V
nA
PGA enabled, all gains,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
–1
0.02
3
1
PGA bypassed,
VCM = AVDD / 2, –VREF ≤ VIN ≤ VREF
pA/°C
PGA enabled, all gains,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
1
PGA
1, 2, 4, 8, 16,
32, 64, 128
Gain settings
Startup time
Enabling the PGA in conversion mode
190
µs
SYSTEM PERFORMANCE
Resolution (no missing codes)
24
Bits
SPS
2.5, 5, 10, 16.6,
20, 50, 60, 100,
200, 400, 800,
DR
INL
Data rate
1000, 2000, 4000
PGA bypassed, VCM = AVDD / 2
1
2
10
15
PGA enabled, gain = 1 to 8, VCM = AVDD / 2
Integral nonlinearity (best fit)
ppmFSR
PGA enabled, gain = 16 to 128, VCM = AVDD / 2,
TA = –40°C to +85°C
3
15
TA = 25°C, PGA bypassed
–120
–120 / Gain
–15
20
20 / Gain
2
120
120 / Gain
15
TA = 25°C, PGA enabled, gain = 1 to 8
TA = 25°C, PGA enabled, gain = 16 to 128
TA = 25°C, PGA bypassed, after internal offset
calibration
On the order of noisePP at the
set DR and gain
VIO
Input offset voltage
µV
TA = 25°C, PGA enabled, gain = 1 to 128, after
internal offset calibration
On the order of noisePP at the
set DR and gain
TA = 25°C, PGA bypassed, global chop enabled
–2
–2
0.2
0.2
2
2
TA = 25°C, PGA enabled, gain = 1 to 128,
global chop enabled
TA = –40°C to +85°C, PGA bypassed
TA = –40°C to +85°C, PGA enabled, gain = 1 to 128
PGA bypassed
–75
–100
–75
10
15
10
15
15
2
75
100
75
Offset drift
PGA enabled, gain = 1 to 8
–200
–150
–10
200
150
10
nV/°C
PGA enabled, gain = 16 to 128
PGA bypassed, global chop enabled
PGA enabled, gain = 1 to 128, global chop enabled
–10
2
10
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Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –50°C to +125°C; Typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal
oscillator, all data rates, and global chop disabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE (continued)
TA = 25°C, PGA bypassed
40
40
40
0.5
0.5
0.5
1
120
120
200
1
Gain error(1)
TA = 25°C, PGA enabled, gain = 1 to 32
TA = 25°C, PGA enabled, gain = 64 and 128
TA = –40°C to +85°C, PGA bypassed
TA = –40°C to +85°C, PGA enabled, gain = 1 to 128
PGA bypassed
ppm
2
Gain drift(1)
ppm/°C
nVRMS
1
PGA enabled, gain = 1 to 128
4
PGA enabled, gain = 128, DR = 2.5 SPS,
sinc3 filter
Noise (input-referred)(2)
19
fIN = 50 Hz or 60 Hz (±1 Hz), DR = 10 SPS,
sinc3 filter
88
102
79
fIN = 50 Hz or 60 Hz (±1 Hz), DR = 10 SPS,
sinc3 filter, external fCLK = 4.096 MHz
fIN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS,
low-latency filter
fIN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS,
low-latency filter, external fCLK = 4.096 MHz
95
87
NMRR Normal-mode rejection ratio(3)
dB
fIN = 50 Hz (±1 Hz), DR = 50 SPS, sinc3 filter
fIN = 50 Hz (±1 Hz), DR = 50 SPS,
sinc3 filter, external fCLK = 4.096 MHz
101
89
fIN = 60 Hz (±1 Hz), DR = 60 SPS, sinc3 filter
fIN = 60 Hz (±1 Hz), DR = 60 SPS,
sinc3 filter, external fCLK = 4.096 MHz
105
110
120
At dc
120
130
fCM = 50 Hz or 60 Hz (±1 Hz),
DR = 2.5 SPS to 10 SPS, sinc3 filter
CMRR Common-mode rejection ratio
PSRR Power-supply rejection ratio
dB
dB
fCM = 50 Hz or 60 Hz (±1 Hz),
DR = 2.5 SPS, 5 SPS, 10 SPS, 20 SPS, low-latency
filter
115
125
AVDD at dc
90
100
100
105
115
115
AVDD at 50 Hz or 60 Hz
DVDD at dc
(1) Excluding error of voltage reference.
(2) See the Noise Performance section for more information.
(3) See the 50-Hz and 60-Hz Line Cycle Rejection section for more information.
10
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ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –50°C to +125°C; Typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal
oscillator, all data rates, and global chop disabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REFERENCE INPUTS
Reference buffers disabled, external VREF = 2.5 V,
REFP1/REFN1 inputs
-6
4
5
6
µA/V
nA
Absolute input current
Reference buffers enabled, external VREF = 2.5 V,
REFP1/REFN1 inputs
–15
15
INTERNAL VOLTAGE REFERENCE
VREF
Output voltage
2.5
±0.01%
±0.01%
2.5
V
TA = 25°C, TQFP package
TA = 25°C, VQFN package
TA = –40°C to +85°C
–0.05%
–0.1%
0.05%
0.1%
8
Accuracy
Temperature drift
ppm/°C
mA
TA = –50°C to +125°C
3
10
AVDD = 2.7 V to 3.3 V, sink and source
AVDD = 3.3 V to 5.25 V, sink and source
Sink and source
–5
5
Output current
–10
10
Short-circuit current limit
70
85
100
mA
dB
PSRR Power-supply rejection ratio
AVDD at dc
AVDD = 2.7 V to 3.3 V,
load current = –5 mA to 5 mA
8
Load regulation
µV/mA
AVDD = 3.3 V to 5.25 V,
load current = –10 mA to 10 mA
8
Startup time
Capacitive load stability
Reference noise
1-µF capacitor on REFOUT, 0.001% settling
Capacitor on REFOUT
5.9
ms
µF
1
47
f = 0.1 Hz to 10 Hz, 1-µF capacitor on REFOUT
9
µVPP
INTERNAL OSCILLATOR
fCLK
Frequency
Accuracy
4.096
MHz
–1.5%
1.5%
EXCITATION CURRENT SOURCES (IDACS)
10, 50, 100,
250, 500, 750,
1000, 1500, 2000
Current settings
µA
V
10 µA to 750 µA, 0.1% deviation
AVSS
AVSS
–5%
AVDD – 0.4
AVDD – 0.6
5%
Compliance voltage(4)
Accuracy (each IDAC)
1 mA to 2 mA, 0.1% deviation
TA = 25°C, 10 µA to 100 µA
TA = 25°C, 250 µA to 2 mA
TA = 25°C, 10 µA to 100 µA
TA = 25°C, 250 µA to 750 µA
TA = 25°C, 1 mA to 2 mA
10 µA to 750 µA
±0.7%
±0.5%
0.15%
0.10%
0.07%
20
–3%
3%
0.8%
0.6%
0.4%
120
Current mismatch between
IDACs
Temperature drift (each IDAC)
ppm/°C
1 mA to 2 mA
10
80
10 µA to 100 µA
3
25
Temperature drift matching
between IDACs
ppm/°C
µs
250 µA to 2 mA
2
15
With internal reference already settled. From end of
WREG command to current flowing out of pin.
Startup time
22
(4) The IDAC current does not change by more than 0.1% from the nominal value when staying within the specified compliance voltage.
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Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –50°C to +125°C; Typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal
oscillator, all data rates, and global chop disabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BIAS VOLTAGE
(AVDD + AVSS) / 2,
(AVDD + AVSS) / 12
VBIAS
Output voltage settings
Output impedance
Startup time
V
Ω
350
2.8
Combined capacitive load on all selected analog
inputs CLOAD = 1 µF, 0.1% settling
ms
BURNOUT CURRENT SOURCES (BOCS)
Current settings
0.2, 1, 10
±8%
µA
0.2 µA, sinking or sourcing
1 µA, sinking or sourcing
10 µA, sinking or sourcing
Accuracy
±4%
±2%
PGA RAIL DETECTION
Positive rail threshold
Negative rail threshold
REFERENCE DETECTION
Threshold 1
Referred to the output of the PGA
Referred to the output of the PGA
AVDD – 0.15
AVSS + 0.15
V
V
0.3
V
V
Threshold 2
1/3·(AVDD – AVSS)
Threshold 2 accuracy
Pull-together resistance
SUPPLY VOLTAGE MONITORS
–3%
±1%
10
3%
MΩ
(AVDD – AVSS) / 4 monitor
DVDD / 4 monitor
±1%
±1%
Accuracy
TEMPERATURE SENSOR
Output voltage
TA = 25°C
129
403
mV
Temperature coefficient
LOW-SIDE POWER SWITCH
µV/°C
RON
On-resistance
1
3
Ω
Current through switch
75
mA
GENERAL-PURPOSE INPUT/OUTPUTS (GPIOs)
VIL
Logic input level, low
Logic input level, high
Logic output level, low
Logic output level, high
AVSS – 0.05
0.7 AVDD
AVSS
0.3 AVDD
AVDD + 0.05
0.2 AVDD
AVDD
V
V
V
V
VIH
VOL
VOH
IOL = 1 mA
IOH = 1 mA
0.8 AVDD
DIGITAL INPUT/OUTPUTS
VIL
Logic input level, low
Logic input level, high
Logic output level, low
Logic output level, high
Input current
DGND
0.7 IOVDD
DGND
0.3 IOVDD
IOVDD
0.2 IOVDD
IOVDD
1
V
V
VIH
VOL
VOH
IOL = 1 mA
V
IOH = 1 mA
0.8 IOVDD
–1
V
DGND ≤ VDigital Input ≤ IOVDD
µA
12
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ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –50°C to +125°C; Typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal
oscillator, all data rates, and global chop disabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG SUPPLY CURRENT (AVDD = 3.3 V, External Reference, Internal Reference Disabled, Reference Buffers Disabled, IDACs Disabled, VBIAS
Disabled, Flags Disabled, Internal Oscillator, All Data Rates, VIN = 0 V)
Power-down mode
0.1
70
1.5
Standby mode, PGA bypassed
Conversion mode, PGA bypassed
85
Conversion mode, PGA enabled, gain = 1, 2
Conversion mode, PGA enabled, gain = 4, 8
Conversion mode, PGA enabled, gain = 16, 32
Conversion mode, PGA enabled, gain = 64
Conversion mode, PGA enabled, gain = 128
120
140
165
200
250
135
155
180
IAVDD
Analog supply current
µA
ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 3.3 V)
Internal 2.5-V reference, no external load
Positive reference buffer
185
35
25
10
20
30
40
50
65
10
280
60
Negative reference buffer
40
VBIAS buffer, no external load
IDAC overhead, 10 µA to 250 µA
35
IAVDD
Analog supply current
µA
IDAC overhead, 500 µA to 750 µA
IDAC overhead, 1 mA
IDAC overhead, 1.5 mA
IDAC overhead, 2 mA
PGA rail detection and reference detection circuit
DIGITAL SUPPLY CURRENT (DVDD = IOVDD = 3.3 V, All Data Rates, SPI Not Active)
Power-down mode, internal oscillator
0.1
185
225
195
Standby mode, internal oscillator
IDVDD
IIOVDD
+
Digital supply current
µA
Conversion mode, internal oscillator
300
Conversion mode, external fCLK = 4.096 MHz
POWER DISSIPATION (AVDD = DVDD = IOVDD = 3.3 V, Internal Reference Enabled, Reference Buffers Disabled, IDACs Disabled, VBIAS Disabled,
Flags Disabled, Internal Oscillator, All Data Rates, VIN = 0 V, SPI Not Active)
PD
Power dissipation
Conversion mode, PGA enabled, gain = 1
1.75
mW
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7.6 Timing Characteristics
over operating ambient temperature range, DVDD = 2.7 V to 3.6 V, IOVDD = DVDD to 5.25 V, and
DOUT/DRDY load = 20 pF || 100 kΩ to DGND (unless otherwise noted)
MIN
MAX
UNIT(1)
SERIAL INTERFACE
td(CSSC)
td(SCCS)
tw(CSH)
tc(SC)
Delay time, first SCLK rising edge after CS falling edge
Delay time, CS rising edge after final SCLK falling edge
Pulse duration, CS high
20
20
30
100
40
40
15
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK period
tw(SCH)
tw(SCL)
tsu(DI)
Pulse duration, SCLK high
Pulse duration, SCLK low
Setup time, DIN valid before SCLK falling edge
Hold time, DIN valid after SCLK falling edge
Delay time, between bytes or commands
th(DI)
td(CMD)
RESET PIN
tw(RSL)
Pulse duration, RESET low
4
tCLK
tCLK
Delay time, first SCLK rising edge after RESET rising edge (or 7th SCLK
falling edge of RESET command)
td(RSSC)
4096
START/SYNC PIN
tw(STH) Pulse duration, START/SYNC high
tw(STL)
4
4
tCLK
tCLK
Pulse duration, START/SYNC low
Setup time, START/SYNC falling edge (or 7th SCLK falling edge of STOP
command) before DRDY falling edge to stop further conversions
(continuous conversion mode)
tsu(STDR)
32
tCLK
READING CONVERSION DATA WITHOUT RDATA COMMAND
th(SCDR)
td(DRSC)
(1) tCLK = 1 / fCLK
Hold time, SCLK low before DRDY falling edge(2)
Delay time, SCLK rising edge after DRDY falling edge(2)
28
4
tCLK
tCLK
.
(2) Only applicable when reading data without the RDATA command. All commands can be send without any SCLK to DRDY signal timing
restrictions.
7.7 Switching Characteristics
over operating ambient temperature range, DVDD = 2.7 V to 3.6 V, IOVDD = DVDD to 5.25 V, and
DOUT/DRDY load = 20 pF || 100 kΩ to DGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT(1)
Propagation delay time, CS falling edge to DOUT
driven
tp(CSDO)
tp(SCDO)
tp(CSDOZ)
0
25
ns
Propagation delay time, SCLK rising edge to valid
new DOUT
3
0
30
25
ns
ns
Propagation delay time, CS rising edge to DOUT high
impedance
Propagation delay time, START/SYNC rising edge (or
first SCLK rising edge of any command or data read)
to DRDY rising edge
tp(STDR)
2
tCLK
tw(DRH)
tp(GPIO)
Pulse duration, DRDY high
24
3
tCLK
ns
Propagation delay time, last SCLK falling edge of
WREG command to GPIOx output valid
100
SPI timeout per 8 bit(2)
215
tCLK
(1) tCLK = 1 / fCLK
(2) The SPI interface resets when an entire byte is not sent within the specified timeout time.
14
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ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
tw(CSH)
CS
SCLK
DIN
ttd(CSSC)
t
ttc(SC)
t
tw(SCH)
ttd(SCCS)t
tsu(DI)
th(DI)
tw(SCL)
NOTE: Single-byte communication is shown. Actual communication can be multiple bytes.
图 1. Serial Interface Timing Requirements
CS
SCLK
tp(CSDO)
tp(SCDO)
tp(CSDOZ)
Hi-Z
Hi-Z
DOUT/DRDY
NOTE: Single-byte communication is shown. Actual communication can be multiple bytes.
图 2. Serial Interface Switching Characteristics
tw(RSL)
RESET
SCLK
DIN
td(RSSC)
RESET command
New command
图 3. RESET Pin and RESET Command Timing Requirements
tw(STL)
START/SYNC
DRDY
tw(STH)
tp(STDR)
tw(DRH)
tp(STDR)
tsu(STDR)
图 4. START/SYNC Pin Timing Requirements
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SCLK
DIN
START command
STOP command
tp(STDR)
tp(STDR)
DRDY
tsu(STDR)
图 5. START Command Timing Requirements
th(SCDR)
DRDY
CS
SCLK
td(DRSC)
DOUT/DRDY
Data 1
Data 2
Data 3
图 6. Read Data Direct (Without an RDATA Command) Timing Requirements
SCLK
DIN
WREG
01h
01h
01h
GPIO0 set as output
GPIO0 set high
GPIO0 enabled
Write two registers
WREG GPIODAT
GPIO0
tp(GPIO)
图 7. GPIO Switching Characteristics
16
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ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
7.8 Typical Characteristics
at TA = 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal VREF = 2.5 V, internal 4.096-MHz oscillator,
and PGA enabled (unless otherwise noted)
2000
1000
0
2000
1000
0
-50èC
25èC
85èC
125èC
-50èC
25èC
85èC
125èC
-1000
-2000
-3000
-4000
-1000
-2000
-3000
-4000
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
V(AINx) (V)
V(AINx) (V)
PGA bypassed, DR = 20 SPS, VIN = 0 V
PGA bypassed, DR = 4 kSPS, VIN = 0 V
图 8. Absolute Input Current vs Absolute Input Voltage
图 9. Absolute Input Current vs Absolute Input Voltage
2000
1500
1000
500
2000
1500
1000
500
-50èC
25èC
85èC
125èC
-50èC
25èC
85èC
125èC
0
0
-500
-1000
-1500
-2000
-500
-1000
-1500
-2000
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
V(AINx) (V)
V(AINx) (V)
PGA enabled, gain = 1, DR = 20 SPS, VIN = 0 V
PGA enabled, gain = 1, DR = 4 kSPS, VIN = 0 V
图 10. Absolute Input Current vs Absolute Input Voltage
图 11. Absolute Input Current vs Absolute Input Voltage
2000
2000
-50èC
25èC
85èC
125èC
-50èC
25èC
85èC
125èC
1500
1000
500
1500
1000
500
0
0
-500
-1000
-1500
-2000
-500
-1000
-1500
-2000
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
VIN (V)
VIN (V)
PGA bypassed, DR = 20 SPS, VCM = 1.65 V
PGA bypassed, DR = 4 kSPS, VCM = 1.65 V
图 12. Differential Input Current vs Differential Input Voltage
图 13. Differential Input Current vs Differential Input Voltage
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal VREF = 2.5 V, internal 4.096-MHz oscillator,
and PGA enabled (unless otherwise noted)
200
150
100
50
400
300
200
100
0
-50èC
25èC
85èC
125èC
-50èC
25èC
85èC
125èC
0
-50
-100
-200
-300
-400
-100
-150
-200
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
VIN (V)
VIN (V)
PGA enabled, DR = 20 SPS, VCM = 1.65 V
PGA enabled, DR = 4 kSPS, VCM = 1.65 V
图 14. Differential Input Current vs Differential Input Voltage
图 15. Differential Input Current vs Differential Input Voltage
3
3
2
1
2
1
0
0
-1
-2
-3
-1
-2
-3
-100 -80 -60 -40 -20
0
20
40
60
80 100
-100 -80 -60 -40 -20
0
20
40
60
80 100
VIN (% of FSR)
VIN (% of FSR)
PGA enabled, gain = 1
PGA bypassed, gain = 1
图 16. INL vs Differential Input Voltage
图 17. INL vs Differential Input Voltage
16
14
12
10
8
10
8
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
6
4
6
4
2
2
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
图 18. INL vs Temperature
图 19. Offset Voltage vs Temperature
18
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal VREF = 2.5 V, internal 4.096-MHz oscillator,
and PGA enabled (unless otherwise noted)
100
2.5
2.4995
2.499
50
0
-50
-100
-150
-200
-250
2.4985
2.498
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
2.4975
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
28 units, TQFP package
图 20. Gain Error vs Temperature
图 21. Internal Reference Voltage vs Temperature
2.5002
2.5001
2.5
10
8
6
4
2
0
2.4999
2.4998
2.4997
-2
-4
-6
-8
-10
2.7
3
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
Time (1 s/div)
AVDD (V)
图 23. Internal Reference Voltage Noise
图 22. Internal Reference Voltage vs AVDD
250
200
150
100
50
4.13
4.12
4.11
4.1
4.09
4.08
4.07
4.06
0
-50
-25
0
25
50
75
100
125
Temperature (èC)
Internal Oscillator Frequency (MHz)
28 units
图 24. Internal Oscillator Frequency Histogram
图 25. Internal Oscillator Frequency vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal VREF = 2.5 V, internal 4.096-MHz oscillator,
and PGA enabled (unless otherwise noted)
0
-1
-2
-3
-4
-5
0
-10
-20
-30
-40
-50
10 µA
50 µA
100 µA
250 µA
500 µA
750 µA
1 mA
1.5 mA
2 mA
10 µA
50 µA
100 µA
250 µA
500 µA
750 µA
1 mA
1.5 mA
2 mA
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
0
0.5
1
1.5
2
2.5
3
3.5
IDAC Output Voltage (V)
IDAC Output Voltage (V)
图 27. IDAC Accuracy vs Compliance Voltage
图 26. IDAC Accuracy vs Compliance Voltage
3
2
0.3
0.25
0.2
10 mA
750 mA
50 mA
1 mA
100 mA
250 mA
500 mA
1.5 mA
2 mA
1
0
0.15
0.1
-1
-2
-3
10 mA
750 mA
1 mA
1.5 mA
2 mA
50 mA
100 mA
250 mA
500 mA
0.05
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
IDAC output voltage = 1.65 V
图 28. IDAC Accuracy vs Temperature
图 29. IDAC Matching vs Temperature
0.501
0.5005
0.5
0.085
0.084
0.083
0.082
0.081
0.08
AVDD = 2.7 V
AVDD = 5.25 V
AVDD = 2.7 V
AVDD = 5.25 V
0.4995
0.499
0.4985
0.498
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
图 30. VBIAS Voltage [(AVDD – AVSS) / 2] vs Temperature
图 31. VBIAS Voltage [(AVDD – AVSS) / 12] vs Temperature
20
版权 © 2016–2017, Texas Instruments Incorporated
ADS124S06, ADS124S08
www.ti.com.cn
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal VREF = 2.5 V, internal 4.096-MHz oscillator,
and PGA enabled (unless otherwise noted)
0.18
0.17
0.16
0.15
0.14
0.13
0.12
0.11
0.1
0.18
0.17
0.16
0.15
0.14
0.13
0.12
0.11
0.1
AVDD = 2.7 V
AVDD = 5.25 V
AVDD = 2.7 V
AVDD = 5.25 V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
图 32. PGA Rail Detection, PGAN_RAILP, PGAP_RAILP
图 33. PGA Rail Detection, PGAN_RAILN, PGAP_RAILN
Threshold From AVDD
Threshold From AVSS
0.335
0.32
AVDD = 2.7 V
AVDD = 5.25 V
AVDD = 2.7 V
AVDD = 5.25 V
0.31
0.3
0.3345
0.334
0.29
0.28
0.27
0.3335
0.333
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
Level 0 = 300 mV
图 34. Reference Threshold Voltage, Level 0
Level 1 = 1/3 · (AVDD – AVSS)
图 35. Reference Threshold Voltage, Level 1
180
160
140
120
100
80
1.8
1.6
1.4
1.2
1
AVDD = 2.7 V
AVDD = 3.3 V
AVDD = 5.25 V
0.8
0.6
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
图 36. Temperature Sensor Voltage vs Temperature
图 37. Low-Side Switch RON vs Temperature
版权 © 2016–2017, Texas Instruments Incorporated
21
ADS124S06, ADS124S08
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal VREF = 2.5 V, internal 4.096-MHz oscillator,
and PGA enabled (unless otherwise noted)
3.3
3.2
3.1
3
0.6
0.5
0.4
0.3
0.2
0.1
0
-50èC
25èC
85èC
125èC
2.9
2.8
2.7
-50èC
25èC
85èC
125èC
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Sourcing Current (mA)
Sinking Current (mA)
AVDD = 3.3 V
AVDD = 3.3 V
图 38. GPIO Pin Output Voltage vs Sourcing Current
图 39. GPIO Pin Output Voltage vs Sinking Current
0.6
0.5
0.4
0.3
0.2
0.1
0
3.3
-50èC
25èC
85èC
125èC
3.2
3.1
3
2.9
2.8
2.7
-50èC
25èC
85èC
125èC
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Sourcing Current (mA)
Sinking Current (mA)
DVDD = 3.3 V
DVDD = 3.3 V
图 40. Digital Pin Output Voltage vs Sourcing Current
图 41. Digital Pin Output Voltage vs Sinking Current
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
Standby mode
PGA bypassed
Gain = 1
Gain = 4
Gain = 16
Gain = 64
Gain = 128
PGA bypassed
Gain = 1
Gain = 4
Gain = 16
Gain = 64
Gain = 128
0
0
-50
-25
0
25
50
75
100
125
2.7
3
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
Temperature (èC)
AVDD (V)
Standby and conversion mode, external VREF
Conversion mode, external VREF
图 42. Analog Supply Current vs Temperature
图 43. Analog Supply Current vs AVDD
22
版权 © 2016–2017, Texas Instruments Incorporated
ADS124S06, ADS124S08
www.ti.com.cn
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal VREF = 2.5 V, internal 4.096-MHz oscillator,
and PGA enabled (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
260
240
220
200
180
160
140
120
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
Power-down mode
图 44. Analog Supply Current vs Temperature
图 45. Internal Reference AVDD Current vs Temperature
260
260
240
220
200
180
160
140
120
240
220
200
180
160
140
120
Standby mode
Conversion mode
-50
-25
0
25
50
75 100 125
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
Temperature (èC)
DVDD (V)
Standby and conversion mode
Conversion mode
图 47. Digital Supply Current vs DVDD
图 46. Digital Supply Current vs Temperature
5
4
3
2
1
0
-50
-25
0
25
50
75
100
125
Temperature (èC)
Power-down mode
图 48. Digital Supply Current vs Temperature
版权 © 2016–2017, Texas Instruments Incorporated
23
ADS124S06, ADS124S08
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
www.ti.com.cn
8 Parameter Measurement Information
8.1 Noise Performance
Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input
signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and
decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between
modulator frequency and output data rate is called the oversampling ratio (OSR). By increasing the OSR, and
thus reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the
input-referred noise drops when reducing the output data rate because more samples of the internal modulator
are averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is
particularly useful when measuring low-level signals.
表 1 to 表 4 summarize the device noise performance. 表 1 and 表 2 list the ADC measurement noise using the
sinc3 digital filter at different data rates and different PGA settings, and 表 3 and 表 4 list the ADC measurement
noise using the low-latency digital filter. Data are representative of typical noise performance at TA = 25°C using
the internal 2.5-V reference. Data shown are based on 512 consecutive samples from a single device with inputs
internally shorted. 表 1 and 表 3 list the input-referred root mean square noise in units of μVRMS for the conditions
shown. Note that peak-to-peak (µVPP) values are shown in parentheses. 表 2 and 表 4 list the corresponding
data in effective resolution calculated from μVRMS values using 公式 1. Noise-free resolution is calculated from
µVPP values using 公式 2.
The input-referred noise (表 1 and 表 3) only changes marginally when using an external low-noise reference,
such as the REF5025. To calculate effective resolution and noise-free resolution when using a reference voltage
other than 2.5 V, use 公式 1 and 公式 2:
Effective Resolution = ln[(2 · VREF / Gain) / VRMS-Noise] / ln(2)
Noise-Free Resolution= ln[(2 · VREF / Gain) / VPP-Noise] / ln(2)
(1)
(2)
表 5 to 表 8 repeat the measurements of 表 1 to 表 4 but use the global chop feature of the device. The global
chop feature averages two measurement of the ADC with the inputs swapped. This feature significantly reduces
the input offset of the device, and reduces noise in the measurement.
Noise performance with the PGA bypassed are identical to the noise performance of the device with gain = 1 in
表 1 to 表 8.
表 1. Noise in μVRMS (μVPP) with Sinc3 Filter,
at AVDD = 3.3 V, AVSS = 0 V, PGA Enabled, Global Chop Disabled, and Internal 2.5-V Reference
DATA
RATE
(SPS)
GAIN
1
2
4
8
16
32
64
128
2.5
5
0.32 (1.8)
0.40 (2.4)
0.53 (3.0)
0.76 (4.2)
0.81 (4.8)
1.3 (7.2)
1.4 (8.0)
1.8 (9.2)
2.4 (13)
3.6 (19)
5.0 (29)
6.0 (32)
7.8 (45)
15. (95)
0.16 (0.89)
0.21 (1.0)
0.29 (1.6)
0.36 (2.2)
0.41 (2.4)
0.62 (3.7)
0.70 (4.5)
0.91 (5.8)
1.2 (7.7)
1.8 (10)
0.085 (0.45)
0.11 (0.60)
0.16 (0.89)
0.20 (1.2)
0.22 (1.4)
0.33 (1.9)
0.37 (2.4)
0.49 (2.6)
0.64 (4.0)
0.87 (5.0)
1.3 (7.8)
0.049 (0.26)
0.066 (0.37)
0.088 (0.52)
0.11 (0.67)
0.12 (0.71)
0.18 (1.2)
0.21 (1.3)
0.27 (1.8)
0.39 (2.3)
0.54 (3.4)
0.76 (5.2)
0.85 (5.2)
1.2 (6.9)
0.036 (0.20)
0.040 (0.30)
0.061 (0.39)
0.077 (0.47)
0.082 (0.48)
0.13 (0.76)
0.12 (0.71)
0.17 (1.1)
0.26 (1.6)
0.34 (2.1)
0.49 (2.7)
0.56 (3.2)
0.78 (4.5)
1.2 (7.1)
0.025 (0.14)
0.033 (0.20)
0.046 (0.25)
0.060 (0.35)
0.064 (0.44)
0.11 (0.69)
0.11 (0.87)
0.14 (0.88)
0.21 (1.3)
0.28 (1.7)
0.41 (2.5)
0.42 (2.5)
0.64 (4.0)
0.87 (5.2)
0.020 (0.13)
0.029 (0.18)
0.040 (0.24)
0.052 (0.32)
0.056 (0.37)
0.091 (0.54)
0.10 (0.67)
0.12 (0.72)
0.19 (1.1)
0.019 (0.11)
0.027 (0.16)
0.036 (0.23)
0.046 (0.30)
0.048 (0.30)
0.080 (0.53)
0.089 (0.58)
0.11 (0.52)
0.15 (0.95)
0.22 (1.3)
10
16.6
20
50
60
100
200
400
800
1000
2000
4000
0.25 (1.5)
2.6 (16)
0.37 (2.2)
0.34 (2.0)
2.9 (17)
1.5 (10)
0.41 (2.3)
0.37 (2.2)
4.2 (26)
2.1 (14)
0.57 (3.5)
0.54 (2.8)
7.3 (45)
3.9 (25)
2.0 (11)
0.83 (5.1)
0.80 (5.0)
24
版权 © 2016–2017, Texas Instruments Incorporated
ADS124S06, ADS124S08
www.ti.com.cn
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
表 2. Effective Resolution from RMS Noise (Noise-Free Resolution from Peak-to-Peak Noise)
with Sinc3 Filter at AVDD = 3.3 V, AVSS = 0 V, PGA Enabled,
Global Chop Disabled, and Internal 2.5-V Reference
DATA
RATE
(SPS)
GAIN
1
2
4
8
16
32
64
128
2.5
5
23.9 (21.4)
23.6 (21.0)
23.2 (20.7)
22.6 (20.2)
22.6 (20.0)
21.9 (19.4)
21.8 (19.2)
21.4 (19.0)
21.0 (18.6)
20.4 (18.0)
19.9 (17.4)
19.7 (17.2)
19.3 (16.8)
18.4 (15.7)
23.9 (21.4)
23.5 (21.2)
23.0 (20.5)
22.7 (20.1)
22.5 (20.0)
21.9 (19.4)
21.8 (19.1)
21.4 (18.7)
20.9 (18.3)
20.4 (17.9)
19.9 (17.2)
19.7 (17.2)
19.2 (16.6)
18.4 (15.7)
23.8 (21.4)
23.4 (21.0)
22.9 (20.4)
22.6 (20.0)
22.4 (19.8)
21.9 (19.3)
21.7 (19.0)
21.3 (18.9)
20.9 (18.2)
20.5 (17.9)
19.9 (17.3)
19.6 (16.9)
19.2 (16.5)
18.3 (15.6)
23.6 (21.2)
23.2 (20.7)
22.8 (20.2)
22.4 (19.8)
22.3 (19.8)
21.7 (19.0)
21.5 (18.8)
21.1 (18.4)
20.6 (18.1)
20.2 (17.5)
19.7 (16.9)
19.5 (16.9)
18.9 (16.5)
18.3 (15.7)
23.0 (20.5)
22.9 (20.0)
22.3 (19.6)
22.0 (19.4)
21.9 (19.3)
21.2 (18.6)
21.3 (18.8)
20.8 (18.1)
20.2 (17.6)
19.8 (17.2)
19.3 (16.8)
19.1 (16.6)
18.6 (16.1)
18.0 (15.4)
22.6 (20.2)
22.2 (19.5)
21.7 (19.2)
21.3 (18.8)
21.2 (18.4)
20.5 (17.8)
20.4 (17.5)
20.1 (17.4)
19.5 (16.9)
19.1 (16.5)
18.6 (16.0)
18.5 (16.1)
17.9 (15.3)
17.5 (14.9)
21.9 (19.1)
21.4 (18.9)
20.9 (18.4)
20.5 (17.9)
20.4 (17.7)
19.7 (17.2)
19.5 (16.8)
19.3 (16.7)
18.6 (16.1)
18.2 (15.7)
17.7 (15.1)
17.6 (14.9)
17.1 (14.4)
16.5 (13.9)
21.0 (18.4)
20.5 (17.6)
20.1 (17.3)
19.7 (17.0)
19.6 (17.0)
18.9 (16.2)
18.7 (16.0)
18.4 (16.0)
18.0 (15.3)
17.4 (14.9)
16.8 (14.3)
16.7 (14.1)
16.2 (13.8)
15.6 (12.9)
10
16.6
20
50
60
100
200
400
800
1000
2000
4000
表 3. Noise in μVRMS (μVPP) with Low-Latency Filter,
at AVDD = 3.3 V, AVSS = 0 V, PGA Enabled, Global Chop Disabled, and Internal 2.5-V Reference
DATA
GAIN
RATE
(SPS)
1
2
4
8
16
32
64
128
2.5
5
0.46 (2.7)
0.62 (3.9)
0.94 (6.6)
1.3 (8.0)
1.2 (8.0)
2.1 (13)
2.3 (15)
2.8 (18)
4.6 (28)
6.1 (31)
8.6 (36)
10 (50)
0.24 (1.3)
0.33 (1.6)
0.47 (3.0)
0.66 (3.9)
0.65 (3.9)
1.0 (6.6)
1.2 (7.5)
1.6 (10)
2.2 (13)
3.0 (19)
4.3 (27)
5.0 (29)
11 (80)
0.12 (0.82)
0.18 (1.1)
0.24 (1.4)
0.32 (2.0)
0.34 (1.9)
0.54 (3.1)
0.62 (3.7)
0.83 (5.1)
1.1 (6.9)
1.6 (11)
0.072 (0.41)
0.10 (0.52)
0.14 (0.78)
0.18 (1.2)
0.20 (1.2)
0.30 (1.9)
0.35 (2.2)
0.45 (2.9)
0.67 (4.1)
0.92 (5.1)
1.3 (8.0)
0.051 (0.30)
0.064 (0.37)
0.09 (0.52)
0.12 (0.69)
0.13 (0.67)
0.22 (1.3)
0.22 (1.4)
0.30 (1.7)
0.42 (2.6)
0.46 (2.6)
0.81 (4.6)
0.90 (5.4)
1.6 (11)
0.041 (0.27)
0.053 (0.31)
0.074 (0.44)
0.10 (0.56)
0.10 (0.64)
0.16 (1.2)
0.19 (1.1)
0.23 (1.3)
0.34 (2.0)
0.48 (2.8)
0.66 (4.0)
0.79 (5.1)
1.1 (6.7)
0.037 (0.20)
0.050 (0.33)
0.065 (0.37)
0.086 (0.55)
0.093 (0.54)
0.15 (0.90)
0.16 (0.99)
0.38 (2.6)
0.29 (1.9)
0.42 (2.9)
0.58 (3.8)
0.66 (4.3)
1.1 (6.7)
0.034 (0.19)
0.046 (0.27)
0.057 (0.35)
0.079 (0.52)
0.082 (0.51)
0.13 (0.84)
0.15 (0.90)
0.20 (1.3)
0.28 (1.7)
0.39 (2.3)
0.55 (3.2)
0.59 (3.8)
1.0 (6.6)
10
16.6
20
50
60
100
200
400
800
1000
2000
4000
2.3 (15)
2.6 (15)
1.4 (8.9)
22 (83)
5.5 (32)
2.9 (17)
103 (629)
48 (404)
24 (160)
12 (70)
6.4 (39)
3.3 (21)
3.6 (20)
3.1 (19)
版权 © 2016–2017, Texas Instruments Incorporated
25
ADS124S06, ADS124S08
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
www.ti.com.cn
表 4. Effective Resolution from RMS Noise (Noise-Free Resolution from Peak-to-Peak Noise)
with Low-Latency Filter, at AVDD = 3.3 V, AVSS = 0 V, PGA Enabled,
Global Chop Disabled, and Internal 2.5-V Reference
DATA
RATE
(SPS)
GAIN
1
2
4
8
16
32
64
128
2.5
5
23.4 (20.8)
22.9 (20.3)
22.3 (19.5)
21.9 (19.2)
22.0 (19.2)
21.2 (18.5)
21.0 (18.3)
20.8 (18.1)
20.1 (17.4)
19.6 (17.3)
19.2 (17.1)
19.0 (16.6)
17.8 (15.9)
15.6 (13.0)
23.3 (20.8)
22.8 (20.5)
22.3 (19.7)
21.9 (19.3)
21.9 (19.3)
21.2 (18.5)
21.0 (18.4)
20.6 (17.9)
20.1 (17.6)
19.7 (17.0)
19.1 (16.5)
18.9 (16.4)
17.8 (14.9)
15.7 (12.6)
23.3 (20.5)
22.7 (20.1)
22.3 (19.8)
21.9 (19.2)
21.8 (19.3)
21.1 (18.6)
21.0 (18.4)
20.5 (17.9)
20.1 (17.5)
19.6 (16.8)
19.0 (16.4)
18.9 (16.3)
17.8 (15.3)
15.7 (12.9)
23.0 (20.5)
22.6 (20.2)
22.1 (19.6)
21.7 (19.0)
21.6 (19.0)
21.0 (18.3)
20.8 (18.1)
20.4 (17.7)
19.8 (17.2)
19.4 (16.9)
18.9 (16.3)
18.7 (16.1)
17.7 (15.2)
15.7 (13.1)
22.6 (20.0)
22.2 (19.7)
21.7 (19.2)
21.3 (18.8)
21.3 (18.8)
20.5 (17.9)
20.4 (17.7)
20.0 (17.5)
19.5 (16.9)
19.4 (16.9)
18.6 (16.0)
18.4 (15.8)
17.5 (14.8)
15.6 (13.0)
21.9 (19.1)
21.5 (19.0)
21.0 (18.4)
20.5 (18.1)
20.5 (17.9)
19.9 (17.0)
19.7 (17.1)
19.4 (16.9)
18.8 (16.2)
18.3 (15.8)
17.9 (15.2)
17.6 (14.9)
17.1 (14.5)
15.5 (12.9)
21.1 (18.6)
20.6 (17.9)
20.2 (17.8)
19.8 (17.1)
19.7 (17.2)
19.0 (16.4)
18.9 (16.3)
17.6 (14.9)
18.0 (15.3)
17.5 (14.7)
17.0 (14.3)
16.8 (14.2)
16.1 (13.5)
14.4 (11.9)
20.0 (17.6)
19.7 (17.1)
19.4 (16.7)
18.9 (16.2)
18.9 (16.2)
18.2 (15.5)
18.0 (15.4)
17.6 (14.9)
17.1 (14.5)
16.6 (14.0)
16.1 (13.6)
16.0 (13.3)
15.2 (12.5)
13.6 (11.0)
10
16.6
20
50
60
100
200
400
800
1000
2000
4000
表 5. Noise in μVRMS (μVPP) with Sinc3 Filter,
at AVDD = 3.3 V, AVSS = 0 V, PGA Enabled, Global Chop Enabled, and Internal 2.5-V Reference
DATA
GAIN
RATE
(SPS)(1)
1
2
4
8
16
32
64
128
2.5
5
0.22 (1.2)
0.31 (1.8)
0.41 (2.4)
0.54 (3.3)
0.60 (3.3)
0.91 (4.8)
1.0 (5.7)
1.2 (6.9)
1.8 (10)
2.5 (14)
3.5 (21)
3.9 (23)
6.0 (35)
10 (63)
0.11 (0.60)
0.15 (0.70)
0.21 (1.2)
0.28 (1.5)
0.31 (1.8)
0.49 (2.5)
0.51 (3.1)
0.63 (3.7)
0.90 (4.9)
1.2 (7.0)
1.8 (11)
0.063 (0.30)
0.080 (0.52)
0.12 (0.60)
0.14 (0.80)
0.16 (0.80)
0.23 (1.3)
0.26 (1.5)
0.33 (1.7)
0.48 (2.8)
0.60 (3.4)
1.0 (5.7)
0.031 (0.19)
0.049 (0.26)
0.061 (0.37)
0.080 (0.48)
0.090 (0.56)
0.14 (0.90)
0.16 (0.90)
0.19 (1.0)
0.022 (0.15)
0.032 (0.19)
0.042 (0.24)
0.052 (0.32)
0.059 (0.34)
0.090 (0.45)
0.10 (0.54)
0.13 (0.70)
0.19 (1.1)
0.017 (0.09)
0.024 (0.15)
0.031 (0.20)
0.043 (0.26)
0.046 (0.25)
0.070 (0.41)
0.090 (0.45)
0.11 (0.59)
0.15 (0.80)
0.20 (1.1)
0.014 (0.08)
0.020 (0.12)
0.029 (0.17)
0.039 (0.23)
0.043 (0.27)
0.069 (0.36)
0.070 (0.41)
0.089 (0.52)
0.14 (0.80)
0.18 (1.0)
0.013 (0.07)
0.019 (0.11)
0.027 (0.16)
0.034 (0.20)
0.037 (0.19)
0.058 (0.33)
0.067 (0.40)
0.084 (0.49)
0.12 (0.75)
0.16 (0.90)
0.23 (1.3)
10
16.6
20
50
60
100
200
400
800
1000
2000
4000
0.27 (1.4)
0.39 (2.4)
0.26 (1.6)
0.55 (3.2)
0.35 (2.1)
0.29 (1.7)
0.26 (1.4)
2.1 (13)
1.1 (6.0)
0.65 (3.5)
0.39 (2.3)
0.32 (1.9)
0.28 (1.6)
0.26 (1.5)
2.8 (16)
1.6 (8.0)
0.90 (5.0)
0.59 (3.5)
0.47 (2.5)
0.39 (2.2)
0.36 (2.1)
5.3 (30)
2.8 (16)
1.4 (9.0)
0.90 (5.0)
0.67 (4.0)
0.58 (3.3)
0.54 (3.2)
(1) The actual data conversion period changes with the sinc3 filter and global chop mode enabled; see 表 19 for details.
26
版权 © 2016–2017, Texas Instruments Incorporated
ADS124S06, ADS124S08
www.ti.com.cn
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
表 6. Effective Resolution from RMS Noise (Noise-Free Resolution from Peak-to-Peak Noise)
with Sinc3 Filter at AVDD = 3.3 V, AVSS = 0 V, PGA Enabled,
Global Chop Enabled, and Internal 2.5-V Reference
DATA
RATE
GAIN
(SPS)(1)
1
2
4
8
16
32
64
128
2.5
5
24.4 (22.0)
24.0 (21.4)
23.5 (21.0)
23.1 (20.5)
23.0 (20.5)
22.4 (20.0)
22.3 (19.8)
22.0 (19.5)
21.4 (18.9)
21.0 (18.5)
20.4 (17.9)
20.3 (17.7)
19.7 (17.1)
19.0 (16.3)
24.5 (22.0)
24.0 (21.7)
23.5 (21.0)
23.1 (20.7)
22.9 (20.4)
22.3 (19.9)
22.2 (19.6)
21.9 (19.4)
21.5 (19.0)
20.9 (18.4)
20.4 (17.8)
20.2 (17.6)
19.8 (17.2)
18.9 (16.4)
24.2 (22.0)
23.9 (21.2)
23.3 (21.0)
23.1 (20.5)
22.9 (20.5)
22.4 (19.8)
22.2 (19.7)
21.8 (19.5)
21.3 (18.8)
21.0 (18.5)
20.3 (17.7)
20.1 (17.7)
19.6 (17.2)
18.8 (16.2)
24.3 (21.7)
23.6 (21.2)
23.3 (21.0)
22.8 (20.5)
22.7 (20.5)
22.1 (19.8)
21.9 (19.7)
21.6 (19.5)
21.1 (18.8)
20.6 (18.5)
20.1 (17.7)
19.9 (17.7)
19.4 (17.2)
18.7 (16.2)
23.7 (21.0)
23.2 (20.7)
22.8 (20.3)
22.5 (19.9)
22.3 (19.8)
21.8 (19.4)
21.6 (19.1)
21.2 (18.7)
20.7 (18.1)
20.2 (17.6)
19.8 (17.2)
19.6 (17.0)
19.0 (16.5)
18.4 (15.9)
23.1 (20.7)
22.6 (20.0)
22.2 (19.6)
21.8 (19.2)
21.7 (19.2)
21.1 (18.5)
20.8 (18.4)
20.5 (18.0)
20.0 (17.6)
19.6 (17.1)
19.0 (16.5)
18.9 (16.3)
18.3 (15.9)
17.8 (15.3)
22.4 (19.8)
21.9 (19.4)
21.4 (18.9)
20.9 (18.4)
20.8 (18.2)
20.1 (17.7)
20.0 (17.5)
19.7 (17.2)
19.1 (16.6)
18.7 (16.1)
18.2 (15.7)
18.1 (15.6)
17.6 (15.2)
17.0 (14.5)
21.5 (19.1)
20.9 (18.5)
20.5 (17.9)
20.1 (17.6)
20.0 (17.6)
19.4 (16.8)
19.2 (16.6)
18.8 (16.3)
18.3 (15.7)
17.9 (15.4)
17.4 (14.9)
17.2 (14.7)
16.7 (14.2)
16.1 (13.6)
10
16.6
20
50
60
100
200
400
800
1000
2000
4000
(1) The actual data conversion period changes with the sinc3 filter and global chop mode enabled; see 表 19 for details.
表 7. Noise in μVRMS (μVPP) with Low-Latency Filter,
at AVDD = 3.3 V, AVSS = 0 V, PGA Enabled, Global Chop Enabled, and Internal 2.5-V Reference
DATA
GAIN
RATE
(SPS)
1
2
4
8
16
32
64
128
2.5
5
0.34 (2.1)
0.47 (2.7)
0.63 (3.6)
0.90 (4.5)
0.90 (5.1)
1.3 (8.0)
1.7 (10)
2.0 (12)
3.0 (17)
4.3 (22)
6.2 (25)
6.0 (38)
15 (51)
0.16 (0.90)
0.22 (1.3)
0.33 (1.8)
0.43 (2.5)
0.42 (2.5)
0.80 (4.6)
0.80 (4.3)
1.1 (6.0)
1.5 (8.0)
2.3 (13)
0.09 (0.52)
0.12 (0.60)
0.18 (1.0)
0.24 (1.4)
0.23 (1.4)
0.39 (2.5)
0.42 (2.8)
0.55 (3.2)
0.70 (4.1)
1.1 (6.0)
1.5 (9.0)
1.8 (11)
0.051 (0.26)
0.076 (0.45)
0.10 (0.56)
0.14 (0.90)
0.14 (0.90)
0.23 (1.2)
0.23 (1.4)
0.34 (1.9)
0.48 (2.9)
0.64 (3.7)
0.90 (5.0)
1.1 (6.3)
0.034 (0.17)
0.038 (0.22)
0.069 (0.37)
0.090 (0.50)
0.090 (0.63)
0.14 (0.90)
0.18 (1.0)
0.21 (1.3)
0.28 (1.7)
0.44 (2.4)
0.62 (3.4)
0.66 (3.7)
1.2 (7.0)
0.027 (0.15)
0.039 (0.23)
0.051 (0.30)
0.070 (0.40)
0.070 (0.41)
0.12 (0.70)
0.13 (0.70)
0.18 (1.1)
0.26 (1.4)
0.33 (1.9)
0.49 (2.8)
0.52 (2.8)
0.90 (5.2)
2.3 (15)
0.024 (0.14)
0.034 (0.20)
0.045 (0.26)
0.065 (0.38)
0.070 (0.39)
0.11 (0.61)
0.12 (0.69)
0.16 (0.90)
0.23 (1.3)
0.29 (1.8)
0.45 (2.5)
0.45 (2.7)
0.80 (5.6)
2.4 (13)
0.021 (0.13)
0.029 (0.19)
0.041 (0.25)
0.056 (0.35)
0.059 (0.36)
0.090 (0.50)
0.11 (0.67)
0.14 (0.80)
0.19 (1.0)
0.28 (1.7)
0.40 (2.3)
0.45 (2.5)
0.70 (3.9)
2.2 (12)
10
16.6
20
50
60
100
200
400
800
1000
2000
4000
3.1 (19)
3.3 (19)
8.0 (50)
4.0 (23)
2.2 (13)
65 (275)
35 (211)
18 (116)
9.0 (51)
4.4 (24)
版权 © 2016–2017, Texas Instruments Incorporated
27
ADS124S06, ADS124S08
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
www.ti.com.cn
表 8. Effective Resolution from RMS Noise (Noise-Free Resolution from Peak-to-Peak Noise)
with Low-Latency Filter, at AVDD = 3.3 V, AVSS = 0 V, PGA Enabled,
Global Chop Enabled, and Internal 2.5-V Reference
DATA
RATE
(SPS)
GAIN
1
2
4
8
16
32
64
128
2.5
5
23.8 (21.2)
23.3 (20.8)
22.9 (20.4)
22.4 (20.1)
22.4 (19.9)
21.8 (19.3)
21.5 (19.0)
21.2 (18.6)
20.7 (18.2)
20.1 (17.8)
19.6 (17.6)
19.6 (17.0)
18.4 (16.6)
16.2 (14.1)
23.9 (21.4)
23.4 (20.8)
22.9 (20.4)
22.5 (19.9)
22.5 (19.9)
21.7 (19.0)
21.6 (19.1)
21.1 (18.6)
20.7 (18.2)
20.1 (17.6)
19.6 (17.0)
19.5 (17.0)
18.2 (15.6)
16.1 (13.5)
23.7 (21.2)
23.3 (21.0)
22.7 (20.3)
22.3 (19.8)
22.4 (19.8)
21.6 (19.0)
21.5 (18.8)
21.1 (18.6)
20.7 (18.2)
20.1 (17.6)
19.7 (17.1)
19.4 (16.8)
18.2 (15.7)
16.1 (13.4)
23.5 (21.2)
23.0 (20.4)
22.6 (20.1)
22.1 (19.4)
22.1 (19.4)
21.4 (19.0)
21.3 (18.8)
20.8 (18.3)
20.3 (17.7)
19.9 (17.4)
19.4 (16.8)
19.1 (16.6)
18.1 (15.6)
16.1 (13.6)
23.1 (20.8)
23.0 (20.4)
22.1 (19.7)
21.8 (19.2)
21.8 (18.9)
21.0 (18.4)
20.8 (18.3)
20.5 (17.9)
20.1 (17.5)
19.4 (17.0)
18.9 (16.5)
18.9 (16.4)
18.0 (15.4)
16.1 (13.7)
22.5 (20.0)
21.9 (19.4)
21.6 (19.9)
21.1 (18.6)
21.0 (18.6)
20.4 (17.8)
20.2 (17.7)
19.7 (17.1)
19.2 (16.8)
18.8 (16.4)
18.3 (15.8)
18.2 (15.8)
17.4 (14.9)
16.1 (13.4)
21.7 (19.1)
21.1 (18.6)
20.7 (18.2)
20.2 (17.6)
20.1 (17.8)
19.4 (17.0)
19.3 (16.8)
18.9 (16.4)
18.4 (15.9)
18.0 (15.4)
17.4 (14.9)
17.4 (14.8)
16.6 (13.8)
15.0 (12.7)
20.8 (18.2)
20.4 (17.7)
19.9 (17.2)
19.4 (16.8)
19.3 (16.7)
18.7 (16.3)
18.5 (15.8)
18.1 (15.6)
17.6 (15.2)
17.1 (14.5)
16.6 (14.0)
16.4 (13.9)
15.9 (13.3)
14.1 (11.5)
10
16.6
20
50
60
100
200
400
800
1000
2000
4000
28
版权 © 2016–2017, Texas Instruments Incorporated
ADS124S06, ADS124S08
www.ti.com.cn
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
9 Detailed Description
9.1 Overview
The ADS124S06 and ADS124S08 are precision 24-bit, delta-sigma (ΔΣ) ADCs with an integrated analog front
end (AFE) to simplify precision sensor connections. The ADC provides output data rates from 2.5 SPS to
4000 SPS for flexibility in resolution and data rates over a wide range of applications. The low-noise and low-drift
architecture make these devices suitable for precise measurement of low-voltage sensors, such as load cells and
temperature sensors.
The ADS124S0x incorporate several features that simplify precision sensor measurements. Key integrated
features include:
•
•
•
•
•
•
•
•
Low-noise, CMOS PGA with integrated signal fault detection
Low-drift, 2.5-V voltage reference
Two sets of buffered external reference inputs with reference voltage level detection
Dual, matched, sensor-excitation current sources (IDACs)
Internal 4.096-MHz oscillator
Temperature sensor
Four general-purpose input/output pins (GPIOs)
A low-resistance switch (when connected to AVSS) can be used to disconnect bridge sensors to reduce
current consumption
As described in the Functional Block Diagram section, these devices provide 13 (ADS124S08) or 7
(ADS124S06) analog inputs that are configurable as either single-ended inputs, differential inputs, or any
combination of the two. Many of the analog inputs have additional features as programmed by the user. The
analog inputs can be programmed to enable the following extended features:
•
•
•
•
Two sensor excitation current sources: all analog input pins (and REFP1 and REFN1 on the ADS124S06)
Sensor biasing voltage (VBIAS): pins AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AINCOM
Four GPIO pins: AIN8, AIN9, AIN10, AIN11 (ADS124S08 only, the ADS124S06 has dedicated GPIOs)
Sensor burn-out current sources: analog input pins selected for ADC input
Following the input multiplexer (MUX), the ADC features a high input-impedance, low-noise, programmable gain
amplifier (PGA), eliminating the need for an external amplifier. The PGA gain is programmable from 1 to 128 in
binary steps. The PGA can be bypassed to allow the input range to extend 50 mV below ground or above
supply. The PGA has output voltage monitors to verify the integrity of the conversion result.
An inherently stable delta-sigma modulator measures the ratio of the input voltage to the reference voltage to
provide the ADC result. The ADC operates with the internal 2.5-V reference, or with up to two external reference
inputs. The external reference inputs can be continuously monitored for low (or missing) voltage. The REFOUT
pin provides the buffered 2.5-V internal voltage reference output that can be used to bias external circuitry.
The digital filter provides two filter modes, sinc3 and low-latency, allowing optimization of settling time and line-
cycle rejection. The third-order sinc filter offers simultaneous 50-Hz and 60-Hz line-cycle rejection at data rates of
2.5 SPS, 5 SPS, and 10 SPS, 50-Hz rejection at data rates of 16.6 SPS and 50 SPS, and 60-Hz rejection at data
rates of 20 SPS and 60 SPS. The low-latency filter provides settled data with 50-Hz and 60-Hz line-cycle
rejection at data rates of 2.5 SPS, 5 SPS, 10 SPS, and 20 SPS, 50-Hz rejection at data rates of 16.6 SPS and
50 SPS, and 60-Hz rejection at a data rate of 60 SPS.
Two programmable excitation current sources provide bias to resistive sensors [such as resistance temperature
detectors (RTDs) or thermistors]. The ADC integrates several system monitors for read back, such as
temperature sensor and supply monitors. Four GPIO pins are available as either dedicated pins (ADS124S06) or
combined with analog input pins (ADS124S08).
The ADS124S0x system clock is either provided by the internal low-drift, 4.096-MHz oscillator or an external
clock source on the CLK input.
版权 © 2016–2017, Texas Instruments Incorporated
29
REFN0 REFP0 REFCOM REFOUT
DVDD
ADS124S06, ADS124S08
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
www.ti.com.cn
Overview (接下页)
The SPI-compatible serial interface is used to read the conversion data and also to configure and control the
ADC. The serial interface consists of four signals: CS, SCLK, DIN, and DOUT/DRDY. The conversion data are
provided with an optional CRC code for improved data integrity. The dual function DOUT/DRDY output indicates
when conversion data are ready and also provides the data output. The serial interface can be implemented with
as little as three connections by tying CS low. Start ADC conversions with either the START/SYNC pin or with
commands. The ADC can be programmed for a continuous conversion mode or to perform single-shot
conversions.
The AVDD analog supply operates with bipolar supplies from ±1.5 V to ±2.625 V or with a unipolar supply from
2.7 V to 5.25 V. For unipolar-supply operation, use the VBIAS voltage to bias isolated (floating) sensors. The
digital supplies operate with unipolar supplies only. The DVDD digital power supply operates from 2.7 V to 3.6 V
and the IOVDD supply operates from DVDD to 5.25 V.
9.2 Functional Block Diagram
AVSS-SW
AVDD
IOVDD
Burnout
Detect
2.5-V
Reference
ADS124S06
ADS124S08
Reference
Mux
Excitation
Current
AINCOM
AIN0
Sources
Reference
Detection
AIN1
Reference
Buffers
AIN2
VBIAS
START/SYNC
RESET
CS
AIN3
AIN4
Configurable
Serial
Interface
and
24-Bit ûꢀ
ADC
Input
Mux
Digital
Filter
PGA
AIN5
SCLK
AIN6 / REFP1
AIN7 / REFN1
AIN8 / GPIO0
AIN9 / GPIO1
Control
DIN
PGA Rail
Detection
DOUT/DRDY
DRDY
System-, Self-
Calibration
Power Supplies
AIN10 / GPIO2
AIN11 / GPIO3
Temperature
Sensor
4.096-MHz
Oscillator
CLK
ADS124S08
only
Burnout
Detect
AVSS
DGND
Copyright © 2016, Texas Instruments Incorporated
30
版权 © 2016–2017, Texas Instruments Incorporated
ADS124S06, ADS124S08
www.ti.com.cn
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
9.3 Feature Description
9.3.1 Multiplexer
The ADS124S0x contains a flexible input multiplexer; see 图 49. Select any of the six (ADS124S06) or 12
(ADS124S08) analog inputs as the positive or negative input for the PGA using the MUX_P[3:0] and MUX_N[3:0]
bits in the input multiplexer register (02h). In addition, AINCOM can be selected as the positive or negative PGA
input. AINCOM is treated as a regular analog input, as is AINx. Use AINCOM in single-ended measurement
applications as the common input for the other analog inputs.
The multiplexer also routes the excitation current sources to drive resistive sensors (bridges, RTDs, and
thermistors) and can provide bias voltages for unbiased sensors (unbiased thermocouples for example) to analog
input pins.
The ADS124S0x also contain a set of system monitor functions measured through the multiplexer. The inputs
can be shorted together at mid-supply [(AVDD + AVSS) / 2] to measure and calibrate the input offset of the
analog front-end and the ADC. The system monitor also includes a temperature sensor that provides a
measurement of the device temperature. The system monitor can also measure the analog and digital supplies,
measuring [(AVDD – AVSS) / 4] for the analog supply or DVDD / 4 for the digital supply. Finally, the system
monitor contains a set of burn-out current sources that pull the inputs to either supply if the sensor has burned
out and has a high impedance so that the ADC measures a full-scale reading.
The multiplexer implements a break-before-make circuit. When changing the multiplexer channels using the
MUX_P[3:0] and MUX_N[3:0] bits, the device first disconnects the PGA inputs from the analog inputs and
connects them to mid-supply for 2 · tCLK. In the next step, the PGA inputs connect to the selected new analog
input channels. This break-before-make behavior ensures the ADC always starts from a known state and that the
analog inputs are not momentarily shorted together.
Electrostatic discharge (ESD) diodes to AVDD and AVSS protect the inputs. To prevent the ESD diodes from
turning on, the absolute voltage on any input must stay within the range provided by 公式 3:
AVSS – 0.3 V < V(AINx) < AVDD + 0.3 V
(3)
External Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see
the Absolute Maximum Ratings table). Overdriving an unselected input on the device can affect conversions
taking place on other input pins.
版权 © 2016–2017, Texas Instruments Incorporated
31
ADS124S06, ADS124S08
ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
www.ti.com.cn
Feature Description (接下页)
AVDD
AVDD
IDAC1
IDAC2
(1)
VBIAS
VBIAS
VBIAS
VBIAS
VBIAS
VBIAS
VBIAS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
(AVDD + AVSS) / 2
AINCOM
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AVDD
AVDD
Temperature
Diode
(2)
(AVDD Þ AVSS) • (5 / 8)
(AVDD Þ AVSS) • (3 / 8)
(3)
DVDD • (4 / 12)
DVDD • (1 / 12)
AVDD
Burn-Out Current Source
AINP
To ADC
PGA
AINN
Burn-Out Current Source
AVSS
ADS124S08 Only
Copyright © 2016, Texas Instruments Incorporated
(1) AINP and AINN are connected together to (AVDD + AVSS) / 2 for offset measurement.
(2) Measurement for the analog supply equivalent to (AVDD – AVSS) / 4.
(3) Measurement for the analog supply equivalent to DVDD / 4.
图 49. Analog Input Multiplexer
32
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Feature Description (接下页)
9.3.2 Low-Noise Programmable Gain Amplifier
The ADS124S06 and ADS124S08 feature a low-drift, low-noise, high input impedance programmable gain
amplifier (PGA). 图 50 shows a simplified diagram of the PGA. The PGA consists of two chopper-stabilized
amplifiers (A1 and A2) and a resistor feedback network that sets the gain of the PGA. The PGA input is equipped
with an electromagnetic interference (EMI) filter and an antialiasing filter on the output.
250 ꢀ
+
AINP
A1
RF
16 pF
2.5 kꢀ
320 pF
RG
ADC
RF
A2
2.5 kꢀ
250 ꢀ
+
AINN
16 pF
图 50. Simplified PGA Diagram
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128 using the GAIN[2:0] bits in the gain setting register
(03h). Gain is changed inside the device using a variable resistor, RG. The differential full-scale input voltage
range (FSR) of the PGA is defined by the gain setting and the reference voltage used, as shown in 公式 4:
FSR = ±VREF / Gain
(4)
表 9 shows the corresponding full-scale ranges when using the internal 2.5-V reference.
表 9. PGA Full-Scale Range
GAIN SETTING
FSR
1
2
±2.5 V
±1.25 V
±0.625 V
±0.313 V
±0.156 V
±0.078 V
±0.039 V
±0.020 V
4
8
16
32
64
128
The PGA must be enabled with the PGA_EN[1:0] bits of the gain setting register (03h). Setting these bits to 00
powers down and bypasses the PGA. A setting of 01 enables the PGA. The 10 and 11 settings are reserved and
must not be written to the device.
With the PGA enabled, gains 64 and 128 are established in the digital domain. When the device is set to 64 or
128, the PGA is set to a gain of 32, and additional gain is established with digital scaling. The input-referred
noise does still improve compared to the gain = 32 setting because the PGA is biased with a higher supply
current to reduce noise.
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9.3.2.1 PGA Input-Voltage Requirements
As with many amplifiers, the PGA has an absolute input voltage range requirement that cannot be exceeded.
The maximum and minimum absolute input voltages are limited by the voltage swing capability of the PGA
output. The specified minimum and maximum absolute input voltages (VAINP and VAINN) depend on the PGA gain,
the maximum differential input voltage (VINMAX), and the tolerance of the analog power-supply voltages (AVDD
and AVSS). Use the maximum voltage expected in the application for VINMAX. The absolute positive and negative
input voltages must be within the specified range, as shown in 公式 5:
AVSS + 0.15 V + |VINMAX| · (Gain – 1) / 2 < VAINP, VAINN < AVDD – 0.15 V – |VINMAX| · (Gain – 1) / 2
where
•
•
VAINP, VAINN = absolute input voltage
VINMAX = VAINP – VAINN = maximum differential input voltage
(5)
As mentioned in the previous section, PGA gain settings of 64 and 128 are scaled in the digital domain and are
not implemented with the amplifier. When using the PGA in gains of 64 and 128, set the gain in 公式 5 to 32 to
calculate the absolute input voltage range.
The relationship between the PGA input to the PGA output is shown graphically in 图 51. The PGA output
voltages (VOUTP, VOUTN) depend on the PGA gain and the input voltage magnitudes. For linear operation, the
PGA output voltages must not exceed AVDD – 0.15 V or AVSS + 0.15 V. Note that the diagram depicts a
positive differential input voltage that results in a positive differential output voltage.
PGA Input
PGA Output
AVDD
AVDD œ 0.15 V
VOUTP = VAINP + VIN ‡ (Gain œ 1) / 2
VAINP
VIN = VAINP œ VAINN
VAINN
VOUTN = VAINN œ VIN ‡ (Gain œ 1) / 2
AVSS + 0.15 V
AVSS
图 51. PGA Input/Output Range
Download the ADS1x4S0x design calculator from www.ti.com. This calculator can be used to determine the input
voltage range of the PGA.
9.3.2.2 PGA Rail Flags
The PGA rail flags (FL_P_RAILP, FL_P_RAILN, FL_N_RAILP, and FL_N_RAILN) in the status register (01h)
indicate if the positive or negative output of the PGA is closer to the analog supply rails than 150 mV. Enable the
PGA output rail detection circuit using the FL_RAIL_EN bit in the excitation current register 1 (06h). A flag going
high indicates that the PGA is operating outside the linear operating or absolute input voltage range. PGA rail
flags are discussed in more detail in the PGA Output Voltage Rail Monitors section.
9.3.2.3 Bypassing the PGA
At a gain of 1, the device can be configured to disable and bypass the low-noise PGA. Disabling the PGA lowers
the overall power consumption and also removes the restrictions of 公式 5 for the input voltage range. If the PGA
is bypassed, the ADC absolute input voltage range extends beyond the AVDD and AVSS power supplies,
allowing input voltages at or below ground. The absolute input voltage range when the PGA is bypassed is
shown in 公式 6:
AVSS – 0.05 V < VAINP, VAINN < AVDD + 0.05 V
(6)
34
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In order to measure single-ended signals that are referenced to AVSS (AINP = VIN, AINN = AVSS), the PGA must
be bypassed. The PGA is bypassed and powered down by setting the PGA_EN[1:0] bits to 00 in the gain setting
register (03h).
For signal sources with high output impedance, external buffering may still be necessary. Note that active buffers
introduce noise and also introduce offset and gain errors. Consider all of these factors in high-accuracy
applications.
9.3.3 Voltage Reference
The devices require a reference voltage for operation. The ADS124S0x offers an integrated low-drift 2.5-V
reference. For applications that require a different reference voltage value or a ratiometric measurement
approach, the ADS124S08 offers two differential reference input pairs (REFP0, REFN0 and REFP1, REFN1).
The differential reference inputs allow freedom in the reference common-mode voltage. REFP0 and REFN0 are
dedicated reference inputs, whereas REFP1 and REFN1 are shared with inputs AIN6 and AIN7 (respectively) on
the ADS124S08. The specified external reference voltage range is 0.5 V to AVDD. The reference voltage is
shown in 公式 7, where V(REFPx) and V(REFNx) are the absolute positive and absolute negative reference voltages.
VREF = V(REFPx) – V(REFNx)
(7)
The polarity of the reference voltage internal to the ADC must be positive. The magnitude of the reference
voltage together with the PGA gain establishes the ADC full-scale differential input range as defined by
FSR = ±VREF / Gain.
图 52 shows the block diagram of the reference multiplexer. The ADC reference multiplexer selects between the
internal reference and two external references (REF0 and REF1). The reference multiplexer is programmed with
the REFSEL[1:0] bits in the reference control register (05h). By default, the external reference pair REFP0,
REFN0 is selected.
REFSEL[1:0] bits of REF register
00 = REFP0, REFN0
01 = REFP1, REFN1
10 = Internal 2.5-V reference
11 = Reserved
00
01
10
REFP0
REFP1
VREFP
REFOUT
Internal
2.5 V
Reference
Reference
Detection
1 mF(1)
VREFN
00
REFN0
REFN1
01
10
REFP_BUF bit of REF register
0 = Enabled
REFCOM
1 = Disabled
REFCON[1:0] bits of REF register
00 = Internal reference off
01 = Internal reference on;
off in power-down mode
10 = Internal reference always on
11 = Reserved
REFN_BUF bit of REF register
0 = Enabled
1 = Disabled
ADC
(1) The internal reference requires a minimum 1-µF capacitor connected from REFOUT to REFCOM.
图 52. Reference Multiplexer Block Diagram
The ADC also contains an integrated reference voltage monitor. This monitor provides continuous detection of a
low or missing reference during the conversion cycle. The reference monitor flags (FL_REF_L0 and FL_REF_L1)
are set in the STATUS byte and described in the Reference Monitor section.
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9.3.3.1 Internal Reference
The ADC integrates a precision, low-drift, 2.5-V reference. The internal reference is enabled by setting
REFCON[1:0] to 10 (reference is always on) or 01 (reference is on, but powers down in power-down mode) in
the reference control register (05h). By default, the internal voltage reference is powered down. To select the
internal reference for use with the ADC, set the REFSEL[1:0] bits to 10. The REFOUT pin provides a buffered
reference output voltage when the internal reference voltage is enabled. The negative reference output is the
REFCOM pin, as shown in 图 52. Connect a capacitor in the range of 1 μF to 47 μF between REFOUT and
REFCOM. Larger capacitor values help filter more noise at the expense of a longer reference start-up time.
The capacitor is not required if the internal reference is not used. However, the internal reference must be
powered on if using the IDACs.
The internal reference requires a start-up time that must be accounted for before starting a conversion, as shown
in 表 10.
表 10. Internal Reference Settling Time
REFOUT CAPACITOR
SETTLING ERROR
0.01%
SETTLING TIME (ms)
4.5
5.9
4.9
6.3
5.5
7.0
1 µF
0.001%
0.01%
10 µF
47 µF
0.001%
0.01%
0.001%
9.3.3.2 External Reference
The ADS124S0x provides two external reference inputs selectable through the reference multiplexer. The
reference inputs are differential with independent positive and negative inputs. REFP0 and REFN0 or REFP1
and REFN1 can be selected as the ADC reference. REFP1 and REFN1 are shared inputs with analog pins AIN6
and AIN7 in the ADS124S08.
Without buffering, the reference input impedance is approximately 250 kΩ. The reference input current can lead
to possible errors from either high reference source impedance or through reference input filtering. To reduce the
input current, use either internal or external reference buffers. In most applications external reference buffering is
not necessary.
Connect a 100-nF bypass capacitor across the external reference input pins. Follow the specified absolute and
differential reference voltage requirements.
9.3.3.3 Reference Buffers
The device has two individually selectable reference input buffers to lower the reference input current. Use the
REFP_BUF and REFN_BUF bits in the reference control register (05h) to enable or disable the positive and
negative reference buffers respectively. Note that these bits are active low. Writing a 1 to REFP_BUF or
REFN_BUF disables the reference buffers.
The reference buffers are recommended to be disabled when the internal reference is selected for
measurements. When the external reference input is at the supply voltage (REFPx at AVDD or REFNx at AVSS),
the reference buffer is recomended to be disabled.
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9.3.4 Clock Source
The ADS124S0x system clock is either provided by the internal low-drift 4.096-MHz oscillator or an external clock
source on the CLK input. Use the CLK bit within the data rate register (04h) to select the internal
4.096-MHz oscillator or an external clock source.
The device defaults to using the internal oscillator. If the device is reset (from either the RESET pin, or the
RESET command), then the clock source returns to using the internal oscillator even if an external clock is
selected.
9.3.5 Delta-Sigma Modulator
A delta-sigma (ΔΣ) modulator is used in the devices to convert the analog input voltage into a pulse code
modulated (PCM) data stream. The modulator runs at a modulator clock frequency of fMOD = fCLK / 16, where fCLK
is either provided by the internal 4.096-MHz oscillator or the external clock source.
9.3.6 Digital Filter
The devices offer digital filter options for both filtering and decimation of the digital data stream coming from the
delta-sigma modulator. The implementation of the digital filter is determined by the data rate and filter mode
setting. 图 53 shows the digital filter implementation. Choose between a third-order sinc filter (sinc3) and a low-
latency filter (low-latency filter with multiple components) using the FILTER bit in the data rate register (04h).
fCLK = 4.096 MHz
Sinc3 Filter
4000, 2000, 1000, 800, 400, 200,
fCLK / 16
Sinc3
100, 60, 50, 20, 16.6, 10, 5, 2.5 SPS
Filter
fMOD = 256 kHz
Sinc1
Filter
Low-Latency Filter
20, 10, 5, 2.5 SPS
LL2
Filter
ADC
ADC Data
Output
Sinc1
Filter
400, 200, 100, 60, 50, 16.6 SPS
4000, 2000, 1000, 800 SPS
LL1
Filter
FILTER Bit of
DR[3:0] Bits of
DATARATE Register
DATARATE Register
0 = Sinc3 Filter
0000 = 2.5 SPS
1000 = 200 SPS
1001 = 400 SPS
1010 = 800 SPS
1011 = 1000 SPS
1100 = 2000 SPS
1101 = 4000 SPS
1110 = 4000 SPS
1111 = Reserved
1 = Low-Latency filter
0001 = 5 SPS
0010 = 10 SPS
0011 = 16.6 SPS
0100 = 20 SPS
0101 = 50 SPS
0110 = 60 SPS
0111 = 100 SPS
NOTE: LL filter = low-latency filter.
图 53. Digital Filter Architecture
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Regardless of the FILTER type setting, the oversampling ratio is the same for each given data rate, meaning that
the device requires a set number of modulator clocks to output a single ADC conversion data. The output data
rate is selected using the DR[3:0] bits in the data rate register and is shown in 表 11.
表 11. ADC Data Rates and Digital Filter Oversampling Ratios
NOMINAL DATA RATE
(SPS)(1)
DATA RATE REGISTER
DR[3:0]
OVERSAMPLING
RATIO(2)
2.5
5
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
102400
51200
25600
15360
12800
5120
4264
2560
1280
640
10
16.6
20
50
60
100
200
400
800
1000
2000
4000
320
256
128
64
(1) Valid for the internal oscillator or an external 4.096-MHz clock.
(2) The oversampling ratio is fMOD divided by the data rate; fMOD = fCLK / 16.
9.3.6.1 Low-Latency Filter
The low-latency filter is selected when the FILTER bit is set to 0 in the data rate register (04h). The filter is a
finite impulse response (FIR) filter that provides settled data, given that the analog input signal has settled to the
final value before the conversion is started. The low-latency filter is especially useful when multiple channels
must be scanned in minimal time.
9.3.6.1.1 Low-Latency Filter Frequency Response
The low-latency filter provides many data rate options for rejecting 50-Hz and 60-Hz line cycle noise. At data
rates of 2.5 SPS, 5 SPS, 10 SPS, and 20 SPS, the filter rejects both 50-Hz and 60-Hz line frequencies. At data
rates of 16.6 SPS and 50 SPS, the filter has a notch at 50 Hz. At a 60-SPS data rate, the filter has a notch at
60 Hz.
For detailed frequency response plots showing line cycle noise rejection, download the ADS1x4S0x design
calculator from www.ti.com.
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图 54 to 图 68 show the frequency response of the low-latency filter for different data rates. 表 12 gives the
bandwidth of the low-latency filter for each data rate.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
Frequency (Hz)
Frequency (Hz)
fCLK = 4.096 MHz, low-latency filter
fCLK = 4.096 MHz, low-latency filter
图 54. Low-Latency Filter Frequency Response,
图 55. Low-Latency Filter Frequency Response,
Data Rate = 2.5 SPS
Data Rate = 5 SPS
0
-20
-40
-60
0
-20
-40
-60
-80
-100
-120
0
10
20
30
40
50
60
70
80
90 100
0
20
40
60
80
100
120
140
160
Frequency (Hz)
Frequency (Hz)
fCLK = 4.096 MHz, low-latency filter
fCLK = 4.096 MHz, low-latency filter
图 56. Low-Latency Filter Frequency Response,
图 57. Low-Latency Filter Frequency Response,
Data Rate = 10 SPS
Data Rate = 16.6 SPS
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
20
40
60
80 100 120 140 160 180 200
Frequency (Hz)
40
45
50
55
60
65
70
Frequency (Hz)
fCLK = 4.096 MHz, low-latency filter
fCLK = 4.096 MHz, low-latency filter
图 58. Low-Latency Filter Frequency Response,
图 59. Low-Latency Filter Frequency Response,
Data Rate = 20 SPS
Data Rate = 20 SPS, Zoomed to 50 Hz and 60 Hz
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0
-20
-40
-60
0
-20
-40
-60
0
50
100
150
200
250
300
350
400
0
0
0
100
200
300
400
Frequency (Hz)
Frequency (Hz)
fCLK = 4.096 MHz, low-latency filter
fCLK = 4.096 MHz, low-latency filter
图 60. Low-Latency Filter Frequency Response,
图 61. Low-Latency Filter Frequency Response,
Data Rate = 50 SPS
Data Rate = 60 SPS
0
-20
-40
-60
0
-20
-40
-60
400
800
1200
1600
2000
0
200
400
600
800
1000
Frequency (Hz)
Frequency (Hz)
fCLK = 4.096 MHz, low-latency filter
fCLK = 4.096 MHz, low-latency filter
图 63. Low-Latency Filter Frequency Response,
图 62. Low-Latency Filter Frequency Response,
Data Rate = 200 SPS
Data Rate = 100 SPS
0
-20
-40
-60
-80
0
-20
-40
-60
-80
0
500 1000 1500 2000 2500 3000 3500 4000
Frequency (Hz)
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (Hz)
fCLK = 4.096 MHz, low-latency filter
fCLK = 4.096 MHz, low-latency filter
图 64. Low-Latency Filter Frequency Response,
图 65. Low-Latency Filter Frequency Response,
Data Rate = 400 SPS
Data Rate = 800 SPS
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0
0
-20
-20
-40
-60
-40
-60
-80
-100
-80
0
0
4000
8000
12000
16000
20000
2000
4000
6000
8000
10000
Frequency (Hz)
Frequency (Hz)
fCLK = 4.096 MHz, low-latency filter
fCLK = 4.096 MHz, low-latency filter
图 67. Low-Latency Filter Frequency Response,
图 66. Low-Latency Filter Frequency Response,
Data Rate = 2 kSPS
Data Rate = 1 kSPS
0
-20
-40
-60
-80
-100
0
8000
16000
24000
32000
40000
Frequency (Hz)
fCLK = 4.096 MHz, low-latency filter
图 68. Low-Latency Filter Frequency Response,
Data Rate = 4 kSPS
表 12. Low-Latency Filter Bandwidth
NOMINAL DATA RATE (SPS)(1)
–3-dB BANDWIDTH (Hz)(1)
2.5
5
1.1
2.2
10
4.7
16.6
20
7.4
13.2
22.1
26.6
44.4
89.9
190
574
718
718
718
50
60
100
200
400
800
1000
2000
4000
(1) Valid for the internal oscillator or an external 4.096-MHz clock. Scales proportional with fCLK
.
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The low-latency filter notches and output data rate scale proportionally with the clock frequency. For example, a
notch that appears at 20 Hz when using a 4.096-MHz clock appears at 10 Hz if a 2.048-MHz clock is used. Note
that the internal oscillator can vary over temperature as specified in the Electrical Characteristics table. The data
rate, conversion time, and filter notches consequently vary by the same percentage. Consider using an external
precision clock source if a digital filter notch at a specific frequency with a tighter tolerance is required.
9.3.6.1.2 Data Conversion Time for the Low-Latency Filter
The amount of time required to receive data from the ADC depends on more than just the nominal data rate of
the device. The data period also depends on the mode of operation and other configurations of the device. When
the low-latency filter is enabled, the data settles in one data period. However, a small amount of latency exists to
set up the device, calculate the conversion data from the modulator samples, and other overhead that adds time
to the conversion. For this reason, the first conversion data takes longer than subsequent data conversions.
表 13 shows the conversion times for the low-latency filter for each ADC data rate and various conversion
modes.
表 13. Data Conversion Time for the Low-Latency Filter
FIRST DATA
SECOND AND SUBSEQUENT
CONVERSIONS FOR CONTINUOUS
CONVERSION MODE
FOR CONTINUOUS CONVERSION MODE
NOMINAL
DATA RATE(1)
(SPS)
OR SINGLE-SHOT CONVERSION MODE(2)
NUMBER OF
NUMBER OF
ms(3)
ms(4)
tMOD PERIODS(3)
tMOD PERIODS(4)
2.5
5
406.504
206.504
106.504
60.254
56.504
20.156
16.910
10.156
5.156
104065
52865
27265
15425
14465
5160
4329
2600
1320
680
400
200
100
60
102400
51200
25600
15360
12800
5120
4264
2560
1280
640
10
16.6
20
50
50
20
60
16.66
10
100
200
400
800
1000
2000
4000
5
2.656
2.5
1.25
1
1.406
360
320
1.156
296
256
0.656
168
0.5
0.25
128
0.406
104
64
(1) Valid for the internal oscillator or an external 4.096-MHz clock. Scales proportional with fCLK
.
(2) Conversions start at the rising edge of the START/SYNC pin or on the seventh SCLK falling edge for a START command.
(3) Time does not include the programmable delay set by the DELAY[2:0] bits in the gain setting register. The default setting is an additional
14 · tMOD, where tMOD = tCLK · 16.
(4) Subsequent readings in continuous conversion mode do not have the programmable delay time.
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9.3.6.2 Sinc3 Filter
The sinc3 digital filter is selected when the FILTER bit is set to 0 in the data rate register (04h). Compared to the
low-latency filter, the sinc3 filter has improved noise performance but has a three-cycle latency in the data output.
9.3.6.2.1 Sinc3 Filter Frequency Response
The low-pass nature of the sinc3 filter establishes the overall frequency response. The frequency response is
given by 公式 8:
3
≈
∆
«
’
÷
◊
16 pf ∂OSR
sin
fCLK
H(f)
= HSinc3(f) =
≈
∆
«
’
16 pf
OSRì sin
÷
fCLK ◊
where
•
•
•
f = signal frequency
fCLK = ADC clock frequency
OSR = oversampling ratio
(8)
The sinc3 filter offers simultaneous 50-Hz and 60-Hz line cycle rejection at data rates of 2.5 SPS, 5 SPS, and
10 SPS. The sinc3 filter offers only 50-Hz rejection at data rates of 16.6 SPS and 50 SPS, and only 60-Hz
rejection at data rates of 20 SPS and 60 SPS. The sinc3 digital filter response scales with the data rate and has
notches at multiples of the data rate. 图 69 shows the sinc3 digital filter frequency response normalized to the
data rate. As an example, 图 70 shows the frequency response when the data rate is set to 10 SPS, and 图 71
illustrates a close-up of the filter rejection of 50-Hz and 60-Hz line frequencies. For more detailed frequency
response plots, download the ADS1x4S0x design calculator from www.ti.com.
表 14 gives the bandwidth of the sinc3 filter for each data rate.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
1
2
3
4
5
6
7
8
9
10
0
10
20
30
40
50
60
70
80
90 100
Normalized Frequency
Frequency (Hz)
Frequency normalized to data rate, sinc3 filter
fCLK = 4.096 MHz, sinc3 filter
图 69. Sinc3 Filter Frequency Response,
图 70. Sinc3 Filter Frequency Response,
Normalized to Data Rate
Data Rate = 10 SPS
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0
-20
-40
-60
-80
-100
-120
-140
40
45
50
55
60
65
70
Frequency (Hz)
fCLK = 4.096 MHz, sinc3 filter
图 71. Sinc3 Filter Frequency Response,
Data Rate = 10 SPS, Zoomed to 50 Hz and 60 Hz
表 14. Sinc3 Filter –3-dB Bandwidth
NOMINAL DATA RATE (SPS)(1)
–3-dB BANDWIDTH (Hz)(1)
2.5
5
0.65
1.3
10
2.6
16.6
20
4.4
5.2
50
13.1
15.7
26.2
52.3
105
209
262
523
1046
60
100
200
400
800
1000
2000
4000
(1) Valid for the internal oscillator or an external 4.096-MHz clock. Scales proportional with fCLK
.
As mentioned in the previous section, filter notches and output data rate scale proportionally with the clock
frequency and the internal oscillator can change frequency with temperature.
44
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9.3.6.2.2 Data Conversion Time for the Sinc3 Filter
Similar to the low-latency filter, the sinc3 filter requires different amounts of time to complete a conversion. By
nature, the sinc3 filter normally takes three conversion to settle. In both single-shot conversion mode and
continuous conversion mode, the first two conversions are suppressed so that only settled data are output by the
ADC.
表 15 shows the conversion times for the sinc3 filter for each ADC data rate and various conversion modes.
表 15. Data Conversion Time for the Sinc3 Filter
FIRST DATA FOR
SECOND AND SUBSEQUENT
CONVERSIONS FOR CONTINUOUS
CONVERSION MODE
CONTINUOUS CONVERSION MODE OR
NOMINAL DATA RATE(1)
(SPS)
SINGLE-SHOT CONVERSION MODE(2)
NUMBER OF
NUMBER OF
ms(3)
ms(4)
tMOD PERIODS(3)
tMOD PERIODS(4)
2.5
5
1200.254
600.254
300.254
180.254
150.254
60.254
50.223
30.254
15.254
7.754
307265
153665
76865
46145
38465
15425
12857
7745
400
200
100
60
102400
51200
25600
15360
12800
5120
4264
2560
1280
640
10
16.6
20
50
50
20
60
16.66
10
100
200
400
800
1000
2000
4000
3905
5
1985
2.5
1.25
1
4.004
1025
320
3.156
808
256
1.656
424
0.5
0.25
128
0.906
232
64
(1) Valid for the internal oscillator or an external 4.096-MHz clock. Scales proportional with fCLK
.
(2) Conversions start at the rising edge of the START/SYNC pin or on the seventh SCLK falling edge for a START command.
(3) Time does not include the programmable delay set by the DELAY[2:0] bits in the gain setting register. The default setting is an additional
14 · tMOD, where tMOD = tCLK · 16.
(4) Subsequent readings in continuous conversion mode do not have the programmable delay time.
9.3.6.3 Note on Conversion Time
Each data period consists of time required for the modulator to sample the analog inputs. However, there is
additional time required before the samples become an ADC conversion result. First, there is a programmable
conversion delay (described in the Programmable Conversion Delay section) that is added before the conversion
starts. This delay allows for additional settling time for input filtering on the analog inputs and for the antialiasing
filter after the PGA. The default programmable conversion delay is 14 · tMOD. Also, overhead time is needed to
convert the modulator samples into an ADC conversion result. This overhead time includes any necessary offset
or gain compensation after the digital filter accumulates a data result.
The first conversion when the device is in continuous conversion mode (just as in single-shot conversion mode)
includes the programmable conversion delay, the modulator sampling time, and the overhead time. The second
and subsequent conversions are the normal data period (period as given by the inverse of the data rate).
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图 72 shows the time sequence for the ADC in both continuous conversion and single-shot conversion modes.
The sequence is the same regardless of the filter setting. However, when the low-latency filter settles for each
data, the sinc3 filter does not settle until the third data.
Single-shot conversion mode: Low-Latency filter
Conversion
start(1)
Data
ready
Programmable delay
Modulator sampling
ADC overhead
Sampling for
first data
DRDY
Single-shot conversion mode: Sinc3 Filter
Conversion
start(1)
Data not
settled
Data not
settled
Filter settled
First data ready(2)
Sampling for
first data.
Sampling for
second data.
Sampling for
third data.
DRDY
Continuous conversion mode: Low-Latency or Sinc3 Filter
Conversion
start(1)
First
Second
data ready
Third data
ready
Fourth data
ready
data ready(3)
Sampling for
first data.
Sampling for
second data.
Sampling for
third data.
Continued
sampling.
Sampling for
fourth data.
Low-Latency Filter
DRDY
Sinc3 Filter
DRDY
(1) Conversions start at the rising edge of the START/SYNC pin or on the seventh SCLK falling edge for a START
command.
(2) In sinc3 filter mode, the first two data outputs are suppressed to allow for the measurement data to settle.
(3) In sinc3 filter mode, there is no overhead time for the first two data, which are not available to be read.
图 72. Single-Shot Conversion Mode and Continuous Conversion Mode Sequences
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9.3.6.4 50-Hz and 60-Hz Line Cycle Rejection
If the ADC connection leads are in close proximity to industrial motors and conductors, coupling of 50-Hz and
60-Hz power line frequencies can occur. The coupled noise interferes with the signal voltage, and can lead to
inaccurate or unstable conversions. The digital filter provides enhanced rejection of power-line-coupled noise for
data rates of 60 SPS and less. Program the filter to tradeoff data rate and conversion latency versus the desired
level of line cycle rejection. 表 16 and 表 17 summarize the ADC 50-Hz and 60-Hz line-cycle rejection based on
±1-Hz and ±2-Hz tolerance of power-line to ADC clock frequency. The best possible power-line rejection is
provided by using an accurate ADC clock.
表 16. Low-Latency Filter, 50-Hz and 60-Hz Line Cycle Rejection
LOW-LATENCY DIGITAL FILTER LINE CYCLE REJECTION (dB)
DATA RATE (SPS)(1)
50 Hz ± 1 Hz
–113.7
–111.9
–111.5
–33.8
60 Hz ± 1 Hz
–95.4
50 Hz ± 2 Hz
–97.7
60 Hz ± 2 Hz
–92.4
2.5
5
–95.4
–87.6
–81.8
10
–95.4
–85.7
–81.0
16.6
20
–20.9
–27.8
–20.8
–95.4
–95.4
–75.5
–80.5
50
–33.8
–15.5
–27.6
–15.1
60
–13.4
–35.0
–12.6
–29.0
(1) fCLK = 4.096 MHz.
表 17. Sinc3 Filter, 50-Hz and 60-Hz Line Cycle Rejection
SINC3 DIGITAL FILTER LINE CYCLE REJECTION (dB)
DATA RATE (SPS)(1)
50 Hz ± 1 Hz
–108.7
–103.2
–101.8
–101.6
–53.5
60 Hz ± 1 Hz
–113.4
–107.8
–106.4
–63.0
50 Hz ± 2 Hz
–107.2
–90.1
60 Hz ± 2 Hz
–112.1
–95.0
2.5
5
10
–84.6
–89.4
16.6
20
–83.4
–62.4
–106.1
–46.7
–53.5
–88.0
50
–101.4
–40.3
–82.9
–45.3
60
–105.1
–37.8
–87.2
(1) fCLK = 4.096 MHz.
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9.3.6.5 Global Chop Mode
The device uses a very low-drift PGA and modulator in order to provide very low input voltage offset drift.
However, a small amount of offset voltage drift sometimes remains in normal measurement. The ADC
incorporates a global chop option to reduce the offset voltage and offset voltage drift to very low levels. When the
global chop is enabled, the ADC performs two internal conversions to cancel the input offset voltage. The first
conversion is taken with normal input polarity. The ADC reverses the internal input polarity for a second
conversion. The average of the two conversions yields the final corrected result, removing the offset voltage. The
global chop mode is enabled using the G_CHOP bit in the data rate register (04h). 图 73 shows a block diagram
of the global chop implementation. The combined PGA and ADC internal offset voltage is modeled as VOFS
.
G_CHOP bit of DATARATE register
0 = Global chop off
1 = Global chop on
Chop Switch
VOFS
AIN0
AINP
AINN
-
+
Digital
Filter
Chop
C
A D
Input
MUX
ADC
Conversion Output
PGA
Control
AINCOM
图 73. ADC Global Chop Block Diagram
The first conversion result is available after the ADC takes two separate conversions with settled data. When
using the low-latency filter, data settles in a single conversion. When the global chop mode is enabled, the first
conversion result appears after a time period of approximately two conversions. When using the sinc3 filter, data
settles in three conversions. If the global chop mode is enabled, the first conversion result appears after a time
period of approximately six conversions.
In continuous conversion mode with the global chop mode enabled, subsequent conversions complete in half the
time as the first conversion completed. Data for alternating inputs are pipelined so that averaging appears on
each ADC data cycle. Conversion times using the global chop mode are given in 表 18 and 表 19.
表 18. Data Conversion Time for Global Chop Mode Using the Low-Latency Filter
FIRST DATA CONVERSION PERIOD
FOR GLOBAL CHOP MODE(2)
SECOND AND SUBSEQUENT CONVERSION
PERIODS FOR GLOBAL CHOP MODE
NOMINAL
DATA RATE(1)
(SPS)
NUMBER OF
NUMBER OF
ms(3)
ms(3)
tMOD PERIODS(3)
tMOD PERIODS(3)
2.5
5
813.008
413.008
213.008
120.508
113.008
40.313
33.820
20.313
10.313
5.313
208130
105730
54530
30850
28930
10320
8658
5200
2640
1360
720
406.504
206.504
106.504
60.254
56.504
20.156
16.910
10.156
5.156
104065
52865
27265
15425
14465
5160
4329
2600
1320
680
10
16.66
20
50
60
100
200
400
800
1000
2000
4000
2.656
2.813
1.406
360
2.313
592
1.156
296
1.313
336
0.656
168
0.813
208
0.406
104
(1) Valid for the internal oscillator or an external 4.096-MHz clock. Scales proportional with fCLK
.
(2) Conversions start at the rising edge of the START/SYNC pin or on the seventh SCLK falling edge for a START command.
(3) Time does not include the programmable delay set by the DELAY[2:0] bits in the gain setting register. Global chop mode requires two
conversions, doubling the additional time. The default setting adds an extra 28 · tMOD (where tMOD = tCLK · 16) to this column.
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表 19. Data Conversion Time for Global Chop Mode Using the Sinc3 Filter
FIRST DATA CONVERSION PERIOD
FOR GLOBAL CHOP MODE(2)
SECOND AND SUBSEQUENT CONVERSION
PERIODS FOR GLOBAL CHOP MODE
NOMINAL
DATA RATE(1)
(SPS)
NUMBER OF tMOD
NUMBER OF tMOD
ms(3)
ms(3)
PERIODS(3)
614530
307330
153730
92290
76930
30850
25714
15490
7810
PERIODS(3)
2.5
5
2400.508
1200.508
600.508
360.508
300.508
120.508
100.445
60.508
30.508
15.508
8.008
1200.254
600.254
300.254
180.254
150.254
60.254
50.223
30.254
15.254
7.754
307265
153665
76865
46145
38465
15425
12857
7745
10
16.66
20
50
60
100
200
400
800
1000
2000
4000
3905
3970
1985
2050
4.004
1025
6.313
1616
3.156
808
3.313
848
1.656
424
1.813
464
0.906
232
(1) Valid for the internal oscillator or an external 4.096-MHz clock. Scales proportional with fCLK
.
(2) Conversions start at the rising edge of the START/SYNC pin or on the seventh SCLK falling edge for a START command.
(3) Time does not include the programmable delay set by the DELAY[2:0] bits in the gain setting register. Global chop mode requires two
conversions, doubling the additional time. The default setting adds an extra 28 · tMOD (where tMOD = tCLK · 16) to this column.
In global chop mode, sequences are similar to taking consecutive single-shot conversions and swapping the
input on each conversion. Output data are averaged using the last two data read operations by the ADC with the
inputs swapped. 图 74 shows the time sequence for the ADC using global chop mode.
Global chop enabled, continuous conversion mode: Low-Latency filter
Conversion
start(1)
Inputs
First
data ready
Second
data ready
Third
data ready
Programmable delay
Modulator sampling
ADC overhead
Swapped(2)
Sampling for
positive input data
Sampling for
negative input data
Averaged for
first data
Sampling for
positive input data
Sampling for
negative input data
Averaged for
third data
Additional
sampling
Averaged for
second data(3)
Global chop enabled, continuous conversion mode: Sinc3 Filter
Data not
settled
Data not
settled
First
data ready
Second
data ready
Conversion
start(1)
Data not
settled
Inputs
Data not
settled
swapped(2)
Sampling for
positive input data
Sampling for
negative input data
Sampling for
positive input data
Continued
sampling
Sampling
Sampling
Sampling
Sampling
Averaged for
first data
Averaged for
second data(3)
(1) Conversions start at the rising edge of the START/SYNC pin or on the seventh SCLK falling edge for a START
command.
(2) When the first data are collected, the inputs are swapped.
(3) Measurements are averaged after the inputs are swapped for each conversion.
图 74. Global Chop Enabled Conversion Mode Sequences
Because the digital filter must settle after reversing the inputs, the global chop mode data rate is less than the
nominal data rate, depending on the digital filter and programmed settling delay. However, if the data rate in use
has 50-Hz and 60-Hz frequency response notches, the null frequencies remain unchanged.
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The global chop mode also reduces the ADC noise by a factor of √2 because two conversions are averaged. In
some cases, the programmable conversion delay must be increased, DELAY[2:0] in the gain setting register
(03h), to allow for settling of external components.
9.3.7 Excitation Current Sources (IDACs)
The ADS124S0x incorporates two integrated, matched current sources (IDAC1, IDAC2). The current sources
provide excitation current to resistive temperature devices (RTDs), thermistors, diodes, and other resistive
sensors that require constant current biasing. The current sources are programmable to output values between
10 μA to 2000 μA using the IMAG[3:0] bits in the excitation current register 1 (06h). Each current source can be
connected to any of the analog inputs AINx as well as the REFP1 and REFN1 inputs for the ADS124S06. Both
current sources can also be connected to the same pin. The routing of the IDACs is configured by the
I1MUX[3:0] and I2MUX[3:0] bits in the excitation current register 2 (07h). In three-wire RTD applications, the
matched current sources can be used to cancel errors caused by sensor lead resistance (see the Typical
Application section for more details). 图 75 details the IDAC connection through the input multiplexer.
I1MUX[3:0] bits of the IDACMUX register.
IDAC routing to AIN8 œ AIN11 is available
only on the ADS124S08.
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
AIN0
AIN1
AIN2
AVDD
AIN3
AIN4
AIN5
AIN6/REFP1
AIN7/REFN1
AIN8
AIN6 / REFP1
AIN7 / REFN1
AIN8
IDAC1
MUX
IDAC1
AIN9
ADS124S08 AIN9
IMAG[3:0] bits of the IDACMAG register.
0000 = Off
0001 = 10 µA
AIN10
Only
AIN10
AIN11
AIN11
AINCOM
0010 = 50 µA
AINCOM
0011 = 100 µA
0100 = 250 µA
No Connection 1101-1111
0101 = 500 µA
0110 = 750 µA
0111 = 1000 µA
1000 = 1500 µA
1001 = 2000 µA
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
AVDD
AIN6/REFP1
AIN7/REFN1
AIN8
IDAC2
MUX
IDAC2
AIN9
AIN10
AIN11
AINCOM
No Connection 1101-1111
I2MUX[3:0] bits of the IDACMUX register.
IDAC routing to AIN8 œ AIN11 is available
only on the ADS124S08.
Copyright © 2017, Texas Instruments Incorporated
图 75. IDAC Block Diagram
The internal reference must be enabled for IDAC operation. As a current source, the IDAC requires voltage
headroom to the positive supply to operate. This voltage headroom is the compliance voltage. When driving
resistive sensors and biasing resistors, take care not to exceed the compliance voltage of the IDACs, otherwise
the specified accuracy of the IDAC current may not be met. For IDAC compliance voltage specifications, see the
Electrical Characteristics table.
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9.3.8 Bias Voltage Generation
The ADS124S0x provides an internal bias voltage generator, VBIAS, that can be set to two different levels,
(AVDD + AVSS) / 2 and (AVDD + AVSS) / 12 by using the VB_LEVEL bit in the sensor biasing register (08h).
The bias voltage is internally buffered and can be established on the analog inputs AIN0 to AIN5 and AINCOM
using the VB_AINx bits in the sensor biasing register (08h). A typical use case for VBIAS is biasing unbiased
thermocouples to within the common-mode voltage range of the PGA. A block diagram of the VBIAS voltage
generator and connection diagram is shown in 图 76.
AVDD
AIN0
AIN1
AIN2
AIN3
VB_LEVEL bit of VBIAS register
0 = (AVDD + AVSS) / 2
1 = (AVDD + AVSS) / 12
6R
5R
INPUT
MUX
AIN4
(AVDD + AVSS) / 2
AIN5
AINCOM
(AVDD + AVSS) / 12
R
VB_AINx bits of VBIAS register
0 = VBIAS not connected to AINx
1 = VBIAS connected to AINx
AVSS
图 76. VBIAS Block Diagram
The start-up time of the VBIAS voltage depends on the pin load capacitance. The total capacitance includes any
capacitance connected from VBIAS to AVDD, AVSS, and ground. 表 20 lists the VBIAS voltage settling times for
various external load capacitances. Ensure the VBIAS voltage is fully settled before starting a conversion.
表 20. VBIAS Settling Time
LOAD CAPACITANCE
SETTLING TIME
280 µs
0.1 µF
1 µF
2.8 ms
10 µF
28 ms
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9.3.9 System Monitor
The ADS124S0x provides a set of system monitor functions. These functions measure the device temperature,
analog power supply, digital power supply, or use current sources to detect sensor malfunction. System monitor
functions are enabled through the SYS_MON[2:0] bits of the system control register (09h).
9.3.9.1 Internal Temperature Sensor
On-chip diodes provide temperature-sensing capability. Enable the internal temperature sensor by setting
SYS_MON[2:0] = 010 in the system control register (09h). The temperature sensor outputs a voltage proportional
to the device temperature as specified in the Electrical Characteristics table.
When measuring the internal temperature sensor, the analog inputs are disconnected from the ADC and the
output voltage of the temperature sensor is routed to the ADC for measurement using the selected PGA gain,
data rate, and voltage reference. If enabled, PGA gain must be limited to 4 for the temperature sensor
measurement to remain within the allowed absolute input voltage range of the PGA. As a result of the low device
junction-to-PCB thermal resistance (RθJB), the internal device temperature closely tracks the printed circuit board
(PCB) temperature.
9.3.9.2 Power Supply Monitors
The ADS124S0x provides a means for monitoring both the analog and digital power supply (AVDD and DVDD).
The power-supply voltages are divided by a resistor network to reduce the voltages to within the ADC input
range. The reduced power-supply voltage is routed to the ADC input multiplexer. The analog (VANLMON) and
digital (VDIGMON) power-supply readings are scaled by 公式 9 and 公式 10, respectively:
VANLMON = (AVDD – AVSS) / 4
VDIGMON = (DVDD – DGND) / 4
(9)
(10)
Enable the supply voltage monitors using the SYS_MON[2:0] bits in the system control register (09h). Setting
SYS_MON[2:0] to 011 measures VANLMON, and setting SYS_MON[2:0] to 100 measures VDIGMON
.
When the supply voltage monitor is enabled, the analog inputs are disconnected from the ADC and the PGA gain
is set to 1, regardless of the GAIN[2:0] bit values in the gain setting register (03h). Supply voltage monitor
measurements can be done with either the PGA enabled or PGA disabled via the PGA_EN[1:0] register. To
obtain valid power supply monitor readings, the reference voltage must be larger than the power-supply
measurements shown in 公式 9 and 公式 10.
9.3.9.3 Burn-Out Current Sources
To help detect a possible sensor malfunction, the ADS124S0x provides selectable current sources to function as
burn-out current sources (BOCS) using the SYS_MON[2:0] bits in the system control register (09h). Current
sources are set to values of 0.2 µA, 1 µA, and 10 µA with SYS_MON[2:0] settings of 101, 110, and 111,
respectively.
When enabled, one BOCS sources current to the selected positive analog input (AINP) and the other BOCS
sinks current from the selected negative analog input (AINN). With an open-circuit in a burned out sensor, these
BOCSs pull the positive input towards AVDD and the negative input towards AVSS, resulting in a full-scale
reading. A full-scale reading can also indicate that the sensor is overloaded or that the reference voltage is
absent. A near-zero reading can indicate a shorted sensor. Distinguishing a shorted sensor condition from a
normal reading can be difficult, especially if an RC filter is used at the inputs. The voltage drop across the
external filter resistance and the residual resistance of the multiplexer can cause the output to read a value
higher than zero.
The ADC readings of a functional sensor can be corrupted when the burn-out current sources are enabled. The
burn-out current sources are recommended to be disabled when performing the precision measurement, and
only enabling them to test for sensor fault conditions. If the global chop mode is enabled, disable this mode
before making a measurement with the burn-out current sources.
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9.3.10 Status Register
The ADS124S0x has a one-byte status register that contains flags to indicate if a fault condition has occurred.
This byte can be read out from the status register (01h), or can be prepended to each data read as the first byte
when reading data from the ADC. To prepend the STATUS byte to each conversion result, set the SENDSTAT
bit to 1 in the system control register (09h).
The STATUS byte data field and field description are found in 图 94 and 表 27. The following sections describe
various flagged fault conditions that are indicated in the STATUS byte.
Flags for the PGA output voltage rail monitors and reference monitor are set after each conversion. Reading the
STATUS byte reads the flags latched during the last conversion cycle.
9.3.10.1 POR Flag
After the power supplies are turned on, the ADC remains in reset until DVDD, IOVDD, and the analog power
supply (AVDD – AVSS) voltage exceed the respective power-on reset (POR) voltage thresholds. If a POR event
has occurred, the FL_POR flag (bit 7 of the STATUS byte) is set. This flag indicates that a POR event has
occurred and has not been cleared. This flag is cleared with a user register write to set the bit to 0. The power-on
reset is described further in the Power-On Reset section.
9.3.10.2 RDY Flag
The RDY flag indicates that the device has started up and is ready to receive a configuration change. During a
reset or POR event, the device is resetting the register map and may not be available. The RDY flag is shown
with bit 6 of the STATUS byte.
9.3.10.3 PGA Output Voltage Rail Monitors
The PGA contains an integrated output-voltage monitor. If the level of the PGA output voltage exceeds
AVDD – 0.15 V or drops below AVSS + 0.15 V, a flag is set to indicate that the output has gone beyond the
output range of the PGA. Each PGA output VOUTN and VOUTP can trigger an overvoltage or undervoltage flag,
giving a total of four flags. The PGA output voltage rail monitors are enabled with the FL_REF_EN bit of
excitation current register 1. The PGA output voltage rail monitor block diagram is shown in 图 77. If the PGA is
bypassed, then the rail monitor is still operational and is sensing the connection at the input of the ADC.
The PGA output voltage rail monitors are:
•
•
•
•
FL_P_RAILP (bit 5 of the STATUS byte): VOUTP has exceeded AVDD – 0.15 V
FL_P_RAILN (bit 4 of the STATUS byte): VOUTP dropped below AVSS + 0.15 V
FL_N_RAILP (bit 3 of the STATUS byte): VOUTN has exceeded AVDD – 0.15 V
FL_N_RAILN (bit 2 of the STATUS byte): VOUTN dropped below AVSS + 0.15 V
STATUS byte [5:2]
FL_N_RAILP FL_N_RAILN
FL_P_RAILP FL_P_RAILN
VOUTP
C
A D
ADC
PGA
VOUTN
AVDD œ 0.15 V
Latch
œ
S
Q
+
R
œ
S
R
Q
+
Supply Rail
Comparators
œ
S
R
Q
Q
+
œ
S
R
+
AVSS + 0.15 V
Conversion
Start Reset
图 77. PGA Output Voltage Rail Monitors
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图 78 shows an example of a PGA output voltage rail monitor overrange event and the respective behavior of the
flags. A fault is latched during a conversion cycle. The flags are updated (set or cleared) only at the end of a
conversion cycle.
AVDD - 0.15 V
AVSS + 0.15 V
Flag latched during
conversion cycle
Conversions (DRDY)
FL_P_RAILP bit
FL_P_RAILN bit
图 78. PGA Output Voltage Rail Monitor Timing
9.3.10.4 Reference Monitor
The user can select to continuously monitor the ADC reference inputs for a shorted or missing reference voltage.
The reference detection circuit offers two thresholds, the first threshold is 300 mV and the second threshold is
1/3 · (AVDD – AVSS). The reference detection circuit measures the differential reference voltage and sets a flag
latched after each conversion in the STATUS byte if the voltage is below the threshold. A reference voltage less
than 300 mV can indicate a potential short on the reference inputs or, in case of a ratiometric RTD measurement,
a broken wire between the RTD and the reference resistor. A reference voltage between 300 mV and 1/3 ·
(AVDD – AVSS) can indicate a broken sensor excitation wire in a 3-wire RTD setup.
Additionally, a resistor of 10 MΩ can be connected between the selected REFPx and REFNx inputs. The resistor
can be used to detect a floating reference input. With a floating input, the resistor pulls both reference inputs to
the same potential so that the reference detection circuit can detect this condition. The pull-together reference
resistor is not recommended to be continuously connected to active reference inputs. This resistor lowers the
input impedance of the reference inputs and can contribute gain error to the measurement.
The reference detection circuits must be enabled with the FL_REF_EN[1:0] bits of the reference control register
(05h). The FL_REF_L0 flag (bit 0 of the STATUS byte) indicates if the reference voltage is lower than 0.3 V. The
FL_REF_L1 flag (bit
1 of the STATUS byte) indicates if the reference voltage is lower than
1/3 · (AVDD – AVSS). A diagram of the reference detection circuit is shown in 图 79. A reference monitor fault is
latched at each conversion cycle and the flags in the status register are updated at the falling edge of DRDY.
FL_REF_EN[1:0] bits of REF register
00 = Reference monitor off
01 = 0.3 V threshold enabled
10 = 1/3 • (AVDD - AVSS) threshold enabled
11 = 0.3 V threshold and 10-Mꢀ pull-together enabled
FL_REF_L0 bit of
STATUS register
0 = no alarm
0.3 V
1 = alarm
+
S
R
Q
Q
œ
FL_REF_L1 bit of
STATUS register
0 = no alarm
REFPx
1/3 • (AVDD œ AVSS)
1 = alarm
+
+
S
R
œ
œ
10 Mꢀ
REFNx
Conversion
Start Reset
图 79. Reference Monitor Block Diagram
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9.3.11 General-Purpose Inputs and Outputs (GPIOs)
The ADS124S06 offers four dedicated general-purpose input and output (GPIO) pins, and the ADS124S08 offers
four pins (AIN8 to AIN11) that serve a dual purpose as either analog inputs or GPIOs.
Two registers control the function of the GPIO pins. Use the CON[3:0] bits of the GPIO configuration register
(11h) to configure a pin as a GPIO pin. The upper four bits (DIR[3:0]) of the GPIO data register (10h) configure
the GPIO pin as either an input or an output. The lower four bits (DAT[3:0]) of the GPIO data register contain the
input or output GPIO data. If a GPIO pin is configured as an input, the respective DAT[x] bit reads the status of
the pin; if a GPIO pin is configured as an output, write the output status to the respective DAT[x] bit. For more
information about the use of GPIO pins, see the Configuration Registers section.
图 80 shows a diagram of how these functions are combined onto a single pin. Note that when the pin is
configured as a GPIO, the corresponding logic is powered from AVDD and AVSS. When the devices are
operated with bipolar analog supplies, the GPIO outputs bipolar voltages. Care must be taken to not load the
GPIO pins when used as outputs because large currents can cause droop or noise on the analog supplies. GPIO
pins use Schmitt triggered inputs, with hysteresis to make the input more resistance to noise; see the Electrical
Characteristics table for GPIO thresholds.
AVDD
CON[3:0] bits of GPIOCON register
0 = no connect
DAT[3:0] bits of GPIODAT register
0 = VGPIO is low
1 = connect
1 = VGPIO is high
GPIO
1 of 4
Write
0
Read
GPIO[0]
GPIO[1]
GPIO[2]
0
1
AIN8
AIN9
AIN10
AIN11
GPIO Read Select
GPIO[3]
DIR[7:4] bits of GPIODAT register
0 = Output
1 = Input
GPIO logic is powered from
AVDD to AVSS
AVSS
图 80. GPIO Block Diagram
For connections of unused GPIO pins, see the Unused Inputs and Outputs section.
9.3.12 Low-Side Power Switch
A low-side power switch with low on-resistance connected between REFN0 and AVSS-SW is integrated in the
devices. This power switch can be used to reduce system power consumption in resistive bridge sensor
applications by powering down the bridge circuit between conversions. When the PSW bit in the excitation
current register 1 (06h) is set to 1, the switch closes. The switch automatically opens when the POWERDOWN
command is issued. The switch is opened by setting the PSW bit to 0. By default, the switch is open. Connect
AVSS-SW to AVSS.
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9.3.13 Cyclic Redundancy Check (CRC)
A cyclic redundancy check (CRC) is enabled by setting the CRC bit to 1 in the system control register (10h).
When CRC mode is enabled, the 8-bit CRC is appended to the conversion result. The CRC is calculated for the
24-bit conversion result and the STATUS byte when enabled.
In CRC mode, the checksum byte is the 8-bit remainder of the bitwise exclusive-OR (XOR) of the data bytes by a
CRC polynomial. For conversion data, use three data bytes. The CRC is based on the CRC-8-ATM (HEC)
polynomial: X8 + X2 + X + 1.
The nine binary coefficients of the polynomial are: 100000111. To calculate the CRC, divide (XOR operation) the
data bytes (excluding the CRC) with the polynomial and compare the calculated CRC values to the ADC CRC
value. If the values do not match, a data transmission error has occurred. In the event of a data transmission
error, read the data again.
The following list shows a general procedure to compute the CRC value:
1. Left-shift the initial 24-bit data value (32-bit data when the STATUS byte is enabled) by 8 bits, with zeros
padded to the right, creating a new 32-bit data value (the starting data value).
2. Align the MSB of the CRC polynomial (100000111) to the left-most, logic-one value of the data.
3. Perform an XOR operation on the data value with the aligned CRC polynomial. The XOR operation creates a
new, shorter-length value. The bits of the data values that are not in alignment with the CRC polynomial drop
down and append to the right of the new XOR result.
4. When the XOR result is less than 100000000, the procedure ends, yielding the 8-bit CRC value. Otherwise,
continue with the XOR operation shown in step 2, using the current data value. The number of loop iterations
depends on the value of the initial data.
9.3.14 Calibration
The ADC incorporates offset and gain calibration commands, as well as user-offset and full-scale (gain)
calibration registers to calibrate the ADC. The ADC calibration registers are 24 bits wide. Use calibration to
correct internal ADC errors or overall system errors. Calibrate by sending calibration commands to the ADC, or
by direct user calibration. In user calibration, the user calculates and writes the correction values to the
calibration registers. The ADC performs self or system-offset calibration, or a system gain calibration. Perform
offset calibration before system gain calibration. After power-on, wait for the power supplies and reference
voltage to fully settle before calibrating.
As shown in 图 81, the value of the offset calibration register is subtracted from the filter output and then
multiplied by the full-scale register value divided by 400000h. The data are then clipped to a 24-bit value to
provide the final output.
AINP
C A D
+
Output Data
Clipped to 24 bits
Digital
Filter
Final
Output
ADC
AINN
-
1/400000h
OFCAL[2:0] registers
(register addresses = 0Ch, 0Bh, 0Ah)
> 000000h: negative offset
= 000000h: no offset
< 000000h: positive offset
FSCAL[2:0] registers
(register addresses = 0Fh, 0Eh, 0Dh)
< 400000h: Gain > 1
= 400000h: Gain = 1
> 400000h: Gain < 1
图 81. ADC Calibration Block Diagram
Calibration commands cannot be used when the device is in standby mode (when the START/SYNC pin is low,
or when the STOP command is issued).
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9.3.14.1 Offset Calibration
The offset calibration word is 24 bits, consisting of three 8-bit registers, as shown in the three registers starting
with offset calibration register 1. The offset value is twos complement format with a maximum positive value
equal to 7FFFFFh, and a maximum negative value equal to 800000h. This value is subtracted from each output
reading as an offset correction. A register value equal to 000000h has no offset correction. If global chop mode is
enabled, the offset calibration register is disabled. 表 21 shows example settings of the offset register.
表 21. Offset Calibration Register Values
OFC[2:0] REGISTER VALUE
000001h
OFFSET CALIBRATED OUTPUT CODE(1)
FFFFFFh
000000h
000001h
000000h
FFFFFFh
(1) Ideal output code with shorted input, excluding ADC noise and offset voltage error.
The user can select how many samples (1, 4, 8, or 16) to average for self or system offset calibration using the
CAL_SAMP[1:0] bits in the system control register (09h). Fewer readings shorten the calibration time but also
provide less accuracy. Averaging more readings takes longer but yields a more accurate calibration result by
reducing the noise level.
Two commands can be used to perform offset calibration. SFOCAL is a self offset calibration that internally sets
the input to mid-scale using the SYS_MON[2:0] = 001 setting and takes a measurement of the offset. SYOCAL is
a system offset calibration where the user must input a null voltage to calibrate the system offset. After either
command is issued, the OFC register is updated.
After an offset calibration is performed, the device starts a new conversion and DRDY falls to indicate a new
conversion has completed.
9.3.14.2 Gain Calibration
The full-scale (gain) calibration word is 24 bits consisting of three 8-bit registers, as shown in the three registers
starting with gain calibration register 1. The gain calibration value is straight binary, normalized to a unity-gain
correction factor at a register value equal to 400000h. 表 22 shows register values for selected gain factors. Do
not exceed the PGA input range limits during gain calibration.
表 22. Gain Calibration Register Values
FSCAL[2:0] REGISTER VALUE
GAIN FACTOR
433333h
400000h
1.05
1.00
0.95
3CCCCCh
All gains of the ADS124S0x are factory trimmed to meet the gain error specified in the Electrical Characteristics
table at TA = 25°C. When the gain drift of the devices over temperature is very low, there is typically no need for
self gain calibration.
The SYGCAL command initiates a system gain calibration, where the user sets the input to full-scale to remove
gain error. After the SYGCAL is issued, the FSC register is updated. As with the offset calibration, the
CAL_SAMP[1:0] bits determine the number of samples used for a gain calibration.
As with an offset calibration, the device starts a new conversion after a gain calibration and DRDY falls to
indicate a new conversion has completed.
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9.4 Device Functional Modes
The device operates in three different modes: power-down mode, standby mode, and conversion mode. 图 82
shows a flow chart of the different operating modes and how the device transitions from one mode to another.
Power-On Reset or
Power-down
RESET pin high or
Mode(2)
RESET command?(1)
No
Reset device to
default settings
WAKEUP
Command?
Yes
Standby
Mode
Complete current
conversion(4)
No
START/SYNC
rising edge or START
Command?
Yes
Yes
START/SYNC
pin low or STOP
Command?
No
Conversion
Mode
Start new
conversion
1 = Single-Shot
conversion mode
0 = Continuous
conversion mode
Conversion
mode selection(3)
(1) Any reset (power-on, command, or pin), immediately resets the device.
(2) A POWERDOWN command aborts an ongoing conversion and immediately puts the device into power-down mode.
(3) The conversion mode is selected with the MODE bit in the data rate register.
(4) The rising edge of the START/SYNC pin or the START command starts a new conversion without completing the
current conversion.
图 82. Operating Flow Chart
9.4.1 Reset
The ADS124S0x is reset in one of three ways:
•
•
•
Power-on reset
RESET pin
RESET command
When a reset occurs, the configuration registers reset to default values and the device enters standby mode. The
device then waits for the rising edge of the START/SYNC pin or a START command to enter conversion mode.
Note that if the device had been using an external clock, the reset sets the device to use the internal oscillator as
a default configuration. See the Timing Characteristics section for reset timing information.
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Device Functional Modes (接下页)
9.4.1.1 Power-On Reset
The ADS124S0x incorporates a power-on reset circuit that holds the device in reset until all supplies reach
approximately 1.65 V. The power-on reset also ensures that the device starts operating in a known state in case
a brown-out event occurs, when the supplies have dipped below the minimum operating voltages. When the
device completes a POR sequence, the FL_POR flag in the status register is set high to indicate that a POR has
occurred.
Begin communications with the device 2.2 ms after the power supplies reach minimum operating voltages. The
only exception is polling the status register for the RDY bit. If the user polls the RDY bit, then use an SCLK rate
of half the maximum-specified SCLK rate to get a proper reading when the device is making internal
configurations. This 2.2-ms POR time is required for the internal oscillator to start up and the device to properly
set internal configurations. After the internal configurations are set, the device sets the RDY bit in the device
status register (01h). When this bit is set to 0, user configurations can be programmed into the device. 图 83
shows the power-on reset timing sequence for the device.
VPOR
DVDD, IOVDD
VPOR
All supplies reach
AVDD - AVSS
minimum operating voltage
Internal
Oscillator Startup
Internal
Configuration
Standby
Mode
FL_POR bit of
STATUS register is set to 1
RDY bit of
STATUS register is set to 0
2.2 ms
If polling for RDY during this period, SCLK
must be less than half maximum rate
图 83. Power-On Reset Timing Sequence
9.4.1.2 RESET Pin
Reset the ADC by taking the RESET pin low for a minimum of 4 · tCLK· cycles, and then returning the pin high.
After the rising edge of the RESET pin, a delay time of td(RSSC) is required before sending the first serial interface
command or starting a conversion. See the Timing Characteristics section for reset timing information.
9.4.1.3 Reset by Command
Reset the ADC by using the RESET command (06h or 07h). The command is decoded on the seventh SCLK
falling edge. After sending the RESET command, a delay time of td(RSSC) is required before sending the first serial
interface command or starting a conversion. See the Timing Characteristics section for reset timing information.
9.4.2 Power-Down Mode
Power-down mode is entered by sending the POWERDOWN command. In this mode, all analog and digital
circuitry is powered down for lowest power consumption regardless of the register settings. Only the internal
voltage reference can be configured to stay on during power-down mode in case a faster start-up time is
required. All register values retain the current settings during power-down mode. The configuration registers can
be read and written in power-down mode. A WAKEUP command must be issued in order to exit power-down
mode and to enter standby mode.
When the POWERDOWN command is issued, the device enters power-down mode 2 · tCLK after the seventh
SCLK falling edge of the command. For lowest power consumption (on DVDD and IOVDD), stop the external
clock when in power-down mode. The device does not gate the external clock when in power-down mode.
Selecting the internal oscillator before sending the POWERDOWN command is recommended.
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Device Functional Modes (接下页)
To release the device from POWERDOWN, issue the WAKEUP command to enter standby mode. The device
then waits for the rising edge of the START/SYNC pin or a START command to go into conversion mode.
When in power-down mode, the device responds to the RREG, RDATA, and WAKEUP commands. The WREG
and RESET commands can also be sent, but are ignored until a WAKEUP command is sent and the internal
oscillator resumes operation.
9.4.3 Standby Mode
The device powers up in standby mode and automatically enters this mode whenever there is no ongoing
conversion. When the STOP command is sent (or the START/SYNC pin is taken low) in continuous conversion
mode, or when a conversion completes in single-shot conversion mode, the device enters standby mode.
Standby mode offers several different options and features to lower the power consumption:
•
•
The PGA can be powered down by setting PGA_EN[1:0] to 00 in the gain setting register (03h).
The internal voltage reference can be powered down by setting REFCON[1:0] to 00 in the reference control
register (05h). This setting also turns off the IDACs.
•
•
The digital filter is held in reset state.
The clock to the modulator and digital core is gated to decrease dynamic switching losses.
If powered down in standby mode, the PGA and internal reference can require extra time to power up. Extra
delay may be required between power up of the PGA or the internal reference, and the start of conversions. In
particular, the reference power up time is dependent on the capacitance between REFOUT and REFCOM.
Calibration commands are not decoded when the device is in standby mode.
9.4.4 Conversion Modes
The ADS124S0x offers two conversion modes: continuous conversion and single-shot conversion mode.
Continuous-conversion mode converts indefinitely until stopped by the user. Single-shot conversion mode
performs one conversion after the START/SYNC pin is taken high or after the START command is sent. Use the
MODE bit in the data rate register (04h) to program the conversion mode. 图 84 shows how the START/SYNC
pin and the START command are used to control ADC conversions.
(2)
(1)
(2)
DRDY
START/SYNC Pin
SCLK
START
Command
START(3)
STOP
DIN
Conversion Mode
Standby Mode
Standby Mode
(1) DRDY rises at the first SCLK rising edge or the rising edge of the START/SYNC pin.
(2) START and STOP commands take effect 2 · tCLK after the seventh SCLK falling edge. The conversion starts 2 · tCLK
after the START/SYNC rising edge.
(3) To synchronize a conversion, the STOP command must be issued prior to the START command. STOP and START
commands can be issued without a delay between the commands.
图 84. Conversion Start and Stop Timing
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Device Functional Modes (接下页)
ADC conversions are controlled by the START/SYNC pin or by serial commands. For the device to start
converting in continuous conversion or single-shot conversion mode, a START command must be sent or the
START/SYNC pin must be taken high. If using commands to control conversions, keep the START/SYNC pin low
to avoid possible contentions between the START/SYNC pin and commands.
Conversions can be synchronized to perform a conversion at a particular time. To synchronize the conversion
with the START/SYNC pin, take the pin low. The rising edge of the START/SYNC pin starts a new conversion.
Similarly, a conversion can be synchronized using the START command. If the device is in standby mode, issue
a START command. If the device is in conversion mode, issue a STOP command followed by a START
command. The STOP and START commands can be consecutive. A new conversion starts on the seventh
SCLK falling edge of the START command.
9.4.4.1 Continuous Conversion Mode
The device is configured for continuous conversion mode by setting the MODE bit to 0 in the data rate register
(04h). A START command must be sent or the START/SYNC pin must be taken high for the device to start
converting continuously. When controlling the device with commands, hold the START/SYNC pin low. Taking the
START/SYNC pin low or sending the STOP command stops the device from converting after the currently
ongoing conversion completes, indicated by the falling edge of DRDY. The device enters standby mode
thereafter.
For information on the exact timing of single-shot conversion mode data, see 表 13 and 表 15.
9.4.4.2 Single-Shot Conversion Mode
The device is configured for single-shot conversion mode by setting the MODE bit to 1 in the data rate register
(04h). A START command must be sent or the START/SYNC pin must be taken high for the device to start a
single conversion. After the conversion completes, the device enters standby mode again. To start a new
conversion, the START command must be sent again or the START/SYNC pin must be taken low and then high
again.
When the device uses the sinc3 filter, ADC data requires three conversion cycles to settle. When the sinc3 filter is
enabled, a single-shot conversion suppresses the first two ADC conversions and provides the third conversion as
the output data so that the user receives settled data. Because three conversions are required for settled data,
the conversion time in single-shot conversion mode is approximately three times the normal data period. When
the device uses the low-latency filter, the ADC data settles in a single conversion. In single-shot conversion
mode with the low-latency filter, the data period is closer to the normal data period.
For information on the exact timing of single-shot conversion mode data, see 表 13 and 表 15.
9.4.4.3 Programmable Conversion Delay
When a new conversion is started, the ADC provides a delay before the actual start of the conversion. This timed
delay is provided to allow for the integrated analog anti-alias filter to settle. In some cases more delay is required
to allow for external settling effects. The delay time can be configured to automatically delay the start of a
conversion after a START command is sent, the START/SYNC pin is taken high, or a WREG command is sent
to change any configuration register from address 03h to 07h is issued (as described in the WREG section). The
programmable conversion delay is intended to accommodate the analog settling time on the inputs (for example,
when changing a multiplexer channel). Use the DELAY[2:0] bits in the gain setting register (03h) to program a
delay time ranging from 1 · tMOD to 4096 · tMOD (where tMOD = 16 · tCLK). The default programmable conversion
delay setting is 14 · tMOD
.
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9.5 Programming
9.5.1 Serial Interface
The ADC has an SPI-compatible, bidirectional serial interface that is used to read the conversion data as well as
to configure and control the ADC. Only SPI mode 1 (CPOL = 0, CPHA = 1) is supported. The serial interface
consists of five control lines: CS, SCLK, DIN, DOUT/DRDY, and DRDY but can be used with only four or even
three control signals. If the ADS124S08 or ADS124S06 is the only device connected to the SPI bus, then the CS
input can be tied low so that only SCLK, DIN, and DOUT/DRDY are required to communicate with the device.
9.5.1.1 Chip Select (CS)
The CS pin is an active low input that enables the ADC serial interface for communication and is useful when
multiple devices share the same serial bus. CS must be low during the entire data transaction. When CS is high,
the serial interface is reset, SCLK input activity is ignored (blocking input commands), and the DOUT/DRDY
output enters a high-impedance state. ADC conversions are not affected by the state of CS. In situations where
multiple devices are present on the bus, the dedicated DRDY pin can provide an uninterrupted monitor of the
conversion status and is not affected by CS. If the serial bus is not shared with another peripheral, CS can be
tied to DGND to permanently enable the ADC interface and DOUT/DRDY can be used to indicate conversion
status. These changes reduce the serial interface from five I/Os to three I/Os.
9.5.1.2 Serial Clock (SCLK)
The serial interface clock is a noise-filtered, Schmidt-triggered input used to clock data into and out of the ADC.
Input data to the ADC are latched on the falling SCLK edge and output data from the ADC are updated on the
rising SCLK edge. Return SCLK low after the data sequence is complete. Even though the SCLK input has
hysteresis, keep SCLK as clean as possible to prevent unintentional SCLK transitions. Avoid ringing and voltage
overshoot on the SCLK input. Place a series termination resistor at the SCLK drive pin to help reduce ringing.
9.5.1.3 Serial Data Input (DIN)
The serial data input pin (DIN) is used with SCLK to send data (commands and register data) to the device. The
device latches data on DIN on the SCLK falling edge. The device never drives the DIN pin. During data
readback, when no command is intended, keep DIN low.
9.5.1.4 Serial Data Output and Data Ready (DOUT/DRDY)
The DOUT/DRDY pin is a dual-function output. The pin functions as the digital data output and the ADC data-
ready indication.
First, this pin is used with SCLK to read conversion and register data from the device. Conversion or register
data are shifted out on DOUT/DRDY on the SCLK rising edge. DOUT/DRDY goes to a high-impedance state
when CS is high.
Second, the DOUT/DRDY pin indicates availability of new conversion data. DOUT/DRDY transitions low at the
same time that the DRDY pin goes low to indicate new conversion data are available. Both signals can be used
to detect if new data are ready. However, because DOUT/DRDY is disabled when CS is high, use the dedicated
DRDY pin when monitoring conversions on multiple devices on the SPI bus.
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Programming (接下页)
9.5.1.5 Data Ready (DRDY)
The DRDY pin is an output that transitions low to indicate when conversion data are ready for retrieval. Initially,
DRDY is high at power-on. When converting, the state of DRDY depends on whether the conversion data are
retrieved or not. In continuous conversion mode after DRDY goes low, DRDY is driven high on the first SCLK
rising edge. If data are not read, DRDY remains low and then pulses high 24 · tCLK before the next DRDY falling
edge. The data must be retrieved before the next DRDY update, otherwise the data are overwritten by new data
and any previous data are lost. 图 85 shows the DRDY operation without data retrieval. 图 86 shows the DRDY
operation with data retrieval after each conversion completes.
DRDY
START/SYNC Pin
SCLK
START
Command
DIN
START
(1) DRDY returns high with the rising edge of the first SCLK after a data ready indication.
图 85. DRDY Operation Without Data Retrieval
DRDY
START/SYNC Pin
SCLK
START
Command
START(1)
DIN
DOUT/DRDY
Conversion
Data 1
Conversion
Data 2
Conversion
Data 3
(1) DRDY returns high with the rising edge of the first SCLK after a data ready indication.
图 86. DRDY Operation With Data Retrieval
9.5.1.6 Timeout
The ADS124S0x offers a serial interface timeout feature that is used to recover communication when a serial
interface transmission is interrupted. This feature is especially useful in applications where CS is permanently
tied low and is not used to frame a communication sequence. The SPI interface resets when no valid 8 bits are
received within 215 · tCLK. The timeout feature is enabled by setting the TIMEOUT bit to 1 in the system control
register (09h).
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Programming (接下页)
9.5.2 Data Format
The devices provide 24 bits of data in binary twos complement format. The size of one code (LSB) is calculated
using 公式 11.
1 LSB = (2 · VREF / Gain) / 224 = +FS / 223
(11)
A positive full-scale input [VIN ≥ (+FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFFFh
and a negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 800000h. The output clips
at these codes for signals that exceed full-scale.
表 23 summarizes the ideal output codes for different input signals.
表 23. Ideal Output Code vs Input Signal
INPUT SIGNAL,
VIN = VAINP – VAINN
≥ FS (223 – 1) / 223
FS / 223
IDEAL OUTPUT CODE(1)
7FFFFFh
000001h
0
000000h
–FS / 223
FFFFFFh
≤ –FS
800000h
(1) Excludes the effects of noise, INL, offset, and gain errors.
Mapping of the analog input signal to the output codes is shown in 图 87.
7FFFFFh
7FFFFEh
000001h
000000h
FFFFFFh
800001h
800000h
¼
¼
-FS
-FS
0
FS
Input Voltage VIN
223 - 1
223 - 1
FS
223
223
图 87. Code Transition Diagram
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9.5.3 Commands
Commands are used to control the ADC, access the configuration registers, and retrieve data. Many of the
commands are stand-alone (that is, single-byte). The register write and register read commands, however, are
multibyte, consisting of two command bytes plus the register data byte or bytes. The commands are listed in 表
24.
表 24. Command Definitions
FIRST
COMMAND BYTE
SECOND
COMMAND BYTE
COMMAND
DESCRIPTION
Control Commands
NOP
No operation
0000 0000 (00h)
—
—
—
—
—
—
WAKEUP
Wake-up from power-down mode
Enter power-down mode
Reset the device
0000 001x (02h, 03h)(1)
0000 010x (04h, 05h)(1)
0000 011x (06h, 07h)(1)
0000 100x (08h, 09h)(1)
0000 101x (0Ah, 0Bh)(1)
POWERDOWN
RESET
START
Start conversions
STOP
Stop conversions
Calibration Commands
SYOCAL
System offset calibration
System gain calibration
Self offset calibration
0001 0110 (16h)
0001 0111 (17h)
0001 1001 (19h)
—
—
—
SYGCAL
SFOCAL
Data Read Command
RDATA
Read data by command
0001 001x (12h / 13h)(1)
—
Register Read and Write Commands
RREG
WREG
Read nnnnn registers starting at address rrrrr
Write nnnnn registers starting at address rrrrr
001r rrrr(2)
010r rrrr(2)
000n nnnn(3)
000n nnnn(3)
(1) x = don't care.
(2) r rrrr = starting register address.
(3) n nnnn = number of registers to read or write – 1.
Commands can be sent at any time, either during a conversion or when conversions are stopped. However, if
register read or write commands are in progress when conversion data are ready, the ADC blocks loading of
conversion data to the output shift register. The CS input pin can be taken high between commands; or held low
between consecutive commands. CS must stay low for the entire command sequence. Complete the command,
or terminate the command before completion by taking CS high. Only send the commands that are listed in 表
24.
9.5.3.1 NOP
NOP is a no-operation command. The NOP command is used to clock out data without clocking in a command.
9.5.3.2 WAKEUP
Issue the WAKEUP command to exit power-down mode and to place the device into standby mode.
When running off the external clock, the external clock must be running before sending the WAKEUP command,
otherwise the command is not decoded.
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9.5.3.3 POWERDOWN
Sending the POWERDOWN command aborts a currently ongoing conversion and puts the device into power-
down mode. The device goes into power-down mode 2 · tCLK after the seventh SCLK falling edge of the
command.
For lowest power consumption on DVDD and IOVDD, stop the external clock when in power-down mode. The
device does not gate the external clock. When running off the external clock, provide at a minimum two
additional tCLKs after the POWERDOWN command is issued, otherwise the device does not enter power-down
mode. Because an external clock can be gated for lower power consumption, selecting the internal oscillator
before sending the POWERDOWN command is recommended.
During power-down mode, the only commands that are available are RREG, RDATA, and WAKEUP.
9.5.3.4 RESET
The RESET command resets the digital filter and sets all configuration register values to default settings. A
RESET command also puts the device into standby mode. When in standby mode, the device waits for a rising
edge on the START/SYNC pin or a START command to resume conversions. After sending the RESET
command, a delay time of td(RSSC) is required before sending the first serial interface command or starting a
conversion. See the Timing Characteristics section for reset timing information.
Note that if the device had been using an external clock, the reset sets the device to use the internal oscillator as
a default configuration.
9.5.3.5 START
When the device is configured for continuous conversion mode, issue the START command for the device to
start converting. Every time a conversion completes, the device automatically starts a new conversion until the
STOP command is sent.
In single-shot conversion mode, the START command is used to start a single conversion. After the conversion
completes, the device enters standby mode.
Tie the START/SYNC pin low when the device is controlled through the START and STOP commands. The
START command is not decoded if the START/SYNC pin is high. If the device is already in conversion mode, the
command has no effect.
9.5.3.6 STOP
The STOP command is used in continuous conversion mode to stop the device from converting. The current
conversion is allowed to complete. After DRDY transitions low, the device enters standby mode. The command
has no effect in single-shot conversion mode.
Hold the START/SYNC pin low when the device is controlled through START and STOP commands.
9.5.3.7 SYOCAL
The SYOCAL command initiates a system offset calibration. For a system offset calibration, the inputs must be
externally shorted to a voltage within the input range, ideally near the mid-supply voltage of (AVDD + AVSS) / 2.
The OFC registers are updated when the command completes. Calibration commands must be issued in
conversion mode.
9.5.3.8 SYGCAL
The SYGCAL command initiates the system gain calibration. For a system gain calibration, the input must be
externally set to full-scale. The FSC registers are updated after this operation. Calibration commands must be
issued in conversion mode.
9.5.3.9 SFOCAL
The SFOCAL command initiates a self offset calibration. The device internally shorts the inputs to mid-supply
and performs the calibration. The OFC registers are updated after this operation. Calibration commands must be
issued in conversion mode.
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9.5.3.10 RDATA
The RDATA command is used to read conversion data from the device at any time without concern of data
corruption when the DRDY or DOUT/DRDY signal cannot be monitored. The conversion result is read from a
buffer so that a new data conversion does not corrupt the conversion read.
9.5.3.11 RREG
Use the RREG command to read the device register data. Read the register data one register at a time, or read
a block of register data. The starting register address can be any register in the register map. The RREG
command consists of two bytes. The first byte specifies the starting register address: 001r rrrr, where r rrrr is the
starting register address. The second command byte is the number of registers to read (minus 1): 000n nnnn,
where n nnnn is the number of registers to read minus 1.
After the read command is sent, the ADC responds with one or more register data bytes, most significant bit first.
If the byte count exceeds the last register address, the ADC begins to output zero data. During the register read
operation, any conversion data that becomes available is not loaded to the output shift register to avoid data
contention. However, the conversion data can be retrieved later by the RDATA command. After the register read
command has started, further commands are blocked until one of the following conditions are met:
•
•
•
•
The read operation is completed
The read operation is terminated by taking CS high
The read operation is terminated by a serial interface timeout
The ADC is reset by toggling the RESET pin
图 88 depicts a two-register read operation example. As shown, the commands required to read data from two
registers starting at register REF (address = 05h) are: command byte 1 = 25h and command byte 2 = 01h. Keep
DIN low after the two command bytes are sent.
(1)
CS
1
9
17
25
SCLK
DOUT/DRDY
DON‘T CARE
DON‘T CARE
REG DATA 1
REG DATA 2
DIN
0010 0101
0000 0001
(1) CS can be set high or kept low between commands. If kept low, the command must be completed.
图 88. Read Register Sequence
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9.5.3.12 WREG
Use the WREG command to write the device register data. The register data are written one register at a time or
as a block of register data. The starting register address is any register in the register map.
The WREG command consists of two bytes. The first byte specifies the starting register address: 010r rrrr, where
r rrrr is the starting register address The second command byte is the number of registers to write (minus 1):
000n nnnn, where n nnnn is the number of registers to write minus 1. The following byte (or bytes) is the register
data, most significant bit first. If the byte count exceeds the last register address, the ADC ignores the data. After
the register write command has started, further commands are blocked until one of the following conditions are
met:
•
•
•
•
The write operation is completed
The write operation is terminated by taking CS high
The write operation is terminated by a serial interface timeout
The ADC is reset by toggling the RESET pin
图 89 depicts a two-register write operation example. As shown, the required commands to write data to two
registers starting at register REF (address = 05h) are: command byte 1 = 45h and command byte 2 = 01h.
(1)
CS
1
9
17
25
SCLK
DOUT/DRDY
DIN
DON‘T CARE
DON‘T CARE
DON‘T CARE
DON‘T CARE
0100 0101
0000 0001
REG DATA 1
REG DATA 2
(1) CS can be set high or kept low between commands. If kept low, the command must be completed.
图 89. Write Register Sequence
Writing new data to certain configuration registers resets the digital filter and starts a new conversion if a
conversion is in progress. Writing to the following registers triggers a new conversion:
•
•
•
•
•
•
•
Channel configuration register (02h)
Gain setting register (03h)
Data rate register (04h)
Reference control register (05h), bits [5:0]
Excitation current register 1 (06h), bits [3:0]
Excitation current register 2 (07h)
System control register (09h), bits [7:5]
When the device is configured with WREG, the first data ready indication occurs after the new conversion
completes with the new configuration settings. The previous conversion data are cleared at restart; therefore
read the previous data before the register write operation. A WREG to the previously mentioned registers only
starts a new conversion if the register data are new (differs from the previous register data) and if a conversion is
in progress. If the device is in standby mode, the device sets the configuration according to the WREG data, but
does not start a conversion until the START/SYNC pin is taken high or a START command is issued.
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9.5.4 Reading Data
ADC data are read by two methods: read data direct or read data by command. The ADC writes new conversion
data to the output shift register and the internal data-holding register. Data are read either from the output shift
register (in direct mode) or read from the data-holding register (in command mode). Reading data from the data-
holding register (command mode) does not require synchronizing the start of data readback to DRDY.
9.5.4.1 Read Data Direct
In this method of data retrieval, ADC conversion data are shifted out directly from the output shift register. No
command is necessary. Read data direct requires that no serial activity occur from the falling edge of DRDY to
the readback, or the data are invalid. The serial interface is full duplex in the read data direct mode; meaning that
commands are decoded during the data readback. If no command is intended, keep DIN low during readback. If
an input command is sent during readback, the ADC executes the command, and data corruption can result.
Synchronize the data readback to DRDY or to DOUT/DRDY to make sure the data are read before the next
DRDY update, or the old data are overwritten with new data.
As shown in 图 90, the ADC data field is 3, 4, or 5 bytes long. The data field consists of an optional STATUS
byte, three bytes of conversion data, and an optional CRC byte. After all bytes are read, the data-byte sequence
(including the STATUS byte and CRC byte, if selected) is repeated when continued SCLKs are sent. The byte
sequence repeats starting with the first byte. In order to help verify error-free communication, read the same data
multiple times in each conversion interval or use the optional CRC byte.
(1)
DRDY
CS (2)
9
25
41
1
17
33
SCLK
DIN
HI-Z
DOUT/DRDY
Repeat
CRC
STATUS
Data 1
Data 2
Data 3
(3)
Optional (4)
Optional (4)
Repeated Data (5)
ADC Data Bytes
SENDSTAT bit of SYS register
0 = Disabled
CRC bit of SYS register
0 = Disabled
1 = Enabled
1 = Enabled
(1) DRDY returns high on the first SCLK falling edge.
(2) CS can be tied low. If CS is low, DOUT/DRDY asserts low at the same time as DRDY.
(3) Complete data retrieval before new data are ready (28 · tCLK before the next falling edge of DOUT/DRDY and DRDY).
(4) The STATUS and CRC bytes are optional.
(5) The byte sequence, including selected optional bytes, repeats by continuing SCLK.
图 90. Read Data Direct
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9.5.4.2 Read Data by RDATA Command
When the RDATA command is sent, the data are retrieved from the ADC data-holding register. Read data at any
time without the risk of data corruption because the command method does not require synchronizing to DRDY.
Polling of DRDY to determine when ADC data are ready can still be used.
图 91 shows the read data by command sequence. The output data MSB begins on the first SCLK rising edge
after the command. The output data field can be 3, 4, or 5 bytes long. The data field consists of an optional
STATUS byte, three bytes of conversion data, and an optional CRC byte. An RDATA command must be sent for
each read operation. The ADC does not respond to commands until the read operation is complete, or
terminated by taking CS high.
After all bytes are read, the data-byte sequence (including the STATUS byte and CRC byte, if selected) is
repeated by continuing SCLK.
(1)
CS
9
25
41
1
17
33
SCLK
DIN
RDATA
HI-Z
DOUT/DRDY
(2)
Don‘t Care
STATUS
Data 1
Data 2
Data 3
CRC
Optional(3)
ADC Data Bytes
Optional(3)
SENDSTAT bit of SYS register
0 = Disabled
CRC bit of SYS register
0 = Disabled
1 = Enabled
1 = Enabled
(1) CS can be tied low. If CS is low, DOUT/DRDY asserts low with DRDY.
(2) DOUT/DRDY is driven low with DRDY. If a read operation occurs after the DRDY falling edge, then DOUT/DRDY can
be high or low.
(3) The STATUS and CRC bytes are optional.
图 91. Read Data by Command
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9.5.4.3 Sending Commands When Reading Data
The device serial interface is capable of full-duplex operation when reading conversion data and not using the
RDATA command. In full-duplex operation, commands are decoded at the same time that conversion data are
read. Commands can be sent on any 8-bit data boundary during a data read operation. When a RREG or
RDATA command is recognized, the current data read operation is aborted and the conversion data are
corrupted, unless the command is sent when the last byte of the conversion result is retrieved. The device starts
to output the requested data on DOUT/DRDY at the first SCLK rising edge after the command byte. To read data
without interruption, keep DIN low when clocking out data.
A WREG command can be sent without corrupting an ongoing read operation. Sending a WREG command
when reading data minimizes the time between reading the data and setting the device configuration for the next
conversion. 图 92 shows an example for sending a WREG command to write two configuration registers when
reading conversion data by using read data direct mode. After the command is clocked in, the device resets the
digital filter and starts converting with the new register settings as long as the device is in continuous conversion
mode. The digital filter is reset and conversions are restarted after each data byte is received. In this example,
the digital filter is reset when the first byte is received, decoding the input multiplexer and again when the PGA is
set. The WREG command can be sent on any of the 8-bit boundaries. The example in 图 92 has the STATUS
and CRC bytes disabled.
DRDY
CS (1)
9
25
1
17
SCLK
DIN
0100 0010
0000 0001
0011 0010
0000 1011
WREG at 02h
Data 1
Two bytes
Data 2
AINP = AIN3,
AINN = AIN2
PGA enabled,
Gain = 8
HI-Z
DOUT/DRDY
Data 3
Repeat Data 1
ADC Data Bytes(2)
(1) CS can be tied low. If CS is low, DOUT/DRDY asserts low at the same time as DRDY.
(2) The output data buffer is cyclical and the original data byte is re-issued when the fourth DIN byte is clocked in.
图 92. Issuing a WREG Command When Reading Back ADC Data
9.5.5 Interfacing with Multiple Devices
When connecting multiple devices to a single SPI bus, SCLK, DIN, and DOUT/DRDY can be safely shared by
using a dedicated chip-select (CS) line for each SPI-enabled device. When CS transitions high for the respective
device, DOUT/DRDY enters a tri-state mode. Therefore, DOUT/DRDY cannot be used to indicate when new data
are available if CS is high. Only the dedicated DRDY pin indicates that new data are available because the
DRDY pin is actively driven even when CS is high.
In some cases, the DRDY pin cannot be interfaced to the microcontroller. This scenario can occur if there are
insufficient GPIO channels available on the microcontroller or if the serial interface must be galvanically isolated
and thus the amount of channels must be limited. In order to evaluate when a new conversion of one of the
devices is ready, the microcontroller can periodically drop CS to the respective device and poll the state of the
DOUT/DRDY pin.
When CS goes low, the DOUT/DRDY pin immediately drives either high or low. If the DOUT/DRDY line drives
low, new data are available. If the DOUT/DRDY line drives high, no new data are available. This procedure
requires that DOUT/DRDY is forced high after reading each conversion result and before taking CS high. To
make sure DOUT/DRDY is taken high, send a RREG command to read a register where the least significant bit
is 1.
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Retrieving data using direct read mode requires knowledge of the DRDY falling edge timing to avoid data
corruption. Use the RDATA command so that valid data can be retrieved from the device at any time without
concern of data corruption by a new data ready.
9.6 Register Map
9.6.1 Configuration Registers
The ADS124S0x register map consists of 18, 8-bit registers. These registers are used to configure and control
the device to the desired mode of operation. Access the registers through the serial interface by using the RREG
and WREG register commands. After power-on or reset, the registers default to the initial settings, as shown in
the Default column of 表 25.
Data can be written as a block to multiple registers using a single WREG command. If data are written as a
block, the data of certain registers take effect immediately when data are shifted in. Writing new data to certain
registers results in a restart of conversions that are in progress. The registers that result in a conversion restart
are discussed in the WREG section.
表 25. Configuration Register Map
ADDR REGISTER
DEFAULT
xxh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
ID
RESERVED
DEV_ID[2:0]
STATUS
INPMUX
PGA
80h
01h
00h
14h
10h
00h
FFh
00h
10h
00h
00h
00h
00h
00h
40h
00h
00h
FL_POR
RDY
FL_P_RAILP FL_P_RAILN FL_N_RAILP FL_N_RAILN FL_REF_L1 FL_REF_L0
MUXP[3:0] MUXN[3:0]
GAIN[2:0]
DELAY[2:0]
CLK
PGA_EN[1:0]
FILTER
DATARATE
REF
G_CHOP
MODE
REFP_BUF
0
DR[3:0]
FL_REF_EN[1:0]
REFN_BUF
0
REFSEL[1:0]
REFCON[1:0]
IDACMAG
IDACMUX
VBIAS
FL_RAIL_EN
PSW
IMAG[3:0]
I2MUX[3:0]
I1MUX[3:0]
VB_LEVEL
VB_AINC
VB_AIN5
VB_AIN4
VB_AIN3
VB_AIN2
TIMEOUT
VB_AIN1
CRC
VB_AIN0
SYS
SYS_MON[2:0]
CAL_SAMP[1:0]
SENDSTAT
OFCAL0
OFCAL1
OFCAL2
FSCAL0
FSCAL1
FSCAL2
GPIODAT
GPIOCON
OFC[7:0]
OFC[15:8]
OFC[23:16]
FSC[7:0]
FSC[15:8]
FSC[23:16]
DIR[3:0]
DAT[3:0]
CON[3:0]
0
0
0
0
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9.6.1.1 Device ID Register (address = 00h) [reset = xxh]
图 93. Device ID (ID) Register
7
6
5
4
3
2
1
0
RESERVED
R-xxh
DEV_ID[2:0]
R-xh
LEGEND: R = Read only; -n = value after reset; -x = variable
表 26. Device ID (ID) Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
7:3
RESERVED
R
xxh
Values are subject to change without notice
Device identifier
Identifies the model of the device.
000 : ADS124S08 (12 channels, 24 bits)
001 : ADS124S06 (6 channels, 24 bits)
010 : Reserved
2:0
DEV_ID[2:0]
R
xh
011 : Reserved
100 : Reserved
101 : Reserved
110 : Reserved
111 : Reserved
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9.6.1.2 Device Status Register (address = 01h) [reset = 80h]
图 94. Device Status (STATUS) Register
7
6
5
4
3
2
1
0
FL_POR
R/W-1h
RDY
R-0h
FL_P_RAILP
R-0h
FL_P_RAILN
R-0h
FL_N_RAILP
R-0h
FL_N_RAILN
R-0h
FL_REF_L1
R-0h
FL_REF_L0
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 27. Device Status (STATUS) Register Field Descriptions
Bit
Field
Type
Reset
Description
POR flag
Indicates a power-on reset (POR) event has occurred.
7
FL_POR
R/W
1h
0 : Register has been cleared and no POR event has occurred.
1 : POR event occurred and has not been cleared. Flag must be cleared by
user register write (default).
Device ready flag
Indicates the device has started up and is ready for communication.
0 : ADC ready for communication (default)
1 : ADC not ready
Positive PGA output at positive rail flag(1)
6
5
4
3
2
RDY
R
R
R
R
R
0h
0h
0h
0h
0h
Indicates the positive PGA output is within 150 mV of AVDD.
0 : No error (default)
1 : PGA positive output within 150 mV of AVDD
Positive PGA output at negative rail flag(1)
FL_P_RAILP
FL_P_RAILN
FL_N_RAILP
FL_N_RAILN
Indicates the positive PGA output is within 150 mV of AVSS.
0 : No error (default)
1 : PGA positive output within 150 mV of AVSS
Negative PGA output at positive rail flag(1)
Indicates the negative PGA output is within 150 mV of AVDD.
0 : No error (default)
1 : PGA negative output within 150 mV of AVDD
Negative PGA output at negative rail flag(1)
Indicates the negative PGA output is within 150 mV of AVSS.
0 : No error (default)
1 : PGA negative output within 150 mV of AVSS
Reference voltage monitor flag, level 1(2)
Indicates the external reference voltage is lower than 1/3 of the analog
supply voltage. Can be used to detect an open-excitation lead in a 3-wire
RTD application.
0 : Differential reference voltage ≥ 1/3 · (AVDD – AVSS) (default)
1 : Differential reference voltage < 1/3 · (AVDD – AVSS)
1
0
FL_REF_L1
FL_REF_L0
R
R
0h
0h
Reference voltage monitor flag, level 0(2)
Indicates the external reference voltage is lower than 0.3 V. Can be used to
indicate a missing or floating external reference voltage.
0 : Differential reference voltage ≥ 0.3 V (default)
1 : Differential reference voltage < 0.3 V
(1) The PGA rail monitors are enabled with the FL_RAIL_EN bit in excitation current register 1 (06h).
(2) The reference monitors are enabled with the FL_REF_EN[1:0] bits of the reference control register (05h).
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9.6.1.3 Input Multiplexer Register (address = 02h) [reset = 01h]
图 95. Input Multiplexer (INPMUX) Register
7
6
5
4
3
2
1
0
MUXP[3:0]
R/W-0h
MUXN[3:0]
R/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
表 28. Input Multiplexer (INPMUX) Register Field Descriptions
Bit
Field
Type
Reset
Description
Positive ADC input selection
Selects the ADC positive input channel.
0000 : AIN0 (default)
0001 : AIN1
0010 : AIN2
0011 : AIN3
0100 : AIN4
0101 : AIN5
0110 : AIN6 (ADS124S08 only)
0111 : AIN7 (ADS124S08 only)
1000 : AIN8 (ADS124S08 only)
1001 : AIN9 (ADS124S08 only)
1010 : AIN10 (ADS124S08 only)
1011 : AIN11 (ADS124S08 only)
1100 : AINCOM
7:4
MUXP[3:0]
R/W
0h
1101 : Reserved
1110 : Reserved
1111 : Reserved
Negative ADC input selection
Selects the ADC negative input channel.
0000 : AIN0
0001 : AIN1 (default)
0010 : AIN2
0011 : AIN3
0100 : AIN4
0101 : AIN5
0110 : AIN6 (ADS124S08 only)
0111 : AIN7 (ADS124S08 only)
1000 : AIN8 (ADS124S08 only)
1001 : AIN9 (ADS124S08 only)
1010 : AIN10 (ADS124S08 only)
1011 : AIN11 (ADS124S08 only)
1100 : AINCOM
3:0
MUXN[3:0]
R/W
1h
1101 : Reserved
1110 : Reserved
1111 : Reserved
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9.6.1.4 Gain Setting Register (address = 03h) [reset = 00h]
图 96. Gain Setting (PGA) Register
7
6
5
4
3
2
1
0
DELAY[2:0]
R/W-0h
PGA_EN[1:0]
R/W-0h
GAIN[2:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表 29. Gain Setting (PGA) Register Field Descriptions
Bit
Field
Type
Reset
Description
Programmable conversion delay selection
Sets the programmable conversion delay time for the first conversion after a
WREG when a configuration change resets of the digital filter and triggers a
new conversion(1)
.
000 : 14 · tMOD (default)
001 : 25 · tMOD
010 : 64 · tMOD
7:5
DELAY[2:0]
R/W
0h
011 : 256 · tMOD
100 : 1024 · tMOD
101 : 2048 · tMOD
110 : 4096 · tMOD
111 : 1 · tMOD
PGA enable
Enables or bypasses the PGA.
00 : PGA is powered down and bypassed. Enables single-ended
measurements with unipolar supply (Set gain = 1(2)) (default)
01 : PGA enabled (gain = 1 to 128)
10 : Reserved
4:3
PGA_EN[1:0]
R/W
0h
11 : Reserved
PGA gain selection
Configures the PGA gain.
000 : 1 (default)
001 : 2
010 : 4
011 : 8
2:0
GAIN[2:0]
R/W
0h
100 : 16
101 : 32
110 : 64
111 : 128
(1) For details on which bits and registers trigger a new conversion, see the WREG section.
(2) When bypassing the PGA, the user must also set GAIN[2:0] to 000.
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9.6.1.5 Data Rate Register (address = 04h) [reset = 14h]
图 97. Data Rate (DATARATE) Register
7
6
5
4
3
2
1
0
G_CHOP
R/W-0h
CLK
MODE
R/W-0h
FILTER
R/W-1h
DR[3:0]
R/W-4h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 30. Data Rate (DATARATE) Register Field Descriptions
Bit
Field
Type
Reset
Description
Global chop enable
Enables the global chop function. When enabled, the device automatically
swaps the inputs and takes the average of two consecutive readings to
7
G_CHOP
R/W
0h
cancel the offset voltage.
0 : Disabled (default)
1 : Enabled
Clock source selection
Configures the clock source to use either the internal oscillator or an
external clock.
6
CLK
R/W
0h
0 : Internal 4.096-MHz oscillator (default)
1 : External clock
Conversion mode selection
Configures the ADC for either continuous conversion or single-shot
conversion mode.
0 : Continuous conversion mode (default)
1 : Single-shot conversion mode
5
4
MODE
R/W
R/W
0h
1h
Digital filter selection
Configures the ADC to use either the sinc3 or the low-latency filter.
FILTER
0 : Sinc3 filter
1 : Low-latency filter (default)
Data rate selection
Configures the output data rate(1)
0000 : 2.5 SPS
.
0001 : 5 SPS
0010 : 10 SPS
0011 : 16.6 SPS
0100 : 20 SPS (default)
0101 : 50SPS
0110 : 60 SPS
3:0
DR[3:0]
R/W
4h
0111 : 100 SPS
1000 : 200 SPS
1001 : 400 SPS
1010 : 800 SPS
1011 : 1000 SPS
1100 : 2000 SPS
1101 : 4000 SPS
1110 : 4000 SPS
1111 : Reserved
(1) Data rates of 60 Hz or less can offer line-cycle rejection; see the 50-Hz and 60-Hz Line Cycle Rejection section for more information.
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9.6.1.6 Reference Control Register (address = 05h) [reset = 10h]
图 98. Reference Control (REF) Register
7
6
5
4
3
2
1
0
FL_REF_EN[1:0]
R/W-0h
REFP_BUF
R/W-0h
REFN_BUF
R/W-1h
REFSEL[1:0]
R/W-0h
REFCON[1:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表 31. Reference Control (REF) Register Field Descriptions
Bit
Field
Type
Reset
Description
Reference monitor configuration
Enables and configures the reference monitor.
00 : Disabled (default)
01 : FL_REF_L0 monitor enabled, threshold 0.3 V
7:6
FL_REF_EN[1:0]
R/W
0h
10 : FL_REF_L0 and FL_REF_L1 monitors enabled, thresholds 0.3 V and
1/3 · (AVDD – AVSS)
11 : FL_REF_L0 monitor and 10-MΩ pull-together enabled, threshold 0.3 V
Positive reference buffer bypass
Disables the positive reference buffer. Recommended when V(REFPx) is
5
4
REFP_BUF
REFN_BUF
R/W
R/W
0h
1h
close to AVDD.
0 : Enabled (default)
1 : Disabled
Negative reference buffer bypass
Disables the negative reference buffer. Recommended when V(REFNx) is
close to AVSS.
0 : Enabled
1 : Disabled (default)
Reference input selection
Selects the reference input source for the ADC.
00 : REFP0, REFN0 (default)
01 : REFP1, REFN1
3:2
1:0
REFSEL[1:0]
REFCON[1:0]
R/W
R/W
0h
0h
10 : Internal 2.5-V reference(1)
11 : Reserved
Internal voltage reference configuration(2)
Configures the behavior of the internal voltage reference.
00 : Internal reference off (default)
01 : Internal reference on, but powers down in power-down mode
10 : Internal reference is always on, even in power-down mode
11 : Reserved
(1) Disable the reference buffers when the internal reference is selected for measurements.
(2) The internal voltage reference must be turned on to use the IDACs.
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9.6.1.7 Excitation Current Register 1 (address = 06h) [reset = 00h]
图 99. Excitation Current Register 1 (IDACMAG)
7
6
5
0
4
0
3
2
1
0
FL_RAIL_EN
R/W-0h
PSW
IMAG[3:0]
R/W-0h
R/W-0h
R-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 32. Excitation Current Register 1 (IDACMAG) Register Field Descriptions
Bit
Field
Type
Reset
Description
PGA output rail flag enable
Enables the PGA output voltage rail monitor circuit.
0 : Disabled (default)
7
FL_RAIL_EN
R/W
0h
1 : Enabled
Low-side power switch
Controls the low-side power switch. The low-side power switch opens
automatically in power-down mode.
0 : Open (default)
6
PSW
R/W
R
0h
0h
1 : Closed
Reserved
5:4
RESERVED
Always write 0h
IDAC magnitude selection
Selects the value of the excitation current sources. Sets IDAC1 and IDAC2
to the same value.
0000 : Off (default)
0001 : 10 µA
0010 : 50 µA
0011 : 100 µA
0100 : 250 µA
0101 : 500 µA
0110 : 750 µA
0111 : 1000 µA
1000 : 1500 µA
1001 : 2000 µA
1010 - 1111 : Off
3:0
IMAG[3:0]
R/W
0h
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9.6.1.8 Excitation Current Register 2 (address = 07h) [reset = FFh]
图 100. Excitation Current Register 2 (IDACMUX)
7
6
5
4
3
2
1
0
I2MUX[3:0]
R/W-Fh
I1MUX[3:0]
R/W-Fh
LEGEND: R/W = Read/Write; -n = value after reset
表 33. Excitation Current Register 2 (IDACMUX) Register Field Descriptions
Bit
Field
Type
Reset
Description
IDAC2 output channel selection
Selects the output channel for IDAC2.
0000 : AIN0
0001 : AIN1
0010 : AIN2
0011 : AIN3
0100 : AIN4
0101 : AIN5
7:4
I2MUX[3:0]
R/W
Fh
0110 : AIN6 (ADS124S08), REFP1 (ADS124S06)
0111 : AIN7 (ADS124S08), REFN1 (ADS124S06)
1000 : AIN8 (ADS124S08 only)
1001 : AIN9 (ADS124S08 only)
1010 : AIN10 (ADS124S08 only)
1011 : AIN11 (ADS124S08 only)
1100 : AINCOM
1101 - 1111 : Disconnected (default)
IDAC1 output channel selection
Selects the output channel for IDAC1.
0000 : AIN0
0001 : AIN1
0010 : AIN2
0011 : AIN3
0100 : AIN4
0101 : AIN5
3:0
I1MUX[3:0]
R/W
Fh
0110 : AIN6 (ADS124S08 only), REFP1 (ADS124S06)
0111 : AIN7 (ADS124S08 only), REFN1 (ADS124S06)
1000 : AIN8 (ADS124S08 only)
1001 : AIN9 (ADS124S08 only)
1010 : AIN10 (ADS124S08 only)
1011 : AIN11 (ADS124S08 only)
1100 : AINCOM
1101 - 1111 : Disconnected (default)
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9.6.1.9 Sensor Biasing Register (address = 08h) [reset = 00h]
图 101. Sensor Biasing (VBIAS) Register
7
6
5
4
3
2
1
0
VB_LEVEL
R/W-0h
VB_AINC
R/W-0h
VB_AIN5
R/W-0h
VB_AIN4
R/W-0h
VB_AIN3
R/W-0h
VB_AIN2
R/W-0h
VB_AIN1
R/W-0h
VB_AIN0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表 34. Sensor Biasing (VBIAS) Register Field Descriptions
Bit
Field
Type
Reset
Description
VBIAS level selection
Sets the VBIAS output voltage level. VBIAS is disabled when not connected
to any input.
7
VB_LEVEL
R/W
0h
0 : (AVDD + AVSS) / 2 (default)
1 : (AVDD + AVSS) / 12
AINCOM VBIAS selection(1)
Enables VBIAS on the AINCOM pin.
0 : VBIAS disconnected from AINCOM (default)
1 : VBIAS connected to AINCOM
AIN5 VBIAS selection(1)
6
5
4
3
2
1
0
VB_AINC
VB_AIN5
VB_AIN4
VB_AIN3
VB_AIN2
VB_AIN1
VB_AIN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
Enables VBIAS on the AIN5 pin.
0 : VBIAS disconnected from AIN5 (default)
1 : VBIAS connected to AIN5
AIN4 VBIAS selection(1)
Enables VBIAS on the AIN4 pin.
0 : VBIAS disconnected from AIN4 (default)
1 : VBIAS connected to AIN4
AIN3 VBIAS selection(1)
Enables VBIAS on the AIN3 pin.
0 : VBIAS disconnected from AIN3 (default)
1 : VBIAS connected to AIN3
AIN2 VBIAS selection(1)
Enables VBIAS on the AIN2 pin.
0 : VBIAS disconnected from AIN2 (default)
1 : VBIAS connected to AIN2
AIN1 VBIAS selection(1)
Enables VBIAS on the AIN1 pin.
0 : VBIAS disconnected from AIN1 (default)
1 : VBIAS connected to AIN1
AIN0 VBIAS selection(1)
Enables VBIAS on the AIN0 pin.
0 : VBIAS disconnected from AIN0 (default)
1 : VBIAS connected to AIN0
(1) The bias voltage can be selected for multiple analog inputs at the same time.
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9.6.1.10 System Control Register (address = 09h) [reset = 10h]
图 102. System Control (SYS) Register
7
6
5
4
3
2
1
0
SYS_MON[2:0]
R/W-0h
CAL_SAMP[1:0]
R/W-2h
TIMEOUT
R/W-0h
CRC
SENDSTAT
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表 35. System Control (SYS) Register Field Descriptions
Bit
Field
Type
Reset
Description
System monitor configuration(1)
Enables a set of system monitor measurements using the ADC.
000 : Disabled (default)
001 : PGA inputs shorted to (AVDD + AVSS) / 2 and disconnected from
AINx and the multiplexer; gain set by user
010 : Internal temperature sensor measurement; PGA must be enabled
7:5
SYS_MON[2:0]
R/W
0h
(PGA_EN[1:0] = 01); gain set by user(2)
011 : (AVDD – AVSS) / 4 measurement; gain set to 1(3)
100 : DVDD / 4 measurement; gain set to 1(3)
101 : Burn-out current sources enabled, 0.2-µA setting
110 : Burn-out current sources enabled, 1-µA setting
111 : Burn-out current sources enabled, 10-µA setting
Calibration sample size selection
Configures the number of samples averaged for self and system offset and
system gain calibration.
00 : 1 sample
4:3
CAL_SAMP[1:0]
R/W
2h
01 : 4 samples
10 : 8 samples (default)
11 : 16 samples
SPI timeout enable
Enables the SPI timeout function.
0 : Disabled (default)
1 : Enabled
2
1
0
TIMEOUT
CRC
R/W
R/W
R/W
0h
0h
0h
CRC enable
Enables the CRC byte appended to the conversion result. When enabled,
CRC is calculated across the 24-bit conversion result (plus the STATUS
byte if enabled).
0 : Disabled (default)
1 : Enabled
STATUS byte enable
Enables the STATUS byte prepended to the conversion result.
0 : Disabled (default)
1 : Enabled
SENDSTAT
(1) With system monitor functions enabled, the AINx multiplexer switches are open for the (AVDD + AVSS) / 2 measurement, the
temperature sensor, and the supply monitors.
(2) When using the internal temperature sensor, gain must be 4 or less to keep the measurement within the PGA input voltage range.
(3) The PGA gain is automatically set to 1 when the supply monitors are enabled, regardless of the setting in GAIN[2:0].
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9.6.1.11 Offset Calibration Register 1 (address = 0Ah) [reset = 00h]
图 103. Offset Calibration Register 1 (OFCAL0)
7
6
5
4
3
2
1
0
OFC[7:0]
R/W-00h
LEGEND: R/W = Read/Write; -n = value after reset
表 36. Offset Calibration Register 1 (OFCAL0) Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
OFC[7:0]
R/W
00h
Bits [7:0] of the offset calibration value.
9.6.1.12 Offset Calibration Register 2 (address = 0Bh) [reset = 00h]
图 104. Offset Calibration Register 2 (OFCAL1)
7
6
5
4
3
2
1
0
OFC[15:8]
R/W-00h
LEGEND: R/W = Read/Write; -n = value after reset
表 37. Offset Calibration Register 2 (OFCAL1) Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
OFC[15:8]
R/W
00h
Bits [15:8] of the offset calibration value.
9.6.1.13 Offset Calibration Register 3 (address = 0Ch) [reset = 00h]
图 105. Offset Calibration Register 3 (OFCAL2)
7
6
5
4
3
2
1
0
OFC[23:16]
R/W-00h
LEGEND: R/W = Read/Write; -n = value after reset
表 38. Offset Calibration Register 3 (OFCAL2) Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
OFC[23:16]
R/W
00h
Bits [23:16] of the offset calibration value.
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9.6.1.14 Gain Calibration Register 1 (address = 0Dh) [reset = 00h]
图 106. Gain Calibration Register 1 (FSCAL0)
7
6
5
4
3
2
1
0
FSC[7:0]
R/W-00h
LEGEND: R/W = Read/Write; -n = value after reset
表 39. Gain Calibration Register 1 (FSCAL0) Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
FSC[7:0]
R/W
00h
Bits [7:0] of the gain calibration value.
9.6.1.15 Gain Calibration Register 2 (address = 0Eh) [reset = 00h]
图 107. Gain Calibration Register 2 (FSCAL1)
7
6
5
4
3
2
1
0
FSC[15:8]
R/W-00h
LEGEND: R/W = Read/Write; -n = value after reset
表 40. Gain Calibration Register 2 (FSCAL1) Field Descriptions
Bit
Field
Type
Reset
Description
7:0
FSC[15:8]
R/W
00h
Bits [15:8] of the gain calibration value.
9.6.1.16 Gain Calibration Register 3 (address = 0Fh) [reset = 40h]
图 108. Gain Calibration Register 3 (FSCAL2)
7
6
5
4
3
2
1
0
FSC[23:16]
R/W-40h
LEGEND: R/W = Read/Write; -n = value after reset
表 41. Gain Calibration Register 3 (FSCAL2) Field Descriptions
Bit
Field
Type
Reset
Description
7:0
FSC[23:16]
R/W
40h
Bits [23:16] of the gain calibration value.
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9.6.1.17 GPIO Data Register (address = 10h) [reset = 00h]
图 109. GPIO Data (GPIODAT) Register
7
6
5
4
3
2
1
0
DIR[3:0]
R/W-0h
DAT[3:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表 42. GPIO Data (GPIODAT) Register Field Descriptions
Bit
Field
Type
Reset
Description
GPIO direction
Configures the selected GPIO as an input or output.
0 : GPIO[x] configured as output (default)
1 : GPIO[x] configured as input
7:4
DIR[3:0]
R/W
0h
GPIO data
Contains the data of the GPIO inputs or outputs.
0 : GPIO[x] is low (default)
3:0
DAT[3:0]
R/W
0h
1 : GPIO[x] is high
9.6.1.18 GPIO Configuration Register (address = 11h) [reset = 00h]
图 110. GPIO Configuration Register
7
0
6
0
5
0
4
0
3
2
1
0
CON[3:0]
R/W-0h
R-0h
R-0h
R-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 43. GPIO Configuration (GPIOCON) Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
7:4
RESERVED
R
0h
Always write 0h
GPIO pin configuration
Configures the GPIO[x] pin as an analog input or GPIO. CON[x]
corresponds to the GPIO[x] pin.
3:0
CON[3:0]
R/W
0h
0 : GPIO[x] configured as analog input (default)(1)
1 : GPIO[x] configured as GPIO
(1) On the ADS124S06, the GPIO pins default as disabled. Set the CON[3:0] bits to enable the respective GPIO pins.
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The ADS124S06 and ADS124S08 are precision, 24-bit, ΔΣ ADCs that offer many integrated features to simplify
the measurement of the most common sensor types (including various types of temperature, flow, and bridge
sensors). Primary considerations when designing an application with the ADS124S0x include analog input
filtering, establishing an appropriate reference, and setting the absolute input voltage for the internal PGA.
Connecting and configuring the serial interface appropriately is another concern. These considerations are
discussed in the following sections.
10.1.1 Serial Interface Connections
The principle serial interface connections for the ADS124S0x are shown in 图 111.
1 mF
24
23
22
21
20
19
18
17
3.3 V
47 ꢀ
47 ꢀ
47 ꢀ
47 ꢀ
GPIO
NC 25
DVDD
IOVDD
DGND
DRDY
16
15
14
13
12
11
10
9
5 V
26
27
28
AVDD
GPIO/IRQ
MISO
0.1 mF
330 nF
AVSS
AVSS-SW
SCLK
Microcontroller
with SPI
47 ꢀ
47 ꢀ
47 ꢀ
REFN0 29
REFP0 30
DOUT/DRDY
SCLK
MOSI
GPIO
REFN1/AIN7 31
REFP1/AIN6 32
DIN
GPIO
DVDD
DVSS
3.3 V
CS
1
2
3
4
5
6
7
8
0.1 mF
图 111. Serial Interface Connections
Most microcontroller SPI peripherals can interface with the ADS124S0x. The interface operates in SPI mode 1
where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are launched or changed only on
SCLK rising edges; data are latched or read by the master and slave on SCLK falling edges. Details of the SPI
communication protocol employed by the devices are found in the Serial Interface section.
Place 47-Ω resistors in series with all digital input and output pins (CS, SCLK, DIN, DOUT/DRDY, and DRDY).
This resistance smooths sharp transitions, suppresses overshoot, and offers some overvoltage protection. Care
must be taken to meet all SPI timing requirements because the additional resistors interact with the bus
capacitances present on the digital signal lines.
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10.1.2 Analog Input Filtering
Analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process and
second, to reduce external noise from being a part of the measurement.
As with any sampled system, aliasing can occur if proper antialias filtering is not in place. Aliasing occurs when
frequency components are present in the input signal that are higher than half the sampling frequency of the
ADC (also known as the Nyquist frequency). These frequency components are folded back and show up in the
actual frequency band of interest below half the sampling frequency. Note that inside a ΔΣ ADC, the input signal
is oversampled at the modulator frequency, fMOD and not at the output data rate. The filter response of the digital
filter repeats at multiples of fMOD, as shown in 图 112. Signals or noise up to a frequency where the filter
response repeats are attenuated to a certain amount by the digital filter depending on the filter architecture. Any
frequency components present in the input signal around the modulator frequency or multiples thereof are not
attenuated and alias back into the band of interest, unless attenuated by an external analog filter.
Magnitude
Sensor
Signal
Unwanted
Signals
Unwanted
Signals
Output
Data Rate
fMOD/2
fMOD
Frequency
Frequency
Frequency
Magnitude
Digital Filter
Aliasing of
Unwanted Signals
Output
Data Rate
fMOD/2
fMOD
Magnitude
External
Antialiasing Filter
Roll-Off
Output
fMOD/2
fMOD
Data Rate
图 112. Effect of Aliasing
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Many sensor signals are inherently band limited; for example, the output of a thermocouple has a limited rate of
change. In this case, the sensor signal does not alias back into the pass band when using a ΔΣ ADC. However,
any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass band.
Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated
from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors
and cellular phones. Another noise source typically exists on the printed circuit board (PCB) itself in the form of
clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the
measurement result.
A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either eliminate aliasing, or to reduce the
effect of aliasing to a level below the noise floor of the sensor. Ideally, any signal beyond fMOD / 2 is attenuated to
a level below the noise floor of the ADC. The digital filter of the ADS124S0x attenuates signals to a certain
degree, as illustrated in the filter response plots in the Digital Filter section. In addition, noise components are
usually smaller in magnitude than the actual sensor signal. Therefore, using a first-order RC filter with a cutoff
frequency set at the output data rate or 10 times higher is generally a good starting point for a system design.
Internal to the device, prior to the PGA inputs, is an EMI filter; see 图 50. The cutoff frequency of this filter is
approximately 40 MHz and helps reject high-frequency interference.
10.1.3 External Reference and Ratiometric Measurements
The full-scale range of the ADS124S0x is defined by the reference voltage and the PGA gain
(FSR = ±VREF / Gain). An external reference can be used instead of the integrated 2.5-V reference to adapt the
FSR to the specific system needs. An external reference must be used if VIN > 2.5 V. For example, an external
5-V reference and an AVDD = 5 V are required in order to measure a single-ended signal that can swing
between 0 V and 5 V.
The reference inputs of the device also allow the implementation of ratiometric measurements. In a ratiometric
measurement, the same excitation source that is used to excite the sensor is also used to establish the reference
for the ADC. As an example, a simple form of a ratiometric measurement uses the same current source to excite
both the resistive sensor element (such as an RTD) and another resistive reference element that is in series with
the element being measured. The voltage that develops across the reference element is used as the reference
source for the ADC. Because current noise and drift are common to both the sensor measurement and the
reference, these components cancel out in the ADC transfer function. The output code is only a ratio of the
sensor element and the value of the reference resistor. The value of the excitation current source itself is not part
of the ADC transfer function.
The example in the Typical Application section describes a system that uses a ratiometric measurement. One
excitation current source is used to drive a reference resistor and an RTD. The ADC measurement represents a
ratiometric measurement between the RTD value and a known reference resistor value.
10.1.4 Establishing a Proper Input Voltage
The ADS124S0x can be used to measure various types of input signal configurations: single-ended, pseudo-
differential, and fully-differential signals (which can be either unipolar or bipolar). However, configuring the device
properly for the respective signal type is important.
Signals where the negative analog input is fixed and referenced to analog ground (VAINN = 0 V) are commonly
called single-ended signals. The input voltage of a single-ended signal consequently varies between 0 V and VIN.
If the PGA is disabled and bypassed, the input voltage of the ADS124S08 can be as low as 50 mV below AVSS
and as large as 50 mV above AVDD. Therefore, set the PGA_EN bits to 10 in the gain setting register (03h) to
measure single-ended signals when a unipolar analog supply is used (AVSS = 0 V). Only a gain of 1 is possible
in this configuration. Measuring a 0-mA to 20-mA or 4-mA to 20-mA signal across a load resistor of 100 Ω
referenced to GND is a typical example. The ADS124S0x can directly measure the signal across the load
resistor using a unipolar supply, the internal 2.5-V reference, and gain = 1 when the PGA is bypassed.
If gain is needed to measure a single-ended signal, the PGA must be enabled. In this case, a bipolar supply is
required for the ADS124S0x to meet the input voltage requirement of the PGA. Signals where the negative
analog input (AINN) is fixed at a voltage other the 0 V are referred to as pseudo-differential signals. The input
voltage of a pseudo-differential signal varies between VAINN and VAINN + VIN.
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Fully-differential signals in contrast are defined as signals having a constant common-mode voltage where the
positive and negative analog inputs swing 180° out-of-phase but have the same amplitude.
The ADS124S0x can measure pseudo-differential and fully-differential signals both with the PGA enabled or
bypassed. However, the PGA must be enabled in order to measure any input with a gain greater than 1. The
input voltage must meet the input and output voltage restrictions of the PGA, as explained in the PGA Input-
Voltage Requirements section when the PGA is enabled. Setting the input voltage at or near (AVSS + AVDD) / 2
in most cases satisfies the PGA input voltage requirements.
Signals where both the positive and negative inputs are always ≥ 0 V are called unipolar signals. These signals
can in general be measured with the ADS124S0x using a unipolar analog supply (AVSS = 0 V). As mentioned
previously, the PGA must be bypassed in order to measure single-ended, unipolar signals when using a unipolar
supply.
A signal is called bipolar when either the positive or negative input can swing below 0 V. A bipolar analog supply
(such as AVDD = 2.5 V, AVSS = –2.5 V) is required in order to measure bipolar signals with the ADS124S0x. A
typical application task is measuring a single-ended, bipolar, ±10-V signal where AINN is fixed at 0 V and AINP
swings between –10 V and 10 V. The ADS124S0x cannot directly measure this signal because the 10-V signal
exceeds the analog power-supply limits. However, one possible solution is to use a bipolar analog supply (AVDD
= 2.5 V, AVSS = –2.5 V), gain = 1, and a resistor divider in front of the ADS124S0x. The resistor divider must
divide the voltage down to ≤ ±2.5 V to be able to measure the voltage using the internal 2.5-V reference.
10.1.5 Unused Inputs and Outputs
To minimize leakage currents on the analog inputs, leave unused analog and reference inputs floating, or
connect the inputs to mid-supply or to AVDD. Connecting unused analog or reference inputs to AVSS is possible
as well, but can yield higher leakage currents than the previously mentioned options. REFN0 is an exception; this
pin can be accidently shorted to AVSS through the internal low-side switch. Leave the REFN0 pin floating when
not in use or tie the pin to AVSS.
GPIO pins operate on levels based on the analog supply. Do not float GPIO pins that are configured as digital
inputs. Tie unused GPIO pins that are configured as digital inputs to the appropriate levels, AVDD or AVSS,
including when in power-down mode. Tie unused GPIO output pins to AVSS through a pulldown resistor and set
the output to 0 in the GPIO data register. For unused GPIO pins on the ADS124S06, leave the GPIOCON
register set to the default register values and connect these GPIO pins in the same manner as for an unused
analog input.
Do not float unused digital inputs; excessive power-supply leakage current can result. Tie all unused digital
inputs to the appropriate levels, IOVDD or DGND, even when in power-down mode. Connections for unused
digital inputs are listed below.
•
•
•
•
•
Tie the CS pin to DGND if CS is not used
Tie the CLK pin to DGND if the internal oscillator is used
Tie the START/SYNC pin to DGND to control conversions by commands
Tie the RESET pin to IOVDD if the RESET pin is not used
If the DRDY output is not used, leave the DRDY pin unconnected or tie the DRDY pin to IOVDD using a weak
pullup resistor
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10.1.6 Pseudo Code Example
The following list shows a pseudo code sequence with the required steps to set up the device and the
microcontroller that interfaces to the ADC in order to take subsequent readings from the ADS124S0x in
continuous conversion mode. The dedicated DRDY pin is used to indicate availability of new conversion data.
Power-up so that all supplies reach minimum operating levels;
Delay for a minimum of 2.2 ms to allow power supplies to settle and power-up reset to complete;
Configure the SPI interface of the microcontroller to SPI mode 1 (CPOL = 0, CPHA =1);
If the CS pin is not tied low permanently, configure the microcontroller GPIO connected to CS as an
output;
Configure the microcontroller GPIO connected to the DRDY pin as a falling edge triggered interrupt
input;
Set CS to the device low;
Delay for a minimum of td(CSSC)
Send the RESET command (06h) to make sure the device is properly reset after power-up; //Optional
Delay for a minimum of 4096 · tCLK
;
;
Read the status register using the RREG command to check that the RDY bit is 0; //Optional
Clear the FL_POR flag by writing 00h to the status register; //Optional
Write the respective register configuration with the WREG command;
For verification, read back all configuration registers with the RREG command;
Send the START command (08h) to start converting in continuous conversion mode;
Delay for a minimum of td(SCCS)
;
Clear CS to high (resets the serial interface);
Loop
{
Wait for DRDY to transition low;
Take CS low;
Delay for a minimum of td(CSSC)
;
Send the RDATA command;
Send 24 SCLK rising edges to read out conversion data on DOUT/DRDY;
Delay for a minimum of td(SCCS)
;
Clear CS to high;
}
Take CS low;
Delay for a minimum of td(CSSC)
Send the STOP command (0Ah) to stop conversions and put the device in standby mode;
;
Delay for a minimum of td(SCCS)
;
Clear CS to high;
90
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10.2 Typical Application
图 113 shows a fault-protected, filtered, 3-wire RTD application circuit with hardware-based, lead-wire
compensation. Two IDAC current sources provide the lead-wire compensation. One IDAC current source
(IDAC1) provides excitation to the RTD element. The ADC reference voltage (pins AIN6 and AIN7) is derived
from the voltage across resistor RREF sourcing the same IDAC1 current, providing ratiometric cancellation of
current-source drift. The other current source (IDAC2) has the same current setting, providing cancellation of
lead-wire resistance by generating a voltage drop across lead-wire resistance RLEAD2 equal to the voltage drop of
RLEAD1. Because the RRTD voltage is measured differentially at ADC pins AIN1 and AIN2, the voltages across the
lead wire resistance cancel. Resistor RBIAS level-shifts the RTD signal to within the ADC specified input range.
The current sources are provided by two additional pins (AIN5 and AIN3) that connect to the RTD through
blocking diodes. The additional pins are used to route the RTD excitation currents around the input filter
resistors, avoiding the voltage drop otherwise caused by the filter resistors RF1 and RF4. The diodes protect the
ADC inputs in the event of a miswired connection. The input filter resistors limit the input fault currents flowing
into the ADC.
5 V
3.3 V
0.1 mF
330 nF
AVDD
DVDD
IOVDD
AVDD
IDAC1
IIDAC1
AIN5
(IDAC1)
500 ꢁA
ADS124S08
CCM4
RF4
RF3
AIN6
REFOUT
1 mF
(REFP1)
Reference
Mux
2.5-V
Reference
RREF
CDIF2
AIN7
(REFN1)
CCM3
REFCOM
Reference
Detection
Reference
Buffers
3-Wire RTD
RLEAD1
CCM2
START/SYNC
RESET
CS
RF2
RF1
AIN1
(AINP)
Serial
Interface
and
Input
Mux
24-Bit
ûꢀ ADC
Digital
Filter
CDIF1
PGA
RRTD
DIN
RLEAD2
AIN2
DOUT/DRDY
SCLK
DRDY
Control
(AINN)
CCM1
PGA Rail
Detection
AVDD
IDAC2
IIDAC2
AIN3
4.096-MHz
Oscillator
(IDAC2)
CLK
500 ꢁA
AVSS-SW
AVSS
DGND
RLEAD3
IIDAC1 + IIDAC2
Copyright © 2017, Texas Instruments Incorporated
RBIAS
图 113. 3-Wire RTD Application
10.2.1 Design Requirements
表 44 shows the design requirements of the 3-wire RTD application.
表 44. Design Requirements
DESIGN PARAMETER
ADC supply voltage
RTD sensor type
VALUE
4.75 V (minimum)
3-wire Pt100
20 Ω to 400 Ω
0 Ω to 10 Ω
1 mW
RTD resistance range
RTD lead resistance range
RTD self heating
Accuracy(1)
±0.05 Ω
(1) TA = 25°C. After offset and full-scale calibration.
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10.2.2 Detailed Design Procedure
The key considerations in the design of a 3-wire RTD circuit are the accuracy, the lead wire compensation, and
the sensor self-heating. As the design values of 表 45 show, several values of excitation currents are available.
The resolution is expressed in units of noise-free resolution (NFR). Noise-free resolution is resolution with no
code flicker. The selection of excitation currents trades off resolution against sensor self-heating. In general,
measurement resolution improves with increasing excitation current. Increasing the excitation current beyond
1000 µA results in no further improvement in resolution for this example circuit. The design procedure is based
on a 500-µA excitation current, because this level of current results in very low sensor self-heating
(0.4 mW).
表 45. RTD Circuit Design Parameters
(1)
(2)
(3)
(4)
(5)
(6)
(7)
IIDAC
(µA)
NFR
(bits)
PRTD
(mW)
VRTD
(V)
Gain
(V/V)
VREFMIN
(V)
VREF
(V)
RREF
(kΩ)
VAINNLIM
(V)
VAINPLIM
(V)
RBIAS
(kΩ)
VRTDN
(V)
VRTDP
(V)
VIDAC1
(V)
50
16.8
17.8
18.8
19.1
18.9
19.3
19.1
18.3
0.001
0.004
0.025
0.100
0.225
0.400
0.900
1.600
0.02
0.04
0.10
0.20
0.30
0.40
0.60
0.80
32
32
16
8
0.64
1.28
1.60
1.60
1.20
1.60
1.20
0.80
0.70
1.41
1.76
1.76
1.32
1.76
1.32
0.90
18
0.6
0.9
1.1
1.0
0.8
0.9
0.6
0.3
4.1
3.8
3.7
3.8
4.0
3.9
4.2
4.5
7.10
5.10
2.30
1.10
0.57
0.50
0.23
0.10
0.7
1.0
1.2
1.1
0.9
1.0
0.7
0.4
0.7
1.1
1.3
1.3
1.2
1.4
1.3
1.2
1.9
2.8
3.3
3.4
2.8
3.5
3.0
2.4
100
14.1
7.04
3.52
1.76
1.76
0.88
0.45
250
500
750
4
1000
1500
2000
4
2
1
(1) VREFMIN is the minimum reference voltage required by the design.
(2) VREF is the design target reference voltage allowing for 10% overrange.
(3) VAINNLIM is the absolute minimum input voltage required by the ADC.
(4) VAINPLIM is the absolute maximum input voltage required by the ADC.
(5) VRTDN is the design target negative input voltage.
(6) VRTDP is the design target positive input voltage.
(7) VIDAC1 is the design target IDAC1 loop voltage.
Initially, RLEAD1 and RLEAD2 are considered to be 0 Ω. Route the IDAC1 current through the external reference
resistor, RREF. IDAC1 generates the ADC reference voltage, VREF, across the reference resistor. This voltage is
defined by 公式 12:
VREF = IIDAC1 · RREF
(12)
Route the second current (IDAC2) to the second RTD lead.
Program the IDAC value by using the IDACMAG register; however, only the IDAC1 current flows through the
reference resistor and RTD. The IDAC1 current excites the RTD to produce a voltage proportional to the RTD
resistance. The RTD voltage is defined by 公式 13:
VRTD = RRTD · IIDAC1
(13)
The ADC amplifies the RTD signal voltage (VRTD) and measures the resulting voltage against the reference
voltage to produce a proportional digital output code, as shown in 公式 14 through 公式 16.
Code ∝ VRTD · Gain / VREF
(14)
(15)
(16)
Code ∝ (RRTD · IIDAC1) · Gain / (IIDAC1 · RREF
)
Code ∝ (RRTD · Gain) / RREF
As shown in 公式 16, the RTD measurement depends on the value of the RTD, the PGA gain, and the reference
resistor RREF, but not on the IDAC1 value. Therefore, the absolute accuracy and temperature drift of the
excitation current does not matter.
The second excitation current (IDAC2) provides a second voltage drop across the second RTD lead resistance,
RLEAD2. The second voltage drop compensates the voltage drop caused by IDAC1 and RLEAD1. The leads of a 3-
wire RTD typically have the same length; therefore, the lead resistance is typically identical. Taking the lead
resistance into account (RLEADx ≠ 0), the differential voltage (VIN) across ADC inputs AIN8 and AIN9 is shown in
公式 17:
VIN = IIDAC1 · (RRTD + RLEAD1) – IIDAC2 · RLEAD2
(17)
If RLEAD1 = RLEAD2 and IIDAC1 = IIDAC2, the expression for VIN reduces to 公式 18:
VIN = IIDAC1 · RRTD
(18)
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In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is
compensated as long as the lead resistance values and the IDAC values are matched.
Using 公式 13, the value of RTD resistance (400 Ω, maximum) and the excitation current (500 µA) yields an RTD
voltage of VRTD = 500 µA · 400 Ω = 0.2 V. Use the maximum gain of 8 in order to limit the corresponding loop
voltage of IDAC1. Gain = 8 requires a minimum reference voltage VREFMIN = 0.2 V · 8 = 1.6 V. To provide margin
for the ADC operating range, increase the target reference voltage by 10% (VREF = 1.6 V · 1.1 = 1.76 V).
Calculate the value of the reference resistor, as shown in 公式 19:
RREF = VREF / IIDAC1 = 1.76 V / 500 µA = 3.52 kΩ
(19)
For this example application, 3.5 kΩ is chosen for RREF. For best results, use a precision reference resistor RREF
with a low temperature drift (< 10 ppm/°C). Any change in RREF is reflected in the measurement as a gain error.
The next step in the design is determining the value of the RBIAS resistor, in order to level shift the RTD voltage to
meet the ADC absolute input-voltage specification. The required level-shift voltage is determined by calculating
the minimum absolute voltage (VAINNLIM) as shown in 公式 20:
AVSS + 0.15 + VRTDMAX · (Gain – 1) / 2 ≤ VAINNLIM
where
•
•
•
VRTDMAX = maximum differential RTD voltage = 0.2 V
Gain = 8
AVSS = 0 V
(20)
The result of the equation requires a minimum absolute input voltage (VRTDN) > 0.85 V. Therefore, the RTD
voltage must be level shifted by a minimum of 0.85 V. To meet this requirement, a target level-shift value of 1 V
is chosen to provide extra margin. Calculate the value of RBIAS as shown in 公式 21:
RBIAS= VAINN / (IIDAC1+ IIDAC2) = 1 V / ( 2 · 500 µA) = 1 kΩ
(21)
After the level-shift voltage is determined, verify that the positive RTD voltage (VRTDP) is less than the maximum
absolute input voltage (VAINPLIM), as shown in 公式 22:
VAINPLIM ≤ AVDD – 0.15 – VRTDMAX · (Gain – 1) / 2
where
•
•
•
VRTDMAX = maximum differential RTD voltage = 0.2 V
Gain = 8
AVDD = 4.75 V (minimum)
(22)
(23)
Solving 公式 22 results in a required VRTDP of less than 3.9 V. Calculate the VRTDP input voltage by 公式 23:
VAINP = VRTDN + IIDAC1 · (RRTD + RLEAD1) = 1 V + 500 µA · (400 Ω + 10 Ω) = 1.2 V
Because 1.2 V is less than the 3.9-V maximum input voltage limit, the absolute positive and negative RTD
voltages are within the ADC specified input range.
The next step in the design is to verify that the IDACs have enough voltage headroom (compliance voltage) to
operate. The loop voltage of the excitation current must be less than the supply voltage minus the specified IDAC
compliance voltage. Calculate the voltage drop developed across each IDAC current path to AVSS. In this circuit,
IDAC1 has the largest voltage drop developed across its current path. The IDAC1 calculation is sufficient to
satisfy IDAC2 because the IDAC2 voltage drop is always less than IDAC1 voltage drop. The sum of voltages in
the IDAC1 loop is shown in 公式 24:
VIDAC1 = [(IIDAC1 + IIDAC2) · (RLEAD3 + RBIAS)] + [IIDAC1 · (RRTD + RLEAD1 + RREF)] + VD
where
•
VD = external blocking diode voltage
(24)
The equation results in a loop voltage of VIDAC1 = 3.0 V. The worst-case current source compliance voltage is:
(AVDD – 0.4 V) = (4.75 V – 0.4 V) = 4.35 V. The VIDAC1 loop voltage is less than the specified current source
compliance voltage (3.0 V < 4.35 V).
Many applications benefit from using an analog filter at the inputs to remove noise and interference from the
signal. Filter components are placed on the ADC inputs (RF1, RF2, CDIF1, CCM1, and CCM2), as well as on the
reference inputs (RF3, RF4, CDIF2, CCM3, and CCM4). The filters remove both differential and common-mode noise.
The application shows a differential input noise filter formed by RF1, RF2 and CDIF1, with additional differential
mode capacitance provided by the common-mode filter capacitors, CCM1 and CCM2. Calculate the differential
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–3-dB cutoff frequency as shown in 公式 25:
fDIF = 1 / [2π · (RF1 + RF2) · (CDIF1 + CCM1|| CCM2)]
(25)
The common-mode noise filter is formed by components RF1, RF2, CCM1, and CCM2. Calculate the common-mode
signal –3-dB cutoff frequency, as shown in 公式 26:
fCM = 1 / (2π · RF1 · CCM1) = 1 / (2π · RF2 · CCM2
)
(26)
Mismatches in the common-mode filter components convert common-mode noise into differential noise. To
reduce the effect of mismatch, use a differential mode filter with a corner frequency that is at least 10 times lower
than the common-mode filter corner frequency. The low-frequency differential filter removes the common-mode
converted noise. The filter resistors (RFx) also serve as current-limiting resistors. These resistors limit the current
into the analog inputs (AINx) of the device to safe levels when an overvoltage occurs on the inputs.
Filter resistors lead to an offset voltage error due to the dc input current leakage flowing into and out of the
device. Remove this voltage error by system offset calibration. Resistor values that are too large generate
excess thermal noise and degrade the overall noise performance. The recommended range of the filter resistor
values is 100 Ω to 10 kΩ. The properties of the capacitors are important because the capacitors are connected to
the signal; use high-quality C0G ceramics or film-type capacitors.
For consistent noise performance across the full range of RTD measurements, match the corner frequencies of
the input and reference filter. See the RTD Ratiometric Measurements and Filtering Using the ADS1148 and
ADS1248 Application Report (SBAA201) for detailed information on matching the input and reference filter.
10.2.2.1 Register Settings
The register settings for this design are shown in 表 46.
表 46. Register Settings
REGISTER
02h
NAME
INPMUX
PGA
SETTING
12h
DESCRIPTION
Select AINP = AIN1 and AINN = AIN2
03h
0Bh
PGA enabled, PGA Gain = 8
04h
DATARATE
14h
Continuous conversion mode, low-latency filter, 20-SPS data rate
Positive and negative reference buffers enabled, REFP1 and
REFN1 reference inputs selected, internal reference always on
05h
REF
06h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
IDACMAG
IDACMUX
VBIAS
05h
35h
00h
10h
xxh
xxh
xxh
xxh
xxh
xxh
00h
00h
IDAC magnitude set to 500 µA
IDAC2 set to AIN3, IDAC1 set to AIN5
SYS
OFCAL0(1)
OFCAL1
OFCAL2
FSCAL0(1)
FSCAL1
FSCAL2
GPIODAT
GPIOCON
(1) A two-point offset and gain calibration removes errors from the RREF tolerance. The results are used for the OFC and FSC registers.
10.2.3 Application Curves
To test the accuracy of the acquisition circuit, a series of calibrated high-precision discrete resistors are used as
an input to the system. Measurements are taken at TA = 25°C. 图 114 displays the resistance measurement over
an input span from 20 Ω to 400 Ω. Any offset error is generally attributed to the offset of the ADC, and the gain
error can be attributed to the accuracy of the RREF resistor and the ADC. The RREF value is also calibrated to
reduce the gain error contribution.
94
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Precision temperature measurement applications are typically calibrated to remove the effects of gain and offset
errors that generally dominate the total system error. The simplest calibration method is a linear, or two-point
calibration that applies an equal and opposite gain and offset term to cancel the measured system gain and
offset error. In this particular tested application, the gain and offset error was very small, and did not require
additional calibration other than the self offset and gain calibration provided by the device. The resulting
measured resistance error is shown in 图 115.
The results in 图 115 are converted to temperature accuracy by dividing the results by the RTD sensitivity (α) at
the measured resistance. Over the full resistance input range, the maximum total measured error is ±0.00929 Ω.
公式 27 uses the measured resistance error and the RTD sensitivity at 0°C to calculate the measured
temperature accuracy.
Error (°C) = Error (Ω) / α@0°C = ±0.00929 Ω / 0.39083 Ω / °C = ±0.024°C
(27)
图 116 displays the calculated temperature accuracy of the circuit assuming a linear RTD resistance to
temperature response. This figure does not include any linearity compensation of the RTD.
0.002
0
8000000
6000000
4000000
2000000
0
-0.002
-0.004
-0.006
-0.008
-0.01
0
50
100 150 200 250 300 350 400 450
0
50
100 150 200 250 300 350 400 450
Resistance (W)
Resistance (W)
图 114. ADC Output Code vs Equivalent RTD Resistance
图 115. Measured Resistance Error vs Equivalent RTD
Resistance
0.005
0
-0.005
-0.01
-0.015
-0.02
-0.025
0
50
100 150 200 250 300 350 400 450
Resistance (W)
图 116. Equivalent Temperature Error vs Equivalent RTD Resistance
10.3 Do's and Don'ts
•
•
•
•
Do partition the analog, digital, and power-supply circuitry into separate sections on the PCB.
Do use a single ground plane for analog and digital grounds.
Do place the analog components close to the ADC pins using short, direct connections.
Do keep the SCLK pin free of glitches and noise.
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Do's and Don'ts (接下页)
•
Do verify that the analog input voltages are within the specified PGA input voltage range under all input
conditions.
•
Do float unused analog input pins to minimize input leakage current on all other analog inputs. Connecting
unused pins to AVDD is the next best option.
•
•
Do provide current limiting to the analog inputs in case overvoltage faults occur.
Do use a low-dropout linear regulator (LDO) to reduce ripple voltage generated by switch-mode power
supplies. Reducing ripple is especially important for AVDD where the supply noise can affect the
performance.
•
•
Don't cross analog and digital signals.
Don't allow the analog and digital power supply voltages to exceed 5.5 V under any condition, including
during power-up and power-down.
96
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ZHCSFP3C –AUGUST 2016–REVISED JUNE 2017
Do's and Don'ts (接下页)
图 117 shows the do's and don'ts of the ADC circuit connections.
INCORRECT
CORRECT
5 V
5 V
AVDD
AVDD
Device
Device
AINP
AINP
AINN
24-bit
ûꢀ ADC
24-bit
ûꢀ ADC
PGA
PGA
AINN
AVSS
0 V
AVSS
0 V
0 V
0 V
Single-ended input, PGA enabled
Single-ended input, PGA bypassed
CORRECT
CORRECT
5 V
2.5 V
AVDD
AVDD
Device
Device
AINP
AINN
AINP
AINN
24-bit
ûꢀ ADC
24-bit
ûꢀ ADC
PGA
PGA
PGA enabled
2.5 V
AVSS
AVSS
-2.5 V
0 V
0 V
Single-ended input, PGA enabled
Single-ended input, PGA enabled
3.3 V
5 V
5 V
3.3 V
INCORRECT
INCORRECT
AVDD
PGA
DVDD
AVDD
PGA
DVDD
24-bit
Device
Device
24-bit
ûꢀ ADC
ûꢀ ADC
AVSS
DGND
AVSS
DGND
Inductive supply or ground connections
AGND/DGND isolation
CORRECT
3.3 V
3.3 V
5 V
2.5 V
CORRECT
AVDD
PGA
DVDD
24-bit
AVDD
DVDD
Device
Device
24-bit
ûꢀ ADC
PGA
ûꢀ ADC
AVSS
DGND
AVSS
-2.5 V
DGND
Low impedance AGND/DGND connection
Low impedance AGND/DGND connection
图 117. Do's and Don'ts Circuit Connections
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11 Power Supply Recommendations
11.1 Power Supplies
The ADS124S0x requires three power supplies: analog (AVDD, AVSS), digital core (DVDD, DGND), and digital
I/O (IOVDD, DGND). The analog power supply can be bipolar (for example, AVDD = 2.5 V, AVSS = –2.5 V) or
unipolar (for example, AVDD = 3.3 V, AVSS = 0 V) and is independent of the digital power supplies. DVDD is
used to power the digital circuits of the devices. IOVDD sets the digital I/O levels (with the exception of the GPIO
levels that are set by the analog supply of AVDD and AVSS). IOVDD must be equal to or larger than DVDD.
11.2 Power-Supply Sequencing
AVDD and DVDD may be powered up in any order. However, IOVDD is recommended to be powered up before
or at the same time as DVDD. If DVDD comes up before IOVDD, a reset of the device using the RESET pin or
the RESET command may be required.
11.3 Power-On Reset
An internal POR is released after all three supplies exceed approximately 1.65 V. Each supply has an individual
POR circuit. A brownout condition on any of the three supplies triggers a reset of the complete device.
11.4 Power-Supply Decoupling
Good power-supply decoupling is important to achieve best performance. AVDD must be decoupled with at least
a 330-nF capacitor to AVSS. DVDD and IOVDD (when not connected to DVDD) must be decoupled with at least
a 0.1-μF capacitor to DGND. 图 118 and 图 119 show typical power-supply decoupling examples for unipolar and
bipolar analog supplies, respectively. Place the bypass capacitors as close to the power-supply pins of the
device as possible using low-impedance connections. Use multi-layer ceramic chip capacitors (MLCCs) that offer
low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling
purposes. To reduce inductance on the supply pins, avoid the use of vias for connecting the capacitors to the
supply pins. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to
ground planes. Connect analog and digital grounds together as close to the device as possible.
1 mF
1 mF
œ2.5 V
24
23
22
21
20
19
18
17
24
23
22
21
20
19
18
17
3.3 V
3.3 V
NC 25
26
DVDD
IOVDD
DGND
16
15
14
13
12
11
10
9
NC 25
DVDD
IOVDD
DGND
16
15
14
13
12
11
10
9
+2.5 V
5 V
AVDD
26
27
28
AVDD
0.1 mF
0.1 mF
330 nF
330 nF
27
28
AVSS
AVSS
AVSS-SW
DRDY
AVSS-SW
DRDY
œ2.5 V
REFN0 29
REFP0 30
DOUT/DRDY
SCLK
REFN0 29
REFP0 30
DOUT/DRDY
SCLK
REFN1/AIN7 31
REFP1/AIN6 32
DIN
REFN1/AIN7 31
REFP1/AIN6 32
DIN
CS
CS
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
图 119. Bipolar Analog Power Supply
图 118. Unipolar Analog Power Supply
98
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12 Layout
12.1 Layout Guidelines
Employing best design practices is recommended when laying out a printed-circuit board (PCB) for both analog
and digital components. This recommendation generally means that the layout separates analog components
[such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital
components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate
arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching
regulators]. An example of good component placement is shown in 图 120. Although 图 120 provides a good
example of component placement, the best placement for each application is unique to the geometries,
components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every
design and careful consideration must always be used when designing with any analog component.
Ground Fill or
Ground Plane
Ground Fill or
Ground Plane
Supply
Generation
Signal
Conditioning
(RC Filters
and
Interface
Transceiver
Device
Microcontroller
Connector
or Antenna
Amplifiers)
Ground Fill or
Ground Plane
Ground Fill or
Ground Plane
图 120. System Component Placement
The following basic recommendations for layout of the ADS124S0x help achieve the best possible performance
of the ADC. A good design can be ruined with a bad circuit layout.
•
Separate analog and digital signals. To start, partition the board into analog and digital sections where the
layout permits. Route digital lines away from analog lines. This prevents digital noise from coupling back into
analog signals.
•
The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but this (splitting) is
not necessary. Place digital signals over the digital plane, and analog signals over the analog plane. As a
final step in the layout, the split between the analog and digital grounds must be connected to together at the
ADC.
•
•
Fill void areas on signal layers with ground fill.
Provide good ground return paths. Signal return currents will flow on the path of least impedance. If the
ground plane is cut or has other traces that block the current from flowing right next to the signal trace,
another path must be found to return to the source and complete the circuit. If forced into a larger path, the
chance that the signal radiates increases. Sensitive signals are more susceptible to EMI interference.
•
•
Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass
capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active
device yields the best results.
Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react
with the input bias current and cause an added error voltage. Reducing the loop area enclosed by the source
signal and the return current reduces the inductance in the path. Reducing the inductance reduces the EMI
pickup and reduces the high-frequency impedance at the input of the device.
•
•
Watch for parasitic thermocouples in the layout. Dissimilar metals going from each analog input to the sensor
can create a parasitic themocouple that can add an offset to the measurement. Differential inputs must be
matched for both the inputs going to the measurement source.
Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best
input combinations for differential measurements use adjacent analog input lines (such as AIN0, AIN1 and
AIN2, AIN3). The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G
(NPO) that have stable properties and low noise characteristics.
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12.2 Layout Example
Reference
input
Differential
input or
Reference
input
Internal plane connected to GND
(DGND = AVSS)
Via connection to power plane
AIN5
Differential
input
AIN8
Differential
input
AIN4
AIN9
1: AINCOM
2: AIN5
24: REFCOM
23: REFOUT
AIN3
22: GPIO0/
AIN8
3: AIN4
Differential
input
21: GPIO1/
AIN9
4: AIN3
20: GPIO2/
AIN10
5: AIN2
AIN2
19: GPIO3/
AIN11
6: AIN1
AIN10
7: AIN0
18: RESET
17: CLK
Differential
input
8: START
AIN11
AIN1
Differential
input
AIN0
Digital
connections
图 121. ADS124S0x Layout Example
100
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13 器件和文档支持
13.1 器件支持
13.1.1 开发支持
ADS1x4S0x 设计计算器
13.2 文档支持
13.2.1 相关文档
请参阅如下相关文档：
•
•
•
《REF50xx 低噪声、极低漂移、高精度电压基准》
《使用 ADS1148 和 ADS1248 进行 RTD 比例测量和滤波的应用报告》
《3 线 RTD 测量系统参考设计（–200°C 至 850°C）》
13.3 相关链接
下面的表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可通过快速访问立刻订
购。
表 47. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
ADS124S06
ADS124S08
13.4 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
13.5 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.6 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 机械、封装和可订购信息
以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据发生变化时，
我们可能不会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS124S06IPBS
ADS124S06IPBSR
ADS124S06IRHBR
ACTIVE
ACTIVE
ACTIVE
TQFP
TQFP
VQFN
PBS
PBS
RHB
32
32
32
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-50 to 125
-50 to 125
-50 to 125
124S06
1000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
124S06
ADS
124S06
ADS124S06IRHBT
ACTIVE
VQFN
RHB
32
250
250
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-50 to 125
ADS
124S06
ADS124S08IPBS
ADS124S08IPBSR
ADS124S08IRHBR
ACTIVE
ACTIVE
ACTIVE
TQFP
TQFP
VQFN
PBS
PBS
RHB
32
32
32
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-50 to 125
-50 to 125
-50 to 125
124S08
1000 RoHS & Green
3000 RoHS & Green
124S08
ADS
124S08
ADS124S08IRHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-50 to 125
ADS
124S08
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS124S06IPBSR
ADS124S06IRHBR
ADS124S06IRHBT
ADS124S08IPBSR
ADS124S08IRHBR
ADS124S08IRHBT
TQFP
VQFN
VQFN
TQFP
VQFN
VQFN
PBS
RHB
RHB
PBS
RHB
RHB
32
32
32
32
32
32
1000
3000
250
330.0
330.0
180.0
330.0
330.0
180.0
16.4
12.4
12.4
16.4
12.4
12.4
7.2
5.3
5.3
7.2
5.3
5.3
7.2
5.3
5.3
7.2
5.3
5.3
1.5
1.1
1.1
1.5
1.1
1.1
12.0
8.0
16.0
12.0
12.0
16.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
8.0
1000
3000
250
12.0
8.0
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS124S06IPBSR
ADS124S06IRHBR
ADS124S06IRHBT
ADS124S08IPBSR
ADS124S08IRHBR
ADS124S08IRHBT
TQFP
VQFN
VQFN
TQFP
VQFN
VQFN
PBS
RHB
RHB
PBS
RHB
RHB
32
32
32
32
32
32
1000
3000
250
350.0
346.0
210.0
350.0
346.0
210.0
350.0
346.0
185.0
350.0
346.0
185.0
43.0
33.0
35.0
43.0
33.0
35.0
1000
3000
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
ADS124S06IPBS
ADS124S08IPBS
PBS
PBS
TQFP
TQFP
32
32
250
250
10 X 25
10 X 25
150
150
315 135.9 7620 12.2
315 135.9 7620 12.2
11.1 11.25
11.1 11.25
Pack Materials-Page 3
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
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PACKAGE OUTLINE
VQFN - 1 mm max height
RHB0032M
PLASTIC QUAD FLATPACK-NO LEAD
A
5.1
4.9
B
5.1
4.9
PIN 1 INDEX AREA
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
ꢀꢀꢀꢁꢂꢃꢄꢂꢃ
9
16
28X 0.5
8
17
SYMM
33
2X
3.5
1
24
0.3
0.2
32X
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.1
0.05
C A B
C
0.5
0.3
32X
4223725/A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RHB0032M
PLASTIC QUAD FLATPACK-NO LEAD
(4.8)
2.1)
(
32
25
32X (0.6)
32X (0.25)
1
24
28X (0.5)
33
SYMM
(4.8)
2X
(0.8)
ꢅꢄꢂꢁꢆ
VIA TYP
8
17
(R0.05) TYP
9
16
2X (0.8)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
EXPOSED
METAL
OPENING
EXPOSED
METAL UNDER
SOLDER MASK
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223725/A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RHB0032M
PLASTIC QUAD FLATPACK-NO LEAD
(4.8)
4X ( 0.94)
32
25
32X (0.6)
32X (0.25)
1
24
28X (0.5)
33
SYMM
(4.8)
2X
(0.57)
METAL
TYP
8
17
(R0.05) TYP
9
16
2X (0.57)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 15X
4223725/A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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