ADS1243SKGD1 [TI]
24-BIT ANALOG-TO-DIGITAL CONVERTER; 24位模拟数字转换器
| 型号： | ADS1243SKGD1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24-BIT ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总40页 (文件大小：514K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS1243-HT
www.ti.com
SBAS525 –DECEMBER 2011
24-BIT ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS1243-HT
1
FEATURES
2
•
24-Bits No Missing Codes
SUPPORTS EXTREME TEMPERATURE
APPLICATIONS
•
Simultaneous 50-Hz and 60-Hz Rejection
(–90 dB Minimum)
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
•
•
•
•
•
•
•
•
•
•
•
0.0025% INL
PGA Gains From 1 to 128
Single-Cycle Settling
Available in Extreme (–55°C/210°C)
Temperature Range(1)
Programmable Data Output Rates
External Differential Reference of 0.1 V to 5 V
On-Chip Calibration
•
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
SPI™ Compatible
Texas Instruments’ high temperature products
utilize highly optimized silicon (die) solutions
with design and process enhancements to
maximize performance over extended
temperatures. All devices are characterized
and qualified for 1000 hours of continuous
operating life at maximum rated temperatures.
2.7 V to 5.25 V Supply Range
600-µW Power Consumption
Up to Eight Input Channels
Up to Eight Data I/O
APPLICATIONS
•
•
•
•
•
•
Down-Hole Drilling
VDD
VREF+
VREF–
XIN
XOUT
High Temperature Environments
Vibration/Modal Analysis
Multi-Channel Data Acquisition
Acoustics/Dynamic Strain Gauges
Pressure Sensors
VDD
Clock Generator
2µA
Offset
DAC
AIN0/D0
AIN1/D1
AIN2/D2
AIN3/D3
AIN4/D4
AIN5/D5
AIN6/D6
AIN7/D7
A = 1:128
PGA
IN+
IN–
2nd-Order
Modulator
Digital
MUX
+
Controller
Registers
BUF
Filter
SCLK
DIN
Serial Interface
2µA
DOUT
GND
CS
GND
PDWN
DRDY
(1) Custom temperature ranges available
DESCRIPTION
The ADS1243 is a precision, wide dynamic range, delta-sigma, analog-to-digital (A/D) converter with 24-bit
resolution operating from 2.7-V to 5.25-V supplies. This delta-sigma, A/D converter provides up to 24 bits of no
missing code performance and effective resolution of 21 bits.
The input channels are multiplexed. Internal buffering can be selected to provide a very high input impedance for
direct connection to transducers or low-level voltage signals. Burnout current sources are provided that allow for
the detection of an open or shorted sensor. An 8-bit digital-to-analog converter (DAC) provides an offset
correction with a range of 50% of the FSR (Full-Scale Range).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
ADS1243-HT
SBAS525 –DECEMBER 2011
www.ti.com
The Programmable Gain Amplifier (PGA) provides selectable gains of 1 to 128 with an effective resolution of 19
bits at a gain of 128. The A/D conversion is accomplished with a second-order delta-sigma modulator and
programmable FIR filter that provides a simultaneous 50-Hz and 60-Hz notch. The reference input is differential
and can be used for ratiometric conversion.
The serial interface is SPI compatible. Up to eight bits of data I/O are also provided that can be used for input or
output. The ADS1243 is designed for high-resolution measurement applications in smart transmitters, industrial
process control, weight scales, chromatography and portable instrumentation.
ORDERING INFORMATION(1)
TA
PACKAGE
JD
ORDERABLE PART NUMBER
TOP-SIDE MARKING
ADS1243SJD
NA
ADS1243SJD
–55°C to 210°C
KGD
ADS1243SKGD1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.3 to 6
UNIT
V
VDD to GND
Input Current
100, Momentary
10, Continuous
GND – 0.5 to VDD + 0.5
–0.3V to VDD + 0.3
–0.3V to VDD + 0.3
215
mA
mA
V
Input Current
AIN
Digital Input Voltage to GND
Digital Output Voltage to GND
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
V
V
°C
°C
°C
–55 to 210
–65 to 100
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
θJC
Junction-to-case thermal resistance
HKJ package
8.1
°C/W
DIGITAL CHARACTERISTICS
VDD 2.7 V to 5.25 V
TA = –55°C to 125°C
TA = 210°C
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Digital Input/Output
Logic Family
CMOS
CMOS
VIH
0.8 ● VDD
VDD 0.8 ● VDD
VDD
V
V
(1)
VIL
GND
0.2 ● VDD
GND
DD – 0.4
GND
0.2 ● VDD
Logic Level
VOH
VOL
IIH
IOH = 1 mA
IOL = 1 mA
VI = VDD
VI = 0
VDD – 0.4
V
V
GND
GND + 0.4
10
GND + 0.4
10
V
µA
µA
Input Leakage
IIL
–10
–10
Master Clock Rate:
fOSC
1
5
1
5
MHz
(1) VIL for XIN is GND to GND + 0.05 V.
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Product Folder Link(s): ADS1243-HT
ADS1243-HT
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SBAS525 –DECEMBER 2011
DIGITAL CHARACTERISTICS (continued)
VDD 2.7 V to 5.25 V
TA = –55°C to 125°C
TA = 210°C
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Master Clock Period:
tOSC
1/fOSC
200
1000
200
1000
ns
ELECTRICAL CHARACTERISTICS: VDD = 5 V
All specifications VDD = 5 V, fMOD = 19.2 kHz, PGA = 1, Buffer ON, fDATA = 15 Hz,
VREF ≡ (REF IN+) – (REF IN–) = 2.5 V, unless otherwise specified.
TA = –55°C to 125°C
TA = 210°C
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
ANALOG INPUT (AIN0 – AIN7)
Analog Input Range
Buffer OFF
GND – 0.1
VDD + 0.1
GND – 0.1
VDD + 0.1
V
V
Buffer ON
GND + 0.05
V
DD – 1.5 GND + 0.05
±VREF/PGA
±VREF
V
DD – 1.5
±VREF/PGA
±VREF
(In+) – (In–),
See Block Diagram,
RANGE = 0
V
V
Full-Scale Input Range
/
/
RANGE = 1
(2 ● PGA)
(2 ● PGA)
Buffer OFF
Buffer ON
5/PGA
5
12/PGA
8
MΩ
GΩ
Hz
Differential Input Impedance
fDATA = 3.75 Hz –3 dB
1.65
3.44
14.6
Bandwidth fDATA = 7.50 Hz –3 dB
Hz
fDATA = 15 Hz
–3 dB
Hz
Programmable Gain
Amplifier
User-Selectable Gain Ranges
1
128
1
128
Input Capacitance
Input Leakage Current
Burnout Current Sources
OFFSET DAC
9
5
2
25
6
pF
pA
µA
Modulator OFF, T = 25°C
±VREF
(2 ● PGA)
/
±VREF
(2 ● PGA)
/
RANGE = 0
RANGE = 1
V
V
Offset DAC Range
±VREF
(4 ● PGA)
/
±VREF /
(4 ● PGA)
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
SYSTEM PERFORMANCE
Resolution
8
8
Bits
%
±10
±15
1
2.2
ppm/°C
No Missing Codes
End Point Fit
24
24
Bits
Integral Nonlinearity
±0.0015
±0.0018 % of FS
ppm of
FS
Offset Error(1)
Offset Drift(1)
7.5
15
ppm of
FS/°C
0.02
0.04
Gain Error(1)
Gain Error Drift(1)
0.005
0.5
0.100
1.118
%
ppm°°C
dB
at DC
100
94
Common-Mode Rejection
fCM = 60 Hz, fDATA = 15 Hz
fCM = 50 Hz, fDATA = 15 Hz
fSIG = 50 Hz, fDATA = 15 Hz
fSIG = 60 Hz, fDATA = 15 Hz
130
120
100
100
100
100
95
dB
dB
dB
Normal-Mode Rejection
Output Noise
95
dB
See Typical Characteristics
(1) Calibration can minimize these errors.
Copyright © 2011, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS: VDD = 5 V (continued)
All specifications VDD = 5 V, fMOD = 19.2 kHz, PGA = 1, Buffer ON, fDATA = 15 Hz,
VREF ≡ (REF IN+) – (REF IN–) = 2.5 V, unless otherwise specified.
TA = –55°C to 125°C
TA = 210°C
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
at DC,
dB = –20 log(ΔVOUT /VDD
Power-Supply Rejection
80
95
79
95
dB
(2)
)
VOLTAGE REFERENCE INPUT
Reference Input Range
REF IN+, REF IN–
0
0.1
0.1
VDD
2.6
0
0.1
0.1
VDD
2.6
V
V
VREF ≡ (REF IN+) – (REF IN–),
RANGE = 0
2.5
2.5
VREF
RANGE = 1
VDD
VDD
V
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
at DC
120
120
1.3
98
95
10
dB
dB
µA
fVREFCM = 60 Hz, fDATA = 15 Hz
VREF = 2.5 V
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
VDD
4.75
5.25
375
4.75
5.25
480
V
µA
µA
µA
µA
µA
µA
nA
mW
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
SLEEP Mode
240
450
290
960
60
250
630
350
1200
80
800
940
425
585
Current
1400
2050
Read Data Continuous Mode
PDWN
230
0.5
1.2
350
10
Power Dissipation
PGA = 1, Buffer OFF
1.9
1.3
2.52
(2) ΔVOUT is a change in digital result.
(3) 12-pF switched capacitor at fSAMP clock frequency.
ELECTRICAL CHARACTERISTICS: VDD = 3 V
All specifications VDD = 3 V, fMOD = 19.2 kHz, PGA = 1, Buffer ON, fDATA = 15 Hz,
VREF ≡ (REF IN+) – (REF IN–) = 1.25 V, unless otherwise specified.
TA = –55°C to 125°C
TA = 210°C
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
ANALOG INPUT (AIN0 – AIN7)
Buffer OFF
GND – 0.1
VDD + 0.1
GND – 0.1
VDD + 0.1
V
V
Analog Input Range
GND +
0.05
Buffer ON
VDD – 1.5 GND + 0.05
VDD – 1.5
(In+) – (In–), See Block
Diagram, RANGE = 0
±VREF
PGA
/
±VREF
PGA
/
V
V
Full-Scale Input Voltage
Range
±VREF
(2 • PGA)
/
±VREF/
(2 • PGA)
RANGE = 1
Buffer OFF
Buffer ON
5/PGA
5
10/PGA
8
MΩ
GΩ
Hz
Input Impedance
fDATA = 3.75 Hz –3 dB
1.65
3.44
14.6
Bandwidth fDATA = 7.50 Hz –3 dB
Hz
fDATA = 15 Hz
Programmable Gain
–3 dB
Hz
User-Selectable Gain Ranges
1
128
1
128
Amplifier
Input Capacitance
Input Leakage Current
Burnout Current Sources
OFFSET DAC
9
5
2
25
6
pF
pA
µA
Modulator OFF, T = 25°C
±VREF
(2 ● PGA)
/
±VREF
(2 ● PGA)
/
RANGE = 0
RANGE = 1
V
V
Offset DAC Range
±VREF
(4 ● PGA)
/
±VREF
(4 ● PGA)
/
4
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ADS1243-HT
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SBAS525 –DECEMBER 2011
ELECTRICAL CHARACTERISTICS: VDD = 3 V (continued)
All specifications VDD = 3 V, fMOD = 19.2 kHz, PGA = 1, Buffer ON, fDATA = 15 Hz,
VREF ≡ (REF IN+) – (REF IN–) = 1.25 V, unless otherwise specified.
TA = –55°C to 125°C
TA = 210°C
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
SYSTEM PERFORMANCE
Resolution
8
8
Bits
%
±10
±12
1
2
ppm/°C
No Missing Codes
24
24
Bits
Integral Nonlinearity
End Point Fit
±0.0015
±0.0025 % of FS
ppm of
FS
Offset Error(1)
Offset Drift(1)
75
40
ppm of
FS/°C
0.02
0.20
Gain Error(1)
Gain Error Drift(1)
0.005
0.5
0.1
%
ppm/°C
dB
1.118
at DC
100
87
Common-Mode Rejection
fCM = 60 Hz, fDATA = 15 Hz
fCM = 50 Hz, fDATA = 15 Hz
fSIG = 50 Hz, fDATA = 15 Hz
fSIG = 60 Hz, fDATA = 15 Hz
130
120
100
100
98
95
90
90
dB
dB
dB
Normal-Mode Rejection
dB
Output Noise
See Typical Characteristics
at DC,
dB = –20 log(ΔVOUT /VDD
Power-Supply Rejection
80
95
75
90
dB
(2)
)
VOLTAGE REFERENCE INPUT
Reference Input Range
REF IN+, REF IN–
0
0.1
0.1
VDD
1.30
VDD
0
0.1
0.1
VDD
1.30
2.6
V
V
VREF ≡ (REF IN+) –
(REF IN–), RANGE = 0
1.25
1.25
VREF
RANGE = 1
at DC
V
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
120
120
1.3
95
93
8
dB
fVREFCM = 60 Hz,
fDATA = 15 Hz
dB
VREF = 1.25 V
µA
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
VDD
2.7
3.3
375
2.7
3.3
480
V
µA
µA
µA
µA
µA
µA
nA
mW
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
SLEEP Mode
190
460
240
870
75
200
600
350
1200
110
250
7.5
700
940
375
585
Current
1325
1800
Read Data Continuous Mode
PDWN = 0
113
0.5
0.6
Power Dissipation
PGA = 1, Buffer OFF
1.2
0.66
1.58
(1) Calibration can minimize these errors.
(2) ΔVOUT is a change in digital result.
(3) 12-pF switched capacitor at fSAMP clock frequency.
Copyright © 2011, Texas Instruments Incorporated
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SBAS525 –DECEMBER 2011
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10,000,000
1,000,000
100,000
10,000
1000
80
100
120
140
160
180
200
220
Continuous TJ (°C)
(1) See data sheet for absolute maximum and minimum recommended operating conditions.
(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3) The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
Figure 1. ADS1243-HT Operating Life Derating Chart
6
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SBAS525 –DECEMBER 2011
PIN CONFIGURATION
CDIP PACKAGE
(TOP VIEW)
VDD
XIN
XOUT
1
2
3
4
5
6
7
8
9
20 DRDY
19 SCLK
18 DOUT
PDWN
VREF+
17 DIN
16 CS
VREF–
15 GND
AIN0/D0
AIN1/D1
AIN4/D4
14 AIN3/D3
13 AIN2/D2
12 AIN7/D7
11 AIN6/D6
AIN5/D5 10
PIN ASSIGNMENTS
PIN #
1
NAME
VDD
DESCRIPTION
Power Supply
Clock Input
2
XIN
3
XOUT
Clock Output, used with crystal or ceramic resonator.
4
PDWN
VREF+
VREF–
AIN0/D0
AIN1/D1
AIN4/D4
AIN5/D5
AIN6/D6
AIN7/D7
AIN2/D2
AIN3/D3
GND
Active LOW. Power Down. The power down function shuts down the analog and digital circuits.
Positive Differential Reference Input
Negative Differential Reference Input
Analog Input 0/Data I/O 0
5
6
7
8
Analog Input 1/Data I/O 1
9
Analog Input 4/Data I/O 4
10
11
12
13
14
15
16
17
18
19
20
Analog Input 5/Data I/O 5
Analog Input 6/Data I/O 6
Analog Input 7/Data I/O 7
Analog Input 2/Data I/O 2
Analog Input 3/Data I/O 3
Ground
CS
Active LOW, Chip Select
DIN
Serial Data Input, Schmitt Trigger
Serial Data Output
DOUT
SCLK
DRDY
Serial Clock, Schmitt Trigger
Active LOW, Data Ready
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SBAS525 –DECEMBER 2011
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BARE DIE INFORMATION
BACKSIDE
POTENTIAL
BOND PAD
METALLIZATION COMPOSITION
DIE THICKNESS
BACKSIDE FINISH
Silicon with backgrind
15 mils
GND
AlCu
Table 1. Bond Pad Coordinates in Microns(1)
DISCRIPTION
PAD NUMBER
X MIN
1268.55
1030.45
692.45
450.05
6.45
Y MIN
2471.55
2471.55
2471.55
2471.55
2016.65
1721.75
1468.60
1224.80
929.95
655.20
373.25
3.55
X MAX
1478.15
1132.45
902.05
Y MAX
2572.55
2572.55
2572.55
2572.55
2118.65
1823.75
1570.60
1326.80
1031.95
757.20
VDD
1
Connect to substrate
2
Connect to substrate
XIN
3
4
552.05
XOUT
5
107.45
NC
6
6.45
107.45
NC
7
6.45
107.45
PDWN
NC
8
6.45
107.45
9
6.45
107.45
VREF+
VREF-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
6.45
107.45
6.45
107.45
475.25
AIN0/D0
AIN1/D1
AIN4/D4
AIN5/D5
AIN6/D6
AIN7/D7
AIN2/D2
AIN3/D3
NC
361.15
636.45
911.70
1186.85
1466.25
1742.50
2017.60
2292.75
2608.70
2608.75
2608.70
2608.75
2608.70
2608.70
2608.70
2608.70
2234.80
1931.10
1637.90
462.15
105.55
3.55
737.45
105.55
3.55
1012.70
1287.85
1567.25
1843.50
2118.60
2393.75
2709.70
2709.75
2709.70
2709.75
2709.70
2709.70
2709.70
2709.70
2336.80
2033.10
1739.90
105.55
3.55
105.55
3.55
105.55
3.55
105.55
3.55
105.55
3.55
105.55
310.50
553.25
832.20
1001.60
1335.65
1571.45
1797.90
2076.55
2471.55
2471.55
2471.55
412.50
GND
762.85
GND
934.20
NC
1211.20
1437.65
1673.45
1899.90
2178.55
2572.55
2572.55
2572.55
NC
CS
DIN
DOUT
SCLK
DRDY
NC
(1) For signal descriptions see the Pin Assignments table.
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SBAS525 –DECEMBER 2011
2713.55 µm
Connect to Connect to
Substrate Substrate
VDD
XIN
NC
DRDY SCLK
DOUT
XOUT
DIN
NC
CS
NC
NC
PDWN
NC
50 µm
NC
GND
GND
VREF+
VREF-
NC
AIN0/D0 AIN1/D1 AIN4/D4 AIN5/D5 AIN6/D6 AIN7/D7 AIN2/D2 AIN3/D3
0
50 µm
EDGE OF
SCRIBE
0
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TIMING DIAGRAMS
CS
t3
t1
t2
t10
SCLK
t2
t4
t5
t6
t11
DIN
MSB
LSB
t7
t8
t9
(Command or Command and Data)
MSB(1)
LSB(1)
DOUT
NOTE: (1) Bit order = 0.
SCLK Reset Waveform
Resets On
Falling Edge
300 • tOSC < t12 < 500 • tOSC
t13 : > 5 • tOSC
t13
t13
550 • tOSC < t14 < 750 • tOSC
SCLK
1050 • tOSC < t15 < 1250 • tOSC
t12
t14
t15
t16
tDATA
DRDY
PDWN
t17
t18
SCLK
t19
10
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SBAS525 –DECEMBER 2011
TIMING REQUIREMENTS
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tOSC
Periods
4
t1
SCLK Period
DRDY
Periods
3
t2
t3
t4
t5
SCLK Pulse Width, HIGH and LOW
CS low to first SCLK Edge; Setup Time(1)
DIN Valid to SCLK Edge; Setup Time
Valid DIN to SCLK Edge; Hold Time
200
0
ns
ns
ns
ns
50
50
Delay between last SCLK edge for DIN and first SCLK
edge for DOUT: RDATA, RDATAC, RREG, WREG
tOSC
Periods
t6
50
(2)
t7
t8
SCLK Edge to Valid New DOUT
SCLK Edge to DOUT, Hold Time
50
10
ns
ns
(2)
0
6
Last SCLK Edge to DOUT Tri-State
NOTE: DOUT goes tri-state immediately when CS goes
HIGH.
tOSC
Periods
t9
tOSC
Periods
Read from the device
Write to the device
0
8
t10
CS LOW time after final SCLK edge.
tOSC
Periods
RREG, WREG, DSYNC,
SLEEP, RDATA,
RDATAC, STOPC
tOSC
Periods
4
2
SELFGCAL,
SELFOCAL, SYSOCAL,
SYSGCAL
DRDY
Periods
Final SCLK edge of one command until first edge SCLK
of next command:
t11
DRDY
Periods
SELFCAL
4
16
4
RESET (also SCLK
Reset)
tOSC
Periods
tOSC
Periods
t16
t17
t18
Pulse Width
tOSC
Periods
Allowed analog input change for next valid conversion.
DOR update, DOR data not valid.
5000
tOSC
Periods
4
10
0
tOSC
Periods
RDATAC Mode
Any other mode
t19
First SCLK after DRDY goes LOW:
tOSC
Periods
(1) CS may be tied LOW.
(2) Load = 20 pF|| 10 kΩ to GND.
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TYPICAL CHARACTERISTICS
All specifications VDD = 5 V, fOSC = 2.4576 MHz, PGA = 1, fDATA = 15 Hz, and VREF ≡ (REF IN+) – (REF IN–) = 2.5 V,
unless otherwise specified.
EFFECTIVE NUMBER OF BITS
EFFECTIVE NUMBER OF BITS
vs
vs
PGA SETTING
PGA SETTING
22
21
20
19
18
17
16
15
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
DR = 10
DR = 10
DR = 01
DR = 01
DR = 00
DR = 00
Buffer ON
Buffer OFF
1
2
4
8
16
32
64 128
1
2
4
8
16
32
64 128
PGA Setting
PGA Setting
EFFECTIVE NUMBER OF BITS
NOISE
vs
vs
PGA SETTING
INPUT SIGNAL
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
DR = 10
DR = 01
DR = 00
Buffer OFF, VREF = 1.25V
–2.5
–1.5
–0.5
0.5
1.5
2.5
1
2
4
8
16
32
64
128
VIN (V)
PGA Setting
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
140
140
120
100
80
60
40
20
0
120
100
80
60
40
20
0
Buffer ON
10
Buffer ON
10
1
100
1k
10k
100k
1
100
1k
10k
100k
Frequency of Power Supply (Hz)
Frequency of Power Supply (Hz)
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TYPICAL CHARACTERISTICS (continued)
All specifications VDD = 5 V, fOSC = 2.4576 MHz, PGA = 1, fDATA = 15 Hz, and VREF ≡ (REF IN+) – (REF IN–) = 2.5 V,
unless otherwise specified.
OFFSET
vs
GAIN
vs
TEMPERATURE
(Cal AT 25°C)
TEMPERATURE
(Cal AT 25°C)
50
0
1.020
1.016
1.012
1.008
1.004
1.000
0.996
0.992
0.988
0.984
0.980
PGA16
PGA1
–50
–100
–150
–200
–250
PGA64
PGA128
–55 –35 –15
5
25 45 65 85 105 125 145 165 185 205
Temperature (°C)
–55 –35 –15
5
25 45 65 85 105 125 145 165 185 205
Temperature (°C)
INTEGRAL NONLINEARITY
CURRENT
vs
vs
INPUT SIGNAL
TEMPERATURE
325
300
275
250
225
200
175
10
8
–40°C
6
4
+85°C
2
0
–2
–4
–6
–8
–10
+25°C
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0 1.5 2.0 2.5
–55 –35 –15
5
25 45 65 85 105 125 145 165 185 205
Temperature (°C)
VIN (V)
CURRENT
vs
SUPPLY CURRENT
vs
VOLTAGE
SUPPLY
350
300
250
200
150
100
50
300
250
200
150
100
50
Normal
4.91MHz
Normal
2.45MHz
Normal
Normal
4.91MHz
SLEEP
4.91MHz
2.45MHz
SLEEP
2.45MHz
SLEEP
4.91MHz
Power Down
SLEEP
2.45MHz
0
Power Down
3.5
0
–50
3.0
3.25
3.5
3.75
4.0
4.25
4.5
4.75
5.0
3.0
4.0
4.5
5.0
VDD (V)
VDD (V)
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TYPICAL CHARACTERISTICS (continued)
All specifications VDD = 5 V, fOSC = 2.4576 MHz, PGA = 1, fDATA = 15 Hz, and VREF ≡ (REF IN+) – (REF IN–) = 2.5 V,
unless otherwise specified.
OFFSET DAC OFFSET
vs
TEMPERATURE
NOISE HISTOGRAM
(Cal AT 25°C)
200
150
100
50
3500
3000
2500
2000
1500
1000
500
10k Readings
IN = 0V
V
0
–50
–100
–150
–200
–250
0
–55 –35 –15
5
25 45 65 85 105 125 145 165 185 205
Temperature (°C)
–3.5 –3.0 –2.5 –2.0 –1.5 –1 –0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
ppm of FS
OFFSET DAC GAIN
vs
OFFSET DAC NOISE
TEMPEARTURE
(Cal AT 25°C)
vs
SETTING
1.0005
1.0004
1.0003
1.0002
1.0001
1.0000
0.9999
0.9998
0.9997
0.9996
0.9995
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–55 –35 –15
5
25 45 65 85 105 125 145 165 185 205
Temperature (°C)
–128 –96
–64
–32
0
32
64
96
128
Offset DAC Setting
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OVERVIEW
INPUT MULTIPLEXER
The input multiplexer provides for any combination of differential inputs to be selected on any of the input
channels, as shown in Figure 2. For example, if AIN0 is selected as the positive differential input channel, any
other channel can be selected as the negative terminal for the differential input channel. With this method, it is
possible to have up to seven single-ended input channels or four independent differential input channels for the
ADS1243.
The ADS1243 features a single-cycle settling digital filter that provides valid data on the first conversion after a
new channel selection. In order to minimize the settling error, synchronize MUX changes to the conversion
beginning, which is indicated by the falling edge of DRDY. In other words, issuing a MUX change through the
WREG command immediately after DRDY goes LOW minimizes the settling error. Increasing the time between
the conversion beginning (DRDY goes LOW) and the MUX change command (tDELAY) results in a settling error in
the conversion data, as shown in Figure 3.
AIN0/D0
AIN1/D1
VDD
Burnout Current Source
AIN2/D2
AIN3/D3
Input
Buffer
AIN4/D4
AIN5/D5
Burnout Current Source
AIN6/D6
GND
A
IN7/D7
Figure 2. Input Multiplexer Configuration
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New Conversion Begins,
Previous Conversion Data
New Conversion Complete
Complete Previous Conversion
DRDY
tDELAY
SCLK
DIN
MSB
LSB
SETTLING ERROR vs DELAY TIME
fCLK = 2.4576MHz
10
1
0.1
0.01
0.001
0.0001
0.00001
0.000001
0
2
4
6
8
10
12
14
16
Delay Time, tDELAY (ms)
Figure 3. Input Multiplexer Configuration
BURNOUT CURRENT SOURCES
The Burnout Current Sources can be used to detect sensor short-circuit or open-circuit conditions. Setting the
Burnout Current Sources (BOCS) bit in the SETUP register activates two 2µA current sources called burnout
current sources. One of the current sources is connected to the converter’s negative input and the other is
connected to the converter’s positive input.
Figure 4 shows the situation for an open-circuit sensor. This is a potential failure mode for many kinds of
remotely connected sensors. The current source on the positive input acts as a pull-up, causing the positive input
to go to the positive analog supply, and the current source on the negative input acts as a pull-down, causing the
negative input to go to ground. The ADS1243 therefore outputs full-scale (7FFFFF Hex).
Figure 5 shows a short-circuited sensor. Since the inputs are shorted and at the same potential, the ADS1243
signal outputs are approximately zero. (Note that the code for shorted inputs is not exactly zero due to internal
series resistance, low-level noise and other error sources.)
VDD
2mA
VDD
ADC
OPEN CIRCUIT
CODE = 0x7FFFFFH
0V
2mA
Figure 4. Burnout Detection While Sensor is Open-Circuited.
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VDD
2mA
VDD/2
SHORT
ADC
CODE ≅0
CIRCUIT
VDD/2
2mA
Figure 5. Burnout Detection While Sensor is Short-Circuited.
INPUT BUFFER
The input impedance of ADS1243 without the buffer enabled is approximately 5MΩ/PGA. For systems requiring
very high input impedance, the ADS1243 provides a chopper-stabilized differential FET-input voltage buffer.
When activated, the buffer raises the ADS1243 input impedance to approximately 5 GΩ.
The buffer’s input range is approximately 50mV to VDD – 1.5 V. The buffer’s linearity will degrade beyond this
range. Differential signals should be adjusted so that both signals are within the buffer’s input range.
The buffer can be enabled using the BUFEN pin or the BUFEN bit in the ACR register. The buffer is on when the
BUFEN pin is high and the BUFEN bit is set to one. If the BUFEN pin is low, the buffer is disabled. If the BUFEN
bit is set to zero, the buffer is also disabled.
The buffer draws additional current when activated. The current required by the buffer depends on the PGA
setting. When the PGA is set to 1, the buffer uses approximately 50 µA; when the PGA is set to 128, the buffer
uses approximately 500µA.
PGA
The Programmable Gain Amplifier (PGA) can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can
improve the effective resolution of the A/D converter. For instance, with a PGA of 1 on a 5-V full-scale signal, the
A/D converter can resolve down to 1 µV. With a PGA of 128 and a full-scale signal of 39 mV, the A/D converter
can resolve down to 75 nV. VDD current increases with PGA settings higher than 4.
OFFSET DAC
The input to the PGA can be shifted by half the full-scale input range of the PGA using the Offset DAC (ODAC)
register. The ODAC register is an 8-bit value; the MSB is the sign and the seven LSBs provide the magnitude of
the offset. Using the offset DAC does not reduce the performance of the A/D converter. For more details on the
ODAC in the ADS1243, please refer to TI application report SBAA077 (available through the TI website).
MODULATOR
The modulator is a single-loop second-order system. The modulator runs at a clock speed (fMOD) that is derived
from the external clock (fOSC). The frequency division is determined by the SPEED bit in the SETUP register, as
shown in Table 2.
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Table 2. Output Configuration
DR BITS
SPEED
BIT
1st NOTCH
FREQUENCY
fOSC
fMOD
00
01
10
0
1
0
1
19,200 Hz
9,600 Hz
15 Hz
7.5 Hz
30 Hz
15 Hz
7.5 Hz
3.75 Hz
15 Hz
7.5 Hz
3.75 Hz
1.875 Hz
7.5 Hz
50/60 Hz
25/30 Hz
2.4576 MHz
4.9152 MHz
38,400 Hz
19,200 Hz
100/120 Hz
50/60 Hz
3.75 Hz
CALIBRATION
The offset and gain errors can be minimized with calibration. The ADS1243 supports both self and system
calibration.
Self-calibration of the ADS1243 corrects internal offset and gain errors and is handled by three commands:
SELFCAL, SELFGAL, and SELFOCAL. The SELFCAL command performs both an offset and gain calibration.
SELFGCAL performs a gain calibration and SELFOCAL performs an offset calibration, each of which takes two
tDATA periods to complete. During self-calibration, the ADC inputs are disconnected internally from the input pins.
The PGA must be set to 1 prior to issuing a SELFCAL or SELFGCAL command. Any PGA is allowed when
issuing a SELFOCAL command. For example, if using PGA = 64, first set PGA = 1 and issue SELFGCAL.
Afterwards, set PGA = 64 and issue SELFOCAL. For operation with a reference voltage greater than (VDD – 1.5)
volts, the buffer must also be turned off during gain self-calibration to avoid exceeding the buffer input range.
System calibration corrects both internal and external offset and gain errors. While performing system calibration,
the appropriate signal must be applied to the inputs. The system offset calibration command (SYSOCAL)
requires a zero input differential signal (see Table 5). It then computes the offset that nullifies the offset in the
system. The system gain calibration command (SYSGCAL) requires a positive full-scale input signal. It then
computes a value to nullify the gain error in the system. Each of these calibrations takes two tDATA periods to
complete. System gain calibration is recommended for the best gain calibration at higher PGAs.
Calibration should be performed after power on, a change in temperature, or a change of the PGA. The RANGE
bit (ACR bit 2) must be zero during calibration.
Calibration removes the effects of the ODAC; therefore, disable the ODAC during calibration, and enable again
after calibration is complete.
At the completion of calibration, the DRDY signal goes low, indicating the calibration is finished. The first data
after calibration should be discarded since it may be corrupt from calibration data remaining in the filter. The
second data is always valid.
EXTERNAL VOLTAGE REFERENCE
The ADS1243 requires an external voltage reference. The selection for the voltage reference value is made
through the ACR register.
The external voltage reference is differential and is represented by the voltage difference between the pins:
+VREF and –VREF. The absolute voltage on either pin, +VREF or –VREF, can range from GND to VDD. However, the
following limitations apply:
•
•
•
•
For VDD = 5 V and RANGE = 0 in the ACR, the differential VREF must not exceed 2.5 V.
For VDD = 5 V and RANGE = 1 in the ACR, the differential VREF must not exceed 5 V.
For VDD = 3 V and RANGE = 0 in the ACR, the differential VREF must not exceed 1.25 V.
For VDD = 3 V and RANGE = 1 in the ACR, the differential VREF must not exceed 2.5 V.
CLOCK GENERATOR
The clock source for ADS1243 can be provided from a crystal, oscillator, or external clock. When the clock
source is a crystal, external capacitors must be provided to ensure start-up and stable clock frequency. This is
shown in both Figure 6 and Table 3. XOUT is only for use with external crystals and it should not be used as a
clock driver for external circuitry.
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XIN
C1
Crystal
XOUT
C2
Figure 6. Crystal Connection.
Table 3. Recommended Crystals
CLOCK
SOURCE
PART
NUMBER
FREQUENCY
C1
C2
Crystal
Crystal
Crystal
Crystal
2.4576
4.9152
4.9152
4.9152
0-20 pF
0-20 pF
0-20 pF
0-20 pF
0-20 pF
0-20 pF
0-20 pF
0-20 pF
ECS, ECSD 2.45 – 32
ECS, ECSL 4.91
ECS, ECSD 4.91
CTS, MP 042 4M9182
DIGITAL FILTER
The ADS1243 has a 1279 tap linear phase Finite Impulse Response (FIR) digital filter that a user can configure
for various output data rates. When a 2.4576-MHz crystal is used, the device can be programmed for an output
data rate of 15 Hz, 7.5 Hz, or 3.75 Hz. Under these conditions, the digital filter rejects both 50Hz and 60Hz
interference. Figure 7 shows the digital filter frequency response for data output rates of 15 Hz, 7.5 Hz, and 3.75
Hz.
If a different data output rate is desired, a different crystal frequency can be used. However, the rejection
frequencies shift accordingly. For example, a 3.6864-MHz master clock with the default register condition has:
(3.6864 MHz/2.4576 MHz) ● 15 Hz = 22.5 Hz data output rate
and the first and second notch is:
1.5 ● (50 Hz and 60 Hz) = 75 Hz and 90 Hz
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ADS1243
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 15Hz
FILTER RESPONSE WHEN fDATA = 15Hz
0
–20
–40
–50
–60
–40
–70
–60
–80
–80
–90
–100
–120
–140
–160
–180
–100
–110
–120
–130
–140
0
20
40 60
80 100 120 140 160 180 200
45
45
45
50
55
60
65
Frequency (Hz)
Frequency (Hz)
ADS1243
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 7.5Hz
FILTER RESPONSE WHEN fDATA = 7.5Hz
–40
–50
0
–20
–60
–40
–70
–60
–80
–80
–90
–100
–120
–140
–160
–180
–100
–110
–120
–130
–140
50
55
60
65
0
20
40 60
80 100 120 140 160 180 200
Frequency (Hz)
Frequency (Hz)
ADS1243
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 3.75Hz
FILTER RESPONSE WHEN fDATA = 3.75Hz
0
–20
–40
–50
–60
–40
–70
–60
–80
–80
–90
–100
–120
–140
–160
–180
–100
–110
–120
–130
–140
0
20
40 60
80 100 120 140 160 180 200
Frequency (Hz)
50
55
60
65
Frequency (Hz)
fOSC = 2.4576MHz, SPEED = 0 or fOSC = 4.9152MHz, SPEED = 1
ATTENUATION
DATA
–3dB
OUTPUT RATE
BANDWIDTH
f
IN = 50 ± 0.3Hz
fIN = 60 ± 0.3Hz
fIN = 50 ± 1Hz
fIN = 60 ± 1Hz
15Hz
7.5Hz
3.75Hz
14.6Hz
3.44Hz
1.65Hz
–80.8dB
–85.9dB
–93.8dB
–87.3dB
–87.4dB
–88.6dB
–68.5dB
–71.5dB
–86.8dB
–76.1dB
–76.2dB
–77.3dB
Figure 7. Filter Frequency Responses
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DATA I/O INTERFACE
The ADS1243 has eight pins that serve a dual purpose as both analog inputs and data I/O. These pins are
configured through the IOCON, DIR, and DIO registers and can be individually configured as either analog inputs
or data I/O. See Figure 8 for the equivalent schematic of an Analog/Data I/O pin.
The IOCON register defines the pin as either an analog input or data I/O. The power-up state is an analog input.
If the pin is configured as an analog input in the IOCON register, the DIR and DIO registers have no effect on the
state of the pin.
If the pin is configured as data I/O in the IOCON register, then DIR and DIO are used to control the state of the
pin. The DIR register controls the direction of the data pin, either as an input or output. If the pin is configured as
an input in the DIR register, then the corresponding DIO register bit reflects the state of the pin. Make sure the
pin is driven to a logic one or zero when configured as an input to prevent excess current dissipation. If the pin is
configured as an output in the DIR register, then the corresponding DIO register bit value determines the state of
the output pin (0 = GND, 1 = VDD).
It is still possible to perform A/D conversions on a pin configured as data I/O. This may be useful as a test mode,
where the data I/O pin is driven and an A/D conversion is done on the pin.
IOCON
DIR
DIO WRITE
AINx/Dx
To Analog Mux
DIO READ
Figure 8. Analog/Data Interface Pin
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) allows a controller to communicate synchronously with the ADS1243. The
ADS1243 operates in slave-only mode. The serial interface is a standard four-wire SPI (CS, SCLK, DIN and
DOUT) interface.
Chip Select (CS)
The chip select (CS) input must be externally asserted before communicating with the ADS1243. CS must stay
LOW for the duration of the communication. Whenever CS goes HIGH, the serial interface is reset. CS may be
hard-wired LOW.
Serial Clock (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input and is used to clock DIN and DOUT data. Make sure to
have a clean SCLK to prevent accidental double-shifting of the data. If SCLK is not toggled within three DRDY
pulses, the serial interface resets on the next SCLK pulse and starts a new communication cycle. A special
pattern on SCLK resets the entire chip; see the RESET section for additional information.
Data Input (DIN) and Data Output (DOUT
)
The data input (DIN) and data output (DOUT) receive and send data from the ADS1243. DOUT is high impedance
when not in use to allow DIN and DOUT to be connected together and driven by a bidirectional bus. Note: the
Read Data Continuous Mode (RDATAC) command should not be issued when DIN and DOUT are connected.
While in RDATAC mode, DIN looks for the STOPC or RESET command. If either of these 8-bit bytes appear on
DOUT (which is connected to DIN), the RDATAC mode ends.
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DATA READY (DRDY) PIN
The DRDY line is used as a status signal to indicate when data is ready to be read from the internal data
register. DRDY goes LOW when a new data word is available in the DOR register. It is reset HIGH when a read
operation from the data register is complete. It also goes HIGH prior to the updating of the output register to
indicate when not to read from the device to ensure that a data read is not attempted while the register is being
updated.
The status of DRDY can also be obtained by interrogating bit 7 of the ACR register (address 2H). The serial
interface can operate in 3-wire mode by tying the CS input LOW. In this case, the SCLK, DIN, and DOUT lines are
used to communicate with the ADS1243. This scheme is suitable for interfacing to microcontrollers. If CS is
required as a decoding signal, it can be generated from a port bit of the microcontroller.
DSYNC OPERATION
Synchronization can be achieved through the DSYNC command. When the DSYNC command is sent, the digital
filter is reset on the edge of the last SCLK of the DSYNC command. The modulator is held in RESET until the
next edge of SCLK is detected. Synchronization occurs on the next rising edge of the system clock after the first
SCLK following the DSYNC command.
POWER-UP—SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate digital supply ramp rates as slow as 1 V/10 ms. To
ensure proper operation, the power supply should ramp monotonically.
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ADS1243 REGISTERS
The operation of the device is set up through individual registers. Collectively, the registers contain all the
information needed to configure the part, such as data format, multiplexer settings, calibration settings, data rate,
etc. The 16 registers are shown in Table 4.
Table 4. Registers
ADDRESS REGISTER
BIT 7
ID
BIT 6
ID
BIT 5
ID
BIT 4
ID
BIT 3
BOCS
BIT 2
PGA2
BIT 1
PGA1
BIT 0
PGA0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
SETUP
MUX
PSEL3
DRDY
SIGN
PSEL2
U/B
PSEL1
SPEED
OSET5
DIO_5
DIR_5
IO5
PSEL0
BUFEN
OSET4
DIO_4
DIR_4
IO4
NSEL3
BIT ORDER
OSET3
DIO_3
NSEL2
RANGE
OSET2
DIO_2
DIR_2
IO2
NSEL1
DR1
NSEL0
DR0
ACR
ODAC
DIO
OSET6
DIO_6
DIR_6
IO6
OSET1
DIO_1
DIR_1
IO1
OSET0
DIO_0
DIR_0
IO0
DIO_7
DIR_7
IO7
DIR
DIR_3
IOCON
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
DOR2
DOR1
DOR0
IO3
OCR07
OCR15
OCR23
FSR07
FSR15
FSR23
DOR23
DOR15
DOR07
OCR06
OCR14
OCR22
FSR06
FSR14
FSR22
DOR22
DOR14
DOR16
OCR05
OCR13
OCR21
FSR05
FSR13
FSR21
DOR21
DOR13
FSR21
OCR04
OCR12
OCR20
FSR04
FSR12
FSR20
DOR20
DOR12
DOR04
OCR03
OCR11
OCR19
FSR03
FSR11
FSR19
DOR19
DOR11
DOR03
OCR02
OCR10
OCR18
FSR02
FSR10
FSR18
DOR18
DOR10
DOR02
OCR01
OCR09
OCR17
FSR01
FSR09
FSR17
DOR17
DOR09
DOR01
OCR00
OCR08
OCR16
FSR00
FSR08
FSR16
DOR16
DOR08
DOR00
DETAILED REGISTER DEFINITIONS
Setup
(Address 00H) Setup Register
Reset Value = iiii0000
bit 7
ID
bit 6
ID
bit 5
ID
bit 4
ID
bit 3
bit 2
PGA2
bit 1
PGA1
bit 0
BOCS
PGA0
bit 7–4
Factory Programmed Bits
bit 3
BOCS: Burnout Current Source
0 = Disabled (default)
1 = Enabled
bit 2–0
PGA2: PGA1: PGA0: Programmable Gain Amplifier
Gain Selection
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
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MUX
(Address 01H) Multiplexer Control Register
Reset Value = 01H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
bit 7–4
PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
Select
0000 = AIN0 (default)
0001 = AIN
0010 = AIN
0011 = AIN
0100 = AIN
0101 = AIN
0110 = AIN
0111 = AIN
1
2
3
4
5
6
7
1111 = Reserved
bit 3–0
NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel
Select
0000 = AIN
0
0001 = AIN1 (default)
0010 = AIN
0011 = AIN
0100 = AIN
0101 = AIN
0110 = AIN
0111 = AIN
2
3
4
5
6
7
1111 = Reserved
ACR
(Address 02H) Analog Control Register
Reset Value = X0H
bit 7
bit 6
U/B
bit 5
bit 4
bit 3
bit 2
bit 1
DR1
bit 0
DR0
DRDY
SPEED
BUFEN
BIT ORDER
RANGE
bit 7
bit 6
DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
U/B: Data Format
0 = Bipolar (default)
1 = Unipolar
U/B
ANALOG INPUT
DIGITAL OUTPUT (Hex)
0x7FFFFF
+FSR
Zero
0
0x000000
–FSR
+FSR
Zero
0x800000
0xFFFFFF
1
0x000000
–FSR
0x000000
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bit 5
SPEED: Modulator Clock Speed
0 = fMOD = fOSC/128 (default)
1 = fMOD = fOSC/256
bit 4
bit 3
BUFEN: Buffer Enable
0 = Buffer Disabled (default)
1 = Buffer Enabled
BIT ORDER: Data Output Bit Order
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
Data is always shifted in or out MSB first.
bit 2
RANGE: Range Select
0 = Full-Scale Input Range equal to ±VREF (default).
1 = Full-Scale Input Range equal to ±1/2 VREF
NOTE: This allows reference voltages as high as
VDD, but even with a 5V reference voltage the
calibration must be performed with this bit set to 0.
bit 1–0
DR1: DR0: Data Rate
(fOSC = 2.4576MHz, SPEED = 0)
00 = 15 Hz (default)
01 = 7.5 Hz
10 = 3.75 Hz
11 = Reserved
ODAC
(Address 03) Offset DAC
Reset Value = 00H
bit 7
bit 6
OSET6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SIGN
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
bit 7
Sign
0 = Positive
1 = Negative
æ OSET 6:0 ö
VREF
[ ]÷
Offset =
Offset =
·
RANGE = 0
ç
2· PGA
127
è
ø
æ OSET 6:0 ö
VREF
[
127
]
·
RANGE =1
ç
è
÷
ø
4· PGA
NOTE: The offset DAC must be enabled after calibration or the calibration nullifies the effects.
DIO
(Address 04H) Data I/O
Reset Value = 00H
bit 7
bit 6
DIO 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIO 7
DIO 5
DIO 4
DIO 3
DIO 2
DIO 1
DIO 0
If the IOCON register is configured for data, a value written to this register appears on the data I/O pins if the pin is configured
as an output in the DIR register. Reading this register returns the value of the data I/O pins.
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DIR
(Address 05H) Direction Control for Data I/O
Reset Value = FFH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
Each bit controls whether the corresponding data I/O pin is an output (= 0) or input (= 1). The default power-up state is as
inputs.
IOCON
(Address 06H) I/O Configuration Register
Reset Value = 00H
bit 7
IO7
bit 6
IO6
bit 5
IO5
bit 4
IO4
bit 3
IO3
bit 2
IO2
bit 1
IO1
bit 0
IO0
bit 7-0
IO7: IO0: Data I/O Configuration
0 = Analog (default)
1 = Data
Configuring the pin as a data I/O pin allows it to be controlled through the DIO and DIR registers.
ORC0
(Address 07H) Offset Calibration Coefficient
(Least Significant Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
OCR1
(Address 08H) Offset Calibration Coefficient
(Middle Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
OCR2
(Address 09H) Offset Calibration Coefficient
(Most Significant Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
FSR0
(Address 0AH) Full-Scale Register
(Least Significant Byte)
Reset Value = 59H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
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FSR1
(Address 0BH) Full-Scale Register
(Middle Byte)
Reset Value = 55H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR15
FSR14
FSR13
FSR12
FSR11
FSR10
FSR09
FSR08
FSR2
(Address 0CH) Full-Scale Register
(Most Significant Byte)
Reset Value = 55H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR23
FSR22
FSR21
FSR20
FSR19
FSR18
FSR17
FSR16
DOR2
(Address 0DH) Data Output Register
(Most Significant Byte) (Read Only)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DOR23
DOR22
DOR21
DOR20
DOR19
DOR18
DOR17
DOR16
DOR1
(Address 0EH) Data Output Register
(Middle Byte) (Read Only)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DOR15
DOR14
DOR13
DOR12
DOR11
DOR10
DOR09
DOR08
DOR0
(Address 0FH) Data Output Register
(Least Significant Byte) (Read Only)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DOR07
DOR06
DOR05
DOR04
DOR03
DOR02
DOR01
DOR00
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ADS1243 CONTROL COMMAND DEFINITIONS
The commands listed in Table IV control the operations of ADS1243. Some of the commands are stand-alone
commands (for example, RESET) while others require additional bytes (for example, WREG requires the count
and data bytes).
Operands:
•
•
•
n = count (0 to 127)
r = register (0 to 15)
x = don’t care
Table 5. Command Summary
COMMANDS
DESCRIPTION
OP CODE
2nd COMMAND BYTE
Read Data
0000 0001 (01H)
0000 0011 (03H)
—
Read Data Continuously
—
Stop Read Data Continuously
Read from REG “rrrr”
Write to REG “rrrr”
Offset and Gain Self Cal
Self Offset Cal
0000 1111 (0FH)
0001 r r r r (1xH)
0101 r r r r (5xH)
1111 0000 (F0H)
1111 0001 (F1H)
1111 0010 (F2H)
1111 0011 (F3H)
1111 0100 (F4H)
1111 1011 (FBH)
1111 1100 (FCH)
1111 1101 (FDH)
1111 1110 (FEH)
—
xxxx_nnnn (# of regs-1)
RDATA RDATAC
STOPC RREG
WREG SELFCAL
SELFOCAL
SELFGCAL
SYSOCAL
SYSGCAL
WAKEUP
DSYNC SLEEP
RESET
xxxx_nnnn (# of regs-1)
—
—
—
—
—
—
—
—
—
Self Gain Cal
Sys Offset Cal
Sys GainCal
Wakup from SLEEP Mode
Sync DRDY
Put in SLEEP Mode
Reset to Power-Up Values
NOTE: The received data format is always MSB first; the data out format is set by the BIT ORDER bit in the ACR register.
RDATA–Read Data
Description:
Read the most recent conversion result from the Data Output Register (DOR). This is a
24-bit value.
Operands:
Bytes:
None
1
Encoding:
0000 0001
Data Transfer
Sequence:
0000 0001
• • •(1)
xxxx xxxx
MSB
xxxx xxxx
Mid-Byte
xxxx xxxx
LSB
DIN
DOUT
(1) For wait time, refer to timing specification.
RDATAC–Read Data Continuous
Description:
Read Data Continuous mode enables the continuous output of new data on each DRDY. This
command eliminates the need to send the Read Data Command on each DRDY. This mode
may be terminated by either the STOPC command or the RESET command. Wait at least 10
fOSC after DRDY falls before reading.
Operands:
Bytes:
None
1
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Encoding:
0000 0011
Data Transfer Command terminated when “uuuu uuuu” equals STOPC or RESET.
DRDY
Sequence:
DIN
0000 0011
• • •(1)
uuuu uuuu
MSB
uuuu uuuu
Mid-Byte
uuuu uuuu
LSB
• • •
DOUT
DRDY
DOUT
• • •
MSB
Mid-Byte
LSB
(1)For wait time, refer to timing specification.
STOPC–Stop Continuous
Description:
Operands:
Bytes:
Ends the continuous data output mode. Issue after DRDY goes LOW.
None
1
Encoding:
0000 1111
DRDY
Data Transfer
Sequence:
xxx
0000 1111
DIN
RREG–Read from Registers
Description:
Output the data from up to 16 registers starting with the register address specified as part of
the instruction. The number of registers read will be one plus the second byte count. If the
count exceeds the remaining registers, the addresses wrap back to the beginning.
Operands:
Bytes:
r, n
2
Encoding:
0001 rrrr xxxx nnnn
Data Transfer Read Two Registers Starting from Register 01H (MUX)
Sequence:
0001 0001
0000 0001
• • •(1)
xxxx xxxx
MUX
xxxx xxxx
ACR
DIN
DOUT
(1)For wait time, refer to timing specification.
WREG–Write to Registers
Description:
Write to the registers starting with the register address specified as part of the instruction. The
number of registers that will be written is one plus the value of the second byte.
Operands:
Bytes:
r, n
2
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Encoding:
0101 rrrr xxxx nnnn
Data Transfer Write Two Registers Starting from 04H (DIO)
Sequence:
DIN
0101 0100
xxxx 0001
Data for DIO
Data for DIR
SELFCAL–Offset and Gain Self Calibration
Description:
Starts the process of self calibration. The Offset Calibration Register (OCR) and the Full-Scale
Register (FSR) are updated with new values after this operation.
Operands:
Bytes:
None
1
Encoding:
1111 0000
Data Transfer
Sequence:
1111 0000
DIN
SELFOCAL–Offset Self Calibration
Description:
Starts the process of self-calibration for offset. The Offset Calibration Register (OCR) is
updated after this operation.
Operands:
Bytes:
None
1
Encoding:
1111 0001
Data Transfer
Sequence:
1111 0001
DIN
SELFGCAL–Gain Self Calibration
Description:
Starts the process of self-calibration for gain. The Full-Scale Register (FSR) is updated with
new values after this operation.
Operands:
Bytes:
None
1
Encoding:
1111 0010
Data Transfer
Sequence:
1111 0010
DIN
SYSOCAL–System Offset Calibration
Description:
Initiates a system offset calibration. The input should be set to 0V, and the ADS1243
computes the OCR value that compensates for offset errors. The Offset Calibration Register
(OCR) is updated after this operation. The user must apply a zero input signal to the
appropriate analog inputs. The OCR register is automatically updated afterwards.
Operands:
Bytes:
None
1
Encoding:
1111 0011
Data Transfer
Sequence:
1111 0011
DIN
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SYSGCAL–System Gain Calibration
Description:
Starts the system gain calibration process. For a system gain calibration, the input should be
set to the reference voltage and the ADS1243 computes the FSR value that will compensate
for gain errors. The FSR is updated after this operation. To initiate a system gain calibration,
the user must apply a full-scale input signal to the appropriate analog inputs. FCR register is
updated automatically.
Operands:
Bytes:
None
1
Encoding:
1111 0100
Data Transfer
Sequence:
1111 0100
DIN
WAKEUP
Description:
Operands:
Bytes:
Wakes the ADS1243 from SLEEP mode.
None
1
Encoding:
1111 1011
Data Transfer
Sequence:
1111 1011
DIN
DSYNC–Sync DRDY
Description:
Operands:
Bytes:
Synchronizes the ADS1243 to an external event.
None
1
Encoding:
1111 1100
Data Transfer
Sequence:
1111 1100
DIN
SLEEP–Sleep Mode
Description:
Puts the ADS1243 into a low power sleep mode. To exit sleep mode, issue the WAKEUP
command.
Operands:
Bytes:
None
1
Encoding:
1111 1101
Data Transfer
Sequence:
1111 1101
DIN
RESET–Reset to Default Values
Description:
Restore the registers to their power-up values. This command stops the Read Continuous
mode.
None
1
Operands:
Bytes:
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Encoding:
1111 1110
Data Transfer
Sequence:
1111 1110
DIN
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APPLICATION INFORMATION
GENERAL-PURPOSE WEIGHT SCALE
Figure 9 shows a typical schematic of a general-purpose weight scale application using the ADS1243. In this
example, the internal PGA is set to either 64 or 128 (depending on the maximum output voltage of the load cell)
so that the load cell output can be directly applied to the differential inputs of ADS1243.
2.7V ~ 5.25V
EMI Filter
VDD
VDD
VREF+
EMI Filter
AIN0
DRDY
SCLK
DOUT
DOUT
CS
Load Cell
MSP430x4xx
or other
SPI
Microprocessor
EMI Filter
AIN1
MCLK
GND
XIN
XOUT
VREF–
GND
EMI Filter
Figure 9. Schematic of a General-Purpose Weight Scale.
HIGH PRECISION WEIGHT SCALE
Figure 10 shows the typical schematic of a high-precision weight scale application using the ADS1243. The
front-end differential amplifier helps maximize the dynamic range.
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2.7V ~ 5.25V
2.7V ~ 5.25V
EMI Filter
VDD
VDD
VREF+
EMI Filter
RI
OPA2335
AIN0
Load Cell
RF
DRDY
SCLK
DOUT
DIN
MSP430x4xx
or other
CI
SPI
RG
ADS1243
Microprocessor
RF
CS
RI
OPA2335
EMI Filter
AIN1
MCLK
GND
XIN
XOUT
VREF–
GND
EMI Filter
G = 1 + 2 • RF/RG
Figure 10. Block Diagram for a High-Precision Weight Scale.
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DEFINITION OF TERMS
An attempt has been made to be consistent with the terminology used in this data sheet. In that regard, the
definition of each term is given as follows:
Analog Input Voltage – the voltage at any one analog input relative to GND.
Analog Input Differential Voltage –given by the following equation: (IN+) – (IN–). Thus, a positive digital output
is produced whenever the analog input differential voltage is positive, while a negative digital output is produced
whenever the differential is negative.
For example, when the converter is configured with a 2.5-V reference and placed in a gain setting of 1, the
positive full-scale output is produced when the analog input differential is 2.5 V. The negative full-scale output is
produced when the differential is –2.5 V. In each case, the actual input voltages must remain within the GND to
VDD range.
Conversion Cycle –the term conversion cycle usually refers to a discrete A/D conversion operation, such as that
performed by a successive approximation converter. As used here, a conversion cycle refers to the tDATA time
period.
Data Rate – The rate at which conversions are completed. See definition for fDATA
fOSC
.
fDATA
=
128 · 2SPEED · 1280 · 2DR
SPEED = 0,1
DR = 0, 1, 2
fOSC –the frequency of the crystal oscillator or CMOS compatible input signal at the XIN input of the ADS1243.
fMOD – the frequency or speed at which the modulator of the ADS1243 is running. This depends on the SPEED
bit as given by the following equation:
SPEED = 0
SPEED = 1
mfactor
128
256
fosc
fosc
fMOD
=
=
mfactor 128· 2SPEED
PGA SETTING
SAMPLING FREQUENCY
fOSC
fSAMP
fSAMP
fSAMP
fSAMP
=
=
=
=
1, 2, 4, 8
16
mfactor
fOSC· 2
mfactor
fOSC· 4
32
mfactor
fOSC· 8
64, 128
mfactor
fSAMP – the frequency, or switching speed, of the input sampling capacitor. The value is given by one of the
following equations:
fDATA – the frequency of the digital output data produced by the ADS1243, fDATA is also referred to as the Data
Rate.
Full-Scale Range (FSR) – as with most A/D converters, the full-scale range of the ADS1243 is defined as the
input, that produces the positive full-scale digital output minus the input, that produces the negative full-scale
digital output.
For example, when the converter is configured with a 2.5-V reference and is placed in a gain setting of 2, the
full-scale range is: [1.25 V (positive full-scale) minus –1.25 V (negative full-scale)] = 2.5 V.
Least Significant Bit (LSB) Weight – this is the theoretical amount of voltage that the differential voltage at the
analog input has to change in order to observe a change in the output data of one least significant bit. It is
computed as follows:
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Full-ScaleRange
2N - 1
LSBWeight=
where N is the number of bits in the digital output.
tDATA – the inverse of fDATA, or the period between each data output.
Table 6. Full-Scale Range versus PGA Setting
5V SUPPLY ANALOG INPUT(1)
GENERAL EQUATIONS
DIFFERENTIAL
DIFFERENTIAL
INPUT
FULL-SCALE
PGA OFFSET
FULL-SCALE
RANGE
PGA SHIFT
RANGE
GAIN SETTING
INPUT
RANGE
RANGE
VOLTAGES(2)
VOLTAGES(2)
1
2
4
5 V
2.5 V
1.25 V
0.625 V
312.5 mV
156.25 mV
78.125 mV
39.0625 mV
±2.5 V
±1.25 V
±0.625 V
±312.5 mV
±156.25 mV
±78.125 mV
±39.0625 mV
±19.531 mV
±1.25 V
±0.625 V
RANGE = 0
VREF
±VREF
±VREF
±312.5 mV
±156.25 mV
±78.125 mV
±39.0625 mV
±19.531 mV
±9.766 mV
PGA
2·PGA
4·PGA
8
16
32
64
128
RANGE = 1
(1) With a 2.5-V reference.
(2) Refer to electrical specification for analog input voltage range.
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PACKAGE OPTION ADDENDUM
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14-Mar-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ADS1243SJD
ACTIVE
CDIP SB
XCEPT
JD
20
0
1
TBD
TBD
AU
N / A for Pkg Type
N / A for Pkg Type
-55 to 210 ADS1243SJD
-55 to 210
ADS1243SKGD1
ACTIVE
KGD
121
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(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS1243-HT :
Catalog: ADS1243
•
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Mar-2013
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
IMPORTANT NOTICE
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