ADS1241E/1K [TI]
24-Bit ANALOG-TO-DIGITAL CONVERTER; 24位模拟数字转换器
| 型号： | ADS1241E/1K |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24-Bit ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总23页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A
ADS1240
ADS1241
D
S
1
2
4
0
A
D
S
1
2
4
1
SBAS173C – JUNE 2001 – REVISED NOVEMBER 2003
24-Bit
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
● 24 BITS NO MISSING CODES
The ADS1240 and ADS1241 are precision, wide dynamic range,
delta-sigma, Analog-to-Digital (A/D) converters with 24-bit resolution
operating from 2.7V to 5.25V power supplies. The delta-sigma A/D
converter provides up to 24 bits of no missing code performance and
effective resolution of 21 bits.
● SIMULTANEOUS 50Hz AND 60Hz REJECTION
(–90dB MINIMUM)
● 0.0015% INL
● 21 BITS EFFECTIVE RESOLUTION
The input channels are multiplexed. Internal buffering can be
selected to provide very high input impedance for direct connection
to transducers or low-level voltage signals. Burnout current sources
are provided that allow for detection of an open or shorted sensor.
An 8-bit Digital-to-Analog (D/A) converter provides an offset cor-
rection with a range of 50% of the Full-Scale Range (FSR).
(PGA = 1), 19 BITS (PGA = 128)
● PGA GAINS FROM 1 TO 128
● SINGLE CYCLE SETTLING
● PROGRAMMABLE DATA OUTPUT RATES
● EXTERNAL DIFFERENTIAL REFERENCE
OF 0.1V TO 5V
The Programmable Gain Amplifier (PGA) provides selectable gains of
1 to 128, with an effective resolution of 19 bits at a gain of 128. The
A/D conversion is accomplished with a 2nd-order delta-sigma modu-
lator and programmable Finite-Impulse Response (FIR) filter that
provides a simultaneous 50Hz and 60Hz notch. The reference input
is differential and can be used for ratiometric conversion.
● ON-CHIP CALIBRATION
● SPI™ COMPATIBLE
● 2.7V TO 5.25V SUPPLY RANGE
● 600µW POWER CONSUMPTION
● UP TO EIGHT INPUT CHANNELS
● UP TO EIGHT DATA I/O
The serial interface is SPI compatible. Up to eight bits of data
I/O are also provided that can be used for input or output. The
ADS1240 and ADS1241 are designed for high-resolution measure-
ment applications in smart transmitters, industrial process control,
weigh scales, chromatography, and portable instrumentation.
APPLICATIONS
● INDUSTRIAL PROCESS CONTROL
● WEIGH SCALES
AVDD AGND
VREF+ VREF–
XIN
XOUT
● LIQUID/GAS CHROMATOGRAPHY
AVDD
● BLOOD ANALYSIS
Clock Generator
● SMART TRANSMITTERS
● PORTABLE INSTRUMENTATION
2µA
Offset
DAC
AIN0/D0
AIN1/D1
AIN2/D2
AIN3/D3
AIN4/D4
AIN5/D5
AIN6/D6
AIN7/D7
AINCOM
A = 1:128
PGA
2nd-Order
Modulator
Digital
Filter
MUX
+
Controller
Registers
BUF
POL
SCLK
DIN
Serial Interface
ADS1241
Only
DOUT
CS
2µA
AGND
BUFEN
DVDD
DGND
PDWN DSYNC
RESET DRDY
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001-2003, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
AVDD to DGND ...................................................................... –0.3V to +6V
DVDD to DGND ...................................................................... –0.3V to +6V
Input Current ............................................................... 100mA, Momentary
DGND to AGND ....................................................................–0.3V to 0.3V
Input Current ................................................................. 10mA, Continuous
A
IN .................................................................AGND –0.5V to AVDD + 0.5V
Digital Input Voltage to DGND ................................. –0.3V to DVDD + 0.3V
Digital Output Voltage to DGND .............................. –0.3V to DVDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –60°C to +150°C
Lead Temperature (soldering, 10s) .............................................. +300°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
EVALUATION MODULE ORDERING INFORMATION
PRODUCT
DESCRIPTION
ADS1241EVM
ADS1240 and ADS1241 Evaluation Module
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
DESIGNATOR(1)
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
ADS1240
SSOP-24
DB
–40°C to +85°C
ADS1240E
ADS1240E
Rails, 60
"
"
"
"
"
ADS1240E/1K
Tape and Reel, 1000
ADS1241
SSOP-28
DB
–40°C to +85°C
ADS1241E
ADS1241E
Rails, 48
"
"
"
"
"
ADS1241E/1K
Tape and Reel, 1000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
DIGITAL CHARACTERISTICS: –40°C to +85°C, DVDD 2.7V to 5.25V
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Input/Output
Logic Family
CMOS
Logic Level: VIH
0.8 • DVDD
DGND
DVDD – 0.4
DGND
DVDD
0.2 • DVDD
V
V
V
VIL
VOH
VOL
IOH = 1mA
IOL = 1mA
VI = DVDD
VI = 0
DGND + 0.4
10
V
Input Leakage: IIH
IIL
Master Clock Rate: fOSC
Master Clock Period: tOSC
µA
µA
MHz
ns
–10
1
200
5
1000
1/fOSC
ADS1240, 1241
2
SBAS173C
www.ti.com
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, and VREF = +2.5V, unless otherwise specified.
ADS1240
ADS1241
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (AIN0 – AIN7, AINCOM
)
Analog Input Range
Buffer OFF
Buffer ON
AGND – 0.1
AGND + 0.05
AVDD + 0.1
AVDD – 1.5
V
V
Full-Scale Input Range
(In+) – (In–), See Block Diagram, RANGE = 0
RANGE = 1
±VREF /PGA
±VREF /(2 • PGA)
V
V
Differential Input Impedance
Buffer OFF
Buffer ON
5/PGA
5
MΩ
GΩ
Bandwidth
fDATA = 3.75Hz
fDATA = 7.50Hz
fDATA = 15.00Hz
–3dB
–3dB
–3dB
1.65
3.44
14.6
Hz
Hz
Hz
Programmable Gain Amplifier
Input Capacitance
Input Leakage Current
Burnout Current Sources
User-Selectable Gain Ranges
1
128
9
5
2
pF
pA
µA
Modulator OFF, T = 25°C
OFFSET DAC
Offset DAC Range
RANGE = 0
RANGE = 1
±VREF /(2 • PGA)
±VREF /(4 • PGA)
V
V
Offset Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
8
Bits
%
ppm/°C
±10
1
SYSTEM PERFORMANCE
Resolution
Integral Nonlinearity
Offset Error(1)
Offset Drift(1)
Gain Error
Gain Error Drift(1)
Common-Mode Rejection
No Missing Codes
End Point Fit
24
Bits
% of FS
ppm of FS
ppm of FS/°C
%
ppm/°C
dB
±0.0015
7.5
0.02
0.005
0.5
at DC
100
f
CM = 60Hz, fDATA = 15Hz
130
120
100
100
dB
dB
dB
dB
fCM = 50Hz, fDATA = 15Hz
Normal-Mode Rejection
f
f
SIG = 50Hz, fDATA = 15Hz
SIG = 60Hz, fDATA = 15Hz
Output Noise
Power-Supply Rejection
See Typical Characteristics
95
(2)
at DC, dB = –20 log(∆VOUT /∆VDD
)
80
dB
VOLTAGE REFERENCE INPUT
VREF
Reference Input Range
VREF ≡ (REF IN+) – (REF IN–), RANGE = 0
REF IN+, REF IN–
RANGE = 1
0.1
0
0.1
2.5
2.6
AVDD
AVDD
V
V
V
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
at DC
120
120
1.3
dB
dB
µA
fVREFCM = 60Hz, fDATA = 15Hz
VREF = 2.5V
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Analog Current
AVDD
PDWN = 0, or SLEEP
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
4.75
5.25
V
1
nA
µA
µA
µA
µA
µA
µA
µA
nA
120
400
160
760
80
60
230
0.5
250
675
300
1275
125
PGA = 128, Buffer ON
Normal Mode, DVDD = 5V
SLEEP Mode, DVDD = 5V
Read Data Continuous Mode, DVDD = 5V
PDWN
Digital Current
Power Dissipation
PGA = 1, Buffer OFF, DVDD = 5V
1.1
1.9
mW
NOTES: (1) Calibration can minimize these errors to the level of the noise.
(2) ∆VOUT is a change in digital result.
(3) 12pF switched capacitor at fSAMP clock frequency.
ADS1240, 1241
3
SBAS173C
www.ti.com
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, and VREF = +1.25V, unless otherwise specified.
ADS1240
ADS1241
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (AIN0 – AIN7, AINCOM
)
Analog Input Range
Buffer OFF
Buffer ON
AGND – 0.1
AGND + 0.05
AVDD + 0.1
AVDD – 1.5
V
V
Full-Scale Input Voltage Range
(In+) – (In–) See Block Diagram, RANGE = 0
RANGE = 1
±VREF /PGA
±VREF /(2 • PGA)
V
V
Input Impedance
Differential
Buffer OFF
Buffer ON
5/PGA
5
MΩ
GΩ
Bandwidth
fDATA = 3.75Hz
fDATA = 7.50Hz
fDATA = 15.00Hz
–3dB
–3dB
–3dB
1.65
3.44
14.6
Hz
Hz
Hz
Programmable Gain Amplifier
Input Capacitance
Input Leakage Current
Burnout Current Sources
User-Selectable Gain Ranges
1
128
9
5
2
pF
pA
µA
Modulator OFF, T = 25°C
OFFSET DAC
Offset DAC Range
RANGE = 0
RANGE = 1
±VREF /(2 • PGA)
±VREF /(4 • PGA)
V
V
Offset DAC Monotonicity
Offset DAC Gain Error
8
Bits
%
±10
Offset DAC Gain Error Drift
2
ppm/°C
SYSTEM PERFORMANCE
Resolution
Integral Nonlinearity
Offset Error(1)
Offset Drift(1)
Gain Error
Gain Error Drift(1)
Common-Mode Rejection
No Missing Codes
End Point Fit
24
Bits
% of FS
ppm of FS
ppm of FS/°C
%
ppm/°C
dB
±0.0015
15
0.04
0.01
1.0
at DC
100
f
CM = 60Hz, fDATA = 15Hz
130
120
100
100
dB
dB
dB
dB
fCM = 50Hz, fDATA = 15Hz
Normal-Mode Rejection
f
f
SIG = 50Hz, fDATA = 15Hz
SIG = 60Hz, fDATA = 15Hz
Output Noise
Power-Supply Rejection
See Typical Characteristics
90
(2)
at DC, dB = –20 log(∆VOUT /∆VDD
)
75
dB
VOLTAGE REFERENCE INPUT
VREF
Reference Input Range
VREF ≡ (REF IN+) – (REF IN–), RANGE = 0
REF IN+, REF IN–
0.1
0
0.1
1.25
2.5
1.30
AVDD
2.6
V
V
V
RANGE = 1
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
at DC
120
120
0.65
dB
dB
µA
fVREFCM = 60Hz, fDATA = 15Hz
VREF = 1.25
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Analog Current
AVDD
PDWN = 0, or SLEEP
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
2.7
3.3
V
nA
µA
µA
µA
µA
µA
µA
µA
nA
mW
1
107
355
118
483
50
225
600
275
1225
100
PGA = 128, Buffer ON
Normal Mode, DVDD = 3V
SLEEP Mode, DVDD = 3V
Read Data Continuous Mode, DVDD = 3V
PDWN = 0
Digital Current
40
113
0.5
0.6
Power Dissipation
PGA = 1, Buffer OFF, DVDD = 3V
1.2
NOTES: (1) Calibration can minimize these errors to the level of the noise.
(2) ∆VOUT is a change in digital result.
(3) 12pF switched capacitor at fSAMP clock frequency.
ADS1240, 1241
4
SBAS173C
www.ti.com
PIN CONFIGURATION (ADS1240)
PIN CONFIGURATION (ADS1241)
Top View
SSOP
Top View
SSOP
DVDD
DGND
XIN
1
2
3
4
5
6
7
8
9
28 BUFEN
27 DRDY
26 SCLK
25 DOUT
24 DIN
DVDD
DGND
XIN
1
2
3
4
5
6
7
8
9
24 BUFEN
23 DRDY
22 SCLK
21 DOUT
20 DIN
XOUT
XOUT
RESET
DSYNC
PDWN
DGND
VREF+
RESET
DSYNC
PDWN
DGND
VREF+
23 CS
19 CS
22 POL
ADS1240
ADS1241
18 POL
21 AVDD
20 AGND
19 AINCOM
18 AIN3/D3
17 AIN2/D2
17 AVDD
16 AGND
15 AINCOM
14 AIN3/D3
VREF– 10
AIN0/D0 11
AIN1/D1 12
VREF– 10
AIN0/D0 11
AIN1/D1 12
13
AIN2/D2
AIN4/D4 13
16
AIN7/D7
AIN5/D5 14
15 AIN6/D6
PIN DESCRIPTIONS (ADS1241)
PIN DESCRIPTIONS (ADS1240)
PIN
PIN
NUMBER
NAME
DESCRIPTION
NUMBER
NAME
DESCRIPTION
1
2
3
4
5
6
7
DVDD
DGND
XIN
Digital Power Supply
Digital Ground
Clock Input
Clock Output, used with external crystals.
Active LOW, resets the entire device.
Active LOW, Synchronization Control
Active LOW, Power Down. The power down func-
tion shuts down the analog and digital circuits.
Digital Ground
1
2
3
4
5
6
7
DVDD
DGND
XIN
Digital Power Supply
Digital Ground
Clock Input
XOUT
XOUT
Clock Output, used with external crystals.
Active LOW, resets the entire device.
Active LOW, Synchronization Control
RESET
DSYNC
PDWN
RESET
DSYNC
PDWN
Active LOW, Power Down. The power down func-
tion shuts down the analog and digital circuits.
8
DGND
VREF+
VREF–
AIN0/D0
AIN1/D1
AIN4/D4
AIN5/D5
9
Positive Differential Reference Input
Negative Differential Reference Input
Analog Input 0 / Data I/O 0
Analog Input 1 / Data I/O 1
Analog Input 4 / Data I/O 4
Analog Input 5 / Data I/O 5
Analog Input 6 / Data I/O 6
Analog Input 7 / Data I/O 7
Analog Input 2 / Data I/O 2
Analog Input 3 / Data I/O 3
Analog Input Common, connect to AGND if unused.
Analog Ground
8
DGND
VREF+
VREF–
Digital Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
9
Positive Differential Reference Input
Negative Differential Reference Input
Analog Input 0 / Data I/O 0
Analog Input 1 / Data I/O 1
Analog Input 2 / Data I/O 2
Analog Input 3 / Data I/O 3
Analog Input Common, connect to AGND if unused.
Analog Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A
A
IN0/D0
IN1/D1
A
IN6/D6
AIN2/D2
IN3/D3
AIN7/D7
AIN2/D2
AIN3/D3
AINCOM
AGND
AVDD
POL
CS
DIN
DOUT
A
AINCOM
AGND
AVDD
POL
Analog Power Supply
Analog Power Supply
Serial Clock Polarity
Active LOW, Chip Select
Serial Data Input, Schmitt Trigger
Serial Data Output
Serial Clock, Schmitt Trigger
Active LOW, Data Ready
Buffer Enable
Serial Clock Polarity
CS
Active LOW, Chip Select
Serial Data Input, Schmitt Trigger
Serial Data Output
DIN
DOUT
SCLK
DRDY
BUFEN
Serial Clock, Schmitt Trigger
Active LOW, Data Ready
Buffer Enable
SCLK
DRDY
BUFEN
ADS1240, 1241
5
SBAS173C
www.ti.com
TIMING DIAGRAMS
CS
t3
t1
t2
t10
SCLK
(POL = 0)
SCLK
(POL = 1)
t2
t4
t5
t6
t11
DIN
MSB
LSB
t7
t8
t9
(Command or Command and Data)
MSB(1)
LSB(1)
DOUT
NOTE: (1) Bit order = 0.
ADS1240 or ADS1241
Resets On
SCLK Reset Waveform
Falling Edge
300 • tOSC < t12 < 500 • tOSC
t13 : > 5 • tOSC
t13
t13
550 • tOSC < t14 < 750 • tOSC
SCLK
1050 • tOSC < t15 < 1250 • tOSC
t12
t14
t15
DIAGRAM 1.
t16
tDATA
DRDY
RESET, DSYNC, PDWN
t17
t18
SCLK
t19
DIAGRAM 2.
TIMING CHARACTERISTICS TABLES
SPEC
DESCRIPTION
MIN
MAX
UNITS
t1
SCLK Period
4
tOSC Periods
3
DRDY Periods
t2
t3
t4
t5
t6
SCLK Pulse Width, HIGH and LOW
CS low to first SCLK Edge; Setup Time(2)
DIN Valid to SCLK Edge; Setup Time
Valid DIN to SCLK Edge; Hold Time
200
0
ns
ns
ns
ns
50
50
Delay between last SCLK edge for DIN and first SCLK edge for DOUT
:
RDATA, RDATAC, RREG, WREG
SCLK Edge to Valid New DOUT
50
tOSC Periods
ns
(1)
t7
50
10
(1)
t8
SCLK Edge to DOUT, Hold Time
0
6
ns
t9
Last SCLK Edge to DOUT Tri-State
tOSC Periods
NOTE: DOUT goes tri-state immediately when CS goes HIGH.
CS LOW time after final SCLK edge.
t10
t11
0
ns
Final SCLK edge of one command until first edge SCLK
of next command:
RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL
SELFCAL
4
2
4
16
4
tOSC Periods
DRDY Periods
DRDY Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
RESET (also SCLK Reset or RESET Pin)
Pulse Width
Allowed analog input change for next valid conversion.
DOR update, DOR data not valid.
First SCLK after DRDY goes LOW:
RDATAC Mode
t16
t17
t18
t19
5000
4
10
0
tOSC Periods
tOSC Periods
Any other mode
NOTES: (1) Load = 20pF 10kΩ to DGND.
(2) CS may be tied LOW.
ADS1240, 1241
6
SBAS173C
www.ti.com
TYPICAL CHARACTERISTICS
All specifications, AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
EFFECTIVE NUMBER OF BITS vs PGA SETTING
EFFECTIVE NUMBER OF BITS vs PGA SETTING
DR = 10
22
21
20
19
18
17
16
15
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
DR = 10
DR = 01
DR = 01
DR = 00
DR = 00
Buffer ON
Buffer OFF
1
2
4
8
16
32
64
128
1
2
4
8
16
32
64
128
PGA Setting
PGA Setting
EFFECTIVE NUMBER OF BITS vs PGA SETTING
NOISE vs INPUT SIGNAL
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
DR = 10
DR = 01
DR = 00
Buffer OFF, VREF = 1.25V
–2.5
–1.5
–0.5
0.5
1.5
2.5
1
2
4
8
16
32
64
128
VIN (V)
PGA Setting
COMMON-MODE REJECTION RATIO
vs FREQUENCY
POWER SUPPLY REJECTION RATIO
vs FREQUENCY
140
120
100
80
140
120
100
80
60
60
40
40
20
20
Buffer ON
10
Buffer ON
10
0
0
1
100
1k
10k
100k
1
100
1k
10k
100k
Frequency of Power Supply (Hz)
Frequency of Power Supply (Hz)
ADS1240, 1241
7
SBAS173C
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
All specifications, AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
GAIN vs TEMPERATURE
OFFSET vs TEMPERATURE
(Cal at 25°C)
(Cal at 25°C)
1.00010
1.00006
1.00002
0.99998
0.99994
0.99990
0.99986
50
0
PGA16
PGA1
–50
PGA64
–100
–150
–200
PGA128
–50
–30
–10
10
30
50
70
90
–50
–30
–10
10
30
50
70
90
Temperature (°C)
Temperature (°C)
ANALOG CURRENT vs TEMPERATURE
AVDD = 5
INTEGRAL NONLINEARITY vs INPUT SIGNAL
10
8
150
140
130
120
110
100
90
–40°C
6
4
+85°C
2
0
AVDD = 3
–2
–4
–6
–8
–10
80
+25°C
70
Buffer OFF
60
50
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0 1.5 2.0 2.5
–50
–30
–10
10
30
50
70
90
VIN (V)
Temperature (°C)
ANALOG CURRENT vs PGA
DIGITAL CURRENT vs SUPPLY
900
800
700
600
500
400
300
200
100
0
300
250
200
150
100
50
AVDD = 5V, Buffer = ON
Buffer = OFF
Normal
2.45MHz
SLEEP
4.91MHz
Normal
4.91MHz
AVDD = 3V, Buffer = ON
Buffer = OFF
SLEEP
2.45MHz
Power Down
3.5
0
1
2
4
8
16
32
64
128
3.0
4.0
4.5
5.0
PGA Setting
V
DD (V)
ADS1240, 1241
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TYPICAL CHARACTERISTICS (Cont.)
All specifications, AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
OFFSET DAC
OFFSET vs TEMPERATURE
NOISE HISTOGRAM
(Cal at 25°C)
3500
3000
2500
2000
1500
1000
500
200
170
140
110
80
10k Readings
IN = 0V
V
50
20
–10
–40
–70
–100
0
–50
–30
–10
10
30
50
70
90
–3.5 –3.0 –2.5 –2.0 –1.5 –1 –0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
Temperature (°C)
ppm of FS
OFFSET DAC
GAIN vs TEMPERATURE
(Cal at 25°C)
OFFSET DAC
NOISE vs SETTING
1.00020
1.00016
1.00012
1.00008
1.00004
1.00000
0.99996
0.99992
0.99988
0.99984
0.99980
0.99976
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–50
–30
–10
10
30
50
70
90
–128 –96
–64 –32
0
32
64
96
128
Temperature (°C)
Offset DAC Setting
ADS1240, 1241
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channel. With this method, it is possible to have up to eight
single-ended input channels or four independent differential
input channels for the ADS1241, and four single-ended input
channels or two independent differential input channels for
the ADS1240. Note that AINCOM can be treated as an input
channel.
OVERVIEW
INPUT MULTIPLEXER
The input multiplexer provides for any combination of differ-
ential inputs to be selected on any of the input channels, as
shown in Figure 1. For example, if AIN0 is selected as the
positive differential input channel, any other channel can be
selected as the negative terminal for the differential input
The ADS1240 and ADS1241 feature a single-cycle settling
digital filter that provides valid data on the first conversion
after a new channel selection. In order to minimize the
settling error, synchronize MUX changes to the conversion
beginning, which is indicated by the falling edge of DRDY. In
other words, issuing a MUX change through the WREG
command immediately after DRDY goes LOW minimizes the
settling error. Increasing the time between the conversion
beginning (DRDY goes LOW) and the MUX change com-
mand (tDELAY) results in a settling error in the conversion
data, as shown in Figure 2.
A
IN0/D0
AIN1/D1
AIN2/D2
AIN3/D3
AIN4/D4
AIN5/D5
AIN6/D6
AIN7/D7
AINCOM
AVDD
Burnout Current Source
BURNOUT CURRENT SOURCES
The Burnout Current Sources can be used to detect sensor
short-circuit or open-circuit conditions. Setting the Burnout
Current Sources (BOCS) bit in the SETUP register activates
two 2µA current sources called burnout current sources. One
of the current sources is connected to the converter’s nega-
tive input and the other is connected to the converter’s
positive input.
Input
Buffer
Burnout Current Source
AGND
Figure 3 shows the situation for an open-circuit sensor. This
is a potential failure mode for many kinds of remotely con-
nected sensors. The current source on the positive input acts
as a pull-up, causing the positive input to go to the positive
analog supply, and the current source on the negative input
acts as a pull-down, causing the negative input to go to
ground. The ADS1240/41 therefore outputs full-scale (7FFFFF
Hex).
ADS1241
Only
FIGURE 1. Input Multiplexer Configuration.
New Conversion Begins,
Complete Previous Conversion
Previous Conversion Data
New Conversion Complete
DRDY
tDELAY
SCLK
(POL = 0)
DIN
MSB
LSB
SETTLING ERROR vs DELAY TIME
CLK = 2.4576MHz
f
10.000000
1.000000
0.100000
0.010000
0.001000
0.000100
0.000010
0.000001
0
2
4
6
8
10
12
14
16
Delay Time, tDELAY (ms)
FIGURE 2. Input Multiplexer Configuration.
10
ADS1240, 1241
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The buffer draws additional current when activated. The
current required by the buffer depends on the PGA setting.
When the PGA is set to 1, the buffer uses approximately
50µA; when the PGA is set to 128, the buffer uses approxi-
AVDD
2µA
mately 500µA.
AVDD
PGA
ADC
OPEN CIRCUIT
CODE = 0x7FFFFFH
The Programmable Gain Amplifier (PGA) can be set to gains
of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the
effective resolution of the A/D converter. For instance, with a
PGA of 1 on a 5V full-scale signal, the A/D converter can
resolve down to 1µV. With a PGA of 128 and a full-scale signal
of 39mV, the A/D converter can resolve down to 75nV. AVDD
0V
2µA
current increases with PGA settings higher than 4.
FIGURE 3. Burnout detection while sensor is open-circuited.
OFFSET DAC
Figure 4 shows a short-circuited sensor. Since the inputs are
shorted and at the same potential, the ADS1240/41 signal
outputs are approximately zero. (Note that the code for
shorted inputs is not exactly zero due to internal series
The input to the PGA can be shifted by half the full-scale input
range of the PGA using the Offset DAC (ODAC) register. The
ODAC register is an 8-bit value; the MSB is the sign and the
seven LSBs provide the magnitude of the offset. Using the
offset DAC does not reduce the performance of the A/D
converter. For more details on the ODAC, please refer to TI
application report SBAA077.
resistance, low-level noise and other error sources.)
AVDD
MODULATOR
2µA
The modulator is a single-loop second-order system. The
modulator runs at a clock speed (fMOD) that is derived from
the external clock (fOSC). The frequency division is deter-
mined by the SPEED bit in the SETUP register, as shown in
Table I.
AVDD/2
SHORT
CIRCUIT
ADC
CODE
0
AVDD/2
2µA
SPEED
BIT
DR BITS
01
1st NOTCH
FREQ.
fOSC
fMOD
00
10
2.4576MHz
0
1
0
1
19,200Hz 15Hz 7.5Hz 3.75Hz
9,600Hz 7.5Hz 3.75Hz 1.875Hz
50/60Hz
25/30Hz
100/120Hz
50/60Hz
4.9152MHz
38,400Hz 30Hz
15Hz
7.5Hz
19,200Hz 15Hz 7.5Hz 3.75Hz
FIGURE 4. Burnout detection while sensor is short-circuited.
TABLE I. Output Configuration.
INPUT BUFFER
CALIBRATION
The input impedance of the ADS1240/41 without the buffer
enabled is approximately 5MΩ/PGA. For systems requiring
very high input impedance, the ADS1240/41 provides a
chopper-stabilized differential FET-input voltage buffer. When
activated, the buffer raises the ADS1240/41 input impedance
to approximately 5GΩ.
The offset and gain errors can be minimized with calibration.
The ADS1240 and ADS1241 support both self and system
calibration.
Self-calibration of the ADS1240 and ADS1241 corrects inter-
nal offset and gain errors and is handled by three commands:
SELFCAL, SELFGAL, and SLEFOCAL. The SELFCAL com-
mand performs both an offset and gain calibration. SELFGCAL
performs a gain calibration and SELFOCAL performs an
offset calibration, each of which takes two tDATA periods to
complete. During self-calibration, the ADC inputs are discon-
nected internally from the input pins. The PGA must be set to
1 prior to issuing a SELFCAL or SELFGCAL command. Any
PGA is allowed when issuing a SELFOCAL command. For
example, if using PGA = 64, first set PGA = 1 and issue
The buffer’s input range is approximately 50mV to AVDD
–
1.5V. The buffer’s linearity will degrade beyond this range.
Differential signals should be adjusted so that both signals
are within the buffer’s input range.
The buffer can be enabled using the BUFEN pin or the
BUFEN bit in the ACR register. The buffer is on when the
BUFEN pin is high and the BUFEN bit is set to one. If the
BUFEN pin is low, the buffer is disabled. If the BUFEN bit is
set to zero, the buffer is also disabled.
ADS1240, 1241
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SELFGCAL. Afterwards set PGA = 64 and issue SELFOCAL.
For operation with a reference voltage greater than (AVDD
1.5) volts, the buffer must also be turned off during gain self-
calibration to avoid exceeding the buffer input range.
–
XIN
C1
C2
Crystal
System calibration corrects both internal and external offset
and gain errors. While performing system calibration, the
appropriate signal must be applied to the inputs. The system
offset calibration command (SYSOCAL) requires a zero input
differential signal (see Table IV, page 18). It then computes
the offset that nullifies the offset in the system. The system
gain calibration command (SYSGCAL) requires a positive
full-scale input signal. It then computes a value to nullify the
gain error in the system. Each of these calibrations takes two
XOUT
FIGURE 5. Crystal Connection.
CLOCK
PART
NUMBER
SOURCE FREQUENCY
C1
C2
t
DATA periods to complete. System gain calibration is recom-
Crystal
Crystal
Crystal
Crystal
2.4576
4.9152
4.9152
4.9152
0-20pF 0-20pF ECS, ECSD 2.45 - 32
0-20pF 0-20pF
0-20pF 0-20pF
ECS, ECSL 4.91
ECS, ECSD 4.91
mended for the best gain calibration at higher PGAs.
Calibration should be performed after power on, a change in
temperature, or a change of the PGA. The RANGE bit (ACR bit
2) must be zero during calibration.
0-20pF 0-20pF CTS, MP 042 4M9182
TABLE II. Recommended Crystals.
Calibration removes the effects of the ODAC; therefore, dis-
able the ODAC during calibration, and enable again after
calibration is complete.
DIGITAL FILTER
The ADS1240 and ADS1241 have a 1279 tap linear phase
Finite Impulse Response (FIR) digital filter that a user can
configure for various output data rates. When a 2.4576MHz
crystal is used, the device can be programmed for an output
data rate of 15Hz, 7.5Hz, or 3.75Hz. Under these conditions,
the digital filter rejects both 50Hz and 60Hz interference. Figure
6 shows the digital filter frequency response for data output
rates of 15Hz, 7.5Hz, and 3.75Hz.
At the completion of calibration, the DRDY signal goes low,
indicating the calibration is finished. The first data after
calibration should be discarded since it may be corrupt from
calibration data remaining in the filter. The second data is
always valid.
EXTERNAL VOLTAGE REFERENCE
If a different data output rate is desired, a different crystal
frequency can be used. However, the rejection frequencies
shift accordingly. For example, a 3.6864MHz master clock with
the default register condition has:
The ADS1240 and ADS1241 require an external voltage
reference. The selection for the voltage reference value is
made through the ACR register.
The external voltage reference is differential and is repre-
sented by the voltage difference between the pins: +VREF
and –VREF. The absolute voltage on either pin, +VREF or
–VREF, can range from AGND to AVDD. However, the follow-
ing limitations apply:
(3.6864MHz/2.4576MHz) • 15Hz = 22.5Hz data output rate
and the first and second notch is:
1.5 • (50Hz and 60Hz) = 75Hz and 90Hz
For AVDD = 5.0V and RANGE = 0 in the ACR, the differential
DATA I/O INTERFACE
V
REF must not exceed 2.5V.
For AVDD = 5.0V and RANGE = 1 in the ACR, the differential
REF must not exceed 5V.
For AVDD = 3.0V and RANGE = 0 in the ACR, the differential
REF must not exceed 1.25V.
The ADS1240 has four pins and the ADS1241 has eight pins
that serve a dual purpose as both analog inputs and data
I/O. These pins are powered from AVDD and are configured
through the IOCON, DIR, and DIO registers. These pins
can be individually configured as either analog inputs or data
I/O. See Figure 7 (page 14) for the equivalent schematic of
an Analog/Data I/O pin.
V
V
For AVDD = 3.0V and RANGE = 1 in the ACR, the differential
VREF must not exceed 2.5V.
The IOCON register defines the pin as either an analog input
or data I/O. The power-up state is an analog input. If the pin
is configured as an analog input in the IOCON register, the
DIR and DIO registers have no effect on the state of the pin.
CLOCK GENERATOR
The clock source for the ADS1240 and ADS1241 can be
provided from a crystal, oscillator, or external clock. When the
clock source is a crystal, external capacitors must be provided
to ensure start-up and stable clock frequency. This is shown in
both Figure 5 and Table II. XOUT is only for use with external
crystals and it should not be used as a clock driver for external
If the pin is configured as data I/O in the IOCON register,
then DIR and DIO are used to control the state of the pin.
The DIR register controls the direction of the data pin, either
as an input or output. If the pin is configured as an input in
the DIR register, then the corresponding DIO register bit
reflects the state of the pin. Make sure the pin is driven to a
circuitry.
ADS1240, 1241
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ADS1240 AND ADS1241
FILTER RESPONSE WHEN fDATA = 15Hz
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 15Hz
0
–20
–40
–50
–60
–40
–70
–60
–80
–80
–90
–100
–120
–140
–160
–180
–100
–110
–120
–130
–140
0
20
40 60
80 100 120 140 160 180 200
Frequency (Hz)
45
50
55
60
65
Frequency (Hz)
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 7.5Hz
ADS1240 AND ADS1241
FILTER RESPONSE WHEN fDATA = 7.5Hz
–40
–50
0
–20
–60
–40
–70
–60
–80
–80
–90
–100
–120
–140
–160
–180
–100
–110
–120
–130
–140
0
20
40 60
80 100 120 140 160 180 200
Frequency (Hz)
45
50
55
60
65
Frequency (Hz)
ADS1240 AND ADS1241
FILTER RESPONSE WHEN fDATA = 3.75Hz
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 3.75Hz
0
–20
–40
–50
–60
–40
–70
–60
–80
–80
–90
–100
–120
–140
–160
–180
–100
–110
–120
–130
–140
0
20
40 60
80 100 120 140 160 180 200
Frequency (Hz)
45
50
55
60
65
Frequency (Hz)
f
OSC = 2.4576MHz, SPEED = 0 or fOSC = 4.9152MHz, SPEED = 1
ATTENUATION
DATA
–3dB
OUTPUT RATE
BANDWIDTH
fIN = 50 ± 0.3Hz
fIN = 60 ± 0.3Hz
fIN = 50 ± 1Hz
fIN = 60 ± 1Hz
15Hz
7.5Hz
3.75Hz
14.6Hz
3.44Hz
1.65Hz
–80.8dB
–85.9dB
–93.8dB
–87.3dB
–87.4dB
–88.6dB
–68.5dB
–71.5dB
–86.8dB
–76.1dB
–76.2dB
–77.3dB
FIGURE 6. Filter Frequency Responses.
ADS1240, 1241
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logic one or zero when configured as an input to prevent
excess current dissipation. If the pin is configured as an
output in the DIR register, then the corresponding DIO
register bit value determines the state of the output pin
(0 = AGND, 1 = AVDD).
Data Continuous Mode (RDATAC) command should not be
issued when DIN and DOUT are connected. While in RDATAC
mode, DIN looks for the STOPC or RESET command. If
either of these 8-bit bytes appear on DOUT (which is con-
nected to DIN), the RDATAC mode ends.
It is still possible to perform A/D conversions on a pin
configured as data I/O. This may be useful as a test mode,
where the data I/O pin is driven and an A/D conversion is
done on the pin.
DATA READY DRDY PIN
The DRDY line is used as a status signal to indicate when
data is ready to be read from the internal data register.
DRDY goes LOW when a new data word is available in the
DOR register. It is reset HIGH when a read operation from
the data register is complete. It also goes HIGH prior to the
updating of the output register to indicate when not to read
from the device to ensure that a data read is not attempted
while the register is being updated.
IOCON
DIR
DIO WRITE
AINx/Dx
The status of DRDY can also be obtained by interrogating bit
7 of the ACR register (address 2H). The serial interface can
operate in 3-wire mode by tying the CS input LOW. In this
case, the SCLK, DIN, and DOUT lines are used to communi-
cate with the ADS1240 and ADS1241. This scheme is
suitable for interfacing to microcontrollers. If CS is required
as a decoding signal, it can be generated from a port bit of
the microcontroller.
To Analog Mux
DIO READ
FIGURE 7. Analog/Data Interface Pin.
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) allows a controller to
communicate synchronously with the ADS1240 and ADS1241.
The ADS1240 and ADS1241 operate in slave-only mode.
The serial interface is a standard four-wire SPI (CS, SCLK,
DIN and DOUT) interface that supports both serial clock
polarities (POL pin).
DSYNC OPERATION
Synchronization can be achieved either through the DSYNC
pin or the DSYNC command. When the DSYNC pin is used,
the digital circuitry is reset on the falling edge of DSYNC
While DSYNC is LOW, the serial interface is deactivated.
Reset is released when DSYNC is taken HIGH. Synchroni-
zation occurs on the next rising edge of the system clock
after DSYNC is taken HIGH.
.
Chip Select (CS
)
The chip select (CS) input must be externally asserted
before communicating with the ADS1240 or ADS1241. CS
must stay LOW for the duration of the communication.
Whenever CS goes HIGH, the serial interface is reset. CS
may be hard-wired LOW.
When the DSYNC command is sent, the digital filter is reset
on the edge of the last SCLK of the DSYNC command. The
modulator is held in RESET until the next edge of SCLK is
detected. Synchronization occurs on the next rising edge of
the system clock after the first SCLK following the DSYNC
command.
Serial Clock (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input
and is used to clock DIN and DOUT data. Make sure to have
a clean SCLK to prevent accidental double-shifting of the
data. If SCLK is not toggled within 3 DRDY pulses, the serial
interface resets on the next SCLK pulse and starts a new
communication cycle. A special pattern on SCLK resets the
entire chip; see the RESET section for additional information.
POWER-UP—SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotoni-
cally.
Clock Polarity (POL)
The clock polarity input (POL) controls the polarity of SCLK.
When POL is LOW, data is clocked on the falling edge of
SCLK and SCLK should be idled LOW. Likewise, when POL
is HIGH, the data is clocked on the rising edge of SCLK and
SCLK should be idled HIGH.
RESET
The user can reset the registers to their default values in
three different ways: by asserting the RESET pin; by issuing
the RESET command; or by applying a special waveform on
the SCLK (the SCLK Reset Waveform, as shown in the
Timing Diagram). Note: if both POL and SCLK pins are held
high, applying the SCLK Reset Waveform to the CS pin also
resets the part.
Data Input (DIN) and Data Output (DOUT
)
The data input (DIN) and data output (DOUT) receive and send
data from the ADS1240 and ADS1241. DOUT is high imped-
ance when not in use to allow DIN and DOUT to be connected
together and driven by a bidirectional bus. Note: the Read
ADS1240, 1241
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SBAS173C
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tion needed to configure the part, such as data format,
multiplexer settings, calibration settings, data rate, etc. The
set of the 16 registers are shown in Table III.
ADS1240 AND ADS1241
REGISTER
The operation of the device is set up through individual
registers. Collectively, the registers contain all the informa-
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
SETUP
MUX
ID
ID
ID
ID
BOCS
NSEL3
BIT ORDER
OSET3
DIO_3
PGA2
NSEL2
RANGE
OSET2
DIO_2
DIR_2
IO2
PGA1
NSEL1
DR1
PGA0
NSEL0
DR0
PSEL3
DRDY
SIGN
PSEL2
U/B
PSEL1
SPEED
OSET5
DIO_5
DIR_5
IO5
PSEL0
BUFEN
OSET4
DIO_4
DIR_4
IO4
ACR
ODAC
DIO
OSET6
DIO_6
DIR_6
IO6
OSET1
DIO_1
DIR_1
IO1
OSET0
DIO_0
DIR_0
IO0
DIO_7
DIR_7
IO7
DIR
DIR_3
IOCON
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
DOR2
DOR1
DOR0
IO3
OCR07
OCR15
OCR23
FSR07
FSR15
FSR23
DOR23
DOR15
DOR07
OCR06
OCR14
OCR22
FSR06
FSR14
FSR22
DOR22
DOR14
DOR16
OCR05
OCR13
OCR21
FSR05
FSR13
FSR21
DOR21
DOR13
FSR21
OCR04
OCR12
OCR20
FSR04
FSR12
FSR20
DOR20
DOR12
DOR04
OCR03
OCR11
OCR19
FSR03
FSR11
FSR19
DOR19
DOR11
DOR03
OCR02
OCR10
OCR18
FSR02
FSR10
FSR18
DOR18
DOR10
DOR02
OCR01
OCR09
OCR17
FSR01
FSR09
FSR17
DOR17
DOR09
DOR01
OCR00
OCR08
OCR16
FSR00
FSR08
FSR16
DOR16
DOR08
DOR00
TABLE III. Registers.
DETAILED REGISTER DEFINITIONS
SETUP (Address 00H) Setup Register
Reset Value = iiii0000
MUX (Address 01H) Multiplexer Control Register
Reset Value = 01H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
NSEL1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL0
ID
ID
ID
ID
BOCS
PGA2
PGA1
PGA0
bit 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
bit 7-4 Factory Programmed Bits
bit 3 BOCS: Burnout Current Source
Select
0000 = AIN0 (default)
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
0 = Disabled (default)
1 = Enabled
bit 2-0 PGA2: PGA1: PGA0: Programmable Gain Amplifier
Gain Selection
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
1xxx = AINCOM (except when xxx = 111)
1111 = Reserved
bit 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel
Select
0000 = AIN0
0001 = AIN1 (default)
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when xxx = 111)
1111 = Reserved
ADS1240, 1241
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ACR (Address 02H) Analog Control Register
ODAC (Address 03 ) Offset DAC
Reset Value = X0H
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
DR1
bit 0
DR0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DRDY
U/B
SPEED
BUFEN BIT ORDER RANGE
SIGN
OSET6
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
bit 7
DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
U/ : Data Format
bit 7
Sign
0 = Positive
1 = Negative
bit 6
B
0 = Bipolar (default)
1 = Unipolar
VREF
OSET[6 : 0]
127
Offset =
•
RANGE = 0
RANGE = 1
2 • PGA
U/B
ANALOG INPUT
DIGITAL OUTPUT (Hex)
+FSR
Zero
0x7FFFFF
0x000000
0x800000
0xFFFFFF
0x000000
0x000000
VREF
OSET[6 : 0]
127
0
Offset =
•
4 • PGA
–FSR
+FSR
Zero
1
NOTE: The offset DAC must be enabled after calibration or the calibration
nullifies the effects.
–FSR
bit 5
bit 4
bit 3
SPEED: Modulator Clock Speed
0 = fMOD = fOSC/128 (default)
1 = fMOD = fOSC/256
DIO (Address 04H) Data I/O
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
BUFEN: Buffer Enable
0 = Buffer Disabled (default)
1 = Buffer Enabled
DIO 7
DIO 6
DIO 5
DIO 4
DIO 3
DIO 2
DIO 1
DIO 0
If the IOCON register is configured for data, a value written
to this register appears on the data I/O pins if the pin is
configured as an output in the DIR register. Reading this
register returns the value of the data I/O pins.
BIT ORDER: Data Output Bit Order
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
This configuration bit controls only the bit order
within the byte of data that is shifted out. Data is
always shifted out of the part most significant byte
first. Data is always shifted into the part most
significant bit first.
Bit 4 to bit 7 is not used in ADS1240.
DIR (Address 05H) Direction Control for Data I/O
Reset Value = FFH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 2
RANGE: Range Select
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
0 = Full-Scale Input Range equal to ±VREF
(default).
1 = Full-Scale Input Range equal to ±1/2 VREF
Each bit controls whether the corresponding data I/O pin is
an output (= 0) or input (= 1). The default power-up state is
as inputs.
NOTE: This allows reference voltages as high as
AVDD, but even with a 5V reference voltage the
calibration must be performed with this bit set to 0.
Bit 4 to bit 7 is not used in ADS1240.
bit 1-0 DR1: DR0: Data Rate
(fOSC = 2.4576MHz, SPEED = 0)
IOCON (Address 06H) I/O Configuration Register
Reset Value = 00H
00 = 15Hz (default)
01 = 7.5Hz
10 = 3.75Hz
bit 7
bit 6
bit 5
bit 4
IO4
bit 3
IO3
bit 2
IO2
bit 1
IO1
bit 0
IO0
IO7
IO6
IO5
11 = Reserved
bit 7-0 IO7: IO0: Data I/O Configuration
0 = Analog (default)
1 = Data
Configuring the pin as a data I/O pin allows it to be controlled
through the DIO and DIR registers.
Bit 4 to bit 7 is not used in ADS1240.
OCR0 (Address 07H) Offset Calibration Coefficient
(Least Significant Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
ADS1240, 1241
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OCR1 (Address 08H) Offset Calibration Coefficient
(Middle Byte)
FSR2 (Address 0CH) Full-Scale Register
(Most Significant Byte)
Reset Value = 00H
Reset Value = 55H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
FSR23
FSR22
FSR21
FSR20
FSR19
FSR18
FSR17
FSR16
OCR2 (Address 09H) Offset Calibration Coefficient
(Most Significant Byte)
Reset Value = 00H
DOR2 (Address 0DH) Data Output Register
(Most Significant Byte) (Read Only)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DOR23
DOR22
DOR21
DOR20
DOR19
DOR18
DOR17
DOR16
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
FSR0 (Address 0AH) Full-Scale Register
(Least Significant Byte)
DOR1 (Address 0EH) Data Output Register
(Middle Byte) (Read Only)
Reset Value = 59H
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
DOR15
DOR14
DOR13
DOR12
DOR11
DOR10
DOR09
DOR08
FSR1 (Address 0BH) Full-Scale Register
(Middle Byte)
Reset Value = 55H
DOR0 (Address 0FH) Data Output Register
(Least Significant Byte) (Read Only)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR15
FSR14
FSR13
FSR12
FSR11
FSR10
FSR09
FSR08
DOR07
DOR06
DOR05
DOR04
DOR03
DOR02
DOR01
DOR00
ADS1240, 1241
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ADS1240 AND ADS1241 CONTROL COMMAND DEFINITIONS
The commands listed in Table IV control the operations of
the ADS1240 and ADS1241. Some of the commands are
stand-alone commands (e.g., RESET) while others require
additional bytes (e.g., WREG requires the count and data
bytes).
Operands:
n = count (0 to 127)
r = register (0 to 15)
x = don’t care
COMMANDS
DESCRIPTION
OP CODE
2nd COMMAND BYTE
RDATA
RDATAC
STOPC
RREG
WREG
SELFCAL
SELFOCAL
SELFGCAL
SYSOCAL
SYSGCAL
WAKEUP
DSYNC
Read Data
Read Data Continuously
Stop Read Data Continuously
Read from REG “rrrr”
Write to REG “rrrr”
Offset and Gain Self Cal
Self Offset Cal
Self Gain Cal
Sys Offset Cal
Sys GainCal
Wakup from SLEEP Mode
Sync DRDY
0000 0001 (01H)
0000 0011 (03H)
0000 1111 (0FH)
0001 r r r r (1xH)
0101 r r r r (5xH)
1111 0000 (F0H)
1111 0001 (F1H)
1111 0010 (F2H)
1111 0011 (F3H)
1111 0100 (F4H)
1111 1011 (FBH)
1111 1100 (FCH)
1111 1101 (FDH)
1111 1110 (FEH)
—
—
—
xxxx_nnnn (# of regs-1)
xxxx_nnnn (# of regs-1)
—
—
—
—
—
—
—
—
—
SLEEP
RESET
Put in SLEEP Mode
Reset to Power-Up Values
NOTE: The received data format is always MSB First; the data out format is set by the BIT ORDER bit in the ACR register.
TABLE IV. Command Summary.
RDATA–Read Data
RDATAC–Read Data Continuous
Description:Readthemostrecentconversionresultfromthe
Data Output Register (DOR). This is a 24-bit value.
Description: Read Data Continuous mode enables the con-
tinuous output of new data on each DRDY. This command
eliminates the need to send the Read Data Command on each
DRDY. This mode may be terminated by either the STOPC
command or the RESET command. Wait at least 10 fOSC after
DRDY falls before reading.
Operands: None
Bytes:
1
Encoding: 0000 0001
Data Transfer Sequence:
Operands: None
Bytes:
1
Encoding: 0000 0011
0000 0001
• • •(1)
xxxx xxxx
MSB
xxxx xxxx
Mid-Byte
xxxx xxxx
LSB
DIN
Data Transfer Sequence:
Command terminated when “uuuu uuuu” equals STOPC or
RESET.
DOUT
DRDY
NOTE: (1) For wait time, refer to timing specification.
DIN
0000 0011
• • •(1)
uuuu uuuu
MSB
uuuu uuuu
Mid-Byte
uuuu uuuu
LSB
• • •
DOUT
DRDY
DOUT
• • •
MSB
Mid-Byte
LSB
NOTE: (1) For wait time, refer to timing specification.
ADS1240, 1241
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STOPC–Stop Continuous
SELFCAL–Offset and Gain Self Calibration
Description: Ends the continuous data output mode. Issue
after DRDY goes LOW.
Description: Starts the process of self calibration. The Offset
Calibration Register (OCR) and the Full-Scale Register (FSR)
are updated with new values after this operation.
Operands: None
Bytes:
1
Operands: None
Encoding: 0000 1111
Bytes:
1
Data Transfer Sequence:
Encoding: 1111 0000
Data Transfer Sequence:
DRDY
1111 0000
DIN
xxx
0000 1111
DIN
SELFOCAL–Offset Self Calibration
RREG–Read from Registers
Description: Starts the process of self-calibration for offset.
The Offset Calibration Register (OCR) is updated after this
operation.
Description: Output the data from up to 16 registers starting
with the register address specified as part of the instruction.
The number of registers read will be one plus the second byte
count. If the count exceeds the remaining registers, the ad-
dresses wrap back to the beginning.
Operands: None
Bytes:
1
Operands: r, n
Encoding: 1111 0001
Bytes:
2
Data Transfer Sequence:
Encoding: 0001 rrrr xxxx nnnn
Data Transfer Sequence:
Read Two Registers Starting from Register 01H (MUX)
1111 0001
DIN
0001 0001
0000 0001
• • •(1)
xxxx xxxx
MUX
xxxx xxxx
ACR
DIN
SELFGCAL–Gain Self Calibration
Description: Starts the process of self-calibration for gain.
TheFull-ScaleRegister(FSR)isupdatedwithnewvaluesafter
this operation.
DOUT
NOTE: (1) For wait time, refer to timing specification.
Operands: None
Bytes:
1
WREG–Write to Registers
Encoding: 1111 0010
Description: Write to the registers starting with the register
address specified as part of the instruction. The number of
registers that will be written is one plus the value of the second
byte.
Data Transfer Sequence:
1111 0010
DIN
Operands: r, n
Bytes:
2
Encoding: 0101 rrrr xxxx nnnn
Data Transfer Sequence:
Write Two Registers Starting from 04H (DIO)
DIN
0101 0100
xxxx 0001
Data for DIO
Data for DIR
ADS1240, 1241
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DSYNC–Sync DRDY
SYSOCAL–System Offset Calibration
Description: Synchronizes the ADS1240 and ADS1241 to an
external event.
Description: Initiates a system offset calibration. The input
should be set to 0V, and the ADS1240 and ADS1241 compute
the OCR value that compensates for offset errors. The Offset
CalibrationRegister(OCR)isupdatedafterthisoperation. The
user must apply a zero input signal to the appropriate analog
inputs. The OCR register is automatically updated afterwards.
Operands: None
Bytes:
1
Encoding: 1111 1100
Data Transfer Sequence:
Operands: None
Bytes:
1
1111 1100
DIN
Encoding: 1111 0011
Data Transfer Sequence:
SLEEP–Sleep Mode
1111 0011
DIN
Description: Puts the ADS1240 and ADS1241 into a low
power sleep mode. To exit sleep mode, issue the WAKEUP
command.
SYSGCAL–System Gain Calibration
Operands: None
Description: Starts the system gain calibration process. For
a system gain calibration, the input should be set to the
reference voltage and the ADS1240 and ADS1241 compute
the FSR value that will compensate for gain errors. The FSR
is updated after this operation. To initiate a system gain
calibration, the user must apply a full-scale input signal to the
appropriate analog inputs. FCR register is updated automati-
cally.
Bytes:
1
Encoding: 1111 1101
Data Transfer Sequence:
1111 1101
DIN
RESET–Reset to Default Values
Operands: None
Description: Restore the registers to their power-up values.
This command stops the Read Continuous mode.
Bytes:
1
Encoding: 1111 0100
Operands: None
Data Transfer Sequence:
Bytes:
1
Encoding: 1111 1110
1111 0100
DIN
Data Transfer Sequence:
1111 1110
DIN
WAKEUP
Description:WakestheADS1240andADS1241fromSLEEP
mode.
Operands: None
Bytes:
1
Encoding: 1111 1011
Data Transfer Sequence:
1111 1011
DIN
ADS1240, 1241
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ADS1240.
APPLICATION EXAMPLES
GENERAL-PURPOSE WEIGH SCALE
HIGH PRECISION WEIGH SCALE
Figure 8 shows a typical schematic of a general-purpose
weigh scale application using the ADS1240. In this example,
the internal PGA is set to either 64 or 128 (depending on the
maximum output voltage of the load cell) so that the load cell
output can be directly applied to the differential inputs of
Figure 9 shows the typical schematic of a high-precision
weigh scale application using the ADS1240. The front-end
differential amplifier helps maximize the dynamic range.
2.7V ~ 5.25V
2.7V ~ 5.25V
EMI Filter
AVDD
VREF+
DVDD
VDD
EMI Filter
AIN0
DRDY
Load Cell
SCLK
DOUT
DOUT
CS
MSP430x4xx
or other µP
SPI
ADS1240
EMI Filter
AIN1
MCLK
GND
XIN
XOUT
VREF–
AGND
DGND
EMI Filter
FIGURE 8. Schematic of a General-Purpose Weigh Scale.
2.7V ~ 5.25V
EMI Filter
2.7V ~ 5.25V
AVDD
VREF+
DVDD
VDD
EMI Filter
RI
OPA2335
AIN0
Load Cell
RF
DRDY
SCLK
DOUT
DIN
MSP430x4xx
or other µP
ADS1240
ADS1241
CI
SPI
RG
RF
CS
RI
OPA2335
EMI Filter
EMI Filter
AIN1
MCLK
XIN
XOUT
VREF–
AGND
DGND
GND
G = 1 + 2 • RF/RG
FIGURE 9. Block Diagram for a High-Precision Weigh Scale.
ADS1240, 1241
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fOSC
fOSC
128 • 2SPEED
fMOD
=
=
mfactor
DEFINITION OF TERMS
An attempt has been made to be consistent with the termi-
nology used in this data sheet. In that regard, the definition
of each term is given as follows:
fSAMP—the frequency, or switching speed, of the input sam-
PGA SETTING
SAMPLING FREQUENCY
fOSC
1, 2, 4, 8
f SAMP
f SAMP
f SAMP
=
=
=
mfactor
Analog Input Voltage—the voltage at any one analog input
relative to AGND.
fOSC • 2
16
32
mfactor
Analog Input Differential Voltage—given by the following
equation: (IN+) – (IN–). Thus, a positive digital output is
produced whenever the analog input differential voltage is
positive, while a negative digital output is produced whenever
the differential is negative.
fOSC • 4
mfactor
fOSC • 8
64, 128
f SAMP
=
mfactor
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 1, the positive
full-scale output is produced when the analog input differen-
tial is 2.5V. The negative full-scale output is produced when
the differential is –2.5V. In each case, the actual input
voltages must remain within the AGND to AVDD range.
pling capacitor. The value is given by one of the following
equations:
f
DATA—the frequency of the digital output data produced by
the ADS1240 and ADS1241, fDATA is also referred to as the
Data Rate.
Conversion Cycle—the term conversion cycle usually refers
to a discrete A/D conversion operation, such as that per-
formed by a successive approximation converter. As used
here, a conversion cycle refers to the tDATA time period.
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1240 and ADS1241 is defined as
the input, that produces the positive full-scale digital output
minus the input, that produces the negative full-scale digital
output.
Data Rate—The rate at which conversions are completed.
See definition for fDATA
.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: [1.25V (positive full-scale) minus –1.25V (negative
full-scale)] = 2.5V.
fOSC
fDATA
=
128 • 2SPEED •1280 • 2DR
SPEED = 0, 1
DR = 0, 1, 2
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input has to change in order to observe a change in the
output data of one least significant bit. It is computed as
follows:
fOSC—the frequency of the crystal oscillator or CMOS com-
patible input signal at the XIN input of the ADS1240 and
ADS1241.
f
MOD—the frequency or speed at which the modulator of the
Full− Scale Range
LSB Weight =
ADS1240 and ADS1241 is running. This depends on the
SPEED bit as given by the following equation:
2N – 1
where N is the number of bits in the digital output.
t
DATA—the inverse of fDATA, or the period between each data
SPEED = 0
SPEED = 1
output.
mfactor
128
256
5V SUPPLY ANALOG INPUT(1)
GENERAL EQUATIONS
DIFFERENTIAL
FULL-SCALE RANGE INPUT VOLTAGES(2)
PGA OFFSET
RANGE
FULL-SCALE
RANGE
DIFFERENTIAL
INPUT VOLTAGES(2)
PGA SHIFT
RANGE
GAIN SETTING
2 • VREF
±VREF
±VREF
1
2
5V
±2.5V
±1.25V
±0.625V
2.5V
±1.25V
PGA
PGA
2 • PGA
4
1.25V
±0.625V
±312.5mV
±156.25mV
±78.125mV
±39.0625mV
±19.531mV
±9.766mV
RANGE = 0
8
0.625V
±312.5mV
±156.25mV
±78.125mV
±39.0625mV
±19.531mV
16
32
64
128
312.5mV
156.25mV
78.125mV
39.0625mV
VREF
PGA
±V
±V
REF
REF
2 • PGA
4 • PGA
RANGE = 1
NOTES: (1) With a 2.5V reference. (2) Refer to electrical specification for analog input voltage range.
TABLE VI. Full-Scale Range versus PGA Setting.
ADS1240, 1241
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SBAS173C
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