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ADC10D1000QML-SP

SNAS466G –FEBRUARY 2009–REVISED DECEMBER 2016

ADC10D1000QML Low-Power, 10-Bit, Dual 1-GSPS or Single 2-GSPS

Analog-to-Digital Converter

1 Features

3 Description

The ADC10D1000 is a 10-bit, low-power, high-

performance CMOS analog-to-digital converter (ADC)

with sampling rates of up to 1 GSPS in dual-channel

mode or 2 GSPS in single-channel mode. The

ADC10D1000 achieves excellent accuracy and

dynamic performance while consuming a typical

2.9 W of power.

1

•

Space Qualified

–

Total Ionizing Dose 100 krad(Si)

Single-Event Latch-Up 120 MeV-cm²/mg

Single-Event Functional-Interrupt Immune 120

MeV-cm²/mg (see Radiation Reports)

•

Configurable to Either 1-GSPS Dual ADC or 2-

GSPS Interleaved

The ADC10D1000 provides a flexible LVDS interface,

which has multiple SPI-programmable options to

facilitate board design and FPGA/ASIC data capture.

The LVDS outputs are compatible with IEEE 1596.3-

1996 and support programmable common-mode

voltage.

•

Low Power Consumption

R/W SPI Interface for Extended Control Mode±

Internally Terminated, Buffered, Differential

Analog Inputs

•

Test Patterns at Output for System Debug

The product is packaged in a hermatic 376-pin

column grid array (CCGA) that is thermally enhanced

and rated over the temperature range of –55°C to

+125°C.

Programmable 15-Bit Gain and 12-Bit Plus Sign

Offset Adjustments

•

Option of 1:2 Demuxed or 1:1 Non-Demuxed

LVDS Outputs

Device Information⁽¹⁾

•

Auto-Sync Feature for Multi-Chip Systems

Single 1.9-V Power Supply

PART NUMBER

GRADE

PACKAGE

ADC10D1000CCMLS

Flight part 100 krad

CCGA (376)

Pre-flight engineering

prototype

Thermally Enhanced Column-Grid-Array Package

ADC10D1000CCMPR

ADC10D1000CVAL

ADC10D1000DAISY

CCGA (376)

Ceramic evaluation

board

2 Applications

Daisy chain, mechanical

sample, no die

•

Wideband Communications

Direct RF Down Conversion

Star Tracker

CCGA (376)

(1) For all available packages, see the package orderable

addendum (POA) at the end of the data sheet.

Functional Block Diagram

10

VinI+

Rterm

VinI-

DI(9:0)

10

1:2

10-Bit

ADC

T/H

Demux

DId(9:0)

DCLKI

ORI

M

U

X

RCOut1

RCOut2

Clock

Management

and AutoSync

Output

Buffers

ORQ

DCLKQ

10

VinQ+

Rterm

DQ(9:0)

10

1:2

10-Bit

ADC

T/H

Demux

DQd(9:0)

VinQ-

CLK+

Rterm

Control/Status

and Other Logic

CLK-

RCLK+

Rterm

SPI

Control Pins

RCLK-

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADC10D1000QML-SP

SNAS466G –FEBRUARY 2009–REVISED DECEMBER 2016

www.ti.com

Table of Contents

6.18 Typical Characteristics.......................................... 35

Detailed Description ............................................ 41

7.1 Overview ................................................................. 41

7.2 Functional Block Diagram ....................................... 42

7.3 Feature Description................................................. 42

7.4 Device Functional Modes........................................ 50

7.5 Programming........................................................... 52

7.6 Register Maps......................................................... 55

Application and Implementation ........................ 62

8.1 Application Information............................................ 62

Power Supply Recommendations...................... 69

9.1 Power Planes.......................................................... 69

1

2

3

4

5

6

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 4

Specifications....................................................... 14

6.1 Absolute Maximum Ratings .................................... 14

6.2 ESD Ratings .......................................................... 14

6.3 Recommended Operating Conditions..................... 15

6.4 Thermal Information................................................ 15

7

8

9

6.5 Converter Electrical Characteristics: Static Converter

Characteristics ......................................................... 16

6.6 Converter Electrical Characteristics: Dynamic

Converter Characteristics......................................... 17

10 Layout................................................................... 71

10.1 Layout Guidelines ................................................. 71

10.2 Layout Example .................................................... 71

10.3 Thermal Management........................................... 72

10.4 Temperature Sensor Diode................................... 72

10.5 Radiation Environments........................................ 73

11 Device and Documentation Support ................. 74

11.1 Device Support .................................................... 74

11.2 Related Links ........................................................ 76

11.3 Receiving Notification of Documentation Updates 76

11.4 Community Resources.......................................... 76

11.5 Trademarks........................................................... 76

11.6 Electrostatic Discharge Caution............................ 76

11.7 Glossary................................................................ 76

6.7 Converter Electrical Characteristics: Analog

Input/Output and Reference Characteristics............ 21

6.8 Converter Electrical Characteristics: Channel-to-

Channel Characteristics........................................... 22

6.9 Converter Electrical Characteristics: LVDS CLK Input

Characteristics ......................................................... 23

6.10 Electrical Characteristics: AutoSync Feature........ 24

6.11 Converter Electrical Characteristics: Digital Control

and Output Pin Characteristics ................................ 25

6.12 Converter Electrical Characteristics: Power Supply

Characteristics (1:2 Demux Mode) .......................... 27

6.13 Converter Electrical Characteristics: AC Electrical

Characteristics ......................................................... 28

6.14 Timing Requirements: Serial Port Interface.......... 30

6.15 Timing Requirements: Calibration......................... 31

6.16 Quality Conformance Inspection....................... 31

6.17 Timing Diagrams................................................... 32

12 Mechanical, Packaging, and Orderable

Information ........................................................... 77

12.1 Engineering Samples............................................ 77

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

SECTION

CHANGES

RELEASED

02/11/09

A

B

Initial Release

New Product Data Sheet Release

(ECN SENT FOR APPROVAL 02/05/09 - Edit #: 16)

03/18/09

4/20/09

Connection Diagram, Table 3. Section 8.0 -

DCLK_RST± diagram, Section 18.0,

paragraph 18.4.2.

Following Pin names corrected V_A, GND and GND_DR

Section 8.0 - Update DCLK_RST± diagram, Section

18.0 - paragraph added to 18.4.2 and new figure.

Revision A will be Archived.

.

C

D

Features, Key Specifications, Table 10

Electricals.

Moved reference to radiation to Features from Key

Specifications. Table 10 Electricals: V_OHtypo limit

move to Min., Added parameters V_{CMI_DRST}, V_{ID_DRST}

R_{IN_DRST}. Revision B will be Archived.

+

,

05/28/09

Absolute Maximum Ratings and Operating

Absolute Maximum Ratings added Voltage on V_IN,

Ratings, Electrical Section Table 12, Section V_IN^-. Operating Ratings changed V_IN⁺, V_IN^-Voltage

19 Reserved Addr: Fh

Range. Range. Remove Note 10 reference from

Table 12 t_OSK, Correction to Reserved Addr: Fh.

Revision C will be Archived.

09/11/09

E

Electrical Section Table 12 Calibration (Tcal), Added Conditions to Tcal parameter, 17.0 Section

17.0 Section, 19.0 Section (top register 4h)

Addr: 4h (0100b) POR state: DA7Fh

New paragraph 17.4.3.4 and renumbered, Changed

table 4h and title from Reserved to Calibration Adjust

in 19.0 Section. Revision D will be Archived.

2

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SNAS466G –FEBRUARY 2009–REVISED DECEMBER 2016

Revision History (continued)

DATE

REVISION

SECTION

CHANGES

RELEASED

05/10/2010

F

Ordering Information Table, Table 6, Table 10 Added reference to MPR and CVAL NSPN. Table 6

Electrical Section. Sections 15.0, 17.0,

17.4.3, 19.0 Configuration Register 1 Bit 6

section 1:2 Demux Non-DES Mode, Extended Control

Mode, FM (14:0) = 7FFFh SNR Limit and 1:2 Demux

Non-DES Mode, Non-Extended Control Mode, FSR =

VA. Table 10 Digital Control Pins. Update Figure 11,

Added New Figure 12 and 13, Renumbered previous

Figure 12 and 13 to Figure 14 and 15 etc. Changed

paragraph 17.4.3. Configuration Register 1– Bit 6

paragraph. Revision E will be Archived.

12/07/2016

G

Added Device Information table, ESD Ratings table, Detailed Description section, Device Functional

Modes section, Application and Implementation section, Power Supply Recommendations section,

Layout section, Device and Documentation Support section, and Mechanical, Packaging, and

Orderable Information section; updated values in the Thermal Information table to align with JEDEC

standards; add pin VCMOS and information regarding usage throughout data sheet; update several

pin names; removed maximum supply current values in Converter Electrical Characteristics: Power

Supply Characteristics (1:2 Demux Mode), leaving only power consumption specifications; conform

other content to match format of similar data sheets in same device family; change "Panasonic part

number ECJ-0EB1A104K" to "Presidio part number SR0402X7R104KENG5" in Power Supply; update

Abs Max and ROC tables

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5 Pin Configuration and Functions

NAA Package

376-Pin CPGA Package

Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

GND_DR

GND

Vbg

V_A

GND

SDO

ECE

TPM

NDM

V_A

GND

V_A

V_E GND_E

V_DR DId1+

DId4+ V_DR DId7+

DId9+ DId9-

A

B

C

D

E

F

A

GND_E

GND_DR GND_DR GND_DR

DId0+ DId1- DId3+ DId4- DId6+ DId7- DId8+

SDI CalRun V_A

V_E

B

C

D

E

F

Rtrim+ Vcmo Rext+

SCS

GND

SCLK GND

V_E GND_E

DId0- DId2+ DId3- DId5+ DId6-

DId8-

V_DR

DI1+

DI1-

DI0+

DI2+

DI3+

DI4-

DI6+

DI8+

DI9-

DI0-

DI2-

GND_DR

V_DR

V_A

VbiasI

GND_DR

Rtrim- Rext-

GND

CAL

V_A

V_DR DId2-

DId5- V_DR

GND_DR

DI5+

V_A Tdiode+

GND

DI3-

RSV1

11

1

2

3

4

5

6

7

8

9

10

RSV2

GND

GND_TC

V_TC

GND_DR

DI6-

V_A

V_TC

VinI+

VinI-

Tdiode-

DI4+

DI5-

AA

GND

AB

V_TC V_TC

G

H

J

G

H

J

AC

AD

GND_TC

V_A

DI7+

DI7-

DI8-

GND_TC

V_TC VbiasI

V_DR

DI9+

V_DR

AE

AF

AG

GND_TC

GND VbiasI V_TC

GND VbiasQ V_TC

ORI+

ORI- DCLKI+ DCLKI-

K

L

K

L

DCLKQ+ DCLKQ-

ORQ+ ORQ-

GND_TC

GND_DR

DQ7+

GND_DR

DQ8-

DQ6-

V_DR

DQ3-

DQ2-

DQ0-

VinQ-

V_TC VbiasQ

DQ9+ DQ9-

M

N

P

R

T

M

N

P

R

T

AH

AJ

GND_TC

VinQ+ V_TC

V_A

DQ7-

DQ5-

DQ8+

DQ6+

GND_TC

V_TC

V_A

V_TC V_TC

DQ5+

AK

AL

V_DR DQ4+ DQ4-

GND_TC GND_TC

V_A

GND

V_DR

DQ1-

DQ3+

VbiasQ

GND_TC

CLK-

RCOut1-

GND_DR

CLK+

PDI

GND

V_A

V_DR DQd2-

DQd5- V_DR V_DR

DQ1+ DQ2+

U

V

W

Y

GND_DR

U

V

W

Y

DCLK

_RST+

RCOut2+ RCOut2-

GND_DR GND_DR

PDQ

GND

V_E GND_E GND_DR DQd0- DQd2+ DQd3- DQd5+ DQd6- DQd8-

DQ0+

DCLK

_RST-

GND_DR

DQd0+ DQd1- DQd3+ DQd4- DQd6+ DQd7- DQd8+ GND_DR GND_DR GND_DR

GND

V_A

2

RSV DDRPh RCLK-

V_A

6

GND GND_E V_E

RCOut1+

GND_DR

GND_DR GND_DR

DQd9+ DQd9-

GND

1

FSR RCLK+

GND

7

V_E GND_E GND_DR V_DR DQd1+

DQd4+ V_DR DQd7+

3

4

5

8

9

10

11

12

13

14

15

16

17

18

19

20

4

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SNAS466G –FEBRUARY 2009–REVISED DECEMBER 2016

Pin Functions

TYPE

DESCRIPTION

NO.

NAME

ANALOG FRONT-END AND CLOCK PINS

V

A

Bandgap voltage output or LVDS common-mode voltage select. This

pin provides the bandgap output voltage and is capable of sourcing/

sinking 100 µA and driving a load of up to 80 pF. Alternately, this pin

may be used to select the LVDS digital output common-mode voltage.

If tied to logic-high, the higher LVDS common-mode voltage is selected.

The lower value is the default.

B1

V_BG

GND

V

A

External reference and input termination trim resistor terminals. A 3.3-

kΩ ±0.1% resistor must be connected between Rtrim+, Rtrim–. The

Rtrim resistor is used to establish the calibrated 100-Ω input impedance

of VinI+, Vinl–, VinQ+, VinQ– and CLK+, CLK-. These impedances may

be fine-tuned by varying the value of the resistor by a corresponding

percentage; however, the tuning range and performance is not ensured

for such an alternate value.

Rtrim+

Rtrim–

C1/D2

V

GND

V

A

Connect a 3.3-kΩ ±0.1% resistor connected between Rext+, Rext–. The

Rext resistor is used for setting internal temperature-independent bias

currents; the value and precision of this resistor must not be

compromised.

Rext+

Rext–

C3/D3

V

GND

V

A

Tdiode_P

GND

A

Tdiode+

Tdiode–

Temperature sensor diode positive (anode) and negative (cathode)

terminals. This set of pins is used for die temperature measurements.

E2/F3

V

Tdiode_N

GND

V

A

Common-mode voltage output or signal coupling select. If AC-coupled

operation at the analog inputs is desired, this pin must be held at logic-

low level. This pin is capable of sourcing and sinking up to 100 μA. For

DC-coupled operation, V_CMO, leave this pin floating or terminated into

high-impedance. In DC-coupled mode, this pin provides an output

voltage which is the optimal common-mode voltage for the input signal

and should be used to set the common-mode voltage of the driving

buffer.

V

CMO

200k

C2

V_CMO

Enable AC

Coupling

8 pF

GND

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Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

Differential signal I-channel and Q-channel inputs. In the non-dual edge

sampling (non-DES) mode, each I-input and Q-input is sampled and

converted by its respective channel with each positive transition of the

CLK input. In non-extended control mode (non-ECM) and DES mode,

both channels sample the I input. In extended control mode (ECM), the

Q-channel input may optionally be selected for conversion in DES

mode by the DEQ bit (Addr: 0h, Bit 6).

V

A

50k

Each I-channel input and Q-channel input has an internal common

mode bias that is disabled when DC-coupled mode is selected. Both

inputs must be either AC- or DC-coupled. The coupling mode is

selected by the V_CMOpin.

AGND

100

V

CMO

H1/J1

N1/M1

VinI+, Vinl–

VinQ+, VinQ–

Control from V

CMO

V

A

In non-ECM, the full-scale range of these inputs is determined by the

FSR pin; both I channel and Q-channels have the same full-scale input

range. In ECM, the full-scale input range of the I- and Q-channel inputs

may be independently set through the Control Register (Addr: 3h and

Addr: Bh). The high and low full-scale input range setting in non-ECM

corresponds to the mid and minimum full-scale input range in ECM.

50k

AGND

The input offset may also be adjusted in ECM.

V

A

Differential converter sampling clock. In the non-DES mode, the analog

inputs are sampled on the positive transitions of this clock signal. In the

DES mode, the Q channel is sampled on both transitions of this clock.

This clock must be AC-coupled. Additional features include an LC filter

on the clock input.

CLK+

CLK–

50k

AGND

U2/V1

100

V

BIAS

V

A

AGND

V

A

Differential DCLK reset. A positive pulse on this input is used to reset

the DCLKI+, DCLKI– and DCLKQ+, DCLKQ– outputs of two or more

ADC10D1000 devices in order to synchronize them with other

ADC10D1000 devices in the system. DCLKI+, DCLKI– and DCLKQ+,

DCLKQ– are always in phase with each other, unless one channel is

powered down, and do not require a pulse from DCLK_RST+,

DCLK_RST– to become synchronized. The pulse applied here must

meet timing relationships with respect to the CLK+, CLK– inputs. This

feature may still be used while the chip is in the AutoSync mode.

AGND

DCLK_RST+

DCLK_RST–

V2/W1

100

V

A

AGND

6

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SNAS466G –FEBRUARY 2009–REVISED DECEMBER 2016

Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

V

A

Reference clock input. When the AutoSync feature is active and the

ADC10D1000 is in slave mode, the internal divided clocks are

synchronized with respect to this input clock. The delay on this clock

may be adjusted when synchronizing multiple ADCs. This feature is

available in ECM via the Control Register (Addr: Eh).

RCLK+

RCLK–

50k

AGND

Y4/W5

100

V

BIAS

V

A

50k

AGND

V

DR

Reference clock output 1 and 2. These signals provide a reference

clock at a rate of CLK/4, when enabled, independently of whether the

ADC is in master or slave mode. They are used to drive the RCLK of

another ADC10D1000, in order to enable automatic synchronization for

multiple ADCs (AutoSync feature). The impedance of each trace from

RCOut1+, RCOut1– and RCOut2+, RCOut2– to the RCLK+, RCLK– of

another ADC10D1000 must be 100-Ω differential. Having two clock

outputs allows the auto-synchronization to propagate as a binary tree.

Use the DOC Bit (Addr: Eh, Bit 1) to enable/ disable this feature; the

default is disabled.

200W

RCOut1+,

RCOut1–

RCOut2+,

RCOut2–

Y5/U6

V6/V7

-

+

DR GND

CONTROL AND STATUS PINS

V

A

Serial data out. In ECM, serial data is shifted out of the device on this

pin while SCS signal is asserted (logic-low). This output is in tri-state

mode when SCS is de-asserted.

A3

SDO

GND

V

A

Test pattern mode. With this input at logic-high, the device continuously

outputs a fixed, repetitive test pattern at the digital outputs. In the ECM,

this input is ignored and the test pattern mode can only be activated

through the TPM bit of the Control Register (Addr: 0h, Bit 12).

A4

TPM

GND

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Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

V

A

Non-demuxed mode. Setting this input to logic-high causes the digital

output bus to be in the 1:1 Non-demuxed mode. Setting this input to

logic-low causes the digital output bus to be in the 1:2 demuxed mode.

This feature is pin-controlled only and remains active during ECM and

non-ECM.

A5

NDM

GND

A

50 kW

Extended control enable. Extended feature control through the SPI

interface is enabled when this signal is asserted logic-low. In this case,

most of the direct control pins have no effect. When this signal is de-

asserted, that is, logic-high, the SPI interface is disabled and the direct

control pins are enabled.

B3

ECE

GND

A

100 kW

Serial data-in. In ECM, serial data is shifted into the device on this pin

while the SCS signal is asserted (logic-low).

B4

B5

C4

SDI

CalRun

SCS

GND

V

A

Calibration running Indication. This output is logic-high while the

calibration sequence is executing, and logic-low while the calibration

sequence is not running.

GND

V

A

100 kW

Serial chip select. In ECM, when this signal is asserted logic-low, SCLK

is used to clock in serial data that is present on the SDI input and to

source serial data on the SDO output. When this signal is de-asserted,

that is, logic-high, the SDI input is ignored and the SDO output is in tri-

state mode.

GND

8

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Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

V

A

100 kW

Serial clock. In ECM, serial data is shifted into and out of the device

synchronously to this clock signal. This clock may be disabled and held

logic-low, so long as timing specifications are not violated when the

clock is enabled or disabled.

C5

SCLK

GND

V

A

Calibration cycle initiate. The user can command the device to execute

a self-calibration cycle by holding this input high a minimum of t_{CAL_H}

after having held it low a minimum of t_{CAL_L}. This pin is active in both

ECM and non-ECM. In ECM, this pin is logically OR'd with the CAL Bit

(Addr: 0h, Bit 15) in the Control Register. Therefore, both pin and bit

must be set low and then either can be set high to execute an on-

command calibration.

D6

CAL

GND

V

A

Power-down I channel and Q-channel. Setting either input to logic-high

powers down the respective I-channel or Q-channel converter. Setting

either input to logic-low brings the respective I channel or Q-channel

converter to a fully operational state after a finite time delay. This pin is

active in both ECM and non-ECM. In the ECM, either this pin or the PDI

and PDQ bit in the Control Register can be used to power-down the I

channel and Q channel (Addr: 0h, Bit 11 and Bit 10), respectively.

50 kW

U3

V3

PDI

PDQ

GND

Reserved: This pin is used for internal purposes and must be

connected to GND through a 100-KΩ resistor.

W3

W4

RSV

NONE

V

A

DDR phase select. This input, when logic-low, selects the 0-degree

data-to-DCLK phase relationship; when logic-high, the input selects the

90-degree data-to-DCLK phase relationship. This pin only has an effect

when the chip is in 1:2 demuxed mode; for example, when the NDM pin

is set to logic-low. In ECM, this input is ignored and the DDR phase is

selected through the DPS bit of the Control Register (Addr: 0h, bit 14);

the default is 0-degree data-to-DCLK phase relationship.

DDRPh

GND

V

A

Full-scale input range select. In non-ECM, when this input is set to

logic-low or logic-high, the full-scale differential input range for both I-

channel and Q-channel inputs is set to the lower or higher value,

respectively. In ECM, this input is ignored and the full-scale range of

the I-channel and Q-channel inputs is independently determined by the

setting of Addr: 3h and Addr: Bh, respectively. Note that the higher and

lower FSR value in non-ECM does not precisely correspond to the

maximum and minimum available selection in ECM; in ECM, the

selection range is greater.

Y3

FSR

GND

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Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

POWER AND GROUND PINS

A1, A7, B2,

B7, C6, D4,

D5, E4, K1,

L1, T4, U4,

U5, V4, V5,

W2, W7, Y1,

Y7,

GND

NONE

Analog ground return

AA2thru

AL11

A2, A6, B6,

C7, D1, D8,

D9, E1, F1,

H4, N4, R1,

T1, U8, U9,

W6, Y2, Y6

Analog power supply. This supply is tied to the ESD ring. Therefore, it

must be powered up before or with any other supply.

V_A

NONE

A8, B9, C8,

V8, W9, Y8

V_E

NONE

Power supply for the digital encoder

Ground return for the digital encoder

A9, B8, C9,

V9, W8, Y9

GND_E

A10, A13,

A17, A20,

B10 B18,

B19, B20,

C10, C17,

D10, D13,

D16, E17,

F17, F20,

M17, M20,

U10,U13,

U17, V10,

V17, V18,

W10, W18,

W19, W20,

Y10, Y13,

Y17, Y20

GND_DR

NONE

Ground return for the output driver

A11, A15,

C18, D11,

D15, D17,

J17, J20,

R17, R20,

T17, U11,

U15, U16,

Y11, Y15

V_DR

NONE

Power supply for the output drivers

Bias voltage I channel. This is an externally decoupled bias voltage for

the I channel. Each pin must individually be decoupled with a 100-nF

capacitor via a low resistance, low inductance path to GND.

D7, J4, K2

E3

VbiasI

RSV1

NONE

Reserved: This pin is used for internal purposes. This pin must

individually be decoupled with a 100-nF capacitor via a low resistance,

low inductance path to GND.

F2, G2, H3,

J2, K4, L4,

M2, N3, P2,

R2, T2, T3,

U1

GND_TC

NONE

Analog ground return for the track-and-hold and clock circuitry

Bias voltage Q channel. This is an externally decoupled bias voltage for

the Q channel. Each pin must individually be decoupled with a 100-nF

capacitor via a low resistance, low inductance path to GND.

L2, M4, U7

F4

VbiasQ

RSV2

NONE

Reserved: This pin is used for internal purposes. This pin must

individually be decoupled with a 100-nF capacitor via a low resistance,

low inductance path to GND.

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Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

G1, G3, G4,

H2, J3, K3,

L3, M3, N2,

P1, P3, P4,

R3, R4

V_TC

NONE

Analog power supply for the track-and-hold and clock circuitry

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Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

HIGH-SPEED DIGITAL OUTPUTS

A18/A19

B17/C16

A16/B16

B15/C15

C14/D14

A14/B14

B13/C13

C12/D12

A12/B12

B11/C11

·

Y18/Y19

W17/V16

Y16/W16

W15/V15

V14/U14

Y14/W14

W13/V13

V12/U12

Y12/W12

W11/V11

DId9+, Dld9–

DId8+, Dld8–

DId7+, Dld7–

DId6+, Dld6–

DId5+, Dld5–

DId4+, Dld4–

DId3+, Dld3–

DId2+, Dld2–

DId1+, Dld1–

DId0+, Dld0–

·

DQd9+, DQld9–

DQd8+, DQd8–

DQd7+, DQd7–

DQd6+, DQd6–

DQd5+, DQd5–

DQd4+, DQd4–

DQd3+, DQd3–

DQd2+, DQd2–

DQd1+, DQd1–

DQd0+, DQd0–

V_DR

Delayed I-channel and Q-channel digital data outputs. In non-demux

mode, these outputs are tri-stated. In Demux Mode, these outputs

provide ½ the data at ½ the sampling clock rate, synchronized with the

non-delayed data, that is, the other ½ of the data which was sampled

one clock cycle later. Compared with the DI and DQ outputs, these

outputs represent the earlier time samples. Each of these outputs must

always be terminated with a 100-Ω differential resistor placed as closely

as possible to the differential receiver.

-

+

-

+

DR GND

J18/J19

H19/H20

H17/H18

G19/G20

G17/G18

F18/F19

E19/E20

D19/D20

D18/E18

C19/C20

·

M18/M19

N19/N20

N17/N18

P19/P20

P17/P18

R18/R19

T19/T20

U19/U20

U18/T18

V19/V20

DI9+, DI9–

DI8+, DI8–

DI7+, DI7–

DI6+, DI6–

DI5+, DI5–

DI4+, DI4–

DI3+, DI3–

DI2+, DI2–

DI1+, DI1–

DI0+, DI0–

·

DI9+, DI9–

DQ8+, DQ8–

DQ7+, DQ7–

DQ6+, DQ6–

DQ5+, DQ5–

DQ4+, DQ4–

DQ3+, DQ3–

DQ2+, DQ2–

DQ1+, DQ1–

DQ0+, DQ0–

V_DR

I-channel and Q-channel digital data outputs. In non-demux mode, this

LVDS data is transmitted at the sampling clock rate. In demux mode,

these outputs provide ½ the data at ½ the sampling clock rate,

synchronized with the delayed data, that is, the other ½ of the data,

which was sampled one clock cycle earlier. Compared with the DId and

DQd outputs, these outputs represent the later time samples. Always

terminate each of these outputs with a 100-Ω differential resistor placed

as closely as possible to the differential receiver

-

+

-

+

DR GND

V_DR

Out-of-range output for the I channel and Q channel. This differential

output is asserted logic-high while the over- or under-range condition

exists, that is, the differential signal at each respective analog input

exceeds the full-scale value. Each OR results refers to the current data,

with which it is clocked out. Always terminate each of these outputs

with a 100-Ω differential resistor placed as closely as possible to the

differential receiver.

-

+

-

K17/K18

L17/L18

ORI+, ORI–

ORQ+, ORQ–

+

DR GND

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Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

V_DR

Data clock output for the I-channel and Q-channel data bus. These

differential clock outputs are used to latch the output data and must

always be terminated with a 100-Ω differential resistor. Delayed and

non-delayed data outputs are supplied synchronously to this signal. In

1:2 demux mode or non-demux mode, this signal is at ¼ or ½ the input

clock rate, respectively. DCLKI+, DLKI– and DCLKQ+, DLKQ– are

always in phase with each other, unless one channel is powered down,

and they do not require a pulse from DCLK_RST+, DCLK_RST– to

become synchronized.

-

+

-

DCLKI+, DLKI–

DCLKQ+,

K19/K20

L19/L20

DLKQ–

+

DR GND

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

MAX

2.2

UNIT

V

Supply voltage (V_A, V_TC, V_DR, V_E)

Supply difference – max(V_A/TC/DR/E) – min(V_A/TC/DR/E

)

0

100

mV

V

Voltage on any input pin (except VinI+, VinI–, VinQ+, VinQ–)

VinI+, VinI–, VinQ+, VinQ– voltage⁽³⁾

–0.15

–0.5

(V_A+ 0.15)

2.5

V

Input current at VinI+, VinI–, VinQ+, VinQ–⁽⁴⁾

50

mA

mV

mA

W

Ground difference – max(GND_TC/DR/E) – min(GND_TC/DR/E

Input current at any pin⁽⁴⁾

Package power dissipation at T_A≤ 85°C⁽⁴⁾

Storage temperature, T_stg

)

0

100

±50

3.45

150

–65

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are measured with respect to GND = GND_DR= GND_E= GND_TC= 0 V, unless otherwise specified.

(3) Verified during product qualification high-temperature lifetime testing (HTOL) at T_J= 150°C for 1000 hours continuous operation with

V_A= V_D= 2.2 V.

(4) When the input voltage at any pin exceeds the power supply limits, that is, less than GND or greater than V_A, the current at that pin

must be limited to 50 mA. In addition, overvoltage at a pin must adhere to the maximum voltage limits. Simultaneous overvoltage at

multiple pins requires adherence to the maximum package power dissipation limits. These dissipation limits are calculated using JEDEC

JESD51-7 thermal model. Higher dissipation may be possible based on specific customer thermal situation and specified package

thermal resistances from junction to case.

6.2 ESD Ratings

VALUE

±8000

±750

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Machine model

V_(ESD)

Electrostatic discharge

V

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–55

1.8

NOM

MAX

125

2

UNIT

°C

V

Ambient temperature, T_A

Supply voltage (V_A, V_TC, V_E)

Driver supply voltage (V_DR

)

1.8

V_A

V

VinI+, VinI–, VinQ+, VinQ–

voltage⁽²⁾

DC-coupled

–0.4

2.4

V

DC-coupled at 100% duty cycle

DC-coupled at 20% duty cycle

DC-coupled at 10% duty cycle

1

2

VinI+, VinI–, VinQ+, VinQ–

differential voltage⁽³⁾

2.8

VinI+, VinI–, VinQ+, VinQ–

current⁽²⁾

AC-coupled

–50

50

15.3

17.1

mA

Maintaining common-mode voltage

AC-coupled

VinI+, VinI–, VinQ+, VinQ– power

dBm

Not maintaining common-mode voltage,

AC-coupled

Ground difference – max(GND_TC/DR/E) – min(GND_TC/DR/E

)

0

V

CLK+, CLK– voltage

0

0.4

V_A

2

Differential CLK amplitude

V_P-P

mV

V_CMIcommon-mode input voltage

V_CMO– 150

V_CMO+ 150

(1) All voltages are measured with respect to GND = GND_DR= GND_E= GND_TC= 0 V, unless otherwise specified.

(2) Proper common-mode voltage must be maintained to ensure proper output codes, especially during input overdrive.

(3) This rating is intended for DC-coupled applications; the voltages and duty cycles listed may be safely applied to V_IN± for the lifetime of

the part.

6.4 Thermal Information

ADC10D1000QML-SP

THERMAL METRIC⁽¹⁾⁽²⁾

NAA (CCGA)

UNIT

376 PINS

13.1

5.0

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

5.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

2.6

ψ_JB

4.7

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) Solder process specifications in Board Mounting Recommendation.

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6.5 Converter Electrical Characteristics: Static Converter Characteristics

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q-channel; duty-cycle stabilizer on.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

SUB-GROUPS

MIN

TYP⁽⁴⁾

MAX UNIT

DC-coupled, 1-MHz sine wave

over-ranged

INL

Integral non-linearity

[1, 2, 3]

±0.7

±1.4

±0.5

10

LSB

bits

DC-coupled, 1-MHz sine wave

over-ranged

DNL

Differential non-linearity

[1, 2, 3]

±0.2

Resolution with no missing

codes

V_OFF

Offset error

–2.8

±45

LSB

mV

V_{OFF_ADJ}

PFSE

NFSE

Input offset adjustment range

Positive full-scale error

Negative full-scale error

See⁽⁵⁾

[1, 2, 3]

±28

1023

0

(V_IN+) − (V_IN−) > + full scale

(V_IN+) − (V_IN−) > – full scale

Out-of-range output code

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings

may damage this device.

V

A

TO INTERNAL

CIRCUITRY

I / O

GND

(2) To ensure accuracy, it is required that V_A, V_TC, V_Eand V_DRbe well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average

outgoing quality level (AOQL).

(5) Calculation of full-scale error for this device assumes that the actual reference voltage is exactly its nominal value. Full-scale error for

this device, therefore, is a combination of full-scale error and reference voltage error. For relationship between gain error and full-scale

error, see gain error in Specification Definitions.

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6.6 Converter Electrical Characteristics: Dynamic Converter Characteristics

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q-channel; duty-cycle stabilizer on.^(1)(2)(3)

PARAMETER

Full-power bandwidth

Code error rate

Gain flatness

TEST CONDITIONS

Non-DES mode

DES mode

SUB-GROUPS

MIN

TYP⁽⁴⁾

2.8

MAX

UNIT

GHz

FPBW

CER

1.3

10^–18

±0.25

±0.5

Error/Sample

dBFS

DC to 498 MHz

DC to 1 GHz

f_c= 325 MHz,

notch width = 25 MHz

NPR

Noise power ratio

47.5

dB

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings

may damage this device.

V

A

TO INTERNAL

CIRCUITRY

I / O

GND

(2) To ensure accuracy, it is required that V_A, V_TC, V_Eand V_DRbe well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average

outgoing quality level (AOQL).

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Converter Electrical Characteristics: Dynamic Converter Characteristics (continued)

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q-channel; duty-cycle stabilizer on.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

SUB-GROUPS

MIN

TYP⁽⁴⁾

MAX

UNIT

1:2 DEMUX NON-DES MODE, EXTENDED CONTROL MODE, FM (14:0) = 7FFFh

f_IN= 248 MHz, V_IN= –0.5

dBFS

[4, 5]

8.4

7.8

9

f_IN= 248 MHz, V_IN= –0.5

dBFS

[6]

ENOB

SINAD

SNR

Effective number of bits

bits

f_IN= 498 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

8.2

8.9

f_IN= 498 MHz, V_IN= –0.5

dBFS,

7.8

8.9

f_IN= 248 MHz, V_IN= –0.5

dBFS,

[4, 5]

[6]

52.2

48.5

51

55.8

56.8

56.1

–68

–61

−75

−68

−72

−67

63

f_IN= 248 MHz, V_IN= –0.5

dBFS

Signal-to-noise plus

distortion ratio

dB

f_IN= 498 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

f_IN= 498 MHz, V_IN= –0.5

dBFS

48.8

53.2

49.4

52

f_IN= 248 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

f_IN= 248 MHz, V_IN= –0.5

dBFS

Signal-to-noise ratio

dBc

f_IN= 498 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

f_IN= 498 MHz, V_IN= –0.5

dBFS

49.4

f_IN= 248 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

–59

–56

–58

–57

f_IN= 248 MHz, V_IN= –0.5

dBFS

THD

Total harmonic distortion

dBc

f_IN= 498 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

f_IN= 498 MHz, V_IN= –0.5

dBFS

f_IN= 248 MHz, V_IN= –0.5

dBFS

2nd

Harm

Second harmonic distortion

Third harmonic distortion

dBc

f_IN= 498 MHz, V_IN= –0.5

dBFS

f_IN= 248 MHz, V_IN= –0.5

dBFS

3rd

Harm

f_IN= 498 MHz, V_IN= –0.5

dBFS

f_IN= 248 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

59

53

f_IN= 248 MHz, V_IN= –0.5

dBFS

63

Spurious-free dynamic

range

SFDR

dBc

f_IN= 498 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

57.5

54.5

63

f_IN= 498 MHz, V_IN= –0.5

dBFS

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Converter Electrical Characteristics: Dynamic Converter Characteristics (continued)

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q-channel; duty-cycle stabilizer on.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

SUB-GROUPS

MIN

TYP⁽⁴⁾

MAX

UNIT

NON-DEMUX NON-DES MODE, NON-EXTENDED CONTROL MODE, FSR = V_A

f_IN= 248 MHz, V_IN= –0.5

dBFS

[4, 5]

8.1

7.8

8.9

f_IN= 248 MHz, V_IN= –0.5

dBFS

[6]

ENOB

SINAD

SNR

Effective number of bits

bits

f_IN= 498 MHz, V_IN= –0.5

dBFS,

[4, 5]

[6]

8

8.9

f_IN= 498 MHz, V_IN= –0.5

dBFS

7.7

8.9

f_IN= 248 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

50.3

48.5

49.8

48

55.3

55.6

55.9

–67

f_IN= 248 MHz, V_IN= –0.5

dBFS

Signal-to-noise plus

distortion ratio

dB

f_IN= 498 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

f_IN= 498 MHz, V_IN= –0.5

dBFS

f_IN= 248 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

50.9

49

f_IN= 248 MHz, V_IN= –0.5

dBFS

Signal-to-noise ratio

dBc

f_IN= 498 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

50.5

48.5

f_IN= 498 MHz, V_IN= –0.5

dBFS

f_IN= 248 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

–59.5

–58.5

–58

f_IN= 248 MHz, V_IN=–0.5

dBFS

–67

THD

Total harmonic distortion

dBc

f_IN= 498 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

–64.3

−75

f_IN= 498 MHz, V_IN= –0.5

dBFS

f_IN= 248 MHz, V_IN= –0.5

dBFS

2nd

Harm

Second harmonic distortion

Third harmonic distortion

dBc

f_IN= 498 MHz, V_IN= -0.5

dBFS

−68

f_IN= 248 MHz, V_IN= –0.5

dBFS

−72

3rd

Harm

f_IN= 498 MHz, V_IN= –0.5

dBFS

−68

f_IN= 248 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

57.5

53

66.7

f_IN= 248 MHz, V_IN= –0.5

dBFS

Spurious-free dynamic

range

SFDR

dBc

f_IN= 498 MHz, V_IN= –0.5

dBFS

[4, 5]

[6]

57.5

54.5

f_IN= 498 MHz, V_IN= –0.5

dBFS

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Converter Electrical Characteristics: Dynamic Converter Characteristics (continued)

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q-channel; duty-cycle stabilizer on.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

SUB-GROUPS

MIN

TYP⁽⁴⁾

MAX

UNIT

NON-DEMUX NON-DES MODE, NON-EXTENDED CONTROL MODE, FSR = V_A

f_IN= 498 MHz, V_IN= –0.5

dBFS

ENOB

SINAD

SNR

Effective number of bits

9

bits

dB

Signal-to-noise plus

distortion ratio

f_IN= 498 MHz, V_IN= –0.5

dBFS

56.2

f_IN= 498 MHz, V_IN= –0.5

dBFS

Signal-to-noise ratio

56.7

-65.7

−75

dBc

f_IN= 498 MHz, V_IN= –0.5

dBFS

THD

Total harmonic distortion

Second harmonic distortion

Third harmonic distortion

2nd

Harm

f_IN= 498 MHz, V_IN= –0.5

dBFS

3rd

Harm

f_IN= 498 MHz, V_IN= –0.5

dBFS

−68

Spurious-free dynamic

range

f_IN= 498 MHz, V_IN= –0.5

dBFS

SFDR

67.6

1:4 DEMUX DES MODE (Q-CHANNEL ONLY), ECM, OFFSET/GAIN ADJUSTED ENOB EFFECTIVE NUMBER OF BITS

FIN = 498 MHZ, V_IN= –0.5 DBFS

f_IN= 498 MHz, V_IN= –0.5

dBFS

ENOB

SINAD

SNR

Effective number of bits

8.7

54.2

55.3

60.7

−78

−67

63.6

bits

dB

Signal-to-noise plus

distortion ratio

f_IN= 498 MHz, V_IN= –0.5

dBFS

f_IN= 498 MHz, V_IN= –0.5

dBFS

Signal-to-noise ratio

dBc

f_IN= 498 MHz, V_IN= –0.5

dBFS

THD

Total harmonic distortion

Second harmonic distortion

Third harmonic distortion

2nd

Harm

f_IN= 498 MHz, V_IN= –0.5

dBFS

3rd

Harm

f_IN= 498 MHz, V_IN= –0.5

dBFS

Spurious-free dynamic

range

f_IN= 498 MHz, V_IN= –0.5

dBFS

SFDR

20

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6.7 Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

FSR pin Y3 low

SUB-GROUPS

[4, 5, 6]

MIN

560

750

TYP⁽⁴⁾

630

MAX UNIT

680 mV_P-P

890 mV_P-P

FSR pin Y3 high

[4, 5, 6]

820

EXTENDED CONTROL MODE

FM(14:0) = 0000h

Analog differential input full-

scale range

V_{IN_FSR}

600

790

mV_P-P

FM(14:0) = 4000h (default)

FM(14:0) = 7FFFh

Differential

980

0.02

1.6

Analog input capacitance,

Non-DES mode⁽⁵⁾⁽⁶⁾

pF

Each input pin to ground

Differential

C_IN

R_IN

0.08

2.2

Analog input capacitance,

DES mode⁽⁵⁾⁽⁶⁾

Each input pin to ground

Differential input resistance

[1, 2, 3]

100

103.5

108

Ω

COMMON-MODE OUTPUT

Common-mode output

voltage

V_CMO

I_CMO= ±100 µA

1.15

1.25

38

1.35

V

Common-mode output

voltage temperature

coefficient

TC_V_CMO

ppm/°C

V_CMOinput threshold to set

DC-coupling mode

V_{CMO_LVL}

C_L_V_CMO

0.63

V

Maximum V_CMOload

capacitance

See⁽⁶⁾

80

pF

BANDGAP REFERENCE

Bandgap reference output

voltage

I_BG= ±100 µA

V_BG

[1, 2, 3]

1.15

1.25

50

1.35

V

ppm/°C

pF

Bandgap reference voltage

temperature coefficient

TC_V_BG

C_LOADV_BG

Maximum bandgap reference

load capacitance

80

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings

may damage this device.

V

A

TO INTERNAL

CIRCUITRY

I / O

GND

(2) To ensure accuracy, it is required that V_A, V_TC, V_Eand V_DRbe well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average

outgoing quality level (AOQL).

(5) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.22 pF differential and 1.06 pF

each pin to ground are isolated from the die capacitances by lead and bond wire inductances.

(6) This parameter is ensured by design and/or characterization and is not tested in production.

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6.8 Converter Electrical Characteristics: Channel-to-Channel Characteristics

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽⁴⁾

MAX

UNIT

LSB

Offset match

2

Positive full-scale match

Negative full-scale match

Phase matching (I, Q)

Zero offset selected in control register

f_IN= 1 GHz

LSB

2

LSB

< 1

Degree

Crosstalk from I channel

(aggressor) to Q-channel

(victim)

Aggressor = 498 MHz F.S.

Victim = 100 MHz F.S.

X-TALK

Q-channel

−61

dB

X-TALK

I channel

Crosstalk from Q-channel

(aggressor) to I channel (victim) Victim = 100 MHz F.S.

Aggressor = 498 MHz F.S.

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings

may damage this device.

V

A

TO INTERNAL

CIRCUITRY

I / O

GND

(2) To ensure accuracy, it is required that V_A, V_TC, V_Eand V_DRbe well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average

outgoing quality level (AOQL).

22

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6.9 Converter Electrical Characteristics: LVDS CLK Input Characteristics

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

Sine wave clock

SUB-GROUPS

[1, 2, 3]

MIN

0.4

TYP⁽⁴⁾

0.6

MAX UNIT

2

V_{IN_CLK}

Differential clock input level

V_P-P

Square wave clock

Differential

[1, 2, 3]

0.4

0.6

2

0.1

Sampling clock input

capacitance⁽⁵⁾⁽⁶⁾

C_{IN_CLK}

R_{IN_CLK}

pF

Each input to ground

1

Sampling clock input

resistance

100

Ω

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings

may damage this device.

V

A

TO INTERNAL

CIRCUITRY

I / O

GND

(2) To ensure accuracy, it is required that V_A, V_TC, V_Eand V_DRbe well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average

outgoing quality level (AOQL).

(5) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.22-pF differential and 1.06 pF

each pin to ground are isolated from the die capacitances by lead and bond wire inductances.

(6) This parameter is ensured by design and/or characterization and is not tested in production.

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6.10 Electrical Characteristics: AutoSync Feature

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.^(1)(2)(3)

SUB-

GROUPS

PARAMETER

TEST CONDITIONS

MIN

TYP⁽⁴⁾

MAX

UNIT

V_{IN_RCLK}

C_{IN_RCLK}

Differential RCLK input level Differential peak-to-peak

360

0.1

1

mV_P-P

Differential

RCLK input capacitance

pF

Each input to ground

RCLK differential input

resistance

R_{IN_RCLK}

100

Ω

I_{IH_RCLK}

I_{IL_RCLK}

Input leakage current

V_IN= V_A

[1, 2, 3]

–6

6

µA

V_IN= GND

Differential RCOut output

voltage

V_{O_RCOUT}

360

mV

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings

may damage this device.

V

A

TO INTERNAL

CIRCUITRY

I / O

GND

(2) To ensure accuracy, it is required that V_A, V_TC, V_Eand V_DRbe well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average

outgoing quality level (AOQL).

24

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SNAS466G –FEBRUARY 2009–REVISED DECEMBER 2016

6.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.^(1)(2)(3)

SUB-

GROUPS

PARAMETER

TEST CONDITIONS

MIN

TYP⁽⁴⁾

MAX

UNIT

DIGITAL CONTROL PINS (DES, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS— unless otherwise specified)

V_IH

V_IL

I_IH

Logic high input voltage

Logic low input voltage

Input leakage current

[1, 2, 3]

0.7 × V_A

V

0.3 × V_A

–0.1

V_IN= V_A

–6

µA

Input leakage current

(DES, CAL, TPM, FSR,

DDRPh)

[1, 2, 3]

–0.1

µA

I_IL

Input leakage current

(SCLK, SDI, SCS)

V_IN= GND

[1, 2, 3]

–33

–66

–18

–36

Input leakage current

(PDI, PDQ, ECE,)

Input capacitance⁽⁵⁾⁽⁶⁾

µA

pF

C_{IN_DIG}

Each input to ground

1.5

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings

may damage this device.

V

A

TO INTERNAL

CIRCUITRY

I / O

GND

(2) To ensure accuracy, it is required that V_A, V_TC, V_Eand V_DRbe well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average

outgoing quality level (AOQL).

(5) This parameter is ensured by design and/or characterization and is not tested in production.

(6) The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated

from the die capacitances by lead and bond wire inductances.

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Converter Electrical Characteristics: Digital Control and Output Pin Characteristics (continued)

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.^(1)(2)(3)

SUB-

GROUPS

PARAMETER

TEST CONDITIONS

MIN

TYP⁽⁴⁾

MAX

UNIT

LVDS OUTPUT PINS (DATA, DCLKI, DCLKQ, ORI, ORQ)

V_BG= Floating, OVS = High

300

160

340

190

520

374

568

400

700

540

760

600

V_BG= Floating, OVS = Low

V_BG= V_A, OVS = High

V_BG= V_A, OVS = Low

V_OD

LVDS differential output voltage

[1, 2, 3]

mV_P-P

mV

Change in LVDS output swing

between logic levels

ΔV_{O DIFF}

V_OS

±1

V_BG= Floating

V_BG= V_A

0.8

1.2

V

Output offset voltage

Change in output offset voltage

between logic levels

ΔV_OS

±1

mV

V_BG= Floating; D+ and D−

connected to 0.8 V

I_OS

Z_O

Output short-circuit current

Differential output impedance

±3.8

100

mA

Ω

DIFFERENTIAL DCLK RESET PINS (DCLK_RST)

DCLK_RST common mode

V_{CMI_DRST}

1.25 ±

0.15

V

V_P-P

Ω

input voltage

Differential DCLK_RST input

V_{ID_DRST}

voltage

0.6

Differential DCLK_RST input

R_{IN_DRST}

100

resistance⁽⁵⁾

DIGITAL OUTPUT PINS (CalRun, SDO)

CalRun, SDO I_OH= –400

µA

V_OH

V_OL

Logic high output level

Logic low output level

[1, 2, 3]

1.5

1.65

0.15

V

CalRun, SDO I_OH= 400 µA

0.3

26

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SNAS466G –FEBRUARY 2009–REVISED DECEMBER 2016

6.12 Converter Electrical Characteristics: Power Supply Characteristics (1:2 Demux Mode)

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

PDI = PDQ = Low

SUB-GROUPS

MIN

TYP⁽⁴⁾

890

505

2

MAX

UNIT

mA

µA

PDI = Low; PDQ = High

PDI = High; PDQ = Low

PDI = PDQ = High

I_A

Analog supply current

PDI = PDQ = Low

358

220

1

PDI = Low; PDQ = High

PDI = High; PDQ = Low

PDI = PDQ = High

Track-and-hold and clock

supply current

I_TC

I_DR

I_E

PDI = PDQ = Low

210

111

10

PDI = Low; PDQ = High

PDI = High; PDQ = Low

PDI = PDQ = High

Output driver supply current

PDI = PDQ = Low

60

mA

µA

PDI = Low; PDQ = High

PDI = High; PDQ = Low

PDI = PDQ = High

30.5

10

Digital encoder supply

current

PDI = PDQ = Low

2.9

3.22

1.88

W

PDI = Low; PDQ = High

PDI = High; PDQ = Low

PDI = PDQ = High

[1, 2, 3]

1.64

6

W

P_C

Power consumption

W

mW

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings

may damage this device.

V

A

TO INTERNAL

CIRCUITRY

I / O

GND

(2) To ensure accuracy, it is required that V_A, V_TC, V_Eand V_DRbe well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average

outgoing quality level (AOQL).

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6.13 Converter Electrical Characteristics: AC Electrical Characteristics

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.^(1)(2)(3)

PARAMETER

INPUT CLOCK (CLK)

TEST CONDITIONS

SUB-GROUPS

MIN

TYP⁽⁴⁾

MAX

UNIT

Maximum input clock

frequency

f_{CLK (max)}

f_{CLK (min)}

[9, 10, 11]

1

GHz

MHz

Non-DES mode

DES mode

[9, 10, 11]

200

Minimum input clock

frequency

250

50

Input clock duty cycle

Input clock low time

Input clock high time

f_{CLK (min)}≤ f_CLK≤ f_{CLK (max)}

20

200

80

%

ps

%

t_CL

500

50

t_CH

DCLK duty cycle

50

DCLK_RST

t_SRSetup time DCLK_RST±

t_HR

45

ps

Hold time DCLK_RST±

Input

Clock

Cycles

t_PWR

Pulse Width DCLK_RST±

5

DATA CLOCK (DCLKI, DCLKQ)

Input

Clock

Cycles

90° mode

4

DCLK synchronization

t_{SYNC_DLY}

delay

0° mode

5

Differential low-to-high

transition time

t_LHT

10% to 90%, C_L= 2.5 pF

220

ps

Differential high-to-low

transition time

t_HLT

10% to 90%, C_L= 2.5 pF

220

t_SU

t_H

Data-to-DCLK set-up time

DCLK-to-data hold time

DDR mode, 90° DCLK

850

ps

50% of DCLK transition to

50% of data transition

t_OSK

DCLK-to-data output skew

DCLK duty cycle

±75

ps

50

%

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings

may damage this device.

V

A

TO INTERNAL

CIRCUITRY

I / O

GND

(2) To ensure accuracy, it is required that V_A, V_TC, V_Eand V_DRbe well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average

outgoing quality level (AOQL).

28

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Converter Electrical Characteristics: AC Electrical Characteristics (continued)

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

SUB-GROUPS

MIN

TYP⁽⁴⁾

MAX

UNIT

DATA INPUT-TO-OUTPUT

Input CLK+ fall to

acquisition of data

t_AD

t_AJ

Sampling (aperture) delay

1.1

0.2

ns

Aperture jitter

ps (rms)

50% of input clock

transition to 50% of data

transition

Input clock-to data output

t_OD

2.4

ns

delay (in addition to t_LAT

)

DI, DQ outputs

34

35

34

35

Input

Clock

Cycles

Latency in 1:2 demux non-

DES mode⁽⁵⁾

[4, 5, 6]

DId, DQd outputs

DI outputs

34

34.5

35

34

34.5

35

Input

Clock

Cycles

DQ outputs

DId outputs

DQd Outputs

DI outputs

Latency in 1:4 demux DES

mode⁽⁵⁾

t_LAT

35.5

34

35.5

34

Input

Clock

Cycles

Latency in non-demux non-

DES mode⁽⁵⁾

[4, 5, 6]

DQ outputs

DI outputs

DQ outputs

34

Input

Clock

Cycles

Latency in non-demux DES

mode⁽⁵⁾

34.5

Differential V_INstep from

±1.2 V to 0 V to get

accurate conversion

Input

Clock

Cycle

t_ORR

Over-range recovery time

1

Non-DES mode

DES mode

500

1

ns

µs

PD low-to-rated accuracy

conversion (wake-up time)

t_WU

(5) This parameter is ensured by design and/or characterization and is not tested in production.

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6.14 Timing Requirements: Serial Port Interface

over operating free-air temperature range (unless otherwise noted)

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

See⁽⁵⁾

SUB-GROUPS

MIN

NOM⁽⁴⁾

MAX

UNIT

MHz

ns

f_SCLK

Serial clock frequency

Serial clock low time

Serial clock high time

15

[9, 10, 11]

30

ns

Serial data-to-serial clock

rising setup time

t_SSU

t_SH

See⁽⁵⁾

2.5

1

ns

Serial data-to-serial clock

rising hold time

SCS-to-serial clock rising

setup time

t_SCS

2.5

SCS-to-serial clock falling hold

time

t_HCS

t_BSU

1.5

10

ns

Bus turnaround time

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings

may damage this device.

V

A

TO INTERNAL

CIRCUITRY

I / O

GND

(2) To ensure accuracy, it is required that V_A, V_TC, V_Eand V_DRbe well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average

outgoing quality level (AOQL).

(5) This parameter is ensured by design and/or characterization and is not tested in production.

30

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6.15 Timing Requirements: Calibration

over operating free-air temperature range (unless otherwise noted)

The following specifications apply after calibration for V_A= V_DR= V_TC= V = 1.9 V; I-channel and Q-channel AC-coupled, FSR

pin = high; C_L= 10 pF; differential AC-coupled sine wave input clock, f_CLK= 1 GHz at 0.5 V_P-Pwith 50% duty cycle; V_BG

=

floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2

demultiplex non-DES mode; I channel and Q channel; duty-cycle stabilizer on.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

SUB-

MIN

NOM

MAX

UNIT

GROUPS

Non-ECM

2.4 × 10⁷

2.3 × 10⁷

Clock Cycles

ECM CSS = 0b

ECM; CSS = 1b

CMS(1:0) = 00b

CMS(1:0) = 01b

0.8 × 10⁷

1.5 × 10⁷

t_CAL

Calibration cycle time

Clock Cycles

CMS(1:0) = 10b (ECM

default)

2.4 × 10⁷

t_{CAL_L}

t_{CAL_H}

CAL pin low time

CAL pin high time

See⁽⁴⁾

[9, 10,11]

[9, 10, 11]

1280

Clock Cycles

(1) The analog inputs are protected as shown in the following graphic. Input voltage magnitudes beyond the Absolute Maximum Ratings

may damage this device.

V

A

TO INTERNAL

CIRCUITRY

I / O

GND

(2) To ensure accuracy, it is required that V_A, V_TC, V_Eand V_DRbe well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) The maximum clock frequency for non-demux mode is 1 GHz.

(4) This parameter is ensured by design and/or characterization and is not tested in production.

6.16 Quality Conformance Inspection

MIL-STD-883, Method 5005 - Group A

SUBGROUP

DESCRIPTION

Static tests at

TEMPERATURE (°C)

1

2

25

125

–55

25

Static tests at

3

Static tests at

4

Dynamic tests at

Functional tests at

Switching tests at

Setting time at

5

125

–55

25

6

7

8A

8B

9

125

–55

25

10

11

12

13

14

125

–55

25

Setting time at

125

–55

Setting time at

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6.17 Timing Diagrams

DQ

DI

c

DId

Sample N-1

Sample N

Sample N-0.5

DQd

c

V

Q+/-

IN

Sample

N-1.5

Sample N+1

t

AD

c

CLK+/-

t

OD

DQd, DId,

DQ, DI

Sample N-37.5, N-37,

N-36.5, N-36

Sample N-35.5, N-35,

N-34.5, N-34

Sample N-39.5, N-39,

N-38.5, N-38

t

OSK

DCLKQ+/-

(0°Phase)

t

H

SU

DCLKQ+/-

(90°Phase)

Figure 1. Clocking in 1:4 Demux DES Mode

Sample N

DI

Sample N-1

DId

V

I+/-

IN

Sample N+1

t

AD

CLK+

t

OD

Sample N-39 and

Sample N-38

DId, DI

Sample N-37 and Sample N-36

Sample N-35 and Sample N-34

t

OSK

DCLKI+/-

(0°Phase)

t

H

SU

DCLKI+/-

(90°Phase)

Figure 2. Clocking in 1:2 Demux Non-DES Mode*

* The timing here is shown for the I channel only. However, the Q channel functions precisely the same as the I

channel, with VinQ+, VinQ–, DCLKQ+, DCLKQ–, DQd and DQ instead of VinI+, VinI–, DCLKI+, DCLKI–, DId and

DI. Both the I channel and the Q channel use the same CLK+, CLK–.

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Timing Diagrams (continued)

Sample N

DQ

Sample N-1

DQd

V

Q+/-

IN

Sample N+1

t

AD

CLK+

t

OD

Sample N-37.5,

N-37

Sample N-34.5, N-34

Sample N-33.5, N-33

Sample N-36.5, N-36

DQ, DI

Sample N-35.5, N-35

t

OSK

DCLKQ+/-

(0°Phase)

Figure 3. Clocking in Non-Demux Mode Non-DES Mode**

** The timing here is shown for the Q channel only. However, for the non-demux non-DES node, either the I

channel and the Q channel may be used as input. For this case, the I-channel functions precisely the same as

those of the Q channel, with VinI+, VinI–, DCLKI+, DCLKI–, and DI instead of VinQ+, VinQ–, DCLKQ+, DCLKQ–,

and DQ. Both the I channel and Q channel use the same CLK+, CLK–.

Sample N - 0.5

Sample N

Sample N-1

DQ

DI

V

Q+/-

IN

Sample N + 0.5

DQ

Sample N+1

t

AD

CLK+

t

OD

Sample N-34.5, N-34

Sample N-33.5, N-33

Sample N-37.5, N-37

Sample N-36.5, N-36

DQ, DI

Sample N-35.5, N-35

t

OSK

DCLKQ+/-

(0°Phase)

Figure 4. Clocking in Non-Demux Mode DES Mode

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Timing Diagrams (continued)

Synchronizing Edge

t

SYNC_DLY

CLK

t

HR

t

SR

DCLK_RST-

DCLK_RST+

t

OD

t

PWR

DCLKI+

DCLKQ+

Figure 5. Data Clock Reset Timing

t

CAL

CalRun

t

CAL_H

CAL

t

CAL_L

POWER

SUPPLY

Figure 6. On-Command Calibration Timing

Single Register Access

SCS

t

SCS

t

HCS

t

HCS

24

1

8

9

SCLK

SDI

Command Field

Data Field

LSB

MSB

t

SH

t

SSU

t

BSU

SDO

ad mode)

High Z

LSB

Figure 7. Serial Interface Timing

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6.18 Typical Characteristics

V_A= V_DR= V_TC= V_E= 1.9 V, f_CLK= 1000 MHz, f_IN= 498 MHz, T_A= 25°C, I channel and Q channel, unused channel

terminated to AC ground and 1:2 demux non-DES mode (1:1 demux mode has similar performance), unless otherwise stated.

NPR plots Notch f_C= 325 MHz and Notch width = 25 MHz.

Figure 8. INL vs Code

Figure 9. INL vs Temperature

Figure 10. DNL vs Code

Figure 11. DNL vs Temperature

Figure 12. ENOB vs Temperature

Figure 13. ENOB vs Supply Voltage

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Typical Characteristics (continued)

V_A= V_DR= V_TC= V_E= 1.9 V, f_CLK= 1000 MHz, f_IN= 498 MHz, T_A= 25°C, I channel and Q channel, unused channel

terminated to AC ground and 1:2 demux non-DES mode (1:1 demux mode has similar performance), unless otherwise stated.

NPR plots Notch f_C= 325 MHz and Notch width = 25 MHz.

Figure 14. ENOB vs Clock Frequency

Figure 15. ENOB vs Input Frequency

Figure 16. SNR vs Temperature

Figure 17. SNR vs Supply Voltage

Figure 18. SNR vs Clock Frequency

Figure 19. SNR vs Input Frequency

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Typical Characteristics (continued)

V_A= V_DR= V_TC= V_E= 1.9 V, f_CLK= 1000 MHz, f_IN= 498 MHz, T_A= 25°C, I channel and Q channel, unused channel

terminated to AC ground and 1:2 demux non-DES mode (1:1 demux mode has similar performance), unless otherwise stated.

NPR plots Notch f_C= 325 MHz and Notch width = 25 MHz.

Figure 20. THD vs Temperature

Figure 21. THD vs Supply Voltage

Figure 22. THD vs Clock Frequency

Figure 23. THD vs Input Frequency

Figure 24. SFDR vs Temperature

Figure 25. SFDR vs Supply Voltage

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Typical Characteristics (continued)

V_A= V_DR= V_TC= V_E= 1.9 V, f_CLK= 1000 MHz, f_IN= 498 MHz, T_A= 25°C, I channel and Q channel, unused channel

terminated to AC ground and 1:2 demux non-DES mode (1:1 demux mode has similar performance), unless otherwise stated.

NPR plots Notch f_C= 325 MHz and Notch width = 25 MHz.

Figure 26. SFDR vs Clock Frequency

Figure 27. SFDR vs Input Frequency

Figure 28. Spectral Response at FIN = 248 MHz

Figure 29. Spectral Response at FIN = 498 MHz

Figure 30. Crosstalk vs Source Frequency

Figure 31. Full Power Bandwidth

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Typical Characteristics (continued)

V_A= V_DR= V_TC= V_E= 1.9 V, f_CLK= 1000 MHz, f_IN= 498 MHz, T_A= 25°C, I channel and Q channel, unused channel

terminated to AC ground and 1:2 demux non-DES mode (1:1 demux mode has similar performance), unless otherwise stated.

NPR plots Notch f_C= 325 MHz and Notch width = 25 MHz.

Figure 32. Power Consumption vs Clock Frequency

Figure 33. Gain vs Temperature FS Percent Change

Figure 34. Gain vs Temperature ENOB

Figure 35. Gain vs Temperature FS

Figure 36. NPR vs f_CNotch

Figure 37. Amplitude vs Frequency

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Typical Characteristics (continued)

V_A= V_DR= V_TC= V_E= 1.9 V, f_CLK= 1000 MHz, f_IN= 498 MHz, T_A= 25°C, I channel and Q channel, unused channel

terminated to AC ground and 1:2 demux non-DES mode (1:1 demux mode has similar performance), unless otherwise stated.

NPR plots Notch f_C= 325 MHz and Notch width = 25 MHz.

Figure 38. NPR vs RMS Noise Loading Level

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7 Detailed Description

7.1 Overview

The ADC10D1000 is a versatile analog-to-digital converter with an innovative architecture permitting very high-

speed operation. The controls available ease the application of the device to circuit solutions. Optimum

performance requires adherence to the provisions discussed here and in Application and Implementation. This

section covers an overview and the control modes: extended control mode (ECM) and non extended control

mode (non-ECM).

The ADC10D1000 uses a calibrated folding and interpolating architecture that achieves a high 9.0 effective

number of bits (ENOB). The use of folding amplifiers greatly reduces the number of comparators and power

consumption. Interpolation reduces the number of front-end amplifiers required, minimizing the load on the input

signal and further reducing power requirements. In addition to correcting other non-idealities, on-chip calibration

reduces the INL bow often seen with folding architectures. The result is an extremely fast, high-performance,

low-power converter. The calibration registers are radiation hard and are not upset by a heavy ion strike up to

120 MeV-cm²/mg.

The analog input signal (which is within the input voltage range of the converter) is digitized to ten bits at speeds

of 200 MHz to 1300 MHz, typical. Differential input voltages below negative full-scale cause the output word to

consist of all zeroes. Differential input voltages above positive full-scale cause the output word to consist of all

ones. Either of these conditions at the I- or Q-input causes the out-of-range I-channel or Q-channel output (ORI

or ORQ), respectively, to output a logic-high signal.

The device may be operated in one of two control modes: ECM or non-ECM. In non-ECM, the features of the

device may be accessed via simple pin control. In ECM, an expanded feature set is available via the serial

interface. Important new features include AutoSync for multi-chip synchronization, programmable 15-bit input full-

scale range and independent programmable 12-bit plus sign offset adjustment.

Each channel has a selectable output demultiplexer, which feeds two LVDS buses. If the 1:2 demux mode is

selected, the output data rate is reduced to half the input sample rate on each bus. When non-demux mode is

selected, the output data rate on each channel is at the same rate as the input sample clock and only one 10-bit

bus per channel is active.

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7.2 Functional Block Diagram

10

VinI+

Rterm

VinI-

DI(9:0)

10

1:2

10-Bit

ADC

T/H

Demux

DId(9:0)

DCLKI

ORI

M

U

X

RCOut1

RCOut2

Clock

Management

and AutoSync

Output

Buffers

ORQ

DCLKQ

10

VinQ+

Rterm

DQ(9:0)

10

1:2

10-Bit

ADC

T/H

Demux

DQd(9:0)

VinQ-

CLK+

Rterm

Control/Status

and Other Logic

CLK-

RCLK+

Rterm

SPI

Control Pins

RCLK-

7.3 Feature Description

7.3.1 Features

The ADC10D1000 offers many features to make the device convenient to use in a wide variety of applications.

Table 1 is a summary of the features available, as well as details for the control mode chosen.

Table 1. Features and Modes

CONTROL PIN ACTIVE

FEATURE

NON-ECM

ECM

DEFAULT ECM STATE

IN ECM

INPUT CONTROL AND ADJUST

Selected via the

Configuration Register

(Addr: 3h and Bh)

Input full-scale adjust

setting

Selected via FSR

(pin Y3)

No

mid FSR value

Offset = 0 mV

LC filter off

Selected via the

Configuration Register

(Addr: 2h and Ah)

Input offset adjust setting

LC filter on Clock

Not available

Not applicable

Selected via the

Configuration Register

(Addr: Dh)

Selected via the

Configuration Register

(Addr: Ch and Dh)

Sampling clock phase

adjust

Not available

Not applicable

No

Phase adjust disable

Non-DES mode

V_CMO

DES/Non-DES mode

selection

Selected via DES bit

(Addr: Ch and Dh

Selected via the

Configuration Register

(Addr: 1h)

V_CMOadjust

Not applicable

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Feature Description (continued)

Table 1. Features and Modes (continued)

CONTROL PIN ACTIVE

IN ECM

FEATURE

NON-ECM

ECM

DEFAULT ECM STATE

OUTPUT CONTROL AND ADJUST

Selected via DPS in the

Configuration Register

(Addr: 0h; Bit: 14)

DDR clock phase

selection

Selected via DDRPh

No

0° mode

(pin W4)

LVDS differential output

voltage amplitude

selection

Selected via OVS in the

Configuration Register

(Addr: 0h; Bit: 13)

Higher amplitude only

Not applicable

Yes

Higher amplitude

Offset binary

LVDS common-mode

output voltage amplitude

selection

Selected via V_BG

(pin B1)

Not available

Selected via 2SC in the

Configuration Register

(Addr: 0h; Bit: 4)

Output formatting

selection

Offset binary only

Not applicable

Selected via TPM in the

Configuration Register

(Addr: 0h; Bit: 12)

Test pattern mode at

output

Selected via TPM

(pin A4)

No

TPM not active

N/A

Demux/non-demux mode

selection

Selected via NDM

(pin A5)

Yes

Not available

Selected via the

Configuration Register

(Addr: Eh)

Master mode, RCOut1/2

disabled

AutoSync

Not available

Not applicable

Select via the Config Reg

DCLK RST

DLCK reset disabled

(Addr: Eh)

CALIBRATION

Selected via CAL in the

Configuration Register

(Addr: 0h; Bit: 15)

On-command calibration

event

Selected via CAL

(pin D6)

N/A

(CAL = 0)

Yes

POWER-DOWN

Selected via PDI in the

Configuration Register

(Addr: 0h; Bit: 11)

Selected via PDI

(pin U3)

Power down I channel

Yes

I channel operational

Q channel operational

Selected via PDQ in

theConfiguration Register

(Addr: 0h; Bit: 10)

Selected via PDQ

(pin V3)

Power down Q channel

7.3.1.1 Input Control and Adjust

There are several features and configurations for the input of the ADC10D1000. This section covers input full-

scale range adjust, input offset adjust, DES/non-DES modes, sampling clock phase adjust, and LC filter on the

sampling clock.

7.3.1.1.1 AC- and DC-Coupled Modes

The analog inputs may be AC- or DC-coupled. See AC-DC-Coupled Mode Pin (V_CMO) for information on how to

select the desired mode; see DC-Coupled Input Signals and AC-Coupled Input Signals for applications

information.

7.3.1.1.2 Input Full-Scale Range Adjust

The input full-scale range for the ADC10D1000 may be adjusted via non-ECM or ECM. In non-ECM, a control

pin selects a higher or lower value; see Full-Scale Input Range Pin (FSR). In ECM, the input full-scale range may

be selected with 15 bits of precision; see V_{IN_FSR}in Converter Electrical Characteristics: Analog Input/Output and

Reference Characteristics, for details. Note that the higher and lower full-scale input range settings in non-ECM

do not correspond to the maximum and minimum full-scale input range settings in ECM. It is necessary to

execute a manual calibration following any change of the input full-scale range. See Register Maps for

information about the registers.

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7.3.1.1.3 Input Offset Adjust

The input offset adjust for the ADC10D1000 may be adjusted with 12 bits of precision plus sign via ECM. See

Register Maps for information about the registers.

7.3.1.1.4 DES/Non-DES Mode

The ADC10D1000 is available in dual-edge sampling (DES) or non-DES mode. The DES mode allows for the

device Q-channel input to be sampled by the ADCs of both channels. One ADC samples the input on the rising

edge of the input clock and the other ADC samples the same input on the falling edge of the input clock. A single

input is thus sampled twice per input clock cycle, resulting in an overall sample rate of twice the input clock

frequency, for example, 2 GSPS with a 1-GHz input clock. See for information on how to select the desired

mode.

For the DES mode, only the Q channel may be used for the input. This may be selected in ECM by using the

DES bit (Addr: 0h, Bit 7) to select the DES mode and the DESQ bit (Addr: 0h, Bit: 6) to select the Q channel as

input.

In this mode, the outputs must be carefully interleaved in order to reconstruct the sampled signal. If the device is

programmed into the 1:4 Demux DES mode, the data is effectively demultiplexed by 1:4. If the input clock is 1

GHz, the effective sampling rate is doubled to 2 GSPS, and each of the 4 output buses has an output rate of 500

MHz. All data is available in parallel. To properly reconstruct the sampled waveform, the four words of parallel

data that are output with each DCLK must be correctly interleaved. The sampling order is as follows, from the

earliest to the latest: DQd, DId, DQ, DI. See Figure 1. If the device is programmed into the non-demux DES

mode, two bytes of parallel data are output with each edge of the DCLK in the following sampling order, from the

earliest to the latest: DQ, DI. See Figure 4.

The performance of the ADC10D1000 in DES mode depends on how well the two channels are interleaved; that

is, that the clock samples each channel with precisely a 50% duty cycle, each channel has the same offset

(nominally code 511/512), and each channel has the same full-scale range. The ADC10D1000 also includes an

automatic clock phase background adjustment in DES mode to automatically and continuously adjust the clock

phase of the I and Q channels. This feature removes the need to adjust the clock phase setting manually and

provides optimal performance in the DES mode. A difference exists in the typical offset between the I and Q

channels, which can be removed via the offset adjust feature in ECM to optimize DES mode performance. To

adjust the I- and Q-channel offset, measure a histogram of the digital data and adjust the offset via the control

register until the histogram is centered at code 511/512. Similarly, the full-scale range of each channel may be

adjusted for optimal performance.

7.3.1.1.5 Sampling Clock Phase Adjust

The sampling clock (CLK) phase may be delayed internally to the ADC up to 825 ps in ECM. This feature is

intended to help the system designer remove small imbalances in clock distribution traces at the board level

when multiple ADCs are used, or simplify complex system functions such as beam steering for phase array

antennas. A clock-jitter cleaner is available only when the CLK phase adjust feature is used. This adjustment

delays all clocks, including the DCLKs and output data, and the user is strongly advised to use the minimal

amount of adjustment and verify the net benefit of this feature in the system before relying on it.

7.3.1.1.6 LC Filter-On Input Clock

An LC bandpass filter is available on the ADC10D1000 sampling clock to clean jitter on the incoming clock. This

feature is available when the CLK phase adjust is also used. This feature was designed to minimize the dynamic

performance degradation resulting from additional clock jitter as much as possible. This feature is available in

ECM via the LC filter (LCF) bits in the Control Register (Addr: Dh, Bits 7:0).

If the clock phase adjust feature is enabled, the sampling clock passes through additional gate delay, which adds

jitter to the clock signal; the LCF helps to remove this additional jitter, so it is only available when the clock phase

adjust feature is also enabled. To enable both features, use SA (Addr: Dh, Bit 8). The LCF bits are thermometer

encoded and may be used to set a filter center frequency ranging from 0.8 GHz to 1.5 GHz; see Table 2.

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Table 2. LC Filter Code vs F_C

LCF(7:0)

f_C(GHz)

1.5

0

1

2

3

4

5

6

7

8

0000 0000b

0000 0001b

0000 0011b

0000 0111b

0000 1111b

0001 1111b

0011 1111b

0111 1111b

1111 1111b

1.4

1.3

1.2

1.1

1

0.92

0.85

0.8

The LC filter is a second-order bandpass filter, which has the following simulated bandwidth for a center

frequency, f_cat 1 GHz (see Table 3).

Table 3. LC Filter Bandwidth at 1 GHz

BANDWIDTH [dB]

BANDWIDTH [MHz]

–3

–6

±135

±235

±360

±525

–9

–12

7.3.1.1.7 V_CMOAdjust

The V_CMOof the ADC10D1000QML is generated as a buffered version of the internal bandgap reference; see

AC-DC-Coupled Mode Pin (V_CMO). This pin provides an output voltage, which is the optimal common-mode

voltage for the input signal and should be used to set the common-mode voltage of the driving buffer. However,

in order to accommodate larger signals at the analog inputs, the V_CMOmay be adjusted to a lower value. From its

typical default value, the V_CMOmay be lowered by approximately 200 mV via the VCA(2:0) bits of the Control

Register (Addr: 1h; Bits: 7:5) in ECM. See Register Definitions for more information. Adjusting the V_CMOaway

from its optimal value also degrades the dynamic performance; see V_CMOin Recommended Operating

Conditions.

7.3.1.2 Output Control and Adjust

There are several features and configurations for the output of the ADC10D1000 so that it may be used in many

different applications. This section covers DDR clock phase, LVDS output differential and common-mode voltage,

output formatting, Demux/Non-Demux Mode, and test pattern mode.

7.3.1.2.1 DDR Clock Phase

The ADC10D1000 output data is always delivered in double data rate (DDR). With DDR, the DCLK frequency is

half the data rate and data is sent to the outputs on both edges of DCLK; see Figure 39. The DCLK-to-data

phase relationship may be either 0° or 90°. For 0° mode, the data transitions on each edge of the DCLK. Any

offset from this timing is t_OSK; see Converter Electrical Characteristics: AC Electrical Characteristics for details.

For 90° mode, the DCLK transitions in the middle of each data cell. Setup and hold times for this transition, t_SU

and t_H, may also be found in Converter Electrical Characteristics: AC Electrical Characteristics. The DCLK-to-

data phase relationship may be selected via the DDRPh Pin in Non-ECM (see Dual Data-Rate Phase Pin

(DDRPh)) or the DPS bit in the Configuration Register (Addr: 0h; Bit: 14) in ECM.

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Data

DCLK

0°Mode

DCLK

90°Mode

Figure 39. DDR DCLK-to-Data Phase Relationship

7.3.1.2.2 LVDS Output Differential Voltage

The ADC10D1000 is available with a selectable higher or lower LVDS output differential voltage. This parameter

is V_ODand may be found in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics.

The desired voltage may be selected via OVS Bit (Addr: 0h, Bit 13); see Register Maps for more information. In

non-extended control mode only higher V_ODis available.

7.3.1.2.3 LVDS Output Common-Mode Voltage

The ADC10D1000 is available with a selectable higher or lower LVDS output common-mode voltage. This

parameter is V_OSand may be found in Converter Electrical Characteristics: Digital Control and Output Pin

Characteristics. See LVDS Output Common-Mode Pin (V_BG) for information on how to select the desired voltage.

7.3.1.2.4 Output Formatting

The formatting at the digital data outputs may be either offset binary or two's complement. The desired formatting

is set via the 2SC bit of the Control Register (Addr: 0h; Bit: 4) in ECM; see Register Maps for more information.

7.3.1.2.5 Demux/Non-Demux Mode

The ADC10D1000 may be in one of two demultiplex modes: demux mode or non-demux mode (also sometimes

referred to as 1:1 demux mode). In non-demux mode, the data from the input is simply output at the sampling

rate at which it was sampled on one 10-bit bus. In demux mode, the data from the input is output at half the

sampling rate, on twice the number of buses (see Functional Block Diagram). Demux or non-demux mode may

only be selected by the NDM pin; see Non-Demultiplexed Mode Pin (NDM). In non-DES mode, the output data

from each channel may be demultiplexed by a factor of 1:2 (1:2 demux non-DES mode). In DES mode, the

output data from both channels interleaved may be demultiplexed (1:4 demux DES mode) or not demultiplexed

(non-demux DES mode).

7.3.1.2.6 Test Pattern Mode

The ADC10D1000 can provide a test pattern at the four output buses independently of the input signal to aid in

system debug. In test-pattern mode, the ADC is disengaged, and a test pattern generator is connected to the

outputs, including ORI and ORQ. The test pattern output is the same in DES mode or non-DES mode. Each port

is given a unique 10-bit word, alternating between 1's and 0's. When the device is programmed into the demux

mode, the order of the test pattern is as described in Table 4.

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Table 4. Test Pattern By Output Port In

1:2 Demux Mode

TIME

T0

Qd

Id

Q

I

ORQ

0b

1b

0b

1b

0b

1b

0b

1b

0b

1b

0b

...

ORI

0b

1b

0b

1b

0b

1b

0b

1b

0b

1b

0b

...

COMMENTS

000h

3FFh

000h

3FFh

000h

3FFh

000h

3FFh

000h

3FFh

000h

...

001h

3FEh

001h

3FEh

001h

3FEh

001h

3FEh

001h

3FEh

001h

...

002h

3FDh

002h

3FDh

002h

3FDh

002h

3FDh

002h

3FDh

002h

...

004h

3FBh

004h

3FBh

004h

3FBh

004h

3FBh

004h

3FBh

004h

...

T1

Pattern sequence

T2

n

T3

T4

T5

T6

Pattern sequence

T7

n+1

T8

T9

T10

T11

T12

T13

Pattern sequence

n+2

When the device is programmed into the non-demux mode, the order of the test pattern is as described in

Table 5.

Table 5. Test Pattern By Output Port In

Non-Demux Mode

TIME

T0

I

Q

ORI

0b

1b

0b

1b

0b

1b

0b

1b

...

ORQ

0b

1b

0b

1b

0b

1b

0b

1b

...

COMMENTS

001h

3FEh

001h

3FEh

001h

3FEh

001h

3FEh

...

000h

3FFh

000h

3FFh

000h

3FFh

000h

3FFh

...

T1

T2

T3

Pattern

sequence

n

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

Pattern

sequence

n+1

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7.3.1.3 Calibration Feature

The ADC10D1000 calibration must be run to achieve specified performance. The calibration procedure is exactly

the same regardless of how it was initiated or when it is run. The DCLK outputs are present during all phases of

the calibration process. All data and over-range output bits are held at logic low during calibration. Calibration

must be performed in the planned mode of operation. Calibration trims the analog input differential termination

resistor, the CLK input resistor, and sets internal bias currents which affects the linearity of the converter. This

minimizes full-scale error, offset error, DNL and INL, resulting in maximizing the dynamic performance as

measured by SNR, THD, SINAD (SNDR), and ENOB.

7.3.1.3.1 Calibration Pins

Table 6 is a summary of the pins used for calibration. See Pin Configuration and Functions for complete pin

information and Figure 6 for the timing diagram.

Table 6. Calibration Pins

NAME

FUNCTION

CAL

(calibration)

D6

Initiate calibration event; see Calibration Pin (CAL)

CalRun

(calibration running)

B5

Indicates when calibration is running

External resistor used to calibrate analog and CLK inputs

External resistor used to calibrate internal linearity

Rtrim+, Rtrim–

(input termination trim resistor)

C1/D2

C3/D3

Rext+, Rext–

(external reference resistor)

7.3.1.3.2 How to Initiate a Calibration Event

The calibration event must be initiated by holding the CAL pin low for at least t_{CAL_L}clock cycles, and then

holding it high for at least another t_{CAL_H}clock cycles, as defined in Timing Requirements: Calibration. The

minimum t_{CAL_L}and t_{CAL_H}input clock cycle sequences are required to ensure that random noise does not cause

a calibration to begin when it is not desired. The time taken by the calibration procedure is specified as t_CAL. In

ECM, either the CAL bit (Addr: 0h; Bit: 15) or the CAL pin may be used to initiate a calibration event.

7.3.1.3.3 On-Command Calibration

An on-command calibration must be run after power up and whenever the FSR is changed. TI recommends

execution of an on-command calibration whenever the settings or conditions to the device are altered

significantly, in order to obtain optimal parametric performance. Some examples include: changing the FSR via

either ECM or non-ECM, power-cycling either channel, and switching into or out of DES mode. For best

performance, it is also recommended that an on-command calibration be run 20 seconds or more after

application of power and whenever the operating temperature changes significantly, relative to the specific

system performance requirements.

Due to the nature of the calibration feature, TI recommends avoiding unnecessary activities on the device while

the calibration is taking place. For example, do not read or write to the serial interface or use the DCLK reset

feature while calibrating the ADC. Doing so impairs the performance of the device until it is re-calibrated

correctly. Also, it is recommended to not apply a strong narrow-band signal to the analog inputs during calibration

because this may impair the accuracy of the calibration; broad spectrum noise is acceptable.

7.3.1.3.4 Calibration Adjust

The calibration event itself may be adjusted, for sequence and mode. This feature can be used if a shorter

calibration time than the default is required; see t_CALin Timing Requirements: Calibration. However, the

performance of the device, when using a shorter calibration time than the default setting, is not ensured.

The calibration sequence may be adjusted via CSS (Addr: 4h, bit 14). The default setting of CSS = 1b executes

both R_INand R_IN_CLK calibration (using Rtrim) and internal linearity calibration (using Rext). Executing a

calibration with CSS = 0b executes only the internal linearity calibration. The first time that calibration is

executed, it must be with CSS = 1b to trim R_INand R_IN_CLK. However, once the device is at its operating

temperature, and R_INhas been trimmed at least one time, it does not drift significantly. To save time in

subsequent calibrations, trimming R_INand R_IN_CLK may be skipped — that is, by setting CSS = 0b.

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The mode may be changed, to save calibration execution time for the internal linearity calibration. See t_CALin

Converter Electrical Characteristics: AC Electrical Characteristics. Adjusting the CMS(1:0) bits of the Calibration

Adjust Register (Addr: 4h; Bits: 9:8) selects three different pre-defined calibration times. A longer of time

calibrates each channel more closely to the ideal values, but choosing shorter times does not significantly impact

the performance. The fourth setting, CMS(1:0) = 11b, is not available.

7.3.1.3.5 Calibration and Power Down

If PDI and PDQ are simultaneously asserted during a calibration cycle, the ADC10D1000 immediately powers

down. The calibration cycle continues when either or both channels are powered back up, but the calibration is

compromised due to the incomplete settling of bias currents directly after power up. Therefore, a new calibration

must be executed upon powering the ADC10D1000 back up. In general, the ADC10D1000 must be re-calibrated

when either or both channels are powered back up, or after one channel is powered down. For best results,

power back up after the device has stabilized to its operating temperature.

7.3.1.3.6 Read/Write Calibration Settings

When the ADC performs a calibration, the calibration constants are stored in an array which is accessible via the

Calibration Values Register (Addr: 5h). To save the time that it takes to execute a calibration, t_CAL, or if re-using a

previous calibration result, these values can be read from and written to the register at a later time. For example,

if an application requires the same input impedance, R_IN, this feature can be used to load a previously

determined set of values. For the calibration values to be valid, the ADC must be operating under the same

conditions, including temperature, at which the calibration values were originally read from the ADC.

To read calibration values from the SPI, do the following:

1. Set ADC to desired operating conditions.

2. Set SSC (Addr: 4h, Bit 7) to 1

3. Read exactly 184 times the Calibration Values Register (Addr: 5h). The register values are R0, R1, R2...

R183 where R0 is a dummy value. The contents of R <183:1> must be stored.

4. Set SSC (Addr: 4h, Bit 7) to 0.

5. Continue with normal operation.

To write calibration values to the SPI, do the following:

1. Set ADC to operating conditions at which calibration values were previously read.

2. Set SSC (Addr: 4h, Bit 7) to 1.

3. Write exactly 183 times the Calibration Values Register (Addr: 5h). The registers should be written with

stored register values R1, R2... R183.

4. Make two additional dummy writes of 0000h.

5. Set SSC (Addr: 4h, Bit 7) to 0.

6. Continue with normal operation.

7.3.1.4 Power Down

On the ADC10D1000, the I and Q channels may be powered down individually. This may be accomplished via

the control pins, PDI and PDQ, or via the PDI and PDQ bits of the Control Register (Addr: 0h; Bits: 11:10) in

ECM. In ECM, the PDI and PDQ pins are logically OR'd with the Control Register setting. See Power-Down I-

Channel Pin (PDI) and Power-Down Q-Channel Pin (PDQ) for more information.

7.3.2 Power-On Reset

The device power-on reset has been disabled to ensure single-effect functional interrupts do not occur during

space operation. Therefore, the calibration routine at power-on is not reliable for the space version of the

ADC10D1000. This means a manual calibration is always required after the device is power-on and is stable.

Specifically, the device must either be in non-ECM or in ECM with the configuration registers reset or written to

the correct values, and then a manual calibration must be run before the ADC can be used to digitize data

correctly. See Calibration Feature for more information on calibration.

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7.4 Device Functional Modes

7.4.1 Control Modes

The ADC10D1000 may be operated in one of two control modes: non-extended control mode (non-ECM) or

extended control mode (ECM). In the simpler non-ECM (also sometimes referred to as pin-control mode), the

user affects available configuration and control of the device through the control pins. The ECM provides

additional configuration and control options through a serial interface and a set of 16 registers.

7.4.1.1 Non-Extended Control Mode

In non-ECM, the serial interface is not active and all available functions are controlled with various pin settings.

Non-ECM is selected by setting ECE (pin B3) to logic high. Seven dedicated control pins provide a wide range of

control for the ADC10D1000 and facilitate its operation. These control pins provide demux mode selection, DDR

phase selection, calibration event initiation, power-down I channel, power-down Q channel, test-pattern mode

selection, and full-scale input range selection. In addition to this, a one dual-purpose control pin provides for

LVDS output common-mode voltage selection. See Table 7 for a summary.

Table 7. Non-ECM Pin Summary

PIN NAME

NDM

LOGIC LOW

demux mode

0° mode

LOGIC HIGH

non-demux mode

90° mode

FLOATING

Not allowed

DDRPh

CAL

See Calibration Pin (CAL)

Power-down

I channel

PDI

I channel active

Q channel active

Not allowed

Power-down

Q channel

PDQ

TPM

FSR

Non-test pattern mode

Lower FS input range

Test pattern mode

Not allowed

Higher FS input range

DUAL-PURPOSE CONTROL PINS

V_CMO

V_BG

AC-coupled operation

Not allowed

DC-coupled operation

Higher LVDS common-mode voltage Lower LVDS common-mode voltage

7.4.1.1.1 Non-Demultiplexed Mode Pin (NDM)

The non-demultiplexed mode (NDM) pin selects whether the ADC10D1000 is in demux mode (logic-low) or non-

demux mode (logic-high). In Non-demux mode, the data from the input is produced at the data-rate at a single

10-bit output bus. In demux mode, the data from the input is produced at half the data-rate at twice the number

of output buses. For non-des mode, each I or Q channel produces its data on one or two buses for non-demux

mode or demux mode, respectively. For DES mode, the Q channel produces its data on two or four buses for

non-demux mode or demux mode, respectively.

This feature is pin-controlled only and remains active during both non-ECM and ECM. See Table 7 for more

information.

7.4.1.1.2 Dual Data-Rate Phase Pin (DDRPh)

The dual data-rate-phase (DDRPh) pin selects whether the ADC10D1000 is in 0° mode (logic-low) or 90° mode

(logic-high). In dual data rate (DDR) mode, the data may transition either with the DCLK transition (0° mode) or

halfway between DCLK transitions (90° mode). The data is always in DDR mode on the ADC10D1000. The

DDRPh pin selects 0° mode or 90° mode for both the I-channel DI- and DId-to-DCLKI phase relationship and for

the Q-channel DQ- and DQd-to-DCLKQ phase relationship.

To use this feature in ECM, use the DPS bit in the Configuration Register (Addr: 0h; Bit: 14). See Table 11 for

more information.

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7.4.1.1.3 Calibration Pin (CAL)

The calibration pin (CAL) must be used to initiate an on-command calibration event. The effect of calibration is to

maximize the dynamic performance. To initiate an on-command calibration via the CAL pin, bring the CAL pin

high for a minimum of t_{CAL_H}input clock cycles after it has been low for a minimum of t_{CAL_L}input clock cycles.

Hold the CAL pin high when not in use to ensure no undesired calibrating in space environment. In ECM mode

this pin remains active and is logically OR'd with the CAL bit.

To use this feature in ECM, use the CAL bit in the Configuration Register (Addr: 0h; Bit: 15). See Calibration

Feature for more information.

7.4.1.1.4 Power-Down I-Channel Pin (PDI)

The power-down I-channel (PDI) pin selects whether the I channel is powered down (logic-high) or active (logic-

low). The digital data output pins (both positive and negative) are put into a high impedance state when the I

channel is powered down. Upon return to the active state, the pipeline contains meaningless information and

must be flushed. The supply currents (typicals and limits) are available for the I channel powered down or active

and may be found in Converter Electrical Characteristics: Power Supply Characteristics (1:2 Demux Mode). It is

recommended that the user thoroughly understand how the PDI feature functions in relationship with the

Calibration feature and control them appropriately for their application.

This pin remains active in ECM. In ECM, either this pin or the PDI bit (Addr: 0h; Bit: 11) in the Control Register

may be used to power down the I channel. See Power Down for more information.

7.4.1.1.5 Power-Down Q-Channel Pin (PDQ)

The power-down Q-channel (PDQ) pin selects whether the Q- channel is powered down (logic-high) or active

(logic-low). This pin functions similarly to the PDI pin, except that it applies to the Q channel. The PDI and PDQ

pins function independently of each other to control whether each I channel or Q channel is powered down or

active.

This pin remains active in ECM. In ECM, either this pin or the PDQ bit (Addr: 0h; Bit: 10) in the Control Register

may be used to power-down the I channel. See Power Down for more information.

7.4.1.1.6 Test Pattern Mode Pin (TPM)

The test-pattern mode (TPM) pin selects whether the output of the ADC10D1000 is a test pattern (logic-high) or

the converted input (logic-low). The ADC10D1000 can provide a test pattern at the four output buses

independently of the input signal to aid in system debug. In TPM, the ADC is disengaged, and a test pattern

generator is connected to the outputs, including ORI and ORQ. See Test Pattern Mode for more information.

7.4.1.1.7 Full-Scale Input Range Pin (FSR)

The full-scale input range (FSR) pin selects whether the full-scale input range for both the I channel and Q

channel is higher (logic-high) or lower (logic-low). The input full-scale range is specified as V_{IN_FSR}in Converter

Electrical Characteristics: Analog Input/Output and Reference Characteristics. In non-ECM, the full-scale input

range for each I channel and Q channel may not be set independently, but it is possible to do so in ECM. The

device must be calibrated following a change in FSR to obtain optimal performance.

To use this feature in ECM, use the Configuration Register (Addr: 3h and Bh). See Input Control and Adjust for

more information.

7.4.1.1.8 AC-DC-Coupled Mode Pin (V_CMO

)

The V_CMOpin serves a dual purpose. When functioning as an output, it provides the optimal common-mode

voltage for the DC-coupled analog inputs. When functioning as an input, it selects whether the device is AC-

coupled (logic-low) or DC-coupled (floating). This pin is always active, in both ECM and non-ECM.

7.4.1.1.9 LVDS Output Common-Mode Pin (V_BG

)

The V_BGpin serves a dual purpose and may either provide the bandgap output voltage or select whether the

LVDS output common-mode voltage is higher (logic-high) or lower (floating). The LVDS output common-mode

voltage is specified as V_OSand may be found in Converter Electrical Characteristics: Digital Control and Output

Pin Characteristics. This pin is always active, in both ECM and Non-ECM. See Output Control and Adjust for

more information.

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7.4.2 Extended Control Mode

In extended control mode (ECM), all available functions are controlled via the serial interface. In addition to this,

several of the control pins remain active. See Table 1 for details. ECM is selected by setting ECE (pin B3) to

logic low.

The space version of the ADC10D1000 does not include a power-on reset. Therefore, when powered up in ECM,

the registers are in an unknown, random state. There are two ways to set the ECM registers: toggling the ECE

pin or writing to the registers. If the device is programmed into non-ECM (by setting ECE logic high), the registers

are programmed to their default values. Thus, if the ECE pin is set to logic high, then set to logic low (ECM), the

device will be in ECM, and the registers will have their default values. The second method is to simply explicitly

write the default (or otherwise desired) values to the register in ECM; TI recommends the second method.

7.5 Programming

Four pins on the ADC10D1000 control the serial interface: SCS, SCLK, SDI, and SDO. Serial Interface covers

the serial interface. Also see Register Maps.

7.5.1 Serial Interface

The ADC10D1000 offers a serial interface that allows access to the sixteen control registers within the device.

The serial interface is a generic 4-wire (optionally 3-wire) synchronous interface that is compatible with SPI-type

interfaces that are used on many microcontrollers and DSP controllers. Each serial interface access cycle is

exactly 24 bits long. A register-read or register-write can be accomplished in one cycle. The signals are defined

in such a way that the user can opt to simply join SDI and SDO signals in their system to accomplish a single,

bidirectional SDI/O signal. A summary of the pins for this interface may be found in Table 8. See Figure 7 for the

timing diagram and Converter Electrical Characteristics: AC Electrical Characteristics for timing specification

details. Control register contents are retained when the device is put into power-down mode.

Table 8. Serial Interface Pins

C4

C5

B4

A3

NAME

SCS (serial chip select)

SCLK (serial clock)

SDI (serial data in)

SDO (serial data out)

SCS: Each assertion (logic-low) of this signal starts a new register access; that is, the SDI command field must

be ready. The user is required to de-assert this signal after the 24th clock. If the SCS is de-asserted before the

24th clock, no data read/write occurs. If the SCS is asserted longer than 24 clocks, data write occurs normally

through the SDI input upon the 24th clock, and the SDO output holds the D0 bit until SCS is de-asserted. Setup

and hold times, t_SCSand t_HCS, with respect to the SCLK must be observed.

SCLK: This signal is used to register the input data (SDI) on the rising edge; and to source the output data

(SDO) on the falling edge. The user may disable the clock and hold it in the low-state. There is no minimum

frequency requirement for SCLK; see f_SCLKin Timing Requirements: Serial Port Interface for more details.

SDI: Each register access requires a specific 24-bit pattern at this input, consisting of a command field and a

data field. When in read mode, the data field is high impedance in case the bidirectional SDI/O option is used.

Setup and hold times, t_SHand t_SSU, with respect to the SCLK must be observed.

SDO: This output is normally tri-stated and is driven only when SCS is asserted, the first 8 bits of command data

have been received and it is a READ operation. The data is shifted out, MSB first, starting with the 8th clock's

falling edge. At the end of the access, when SCS is de-asserted, this output is tri-stated once again. If an invalid

address is accessed, the data sourced consists of all zeroes. Setup and hold times, t_SHand t_SSU, with respect to

the SCLK must be observed. If it is a READ operation, there is a bus turnaround time, t_BSU, from when the last bit

of the command field was read in until when the first bit of the data field is written out.

Table 9 shows the Serial Interface bit definitions.

Table 9. Command and Data Field Definitions

BIT NO.

NAMES

COMMENTS

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Table 9. Command and Data Field Definitions (continued)

1b indicates a read operation

0b indicates a write operation

1

2-3

4-7

8

Read/Write (R/W)

Reserved

A<3:0>

Bits must be set to 10b

16 registers may be addressed. The order is

MSB first

X

This is a "don't care" bit

Data written to or read from addressed

register

9-24

D<15:0>

Single Register Access

SCS

t

SCS

t

HCS

1

SCLK

SDI

Command Field

t

SH

t

SSU

Figure 40. Serial Interface Timing (Zoom Start)***

***SCS transition from High to Low must occur t_HCSafter the falling edge of SCLK, and t_SCSbefore the rising

edge of SCLK.

Single Register Access

SCS

t

HCS

24

SCLK

SDI

Data Field

LSB

Figure 41. Serial Interface Timing (Zoom End)****

****SCS transition from Low to High must occur t_HCSafter the 24^thSCLK cycle during a low cycle.

The serial data protocol is shown for a read and write operation in Figure 42 and Figure 43, respectively.

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

SCSb

SCLK

*Only required to be tri-stated in 3-wire mode.

1

0

A3

A2

A1

A0

X

SDI

R/W

SDO

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 42. Serial Data Protocol - Read Operation

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

SCSb

SCLK

R/W

1

0

A3

A2

A1

A0

X

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDI

SDO

Figure 43. Serial Data Protocol - Write Operation

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7.6 Register Maps

7.6.1 Register Definitions

Eight read/write registers provide several control and configuration options in the extended control mode. These

registers have no effect when the device is in the non-extended control mode. The ADC10D1000 does not have

a power-on reset. The user can write the registers with the desired values, or in extended control mode set

ECEb Logic high setting resisters to the default values.

Table 10. Register Addresses

A3

0

1

A2

0

1

0

1

A1

0

1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Hex

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

REGISTER ADDRESSED

Configuration Register 1

V_CMOAdjust

I-channel Offset

I-channel FSR

Res

Q-Channel Offset

Q-Channel FSR

Aperture Delay Coarse Adjust

Aperture Delay Fine Adjust and LC Filter Adjust

AutoSync

Res

Table 11. Configuration Register 1

Addr: 0h (0000b)

Default Values: 2000h

Bit

Name

DV

15

CAL

0

14

13

OVS

1

12

TPM

0

11

PDI

0

10

PDQ

0

9

Res

0

8

LFS

0

7

DES

0

6

DESQ

0

5

Res

0

4

2SC

0

3

0

2

1

0

DPS

0

Res

0

Bit 15

CAL: Calibration Enable. When this bit is set to 1b, an on-command calibration cycle is initiated. This bit is not reset

automatically upon completion of the cal cycle. Therefore, the user must reset this bit to 0b and then set it to 1b again to

initiate another calibration event. This bit is logically OR'd with the CAL pin; both bit and pin must be set to 0b before either is

used to execute a calibration.

Bit 14

Bit 13

DPS: DDR phase select. Set this bit to 0b to select the 0° Mode DDR Data-to-DCLK phase relationship and to 1b to select the

90° mode. This bit has no effect when the device is in Non-Demux Mode.

OVS: Output Voltage Select. This bit sets the differential voltage level for the LVDS outputs including Data, OR, RCOut1,

RCOut2 and DCLK. 0b selects the lower level and 1b selects the higher level. See V_ODin Converter Electrical Characteristics:

Digital Control and Output Pin Characteristics for details.

Bit 12

TPM: Test Pattern Mode. When this bit is set to 1b, the device continually outputs a fixed digital pattern at the digital data and

OR outputs. When set to 0b, the device continually outputs the converted signal, which was present at the analog inputs. See

Test Pattern Mode for details about the TPM pattern.

Bit 11

Bit 10

PDI: Power-down I channel. When this bit is set to 0b, the I channel is fully operational, but when it is set to 1b, the I channel

is powered down. The I channel may be powered down via this bit or the PDI pin, which is active, even in ECM.

PDQ: Power-down Q channel. When this bit is set to 0b, the Q channel is fully operational, but when it is set to 1b, the Q

channel is powered down. The Q channel may be powered-down via this bit or the PDQ pin, which is active, even in ECM.

Bits 9

Bits 8

Bit 7

Reserved. Must be set to 0b.

LFS: Low Frequency Select. If the sampling Clock (CLK) is at or below 300 MHz, set this bit to 1b.

DES: Dual-Edge-Sampling Mode Select. When this bit is set to 0b, the device operates in the non-DES mode; when it is set to

1b, the device operates in the DES mode. See DES/Non-DES Mode for more information about DES/non-DES mode.

Bit 6

DESQ: DES Q-channel select. When the device is in DES mode; always set this bit to 1b selecting the Q channel.

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Bit 5

Bit 4

Reserved. Must be set to 0b.

2SC: Two's Complement Output. For the default setting of 0b, the data is output in offset binary format; when set to 1b, the

data is output in two's complement format.

Bits 3:0

Reserved. Must be set to 0b.

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Table 12. V_CMOAdjust

Addr: 1h (0001b)

Default values: 2A00h

Bit

15

14

0

13

1

12

11

10

0

9

1

8

0

7

0

6

VCA(2:0)

0

5

0

4

0

3

0

2

Reserved

0

1

0

Name

POR

Reserved

0

1

0

Bits 15:8

Bits 7:5

Reserved. Must be set as shown.

VCA(2:0): V_CMOAdjust. Adjusting from the default VCA(2:0) = 0d to VCA(2:0) = 7d decreases V_CMOfrom its typical value (see

V_CMOin Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics) to 1.05 V by increments of

~28.6 mV.

CODE

V_CMO

000 (default)

V_CMO

100

V_CMO–114 mV

V_CMO–200 mV

111

Bits 4:0

Reserved. Must be set as shown.

Table 13. I-Channel Offset Adjust

Addr: 2h (0010b)

Default Values: 0000h

Bit

Name

DV

15

14

Reserved

0

13

0

12

OS

0

11

0

10

0

9

0

8

0

7

0

6

5

4

0

3

0

2

1

0

OM(11:0)

0

Bits 15:13 Reserved. Must be set to 0b.

Bit 12

OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by bits 11:0 to the ADC output. Setting

this bit to 1b incurs a negative offset of the set magnitude.

Bits 11:0

OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding).

The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 μV. Monotonicity is ensured by

design only for the 9 MSBs.

CODE

OFFSET [mV]

0000 0000 0000 (default)

1000 0000 0000

1111 1111 1111

0

22.5

45

Table 14. I-Channel Full Scale Range Adjust

Addr: 3h (0011b)

Bit 15

Name Res.

Default Values: 4000h

14

1

13

0

12

0

11

0

10

0

9

0

8

0

7

FM(14:0)

0

6

0

5

0

4

0

3

0

2

1

0

DV

0

Bit 15

Reserved. Must be set to 0b.

Bits 14:0

FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from

630 mV (0d) to 980 mV (32767d) with the default setting at 820 mV (162384d). Monotonicity is ensured by design only for the

9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR

values is available in EC; that is, FSR values above 820 mV. See Converter Electrical Characteristics: Analog Input/Output and

Reference Characteristics for characterization details.

CODE

FSR [mV]

630

000 0000 0000 0000

100 0000 0000 0000 (default)

111 1111 1111 1111

820

980

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Table 15. Calibration Adjust

Addr: 4h (0100b)

Default Values: DA7Fh

Bit

15

14

CSS

1

13

0

12

11

10

0

9

1

8

0

7

0

6

1

5

1

4

3

2

1

0

Name Res

Reserved

CMS

Reserved

DV

1

Bit 15

Bit 14

Reserved. Must be set to 1b.

CSS: calibration sequence select. The default 1b selects the following calibration sequence: reset all previously calibrated

elements to nominal values, do R_INcalibration, do internal linearity calibration. Setting CSS = 0b selects the following

calibration sequence: do not reset R_INto its nominal value, skip R_INcalibration, do internal linearity calibration. The calibration

must be completed at least one time with CSS = 1b to calibrate R_IN. Subsequent calibrations may be run with CSS = 0b (skip

R_INcalibration) or 1b (full R_INand internal linearity calibration).

Bits 13:10 Reserved. Must be set as shown.

Bits 9:8

CMS(1:0): Calibration Mode Select. These bits affect the length of time taken to calibrate the internal linearity. CMS(1:0) = 11b

is not available. See t_CALin Converter Electrical Characteristics: AC Electrical Characteristics.

Bits 7:0

Reserved. Must be set as shown.

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Table 16. Reserved

Addr: 5h (0101b)

Default Values: XXXXh

Bit

Name

DV

15

14

X

13

X

12

X

11

X

10

X

9

8

7

6

5

4

3

2

1

0

Reserved

X

Bits 15:0

Reserved. Do not write.

Table 17. Reserved

Addr: 6h (0110b)

Default Values: 1C70h

Bit

Name

DV

15

14

0

13

0

12

1

11

1

10

1

9

0

8

7

6

1

5

1

4

1

3

0

2

1

0

Reserved

0

Bits 15:0

Reserved. Must be set as shown.

Table 18. Reserved

Addr: 7h (0111b)

Default Values: 0000h

Bit

Name

DV

15

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

0

5

0

4

0

3

0

2

1

0

Reserved

0

Bits 15:0

Reserved. Must be set as shown.

Table 19. Reserved

Addr: 8h (1000b)

Default Values: 0000h

Bit

Name

DV

15

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

0

5

0

4

0

3

0

2

1

0

Reserved

0

Bits 15:0

Reserved. Must be set as shown.

Table 20. Reserved

Addr: 9h (1001b)

Default Values: 0000h

Bit

Name

DV

15

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

0

5

0

4

0

3

0

2

1

0

Reserved

0

Bits 15:0

Reserved. Must be set as shown.

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Table 21. Q-Channel Offset Adjust

Addr: Ah (1010b)

Default Values: 0000h

Bit

Name

DV

15

14

Reserved

0

13

0

12

OS

0

11

0

10

0

9

0

8

0

7

0

6

5

4

0

3

0

2

1

0

OM(11:0)

0

Bits 15:13 Reserved. Must be set to 0b.

Bit 12

OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting

this bit to 1b incurs a negative offset of the set magnitude.

Bits 11:0

OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding).

The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of -11 μV. Monotonicity is ensured by

design only for the 9MSBs.

CODE

OFFSET [mV]

0000 0000 0000 (default)

1000 0000 0000

1111 1111 1111

0

22.5

45

Table 22. Q-Channel Full-Scale Range Adjust

Addr: Bh (1011b)

Bit 15

Name Res

Default Values: 4000h

14

1

13

0

12

0

11

0

10

0

9

0

8

0

7

FM(14:0)

0

6

0

5

0

4

0

3

0

2

1

0

DV

0

Bit 15

Reserved. Must be set to 0b.

Bits 14:0

FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from

630 mV (0d) to 980 mV (32767d) with the default setting at 820 mV (16384d). Monotonicity is ensured by design only for the 9

MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR

values is available in ECM; that is, FSR values above 820 mV. See Converter Electrical Characteristics: Analog Input/Output

and Reference Characteristicsfor characterization details.

CODE

FSR [mV]

630

000 0000 0000 0000

100 0000 0000 0000 (default)

111 1111 1111 1111

820

980

Table 23. Aperture Delay Coarse Adjust

Addr: Ch (1100b)

Default Values: 0004h

Bit

Name

DV

15

14

0

13

0

12

0

11

0

10

9

8

0

7

0

6

0

5

0

4

0

3

STA

0

2

DCC

1

0

CAM(11:0)

Reserved

0

Bits 15:4

CAM(11:0): Coarse Adjust Magnitude. This 12-bit value determines the amount of delay that will be applied to the input CLK

signal. The range is 0 ps delay for CAM(11:0) = 0d to a maximum delay of 825 ps for CAM(11:0) = 2431d (±95 ps due to PVT

variation) in steps of ~340 fs. For code CAM(11:0) = 2432d and above, the delay saturates and the maximum delay applies.

Additional, finer delay steps are available in register Dh. Either STA (Bit 3) or SA (Addr: Dh, Bit 8) must be selected to enable

this function.

Bit 3

STA: Select t_ADAdjust. Set this bit to 1b to enable the t_ADadjust feature. When using this feature, make sure that SA (Addr:

Dh, Bit 8) is set to 0b.

Bit 2

DCC: Duty Cycle Correct. This bit can be set to 0b to disable the automatic duty-cycle stabilizer feature of the chip. This

feature is enabled by default.

Bits 1:0

Reserved. Must be set to 0b.

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Table 24. Aperture Delay Fine Adjust and LC Filter Adjust

Addr: Dh (1101b)

Default Values: 0000h

Bit

Name

DV

15

14

0

13

12

0

11

0

10

0

9

Res

0

8

SA

0

7

0

6

0

5

0

4

3

0

2

1

0

FAM(5:0)

LCF(7:0)

0

Bits 15:10 FAM(5:0): Fine Aperture Adjust Magnitude. This 6-bit value determines the amount of additional delay that will be applied to

the input CLK when the Clock Phase Adjust feature is enabled via STA (Addr: Ch, Bit 3) or SA (Addr: Dh, Bit 8). The range is

straight binary from 0 ps delay for FAM(5:0) = 0d to 2.3 ps delay for FAM(5:0) = 63d (±300 fs due to PVT variation) in steps of

~36 fs.

Bit 9

Bit 8

Reserved. Must be set to 0b.

SA: Select t_ADand LC filter adjust. Set this bit to 1b to enable the t_ADand LC filter adjust features. Using this bit is the same as

enabling STA (Addr: Ch, Bit3), but also enables the LC filter to clean the clock jitter.

Bits 7:0

LCF(7:0): LC tank select frequency. Use these bits to select the center frequency of the LC filter on the Clock inputs. The

range is from 0.8 GHz (255d) to 1.5 GHz (0d). Note that the tuning range is not binary encoded, and the eight bits are

thermometer encoded; that is, the mid value of 1.1 GHz tuning is achieved with LCF(7:0) = 0000 1111b.

Table 25. AutoSync

Addr: Eh (1110b)

Default Values: 0003h

Bit

Name

DV

15

14

0

13

0

12

0

11

10

0

9

0

8

0

7

0

6

0

5

Res.

0

4

3

0

2

ES

0

1

DOC

1

0

DR

1

DRC(9:0)

SP(1:0)

0

Bits 15:6

DRC(9:0): Delay Reference Clock (9:0). These bits may be used to increase the delay on the input reference clock when

synchronizing multiple ADCs. The minimum delay is 0s (0d) to 1000 ps (639d). The delay remains the maximum of 1000 ps for

any codes above or equal to 639d.

Bit 5

Reserved. Must be set to 0b.

Bits 4:3

SP(1:0): Select Phase. These bits select the phase of the reference clock which is latched. The codes correspond to the

following phase shift:

00 = 0°

01 = 90°

10 = 180°

11 = 270°

Bit 2

Bit 1

Bit 0

ES: Enable Slave. Set this bit to 1b to enable the slave mode of operation. In this mode, the internal divided clocks are

synchronized with the reference clock coming from the master ADC. The master clock is applied on the input pins RCLK+ or

RCLK-. If this bit is set to 0b, then the device is in master mode.

DOC: Disable Output Reference Clocks. Setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2. The default

setting of 1b disables these output drivers. This bit functions as described, regardless of whether the device is operating in

master or slave mode, as determined by ES (Bit 2).

DR: Disable Reset. The default setting of 1b leaves the DCLK_RST functionality disabled. Set this bit to 0b to enable

DCLK_RST functionality.

Table 26. Reserved

Addr: Fh (1111b)

Default Values: XXXXh

Bit

Name

DV

15

14

X

13

X

12

X

11

X

10

X

9

8

7

6

5

4

3

2

1

0

Reserved

X

Bits 15:0

Reserved. Do not write.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Analog Inputs

The ADC10D1000 continuously converts any signal which is present at the analog inputs, as long as a CLK

signal is also provided to the device. This section covers important aspects related to the analog inputs including:

acquiring the input, the reference voltage and FSR, out-of-range indication, AC-coupled signals, and single-

ended input signals.

8.1.1.1 Acquiring the Input

Data is acquired at the rising edge of CLK+ in non-DES mode and both the falling and rising edge of CLK+ in

DES mode. The digital equivalent of that data is available at the digital outputs a constant number of input clock

cycles later for the DI, DQ, DId and DQd output buses, also known as latency, depending on the demultiplex

mode which was chosen. See t_LATin Converter Electrical Characteristics: AC Electrical Characteristics. In

addition to latency, there is a constant output delay, t_OD, before the data is available at the outputs. See t_ODin

Converter Electrical Characteristics: AC Electrical Characteristics and Timing Diagrams.

For demux mode, the signal which is sampled at the input will appear at the output after a certain latency, as

shown in Table 27.

Table 27. Input Channel Samples Produced at Data Outputs in Demultiplexed Mode

DES MODE

(Q channel ONLY)

DATA OUTPUTS

NON-DES MODE

I channel sampled with rise of CLK,

34 cycles earlier.

Q channel sampled with rise of CLK,

34 cycles earlier.

DI

DQ

Q channel sampled with rise of CLK,

34 cycles earlier.

Q channel sampled with fall of CLK,

34.5 cycles earlier.

I channel sampled with rise of CLK,

35 cycles earlier.

Q channel sampled with rise of CLK,

35 cycles earlier.

DId

DQd

Q channel sampled with rise of CLK,

35 cycles earlier.

Q channel sampled with fall of CLK,

35.5 cycles earlier.

Non-Demux Mode is similarly shown in Table 28.

Table 28. Input Channel Samples Produced at Data Outputs in Non-Demux Mode

DES MODE

(Q channel ONLY)

DATA OUTPUTS

NON-DES MODE

I channel sampled with rise of CLK,

34 cycles earlier.

Q channel sampled with rise of CLK,

34 cycles earlier.

DI

DQ

Q channel sampled with rise of CLK,

34 cycles earlier.

Q channel sampled with fall of CLK,

34.5 cycles earlier.

No output;

high impedance.

No output;

high impedance.

DId

DQd

No output;

high impedance.

No output;

high impedance.

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8.1.1.2 Terminating Unused Analog Inputs

In the case that only one channel is used in non-des mode or that the ADC is driven in DESI or DESQ mode, the

unused analog input must be terminated to reduce any noise coupling into the ADC. See Table 29 for details.

Table 29. Unused Analog Input Recommended Termination

MODE

POWER DOWN

COUPLING

AC/DC

DC

RECOMMENDED TERMINATION

Tie unused+ and unused– to V_BG

Tie unused+ to unused–

Non-DES

Yes

No

DES/ Non-DES

No

AC

8.1.1.3 Reference Voltage and FSR

The full-scale analog differential input range (V_{IN_FSR}) of the ADC10D1000 is derived from an internal 1.254-V

bandgap reference. In non-ECM, this full-scale range has two settings controlled by the FSR pin; see Full-Scale

Input Range Pin (FSR). The FSR pin operates on both the I channel and the Q channel. In ECM, the full-scale

range may be independently set for each channel via the I-channel and Q-channel Full-Scale Range Adjust

Registers (Addr: 3h and Bh, respectively) with 15 bits of precision; see Register Maps. The best SNR is obtained

with a higher full-scale input range, but better distortion and SFDR are obtained with a lower full-scale input

range. It is not possible to use an external analog reference voltage to modify the full-scale range, and this

adjustment should only be done digitally, as described.

A buffered version of the internal 1.254-V bandgap reference voltage is made available at the V_BGpin for the

user. The V_BGpin can drive a load of up to 80 pF and source or sink up to ±100 μA; it must be buffered if more

current than this is required. The pin remains as a constant reference voltage regardless of what full-scale range

is selected and may be used for a system reference. V_BGis a dual-purpose pin and it may also be used to select

a higher LVDS output common-mode voltage; see LVDS Output Common-Mode Voltage.

8.1.1.4 Out-of-Range Indication

Differential input signals are digitized to 10 bits, based on the full-scale range. Signal excursions beyond the full-

scale range (greater than +V_IN/ 2 or less than –V_IN/ 2) are clipped at the output. An input signal that is above

the FSR results in all 1's at the output and an input signal which is below the FSR results in all 0's at the output.

When the conversion result is clipped for the I-channel input, the ORI I-channel output is activated such that

ORI+ goes high and ORI– goes low for the time that the signal is out of range. This output is active as long as

accurate data on either or both of the buses would be outside the range of 000h to 3FFh. The Q channel has a

separate ORQ which functions similarly.

8.1.1.5 AC-Coupled Input Signals

The ADC10D1000QML-SP analog inputs require a precise common-mode voltage. This voltage is generated

onchip when AC-coupling mode is selected. See AC-DC-Coupled Mode Pin (V_CMO) for more information about

how to select AC-coupled mode.

In AC-coupled mode, the analog inputs must of course be AC-coupled. For an ADC10D1000QML-SP used in a

typical application, this may be accomplished by on-board capacitors, as shown in Figure 44.

When the AC-coupled mode is selected, an analog input channel that is not used (for example, in DES mode)

must be connected to AC ground — for example, through capacitors to ground. Do not connect an unused

analog input directly to ground.

C

couple

V

+

IN

couple

V

-

IN

V

CMO

ADC12D1XXX

Figure 44. AC-Coupled Differential Input

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The analog inputs for the ADC10D1000QML-SP are internally buffered, which simplifies the task of driving these

inputs and the RC pole, which is generally used at sampling ADC inputs, is not required. If the user desires to

place an amplifier circuit before the ADC, take care to choose an amplifier with adequate noise and distortion

performance, and adequate gain at the frequencies used for the application.

8.1.1.6 DC-Coupled Input Signals

In DC-coupled mode, the ADC10D1000QML-SP differential inputs must have the correct common-mode voltage.

This voltage is provided by the device itself at the V_CMOoutput pin. TI recommends using this voltage because

the V_CMOoutput potential changes with temperature and the common-mode voltage of the driving device must

track this change. Full-scale distortion performance falls off as the input common-mode voltage deviates from

V_CMO. Therefore, TI recommends keeping the input common-mode voltage within 100 mV of V_CMO(typical),

although this range may be extended to ±150 mV (maximum).

8.1.1.7 Single-Ended Input Signals

It is not possible on the ADC10D1000 to accept single-ended signals. The best way to handle single-ended

signals is to first convert them to differential signals before presenting them to the ADC. The easiest way to

accomplish single-ended to differential signal conversion is with an appropriate balun-transformer, as shown in

Figure 45.

C

couple

V

IN

+

50W

Source

100W

1:2 Balun

V

IN

-

C

couple

ADC10D1000

Figure 45. Single-Ended-to-Differential Conversion Using a Balun

When selecting a balun, it is important to understand the input architecture of the ADC. The impedance of the

analog source must be matched to the ADC10D1000's on-chip 100-Ω differential input termination resistor. The

range of this termination resistor is specified as R_INin Converter Electrical Characteristics: Analog Input/Output

and Reference Characteristics.

8.1.2 Clock Inputs

The ADC10D1000 has a differential clock input, CLK+ and CLK–, which must be driven with an AC-coupled,

differential clock signal. This provides the level shifting to the clock to be driven with LVDS, PECL, LVPECL, or

CML levels. The clock inputs are internally terminated to 100-Ω differential and self-biased. This section covers

coupling, frequency range, level, duty-cycle, jitter, and layout considerations.

8.1.2.1 CLK Coupling

The clock inputs of the ADC10D1000 must be capacitively coupled to the clock pins as indicated in Figure 46.

C

couple

CLK+

CLK-

ADC10D1000

Figure 46. Differential Input Clock Connection

The choice of capacitor values depends on the clock frequency, capacitor component characteristics, and other

system factors.

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8.1.2.2 CLK Frequency

Although the ADC10D1000 is tested and its performance is ensured with a differential 1-GHz clock, the device

typically functions well over the input clock frequency range; see f_{CLK (min)}and f_{CLK (max)}in Converter Electrical

Characteristics: AC Electrical Characteristics. Operation up to f_CLK

is possible if the maximum ambient

(max)

temperatures indicated are not exceeded. Operating at sample rates above f_{CLK (max)}for the maximum ambient

temperature may result in reduced device reliability and product lifetime. This is due to the fact that higher

sample rates results in higher power consumption and die temperatures. If the f_CLK≤ 300 MHz, enable LFS in

control register (Addr: 0h Bit 8).

8.1.2.3 CLK Level

The input clock amplitude is specified as V_{IN_CLK}in Converter Electrical Characteristics: LVDS CLK Input

Characteristics. Input clock amplitudes above the maximum V_{IN_CLK}may result in increased input offset voltage.

This would cause the converter to produce an output code other than the expected 511/512 when both input pins

are at the same potential. Insufficient input clock levels will result in poor dynamic performance. Both of these

results may be avoided by keeping the clock input amplitude within the specified limits of V_{IN_CLK.}

8.1.2.4 CLK Duty Cycle

The duty cycle of the input clock signal can affect the performance of any ADC. The ADC10D1000 features a

duty-cycle-clock correction circuit, which can maintain performance over the 20%-to-80% specified clock duty

cycle range. This feature is enabled by default and provides improved ADC clocking, especially in the dual-edge

sampling (DES) mode.

8.1.2.5 CLK Jitter

High-speed, high-performance ADCs such as the ADC10D1000 require a very stable input clock signal with

minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of bits),

maximum ADC input frequency and the input signal amplitude relative to the ADC input full-scale range. The

maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR is

found to be

t_J(MAX)= (V_IN(P-P)/ V_FSR) × (1/(2^(N+1)× π × f_IN))

where

•

t_J(MAX)is the rms total of all jitter sources in seconds

V_IN(P-P)is the peak-to-peak analog input signal

V_FSRis the full-scale range of the ADC

N is the ADC resolution in bits

f_INis the maximum input frequency, in Hertz, at the ADC analog input

(1)

t_J(MAX)is the square root of the sum of the squares (RSS) sum of the jitter from all sources, including the ADC

input clock, system, input signals and the ADC itself. Since the effective jitter added by the ADC is beyond user

control, TI recommends keeping the sum of all other externally added jitter to a mimimum.

8.1.2.6 CLK Layout

The ADC10D1000 clock input is internally terminated with a trimmed 100-Ω resistor. The differential input clock

line pair must have a characteristic impedance of 100 Ω and (when using a balun), be terminated at the clock

source in that (100-Ω) characteristic impedance.

It is good practice to keep the ADC input clock line as short as possible, to keep it well away from any other

signals, and to treat it as a transmission line. Otherwise, other signals can introduce jitter into the input clock

signal. Also, the clock signal can also introduce noise into the analog path if it is not properly isolated.

8.1.3 The LVDS Outputs

The Data, ORI, ORQ, DCLKI, and DCLKQ outputs are LVDS. The electrical specifications of the LVDS outputs

are compatible with typical LVDS receivers available on ASIC and FPGA chips, but they are not IEEE or ANSI

communications standards compliant due to the low 1.9-V supply used on this device. These outputs must be

terminated with a 100-Ω differential resister placed as closely as possible to the receiver. This section covers

common-mode and differential voltage, and data rate.

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8.1.3.1 Common-Mode and Differential Voltage

The LVDS outputs have selectable common-mode and differential voltage, V_OSand V_OD; see Converter Electrical

Characteristics: Digital Control and Output Pin Characteristics. See Output Control and Adjust for more

information.

Selecting the higher V_OSalso increases V_ODby up to 40 mV. The differential voltage, V_OD, may be selected for

the higher or lower value. For short LVDS lines and low noise systems, satisfactory performance may be realized

with the lower V_OD. This also results in lower power consumption. If the LVDS lines are long and/or the system in

which the ADC10D1000 is used is noisy, it may be necessary to select the higher V_OD

.

8.1.3.2 Output Data Rate

The data is produced at the output at the same rate as it is sampled at the input. The minimum recommended

input clock rate for this device is f_{CLK (MIN)}; see Converter Electrical Characteristics: AC Electrical Characteristics.

However, it is possible to operate the device in 1:2 demux mode and capture data from just one 10-bit bus, for

example, just DI (or DId) although both DI and DId are fully operational. This will decimate the data by two and

effectively halve the data rate.

8.1.4 Synchronizing Multiple ADC10D1000S in a System

The ADC10D1000 has two features to assist the user with synchronizing multiple ADCs in a system: AutoSync

and DCLK Reset. The AutoSync feature is new and designates one ADC10D1000 as the master ADC and other

ADC10D1000s in the system as Slave ADCs. The DCLK Reset feature performs the same function as the

AutoSync feature, but is the first generation solution to synchronizing multiple ADCs in a system; it is disabled by

default. For applications in which there are multiple master and slave ADC10D1000s in a system, AutoSync may

be used to synchronize the slave ADC10D1000(s) to each respective master ADC10D1000, and the DCLK

Reset may be used to synchronize the master ADC10D1000s with each other.

If the AutoSync or DCLK reset feature is not used, see Table 30 for recommendations about terminating unused

ins.

Table 30. Unused AutoSync and DCLK Pin Recommendations

PIN(s)

UNUSED TERMINATION

Do not connect.

RCLK+, RCLK–

RCOUT1+, RCOUT–

RCOUT2+, RCOUT–

DCLK_RST+

Do not connect.

Connect to GND with a 1-kΩ resistor.

Connect to VA with a 1-kΩ resistor.

DCLK_RST–

8.1.4.1 AutoSync Feature

AutoSync is a new feature, which continuously synchronizes the outputs of multiple ADC10D1000s in a system.

It may be used to synchronize the DCLK and data outputs of one or more dlave ADC10D1000s to one master

ADC10D1000. Several advantages of this feature include no special synchronization pulse required, any upset in

synchronization is recovered upon the next DCLK cycle, and the master/dlave ADC10D1000s may be arranged

as a binary tree so that any upset quickly propagates out of the system.

An example system, which consists of one master ADC and two slave ADCs, is shown in Figure 47. For

simplicity, only one DCLK is shown; in reality, there is DCLKI and DCLKQ, but they are always in phase with one

another.

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Slave 1

ADC10D1000

Slave 2

ADC10D1000

RCOut1

RCOut2

DCLK

RCOut1

RCOut2

DCLK

Master

ADC10D1000

RCOut1

RCOut2

DCLK

CLK

Figure 47. AutoSync Example

In order to synchronize the DCLK (and data) outputs of multiple ADCs, the DCLKs must transition at the same

time, as well as be in phase with one another. The DCLK at each ADC is generated from the CLK after some

latency, plus t_ODminus t_AD. Therefore, in order for the DCLKs to transition at the same time, the CLK signal must

reach each ADC at the same time. To tune out any differences in the CLK path to each ADC, the t_ADadjust

feature may be used. However, using the t_ADadjust feature will also affect when the DCLK is produced at the

output. If the device is in demux mode, then there are four possible phases which each DCLK may be generated

on because the typical CLK = 1 GHz and DCLK = 250 MHz for this case. The RCLK signal controls the phase of

the DCLK, so that each Slave DCLK is on the same phase as the Master DCLK.

The AutoSync feature may only be used via the Control Registers. For more information, see AN-2132

Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (SNAA073).

8.1.4.2 DCLK Reset Feature

The DCLK reset feature is available via ECM, but is disabled by default. DCLKI and DCLKQ are always

synchronized, by design, and do not require a pulse from DCLK_RST to become synchronized.

The DCLK_RST signal must observe certain timing requirements, which are shown in Figure 5 of Timing

Diagrams. The DCLK_RST pulse must be of a minimum width and its deassertion edge must observe setup and

hold times with respect to the CLK input rising edge. These timing specifications are listed as t_PWR, t_SRand t_HR

and may be found in Converter Electrical Characteristics: AC Electrical Characteristics.

The DCLK_RST signal can be asserted asynchronously to the input clock. If DCLK_RST is asserted, the DCLK

output is held in a designated state (logic-high) in demux mode; in non-demux mode, the DCLK continues to

function normally. Depending upon when the DCLK_RST signal is asserted, there may be a narrow pulse on the

DCLK line during this reset event When the DCLK_RST signal is de-asserted, there are t_{SYNC_DLY}CLK cycles of

systematic delay, and the next CLK rising edge synchronizes the DCLK output with those of other ADC10D1000s

in the system. For 90° mode (DDRPh = logic-high), the synchronizing edge occurs on the rising edge of CLK, 4

cycles after the first rising edge of CLK after DCLK_RST is released. For 0° mode (DDRPh = logic-low), this is 5

cycles instead. The DCLK output is enabled again after a constant delay of t_OD

.

For both demux and non-demux modes, there is some uncertainty about how DCLK comes out of the reset state

for the first DCLK_RST pulse. For the second (and subsequent) DCLK_RST pulses, the DCLK comes out of the

reset state in a known way. Therefore, if using the DCLK reset feature, TI recommends applying one dummy

DCLK_RST pulse before using the second DCLK_RST pulse to synchronize the outputs. This recommendation

applies each time the device or channel is powered on.

When the DCLK_RST function is not going to be used TI recommends pulling the DCLK+ pin to GND through a

261-Ω resister and pulling the DCLK− pin to V_Athrough a 261-Ω resistor (see Figure 48). This provides noise

immunity and prevent false resets.

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V

A

5/[Y+

5/[Y-

261

!5/1051000

!Db5

Figure 48. DCLK RST±

When using DCLK-RST to synchronize multiple ADC10D1000s, it is required that the select phase bits in the

Control Register (Addr: Eh, Bits 3,4) be the same for each Slave ADC10D1000.

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9 Power Supply Recommendations

9.1 Power Planes

Source all supply buses for the ADC from a common linear voltage regulator. This ensures that all power buses

to the ADC are turned on and off simultaneously. This single source is split into individual sections of the power

plane, with individual decoupling and connection to the different power supply buses of the ADC. Due to the low

voltage but relatively high supply current requirement, the optimal solution may be to use a switching regulator to

provide an intermediate low voltage, which is then regulated down to the final ADC supply voltage by a linear

regulator. Refer to the documentation provided for the ADC10D1000RB for additional details on specific

regulators that TI recommends for this configuration.

Provide power for the ADC through a broad plane, which is located on one layer adjacent to the ground plane(s).

Placing the power and ground planes on adjacent layers provides low impedance decoupling of the ADC

supplies, especially at higher frequencies. The output of a linear regulator must feed into the power plane

through a low impedance multi-via connection. Split the power plane into individual power peninsulas near the

ADC. Each peninsula should feed a particular power bus on the ADC, with decoupling for that power bus

connecting the peninsula to the ground plane near each power/ground pin pair. Using this technique can be

difficult on many printed circuit CAD tools. To work around this, 0-Ω resistors can be used to connect the power

source net to the individual nets for the different ADC power buses. As a final step, the 0-Ω resistors can be

removed, and the plane and peninsulas can be connected manually after all other error checking is completed.

9.1.1 Bypass Capacitors

The general recommendation is to have one 100-nF capacitor for each power/ground pin pair. The capacitors

must be surface mount multi-layer ceramic chip capacitors similar to Presidio SR0402X7R104KENG5.

9.1.1.1 Ground Plane

Grounding must be done using continuous full ground planes to minimize the impedance for all ground return

paths, and provide the shortest possible image/return path for all signal traces.

9.1.1.2 Power Supply Example

The ADC10D1000RB uses continuous ground planes (except where clear areas are needed to provide

appropriate impedance management for specific signals), see Figure 49. Power is provided on one plane, with

the 1.9-V ADC supply being split into multiple zones or peninsulas for the specific power buses of the ADC.

Decoupling capacitors are connected between these power bus peninsulas and the adjacent power planes using

vias. The capacitors are located as close to the individual power/ground pin pairs of the ADC as possible. In

most cases, this means the capacitors are located on the opposite side of the PCB to the ADC.

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Power Planes (continued)

HV or Unreg

Voltage

Linear

Regulator

Switching

Regulator

Cross Section

Line

Intermediate

Voltage

1.9V ADC Main

V_TCV_AV_E

V_DR

ADC

Top Layer œ Signal 1

Ground 1

Dielectric 1

Dielectric 2

Dielectric 3

Dielectric 4

Dielectric 5

Dielectric 6

Dielectric 7

Signal 2

Ground 2

Signal 3

Power 1

Ground 3

Bottom Layer œ Signal X

Figure 49. Power and Grounding Example

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10 Layout

10.1 Layout Guidelines

10.1.1 Board Mounting Recommendation

Proper thermal profile is required to establish re-flow under the package and ensure all joints meet profile

specifications, See Table 31.

Table 31. Solder Profile Specification

MAXIMUM PEAK

TEMPERATURE

RANGE UP

PEAK TEMPERATURE (T_PK

)

RAMP DOWN

≤ 4°C/sec

210°C ≤ t_PK≤ 215°C

≤ 220°C

≤ 5°C/sec

The 220°C peak temperature is driven by the requirement to limit the dissolution of lead from the high-melt

column to the eutectic solder. Too much lead increases the effective melting point of the board-side joint and

makes it much more difficult to remove the part if module rework is required.

Cool-down rates and methods affect CCGA assemble yield and reliability. Picking up boards or opening the oven

while solder joints are in molten state can disturb the solder joint. Do not pick up boards until the solder joints

have fully solidified. Board warping may potentially cause the CCGA to lift off of pads during cooling and this

condition can also cause column cracking when severe. This warping is a result of a high differential cooling rate

between the top and bottom of the board. Both conditions can be prevented by using even top and bottom

cooling.

10.2 Layout Example

Figure 50. Landing Pattern Recommendation

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10.3 Thermal Management

The ceramic column grid array (CCGA) package is a modified ceramic land grid array with an added heat sink.

The signal columns on the outer edge are 1.27-mm pitch, while the columns in the center attached to the heat

sink are 1 mm. The smaller pitch for the center columns is to improve the thermal resistance. The center

columns of the package are attached to the back of the die through a heat sink. Connecting these columns to the

PCB ground planes with a low thermal resistance path is the best way to remove heat from the ADC. These pins

must also be connected to the ground planes through low impedance path for electrical purposes.

IC Die

Cross Section

Line

Heat Sink

Not to Scale

Figure 51. CCGA Conceptual Drawing

10.4 Temperature Sensor Diode

The ADC10D1000 has an on-die temperature diode connected to pins Tdiode+, Tdiode– which may be used to

monitor the die temperature. Texas Instruments also provides a family of temperature sensors for this application

which monitor different numbers of external devices, See Table 32.

Table 32. Temperature Sensor Recommendation

NUMBER OF EXTERNAL DEVICES MONITORED

RECOMMENDED TEMPERATURE SENSOR

1

2

4

LM95235

LM95213

LM95214

The LM95235/13/14 is an 11-bit digital temperature sensor with a 2-wire system management bus (SMBus)

interface that can monitor the temperature of one/two/four remote diodes as well as its own temperature. The

LM95235/13/14 can be used to accurately monitor the temperature of up to one/two/four external devices such

as the ADC10D1000, a FPGA, other system components, and the ambient temperature.

The LM95235/13/14 reports temperature in two different formats for 127.875°C range and 0°/255°C range. The

LM95235/13/14 has a sigma-delta ADC core which provides the first level of noise immunity. For improved

performance in a noise environment, the LM9535/13/14 includes programmable digital filters for remote diode

temperature readings. When the digital filters are invoked, the resolution for the remote diode readings increases

to 0.03125°C. For maximum flexibility and best accuracy, the LM95235/13/14 includes offset registers that allow

calibration of other diode types.

Diode fault detection circuitry in the LM95235/13/14 can detect the absence or fault state of a remote diode:

whether the D+ pin is detected as shorted to GND, D-, VDD or D+ is floating.

In the following typical application, the LM95213 is used to monitor the temperature of an ADC10D1000 as well

as an FPGA. See Figure 52.

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7

5

D1+

I

= I

F

E

100 pF

ADC10D1000

I

R

D-

I

E

= I

F

100 pF

FPGA

6

D2+

I

R

LM95213

Figure 52. Typical Temperature Sensor Application

10.5 Radiation Environments

Give careful consideration to environmental conditions when using a product in a radiation environment.

10.5.1 Total Ionizing Dose

Radiation hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level

specified in on the front page. Testing and qualification of these products is done on a wafer level according to

MIL-STD-883, Test Method 1019. Wafer-level TID data is available with lot shipments.

10.5.2 Single Event Latch-Up and Functional Interrupt

One time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was preformed

according to EIA/JEDEC Standard, EIA/JEDEC57. The linear energy transfer threshold (LETth) shown in

Features is the maximum LET tested. A test report is available upon request.

10.5.3 Single Event Upset

A report on single event upset (SEU) is available at www.ti.com/radiation.

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Device Nomenclature

11.1.2.1 Specification Definitions

APERTURE (SAMPLING) DELAY is the amount of delay, measured from the sampling edge of the CLK input,

after which the signal present at the input pin is sampled inside the device.

APERTURE JITTER (t_AJ) is the variation in aperture delay from sample-to-sample. Aperture jitter can be

effectively considered as noise at the input.

CODE ERROR RATE (C.E.R.) is the probability of error and is defined as the probable number of word errors on

the ADC output per unit of time divided by the number of words seen in that amount of time. A CER of 10^-18

corresponds to a statistical error in one word about every four (4) years.

CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of one

clock period.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB. It is measured at sample rate = 500 MSPS with a 1-MHz input sine wave.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion Ratio, or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and states that the converter is

equivalent to a perfect ADC of this many (ENOB) number of bits.

FULL POWER BANDWIDTH (FPBW) is a measure of the frequency at which the reconstructed output

fundamental drops to 3 dB below its low frequency value for a full-scale input.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Offset and

Full-Scale Errors. The Positive Gain Error is the Offset Error minus the Positive Full-Scale Error. The Negative

Gain Error is the Negative Full-Scale Error minus the Offset Error. The Gain Error is the Negative Full-Scale

Error minus the Positive Full-Scale Error; it is also equal to the Positive Gain Error plus the Negative Gain Error.

INTEGRAL NON-LINEARITY (INL) is a measure of worst case deviation of the ADC transfer function from an

ideal straight line drawn through the ADC transfer function. The deviation of any given code from this straight line

is measured from the center of that code value step. The best fit method is used.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in

the second and third order intermodulation products to the power in one of the original frequencies. IMD is

usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is

V_FS/ 2^N

(2)

where V_FSis the differential full-scale amplitude V_INas set by the FSR input and "N" is the ADC resolution in bits,

which is 10 for the ADC10D1000.

LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) DIFFERENTIAL OUTPUT VOLTAGE (V_IDand V_OD) is

two times the absolute value of the difference between the V_D+ and V_D– signals; each measured with respect to

Ground.

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Device Support (continued)

V

+

D

V

D

-

V

OD

V

D

+

V

OS

V

D

-

GND

V

= | V + - V - | x 2

D D

OD

Figure 53. LVDS Output Signal Levels

LVDS OUTPUT OFFSET VOLTAGE (V_OS) is the midpoint between the D+ and D– pins output voltage with

respect to ground; that is, [(V_D+) +( V_D-)]/2. See Figure 53.

MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These

codes cannot be reached with any input value.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.

NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of how far the first code transition is from the ideal 1/2

LSB above a differential −V_IN/2 with the FSR pin low. For the ADC10D1000 the reference voltage is assumed to

be ideal, so this error is a combination of full-scale error and reference voltage error.

NOISE POWER RATIO (NPR) is the ratio of the sum of the power inside the notched bins to the sum of the

power in an equal number of bins outside the notch, expressed in dB.

OFFSET ERROR (V_OFF) is a measure of how far the mid-scale point is from the ideal zero voltage differential

input. Offset Error = Actual Input causing average of 8k samples to result in an average code of 511.5.

OUTPUT DELAY (t_OD) is the time delay (in addition to Pipeline Delay) after the falling edge of CLK+ before the

data update is present at the output pins.

OVER-RANGE RECOVERY TIME is the time required after the differential input voltages goes from ±1.2 V to 0

V for the converter to recover and make a conversion with its rated accuracy.

PIPELINE DELAY (LATENCY) is the number of input clock cycles between initiation of conversion and when

that data is presented to the output driver stage. New data is available at every clock cycle, but the data lags the

conversion by the Pipeline Delay plus the t_OD

.

POSITIVE FULL-SCALE ERROR (PFSE) is a measure of how far the last code transition is from the ideal 1-1/2

LSB below a differential +V_IN/2. For the ADC10D1000 the reference voltage is assumed to be ideal, so this error

is a combination of full-scale error and reference voltage error.

POWER SUPPLY REJECTION RATIO (PSRR) is the ratio of the change in full-scale error that results from a

power supply voltage change from 1.8 V to 2 V. PSRR is expressed in dB.

SIGNAL-TO-NOISE RATIO (SNR) is the ratio, expressed in dB, of the RMS value of the input signal at the

output to the RMS value of the sum of all other spectral components below one-half the sampling frequency, not

including harmonics or DC.

SIGNAL-TO-NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the RMS value of

the input signal at the output to the RMS value of all of the other spectral components below half the input clock

frequency, including harmonics but excluding DC.

SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the RMS values of

the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the

output spectrum that is not present at the input, excluding DC.

TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the RMS total of the first nine harmonic

levels at the output to the level of the fundamental at the output. THD is calculated as

2

f10

A

+ . . . + A

f2

THD = 20 x log

2

A

f1

(3)

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Device Support (continued)

where A_f1is the RMS power of the fundamental (output) frequency and A_f2through A_f10are the RMS power of

the first 9 harmonic frequencies in the output spectrum.

– Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in the

input frequency seen at the output and the power in its 2nd harmonic level at the output.

– Third Harmonic Distortion (3rd Harm) is the difference expressed in dB between the RMS power in the input

frequency seen at the output and the power in its 3rd harmonic level at the output.

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 33. Related Links

PRODUCT

FOLDER

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

SAMPLE & BUY

ADC10D1000CCMLS

ADC10D1000CVAL

Click here

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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Product Folder Links: ADC10D1000QML-SP

ADC10D1000QML-SP

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SNAS466G –FEBRUARY 2009–REVISED DECEMBER 2016

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

12.1 Engineering Samples

Engineering samples are available for order and are identified by the MPR in the orderable device name (see

Packaging Information in the POA). Engineering (MPR) samples meet the performance specifications of the

datasheet at room temperature only and have not received the full space production flow or testing. Engineering

samples may be QCI rejects that failed tests that would not impact the performance at room temperature, such

as radiation or reliability testing.

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MECHANICAL DATA

NAA0376A

CCC376A (Rev D)

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型号：	ADC10D1000CCMPR
厂家：	TEXAS INSTRUMENTS
描述：	耐辐射加固保障 (RHA)、100krad、陶瓷、10 位、双通道 1GSPS 或单通道 2GSPS ADC \| NAA \| 376 \| 25 to 25 转换器
文件：	总81页 (文件大小：1440K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC10D1000CCMPR [TI]

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