ADC10D020CIVS/NOPB [TI]
双通道、10 位、20MSPS 模数转换器 (ADC) | PFB | 48 | -40 to 85;
| 型号： | ADC10D020CIVS/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双通道、10 位、20MSPS 模数转换器 (ADC) | PFB | 48 | -40 to 85 转换器 模数转换器 |
| 文件： | 总38页 (文件大小：1620K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC10D020
www.ti.com
SNAS143D –SEPTEMBER 2001–REVISED MARCH 2013
ADC10D020 Dual 10-Bit, 20 MSPS, 150 mW A/D Converter
Check for Samples: ADC10D020
1
FEATURES
DESCRIPTION
The ADC10D020 is
a
dual low power, high
2
•
•
•
•
•
Internal Sample-and-Hold
Internal Reference Capability
Dual Gain Settings
performance CMOS analog-to-digital converter that
digitizes signals to 10 bits resolution at sampling
rates up to 30 MSPS while consuming a typical 150
mW from a single 3.0V supply. No missing codes is
ensured over the full operating temperature range.
The unique two stage architecture achieves 9.5
Effective Bits over the entire Nyquist band at 20 MHz
sample rate. An output formatting choice of offset
binary or 2's complement coding and a choice of two
gain settings eases the interface to many systems.
Also allowing great flexibility of use is a selectable 10-
bit multiplexed or 20-bit parallel output mode. An
offset correction feature minimizes the offset error.
Offset Correction
Selectable Offset Binary or 2's Complement
Output
•
•
•
Multiplexed or Parallel Output Bus
Single +2.7V to 3.6V Operation
Power Down and Standby Modes
APPLICATIONS
•
•
•
•
•
•
Digital Video
To ease interfacing to most low voltage systems, the
digital output power pins of the ADC10D020 can be
tied to a separate supply voltage of 1.5V to 3.6V,
making the outputs compatible with other low voltage
systems. When not converting, power consumption
can be reduced by pulling the PD (Power Down) pin
high, placing the converter into a low power state
where it typically consumes less than 1 mW and from
which recovery is less than 1 ms. Bringing the STBY
(Standby) pin high places the converter into a
standby mode where power consumption is about 27
mW and from which recovery is 800 ns.
CCD Imaging
Portable Instrumentation
Communications
Medical Imaging
Ultrasound
KEY SPECIFICATIONS
•
•
•
•
•
Resolution 10 Bits
Conversion Rate 20 MSPS
ENOB 9.5 Bits (typ)
DNL 0.35 LSB (typ)
The ADC10D020's speed, resolution and single
supply operation makes it well suited for a variety of
applications,
applications.
including
high
speed
portable
Conversion Latency Parallel Outputs 2.5 Clock
Cycles
Operating over the industrial (−40° ≤ TA ≤ +85°C)
temperature range, the ADC10D020 is available in a
48-pin TQFP package. An evaluation board is
available to ease the design effort.
•
•
Multiplexed Outputs, I Data Bus 2.5 Clock
Cycles
Multiplexed Outputs, Q Data Bus 3 Clock
Cycles
•
•
PSRR 90 dB
Power Consumption—Normal Operation 150
mW (typ)
•
•
Power Down Mode <1 mW (typ)
Fast Recovery Standby Mode 27 mW (typ)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2013, Texas Instruments Incorporated
ADC10D020
SNAS143D –SEPTEMBER 2001–REVISED MARCH 2013
www.ti.com
Connection Diagram
Figure 1. TOP VIEW
24-Lead TQFP
See PFB Package
Block Diagram
2
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Pin No.
SNAS143D –SEPTEMBER 2001–REVISED MARCH 2013
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Symbol
Equivalent Circuit
Description
48
47
I+
I−
Analog inputs to “I” ADC. Nominal conversion range is 1.25V to
1.75V with GAIN pin low, or 1.0V to 2.0V with GAIN pin high.
37
38
Q+
Q−
Analog inputs to “Q” ADC. Nominal conversion range is 1.25V to
1.75V with GAIN pin low, or 1.0V to 2.0V with GAIN pin high.
Analog Reference Voltage input. The voltage at this pin should be in
the range of 0.8V to 1.5V. With 1.0V at this pin and the GAIN pin
low, the full scale differential inputs are 1 VP-P. With 1.0V at this pin
1
VREF
and the GAIN pin high, the full scale differential inputs are 2 VP-P
.
This pin should be bypassed with a minimum 1 µF capacitor.
This is an analog output which can be used as a reference source
and/or to set the common mode voltage of the input. It should be
bypassed with a minimum of 1 µF low ESR capacitor in parallel with
a 0.1 µF capacitor. This pin has a nominal output voltage of 1.5V
and has a 1 mA output source capability.
45
43
VCMO
Top of the reference ladder. Do not drive this pin. Bypass this pin
with a 10 µF low ESR capacitor and a 0.1 µF capacitor.
VRP
Bottom of the reference ladder. Do not drive this pin. Bypass this
pin with a 10 µF low ESR capacitor and a 0.1 µF capacitor.
44
VRN
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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)
Pin No.
Symbol
Equivalent Circuit
Description
Digital clock input for both converters. The analog inputs are
sampled on the falling edge of this clock input.
33
CLK
Output Bus Select. With this pin at a logic high, both the “I” and the
“Q” data are present on their respective 10-bit output buses (Parallel
mode of operation). When this pin is at a logic low, the “I” and “Q”
data are multiplexed onto the “I” output bus and the “Q” output lines
all remain at a logic low (multiplexed mode).
2
OS
OC
Offset Correct pin. A low-to-high transition on this pin initiates an
independent offset correction sequence for each converter, which
takes 34 clock cycles to complete. During this time 32 conversions
are taken and averaged. The result is subtracted from subsequent
conversions. Each input pair should have 0V differential value during
this entire 34 clock period.
31
Output Format pin. When this pin is LOW the output format is Offset
Binary. When this pin is HIGH the output format is 2's complement.
This pin may be changed asynchronously, but this will result in
errors for one or two conversions.
32
34
OF
Standby pin. The device operates normally with a logic low on this
and the PD (Power Down) pin. With this pin at a logic high and the
PD pin at a logic low, the device is in the standby mode where it
consumes just 27 mW of power. It takes just 800 ns to come out of
this mode after the STBY pin is brought low.
STBY
Power Down pin that, when high, puts the converter into the Power
Down mode where it consumes less than 1 mW of power. It takes
less than 1 ms to recover from this mode after the PD pin is brought
low. If both the STBY and PD pins are high simultaneously, the PD
pin dominates.
35
36
PD
This pin sets the internal signal gain at the inputs to the ADCs. With
this pin low the full scale differential input peak-to-peak signal is
equal to VREF. With this pin high the full scale differential input peak-
to-peak signal is equal to 2 x VREF..
GAIN
3V TTL/CMOS-compatible Digital Output pins that provide the
conversion results of the I and Q inputs. I0 and Q0 are the LSBs, I9
and Q9 are the MSBs. Valid data is present just after the rising edge
of the CLK input in the Parallel mode. In the multiplexed mode, I-
channel data is valid on I0 through I9 when the I/Q output is high
and the Q-channel data is valid on I0 through I9 when the I/Q output
is low.
8 thru 27
I0–I9 and Q0–Q9
Output data valid signal. In the multiplexed mode, this pin transitions
from low to high when the data bus transitions from Q-data to I-data,
and from high to low when the data bus transitions from I-data to Q-
data. In the Parallel mode, this pin transitions from low to high as the
output data changes.
28
I/Q
Positive analog supply pin. This pin should be connected to a quiet
voltage source of +2.7V to +3.6V. VA and VD should have a common
supply and be separately bypassed with 10 µF to 50 µF capacitors in
parallel with 0.1 µF capacitors.
40, 41
VA
VD
Digital supply pin. This pin should be connected to a quiet voltage
source of +2.7V to +3.6V. VA and VD should have a common supply
and be separately bypassed with 10 µF to 50 µF capacitors in
parallel with 0.1 µF capacitors.
4
Digital output driver supply pins. These pins should be connected to
a voltage source of +1.5V to VD and be bypassed with 10 µF to 50
µF capacitors in parallel with 0.1 µF capacitors.
6, 30
VDR
3, 39, 42,
46
The ground return for the analog supply. AGND and DGND should
be connected together close to the ADC10D020 package.
AGND
The ground return for the digital supply. AGND and DGND should be
connected together close to the ADC10D020 package.
5
DGND
7, 29
DR GND
The ground return of the digital output drivers.
4
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SNAS143D –SEPTEMBER 2001–REVISED MARCH 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)(3)
Absolute Maximum Ratings
Positive Supply Voltages
3.8V
−0.3V to (VA or VD +0.3V)
±25 mA
Voltage on Any Pin
(4)
Input Current at Any Pin
(4)
Package Input Current
±50 mA
(5)
Package Dissipation at TA = 25°C
See
(6)
ESD Susceptibility
Human Body Model
Machine Model
2500V
250V
(7)
Soldering Temperature, Infrared,10 sec.
Storage Temperature
235°C
−65°C to +150°C
(1) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) When the input voltage at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 25 mA to two.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax - TA )/θJA. In the 48-pin TQFP, θJA is 76°C/W, so PDMAX = 1,645 mW at 25°C and 855 mW at the maximum
operating ambient temperature of 85°C. Note that the power dissipation of this device under normal operation will typically be about 170
mW (150 mW quiescent power + 20 mW due to 1 LVTTL load on each digital output). The values for maximum power dissipation listed
above will be reached only when the ADC10D020 is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
(7) See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any
post 1986 Texas Instruments Linear Data Book, for other methods of soldering surface mount devices.
(1)(2)
Operating Ratings
Operating Temperature Range
−40°C ≤ TA ≤ +85°C
+2.7V to +3.6V
+1.5V to VD
VA, VD Supply Voltage
VDR Supply Voltage
VIN Differential Voltage Range
GAIN = Low
GAIN = High
GAIN = Low
GAIN = High
±VREF/2
±VREF
VCM Input Common Mode Range
VREF/4 to (VA–VREF/4)
VREF/2 to (VA–VREF/2)
VREF Voltage Range
0.8V to 1.5V
−0.3V to (VA +0.3V)
Digital Input Pins Voltage Range
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
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Converter Electrical Characteristics
The following specifications apply for VA = VD = VDR = +3.0 VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN (a.c.
coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected.
(1)
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C
.
Typical
Units
(Limits)
(3)
Symbol
Parameter
Conditions
Limits
(2)
STATIC CONVERTER CHARACTERISTICS
INL
Integral Non-Linearity
±0.65
±0.35
±1.8
LSB (max)
+1.2
−1.0
LSB (max)
LSB (min)
DNL
Differential Non-Linearity
Resolution with No Missing Codes
10
Bits
+10
−16
LSB (max)
LSB (min)
Without Offset Correction
With Offset Correction
−5
+0.5
−4
VOFF
GE
Offset Error
+2.0
−1.5
LSB (max)
LSB (min)
+6
−14
%FS (max)
%FS (min)
Gain Error
DYNAMIC CONVERTER CHARACTERISTICS
fIN = 1.0 MHz, VIN = FSR −0.1 dB
fIN = 4.7 MHz, VIN = FSR −0.1 dB
fIN = 9.5 MHz, VIN = FSR −0.1 dB
fIN = 19.5 MHz, VIN = FSR −0.1 dB
fIN = 1.0 MHz, VIN == FSR −0.1 dB
fIN = 4.7 MHz, VIN = FSR −0.1 dB
fIN = 9.5 MHz, VIN = FSR −0.1 dB
fIN = 19.5 MHz, VIN = FSR −0.1 dB
fIN = 1.0 MHz, VIN = FSR −0.1 dB
fIN = 4.7 MHz, VIN = FSR −0.1 dB
fIN = 9.5 MHz, VIN = FSR −0.1 dB
fIN = 19.5 MHz, VIN = FSR −0.1 dB
fIN = 1.0 MHz, VIN = FSR −0.1 dB
fIN = 4.7 MHz, VIN = FSR −0.1 dB
fIN = 9.5 MHz, VIN = FSR −0.1 dB
fIN = 19.5 MHz, VIN = FSR −0.1 dB
fIN = 1.0 MHz, VIN = FSR −0.1 dB
fIN = 4.7 MHz, VIN = FSR −0.1 dB
fIN = 9.5 MHz, VIN = FSR −0.1 dB
fIN = 19.5 MHz, VIN = FSR −0.1 dB
fIN = 1.0 MHz, VIN = FSR −0.1 dB
fIN = 4.7 MHz, VIN = FSR −0.1 dB
fIN = 9.5 MHz, VIN = FSR −0.1 dB
fIN = 19.5 MHz, VIN = FSR −0.1 dB
fIN = 1.0 MHz, VIN = FSR −0.1 dB
fIN = 4.7 MHz, VIN = FSR −0.1 dB
fIN = 9.5 MHz, VIN = FSR −0.1 dB
fIN = 19.5 MHz, VIN = FSR −0.1 dB
9.5
9.5
9.5
9.5
59
Bits
Bits (min)
Bits
Bits
dB
9.0
56
ENOB
Effective Number of Bits
59
dB (min)
dB
SINAD Signal-to-Noise Plus Distortion Ratio
59
59
dB
59
dB
59
56
dB (min)
dB
SNR
THD
HS2
Signal-to-Noise Ratio
Total Harmonic Distortion
Second Harmonic
59
59
dB
−73
−73
−73
−73
−84
−92
−87
−87
−80
−78
−78
−78
76
dB
−62
dB (min)
dB
dB
dB
dB
dB
dB
dB
dB
HS3
Third Harmonic
dB
dB
dB
75
dB
SFDR
Spurious Free Dynamic Range
75
dB
74
dB
(1) The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device.
However, errors in the A/D conversion can occur if the input goes beyond the limits given in these tables. See Figure 2
(2) Typical figures are at TJ = 25°C, and represent most likely parametric norms.
(3) Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Performance is ensured only at VREF = 1.0V and a clock duty
cycle of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are
performed and limits specified with clock low and high levels of 0.3V and VD − 0.3V, respectively.
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Converter Electrical Characteristics (continued)
The following specifications apply for VA = VD = VDR = +3.0 VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN (a.c.
coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected.
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1)
.
Typical
Units
(Limits)
(3)
Symbol
Parameter
Conditions
Limits
(2)
fIN1 < 4.9 MHz, VIN = FSR −6.1 dB
fIN2 < 5.1 MHz, VIN = FSR −6.1 dB
IMD
Intermodulation Distortion
65
dB
Overrange Output Code
Underrange Output Code
Full Power Bandwidth
(VIN+−VIN−) > 1.1V
(VIN+−VIN−) < −1.1V
1023
0
FPBW
140
MHz
dB
INTER-CHANNEL CHARACTERISTICS
1 MHz input to tested channel, 4.75 MHz input to
other channel
Crosstalk
−90
Channel - Channel Aperture Delay
Match
fIN = 8 MHz
8.5
ps
Channel - Channel Gain Matching
0.03
%FS
REFERENCE AND ANALOG CHARACTERISTICS
Gain Pin = AGND
Gain Pin = VA
Clock High
1
2
VP-P
VP-P
VIN
Analog Differential Input Range
6
pF
Analog Input Capacitance (each
input)
CIN
Clock Low
3
pF
RIN
Analog Differential Input Resistance
Reference Voltage
27
kΩ
0.8
1.5
V (min)
V (max)
µA
VREF
IREF
VCMO
1.0
<1
Reference Input Current
1.35
1.6
V (min)
V (max)
Common Mode Voltage Output
1 mA load to ground (sourcing current)
1.5
TC
VCMO
Common Mode Voltage Temperature
Coefficient
20
ppm/°C
DIGITAL INPUT CHARACTERISTICS
VIH
VIL
IIH
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
VD = +2.7V
VD = +3.6V
VIH = VD
2.0
0.5
V (min)
V (max)
µA
<1
IIL
VIL = DGND
>−1
µA
DIGITAL OUTPUT CHARACTERISTICS
VOH
VOL
Logical “1” Output Voltage
Logical “0” Output Voltage
VDR = +2.7V, IOUT = −0.5 mA
V
DR −0.3V
V (min)
V (max)
mA
VDR = +2.7V, IOUT = 1.6 mA
0.4
Parallel Mode
VOUT = 0V
−7
−14
7
+ISC
Output Short Circuit Source Current
Output Short Circuit Sink Current
Multiplexed Mode
mA
Parallel Mode
VOUT = VDR
mA
−ISC
Multiplexed Mode
14
mA
POWER SUPPLY CHARACTERISTICS
PD = LOW, STBY = LOW, dc input
PD = LOW, STBY = HIGH
47.6
8.8
55
mA (max)
mA
IA + ID
Core Supply Current
PD = HIGH, STBY = LOW or HIGH
0.22
mA
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Converter Electrical Characteristics (continued)
The following specifications apply for VA = VD = VDR = +3.0 VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN (a.c.
coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected.
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1)
.
Typical
Units
(Limits)
(3)
Symbol
Parameter
Conditions
Limits
1.4
(2)
PD = LOW, STBY = LOW, dc input
PD = LOW, STBY = HIGH
1.3
0.1
0.1
150
178
27
mA (max)
mA
Digital Output Driver Supply Current
IDR
(4)
PD = HIGH, STBY = LOW or HIGH
PD = LOW, STBY = LOW, dc input
PD = LOW, STBY = LOW, 1 MHz Input
PD = LOW, STBY = HIGH
mA
169
mW (max)
mW
PWR
Power Consumption
mW
PD = HIGH, STBY = LOW or HIGH
<1
mW
Change in Full Scale with 2.7V to 3.6V Supply
Change
PSRR1 Power Supply Rejection Ratio
PSRR2 Power Supply Rejection Ratio
90
52
dB
dB
Rejection at output with 20 MHz, 250 mVP-P
Riding on VA and VD
(4) IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output
pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR = VDR (CO x fO + C1 x f1
+ ... + C9 x f9) where VDR is the output driver power supply voltage, Cn is the total capacitance on the output pin, and fn is the average
frequency at which that pin is toggling.
AC Electrical Characteristics OS = Low (Multiplexed Mode)
The following specifications apply for VA = VD = VDR = +3.0VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS = 0V, VIN (a.c. coupled)
= FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected. Boldface
(1)
limits apply for TA = TMIN to TMAX: all other limits TA = 25°C
Units
(2)
(3)
Symbol
Parameter
Conditions
Typical
Limits
20
(Limits)
MHz (min)
MHz
1
fCLK
Maximum Clock Frequency
Minimum Clock Frequency
30
1
2
fCLK
30
70
% (min)
% (max)
Duty Cycle
50
Pipeline Delay (Latency)
I Data
2.5
3.0
Clock Cycles
Clock Cycles
ns
Q Data
tr, tf
tOC
Output Rise and Fall Times
Offset Correction Pulse Width
4
10
18
ns (min)
Output Delay from CLK Edge to Data
Valid
tOD
13
ns (max)
tDIQ
I/Q Output Delay
13
±200
2.4
<10
21
ns
ps
tSKEW
tAD
I/Q to Data Delay
Sampling (Aperture) Delay
Aperture Jitter
ns
tAJ
ps (rms)
ns
tVALID
Data Valid Time
Overrange Recovery Time
Differential VIN step from 1.5V to 0V
50
ns
PD Low to 1/2 LSB Accurate Conversion
(Wake-Up Time)
tWUPD
tWUSB
<1
ms
ns
STBY Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)
800
(1) The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device.
However, errors in the A/D conversion can occur if the input goes beyond the limits given in these tables. See Figure 2
(2) Typical figures are at TJ = 25°C, and represent most likely parametric norms.
(3) Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Performance is ensured only at VREF = 1.0V and a clock duty
cycle of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are
performed and limits specified with clock low and high levels of 0.3V and VD − 0.3V, respectively.
8
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AC Electrical Characteristics OS = High (Parallel Mode)
The following specifications apply for VA = +3.0 VDC, VD = +3.0 VDC, VDR = +3.0VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS =
3.0V, VIN (a.c. coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset
(1)
corrected. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C
Units
(2)
(3)
Symbol
Parameter
Conditions
Typical
Limits
20
(Limits)
MHz (min)
MHz
1
fCLK
Maximum Clock Frequency
Minimum Clock Frequency
30
1
2
fCLK
30
70
% (min)
% (max)
Duty Cycle
50
Pipeline Delay (Latency)
Output Rise and Fall Times
OC Pulse Width
2.5
Conv Cycles
tr, tf
toc
7
ns
ns
10
21
Output Delay from CLK Edge to Data
Valid
tOD
15
ns (max)
tDIQ
tAD
I/Q Output Delay
13
2.4
<10
43
ns
ns
Sampling (Aperture) Delay
Aperture Jitter
tAJ
ps (rms)
ns
tVALID
Data Valid Time
Overrange Recovery Time
Differential VIN step from 1.5V to 0V
50
ns
PD Low to 1/2 LSB Accurate Conversion
(Wake-Up Time)
tWUPD
tWUSB
<1
ms
ns
STBY Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)
800
(1) The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device.
However, errors in the A/D conversion can occur if the input goes beyond the limits given in these tables. See Figure 2
(2) Typical figures are at TJ = 25°C, and represent most likely parametric norms.
(3) Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Performance is ensured only at VREF = 1.0V and a clock duty
cycle of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are
performed and limits specified with clock low and high levels of 0.3V and VD − 0.3V, respectively.
Figure 2.
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Timing Diagrams
Figure 3. ADC10D020 Timing Diagram for Multiplexed Mode
Figure 4. ADC10D020 Timing Diagram for Parallel Mode
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Figure 5. AC Test Circuit
Specification Definitions
APERTURE (SAMPLING) DELAYis that time required after the fall of the clock input for the sampling switch to
open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode
tAD after the clock goes low.
APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input
noise.
CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is high to the total time of one clock
period.
CROSSTALK is coupling of energy from one channel into the other channel.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB. Measured at 20 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio, or SINAD. ENOB is defined as (SINAD − 1.76)/6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW) is the frequency at which the magnitude of the reconstructed output
fundamental drops 3 dB below its 1 MHz value.
GAIN ERRORis the difference between the ideal and actual differences between the input levels at which the
first and last code transitions occur. That is, how far this difference is from Full Scale.
INTEGRAL NON LINEARITY (INL) is a measure of the maximum deviation of each individual code from a line
drawn from zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the
last code transition). The deviation of any given code from this straight line is measured from the center of
that code value. The end point test method is used. Measured at 20 MSPS with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of spectral components that are not present in the
input as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is
defined as the ratio of the power in the second and third order intermodulation products to the total power
in one of the original frequencies. IMD is usually expressed in dB.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value of weight of all bits. This value is
m * VREF/2n
where
•
•
•
“m” is the reference scale factor
“n” is the ADC resolution, which is 10 in the case of the ADC10D020
The value of “m” is determined by the logic level at the gain pin and has a value of 1 when the gain pin
is at a logic low and a value of 2 when the gain pin is at a logic high.
(1)
MISSING CODES are those output codes that are skipped or will never appear at the ADC outputs. These
codes cannot be reached with any input value.
MSB (MOST SIGNIFICANT BIT)is the bit that has the largest value or weight. Its value is one half of full scale.
OFFSET ERROR is a measure of how far the mid-scale transition point is from the ideal zero voltage input.
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OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at
the output pins.
OVERRANGE RECOVERY TIME is the time required after the differential input voltages goes from 1.5V to 0V
for the converter to recover and make a conversion with its rated accuracy.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that
data is presented to the output driver stage. New data is available at every clock cycle, but the data output
lags the input by the Pipeline Delay plus the Output Delay.
POWER SUPPLY REJECTION RATIO (PSRR)can be one of two specifications. PSRR1 (DC PSRR) is the ratio
of the change in full scale gain error that results from a power supply voltage change from 2.7V to 3.6V.
PSRR2 (AC PSRR) is measured with a 20 MHz, 250 mVP-P signal riding upon the power supply and is the
ratio of the signal amplitude on the power supply pins to the amplitude of that frequency at the output.
PSRR is expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the fundamental signal at the
output to the rms value of the sum of all other spectral components below one-half the sampling
frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of
the fundamental signal at the output to the rms value of all of the other spectral components below half the
clock frequency, including harmonics but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
fundamental signal at the output and the peak spurious signal, where a spurious signal is any signal
present in the output spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD)is the ratio, expressed in dB, of the rms total of the first 9 harmonic
levels to the level of the input frequency. THD is calculated as
where
•
•
f1 is the RMS power of the fundamental (output) frequency
f2 through f10 are the RMS power of the first 9 harmonic frequencies in the output spectrum
(2)
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Typical Performance Characteristics
VA = VD = VDR = 3.0V, fCLK = 20 MHz, unless otherwise specified
INL
vs.
Typical INL
Supply Voltage
Figure 6.
Figure 7.
INL
vs.
VREF
INL
vs.
fCLK
Figure 8.
Figure 9.
INL
vs.
INL
vs.
Temperature
Clock Duty Cycle
Figure 10.
Figure 11.
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Typical Performance Characteristics (continued)
VA = VD = VDR = 3.0V, fCLK = 20 MHz, unless otherwise specified
DNL
vs.
Supply Voltage
Typical DNL
Figure 12.
Figure 13.
DNL
vs.
VREF
DNL
vs.
fCLK
Figure 14.
Figure 15.
DNL
vs.
Clock Duty Cycle
DNL
vs.
Temperature
Figure 16.
Figure 17.
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Typical Performance Characteristics (continued)
VA = VD = VDR = 3.0V, fCLK = 20 MHz, unless otherwise specified
SNR
SNR
vs.
vs.
Supply Voltage
@ fIN = 1 MHz to 9.5 MHz
VREF
@ fIN = 4.7 MHz
Figure 18.
Figure 19.
SNR
vs.
SNR
vs.
fIN
fCLK @ fIN = 9.5 MHz
Figure 20.
Figure 21.
SNR
vs.
Clock Duty Cycle
@ fIN = 4.7 MHz
SNR
vs.
VDR @ fIN = 9.5 MHz
Figure 22.
Figure 23.
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Typical Performance Characteristics (continued)
VA = VD = VDR = 3.0V, fCLK = 20 MHz, unless otherwise specified
SNR
SNR
vs.
vs.
VCM @ fIN = 9.5 MHz
Temperature @ fIN = 1 MHz to 9.5 MHz
Figure 24.
Figure 25.
SINAD & ENOB
vs.
Supply Voltage @ fIN = 1 MHz
to 9.5 MHz
SINAD & ENOB
vs.
VREF @ fIN = 4.7 MHz
Figure 26.
Figure 27.
SINAD & ENOB
vs.
@ fCLK (fIN = 9.5 MHz)
SINAD & ENOB
vs.
fIN
Figure 28.
Figure 29.
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Typical Performance Characteristics (continued)
VA = VD = VDR = 3.0V, fCLK = 20 MHz, unless otherwise specified
SINAD & ENOB
SINAD & ENOB
vs.
VDR @ fIN = 9.5 MHz
vs.
Clock Duty Cycle @ fIN = 4.7 MHz
Figure 30.
Figure 31.
SINAD & ENOB
SINAD & ENOB
vs.
VCM @ fIN = 9.5 MHz
vs.
Temperature @ fIN = 1 MHz to
9.5 MHz
Figure 32.
Figure 33.
Distortion
vs.
Supply Voltage @ fIN = 4.7 MHz
Distortion
vs.
VREF @ fIN = 4.7 MHz
Figure 34.
Figure 35.
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Typical Performance Characteristics (continued)
VA = VD = VDR = 3.0V, fCLK = 20 MHz, unless otherwise specified
Distortion
Distortion
vs.
vs.
fIN
fCLK @ fIN = 9.5 MHz
Figure 36.
Figure 37.
Distortion
vs.
Clock Duty Cycle @ fIN = 4.7 MHz
Distortion
vs.
VDR @ fIN = 4.7 MHz
Figure 38.
Figure 39.
Distortion
vs.
VCM @ fIN = 4.7 MHz
Distortion
vs.
Temperature
Figure 40.
Figure 41.
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Typical Performance Characteristics (continued)
VA = VD = VDR = 3.0V, fCLK = 20 MHz, unless otherwise specified
SFDR
SFDR
vs.
VREF @ fIN = 4.7 MHz
vs.
Supply Voltage @ fIN = 4.7 MHz
Figure 42.
Figure 43.
SFDR
vs.
fCLK @ fIN = 9.5 MHz
SFDR
vs.
fIN
Figure 44.
Figure 45.
SFDR
SFDR
vs.
VDR @ fIN = 4.7 MHz
vs.
Clock Duty Cycle @ fIN = 4.7 MHz
Figure 46.
Figure 47.
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Typical Performance Characteristics (continued)
VA = VD = VDR = 3.0V, fCLK = 20 MHz, unless otherwise specified
SFDR
SFDR
vs.
vs.
VCM @ fIN = 4.7 MHz
Temperature @ fIN = 4.7 MHz
Figure 48.
Figure 49.
Crosstalk
Crosstalk
vs.
VDR @ fIN = 4.7 MHz
vs.
fIN
Figure 50.
Figure 51.
Crosstalk
vs.
VCM @ fIN = 4.7 MHz
Crosstalk
vs.
Temperature
Figure 52.
Figure 53.
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Typical Performance Characteristics (continued)
VA = VD = VDR = 3.0V, fCLK = 20 MHz, unless otherwise specified
Power Consumption
vs.
Temperature
Spectral Response @ fIN = 1 MHz
Figure 54.
Figure 55.
Spectral Response @ fIN = 4.7 MHz
Spectral Response @ fIN = 9.5 MHz
Figure 56.
Figure 57.
Spectral Response @ fIN = 21 MHz
Spectral Response @ fIN = 49 MHz
Figure 58.
Figure 59.
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Typical Performance Characteristics (continued)
VA = VD = VDR = 3.0V, fCLK = 20 MHz, unless otherwise specified
Spectral Response @ fIN = 99 MHz
IMD Response @ fIN = 4.9 MHz, 5.1 MHz
Figure 60.
Figure 61.
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FUNCTIONAL DESCRIPTION
Using a subranging architecture, the ADC10D020 achieves 9.5 effective bits over the entire Nyquist band at 20
MSPS while consuming just 150 mW. The use of an internal sample-and-hold amplifier (SHA) not only enables
this sustained dynamic performance, but also lowers the converter's input capacitance and reduces the number
of external components required.
Analog signals at the “I” and “Q” inputs that are within the voltage range set by VREF and the GAIN pin are
digitized to ten bits at up to 30 MSPS. VREF has a range of 0.8V to 1.5V providing a differential peak-to-peak
input range of 0.8 VP-P to 1.5 VP-P with the GAIN pin at a logic low, or an input range of 1.6 VP-P to 3.0 VP-P with
the GAIN pin at a logic high. Differential input voltages less than −VREF/2 with the GAIN pin low, or less than
−VREF with the GAIN pin high will cause the output word to indicate a negative full scale. Differential input
voltages greater than VREF/2 with the GAIN pin low, or greater than VREF with the GAIN pin high, will cause the
output word to indicate a positive full scale.
Both “I” and “Q” channels are sampled simultaneously on the falling edge of the clock input, while the timing of
the data output depends upon the mode of operation.
In the parallel mode, the “I” and “Q” output busses contain the conversion result for their respective inputs. The
“I” and “Q” channel data are present and valid at the data output pins tOD after the rising edge of the input clock.
In the multiplexed mode, “I” channel data is available at the digital outputs tOD after the rise of the clock edge,
while the “Q” channel data is available at the digital outputs tOD after the fall of the clock. However, a delayed I/Q
output signal should be used to latch the output for best, most consistent results.
Data latency in the parallel mode is 2.5 clock cycles. In the multiplexed mode data latency is 2.5 clock cycles for
the “I” channel and 3.0 clock cycles for the “Q” channel. The ADC10D020 will convert as long as the clock signal
is present and the PD and STBY pins are low.
Throughout this discussion, VCM refers to the Common Mode input voltage of the ADC10D020 while VCMO refers
to its Common Mode output voltage.
Applications Information
THE ANALOG SIGNAL INPUTS
Each of the analog inputs of the ADC10D020 consists of a switch (transmission gate) followed by a switched
capacitor amplifier. The capacitance seen at each input pin changes with the clock level, appearing as about 3
pF when the clock is low, and about 6 pF when the clock is high. A switched capacitance is harder to drive than
is a larger, fixed capacitance.
The CLC409 and the CLC428 dual op amp have been found to be a good amplifiers to drive the ADC10D020
because of their wide bandwidth and low distortion. They also have good Differential Gain and Differential Phase
performance.
Care should be taken to avoid driving the inputs beyond the supply rails, even momentarily, as during power-up.
The ADC10D020 is designed for differential input signals for best performance. With a 1.0V reference and the
GAIN pin at a logic low, differential input signals up to 1.0 VP-P are digitized. See Figure 62. For differential
signals, the input common mode is expected to be about 1.5V, but the inputs are not sensitive to the common-
mode voltage and can be anywhere within the supply rails (ground to VA) with little or no performance
degradation, as long as the signal swing at the individual input pins is no more than 300 mV beyond the supply
rails. For single ended drive, operate the ADC10D020 with the GAIN pin at a logic low, connect one pin of the
input pair to 1.5V (VCM) and drive the other pin of the input pair with 1.0 VP-P centered around 1.5V.
Because of the larger signal swing at one input for single-ended operation, distortion performance will not be as
good as with a differential input signal. Alternatively, single-ended to differential conversion with a transformer
provides a quick. easy solution for those applications not requiring response to dc and low frequencies. See
Figure 63. The 36Ω resistors and 110 pF capacitor values are chosen to provide a cutoff frequency near the
clock frequency to compensate for the effects of input sampling. A lower time constant should be used for
undersampling applications.
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The ADC10D020 is designed for use with differential signals of 1.0 VP-P with a common mode voltage of 1.5V. The
signal swing should not cause any pin to experience a swing more than 300 mV beyond the supply rails.
Figure 62.
REFERENCE INPUTS
The VRP and VRN pins should each be bypassed with a 5 µF (or larger) tantalum or electrolytic capacitor and a
0.1 µF ceramic capacitor. Use these pins only for bypassing. DO NOT connect anything else to these pins.
Figure 64 shows a simple reference biasing scheme with minimal components. While this circuit will suffice for
many applications, the value of the reference voltage will depend upon the supply voltage.
The circuit of Figure 65 is an improvement over the circuit of Figure 64 because the reference voltage is
independent of supply voltage. This reduces problems of reference voltage variability. The reference voltage at
the VREF pin should be bypassed to AGND with a 5 µF (or larger) tantalum or electrolytic capacitor and a 0.1 µF
ceramic capacitor.
The circuit of Figure 66 may be used if it is desired to obtain a precise reference voltage not available with a
fixed reference source. The 240Ω and 1k resistors can be replaced with a potentiometer, if desired.
Use of an input transformer for single-ended to differential conversion can simplify circuit design for single-ended
signals.
Figure 63.
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Figure 64. Simple Reference Biasing
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Figure 65. Improved Low Component Count Reference Biasing
The VCMO output can be used as the ADC reference source as long as care is taken to prevent excessive loading
of this pin. However, the VCMO output was not designed to be a precision reference and has more variability than
does a precision reference. Refer to VCMO, Common Mode Voltage Output, in Electrical Characteristics. Since
the reference input of the ADC10D020 is buffered, there is virtually no loading on the VCMO output by the VREF
pin. While the ADC10D020 will work with a 1.5V reference voltage, it is fully specified for a 1.0V reference. To
use the VCMO for a reference voltage at 1.0V, the 1.5V VCMO output needs to be divided down. The divider
resistor values need to be carefully chosen to prevent excessive VCMO loading. See Figure 67. While the average
temperature coefficient of VCMO is 20 ppm/°C, that temperature coefficient can be broken down to a typical 50
ppm/°C between −40°C and +25°C and a typical −12 ppm/°C between +25°C and +85°C.
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Figure 66. Setting An Accurate Reference Voltage
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The VCMO output pin may be used as an internal reference source if its output is divided down and not loaded
excessively.
Figure 67.
REFERENCE VOLTAGE
The reference voltage should be within the range specified in the Operating Ratings (0.8V to 1.5V). A reference
voltage that is too low could result in a noise performance that is less than desired because the quantization level
falls below other noise sources. On the other hand, a reference voltage that is too high means that an input
signal that produces a full scale output uses such a large input range that the input stage is less linear, resulting
in a degradation of distortion performance. Also, for large reference voltages, the internal ladder buffer runs out
of head-room, leading to a reduction of gain in that buffer and causing gain error degradation.
The Reference bypass pins VRP and VRN are output compensated and should each be bypassed with a parallel
combination of a 5 µF (minimum) and 0.1 µF capacitors.
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As mentioned in the previous section, the VCMO output can be used as the ADC reference.
VCMO OUTPUT
The VCMO output pin is intended to provide a common mode bias for the differential input pins of the
ADC10D020. It can also be used as a voltage reference source. Care should be taken, however, to avoid loading
this pin with more than 1 mA. A load greater than this could result in degraded long term and temperature
stability of this voltage. The VCMO pin is output compensated and should be bypassed with a 2 µF/0.1 µF
combination, minimum. See REFERENCE INPUTS for more information on using the VCMO output as a reference
source.
DIGITAL INPUT PINS
The seven digital input pins are used to control the function of the ADC10D020.
CLOCK (CLK) INPUT
The clock (CLK) input is common to both A/D converters. This pin is CMOS/LVTTL compatible with a threshold
of about VA/2. Although the ADC10D020 is tested and its performance is specified with a 20 MHz clock, it
typically will function well with low-jitter clock frequencies from 1 MHz to 30 MHz. The clock source should be
series terminated to match the source impedance with the characteristic impedance, ZO, of the clock line and the
ADC clock pin should be AC terminated, near the clock input, with a series RC to ground. The resistor value
should equal the characteristic impedance, ZO, of the clock line and the capacitor should have a value such that
C × ZO ≥ 4 × tPD, where tPD is the time of propagation of the clock signal from its source to the ADC clock pin.
The typical propagation rate on a board of FR4 material is about 150 ps/inch. The rise and fall times of the clock
supplied to the ADC clock pin should be no more than 4 ns. The analog inputs I = (I+) – (I−) and Q = (Q+) – (Q−)
are simultaneously sampled on the falling edge of this input to ensure the best possible aperture delay match
between the two channels.
OUTPUT BUS SELECT (OS) PIN
The Output Bus Select (OS) pin determines whether the ADC10D020 is in the parallel or multiplexed mode of
operation. A logic high at this pin puts the device into the parallel mode of operation where “I” and “Q” data
appear at their respective output buses. A logic low at this pin puts the device into the multiplexed mode of
operation where the “I” and “Q” data are multiplexed onto the “I” output bus and the “Q” output lines all remain at
a logic low.
OFFSET CORRECT (OC) PIN
The Offset Correct (OC) pin is used to initiate an offset correction sequence. This procedure should be done
after power up and need not be performed again unless power to the ADC10D020 is interrupted. An independent
offset correction sequence for each converter is initiated when there is a low-to-high transition at the OC pin. This
sequence takes 34 clock cycles to complete, during which time 32 conversions are taken and averaged. The
result is subtracted from subsequent conversions. Because the offset correction is performed digitally at the
output of the ADC, the output range of the ADC is reduced by the offset amount.
Upon power up, the offset correction coefficients are set to zero. The Electrical Table indicates the Offset Error
with and without performing an offset correction.
Each input pair should have a 0V differential voltage value during this entire 34 clock period, but the “I” and “Q”
input common mode voltages do not have to be equal to each other. Because of the uncertainty as to exactly
when the correction sequence starts, it is best to allow 35 clock periods for this sequence.
OUTPUT FORMAT (OF) PIN
The Output Format (OF) pin provides a choice of offset binary or 2's complement output formatting. With this pin
at a logic low, the output format is offset binary. With this pin at a logic high, the output format is 2's complement.
STANDBY (STBY) PIN
The Standby (STBY) pin may be used to put the ADC10D020 into a low power mode where it consumes just 27
mW and can quickly be brought to full operation. In this mode, most of the ADC10D020 is powered down, but the
bias and reference circuitry remained powered up to allow for a faster recovery from a low power standby
condition. The device operates normally with a logic low on this and the PD pins.
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While in the Standby mode the data outputs contain the results of the last conversion before going into this
Mode.
POWER DOWN (PD) PIN
The Power Down (PD) pin puts the device into a low-power “sleep” state where it consumes less than 1 mW
when the PD pin is at a logic high. Power consumption is reduced more when the PD pin is high than when the
STBY pin is high, but recovery to full operation is much quicker from the standby state than it is from the power
down state. When the STBY and PD pins are both high, the ADC10D020 is in the power down mode.
While in the Power Down mode the data outputs contain the results of the last conversion before going into this
mode.
GAIN PIN
The GAIN pin sets the internal signal gain of the “I” and “Q” inputs. With this pin at a logic low, the full scale
differential peak-to-peak input signal is equal to VREF. With the GAIN pin at a logic high, the full scale differential
peak-to-peak input signal is equal to 2 times VREF
.
INPUT/OUTPUT RELATIONSHIP ALTERNATIVES
The GAIN pin of the ADC10D020 offers input range selection, while the OF pin offers a choice of offset binary or
2's complement output formatting.
The relationship between the GAIN, OF, analog inputs and the output code are as defined in Table 1. Keep in
mind that the input signals must not exceed the power supply rails.
Table 1. ADC10D020 Input/Output Relationships
GAIN
OF
0
I+ / Q+
VCM + 0.25*VREF
VCM
I− / Q−
CM − 0.25*VREF
VCM
Output Code
11 1111 1111
10 0000 0000
00 0000 0000
01 1111 1111
00 0000 0000
10 0000 0000
11 1111 1111
10 0000 0000
00 0000 0000
01 1111 1111
00 0000 0000
10 0000 0000
0
0
0
0
0
0
1
1
1
1
1
1
V
0
0
VCM − 0.25*VREF
VCM + 0.25*VREF
1
VCM + 0.25*VREF
VCM
VCM − 0.25*VREF
1
VCM
1
VCM − 0.25*VREF
VCM + 0.25*VREF
0
VCM + 0.5*VREF
VCM
VCM − 0.5*VREF
0
VCM
0
VCM − 0.5*VREF
VCM + 0.5*VREF
1
VCM + 0.5*VREF
VCM
VCM − 0.5*VREF
1
VCM
1
VCM − 0.5*VREF
VCM + 0.5*VREF
POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A
10 µF to 50 µF tantalum or aluminum electrolytic capacitor should be placed within half an inch (1.2 centimeters)
of the A/D power pins, with a 0.1 µF ceramic chip capacitor placed as close as possible to each of the
converter's power supply pins. Leadless chip capacitors are preferred because they have low lead inductance.
While a single voltage source should be used for the analog and digital supplies of the ADC10D020, these
supply pins should be well isolated from each other to prevent any digital noise from being coupled to the analog
power pins. A choke is recommended between the VA and VD supply lines. VDR should have a separate supply
from VA and VD to avoid noise coupling.
The VDR pins are completely isolated from the other supply pins. Because of this isolation, a separate supply can
be used for these pins. This VDR supply can be significantly lower than the three volts used for the other supplies,
easing the interface to lower voltage digital systems. Using a lower voltage for this supply can also reduce the
power consumption and noise associated with the output drivers.
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The converter digital supply should not be the supply that is used for other digital circuitry on the board. It should
be the same supply used for the ADC10D020 analog supply.
As is the case with all high speed converters, the ADC10D020 should be assumed to have little high frequency
power supply rejection. A clean analog power source should be used.
No pin should ever have a voltage on it that is more than 300 mV in excess of the supply voltages or below
ground, not even on a transient basis. This can be a problem upon application of power to a circuit and upon turn
off of the power source. Be sure that the supplies to circuits driving the CLK, or any other digital or analog inputs
do not come up any faster than does the voltage at the ADC10D020 power pins.
LAYOUT AND GROUNDING
Proper routing of all signals and proper ground techniques are essential to ensure accurate conversion. Separate
analog and digital ground planes may be used if adequate care is taken with signal routing, but may result in
EMI/RFI. A single ground plane with proper component placement will yield good results while minimizing
EMI/RFI.
Analog and digital ground current paths should not coincide with each other as the common impedance will
cause digital noise to be added to analog signals. Accordingly, traces carrying digital signals should be kept as
far away from traces carrying analog signals as is possible. Power should be routed with traces rather than the
use of a power plane. The analog and digital power traces should be kept well away from each other. All power
to the ADC10D020, except VDR, should be considered analog. The DR GND pin should be considered a digital
ground and not be connected to the ground plane in close proximity with the other ground pins of the
ADC10D020.
Each bypass capacitor should be located as close to the appropriate converter pin as possible and connected to
the pin and the appropriate ground plane with short traces. The analog input should be isolated from noisy signal
traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor)
connected between the converter's input and ground should be connected to a very clean point in the ground
return.
The clock line should be properly terminated, as discussed in CLOCK (CLK) INPUT, and be as short as possible.
Figure 68 gives an example of a suitable layout and bypass capacitor placement. All analog circuitry (input
amplifiers, filters, reference components, etc.) and interconnections should be placed in an area reserved for
analog circuitry. All digital circuitry and I/O lines should be placed in an area reserved for digital circuitry.
Violating these rules can result in digital noise getting into the analog circuitry, which will degrade accuracy and
dynamic performance (THD, SNR, SINAD).
Figure 68. An Acceptable Layout Pattern
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DYNAMIC PERFORMANCE
The ADC10D020 is a.c. tested and its dynamic performance is ensured. To meet the published specifications,
the clock source driving the CLK input must be free of jitter. For best dynamic performance, isolating the ADC
clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 69.
Figure 69. Isolating the ADC Clock from Digital Circuitry
COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, no input should
go more than 300 mV beyond the supply pins. Exceeding these limits on even a transient basis can cause faulty
or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC devices) to exhibit
overshoot and undershoot that goes a few hundred millivolts beyond the supply rails. A resistor of 50Ω to 100Ω
in series with the offending digital input, close to the source, will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the ADC10D020 (or any device) with a device that is
powered from supplies outside the range of the ADC10D020 supply. Such practice may lead to conversion
inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers have to
charge for each conversion, the more instantaneous digital current is required from VDR and DR GND. These
large charging current spikes can couple into the analog section, degrading dynamic performance. Adequate
bypassing and attention to board layout will reduce this problem. Buffering the digital data outputs (with a
74ACTQ841, for example) may be necessary if the data bus to be driven is heavily loaded. Dynamic
performance can also be improved by adding series resistors of 47Ω to 56Ω at each digital output, close to the
ADC output pins.
Using a clock source with excessive jitter. This will cause the sampling interval to vary, causing excessive
output noise and a reduction in SNR and SINAD performance. The use of simple gates with RC timing as a clock
source is generally inadequate.
Using the same voltage source for VD and external digital logic. As mentioned in CLOCK (CLK) INPUT, VD
should use the same power source used by VA and other analog components, but should be decoupled from VA.
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 32
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC10D020CIVS/NOPB
ACTIVE
TQFP
PFB
48
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
10D020
CIVS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
ADC10D020CIVS/NOPB
PFB
TQFP
48
250
10 x 25
150
315 135.9 7620 12.2
11.1 11.25
Pack Materials-Page 1
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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