ADC104S021Q-Q1 [TI]
汽车类、4 通道、50ksps 至 200ksps、10 位模数转换器;
| 型号： | ADC104S021Q-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类、4 通道、50ksps 至 200ksps、10 位模数转换器 转换器 模数转换器 |
| 文件： | 总29页 (文件大小：1164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC104S021
www.ti.com
SNAS278H –FEBRUARY 2005–REVISED MARCH 2013
ADC104S021/ADC104S021Q 4-Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter
Check for Samples: ADC104S021
1
FEATURES
DESCRIPTION
The ADC104S021/ADC104S021Q is a low-power,
four-channel CMOS 10-bit analog-to-digital converter
2
•
Specified over a Range of Sample Rates.
Four Input Channels
•
•
•
•
with
conventional practice of specifying performance at a
single sample rate only, the
a high-speed serial interface. Unlike the
Variable Power Management
Single Power Supply with 2.7V - 5.25V Range
ADC104S021/ADC104S021Q is fully specified over a
sample rate range of 50 ksps to 200 ksps. The
converter is based on a successive-approximation
register architecture with an internal track-and-hold
circuit. It can be configured to accept up to four input
signals at inputs IN1 through IN4.
ADC104S021Q is AEC-Q100 Grade 3 Qualified
and is Manufactured on an Automotive Grade
Flow
•
Meets AEC-Q100-011 C2 CDM Classification
APPLICATIONS
The output serial data is straight binary, and is
compatible with several standards, such as SPI™,
QSPI™, MICROWIRE, and many common DSP
serial interfaces.
•
•
•
•
Portable Systems
Remote Data Acquisition
Instrumentation and Control Systems
Automotive
The ADC104S021/ADC104S021Q operates with a
single supply, that can range from +2.7V to +5.25V.
Normal power consumption using a +3V or +5V
supply is 1.94 mW and 6.9 mW, respectively. The
power-down feature reduces the power consumption
to just 0.12 µW using a +3V supply, or 0.47 µW using
a +5V supply.
KEY SPECIFICATIONS
•
•
•
•
DNL: ± 0.13 LSB (typ)
INL: ± 0.13 LSB (typ)
SNR: 61.8 dB (typ)
Power Consumption
The ADC104S021/ADC104S021Q is packaged in a
10-lead VSSOP package. Operation over the
industrial temperature range of −40°C to +85°C is
ensured.
–
–
3V Supply: 1.94 mW (typ)
5V Supply: 6.9 mW (typ)
Table 1. Pin-Compatible Alternatives by Resolution and Speed(1)
Resolution
Specified for Sample Rate Range of:
200 to 500 ksps
50 to 200 ksps
500 ksps to 1 Msps
ADC124S101
12-bit
10-bit
8-bit
ADC124S021
ADC104S021/ADC104S021Q
ADC084S021
ADC124S051
ADC104S051
ADC104S101
ADC084S051
ADC084S101
(1) All devices are fully pin and function compatible.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
ADC104S021
SNAS278H –FEBRUARY 2005–REVISED MARCH 2013
www.ti.com
Connection Diagram
10
9
CS
1
2
3
4
5
SCLK
DOUT
DIN
V
A
ADC104S021/
GND
IN4
8
ADC104S021Q
7
6
IN1
IN3
IN2
Figure 1. 10-Lead VSSOP
See DGK Package
Block Diagram
IN1
10-Bit
SUCCESSIVE
APPROXIMATION
ADC
V
.
.
.
A
MUX
T/H
GND
GND
IN4
SCLK
CS
CONTROL
LOGIC
DIN
DOUT
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin No.
ANALOG I/O
4-7
Symbol
Description
IN1 to IN4
Analog inputs. These signals can range from 0V to VA.
DIGITAL I/O
10
SCLK
DOUT
Digital clock input. This clock directly controls the conversion and readout processes.
Digital data output. The output samples are clocked out of this pin on falling edges of the
SCLK pin.
9
8
Digital data input. The ADC104S021/ADC104S021Q's Control Register is loaded through
this pin on rising edges of the SCLK pin.
DIN
CS
Chip select. On the falling edge of CS, a conversion process begins. Conversions continue
as long as CS is held low.
1
POWER SUPPLY
Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and
bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1
cm of the power pin.
2
3
VA
GND
The ground return for supply and signals.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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(1)(2)(3)
Absolute Maximum Ratings
Supply Voltage VA
−0.3V to 6.5V
−0.3V to VA +0.3V
±10 mA
Voltage on Any Pin to GND
(4)
Input Current at Any Pin
Package Input Current(4)
±20 mA
(5)
Power Consumption at TA = 25°C
See
(6)
ESD Susceptibility
Human Body Model
Machine Model
Charged Device Model
2500V
250V
500V
Junction Temperature
Storage Temperature
+150°C
−65°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to
10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the VA pin. The current into the VA pin is
limited by the Analog Supply Voltage specification.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation listed above will be reached only when the device is operated
in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is
reversed). Obviously, such conditions should always be avoided.
(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms.
(1)(2)
Operating Ratings
Operating Temperature Range
−40°C ≤ TA ≤ +85°C
+2.7V to +5.25V
−0.3V to VA
VA Supply Voltage
Digital Input Pins Voltage Range
Clock Frequency
50 kHz to 16 MHz
0V to VA
Analog Input Voltage
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
Package Thermal Resistance
Package
θJA
10-lead VSSOP
190°C / W
Soldering process must comply with Reflow Temperature Profile specifications. Refer to http://www.ti.com/packaging.(1)
(1) Reflow temperature profiles are different for lead-free and non-lead-free packages.
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(1)(2)
ADC104S021/ADC104S021Q Converter Electrical Characteristics
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50
ksps to 200 ksps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
(3)
Symbol
Parameter
Conditions
Typical
Limits
Units
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
10
Bits
+0.3
−0.4
±0.4
±0.4
±0.5
±0.7
LSB (max)
LSB (min)
LSB (max)
LSB (max)
LSB (max)
LSB (max)
INL
Integral Non-Linearity
±0.13
DNL
VOFF
OEM
FSE
Differential Non-Linearity
Offset Error
±0.13
+0.1
Channel to Channel Offset Error Match
Full-Scale Error
±0.02
−0.1
Channel to Channel Full-Scale Error
Match
FSEM
+0.02
±0.5
LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
VA = +2.7 to 5.25V
fIN = 39.9 kHz, −0.02 dBFS
SINAD
SNR
Signal-to-Noise Plus Distortion Ratio
Signal-to-Noise Ratio
61.8
61.8
−86
82
61
61.3
−72
75
dB (min)
dB (min)
dB (max)
dB (min)
Bits (min)
dB
VA = +2.7 to 5.25V
fIN = 39.9 kHz, −0.02 dBFS
VA = +2.7 to 5.25V
fIN = 39.9 kHz, −0.02 dBFS
THD
Total Harmonic Distortion
VA = +2.7 to 5.25V
fIN = 39.9 kHz, −0.02 dBFS
SFDR
ENOB
Spurious-Free Dynamic Range
Effective Number of Bits
VA = +2.7 to 5.25V
fIN = 39.9 kHz, −0.02 dBFS
9.9
9.8
VA = +5.25V
fIN = 39.9 kHz
Channel-to-Channel Crosstalk
−87
−82
−81
Intermodulation Distortion, Second
Order Terms
VA = +5.25V
fa = 40.161 kHz, fb = 41.015 kHz
dB
IMD
Intermodulation Distortion, Third Order
Terms
VA = +5.25V
fa = 40.161 kHz, fb = 41.015 kHz
dB
VA = +5V
VA = +3V
11
8
MHz
MHz
FPBW
-3 dB Full Power Bandwidth
ANALOG INPUT CHARACTERISTICS
VIN
Input Range
0 to VA
V
µA (max)
pF
IDCL
DC Leakage Current
±1
Track Mode
Hold Mode
33
3
CINA
Input Capacitance
pF
DIGITAL INPUT CHARACTERISTICS
VA = +5.25V
VA = +3.6V
2.4
2.1
0.8
±10
4
V (min)
V (min)
VIH
Input High Voltage
VIL
Input Low Voltage
Input Current
V (max)
µA (max)
pF (max)
IIN
VIN = 0V or VA
±0.1
2
CIND
Digital Input Capacitance
DIGITAL OUTPUT CHARACTERISTICS
ISOURCE = 200 µA
ISOURCE = 1 mA
ISINK = 200 µA
ISINK = 1 mA
V
A − 0.03
V
A − 0.5
V (min)
VOH
Output High Voltage
Output Low Voltage
V
A − 0.1
0.03
0.1
V
V (max)
V
0.4
VOL
(1) Min/max specification limits are specified by design, test, or statistical analysis.
(2) PPAP (Production part Approval Process) documentation of the device technology, process and qualification is available from Texas
Instruments upon request.
(3) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
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ADC104S021/ADC104S021Q Converter Electrical Characteristics (1)(2) (continued)
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50
ksps to 200 ksps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
(3)
Symbol
Parameter
Conditions
Typical
±0.01
2
Limits
Units
IOZH, IOZL TRI-STATE® Leakage Current
±1
4
µA (max)
pF (max)
COUT
TRI-STATE® Output Capacitance
Output Coding
Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)
2.7
V (min)
VA
Supply Voltage
5.25
V (max)
VA = +5.25V,
fSAMPLE = 200 ksps, fIN = 40 kHz
1.3
0.55
90
1.8
0.7
mA (max)
Supply Current, Normal Mode
(Operational, CS low)
VA = +3.6V,
fSAMPLE = 200 ksps, fIN = 40 kHz
mA (max)
IA
VA = +5.25V,
fSAMPLE = 0 ksps
nA
nA
Supply Current, Shutdown (CS high)
VA = +3.6V,
fSAMPLE = 0 ksps
32
VA = +5.25V
VA = +3.6V
VA = +5.25V
VA = +3.6V
6.9
9.5
2.5
mW (max)
mW (max)
µW
Power Consumption, Normal Mode
(Operational, CS low)
1.94
0.47
0.12
PD
Power Consumption, Shutdown (CS
high)
µW
AC ELECTRICAL CHARACTERISTICS
0.8
3.2
50
200
13
30
70
3
MHz (min)
MHz (max)
ksps (min)
ksps (max)
SCLK cycles
% (min)
(4)
(4)
fSCLK
Clock Frequency
fS
Sample Rate
tCONV
DC
Conversion Time
SCLK Duty Cycle
fSCLK = 3.2 MHz
50
% (max)
tACQ
Track/Hold Acquisition Time
Throughput Time
Full-Scale Step Input
SCLK cycles
SCLK cycles
Acquisition Time + Conversion Time
16
(4) This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is
specified under Operating Ratings.
ADC104S021/ADC104S021Q Timing Specifications(1)
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50
ksps to 200 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
(2)
Symbol
Parameter
Conditions
VA = +3.0V
Typical
−3.5
−0.5
+4.5
+1.5
+4
Limits
10
Units
(3)
(3)
tCSU
Setup Time SCLK High to CS Falling Edge
ns (min)
VA = +5.0V
VA = +3.0V
VA = +5.0V
VA = +3.0V
VA = +5.0V
VA = +3.0V
VA = +5.0V
tCLH
Hold time SCLK Low to CS Falling Edge
Delay from CS Until DOUT active
10
30
ns (min)
ns (max)
tEN
+2
+16.5
+15
tACC
tSU
Data Access Time after SCLK Falling Edge
Data Setup Time Prior to SCLK Rising Edge
30
10
ns (max)
ns (min)
+3
(1) PPAP (Production part Approval Process) documentation of the device technology, process and qualification is available from Texas
Instruments upon request.
(2) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(3) Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.
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ADC104S021/ADC104S021Q Timing Specifications(1) (continued)
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50
ksps to 200 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
(2)
Symbol
tH
Parameter
Data Valid SCLK Hold Time
Conditions
Typical
Limits
10
Units
+3
ns (min)
tCH
SCLK High Pulse Width
SCLK Low Pulse Width
0.5 x tSCLK 0.3 x tSCLK ns (min)
tCL
0.5 x tSCLK 0.3 x tSCLK ns (min)
VA = +3.0V
1.7
1.2
Output Falling
Output Rising
VA = +5.0V
VA = +3.0V
VA = +5.0V
tDIS
CS Rising Edge to DOUT High-Impedance
20
ns (max)
1.0
1.0
Timing Diagrams
Figure 2. Timing Test Circuit
Power Down
Power Up
Power Up
Hold
Track
Hold
10
Track
CS
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
SCLK
Control register
b4 b3 b2
Control register
b4 b3
b7
b6
b5
b2
b1
b0
b7
b6
b5
b1
b0
DIN
DOUT
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB9 DB8 DB7 DB6 DB5
Figure 3. ADC104S021/ADC104S021Q Operational Timing Diagram
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Figure 4. ADC104S021/ADC104S021Q Serial Timing Diagram
CS
t
CSU
SCLK
t
CLH
SCLK
Figure 5. SCLK and CS Timing Parameters
Specification Definitions
ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold
capacitor to charge up to the input voltage.
APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the
input signal is acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy
from one analog input that appears at the measured analog input.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below
+
VREF and is defined as:
+
VFSE = Vmax + 1.5 LSB – VREF
where
•
•
Vmax is the voltage at which the transition to the maximum code occurs
FSE can be expressed in Volts, LSB or percent of full scale range
(1)
7
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GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF − 1.5
LSB), after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last
code transition). The deviation of any given code from this straight line is measured from the center of that
code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the
power in the second and third order intermodulation products to the power in one of the original
frequencies. IMD is usually expressed in dB.
MISSING CODES are those output codes that will never appear at the ADC outputs. These codes cannot be
reached with any input value. The ADC104S021/ADC104S021Q is ensured not to have any missing
codes.
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +
0.5 LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of
the input signal to the rms value of all of the other spectral components below half the clock frequency,
including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal where a spurious signal is any signal present in the output
spectrum that is not present at the input, excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five
harmonic components at the output to the rms level of the input signal frequency as seen at the output.
THD is calculated as
2
Af22 +3+ Af6
THD = 20 • log10
2
Af1
where
•
•
Af1 is the RMS power of the input frequency at the output
Af2 through Af6 are the RMS power in the first 5 harmonic frequencies
(2)
THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the
acquisition time plus the conversion and read out times. In the case of the ADC104S021/ADC104S021Q,
this is 16 SCLK periods.
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Typical Performance Characteristics
TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.
DNL - VA = 3.0V
INL - VA = 3.0V
Figure 6.
Figure 7.
DNL - VA = 5.0V
INL - VA = 5.0V
Figure 8.
Figure 9.
DNL
vs.
Supply
INL
vs.
Supply
Figure 10.
Figure 11.
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Typical Performance Characteristics
(continued)
TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.
DNL
INL
vs.
vs.
Clock Frequency
Clock Frequency
Figure 12.
Figure 13.
DNL
vs.
Clock Duty Cycle
INL
vs.
Clock Duty Cycle
Figure 14.
Figure 15.
DNL
vs.
Temperature
INL
vs.
Temperature
Figure 16.
Figure 17.
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Typical Performance Characteristics
(continued)
TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.
SNR
THD
vs.
vs.
Supply
Supply
Figure 18.
Figure 19.
SNR
vs.
Clock Frequency
THD
vs.
Clock Frequency
Figure 20.
Figure 21.
SNR
vs.
Clock Duty Cycle
THD
vs.
Clock Duty Cycle
Figure 22.
Figure 23.
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Typical Performance Characteristics
(continued)
TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.
SNR
THD
vs.
vs.
Input Frequency
Input Frequency
Figure 24.
Figure 25.
SNR
vs.
Temperature
THD
vs.
Temperature
Figure 26.
Figure 27.
SFDR
vs.
Supply
SINAD
vs.
Supply
Figure 28.
Figure 29.
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Typical Performance Characteristics
(continued)
TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.
SFDR
SINAD
vs.
vs.
Clock Frequency
Clock Frequency
Figure 30.
Figure 31.
SFDR
vs.
Clock Duty Cycle
SINAD
vs.
Clock Duty Cycle
Figure 32.
Figure 33.
SFDR
vs.
Input Frequency
SINAD
vs.
Input Frequency
Figure 34.
Figure 35.
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Typical Performance Characteristics
(continued)
TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.
SFDR
SINAD
vs.
vs.
Temperature
Temperature
Figure 36.
Figure 37.
ENOB
vs.
Supply
ENOB
vs.
Clock Frequency
Figure 38.
Figure 39.
ENOB
vs.
Clock Duty Cycle
ENOB
vs.
Input Frequency
Figure 40.
Figure 41.
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Typical Performance Characteristics
(continued)
TA = +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.
ENOB
vs.
Temperature
Spectral Response - 3V, 200 ksps
Figure 42.
Figure 43.
Power Consumption
vs.
Spectral Response - 5V, 200 ksps
Throughput
Figure 44.
Figure 45.
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APPLICATIONS INFORMATION
ADC104S021/ADC104S021Q OPERATION
For the rest of this document, the ADC104S021/ADC104S021Q will be referred to as ADC104S021.
The ADC104S021/ADC104S021Q is a successive-approximation analog-to-digital converter designed around a
charge-redistribution digital-to-analog converter. Simplified schematics of the ADC104S021/ADC104S021Q in
both track and hold modes are shown in Figure 46 and Figure 47, respectively. In Figure 46, the
ADC104S021/ADC104S021Q is in track mode: switch SW1 connects the sampling capacitor to one of four
analog input channels through the multiplexer, and SW2 balances the comparator inputs. The
ADC104S021/ADC104S021Q is in this state for the first three SCLK cycles after CS is brought low.
Figure 47 shows the ADC104S021/ADC104S021Q in hold mode: switch SW1 connects the sampling capacitor to
ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then
instructs the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the
comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC104S021/ADC104S021Q is in this state for the fourth
through sixteenth SCLK cycles after CS is brought low.
The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of
16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is
clocked into the DIN pin to indicate the multiplexer address for the next conversion.
CHARGE
IN1
IN4
REDISTRIBUTION
DAC
MUX
SAMPLING
CAPACITOR
SW1
+
-
CONTROL
LOGIC
SW2
V
A
AGND
2
Figure 46. ADC104S021/ADC104S021Q in Track Mode
CHARGE
IN1
IN4
REDISTRIBUTION
DAC
MUX
SAMPLING
CAPACITOR
SW1
+
-
CONTROL
LOGIC
SW2
V
A
AGND
2
Figure 47. ADC104S021/ADC104S021Q in Hold Mode
USING THE ADC104S021/ADC104S021Q
Figure 3 and Figure 4 are shown in Timing Diagrams. CS is chip select, which initiates conversions and frames
the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data.
DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. Data to
be written to the ADC104S021/ADC104S021Q's Control Register is placed on DIN, the serial data input pin. New
data is written to the ADC at DIN with each conversion.
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A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when
CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a
power down state when CS is high, and also between continuous conversion cycles.
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting on the 5th clock. If
there is more than one conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK
after the N*16th rising edge of SCLK, and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK,
where "N" is an integer.
When CS is brought high, SCLK is internally gated off. If SCLK is stopped in the low state while CS is high, the
subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track
mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADC
enters the track mode on the first falling edge of SCLK after the falling edge of CS.
During each conversion, data is clocked into the DIN pin on the first 8 rising edges of SCLK after the fall of CS.
For each conversion, it is necessary to clock in the data indicating the input that is selected for the conversion
after the current one. See Table 2, Table 3, and Table 4.
If CS and SCLK go low within the times defined by tCSU and tCLH, the rising edge of SCLK that begins clocking
data in at DIN may be one clock cycle later than expected. It is, therefore, best to strictly observe the minimum
tCSU and tCLH times given in the ADC104S021/ADC104S021Q Timing Specifications.
There are no power-up delays or dummy conversions required with the ADC104S021/ADC104S021Q. The ADC
is able to sample and convert an input to full conversion immediately following power up. The first conversion
result after power-up will be that of IN1.
Table 2. Control Register Bits
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DONTC
DONTC
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
Table 3. Control Register Bit Descriptions
Bit #:
Symbol:
Description
7 - 6, 2 - 0
DONTC
Don't care. The value of these bits do not affect device operation.
5
4
3
ADD2
ADD1
ADD0
These three bits determine which input channel will be sampled and converted in the next
track/hold cycle. The mapping between codes and channels is shown in Table 4.
Table 4. Input Channel Selection
ADD2
ADD1
ADD0
Input Channel
x
x
x
x
0
0
1
1
0
1
0
1
IN1 (Default)
IN2
IN3
IN4
ADC104S021/ADC104S021Q TRANSFER FUNCTION
The output format of the ADC104S021/ADC104S021Q is straight binary. Code transitions occur midway between
successive integer LSB values. The LSB width for the ADC104S021/ADC104S021Q is VA/1024. The ideal
transfer characteristic is shown in Figure 48. The transition from an output code of 00 0000 0000 to a code of 00
0000 0001 is at 1/2 LSB, or a voltage of VA/2048. Other code transitions occur at steps of one LSB.
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111...111
111...110
111...000
ö
1LSB = VA/1024
011...111
000...010
000...001
000...000
+VA - 1.5LSB
0.5LSB
0V
ANALOG INPUT
Figure 48. Ideal Transfer Characteristic
TYPICAL APPLICATION CIRCUIT
A typical application of the ADC104S021/ADC104S021Q is shown in Figure 49. Power is provided in this
example by the Texas Instruments LP2950 low-dropout voltage regulator, available in a variety of fixed and
adjustable output voltages. The power supply pin is bypassed with a capacitor network located close to the
ADC104S021/ADC104S021Q.
Because the reference for the ADC104S021/ADC104S021Q is the supply voltage, any noise on the supply will
degrade device noise performance. To keep noise off the supply, use a dedicated linear regulator for this device,
or provide sufficient decoupling from other circuitry to keep noise off the ADC104S021/ADC104S021Q supply
pin. Because of the ADC104S021/ADC104S021Q's low power requirements, it is also possible to use a precision
reference as a power supply to maximize performance. The four-wire interface is also shown connected to a
microprocessor or DSP.
LP2950
5V
1 mF
TANT
0.1 mF
1 mF
0.1 mF
V
A
SCLK
IN1
CS
MICROPROCESSOR
DSP
IN2
IN3
ADC104S021
DIN
IN4
DOUT
GND
Figure 49. Typical Application Circuit
ANALOG INPUTS
An equivalent circuit for one of the ADC104S021/ADC104S021Q's input channels is shown in Figure 50. Diodes
D1 and D2 provide ESD protection for the analog inputs. At no time should any input go beyond (VA + 300 mV)
or (GND − 300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. For this
reason, these ESD diodes should NOT be used to clamp the input signal.
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The capacitor C1 in Figure 50 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor
R1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. Capacitor C2 is the
ADC104S021/ADC104S021Q sampling capacitor, and is typically 30 pF. The ADC104S021/ADC104S021Q will
deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging
of the sampling capacitance. This is especially important when using the ADC104S021/ADC104S021Q to
sample AC signals. Also important when sampling dynamic signals is a band-pass or low-pass filter to reduce
harmonics and noise, improving dynamic performance.
V
A
C2
30 pF
D1
D2
R1
V
IN
C1
3 pF
Conversion Phase - Switch Open
Track Phase - Switch Closed
Figure 50. Equivalent Input Circuit
DIGITAL INPUTS AND OUTPUTS
The ADC104S021/ADC104S021Q's digital output DOUT is limited by, and cannot exceed, the supply voltage,
VA. The digital input pins are not prone to latch-up and, and although not recommended, SCLK, CS and DIN may
be asserted before VA without any latch-up risk.
POWER SUPPLY CONSIDERATIONS
The ADC104S021/ADC104S021Q is fully powered-up whenever CS is low, and fully powered-down whenever
CS is high, with one exception: the ADC104S021/ADC104S021Q automatically enters power-down mode
between the 16th falling edge of a conversion and the 1st falling edge of the subsequent conversion (see Timing
Diagrams).
The ADC104S021/ADC104S021Q can perform multiple conversions back to back; each conversion requires 16
SCLK cycles. The ADC104S021/ADC104S021Q will perform conversions continuously as long as CS is held low.
The user may trade off throughput for power consumption by simply performing fewer conversions per unit time.
Figure 45 in the Typical Performance Characteristics shows the typical power consumption of the
ADC104S021/ADC104S021Q versus throughput. To calculate the power consumption, simply multiply the
fraction of time spent in the normal mode by the normal mode power consumption, and add the fraction of time
spent in shutdown mode multiplied by the shutdown mode power dissipation.
Power Management
When the ADC104S021/ADC104S021Q is operated continuously in normal mode, the maximum throughput is
fSCLK/16. Throughput may be traded for power consumption by running fSCLK at its maximum 3.2 MHz and
performing fewer conversions per unit time, putting the ADC104S021/ADC104S021Q into shutdown mode
between conversions. Figure 45 is shown in the Typical Performance Characteristics. To calculate the power
consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode
power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power
consumption. Generally, the user will put the part into normal mode and then put the part back into shutdown
mode. Note that the curve of Figure 45 is nearly linear. This is because the power consumption in the shutdown
mode is so small that it can be ignored for all practical purposes.
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Power Supply Noise Considerations
The charging of any output load capacitance requires current from the power supply, VA. The current pulses
required from the supply to charge the output capacitance will cause voltage variations on the supply. If these
variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore,
discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current
into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the
substrate that will degrade noise performance if that current is large enough. The larger is the output
capacitance, the more current flows through the die substrate and the greater is the noise coupled into the
analog channel, degrading noise performance.
To keep noise out of the power supply, keep the output load capacitance as small as practical. If the load
capacitance is greater than 50 pF, use a 100 Ω series resistor at the ADC output, located as close to the ADC
output pin as practical. This will limit the charge and discharge current of the output capacitance and improve
noise performance.
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REVISION HISTORY
Changes from Revision G (March 2013) to Revision H
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC104S021CIMM/NOPB
ADC104S021CIMMX/NOPB
ADC104S021QIMM/NOPB
ADC104S021QIMMX/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
VSSOP
DGS
DGS
DGS
DGS
10
10
10
10
1000 RoHS & Green
3500 RoHS & Green
1000 RoHS & Green
3500 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
X20C
X20C
Q20C
Q20C
SN
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADC104S021CIMM/NOPB VSSOP
DGS
DGS
10
10
1000
3500
178.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
ADC104S021CIMMX/
NOPB
VSSOP
VSSOP
VSSOP
ADC104S021QIMM/
NOPB
DGS
DGS
10
10
1000
3500
178.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
ADC104S021QIMMX/
NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADC104S021CIMM/NOPB
VSSOP
VSSOP
DGS
DGS
10
10
1000
3500
210.0
367.0
185.0
367.0
35.0
35.0
ADC104S021CIMMX/
NOPB
ADC104S021QIMM/NOPB
VSSOP
VSSOP
DGS
DGS
10
10
1000
3500
210.0
367.0
185.0
367.0
35.0
35.0
ADC104S021QIMMX/
NOPB
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
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EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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