ADC10221CIVT/NOPB [TI]
IC,A/D CONVERTER,SINGLE,10-BIT,CMOS,QFP,32PIN;
| 型号： | ADC10221CIVT/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,A/D CONVERTER,SINGLE,10-BIT,CMOS,QFP,32PIN 转换器 |
| 文件： | 总18页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2003
ADC10221
10-Bit, 15 MSPS, 98 mW A/D Converter with Internal
Sample and Hold
General Description
Features
n Internal Sample-and-Hold
n Single +5V Operation
The ADC10221 is the first in a family of low power, high
performance CMOS analog-to-digital converters. It can digi-
tize signals to 10 bits resolution at sampling rates up to
20 MSPS (15 MSPS guaranteed) while consuming a typical
98 mW from a single 5V supply. Reference force and sense
pins allow the user to connect an external reference buffer
amplifier to ensure optimal accuracy. The ADC10221 is guar-
anteed to have no missing codes over the full operating
temperature range. The unique two stage architecture
achieves 9.2 Effective Bits with a 10MHz input signal and a
20MHz clock frequency. Output formatting is straight binary
coding.
n Low Power Standby Mode
n Guaranteed No Missing Codes
n TTL/CMOS or 3V Logic Input/Output Compatible
Key Specifications
j
Resolution
10 Bits
20 MSPS (typ)
15 MSPS (min)
j
Conversion Rate
j
@
To ease interfacing to 3V systems, the digital I/O power pins
of the ADC10221 can be tied to a 3V power source, making
the outputs 3V compatible. When not converting, power
consumption can be reduced by pulling the PD (Power
Down) pin high, placing the converter into a low power
standby state, where it typically consumes less than 4 mW.
The ADC10221’s speed, resolution and single supply opera-
tion make it well suited for a variety of applications in video,
imaging, communications, multimedia and high speed data
acquisition. Low power, single supply operation ideally suit
the ADC10221 for high speed portable applications, and its
speed and resolution are ideal for charge coupled device
(CCD) input systems.
ENOB 10 MHz Input,
20 MHz Clock
DNL
9.2 Bits (typ)
0.35 LSB (typ)
98 mW (typ)
j
j
j
Power Consumption
Low Power Standby Mode
<
4 mW (typ)
Applications
n Digital Video
n Document Scanners
n Medical Imaging
n Electro-Optics
The ADC10221 comes in a space saving 32-pin TQFP and
operates over the industrial (−40˚C ≤ TA ≤ +85˚C) tempera-
ture range.
n Plain Paper Copiers
n CCD Imaging
Connection Diagram
10103801
© 2003 National Semiconductor Corporation
DS101038
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Ordering Information
Block Diagram
Commercial
(−40˚C ≤ TA ≤ +85˚C)
ADC10221CIVT
NS Package
TQFP
10103802
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2
Pin Descriptions and Equivalent Circuits
Pin
No.
Symbol
Equivalent Circuit
Description
Analog I/O
Analog Input signal to be converted. Conversion
30
VIN
+
−
range is VREF S to VREF S.
Analog input that goes to the high side of the
reference ladder of the ADC. This voltage should
+
+
−
31
32
2
VREF
VREF
VREF
F
S
F
S
+
force VREF S to be in the range of 2.3V to 4.0V.
Analog output used to sense the voltage near the top
of the ADC reference ladder.
Analog input that goes to the low side of the
reference ladder of the ADC. This voltage should
force VREF− S to be in the range of 1.3V to 3.0V.
Analog output used to sense the voltage near the
bottom of the ADC reference ladder.
1
VREF−
Converter digital clock input. VIN is sampled on the
falling edge of CLK input.
9
CLK
Power Down input. When this pin is high, the
converter is in the Power Down mode and the data
output pins are in a high impedance state.
8
PD
OE
Output Enable pin. When this pin and the PD pin are
low, the output data pins are active. When this pin or
the PD pin is high, the output data pins are in a high
impedance state.
26
14 thru
19
Digital Output pins providing the 10 bit conversion
results. D0 is the LSB, D9 is the MSB. Valid data is
present just after the falling edge of the CLK input.
and
D0 -D9
22 thru
25
Positive analog supply pins. These pins should be
connected to a clean, quiet voltage source of +5V. VA
and VD should have a common supply and be
separately bypassed with 10µF to 50µF capacitors in
parallel with 0.1µF capacitors.
3, 7, 28
VA
3
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Pin Descriptions and Equivalent Circuits (Continued)
Pin
No.
Symbol
Equivalent Circuit
Description
Positive digital supply pins. These pins should be
connected to a clean, quiet voltage source of +5V. VA
and VD should have a common supply and be
separately bypassed with 10µF to 50µF capacitors in
parallel with 0.1µF capacitors.
5, 10
VD
Positive supply pins for the digital output drivers.
These pins should be connected to a clean, quiet
voltage source of +3V to +5V and be separately
bypassed with 10µF capacitors.
12, 21
VD I/O
AGND
The ground return for the analog supply. AGND and
DGND should be connected together close to the
ADC10221 package.
4, 27,
29
The ground return for the digital supply. AGND and
DGND should be connected together close to the
ADC10221 pacjage.
6, 11
DGND
13, 20
DGND I/O
The ground return of the digital output drivers.
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Absolute Maximum Ratings (Notes 1,
2)
Machine Model
200V
Soldering Temp., Infrared, 10 sec. (Note 6)
235˚C
Storage Temperature
−65˚C to +150˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings(Notes 1, 2)
Positive Supply Voltage (V = VA = VD)
6.5V
Operating Temperature
VA, VD Supply Voltage
VD I/O Supply Voltage
VIN Voltage Range
−40˚C ≤ TA ≤ +85˚C
Voltage on Any I/O Pin −0.3V to (VA or VD) +0.3V)
+4.5V to +5.5V
+2.7V to 5.5V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
25mA
50mA
1.3V to (VA-1.0V)
2.3V to (VA-1.0V)
1.3V to 3.0V
Package Dissipation at TA
25˚C
=
See (Note 4)
VREF + Voltage Range
V
REF− Voltage Range
ESD Susceptibility (Note 5)
Human Body Model
PD, CLK, OE Voltage
−0.3V to + 5.5V
1500V
Converter Electrical Characteristics
The following specifications apply for VA = +5.0VDC, VD = 5.0VDC, VD I/O = 5.0VDC, VREF+ = +3.5VDC, VREF− = +1.5VDC
,
CL = 20pF, fCLK = 15 MHz, RS = 25Ω. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C(Note 7)
Typical
(Note 8)
Limits
(Note 9)
Symbol
Parameter
Conditions
Units
Static Converter Characteristics
INL
Integral Non-Linearity
Differential-Non Linearity
Resolution with No Missing
Codes
0.45
0.35
1.0
0.85
10
LSB(max)
LSB(max)
Bits
DNL
Zero Scale Offset Error
Full-Scale Error
−6
−6
mV(max)
mV(max)
Dynamic Converter Characteristics
fIN = 1.0 MHz
9.5
9.5
9.2
59
Bits
Bits(min)
Bits
ENOB
S/(N+D)
SNR
Effective Number of Bits
fIN = 4.43 MHz
9.0
56
fIN = 10 MHz, fCLK = 20 MHz
fIN = 1.0 MHz
dB
Signal-to-Noise Plus
Distortion Ratio
fIN = 4.43 MHz
59
dB(min)
dB
fIN = 10 MHz, fCLK = 20 MHz
fIN = 1.0 MHz
57
60
dB
Signal-to-Noise Ratio
fIN = 4.43 MHz
60
58
dB(min)
dB
fIN = 10 MHz, fCLK = 20 MHz
fIN = 1.0 MHz
58
−71
−70
−66
74
dB
THD
Total Harmonic Distortion
fIN = 4.43 MHz
−59
60
dB(min)
dB
fIN = 10 MHz, fCLK = 20 MHz
fIN = 1.0 MHz
dB
Spurious Free Dynamic
Range
SFDR
fIN = 4.43 MHz
72
dB
fIN = 10 MHz, fCLK = 20 MHz
fIN = 4.43 MHz, fCLK = 17.72 MHz
fIN = 4.43 MHz, fCLK = 17.72 MHz
68
dB
DG
DP
Differential Gain Error
Differential Phase Error
Overrange Output Code
Underrange Output Code
Full Power Bandwidth
Power Supply Rejection
Ratio
0.5
0.5
%
deg
>
VIN VREF
+
−
1023
0
<
VIN VREF
BW
150
56
MHz
dB
Change in Full Scale with 4.5V to 5.5V
Supply Change
PSRR
Reference and Analog Input Characteristics
1.3
4.0
V(min)
V(max)
VIN Analog Input Range
5
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Converter Electrical Characteristics (Continued)
The following specifications apply for VA = +5.0VDC, VD = 5.0VDC, VD I/O = 5.0VDC, VREF+ = +3.5VDC, VREF− = +1.5VDC
,
CL = 20pF, fCLK = 15 MHz, RS = 25Ω. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C(Note 7)
Typical
(Note 8)
Limits
(Note 9)
Symbol
CIN
Parameter
Analog VIN Input
Conditions
Units
5
pF
Capacitance
IIN
Input Leakage Current
Reference Ladder
10
µA
850
1150
4.0
Ω(min)
Ω(max)
V(max)
V(min)
V(min)
V(max)
RREF
1000
Resistance
VREF
VREF
+
Positive Reference Voltage
Negative Reference Voltage
3.5
1.5
−
1.3
(VREF+) −
(VREF −)
1.0
2.7
Total Reference Voltage
2.0
DC and Logic Electrical Characteristics
The following specifications apply for VA = +5.0VDC, VD = +5.0VDC, VD I/O = 5.0VDC, VREF+ = +3.5VDC, VREF− = +1.5VDC, CL
= 20 pF, fCLK = 15 MHz, RS = 25Ω. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Note 7)
Typical
(Note 8)
Limits
(Note 9)
Symbol
Parameter
Conditions
Units
CLK, OE, PD, Digital Input Characteristics
VIH
VIL
IIH
Logical "1" Input Voltage
Logical "0" Input Voltage
Logical "1" Input Current
Logical "0" Input Current
VD = 5.5V
VD = 4.5V
VIH = VD
2.0
1.0
V(min)
V(max)
µA
10
IIL
VIL = DGND
−10
µA
D00 - D13 Digital Output Characteristics
Logical "1" Output
VD I/O = + 4.5V, IOUT = −0.5 mA
VD I/O = + 2.7V, IOUT = −0.5 mA
VD I/O = + 4.5V, IOUT = 1.6 mA
VD I/O = + 2.7V, IOUT = 1.6 mA
VOUT = DGND
4.0
2.4
0.4
0.4
V(min)
V(min)
V(max)
V(max)
µA
VOH
Voltage
Logical "0" Output
VOL
Voltage
TRI-STATE Output
−10
10
IOZ
Current
VOUT = VD
µA
IOS
Output Short Circuit
Current
VD I/O = 3V
12
mA
VD I/O = 5V
25
mA
Power Supply Characteristics
PD = LOW, Ref not included
PD = HIGH, Ref not included
PD = LOW, Ref not included
PD = HIGH, Ref not included
14.5
0.5
5
IA
Analog Supply Current
16
mA(max)
ID + IDI/O
PD
Digital Supply Current
Power Consumption
6
mA(max)
0.2
98
110
mW (max)
AC Electrical Characteristics
The following specifications apply for VA = +5.0VDC, VD I/O = 5.0VDC, VREF+ = +3.5VDC, VREF− = +1.5VDC, fCLK = 15 MHz, trc
= tfc = 5 ns, RS = 25Ω. CL (data bus loading) = 20 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA
25˚C(Note 7)
=
Typical
(Note 8)
20
Limits
(Note 9)
15
Units
Symbol
Parameter
Conditions
(Limits)
MHz(min)
MHz(max)
ns(min
fCLK1
fCLK2
tCH
Maximum Clock Frequency
Minimum Clock Frequency
Clock High Time
1
23
23
45
55
tCL
Clock Low Time
ns(min)
%(min)
Duty Cycle
50
%(max)
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AC Electrical Characteristics (Continued)
The following specifications apply for VA = +5.0VDC, VD I/O = 5.0VDC, VREF+ = +3.5VDC, VREF− = +1.5VDC, fCLK = 15 MHz, trc
= tfc = 5 ns, RS = 25Ω. CL (data bus loading) = 20 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA
25˚C(Note 7)
=
Typical
(Note 8)
Limits
(Note 9)
2.0
Units
Symbol
Parameter
Conditions
(Limits)
Clock Cycles
ns(max)
ns
Pipeliine Delay (Latency)
Clock Input Rise and Fall Time
Output Rise and Fall Times
Fall of CLK to data valid
Output Data Hold Time
trc, tfc
5
tr, tf
tOD
tOH
10
20
12
25
ns(max)
ns
From output High, 2K
to Ground
25
18
ns
ns
tDIS
Rising edge of OE to valid data
From output Low, 2K
to VD I/O
tEN
Falling edge of OE to valid data
Data valid time
1K to VCC
25
40
4
ns
tVALID
tAD
ns
ns
Aperture Delay
<
tAJ
Aperture Jitter
30
ps
Full Scale Step Response
tr = 10ns
1
conversion
VIN step from (VREF
+
Overrange Recovery Time
1
conversion
ns
+100 mV) to (VREF−)
PD low to 1/2 LSB accurate
conversion (Wake-Up time)
tWU
700
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
<
>
V
Note 3: When the input voltage at any pin exceeds the power supplies ( V
AGND or V
or V ), the current at that pin should be limited to 25 mA. The
A D
IN
IN
50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
J
junction-to-ambient thermal resistance (θ ), and the ambient temperature (T ), and can be calculated using the formula P MAX = (T max - T )/θ . In the 32-pin
JA
A
D
J
A
JA
TQFP, θ is 69˚C/W, so P MAX = 1,811 mW at 25˚C and 942 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this
JA
D
device under normal operation will typically be about 110 mW (98 mW quiescent power + 2 mW reference ladder power +10 mW due to 10 TTL load on each digital
output). The values for maximum power dissipation listed above will be reached only when the ADC10221 is operated in a severe fault condition (e.g. when input
or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220 pF discharged through ZERO Ω.
Note 6: The 235˚C reflow temperature refers to infared reflow. For Vapor Phase Reflow (VPR), the following conditions apply: Maintain the temperature at the top
of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle.
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 500mV beyond the supply rails will not damage this device. However, errors in
the A/D conversion can occur if the input goes above V or below AGND by more than 300 mV.
A
7
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AC Electrical Characteristics (Continued)
10103812
10103824
10103811
Note 8: Typical figures are at T = T = 25˚C, and represent most likely parametric norms.
A
J
Note 9: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: When the input signal is between V
+ and (V + 300mV), the output code will be 3FFh, or all 1s. When the input signal is between −300 mV and V
−,
REF
REF
A
the output code will be 000h, or all 0s.
Typical Performance Characteristics VA = VD = VDI/O = 5V, fCLK = 20MHz, unless otherwise
specified.
Typical INL
INL vs fCLK
INL vs VA
10103826
10103827
10103825
INL vs Clock Duty Cycle
Typical DNL
DNL vs fCLK
10103838
10103828
10103839
SINAD & ENOB vs
Temperature and fIN
DNL vs VA
DNL vs Clock Duty Cycle
10103840
10103830
10103829
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Typical Performance Characteristics VA = VD = VDI/O = 5V, fCLK = 20MHz, unless otherwise
specified. (Continued)
SINAD & ENOB vs
SINAD & ENOB vs VA
fCLK and fIN
IA + ID vs. Temperature
10103837
10103832
10103831
Spectral Response at 20 MSPs
10103835
9
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OUTPUT DELAY is the time delay after the fall of the input
clock before the data update is present at the output pins.
Specification Definitions
APERTURE JITTER is the variation in aperture delay from
OUTPUT HOLD TIME is the length of time that the output
data is valid after the fall of the input clock.
sample to sample. Aperture jitter shows up as input noise.
APERTURE DELAY See Sampling Delay.
OVER RANGE RECOVERY TIME is the time required after
DIFFERENTIAL GAIN ERROR is the percentage difference
between the output amplitudes of a given amplitude small
signal, high frequency sine wave input at two different dc
input levels.
VIN goes from AGND to VREF+ or VIN goes from VA to VREF−
for the converter to recover and make a conversion with its
rated accuracy.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
sented to the output driver stage. Data for any given sample
is available by the Pipeline Delay plus the Output Delay after
that sample is taken. New data is available at every clock
cycle, but the data lags the conversion by the pipeline delay.
DIFFERENTIAL PHASE ERROR is the difference in the
output phase of a small signal sine wave input at two differ-
ent dc input levels.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio (S/N+D or SINAD). ENOB is defined as
(SINAD −1.76) / 6.02.
PSRR (POWER SUPPLY REJECTION RATIO) is the ratio
of the change in dc power supply voltage to the resulting
change in Full Scale Error, expressed in dB.
SAMPLING (APERTURE) DELAY or APERTURE TIME is
that time required after the fall of the clock input for the
sampling switch to open. The sample is effectively taken this
amount of time after the fall of the clock input.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its 1 MHz value for a full scale input. The test is
performed with fIN equal to 100 kHz plus integral multiples of
fCLK. The input frequency at which the output is −3 dB
relative to the1 MHz input signal is the full power bandwidth.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
FULL SCALE (FS) INPUT RANGE of the ADC is the input
range of voltages over which the ADC will digitize that input.
For VREF+ = 3.50V and VREF− = 1.50V, FS = (VREF+) −
(VREF−) = 2.00V.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SI-
NAD) is the ratio, expressed in dB, of the RMS value of the
input signal to the RMS value of all of the other spectral
components below half the clock frequency, including har-
monics but excluding dc.
FULL SCALE OFFSET ERROR is a measure of how far the
last code transition is from the ideal 11⁄
LSB below VREF+
2
and is defined as V1023 −1.5 LSB − VREF+ , where V1023 is
the voltage at which the transitions from code 1022 to 1023
occurs.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB or dBc, between the RMS values of
the input signal and the peak spurious signal, where a
spurious signal is any signal present in the output spectrum
that is not present at the input.
FULL SCALE STEP RESPONSE is defined as the time
required after VIN goes from VREF− to VREF+, or VREF+ to
VREF−, and settles sufficiently for the converter to recover
and make a conversion with its rated accuracy.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB, of the rms total of the first six harmonic
components, to the rms value of the input signal.
INTEGRAL NON-LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
ZERO SCALE OFFSET ERROR is the difference between
negative full scale (1⁄
2
LSB below the first code transition)
the ideal input voltage (1⁄
LSB) and the actual input voltage
2
through positive full scale (11⁄
2
LSB above the last code
that just causes a transition from an output code of zero to
an output code of one.
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
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Timing Diagram
10103815
FIGURE 1. ADC10221 Timing Diagram
10103817
10103816
FIGURE 2. AC Test Circuit
FIGURE 3. tEN, tDIS Test Circuit
11
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bandwidth, low distortion and minimal Differential Gain and
Differential Phase. The LMH6702 performs best with a feed-
back resistor of about 100 ohms.
Functional Description
The ADC10221 maintains excellent dynamic performance
for input signals up to half the clock frequency. The use of an
internal sample-and-hold amplifier (SHA) enables sustained
dynamic performance for signals of input frequency beyond
the clock rate, lowers the converter’s input capacitance and
reduces the number of external components required.
Care should be taken to keep digital noise out of the analog
input circuitry to maintain highest noise performance.
2.0 REFERENCE INPUTS
Note: Throughout this data sheet reference is made to
VREF+ and to VREF−. These refer to the internal voltage
across the reference ladder and are, nominally, VREF+ S and
VREF− S, respectively.
The analog signal at VIN that is within the voltage range set
by VREF+ S and VREF− S are digitized to ten bits at up to
25 MSPS. Input voltages below VREF− S will cause the
output word to consist of all zeroes. Input voltages above
VREF+ S will cause the output word to consist of all ones.
VREF+ S has a range of 2.3 to 4.0 Volts, while VREF− S has
a range of 1.3 to 3.0 Volts. VREF+ S should always be at
least 1.0 Volt more positive than VREF− S.
Figure 4 shows a simple reference biasing scheme with
minimal components. While this circuit might suffice for
some applications, it does suffer from thermal drift because
the external resistor at pin 2 will have a different temperature
coefficient than the on-chip resistors. Also, the on-chip resis-
tors, while well matched to each other, will have a large
tolerance compared with any external resistors, causing the
value of VREF- to be quite variable. No d.c. current should be
allowed to flow through pin 1 or 32 or linearity errors will
result near the zero scale and full scale ends of the signal
excursion. The sense pins were designed to be used with
high impedance opamp inputs for high accuracy biasing.
Data is acquired at the falling edge of the clock and the
digital equivalent of that data is available at the digital out-
puts 2.0 clock cycles plus tOD later. The ADC10221 will
convert as long as the clock signal is present at pin 9 and the
PD pin is low. The Output Enable pin (OE), when low,
enables the output pins. The digital outputs are in the high
impedance state when the OE pin is low or the PD pin is
high.
The circuit of Figure 5 is an improvement over the circuit of
Figure 4 in that both ends of the reference ladder are defined
with reference voltages. This reduces problems of high ref-
erence variability and thermal drift, but requires two refer-
ence sources.
Applications Information
1.0 THE ANALOG INPUT
The analog input of the ADC10221 is a switch (transmission
gate) followed by a switched capacitor amplifier. The capaci-
tance seen at the input changes with the clock level, appear-
ing as about 3 pF when the clock is low, and about 5 pF
when the clock is high. This small change in capacitance can
be reasonably assumed to be a fixed capacitance. Care
should be taken to avoid driving the input beyond the supply
rails, even momentarily, as during power-up.
In addition to the usual reference inputs, the ADC10221 has
two sense outputs for precision control of the ladder volt-
ages. These sense outputs (VREF+ S and VREF− S) compen-
sate for errors due to IR drops between the source of the
reference voltages and the ends of the reference ladder
itself.
With the addition of two op-amps, the voltages at the top and
bottom of the reference ladder can be forced to the exact
value desired, as shown in Figure 6.
The LMH6702 has been found to be a good device to drive
the ADC10221 because of its low voltage capability, wide
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Applications Information (Continued)
10103818
FIGURE 4. Simple, low component count reference biasing
13
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Applications Information (Continued)
10103819
FIGURE 5. Better low component count reference biasing
The VREF+ F and VREF− F pins should each be bypassed to
AGND with 10 µF tantalum or electrolytic and 0.1 µF ceramic
capacitors. The circuit of Figure 6 may be used if it is desired
to obtain precise reference voltages. The LMC6082 in this
circuit was chosen for its low offset voltage, low voltage
capability and low cost.
Voltages at the reference sense pins (VREF+ S and VREF− S)
should be within the range specified in the Operating Ratings
table (2.3V to 4.0V for VREF+ and 1.3V to 3.0V for VREF−).
Any device used to drive the reference pins should be able to
source sufficient current into the VREF+ F pin and sink suffi-
cient current from the VREF− F pin when the ladder is at its
minimum value of 850 Ohms.
Since the current flowing through the sense lines (those lines
associated with VREF+ S and VREF− S) is essentially zero,
there is negligible voltage drop across any resistance in
series with these sense pins and the voltage at the inverting
input of the op-amp accurately represents the voltage at the
top (or bottom) of the ladder. The op-amp drives the force
input, forcing the voltage at the ends of the ladder to equal
the voltage at the op-amp’s non-inverting input, plus any
offset voltage. For this reason, op-amps with low VOS, such
as the LMC6081 and LMC6082, should be used for this
application.
The reference voltage at the top of the ladder (VREF+) may
take on values as low as 1.0V above the voltage at the
bottom of the ladder (VREF−) and as high as (VA - 1.0V)
Volts. The voltage at the bottom of the ladder (VREF−) may
take on values as low as 1.3 Volts and as high as 3.0V.
However, to minimize noise effects and ensure accurate
conversions, the total reference voltage range (VREF+ -
VREF−) should be a minimum of 2.0V and a maximum of
2.7V.
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Applications Information (Continued)
10103820
FIGURE 6. Setting precision reference voltages
3.0 POWER SUPPLY CONSIDERATIONS
circuit. Be sure that the supplies to circuits driving the CLK,
PD, OE, analog input and reference pins do not come up any
faster than does the voltage at the ADC10221 power pins.
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A
10 µF to 50 µF tantalum or aluminum electrolytic capacitor
should be placed within an inch (2.5 centimeters) of the A/D
power pins, with a 0.1 µF ceramic chip capacitor placed as
close as possible to each of the converter’s power supply
pins. Leadless chip capacitors are preferred because they
have low lead inductance.
4.0 THE ADC10221 CLOCK
Although the ADC10221 is tested and its performance is
guaranteed with a 15 MHz clock, it typically will function with
clock frequencies from 1 MHz to 20 MHz. Performance is
best if the clock rise and fall times are 5 ns or less.
If the CLK signal is interrupted, or its frequency is too low,
the charge on internal capacitors can dissipate to the point
where the accuracy of the output data will degrade. This is
what limits the minimum sample rate.
While a single voltage source should be used for the analog
and digital supplies of the ADC10221, this supply should not
be the supply that is used for other digital circuitry on the
board.
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty
cycle is difficult, this device is designed to maintain perfor-
mance over a range of duty cycles. While it is specified and
performance is guaranteed with a 50% clock duty cycle,
performance is typically maintained over a clock duty cycle
range of 45% to 55%.
As is the case with all high speed converters, the ADC10221
should be assumed to have little high frequency power sup-
ply rejection. A clean analog power source should be used.
No pin should ever have a voltage on it that is in excess of
the supply voltages or below ground, not even on a transient
basis. This can be a problem upon application of power to a
15
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5.0 LAYOUT AND GROUNDING
Applications Information (Continued)
Proper routing of all signals and proper ground techniques
are essential to ensure accurate conversion. Separate ana-
log and digital ground planes are required to meet data sheet
limits. The analog ground plane should be low impedance
and free of noise form other parts of the system.
The clock line should be series terminated at the source end
in the characteristic impedance of that line. Use a series
resistor right after the source such that the source imped-
ance plus that series resistor equals the characteristic im-
pedance of the clock line. This resistor should be as close to
the source as possible, but in no case should it be further
away than
Each bypass capacitor should be located as close to the
appropriate converter pin as possible and connected to the
pin and the appropriate ground plane with short traces. The
analog input should be isolated from noisy signal traces to
avoid coupling of spurious signals into the input. Any exter-
nal component (e.g., a filter capacitor) connected between
the converter’s input and ground should be connected to a
very clean point in the analog ground return.
where tr is the rise time of the clock signal and tPR is the
propagation rate down the board. For a Board of FR-4
material, tPR is typically about 150 ps/inch.
Figure 7 gives an example of a suitable layout, including
power supply routing, ground plane separation, and bypass
capacitor placement. All analog circuitry (input amplifiers,
filters, reference components, etc.) should be placed on or
over the analog ground plane. All digital circuitry and I/O
lines should be over the digital ground plane.
To maintain a consistent impedance along the clock line, use
stripline or microstrip techniques (see Application Note AN-
1113) and avoid the use of through-holes in the line.
It might also be necessary to terminate the ADC end of the
clock line with a series RC to ground such that the resistor
value equals the characteristic impedance of the clock line
and the capacitor value is
Digital and analog signal lines should never run parallel to
each other in close proximity with each other. They should
only cross each other when absolutely necessary, and then
only at 90˚ angles. Violating this rule can result in digital
noise getting into the input, which degrades accuracy and
dynamic performance (THD, SNR, SINAD).
where tPR is again the propagation rate down the clock line,
L is the length of the line in inches and ZO is the character-
istic impedance of the clock line.
10103821
FIGURE 7. An acceptable layout pattern
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16
(e.g., 74F and 74AC devices) to exhibit undershoot that goes
more than a volt below ground. A resistor of 50 to 100Ω in
series with the offending digital input will usually eliminate
the problem.
Applications Information (Continued)
6.0 DYNAMIC PERFORMANCE
The ADC10221 is ac tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must be free of jitter. For best
ac performance, isolating the ADC clock from any digital
circuitry should be done with adequate buffers, as with a
clock tree. See Figure 8
Care should be taken not to overdrive the inputs of the
ADC10221 (or any device) with a device that is powered
from supplies outside the range of the ADC10221 supply.
Such practice may lead to conversion inaccuracies and even
to device damage.
Meeting dynamic specifications is also dependent upon
keeping digital noise out of the input, as mentioned in Sec-
tions 1.0 and 5.0.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers has to charge for
each conversion, the more instantaneous digital current is
required from VD and DGND. These large charging current
spikes can couple into the analog section, degrading dy-
namic performance. Adequate bypassing and maintaining
separate analog and digital ground planes will reduce this
problem on the board. Buffering the digital data outputs (with
an 74F541, for example) may be necessary if the data bus to
be driven is heavily loaded. Dynamic performance can also
be improved by adding series resistors of 47Ω at each digital
output.
Driving the VREF+ F pin or the VREF− F pin with devices
that can not source or sink the current required by the
ladder. As mentioned in section 2.0, be careful to see that
any driving devices can source sufficient current into the
VREF+ F pin and sink sufficient current from the VREF− F pin.
If these pins are not driven with devices than can handle the
required current, they will not be held stable and the con-
verter output will exhibit excessive noise.
10103822
FIGURE 8. Isolating the ADC clock from digital
circuitry
Using a clock source with excessive jitter. This will cause
the sampling interval to vary, causing excessive output noise
and a reduction in SNR performance. Simple gates with RC
timing is generally inadequate.
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 300mV beyond the supply pins. Exceeding these
limits on even a transient basis can cause faulty or erratic
operation. It is not uncommon for high speed digital circuits
Using the same voltage source for VD and other digital
logic. As mentioned in Section 3.0, VD should use the same
power source used by VA, but should be decoupled from VA.
17
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Physical Dimensions inches (millimeters)
unless otherwise noted
32-Lead TQFP Package
Ordering Number ADC10221CIVT
NS Package Number VBE32A
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significant injury to the user.
2. A critical component is any component of a life
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can be reasonably expected to cause the failure of
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