AD16V130CISQ [TI]
PROPRIETARY METHOD ADC, QCC64, 9 X 9 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-64;
| 型号： | AD16V130CISQ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PROPRIETARY METHOD ADC, QCC64, 9 X 9 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-64 转换器 |
| 文件： | 总24页 (文件大小：552K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 11, 2008
ADC16V130
16-Bit, 130 MSPS A/D Converter with LVDS Outputs
Offset binary or 2's complement data format
■
■
■
General Description
Full data rate LVDS output port
The ADC16V130 is a monolithic high performance CMOS
64-pin LLP package (9x9x0.8, 0.5mm pin-pitch)
analog-to-digital converter capable of converting analog input
signals into 16-bit digital words at rates up to 130 Mega Sam-
ples Per Second (MSPS). This converter uses a differential,
pipelined architecture with digital error correction and an on-
chip sample-and-hold circuit to minimize power consumption
and external component count while providing excellent dy-
namic performance. Automatic power-up calibration enables
excellent dynamic performance and reduces part-to-part vari-
ation, and the ADC16V130 could be re-calibrated at any time
by asserting and then de-asserting power-down. An integrat-
ed low noise and stable voltage reference and differential
reference buffer amplifier easies board level design. On-chip
duty cycle stabilizer with low additive jitter allows wide duty
cycle range of input clock without compromising its dynamic
performance. A unique sample-and-hold stage yields a full-
power bandwidth of 1.4 GHz. The digital data is provided via
full data rate LVDS outputs – making possible the 64-pin,
9mm x 9mm LLP package. The ADC16V130 operates on dual
power supplies +1.8V and +3.0V with a power-down feature
to reduce the power consumption to very low levels while al-
lowing fast recovery to full operation.
Key Specifications
Resolution
16 Bits
130 MSPS
ꢀꢀ
78.5 dBFS (typ)
■
Conversion Rate
SNR
■
■
(fIN = 10MHz)
(fIN = 70MHz)
77.8 dBFS (typ)
(fIN = 160MHz)
76.7 dBFS (typ)
ꢀꢀ
95.5 dBFS (typ)
SFDR
■
(fIN = 10 MHz)
(fIN = 70MHz)
92.0 dBFS (typ)
(fIN = 160MHz)
90.6 dBFS (typ)
1.4 GHz (typ)
ꢀꢀ
Full Power Bandwidth
Power Consumption
■
■
Core
650 mW (typ)
LVDS Driver
105 mW (typ)
Total
755 mW (typ)
-40°C ~ 85°C
Operating Temperature Range
■
Features
Applications
Dual Supplies: 1.8V and 3.0V operation
■
■
■
■
■
■
High IF Sampling Receivers
■
■
On chip automatic calibration during power-up
Multi-carrier Base Station Receivers
Low power consumption
GSM/EDGE, CDMA2000, UMTS, LTE and WiMax
Test and Measurement Equipment
Communications Instrumentation
Data Acquisition
Multi-level multi-function pins for CLK/DF and PD
■
■
■
■
Power-down and sleep modes
On chip precision reference and sample-and-hold circuit
On chip low jitter duty-cycle stabilizer
■
Portable Instrumentation
Block Diagram
30062602
© 2008 National Semiconductor Corporation
300626
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Connection Diagram
30062601
Ordering Information
Package
Industrial (−40°C ≤ TA ≤ +85°C)
ADC16V130CISQ
64 Pin LLP
ADC16V130EB
Evaluation Board
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2
Pin Descriptions
Pin No.
ANALOG I/O
ꢀꢀ
Symbol
Equivalent Circuit
Function and Connection
VIN+
61
ꢀꢀ
Differential analog input pins. The differential full-scale input signal
level is 2.4Vpp as default. Each input pin signal centered on a
common mode voltage, VCM
.
VIN-
62
Upper reference voltage.
This pin should not be used to source or sink current. The
decoupling capacitor to AGND (low ESL 0.1μF) should be placed
very close to the pin to minimize stray inductance. VRP needs to be
VRP
6,7
connected to VRN through a low ESL 0.1μF and a low ESR 10μF
capacitors in parallel.
Lower reference voltage.
This pin should not be used to source or sink current. The
decoupling capacitor to AGND (low ESL 0.1μF) should be placed
very close to the pin to minimize stray inductance. VRN needs to be
VRN
4,5
58
connected to VRP through a low ESL 0.1μF and a low ESR 10μF
capacitors in parallel.
Common mode voltage
The decoupling capacitor to AGND (low ESL 0.1μF) should be
placed as close to the pin as possible to minimize stray inductance.
It is recommended to use VRM to provide the common mode voltage
for the differential analog inputs.
VRM
Internal reference voltage output / External reference voltage input.
By default, this pin is the output for the internal 1.2V voltage
reference. This pin should not be used to sink or source current and
should be decoupled to AGND with a 0.1μF, low ESL capacitor.
The decoupling capacitors should be placed as close to the pins
as possible to minimize inductance and optimize ADC
performance. The size of decoupling capacitor should not be larger
than 0.1μF, otherwise dynamic performance after power-up
calibration can drop due to the long VREF settling.
VREF
57
This pin can also be used as the input for a low noise external
reference voltage. The output impedance for the internal reference
at this pin is 9 kΩ and this can be overdriven provided the
impedance of the external source is <<9 kΩ. Careful decoupling is
just as essential when an external reference is used. The 0.1µF low
ESL decoupling capacitor should be placed as close to this pin as
possible.
The Input differential voltage swing is equal to 2 * VREF
.
ꢀꢀ
ꢀꢀ
10
ꢀꢀ
ꢀꢀ
CLK+
CLK−
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
11
ꢀꢀ
ꢀꢀ
Differential clock input pins. DC biasing is provided internally. For
single-ended clock mode, drive CLK+ through AC coupling while
decoupling CLK- pin to AGND.
ꢀꢀ
ꢀꢀ
3
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Pin No.
Symbol
Equivalent Circuit
Function and Connection
DIGITAL I/O
LVDS Data Output. The 16-bit digital output of the data converter
is provided on these ports in a full data rate manner. A 100 Ω
termination resistor must be placed between each pair of
differential signals at the far end of the transmission line.
15 – 22
25 – 32
35 – 42
45 – 52
D0+/- to D3+/-
D4+/- to D7+/-
D8+/- to D11+/-
D12+/- to D15+/-
Over-Range Indicator. Active High.
This output is set High when analog input signal exceeds full scale
of 16 bit conversion range (<0,> 65535). This signal is asserted
coincidently with the over-range data word. A 100 Ω termination
resistor must be placed between the differential signals at the far
end of the transmission.
53, 54
OR+/-
Output Clock. This pin is used to clock the output data. It has the
same frequency as the sampling clock. One word of data is output
in each cycle of this signal. A 100 Ω termination resistor must be
placed between the differential clock signals at the far end of the
transmission line. The rising edge of this signal should be used to
capture the output data. See the detail Section on Timing
Diagrams .
33, 34
OUTCLK+/-
This is a three-state pin.
PD = VA3.0, then Power Down is enabled. In the Power Down state,
only the reference voltage circuitry remains active and power
dissipation is reduced.
PD =VA3.0 * (2/3), then Sleep mode is enabled. In Sleep mode is
similar to Power Down mode - it consumes more power but has a
faster recovery time.
14
PD
PD = AGND, then Normal operation mode is turned on.
This is a four-state pin controlling two parameters: input clock
selection and output data format.
CLK_SEL/DF = VA3.0, then CLK+ and CLK− are configured as a
differential clock input and the output data format is 2's
complement.
CLK_SEL/DF = VA3.0 * (2/3), then CLK+ and CLK− are configured
as a differential clock input and the output data format is offset
binary.
1
CLK_SEL/DF
CLK_SEL/DF = VA3.0 * (1/3), then CLK+ is configured as a single-
ended clock input and CLK− should be tied to AGND. The output
data format is 2's complement.
CLK_SEL/DF = AGND, then CLK+ is configured as a single-ended
clock input and CLK− should be tied to AGND. The output data
format is offset binary.
POWER SUPPLIES
3.0V Analog Power Supply. These pins should be connected to a
quiet source and should be decoupled to AGND with 0.1μF
capacitors located close to the power pins.
VA3.0
2, 55, 59
Analog Power
Analog Power
1.8V Analog Power Supply. These pins should be connected to a
quiet source and should be decoupled to AGND with 0.1μF
capacitors located close to the power pins.
VA1.8
9, 64
13
1.8V Analog/Digital Power Supply. These pins should be
connected to a quiet source and should be decoupled to AGND
with 0.1μF capacitors located close to the power pins.
Analog Ground Return. The exposed pad (Pin 0) on back of the
package must be soldered to ground plane to ensure rated
performance.
VAD1.8
AGND
Analog/Digital Power
Analog Ground
0, 3, 8, 12,
56, 60, 63
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4
Pin No.
24, 44
23, 43
Symbol
VDR
Equivalent Circuit
Power
Function and Connection
Output Driver Power Supply. This pin should be connected to a
quiet voltage source and be decoupled to DRGND with a 0.1μF
capacitor close to the power pins.
DRGND
Ground
Output Driver Ground Return.
5
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Absolute Maximum Ratings (Notes , 1)
Operating Ratings (Notes 1, )
Specified Temperature
Range:
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
-40°C to +85°C
+2.7V to +3.6V
+1.7V to +1.9V
30/70 %
3.0V Analog Supply Voltage
Range: (VA3.0
)
Supply Voltage (VA3.0
Supply Voltage (VA1.8, VAD1.8
VDR
)
−0.3V to 4.2V
−0.3V to 2.35V
1.8V Supply Voltage Range:
VA1.8, VAD1.8, VDR
,
)
Clock Duty Cycle
Voltage at any Pin except D0-
D15, OVR, OUTCLK, CLK, VIN
−0.3V to (VA3.0 +0.3V)
(Not to exceed 4.2V)
-0.3V to (VDR +0.3V)
(Not to exceed 2.35V)
0.3V to (VDR + 0.3V)
(Not to exceed 2.35V)
5 mA
Voltage at CLK, VIN Pins
Voltage at D0-D15, OR,
OUTCLK Pins
Input Current at any pin (Note
3)
Storage Temperature Range
ESD Rating(Note 4)
Machine Model
-65°C to +150°C
200 V
Human Body Model
2000 V
Soldering process must comply with National
Semiconductor's Reflow Temperature Profile
specifications. Refer to www.national.com/packaging.
(Note 5)
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: VA3.0 = +3.0V, VA1.8 = VAD1.8 = VDR = +1.8V, fCLK = 130 MSPS, AIN
= -1dBFS, LVDS Rterm = 100 Ω, CL = 5 pF. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All
other limits apply for TA = 25°C, unless otherwise noted.
Typical
(Note 6)
Units
(Limits)
Symbol
Parameter
Conditions
Limits
16
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
Bits (min)
LSB
INL
Integral Non Linearity
Differential Non Linearity
Positive Gain Error
±1.5
±0.45
-4.2
DNL
PGE
NGE
VOFF
LSB
%FS
Negative Gain Error
3.7
%FS
Offset Error (VIN+ = VIN−)
Under Range Output Code
Over Range Output Code
0.12
0
%FS
0
65535
65535
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VRM is the common mode reference
voltage
VRM
VCM
Common Mode Input Voltage
V
V
±0.05
Reference Ladder Midpoint Output
Voltage
VRM
1.15
VREF
Internal Reference Voltage
1.20
2.4
V
VPP
Differential Analog Input Range
Internal Reference
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6
Dynamic Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: VA3.0 = +3.0V, VA1.8 = VAD1.8 = VDR = +1.8V, fCLK = 130 MSPS, AIN
= -1dBFS, LVDS Rterm = 100 Ω, CL = 5 pF. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All
other limits apply for TA = 25°C, unless otherwise noted.
Symbol
Parameter
Resolution with no missing codes
Dynamic Range
Conditions
Typ
Limits
16
Units
Bits
DR
0V analog input is applied
Fin = 10 MHz
Fin = 40 MHz
Fin = 70 MHz
Fin = 160 MHz
Fin = 240 MHz
Fin = 10 MHz
Fin = 40 MHz
Fin = 70 MHz
Fin = 160 MHz
Fin = 240 MHz
Fin = 10 MHz
Fin = 40 MHz
Fin = 70 MHz
Fin = 160 MHz
Fin = 240 MHz
Fin = 10 MHz
Fin = 40 MHz
Fin = 70 MHz
Fin = 160 MHz
Fin = 240 MHz
Fin = 10 MHz
Fin = 40 MHz
Fin = 70 MHz
Fin = 160 MHz
Fin = 240 MHz
Fin = 10 MHz
Fin = 40 MHz
Fin = 70 MHz
Fin = 160 MHz
Fin = 240 MHz
Fin = 10 MHz
Fin = 40 MHz
Fin = 70 MHz
Fin = 160 MHz
Fin = 240 MHz
Fin = 10 MHz
Fin = 40 MHz
Fin = 70 MHz
Fin = 160 MHz
Fin = 240 MHz
-3dB Compression Point
79
78.5
78.2
77.8
76.7
75.6
95.5
91
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
SNR
SFDR
THD
Signal-to-Noise Ratio (Note 9)
75.5
87
Single-tone Spurious Free Dynamic
Range (Note 9)
92
90.6
85.3
-91.5
-88.4
-89.4
-87.1
-82.8
-95.5
-104.1
-95.6
-91.5
-85.3
-98.3
-89.4
-92
Total Harmonic Distortion (Note 9)
Second-order Harmonic(Note 9)
Third-order Harmonic (Note 9)
-81
-88
-87
94
H2
H3
-90.6
-87.8
106
103.2
104.1
101.5
98.4
78.3
77.8
77.5
76.3
74.8
12.7
12.6
12.6
12.4
12.1
1.4
Worst Harmonic or Spurious Tone
excluding H2 and H3(Note 9)
Spur-H2/3
SINAD
ENOB
Signal-to-Noise and Distortion Ratio (Note
9)
Bits
Effective Number of Bits
Full Power Bandwidth
Bits
Bits
Bits
GHz
7
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Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: VA3.0 = +3.0V, VA1.8 = VAD1.8 = VDR = +1.8V, fCLK = 130 MSPS, AIN
= -1dBFS, LVDS Rterm = 100 Ω, CL = 5 pF. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All
other limits apply for TA = 25°C, unless otherwise noted.
Units
Symbol
Parameter
Conditions
Full Operation(Note 12)
Typical
Limits
(Limits)
mA (max)
mA (max)
mA (max)
mA
IA3.0
IA1.8
IAD1.8R
IDR
174.5
36
208
42
Analog 3.0V Supply Current
Analog 1.8V Supply Current
Digital 1.8V Supply Current
Output Driver Supply Current
Core Power Consumption
Full Operation(Note 12)
Full Operation (Note 12)
34
41
Full Operation
58.3
650
Excludes IDR (Note 12)
773
mW (max)
Current drawn from the VDR supply; Fin = 10
MHz Rterm = 100Ω
Driver Power Consumption
105
mW
Normal operation; Fin = 10 MHz
Power down state, with external clock
Sleep state, with external clock
755
3
mW
mW
mW
Total Power Consumption
30
LVDS Electrical Characteristics
Unless otherwise specified, the following specifications apply: VA3.0 = +3.0V, VA1.8 = VAD1.8 = VDR = +1.8V, fCLK = 130 MSPS, AIN
= -1dBFS, LVDS Rterm = 100 Ω, CL = 5 pF. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All
other limits apply for TA = 25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVDS DC SPECIFICATIONS (apply to pins DO to D15, OR)
VOD
VOS
IOS
Output Differential Voltage
Output Offset Voltage
175
250
1.2
2.5
± 1
325
mV
V
100 Ω Differential Load
100 Ω Differential Load
0 Ω Differential Load
Termination is open
1.15
1.25
Output Short Circuit Current
Output Open Circuit Current
mA
µA
IOZ
-20
20
Timing Specifications
Unless otherwise specified, the following specifications apply: VIN = -1dBFS, AGND = DRGND = 0V, VA3.0= +3.0V, VA1.8 = VAD1.8
= VDR = +1.8V, Internal VREF = +1.2V, fCLK = 130 MHz, VCM = VRM, CL = 5 pF, Single-Ended Clock Mode, Offset Binary Format.
Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for
TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C, unless otherwise noted.
Parameter
Input Clock Frequency
Data Output Setup Time (Tsu) (Note 10) Measured @ Vdr/2; Fclk = 130 MHz.
Conditions
Typ
Limits
130
Units
MHz (max)
nS (min)
3.3
3.3
11
2.5
Data Output Hold Time (Th) (Note 10)
Pipeline Latency(Note 11)
Aperture Jitter
Measured @ Vdr/2; Fclk = 130 MHz.
2.5
nS (min)
Clock Cycles
fS rms
80
Power-Up Time
From assertion of Power to specified level
of performance.
0.5+ 103*(222+216)/FCLK
0.1+ 103*(219+216)/FCLK
100
mS
mS
μS
Power-Down Recovery Time
Sleep Recovery Time
From de-assertion of power down mode to
output data available.
From de-assertion of sleep mode to output
data available.
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.
Note 2: All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to ±5 mA. The
±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10.
Note 4: Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0 Ω.
Note 5: Reflow temperature profiles are different for lead-free and non-lead-free packages.
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8
Note 6: Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not
guaranteed.
Note 7: The inputs are protected as shown below. Input voltage magnitudes above VA3.0 or below GND will not damage this device, provided current is limited
per (Note 3). However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section.
30062657
Note 8: The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.
Note 9: This parameter is specified in units of dBFS – indicating the equivalent value that would be attained with a full-scale input signal.
Note 10: ) This parameter is a function of the CLK frequency - increasing directly as the frequency is lowered. At frequencies less than 130 MHz, use the following
formulae to calculate the setup and hold times:
For Data and OR+/- Outputs:
Tsu = ½*Tp – 0.5 ns (typical)
Th = ½*Tp – 0.5 ns (typical)
For Data and OR+/- Outputs:
where Tp = CLK input period = OUTCLK period
Note 11: Input signal is sampled with the falling edge of the CLK input.
Note 12: This parameter is guaranteed only at 25°C. For power dissipation over temperature range, refer to Core Power vs. Temperature plot inTypical
Performance Characteristics, Dynamic Performance
9
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MSB (MOST SIGNIFICANT BIT) is the bit that has the largest
value or weight. Its value is one half of full scale.
Specification Definitions
APERTURE DELAY is the time after the falling edge of the
clock to when the input signal is acquired or held for conver-
sion.
NEGATIVE FULL SCALE ERROR is the difference between
the actual first code transition and its ideal value of ½ LSB
above negative full scale.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
OFFSET ERROR is the difference between the two input
voltages (VIN+ – VIN-) required to cause a transition from code
32767LSB and 32768LSB with offset binary data format.
CLOCK DUTY CYCLE is the ratio of the time during one cycle
that a repetitive digital waveform is high to the total time of
one period. The specification here refers to the ADC clock
input signal.
PIPELINE DELAY (LATENCY) See CONVERSION LATEN-
CY.
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 1½ LSB
below positive full scale.
COMMON MODE VOLTAGE (VCM) is the common DC volt-
age applied to both input terminals of the ADC.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the power of input signal to the total power of all other
spectral components below one-half the sampling frequency,
not including harmonics and DC.
CONVERSION LATENCY is the number of clock cycles be-
tween initiation of conversion and the time when data is
presented to the output driver stage. Data for any given sam-
ple is available at the output pins the Pipeline Delay plus the
Output Delay after the sample is taken. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
SIGNAL TO NOISE AND DISTORTION (SINAD) Is the ratio,
expressed in dB, of the power of the input signal to the total
power of all of the other spectral components below half the
clock frequency, including harmonics but excluding DC.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the power of input signal and
the peak spurious signal power, where a spurious signal is
any signal present in the output spectrum that is not present
at the input.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB, of the total power of the first seven harmonic
to the input signal power. THD is calculated as:
Gain Error = Positive Full Scale Error − Negative Full Scale
Error
It can also be expressed as Positive Gain Error and Negative
Gain Error, which are calculated as:
PGE = Positive Full Scale Error - Offset Error
NGE = Offset Error - Negative Full Scale Error
2
where f12 is the power of the fundamental frequency and f2
INTEGRAL NON LINEARITY (INL) is a measure of the de-
viation of each individual code from a best fit straight line. The
deviation of any given code from this straight line is measured
from the center of that code value.
through f82 are the powers of the first seven harmonics in the
output spectrum.
SECOND HARMONIC DISTORTION (2ND HARM or H2) is
the difference expressed in dB, from the power of its 2nd har-
monic level to the power of the input signal.
THIRD HARMONIC DISTORTION (3RD HARM or H3) is the
difference expressed in dB, from the power of the 3nd har-
monic level to the power of the input signal.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dBFS.
HIGHEST SPURIOUS EXCEPT H2 and H3 (Spur-H2/3) is
the difference, expressed in dB, between the power of input
signal and the peak spurious signal power except H2 and H3,
where a spurious signal is any signal present in the output
spectrum that is not present at the input.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-
est value or weight of all bits. This value is VFS/2n, where
“VFS” is the full scale input voltage and “n” is the ADC reso-
lution in bits.
MISSING CODES are those output codes that will never ap-
pear at the ADC outputs. The ADC16V130 is guaranteed not
to have any missing codes.
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10
Timing Diagrams
30062603
Digital Output Timing
Transfer Characteristic
30062699
Transfer Characteristic (Offset Binary Format)
11
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Typical Performance Characteristics, DNL, INL
Unless otherwise noted, these specifications apply: VA3.0= +3.0V, VA1.8, VAD1.8, VDR = 1.8V, fCLK = 130 MSPS. Differential Clock
Mode, Offset Binary Format. LVDS Rterm = 100 Ω. CL = 5 pF. Typical values are at TA = +25°C. Fin = 10MHz with –1dBFS.
DNL
INL
30062641
30062642
DNL vs.VA3.0
INL vs .VA3.0
30062611
30062612
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12
Typical Performance Characteristics, Dynamic Performance
Unless otherwise noted, these specifications apply: VA3.0= +3.0V, VA1.8, VAD1.8, VDR = 1.8V, fCLK = 130 MSPS. Differential Clock
Mode, Offset Binary Format. LVDS Rterm = 100 Ω. CL = 5 pF. Typical values are at TA = +25°C. Fin = 160MHz with –1dBFS..
SNR, SINAD, SFDR vs. fIN
SNR, SINAD, SFDR vs. VA3.0
SNR, SINAD, SFDR vs. VAD1.8
DISTORTION vs. fIN
DISTORTION vs. VA3.0
DISTORTION vs. VAD1.8
30062613
30062614
30062616
30062618
30062615
30062617
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Spectral Response @ 10.11 MHz
Spectral Response @ 40.11 MHz
Spectral Response @ 70.11 MHz
Spectral Response @ 160.11 MHz
30062619
30062620
Spectral Response @ 240.11 MHz
30062621
30062622
Core Power vs. Temperature (Excludes IDR
)
30062623
30062624
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14
VCM = 1.15V (from VRM
)
Functional Description
2.0 ANALOG INPUTS
Operating on dual +1.8 and +3.0V supplies, the ADC16V130
digitizes a differential analog input signals to 16 bits, using a
differential pipelined architecture with error correction circuitry
and an on-chip sample-and-hold circuit to ensure maximum
performance. The user has the choice of using an internal
1.2V stable reference, or using an external 1.2V reference.
Internal 1.2V reference has high output impedance of
> 9 kΩ and can be easily over-driven by external reference.
Two multi-level multi-function pins can program data format,
clock mode, power down and sleep mode.
Analog input circuit of the ADC16V130 is a differential
switched capacitor sample-and-hold circuit (see Figure 1) that
provides optimum dynamic performance wide input frequency
range with minimum power consumption. The clock signal al-
ternates sample mode (QS) and hold mode (QH). An integrat-
ed low jitter duty cycle stabilizer ensures constant optimal
sample and hold time over wide range of input clock duty cy-
cle. The duty cycle stabilizer is always turned on during
normal operation.
During sample mode, analog signals (VIN+, VIN-) are sampled
across two sampling capacitor (CS) while the amplifier in the
sample-and-hold circuit is idle. The dynamic performance of
the ADC16V130 is likely determined during sampling mode.
The sampled analog inputs (VIN+, VIN-) are held during hold
mode by connecting input side of the sampling capacitors to
output of the amplifier in the sample-and-hold circuit while
driving pipeline ADC core.
ADC Architecture
The ADC16V130 architecture consists of a highly linear and
wide bandwidth sample-and-hold circuit, followed by a
switched capacitor pipeline ADC. Each stage of the pipeline
ADC consists of low resolution flash sub-ADC and an inter-
stage multiplying digital-to-analog converter (MDAC), which
is a switched capacitor amplifier with a fixed stage signal gain
and DC level shifting circuits. The amount of DC level shifting
is dependent on sub-ADC digital output code. 16bit final dig-
ital output is the result of the digital error correction logic,
which receives digital output of each stage including redun-
dant bits to correct offset error of each sub-ADC.
The signal source, which drives the ADC16V130, is recom-
mended to have source impedance less than 100 Ω over wide
frequency range for optimal dynamic performance.
A shunt capacitor can be placed across the inputs to provide
high frequency dynamic charging current during sample
mode and also absorb any switching charge coming from the
ADC16V130. A shunt capacitor can be placed across each
input to GND for similar purpose. Smaller physical size and
low ESR and ESL shunt capacitor is recommended.
Applications Information
1.0 OPERATING CONDITIONS
The value of shunt capacitor should be carefully chosen to
optimize the dynamic performance at certain input frequency
range. Larger value shunt capacitors can be used for low input
frequency range, but the value has to be reduced at high input
frequency range.
We recommend that the following conditions be observed for
operation of the ADC16V130:
2.7V ≤ VA3.0 ≤ 3.6V
1.7V ≤ VA1.8 ≤ 1.9V
1.7V ≤ VAD1.8 ≤ 1.9V
1.7V ≤ VDR ≤ 1.9V
5 MSPS ≤ FCLK ≤ 130 MSPS
VREF ≤ 1.2V
Balancing impedance at positive and negative input pin over
entire signal path must be ensured for optimal dynamic per-
formance.
30062606
FIGURE 1. Simplified Switched-Capacitor Sample-and-hold Circuit
2.1 Input Common Mode
voltage (VRM, typically 1.15V) as input common mode for op-
timal dynamic performance regardless of DC and AC coupling
applications. Input common mode signal must be decoupled
with low ESL 0.1μF at the far end of load point to minimize
The analog inputs of the ADC16V130 are not internally dc
biased and the range of input common mode is very narrow.
Hence it is highly recommended to use the common mode
15
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noise performance degradation due to any coupling or switch-
ing noise between the ADC16V130 and input driving circuit.
and drive the ADC16V130 without additive noise. An example
is shown in Figure 2. VRM pin is used to bias the input common
mode by connecting the center tap of the transformer’s sec-
ondary ports. Flux transformer is used for this example, but
AC coupling capacitors should be added once balun type
transformer is used.
2.2 Driving Analog Inputs
For low frequency applications, either a flux or balun trans-
former can convert single-ended input signal into differential
30062607
FIGURE 2. Transformer Drive Circuit for Low Input Frequency
Transformer has a characteristic of band pass filtering. It sets
lower band limit by being saturated at frequencies below a
few MHz and sets upper frequency limit due to its parasitic
resistance and capacitance. The transformer core will be sat-
urated with excessive signal power and it causes distortion as
equivalent load termination becomes heavier at high input
frequencies. This is a reason to reduce shunt capacitors for
high IF sampling application to balance the amount of distor-
tion caused by transformer and charge kick-back noise from
the device.
the other is connected to GND. Distortion increases as the
result.
Cascaded transmission line transformers can be used for
high frequency applications like high IF sampling base station
receiver channel. Transmission line transformer has less
stray capacitance between primary and secondary ports and
so the amount of impedance at secondary ports is effectively
less even with the given inherent impedance mismatch on the
primary ports. Cascading two transmission line transformers
further reduces the effective stray capacitance from the sec-
ondary of ports of the secondary transformer to primary ports
of first transformer, where impedance is mismatched. A trans-
mission line transformer, for instance MABACT0040 from
M/A-COM, with center tap on secondary port could further
reduce amplitude and phase mismatch.
As input frequency goes higher with the input network in Fig-
ure 3, amplitude and phase unbalance increase between
positive and negative inputs (VIN+ and VIN-) due to the inherent
impedance mismatch between the two primary ports of the
transformer while one is connected to the signal source and
30062608
FIGURE 3. Transformer Drive Circuit for High Input Frequency
2.3 Equivalent Input Circuit and Its S11
pipeline ADC core. Equivalent impedance changes drastically
between sample and hold mode while significant amount of
charge injection occurs during the transition between the two
operating modes.
Input circuit of the ADC16V130 during sample mode is a dif-
ferential switched capacitor as shown in Figure 4. Bottom
plate sampling switch is bootstrapped in order to reduce its
turn on impedance and its variation across input signal am-
plitude. Bottom plate sampling switches and top plate sam-
pling switch are all turned off during hold mode. The sampled
analog input signal is processed throughout the following
Distortion and SNR heavily rely on the signal integrity,
impedance matching during sample mode and charge injec-
tion while switching sampling switches.
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16
30062609
FIGURE 4. Input Equivalent Circuit
A measured S11 of the input circuit of the ADC16V130 is
shown in Figure 5 (Currently the figure is a simulated one. It
is subject to be changed later. Note that the simulated S11
closely matches with the measured S11). Up to 500 MHz, it
is predominantly capacitive loading with small stray resis-
tance and inductance as shown in Figure 5. An appropriate
resistive termination at a given input frequency band has to
be added to improve signal integrity. Any shunt capacitor on
analog input pin deteriorates signal integrity but it provides
high frequency charge to absorb the charge inject generated
while sampling switches are toggling. A optimal shunt capac-
itor is dependent on input signal frequency as well as
impedance characteristic of analog input signal path including
components like transformer, termination resistor, DC cou-
pling capacitors.
30062630
FIGURE 5. S11 Curve of Input Circuit
3.0 CLOCK INPUT CONSIDERATIONS
3.1 Clock Input Modes
A preferred differential clocking through a transformer cou-
pled is shown in Figure 7. A 0.1μF decoupling capacitor on
the center tap of the secondary ports of a flux type transformer
stabilizes clock input common mode. Differential clocking in-
creases the maximum amplitude of the clock input at the pins
twice as large as that with singled-ended mode as shown in
Figure 8. Clock amplitude is recommended to be as large as
possible while CLK+ and CLK- both never exceed supply rails
of VA1.8 and AGND. With a given equivalent input noise of the
differential clock receiver shown in Figure 6, larger clock am-
plitude at CLK+ and CLK- pins increases its slope around
zero-crossing point so that higher signal-to-noise could be
obtained by reducing the noise contributed by clock signal
path.
The ADC16V130 provides a low additive jitter differential
clock receiver for optimal dynamic performance at wide input
frequency range. Input common mode of the clock receiver is
internally biased at VA1.8/2 through a 10 kΩ each to be driven
by DC coupled clock input as shown in Figure 6. However
while DC coupled clock input drives CLK+ and CLK-, it is rec-
ommend the common mode (average voltage of CLK+ and
CLK-) not to be higher than VA1.8/2 in order to prevent sub-
stantial tail current reduction, which might cause lowered jitter
performance. Meanwhile, CLK+ and CLK- should not become
lower than AGND. A high speed back-to-back diode connect-
ed between CLK+ and CLK- could limit the maximum swing,
but this could cause signal integrity concerns when the diode
turns on and reduce load impedance instantaneously.
17
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30062631
FIGURE 6. Equivalent Clock Receiver
The differential receiver of the ADC16V130 has excellent low
noise floor but its bandwidth is wide as multiple times of clock
rate. The wide band noise folds back to nyquist frequency
band in frequency domain at ADC output. Increased slope of
the input clock lowers the equivalent noise contributed by the
differential receiver.
Load termination could be a combination of R and C instead
of a pure R. This RC termination could improve noise perfor-
mance of clock signal path by filtering out high frequency
noise through a low pass filter. The size of R and C is depen-
dent on the clock rate and slope of the clock input.
A LVPECL and/or LVDS driver could also drive the AD-
C16V130. However the full dynamic performance of the AD-
C16V130 might not be achieved due to the high noise floor of
the driving circuit itself especially in high IF sampling appli-
cation.
A band-pass filter (BPF) with narrow pass band and low in-
sertion loss could be added on the clock input signal path
when wide band noise of clock source is noticeably large
compared to the input equivalent noise of the differential clock
receiver.
30062632
FIGURE 7. Differential Clocking, Transformer Coupled
Singled-ended clock can drive CLK+ pin through a 0.1μF AC
coupling capacitor while CLK- is decoupled to AGND through
a 0.1μF capacitor as shown in Figure 8.
30062633
FIGURE 8. Singled-ended 1.8V Clocking, Capacitive AC Coupled
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18
3.2 Duty Cycle Stabilizer
Highest operating speed with optimal performance could be
only achieved with 50% of clock duty cycle because the
switched-capacitor circuit of the ADC16V130 is designed to
have equal amount of settling time between each stage. The
maximum operating frequency could be reduced accordingly
while clock duty cycle departs from 50%.
The ADC16V130 contains a duty cycle stabilizer that adjusts
non-sampling (rising) clock edge to make the duty cycle of the
internal clock over 30 to 70% of input clock duty cycle. The
duty cycle stabilizer is always on because the noise and dis-
tortion performance are not affected at all. It is not recom-
mended to use the ADC16V130 at the clock frequencies less
than 5 MSPS, at which the feedback loop in the duty cycle
stabilizer becomes unstable.
3.3 Clock Jitter vs. Dynamic Performance
High speed and high resolution ADCs require low noise clock
input to ensure its full dynamic performance over wide input
frequency range. SNR (SNRFin) at a given input frequency
(Fin) can be calculated by:
30062635
FIGURE 9. SNR with given Jitter vs. Input Frequency
4.0 CALIBRATION
Automatic calibration engine contained within the AD-
C16V130 improves dynamic performance and reduces its
part-to-part variation. Digital output signals including output
clock (OUTCLK+/-) are all logic low while calibrating. The AD-
C16V130 is automatically calibrated when the device is pow-
ered up. Optimal dynamic performance might not be obtained
if power-up time is longer than internal delay time (~32mS @
130 MSPS clock rate). In this case, the ADC16V130 could be
re-calibrated by asserting and then de-asserting power down
mode. Re-calibration is recommended whenever operating
clock rate changes.
30062634
with a given total noise power (VN2) of an ADC, total rms jitter
(Tj), and input amplitude (A) in dBFS.
Clock signal path must be treated as an analog signal when-
ever aperture jitter affects the dynamic performance of the
ADC16V130. Power supplies for the clock drivers has to be
separated from the ADC output drive supplies to prevent
modulated clock signal with the ADC digital output signals.
Higher noise floor and/or increased distortion/spur might re-
sult from any coupling noise from ADC digital output signals
to analog input and clock signals.
5.0 VOLTAGE REFERENCE
A stable and low noise voltage reference and its buffer am-
plifier are built into the ADC16V130. The input full scale is two
times of VREF, which is same as VBG (On-chip bandgap out-
put having 9 kΩ output impedance) as well as VRP - VRN as
shown in Figure 10. The input range can be adjusted by
changing VREF either internally or externally. An external ref-
erence with low output impedance can easily over-drive
VREF pin. Default VREF is 1.2V. Input common mode voltage
(VRM) is a fixed voltage level of 1.15V. Maximum SNR can be
achieved at maximum input range of 1.2V VREF. Although the
ADC16V130 dynamic and static performance is optimized at
VREF of 1.2V, reducing VREF can improve SFDR performance
with sacrificing SNR of the ADC16V130.
In IF sampling applications, the signal-to-noise ratio is partic-
ularly affected by clock jitter as shown in Figure 9. Tj is the
integrated noise power of the clock signal divided by the slope
of clock signal around tripping point. Upper limit of the noise
integration is independent of applications and set by the band-
width of the clock signal path. However lower limit of the noise
integration highly relies on the applications. In base station
receiver channel applications, the lower limit is determined by
channel bandwidth and space from an adjacent channel.
5.1 Reference Decoupling
It is highly recommended to place external decoupling ca-
pacitors connected to VRP, VRN, VRM and VREF pins as close
to pins as possible. The external decoupling capacitor should
have minimal ESL and ESR. During normal operation, inap-
propriate external decoupling with large ESL and/or ESR
capacitors increase settling time of ADC core and results in
lower SFDR and SNR performance. VRM pin may be loaded
up to 1mA for setting input common mode. The remaining pins
should not be loaded. Smaller capacitor values might result
in degraded noise performance. Decoupling capacitor on
VREF pin must not exceed 0.1μF, heavier decoupling on this
pin will cause improper calibration during power-up. All refer-
ence pins except VREF have very low output impedance.
Driving these pins via low output impedance external circuit
for long time period might damage the device.
19
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30062636
FIGURE 10. Internal References and their Decoupling
While VRM pin is used to set input common mode level via
transformer, a smaller serial resistor could be placed on the
signal path to isolate any switching noise interfering between
ADC core and input signal. The serial resistor introduces volt-
age error between VRM and VCM due to charge injection while
sampling switches toggling. The serial resistance should not
be larger than 50 Ω.
All grounds associated with each reference and analog input
pins should be connected to a solid and quite ground on PC
board. Coupling noise from digital outputs and their supplies
to the reference pins and their ground can cause degraded
SNR and SFDR performance.
This is because of the skin effect. Total surface area is more
important than its total ground plane area.
Generally, analog and digital lines should not be crossing
each. However whenever it is inevitable, make sure that these
lines are crossing each other at 90° to minimize cross talk.
Digital output and output clock signals must be separated
from analog input, references and clock signals uncondition-
ally to ensure the maximum performance from ADC16V130.
Any coupling might result degraded SNR and SFDR perfor-
mance especially at high IF applications.
Be especially careful with the layout of inductors and trans-
formers. Mutual inductance can change the characteristics of
the circuit in which they are used. Inductors and transformers
should not be placed side by side, even with just a small part
of their bodies beside each other. For instance, place trans-
formers for the analog input and the clock input at 90° to one
another to avoid magnetic coupling. It is recommended to
place the transformers of input signal path on the top plate,
but the transformer of clock signal path on the bottom plate.
Every critical analog signal path like analog inputs and clock
inputs must be treated as a transmission line and should have
a solid ground return path with a small loop.
6.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-
tial to ensure accurate conversion. Maintaining separate ana-
log and digital areas of the board, with the ADC16V130
between these areas, is required to achieve specified perfor-
mance.
Even though LVDS output reduces ground bounding during
its transition, the positive and negative signal path has to be
well matched and their trace should be kept as short as pos-
sible. It is recommend to place LVDS repeater between the
ADC16V130 and digital data receiver block to isolate coupling
noise from receiving block while the length of the traces are
long or the noise level of the receiving block is high.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected between
the converter’s input pins and ground or to the reference pins
and ground should be connected to a very clean point in the
ground plane. All analog circuitry (input amplifiers, filters, ref-
erence components, etc.) should be placed in the analog area
of the board. All digital circuitry and dynamic I/O lines should
be placed in the digital area of the board. The ADC16V130
should be between these two areas. Furthermore, all compo-
nents in the reference circuitry and the input signal chain that
are connected to ground should be connected together with
short traces and enter the ground plane at a single, quiet
Capacitive coupling between the typically noisy digital circuit-
ry and the sensitive analog circuitry can lead to poor perfor-
mance. The solution is to keep the analog circuitry separated
from the digital circuitry, and to keep the clock line as short as
possible.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
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20
point. All ground connections should have a low inductance
path to ground.
lower SFDR and noise performance. When VA1.8 and VDR are
both from same supply source, coupling noise can be miti-
gated by adding ferrite-bead on VDR supply path.
Ground return current path can be well managed when supply
current path is precisely controlled and ground layer is con-
tinuous and placed next to the supply layer. This is because
of the proximity effect. Ground return current path with a large
loop will cause electro-magnetic coupling and results in poor
noise performance. Not that even if there is a large plane for
a current path, high frequency current path is not spread
evenly over the large plane, but only takes a path with lowest
impedance. Instead of large plane, using thick trace for sup-
plies makes it easy to control return current path. It is recom-
mended to place supply next to GND layer with thin dielectric
for smaller ground return loop. Proper location and size of
decoupling capacitors provide short and clean return current
path.
The user can use different decoupling capacitors to provide
current over wide frequency range. The decoupling capaci-
tors should be located close to the point of entry and close to
the supply pins with minimal trace length. A single ground
plane is recommended because separating ground under the
ADC16V130 could cause unexpected long return current
path.
VA3.0 supply must turn on before VA1.8 and/or VDR reaches
single diode turn-on voltage level. If this supply sequence is
reversed, excessive amount of current will flow through
VA3.0 supply. Ramp rate of VA3.0 supply must be kept less than
60V/mS (i.e., 60μS for 3.0V supply) in order to prevent ex-
cessive surge current through ESD protection devices.
The exposed pad (Pin #0) on the bottom of the package
should be soldered to AGND in order to get optimal noise
performance. The exposed pad is a solid ground for the de-
vice and also is heat sinking path.
7.0 SUPPLIES AND THEIR SEQUENCE
There are four supplies for the ADC16V130; one 3.0V supply
VA3.0 and three 1.8V supplies VA1.8, VAD1.8 and VDR. It is rec-
ommended to separate VDR from VA1.8 supplies, any coupling
from VDR to rest of supplies and analog signals could cause
21
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Physical Dimensions inches (millimeters) unless otherwise noted
64-Lead LLP Package
Ordering Number ADC16V130CISQ
NS Package Number SQA64A
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22
Notes
23
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