8601101EA [TI]
High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs; 高速CMOS逻辑十进制计数器/除法器10解码输出
| 型号： | 8601101EA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs |
| 文件： | 总14页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC4017, CD74HC4017
Data sheet acquired from Harris Semiconductor
SCHS200D
High-Speed CMOS Logic
Decade Counter/Divider with 10 Decoded Outputs
November 1997 - Revised October 2003
Features
Description
The ’HC4017 is a high speed silicon gate CMOS 5-stage
Johnson counter with 10 decoded outputs. Each of the
decoded outputs is normally low and sequentially goes high
on the low to high transition clock period of the 10 clock
period cycle. The CARRY (TC) output transitions low to high
after OUTPUT 10 goes from high to low, and can be used in
conjunction with the CLOCK ENABLE (CE) to cascade
several stages. The CLOCK ENABLE input disables
counting when in the high state. A RESET (MR) input is also
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Positive Edge Clocking
[ /Title
(CD74
HC401
7)
/Sub-
ject
(High
Speed
CMOS
Logic
Decade
Counte
o
• Typical f
MAX
= 50MHz at V = 5V, C = 15pF, T = 25 C
CC L A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads provided which when taken high sets all the decoded
outputs, except “0”, low.
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
The device can drive up to 10 low power Schottky equivalent
loads.
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
• Significant Power Reduction Compared to LSTTL
Logic ICs
TEMP. RANGE
o
• HC Types
PART NUMBER
CD54HC4017F3A
CD74HC4017E
( C)
PACKAGE
16 Ld CERDIP
16 Ld PDIP
- 2V to 6V Operation
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
CD74HC4017M
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
CD74HC4017MT
CD74HC4017M96
CD74HC4017NSR
CD74HC4017PW
CD74HC4017PWR
16 Ld TSSOP
16 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Pinout
CD54HC4017 (CERDIP)
CD74HC4017 (PDIP, SOIC, SOP, TSSOP)
TOP VIEW
5
1
2
3
4
5
6
7
8
16 V
CC
1
15 MR
14 CP
13 CE
12 TC
11 9
0
2
6
7
10 4
3
9
8
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC4017, CD74HC4017
Functional Diagram
3
0
2
14
1
CLOCK
4
13
2
3
4
5
6
7
8
9
CLOCK
7
ENABLE
10
1
15
MASTER
RESET
5
6
9
11
12
TERMINAL
COUNT
TRUTH TABLE
CP
L
CE
X
H
X
L
MR
L
OUTPUT STATE †
No Change
No Change
X
X
↑
L
H
L
“0” = H, “1”-”9” = L
Increments Counter
No Change
↓
X
↑
L
X
H
L
No Change
↓
L
Increments Counter
H = High Level
L = Low Level
↑ = High to Low Transition
↓ = Low to High Transition
X = Don’t Care.
† If n < 5 TC = H, Otherwise = L
2
CD54HC4017, CD74HC4017
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Package Thermal Impedance, θ (see Note 1):
JA
CC
DC Input Diode Current, I
For V < -0.5V or V > V
o
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 C/W
PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . .108 C/W
IK
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
O
o
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
o
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
V
O
High Level Input
Voltage
V
-
-
2
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
IH
4.5
6
3.15
-
-
3.15
-
-
3.15
V
4.2
4.2
4.2
-
V
Low Level Input
Voltage
V
-
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
V
IL
4.5
6
-
-
-
V
-
-
-
V
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
V
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
V
5.9
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
V
-4
4.5
6
3.98
-
3.84
-
3.7
-
V
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
V
OL
4.5
6
V
V
Low Level Output
Voltage
TTL Loads
-
V
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
V
5.2
-
V
Input Leakage
Current
I
V
or
6
µA
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD54HC4017, CD74HC4017
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
Maximum Clock
SYMBOL CONDITIONS (V)
MIN
6
TYP
MAX
MIN
5
MAX
MIN
4
MAX
UNITS
MHz
MHz
MHz
ns
f
-
-
-
-
-
-
2
4.5
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
Frequency
30
35
80
16
14
80
16
14
75
15
13
0
35
49
100
20
17
100
20
17
95
19
16
0
20
23
120
24
20
120
24
20
110
22
19
0
CP Pulse Width
t
t
2
W
W
4.5
6
ns
ns
MR Pulse Width
2
ns
4.5
6
ns
ns
Set-up Time,
CE to CP
t
2
ns
SU
4.5
6
ns
ns
Hold Time,
CE to CP
t
2
ns
H
4.5
6
0
0
0
ns
0
0
0
ns
MR Removal Time
t
2
5
5
5
ns
REM
4.5
6
5
5
5
ns
5
5
5
ns
Switching Specifications Input t , t = 6ns
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
Propagation Delay
MIN TYP MAX MIN
MAX
290
58
MIN
MAX UNITS
t
t
t
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
230
46
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
345
69
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH,
L
t
PHL
CP to any Dec. Out
C = 50pF
L
C = 15pF
19
-
-
L
C = 50pF
6
39
230
46
-
49
59
345
69
-
L
CP to TC
C = 50pF
2
-
290
58
PLH,
L
t
PHL
C = 50pF
4.5
5
-
L
C = 15pF
19
-
-
L
C = 50pF
6
39
250
49
59
375
L
CE to any Dec. Out
C = 50pF
-
315
PLH,
L
t
2
4.5
5
PHL
C = 50pF
-
-
-
-
-
-
-
-
21
-
50
-
-
-
-
-
-
-
-
63
-
-
-
-
-
-
-
-
75
-
ns
ns
ns
ns
ns
ns
ns
L
C = 15pF
L
C = 50pF
6
43
250
50
-
54
315
63
-
64
375
75
-
L
CE to TC
t
t
C = 50pF
2
-
PLH,
L
PHL
C = 50pF
4.5
5
-
L
C = 15pF
21
-
L
C = 50pF
6
43
54
64
L
4
CD54HC4017, CD74HC4017
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
MIN TYP MAX MIN
MAX
MIN
MAX UNITS
MR to any Dec. Out
t
t
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
230
46
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
290
58
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
345
69
-
ns
ns
PLH,
L
PHL
C = 50pF
L
C = 15pF
19
-
ns
L
C = 50pF
6
39
230
46
-
49
290
58
-
59
345
69
-
ns
L
MR to TC
t
t
C = 50pF
2
-
ns
PLH,
L
PHL
C = 50pF
4.5
5
-
ns
L
C = 15pF
19
-
ns
L
C = 50pF
6
39
75
15
13
10
-
49
95
19
16
10
-
59
110
22
19
10
-
ns
L
Transition Time TC, Dec. Out
t
, t
C = 50pF
2
-
ns
TLH THL
L
C = 50pF
4.5
6
-
ns
L
C = 50pF
-
ns
L
Input Capacitance
C
C = 50pF
-
-
pF
MHz
pF
IN
L
Maximum CP Frequency
f
C = 15pF
5
60
39
MAX
L
Power Dissipation Capacitance
(Notes 2, 3)
C
C = 15pF
5
-
-
-
PD
L
NOTES:
2. C
is used to determine the dynamic power consumption, per package.
PD
3. P = V
2
2
f Σ€ C
V
fo where f = input frequency, f = output frequency, C = output load capacitance, V
= supply voltage.
CC
D
CC
i
L
CC
i
o
L
Test Circuits and Waveforms
t = 6ns
t = 6ns
f
r
I
t
+ t
=
WL
WH
V
CC
t C
fC
t C
f
L
L
90%
50%
10%
r
L
INPUT
V
CC
90%
10%
CLOCK
GND
50%
10%
50%
t
50%
GND
t
t
TLH
THL
t
WH
WL
90%
50%
10%
INVERTING
OUTPUT
NOTE: Outputs should be switching from 10% V
to 90% V
in
t
PLH
t
CC
CC
PHL
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
CD54HC4017, CD74HC4017
Test Circuits and Waveforms (Continued)
t C
t C
f
L
r
L
V
CC
90%
10%
CLOCK
INPUT
50%
GND
t
t
H(H)
H(L)
V
CC
DATA
INPUT
50%
GND
t
t
SU(H)
SU(L)
t
t
90%
50%
TLH
THL
90%
OUTPUT
10%
t
t
PHL
PLH
t
REM
V
CC
SET, RESET
OR PRESET
50%
GND
IC
C
L
50pF
FIGURE 3. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED
SEQUENTIAL LOGIC CIRCUITS
Timing Diagrams
CLOCK
MASTER
RESET
CLOCK
ENABLE
C
C
L
“0”
“1”
“2”
“3”
“4”
“5”
“6”
“7”
“8”
“9”
L
0
0
1
P
N
P
N
1
D
Q
Q
2
2
C
L
3
C
C
L
L
C
L
4
C
C
L
C
P N
L
P
N
5
6
C
L
7
8
R
9
TERMINAL
COUNT
FF DETAIL
FIGURE 4.
FIGURE 5.
6
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
PDIP
Drawing
8601101EA
CD54HC4017F3A
CD74HC4017E
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
1
1
TBD
TBD
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC4017EE4
CD74HC4017M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
N
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4017M96
CD74HC4017M96E4
CD74HC4017ME4
CD74HC4017MT
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4017MTE4
CD74HC4017NSR
CD74HC4017NSRE4
CD74HC4017PW
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
NS
PW
PW
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4017PWE4
CD74HC4017PWR
CD74HC4017PWRE4
CD74HC4017PWT
CD74HC4017PWTE4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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