8409501FA [TI]
8-BIT PARALLEL-LOAD SHIFT REGISTERS; 8位并联负载移位寄存器![8409501FA](http://pdffile.icpdf.com/pdf1/p00026/img/icpdf/8409501_133769_icpdf.jpg)
型号: | 8409501FA |
厂家: | ![]() |
描述: | 8-BIT PARALLEL-LOAD SHIFT REGISTERS |
文件: | 总19页 (文件大小:576K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢂ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢇꢂ
ꢋꢌꢍ ꢎ ꢏꢐꢑꢐ ꢒꢒ ꢓꢒ ꢋꢒ ꢔ ꢐꢕ ꢀꢄꢍ ꢖ ꢎ ꢑꢓꢗ ꢍ ꢀ ꢎꢓ ꢑꢀ
ꢊ
SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
D
D
D
D
D
Low Input Current of 1 µA Max
Complementary Outputs
Low Power Consumption, 80-µA Max I
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
CC
Typical t = 13 ns
pd
4-mA Output Drive at 5 V
Parallel-to-Serial Data Conversion
SN54HC165 . . . FK PACKAGE
(TOP VIEW)
SN54HC165 . . . J OR W PACKAGE
SN74HC165 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
SH/LD
CLK
E
V
CC
CLK INH
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D
C
B
A
3
2
1
20 19
18
E
F
D
4
5
6
7
8
F
G
H
C
17
16
15
14
NC
G
NC
B
Q
SER
H
H
A
GND
Q
H
9 10 11 12 13
NC − No internal connection
description/ordering information
The ’HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (Q )
H
output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled
by a low level at the shift/load (SH/LD) input. The ’HC165 devices also feature a clock-inhibit (CLK INH) function
and a complementary serial (Q ) output.
H
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube of 25
Tube of 40
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HC165N
SN74HC165N
SN74HC165D
SN74HC165DR
SN74HC165DT
SN74HC165NSR
SN74HC165DBR
SN74HC165PW
SN74HC165PWR
SN74HC165PWT
SNJ54HC165J
HC165
SOP − NS
HC165
HC165
−40°C to 85°C
SSOP − DB
TSSOP − PW
HC165
CDIP − J
CFP − W
LCCC − FK
SNJ54HC165J
SNJ54HC165W
SNJ54HC165FK
SNJ54HC165W
SNJ54HC165FK
−55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢀꢁ ꢉ ꢃ ꢄꢅꢆ ꢇ ꢂ
ꢊꢋ ꢌꢍ ꢎ ꢏꢐ ꢑ ꢐꢒ ꢒ ꢓ ꢒꢋꢒ ꢔꢐ ꢕ ꢀ ꢄꢍ ꢖꢎ ꢑꢓ ꢗ ꢍꢀ ꢎꢓ ꢑꢀ
SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003
description/ordering information (continued)
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK
INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high
transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK
is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the
register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
FUNCTION TABLE
INPUTS
FUNCTION
SH/LD
CLK CLK INH
L
X
H
X
L
X
X
H
↑
L
Parallel load
No change
No change
H
H
H
H
†
Shift
†
Shift
↑
†
Shift = content of each internal register shifts
toward serial output Q . Data at SER is
H
shifted into the first register.
logic diagram (positive logic)
A
B
C
D
E
F
G
H
11
12
13
14
3
4
5
6
1
SH/LD
9
15
2
Q
H
CLK INH
CLK
S
C1
S
C1
S
C1
S
C1
S
C1
S
C1
S
C1
S
C1
10
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
SER
7
Q
H
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
2
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ꢊ
SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003
typical shift, load, and inhibit sequence
CLK
CLK INH
SER
L
SH/LD
A
H
L
B
C
H
Data
Inputs
L
D
E
H
F
L
H
H
G
H
H
L
H
L
L
H
L
H
L
L
H
L
Q
Q
H
H
H
L
H
H
Inhibit
Serial Shift
Load
3
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢀꢁ ꢉ ꢃ ꢄꢅꢆ ꢇ ꢂ
ꢊꢋ ꢌꢍ ꢎ ꢏꢐ ꢑ ꢐꢒ ꢒ ꢓ ꢒꢋꢒ ꢔꢐ ꢕ ꢀ ꢄꢍ ꢖꢎ ꢑꢓ ꢗ ꢍꢀ ꢎꢓ ꢑꢀ
SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC165
MIN NOM
SN74HC165
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
‡
= 4.5 V
= 6 V
∆t/∆v
Input transition rise/fall time
ns
T
A
Operating free-air temperature
−55
−40
°C
NOTE 3: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
‡
If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V
IL IH
= 2 V does not damage the device; however, functionally,
t
CC
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢂ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢇꢂ
ꢊ ꢋꢌꢍ ꢎ ꢏꢐꢑꢐ ꢒꢒ ꢓꢒ ꢋꢒ ꢔ ꢐꢕ ꢀꢄꢍ ꢖ ꢎ ꢑꢓꢗ ꢍ ꢀ ꢎꢓ ꢑꢀ
SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC165
SN74HC165
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= −20 µA
OH
5.9
V
V
V = V or V
IH
V
OH
OL
I
IL
I
I
= −4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= −5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
8
0.1
0.1
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
0.1
V = V or V
V
I
IH
IL
I
I
= 4 mA
4.5 V
6 V
0.4
0.33
0.33
1000
80
OL
= 5.2 mA
0.4
OL
I
I
V = V
I
or 0
6 V
1000
160
10
nA
µA
pF
I
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
CC
C
2 V to 6 V
3
10
10
i
5
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SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC165
SN74HC165
A
V
UNIT
CC
MIN
MAX
6
MIN
MAX
4.2
21
MIN
MAX
5
2 V
4.5 V
6 V
31
25
f
Clock frequency
Pulse duration
MHz
clock
36
25
29
2 V
80
16
14
80
16
14
80
16
14
40
8
120
24
20
120
24
20
120
24
20
60
12
10
150
30
25
60
12
10
150
30
26
5
100
20
17
100
20
17
100
20
17
50
10
9
4.5 V
6 V
SH/LD low
t
w
ns
ns
ns
2 V
4.5 V
6 V
CLK high or low
2 V
4.5 V
6 V
SH/LD high before CLK↑
SER before CLK↑
2 V
4.5 V
6 V
7
2 V
100
20
17
40
8
125
25
21
50
10
9
4.5 V
6 V
t
su
Setup time
CLK INH low before CLK↑
CLK INH high before CLK↑
Data before SH/LD↓
SER data after CLK↑
PAR data after SH/LD↓
2 V
4.5 V
6 V
7
2 V
100
20
17
5
125
25
21
5
4.5 V
6 V
2 V
4.5 V
6 V
5
5
5
5
5
5
t
h
Hold time
2 V
5
5
5
4.5 V
6 V
5
5
5
5
5
5
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
13
50
62
80
20
16
75
15
13
75
15
13
38
8
SN54HC165
SN74HC165
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
6
MAX
MIN
4.2
21
MAX
MIN
5
MAX
2 V
4.5 V
6 V
31
36
25
29
f
t
t
MHz
max
pd
t
25
2 V
150
30
225
45
190
38
4.5 V
6 V
SH/LD
CLK
H
Q
Q
Q
or Q
or Q
or Q
H
H
H
H
H
H
26
38
32
2 V
150
30
225
45
190
38
4.5 V
6 V
ns
ns
26
38
32
2 V
150
30
225
45
190
38
4.5 V
6 V
26
38
32
2 V
75
110
22
95
Any
4.5 V
6 V
15
19
6
13
19
16
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
75
pF
pd
7
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SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
50%
50%
50%
Pulse
From Output
Under Test
Test
Point
0 V
t
w
C
= 50 pF
L
V
CC
Low-Level
Pulse
(see Note A)
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
PLH
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
84095012A
8409501EA
8409501FA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
16
16
16
16
1
1
1
1
TBD
TBD
TBD
TBD
Call TI
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Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
J
SN54HC165J
SN74HC165D
CDIP
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC165DBR
SN74HC165DBRE4
SN74HC165DE4
SN74HC165DR
SN74HC165DRE4
SN74HC165DT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
DB
DB
D
16
16
16
16
16
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC165DTE4
SN74HC165N
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74HC165N3
SN74HC165NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
16
16
TBD
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Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74HC165NSR
SN74HC165NSRE4
SN74HC165PW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
NS
NS
PW
PW
16
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC165PWG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC165PWLE
SN74HC165PWR
OBSOLETE TSSOP
PW
PW
16
16
TBD
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ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC165PWRG4
SN74HC165PWT
PW
PW
PW
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC165PWTE4
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54HC165FK
SNJ54HC165J
SNJ54HC165W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
16
16
1
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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