74LVT162245ADGGRG4 [TI]
LVT SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48;![74LVT162245ADGGRG4](http://pdffile.icpdf.com/pdf2/p00228/img/icpdf/74LVT162245A_1337456_icpdf.jpg)
型号: | 74LVT162245ADGGRG4 |
厂家: | ![]() |
描述: | LVT SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
文件: | 总15页 (文件大小:790K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SN54LVT162245A, SN74LVT162245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS714D–FEBRUARY 2000–REVISED NOVEMBER 2006
FEATURES
SN54LVT162245A. . . WD PACKAGE
SN74LVT162245A. . . DGG OR DL PACKAGE
(TOP VIEW)
•
Members of the Texas Instruments Widebus™
Family
•
A-Port Outputs Have Equivalent 22-Ω Series
Resistors, So No External Resistors Are
Required
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
2
3
•
•
•
•
•
•
•
•
Supprt Mixed-Mode Signal Operation (5-V
4
Input and Output Voltages With 3.3-V VCC
)
5
Support Unregulated Battery Operation Down
to 2.7 V
6
7
V
CC
V
CC
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Ioff and Power-Up 3-State Support Hot
Insertion
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
V
CC
V
CC
ESD Protection Exceeds JESD 22
2B5
2B6
GND
2B7
2B8
2DIR
2A5
2A6
GND
2A7
2A8
2OE
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
The 'LVT162245A devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage
(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices are designed for asynchronous communication between two data buses. The logic levels of the
direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port
outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to
the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level
applied to prevent excess ICC and ICCZ
.
The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors
to reduce overshoot and undershoot.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2000–2006, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN54LVT162245A, SN74LVT162245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS714D–FEBRUARY 2000–REVISED NOVEMBER 2006
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
FBGA – GRD
SN74LVT162245AGRDR
SN74LVT162245AZRDR
SN74LVT162245ADL
Reel of 1000
Tube of 25
LZ245A
FBGA – ZRD (Pb-free)
SN74LVT162245ADLG4
SN74LVT162245ADLR
74LVT162245ADLRG4
SN74LVT162245ADGGR
74LVT162245ADGGRE4
SN74LVT162245AGQLR
SN74LVT162245AZQLR
SNJ54LVT162245AWD(2)
SSOP – DL
LVT162245A
LVT162245A
–40°C to 85°C
Reel of 1000
Reel of 2000
TSSOP – DGG
VFBGA – GQL
Reel of 1000
Tube
LZ245A
VFBGA – ZQL (Pb-free)
CFP – WD
–55°C to 125°C
SNJ54LVT162245AWD
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) Product preview
GQL OR ZQL PACKAGE
TERMINAL ASSIGNMENTS(1)
(56-Ball GQL/ZQL Package)
(TOP VIEW)
1
2 3 4 5 6
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
1DIR
1B2
1B4
1B6
1B8
2B1
2B3
2B5
2B7
2DIR
NC
NC
NC
NC
1OE
1A2
1A4
1A6
1A8
2A1
2A3
2A5
2A7
2OE
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
GND
VCC
GND
GND
VCC
GND
1A1
1A3
1A5
1A7
2A2
2A4
2A6
2A8
NC
G
H
J
GND
VCC
GND
NC
GND
VCC
GND
NC
K
K
xxx
xxx
(1) NC – No internal connection
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1B1
1B3
1B5
1B7
2B1
2B3
2B5
2B7
2B8
NC
1DIR
NC
1OE
NC
NC
1A1
1A3
1A5
1A7
2A1
2A3
2A5
2A7
2A8
A
B
C
D
1B2
1B4
1B6
1B8
2B2
2B4
2B6
NC
1A2
1A4
1A6
1A8
2A2
2A4
2A6
NC
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
E
F
G
H
J
G
H
J
2DIR
2OE
(1) NC – No internal connection
2
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SN54LVT162245A, SN74LVT162245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS714D–FEBRUARY 2000–REVISED NOVEMBER 2006
FUNCTION TABLE(1)
(EACH 8-BIT SECTION)
CONTROL INPUTS
OUTPUT CIRCUITS
OPERATION
OE
L
DIR
L
A PORT
Enabled
Hi-Z
B PORT
Hi-Z
B data to A bus
A data to B bus
Isolation
L
H
Enabled
Hi-Z
H
X
Hi-Z
(1) Input circuits of the data I/Os always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
24
1
2DIR
1DIR
48
25
13
1OE
2OE
2B1
36
47
1A1
2A1
2
1B1
To Seven Other Channels
To Seven Other Channels
3
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SN54LVT162245A, SN74LVT162245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS714D–FEBRUARY 2000–REVISED NOVEMBER 2006
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
4.6
UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high state(2)
V
7
7
V
V
V
VO
VO
–0.5 VCC + 0.5
SN54LVT162245A (B port)
96
128
30
IO
Current into any output in the low state
Current into any output in the high state(3)
SN74LVT162245A (B port)
A port
mA
mA
SN54LVT162245A (B port)
SN74LVT162245A (B port)
A port
48
IO
64
30
IIK
Input clamp current
Output clamp current
VI < 0
–50
–50
70
mA
mA
IOK
VO < 0
DGG package
DL package
63
θJA
Package thermal impedance(4)
°C/W
°C
GQL/ZQL package
GRD/ZRD package
42
36
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
SN54LVT162245A(2) SN74LVT162245A
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
VCC
VIH
VIL
VI
Supply voltage
3.6
3.6
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
–12
–24
12
0.8
5.5
–12
–32
12
A port
IOH
High-level output current
mA
mA
B port
A port
IOL
Low-level output current
B port
48
64
∆t/∆v
Input transition rise or fall rate
Outputs enabled
10
10
ns/V
µs/V
°C
∆t/∆VCC Power-up ramp rate
TA Operating free-air temperature
200
–55
200
–40
125
85
(1) All unused or driven (floating) data inputs (I/Os) of the device must be held at logic HIGH or LOW (preferably VCCI or GND) to ensure
proper device operation and minimize power. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature
number SCBA004.
(2) Product preview
4
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SN54LVT162245A, SN74LVT162245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS714D–FEBRUARY 2000–REVISED NOVEMBER 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVT162245A(1)
SN54LVT162245A
MIN TYP(2)
PARAMETER
VIK
TEST CONDITIONS
UNIT
MIN TYP(2)
MAX
MAX
VCC = 2.7 V,
II = –18 mA
IOH = –100 µA
IOH = –12 mA
IOH = –100 µA
IOH = –8 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 12 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 48 mA
IOL = 64 mA
VI = VCC or GND
VI = 5.5 V
–1.2
–1.2
V
VCC = 2.7 V to 3.6 V,
VCC = 3 V,
VCC – 0.2
VCC – 0.2
A port
B port
A port
2
VCC – 0.2
2.4
2
VCC – 0.2
2.4
VCC = 2.7 V to 3.6 V,
VCC = 2.7 V,
VOH
V
2
VCC = 3 V
2
VCC = 2.7 V to 3.6 V,
VCC = 3 V,
0.2
0.8
0.2
0.8
0.2
0.5
0.4
0.5
0.2
VCC = 2.7 V
0.5
VOL
V
0.4
B port
0.5
VCC = 3 V
0.55
0.55
±1
VCC = 3.6 V,
±1
10
20
5
Control
inputs
VCC = 0 or 3.6 V,
10
II
VI = 5.5 V
20
µA
A or B
port(3)
VCC = 3.6 V
VCC = 0,
VI = VCC
5
VI = 0
–10
–10
±100
Ioff
VI or VO = 0 to 4.5 V
µA
µA
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don't care
IOZPU
±100(4)
±100(4)
±100
±100
VCC = 1.5 to 0 V, VO = 0.5 V to 3 V,
OE = don't care
IOZPD
µA
Outputs high
VCC = 3.6 V,
0.19
5
0.19
5
ICC
IO = 0,
Outputs low
mA
VI = VCC or GND
Outputs disabled
0.19
0.19
VCC = 3 V to 3.6 V,
One input at VCC – 0.6 V,
(5)
∆ICC
0.3
0.2
mA
Other inputs at VCC or GND
Ci
VI = 3 V or 0
4
4
pF
pF
Cio
VO = 3 V or 0
10
10
(1) Product preview
(2) All typical values are at VCC = 3.3 V, TA = 25°C.
(3) Unused pins at VCC or GND
(4) On products compliant to MIL-PRF-38535, this parameter is not production tested.
(5) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
5
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SN54LVT162245A, SN74LVT162245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS714D–FEBRUARY 2000–REVISED NOVEMBER 2006
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVT162245A(1)
SN74LVT162245A
VCC = 3.3 V
± 0.3 V
MIN TYP(2) MAX MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
PARAMETER
VCC = 2.7 V
VCC = 2.7 V
UNIT
MIN
1
MAX
3.5
3.5
4.3
4.2
4.8
4.8
5.5
5.4
5.5
5.5
5.8
6.3
MIN
MAX
4
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
1
1
2.3
2.2
2.8
2.5
2.8
3
3.3
3.3
4
3.7
3.5
4.6
3.6
5.4
5.2
6.3
5.8
5.5
5.4
5.9
5.5
A
B
A
B
A
B
A
ns
ns
ns
ns
ns
ns
ns
1
3.9
5.3
4.5
5.9
5.5
7.2
6.4
5.8
5.8
6.5
6.3
1
1
B
1
1
3.4
4.6
4.6
5.3
5.1
5.2
5.1
5.6
5.5
0.5
0.5
1
1
OE
OE
OE
OE
1
1
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
tsk(LH)
tsk(HL)
1
1
3.3
3.3
3.8
3.5
4
1
1
1.5
1.5
1.5
1.2
1.5
1.5
1.5
1.5
3.8
(1) Product preview
(2) All typical values are at VCC = 3.3 V, TA = 25°C.
6
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SN54LVT162245A, SN74LVT162245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS714D–FEBRUARY 2000–REVISED NOVEMBER 2006
PARAMETER MEASUREMENT INFORMATION
6 V
Open
GND
S1
TEST
S1
500 Ω
From Output
Under Test
t
/t
Open
6 V
GND
PLH PHL
t
t
/t
PLZ PZL
C = 50 pF
L
/t
500 Ω
PHZ PZH
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
0 V
V
t
t
t
PHL
t
t
PLZ
PLH
PZL
Output
Waveform 1
S1 at 6 V
3 V
OH
1.5 V
1.5 V
1.5 V
Output
1.5 V
V
OL
+ 0.3 V
V
OL
V
OL
(see Note B)
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2013
PACKAGING INFORMATION
Orderable Device
74LVT162245ADGGRE4
74LVT162245ADGGRG4
74LVT162245ADLRG4
SN74LVT162245ADGGR
SN74LVT162245ADL
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
TSSOP
TSSOP
SSOP
TSSOP
SSOP
SSOP
SSOP
DGG
48
48
48
48
48
48
48
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
LVT162245A
ACTIVE
ACTIVE
DGG
DL
2000
1000
2000
25
Green (RoHS
& no Sb/Br)
LVT162245A
LVT162245A
LVT162245A
LVT162245A
LVT162245A
LVT162245A
LZ245A
Green (RoHS
& no Sb/Br)
ACTIVE
DGG
DL
Green (RoHS
& no Sb/Br)
ACTIVE
Green (RoHS
& no Sb/Br)
SN74LVT162245ADLG4
SN74LVT162245ADLR
SN74LVT162245AGQLR
ACTIVE
DL
25
Green (RoHS
& no Sb/Br)
ACTIVE
DL
1000
Green (RoHS
& no Sb/Br)
OBSOLETE
BGA
GQL
TBD
MICROSTAR
JUNIOR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2013
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVT162245ADGGR TSSOP
SN74LVT162245ADLR SSOP
DGG
DL
48
48
2000
1000
330.0
330.0
24.4
32.4
8.6
15.8
1.8
3.1
12.0
16.0
24.0
32.0
Q1
Q1
11.35 16.2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVT162245ADGGR
SN74LVT162245ADLR
TSSOP
SSOP
DGG
DL
48
48
2000
1000
367.0
367.0
367.0
367.0
45.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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