74LTV543MSA [TI]
LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, SSOP-24;型号: | 74LTV543MSA |
厂家: | TEXAS INSTRUMENTS |
描述: | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, SSOP-24 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
文件: | 总2页 (文件大小:64K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
February 1996
74LVT543
3.3V ABT Octal Registered Transceiver
with TRI-STATE Outputs
É
General Description
Features
Y
Input and output interface capability to systems at 5V
V
The ’LVT543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either direc-
tion. Separate Latch Enable and Output Enable inputs are
provided for each register to permit independent control of
inputting and outputting in either direction of data flow.
CC
Y
Bus-Hold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
Y
Live insertion/extraction permitted
Y
These octal registered transceivers is/are designed for low-
applications, but with the capability to
Power Up/Down high impedance provides glitch-free
bus loading
voltage (3.3V) V
CC
Y
provide a TTL interface to a 5V environment. The LVT543 is
fabricated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintaining a
low power dissipation.
b
a
Outputs source/sink 32 mA/ 64 mA
Available in SOIC JEDEC and TSSOP
Functionally compatible with the 74 series 543
Latch-up performance exceeds 500 mA
Y
Y
Y
Pin Descriptions
Connection Diagram
Pin Assignment
for SOIC, SSOP II and TSSOP
Pin Names
Description
OEAB, OEBA
LEAB, LEBA
CEAB, CEBA
Output Enable Inputs
Latch Enable Inputs
Chip Enable Inputs
Side A Inputs or
A –A
0
7
TRI-STATE Outputs
Side B Inputs or
B –B
0
7
TRI-STATE Outputs
TL/F/12448–1
SOIC JEDEC
TSSOP
SSOP II
Order Number
74LVT543WM
74LVT543MTC
74LVT543MTCX
74LTV543MSA
74LTV543MSAX
74LVT543WMX
See NS Package
Number
M24B
MTC24
MSA24
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation
TL/F/12448
RRD-B30M17/Printed in U. S. A.
http://www.national.com
Functional Description
The ’LVT543 contains two sets of D-type latches, with sepa-
rate input and output controls for each. For data flow from A
to B, for example, the A to B Enable (CEAB) input must be
low in order to enter data from the A port or take data from
the B port as indicated in the Data I/O Control Table. With
CEAB low, a low signal on (LEAB) input makes the A to B
latches transparent; a subsequent low to high transition of
the LEAB line puts the A latches in the storage mode and
their outputs no longer change with the A inputs. With CEAB
and OEAB both low, the B output buffers are active and
reflect the data present on the output of the A latches. Con-
trol of data flow from B to A is similar, but using the CEBA,
LEBA and OEBA.
Data I/O Control Table
Inputs
CEAB LEAB OEAB
Latch Status Output Buffers
H
X
L
X
H
L
X
X
X
H
L
Latched
Latched
Transparent
Ð
High Z
Ð
Ð
X
L
X
X
High Z
Driving
Ð
e
e
e
H
L
High Voltage Level
Low Voltage Level
Immaterial
X
Logic Diagram
TL/F/12448–2
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