74GTLPH1612DGGRG4_技术文档

SN74GTLPH1612

18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE

UNIVERSAL BUS TRANSCEIVER

www.ti.com

SCES287D–OCTOBER 1999–REVISED MAY 2005

FEATURES

DGG PACKAGE

(TOP VIEW)

•

Member of the Texas Instruments Widebus™

Family

OEAB

LEAB

A1

A2

GND

A3

CEAB

CLKAB

B1

B2

GND

B3

1

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

•

UBT™ Transceiver Combines D-Type Latches

and D-Type Flip-Flops for Operation in

Transparent, Latched, Clocked, or

Clock-Enabled Modes

2

3

4

5

•

TI-OPC™ Circuitry Limits Ringing on

Unevenly Loaded Backplanes

6

V

CC

BIAS V

7

CC

OEC™ Circuitry Improves Signal Integrity and

Reduces Electromagnetic Interference

A4

A5

GND

A6

A7

A8

B4

B5

GND

B6

B7

8

9

Bidirectional Interface Between GTLP Signal

Levels and LVTTL Logic Levels

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

•

LVTTL Interfaces Are 5-V Tolerant

High-Drive GTLP Outputs (100 mA)

LVTTL Outputs (–24 mA/24 mA)

B8

GND

A9

GND

B9

Variable Edge-Rate Control (ERC) Input

Selects GTLP Rise and Fall Times for Optimal

Data-Transfer Rate and Signal Integrity in

Distributed Loads

V

CC

V

CC

A10

GND

A11

A12

GND

A13

A14

GND

A15

B10

GND

B11

B12

GND

B13

B14

GND

B15

•

I_off, Power-Up 3-State, and BIAS V_CCSupport

Live Insertion

•

Bus Hold on A-Port Data Inputs

Distributed V_CCand GND Pins Minimize

High-Speed Switching Noise

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

V

CC

V

REF

A16

ERC

A17

B16

GND

B17

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

A18 30

35 B18

– 1000-V Charged-Device Model (C101)

OEBA 31

34 CLKBA

LEBA

CEBA

32

33

DESCRIPTION

The SN74GTLPH1612 is

a high-drive, 18-bit UBT™ transceiver that provides LVTTL-to-GTLP and

GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or clock-enabled modes of

data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a

backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL)

backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels,

improved differential input, OEC™ circuitry, and TI-OPC™circuitry. Improved GTLP OEC and TI-OPC circuits

minimize bus-settling time and have been designed and tested using several backplane models. The high drive

allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 11 Ω.

GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard

JESD 8-3. The ac specification of the SN74GTLPH1612 is given only at the preferred higher noise margin GTLP,

but the user has the flexibility of using this device at either GTL (V_TT= 1.2 V and V_REF= 0.8 V) or GTLP

(V_TT= 1.5 V and V_REF= 1 V) signal levels.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, UBT, TI-OPC, OEC, TI are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SN74GTLPH1612

18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE

UNIVERSAL BUS TRANSCEIVER

www.ti.com

SCES287D–OCTOBER 1999–REVISED MAY 2005

DESCRIPTION (CONTINUED)

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,

but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V_REFis the B-port differential input

reference voltage.

This device is fully specified for live-insertion applications using I_off, power-up 3-state, and BIAS V_CC. The I_off

circuitry disables the outputs, preventing damaging current backflow through the device when it is powered

down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power

down, which prevents driver conflict. The BIAS V_CCcircuitry precharges and preconditions the B-port input/output

connections, preventing disturbance of active data on the backplane during card insertion or removal, and

permits true live-insertion capability.

This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated

backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal

integrity, which allows adequate noise margin to be maintained at higher frequencies.

High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC

input voltage between GND and V_CCadjusts the B-port output rise and fall times. This allows the designer to

optimize system data-transfer rate and signal integrity to the backplane load.

Active bus-hold circuitry is provided to hold unused or undriven LVTTL data inputs at a valid logic state. Use of

pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When V_CCis between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V_CC

through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the

driver.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

–40°C to 85°C

TSSOP – DGG

Tape and reel

SN74GTLPH1612DGGR

GTLPH1612

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

2

SN74GTLPH1612

18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE

UNIVERSAL BUS TRANSCEIVER

www.ti.com

SCES287D–OCTOBER 1999–REVISED MAY 2005

FUNCTIONAL DESCRIPTION

The SN74GTLPH1612 is a high-drive (100 mA), 18-bit UBT transceiver containing D-type latches and D-type

flip-flops for data-path operation in transparent, latched, clocked, or clock-enabled modes and can replace any of

the functions shown in Table 1. Data polarity is noninverting.

Table 1. SN74GTLPH1612 UBT Transceiver Replacement Functions

FUNCTION

8 BIT

'245, '623, '645

'241, '244, '541

'543

9 BIT

10 BIT

'861

16 BIT

'16245, '16623

'16241, '16244, '16541

'16543

18 BIT

'16863

'16825

'16472

'16843

'16474

Transceiver

Buffer/driver

'863

'827

Latched transceiver

Latch

'373, '573

'646, '652

'374, '574

'843

'841

'821

'16373

Registered transceiver

Flip-flop

'16646, '16652

'16374

Standard UBT

'16500, '16501

'16835

Universal bus driver

Registered transceiver with clock enable

Flip-flop with clock enable

Standard UBT with clock enable

'2952

'377

'16470, '16952

'823

'16823

'16600, '16601

SN74GTLPH1612 UBT transceiver replaces all above functions

xxx

Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and

LEBA), clock (CLKAB and CLKBA), and output enables (OEAB and OEBA). CEAB and CEBA and OEAB and

OEBA control the 18 bits of data for the A-to-B and B-to-A directions, respectively.

For A-to-B data flow, when CEAB is low, the device operates on the low-to-high transition of CLKAB for the

flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB and LEAB are low, the A data is

latched, regardless of the state of CLKAB (high or low) and if LEAB is high, the device is in transparent mode.

When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.

The data flow for B to A is similar to that of A to B, except that CEBA, OEBA, LEBA, and CLKBA are used.

FUNCTION TABLES

SPACE HOLDER

OUTPUT ENABLE⁽¹⁾

INPUTS

OUTPUT

B

MODE

Isolation

CEAB

OEAB

LEAB

CLKAB

A

X

L

X

L

H

L

X

L

X

H

L

Z

(2)

B₀

Latched storage of A data

(3)

L

B₀

X

L

H

L

X

↑

L

H

L

True transparent

H

L

Clocked storage of A data

Clock inhibit

L

↑

H

X

H

(3)

H

L

X

B₀

(1) A-to-B data flow is shown: B-to-A data flow is similar, but uses CEBA, OEBA, LEBA, and CLKBA.

The condition when OEAB and OEBA are both low at the same time is not recommended.

(2) Output level before the indicated steady-state input conditions were established, provided that

CLKAB was high before LEAB went low

(3) Output level before the indicated steady-state input conditions were established

3

SN74GTLPH1612

18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE

UNIVERSAL BUS TRANSCEIVER

www.ti.com

SCES287D–OCTOBER 1999–REVISED MAY 2005

B-PORT EDGE-RATE CONTROL (ERC)

INPUT ERC

OUTPUT

B-PORT

EDGE RATE

LOGIC

LEVEL

NOMINAL

VOLTAGE

L

GND

V_CC

Slow

Fast

H

LOGIC DIAGRAM (POSITIVE LOGIC)

39

28

1

V

REF

ERC

OEAB

CEAB

64

63

CLKAB

LEAB

LEBA

2

32

34

33

31

3

CLKBA

CEBA

OEBA

A1

CE

1D

62

B1

C1

CLK

CE

1D

C1

CLK

To 17 Other Channels

4

SN74GTLPH1612

18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE

UNIVERSAL BUS TRANSCEIVER

www.ti.com

SCES287D–OCTOBER 1999–REVISED MAY 2005

Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT

V_CC

Supply voltage range

BIAS V_CC

–0.5

4.6

V

A-port, ERC, and control inputs

–0.5

7

4.6

7

V_I

Input voltage range⁽²⁾

B port and V_REF

A port

Voltage range applied to any output in the

high-impedance or power-off state⁽²⁾

V_O

V

B port

4.6

48

A port

I_O

Current into any output in the low state

mA

B port

200

48

Current into any A-port output in the high state⁽³⁾

Continuous current through each V_CCor GND

Input clamp current

mA

±100

–50

I_IK

V_I< 0

I_OK

θ_JA

T_stg

Output clamp current

Package thermal impedance⁽⁴⁾

V_O< 0

55 °C/W

150 °C

Storage temperature range

–65

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3) This current flows only when the output is in the high state and V_O> V_CC

.

(4) The package thermal impedance is calculated in accordance with JESD 51-7.

5

SN74GTLPH1612

18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE

UNIVERSAL BUS TRANSCEIVER

www.ti.com

SCES287D–OCTOBER 1999–REVISED MAY 2005

Recommended Operating Conditions^(1)(2)(3)(4)

MIN NOM

MAX UNIT

V_CC

BIAS V_CC

,

Supply voltage

3.15

3.3

3.45

V

GTL

1.14

1.35

0.74

0.87

1.2

1.5

0.8

1

1.26

1.65

0.87

1.1

V_TT

Termination voltage

GTLP

GTL

V_REF

Reference voltage

Input voltage

V

GTLP

B port

V_TT

5.5

V_I

Except B port

V_CC

B port

V_REF+ 0.05

V_CC– 0.6

2

V_IH

High-level input voltage

Low-level input voltage

ERC

V_CC

5.5

V

Except B port and ERC

B port

V_REF– 0.05

V_IL

ERC

GND

0.6

0.8

–18

–24

24

Except B port and ERC

I_IK

Input clamp current

mA

I_OH

High-level output current

A port

I_OL

Low-level output current

mA

B port

100

10

∆t/∆v

∆t/∆V_CC

T_A

Input transition rise or fall rate

Power-up ramp rate

Outputs enabled

ns/V

µs/V

°C

20

Operating free-air temperature

–40

85

(1) All unused inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

(2) Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V_CC= 3.3 V first, I/O second, and V_CC= 3.3 V

last, because the BIAS V_CCprecharge circuitry is disabled when any V_CCpin is connected. The control and V_REFinputs can be

connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is

acceptable, but generally, GND is connected first.

(3) V_TTand R_TTcan be adjusted to accommodate backplane impedances if the dc recommended I_OLratings are not exceeded.

(4) V_REFcan be adjusted to optimize noise margins, but normally is two-thirds V_TT. TI-OPC circuitry is enabled in the A-to-B direction and is

activated when V_TT> 0.7 V above V_REF. If operated in the A-to-B direction, V_REFshould be set to within 0.6 V of V_TTto minimize current

drain.

6

SN74GTLPH1612

18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE

UNIVERSAL BUS TRANSCEIVER

www.ti.com

SCES287D–OCTOBER 1999–REVISED MAY 2005

Electrical Characteristics

over recommended operating free-air temperature range for GTLP (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP⁽¹⁾

MAX

UNIT

V_IK

V_CC= 3.15 V,

I_I= –18 mA

I_OH= –100 µA

I_OH= –12 mA

I_OH= –24 mA

I_OL= 100 µA

I_OL= 12 mA

I_OL= 24 mA

I_OL= 10 mA

I_OL= 64 mA

I_OL= 100 mA

V_I= 0 or 5.5 V

V_O= V_CC

–1.2

V

V_CC= 3.15 V to 3.45 V,

V_CC– 0.2

V_OH

A port

2.4

2

V

V_CC= 3.15 V

V_CC= 3.15 V to 3.45 V,

V_CC= 3.15 V

0.2

0.4

0.5

0.2

0.4

0.55

±10

10

A port

V_OL

V

B port

V_CC= 3.15 V

I_I

Control inputs

V_CC= 3.45 V,

V_CC= 3.45 V

µA

A port

(2)

I_OZH

B port

V_O= 1.5 V

10

(2)

(3)

(4)

I_OZL

I_BHL

I_BHH

A and B ports

A port

V_CC= 3.45 V,

V_CC= 3.15 V,

V_CC= 3.45 V,

V_O= GND

–10

µA

V_I= 0.8 V

75

–75

A port

V_I= 2 V

(5)

(6)

I_BHLO

I_BHHO

A port

V_I= 0 to V_CC

Outputs high

Outputs low

Outputs disabled

500

A port

–500

45

V_CC= 3.45 V, I_O= 0,

V_I(A-port or control input) = V_CCor GND,

V_I(B port) = V_TTor GND

I_CC

A or B port

mA

V_CC= 3.45 V, One A-port or control input at V_CC– 0.6 V,

Other A-port or control inputs at V_CCor GND

(7)

∆I_CC

1.5

mA

pF

C_i

Control inputs

A port

V_I= 3.15 V or 0

V_O= 3.15 V or 0

V_O= 1.5 V or 0

4

6.5

9.5

5.5

8

C_io

pF

B port

11.5

(1) All typical values are at V_CC= 3.3 V, T_A= 25°C.

(2) For I/O ports, the parameters I_OZHand I_OZLinclude the input leakage current.

(3) The bus-hold circuit can sink at least the minimum low sustaining current at V_ILmax. I_BHLshould be measured after lowering V_INto GND

and then raising it to V_ILmax.

(4) The bus-hold circuit can source at least the minimum high sustaining current at V_IHmin. I_BHHshould be measured after raising V_INto V_CC

and then lowering it to V_IHmin.

(5) An external driver must source at least I_BHLOto switch this node from low to high.

(6) An external driver must sink at least I_BHHOto switch this node from high to low.

(7) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V_CCor GND.

Hot-Insertion Specifications for A Port

over recommended operating free-air temperature range

PARAMETER

I_off

TEST CONDITIONS

BIAS V_CC= 0,

MIN

MAX UNIT

V_CC= 0,

V_Ior V_O= 0 to 5.5 V

OE = 0

10

±30

µA

I_OZPU

V_CC= 0 to 1.5 V,

V_CC= 1.5 V to 0,

V_O= 0.5 V to 3 V,

I_OZPD

OE = 0

7

SN74GTLPH1612

18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE

UNIVERSAL BUS TRANSCEIVER

www.ti.com

SCES287D–OCTOBER 1999–REVISED MAY 2005

Live-Insertion Specifications for B Port

over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

I_off

V_CC= 0,

BIAS V_CC= 0,

V_Ior V_O= 0 to 1.5 V

10

±30

5

µA

mA

µA

V

I_OZPU

I_OZPD

V_CC= 0 to 1.5 V,

V_CC= 1.5 V to 0,

V_CC= 0 to 3.15 V

V_CC= 3.15 V to 3.45 V

V_CC= 0,

V_O= 0.5 V to 1.5 V, OE = 0

I_CC(BIAS V_CC

)

BIAS V_CC= 3.15 V to 3.45 V, V_O(B port) = 0 to 1.5 V

10

V_O

I_O

BIAS V_CC= 3.3 V,

I_O= 0

0.95

–1

1.05

V_CC= 0,

BIAS V_CC= 3.15 V to 3.45 V, V_O(B port) = 0.6 V

µA

Timing Requirements

over recommended ranges of supply voltage and operating free-air temperature,

V_TT= 1.5 V and V_REF= 1 V for GTLP (normal mode) (unless otherwise noted)

MIN

MAX UNIT

f_clock

t_w

Clock frequency

Pulse duration

175

MHz

LEAB or LEBA high

3

ns

CLKAB or CLKBA high or low

A before CLKAB↑

2.2

2.4

1.8

2.1

1.5

0.7

0.5

1.2

0.9

1.5

B before CLKBA↑

A before LEAB↓, CLK = Don't care

B before LEBA↓, CLK = Don't care

CEAB before CLKAB↑

CEBA before CLKBA↑

A after CLKAB↑

t_su

Setup time

ns

B after CLKBA↑

A after LEAB↓, CLK = Don't care

B after LEBA↓, CLK = Don't care

CEAB after CLKAB↑

t_h

Hold time

CEBA after CLKBA↑

8

SN74GTLPH1612

18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE

UNIVERSAL BUS TRANSCEIVER

www.ti.com

SCES287D–OCTOBER 1999–REVISED MAY 2005

Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature,

V_TT= 1.5 V and V_REF= 1 V for GTLP (normal mode) (see Figure 1)

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

EDGE RATE⁽¹⁾

MIN TYP⁽²⁾

MAX UNIT

f_max

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_en

175

MHz

4.2

3

5.6

4.4

4.3

3.8

6.1

4.7

4.8

4.2

6.2

4.7

4.9

4.2

4.6

6

7.1

ns

A

B

Slow

Fast

Slow

Fast

Slow

Fast

Slow

Fast

6.3

3

5.7

ns

A

2.6

4.6

3.3

3.4

3

5.3

7.7

ns

LEAB

CLKAB

OEAB

6.5

6.2

ns

5.7

4.7

3.2

3.5

2.9

3

7.7

ns

6.4

6.2

ns

5.6

6.5

ns

t_dis

4.6

2.7

3.4

7.5

t_en

4.1

4.8

2.5

1.3

3.3

2.5

2.9

3

5.6

ns

t_dis

6.2

Slow

Fast

Slow

Fast

t_r

t_f

Rise time, B outputs (20% to 80%)

Fall time, B outputs (80% to 20%)

ns

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_en

1.3

1.6

1.5

1.2

2.3

4.6

ns

B

A

4.2

3.2

3

4.6

ns

LEBA

CLKBA

OEBA

3.9

3.3

3

4.8

ns

4.2

2.5

3.8

5

ns

t_dis

5.5

(1) Slow (ERC = GND) and Fast (ERC = V_CC

)

(2) All typical values are at V_CC= 3.3 V, T_A= 25°C.

9

SN74GTLPH1612

18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE

UNIVERSAL BUS TRANSCEIVER

www.ti.com

SCES287D–OCTOBER 1999–REVISED MAY 2005

PARAMETER MEASUREMENT INFORMATION

1.5 V

6 V

Open

GND

S1

500 Ω

12.5 Ω

From Output

Under Test

TEST

/t

S1

Open

6 V

From Output

Under Test

Test

Point

t

PLH PHL

t

/t

C = 50 pF

(see Note A)

PLZ PZL

L

500 Ω

/t

GND

C = 30 pF

L

PHZ PZH

(see Note A)

LOAD CIRCUIT FOR A OUTPUTS

LOAD CIRCUIT FOR B OUTPUTS

t

w

3 V

0 V

Timing

Input

1.5 V

Input

0 V

t

su

t

h

VOLTAGE WAVEFORMS

PULSE DURATION

V

OH

Data

Input

V

M

V

M

0 V

3 V

0 V

Input

1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

(V = 1.5 V for A port and 1 V for B port)

(V = 3 V for A port and 1.5 V for B port)

OH

M

t

PHL

PLH

V

OH

Output

1 V

3 V

Output

Control

OL

1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

(A port to B port)

0 V

t

PLZ

PZL

Output

Waveform 1

S1 at 6 V

3 V

V

1.5 V

0 V

1.5 V

1 V

V

OL

+ 0.3 V

Input

OL

(see Note B)

t

PZH

PHZ

t

PHL

PLH

Output

Waveform 2

S1 at GND

V

OH

V

OH

V

OH

− 0.3 V

1.5 V

Output

≈0 V

(see Note B)

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

(B port to A port)

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

(A port)

NOTES: A. C includes probe and jig capacitance.

L

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z = 50 Ω, t ≈ 2 ns, t ≈ 2 ns.

O

r

f

D. The outputs are measured one at a time, with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

10

SN74GTLPH1612

18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE

UNIVERSAL BUS TRANSCEIVER

www.ti.com

SCES287D–OCTOBER 1999–REVISED MAY 2005

Distributed-Load Backplane Switching Characteristics

The preceding switching characteristics table shows the switching characteristics of the device into a lumped

load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical

representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a

resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum

performance in this RLC circuit. The following switching characteristics table shows the switching characteristics

of the device into the RLC load, to help the designer better understand the performance of the GTLP device in

this typical backplane. See www.ti.com/sc/gtlp for more information.

1.5 V

Z

O

= 50 Ω

0.25”

1”

0.25

”

Conn.

1”

Rcvr

Drvr

Slot 1

Slot 2

Slot 19

Slot 20

Figure 2. High-Drive Test Backplane

1.5 V

11 Ω

L = 14 nH

L

From Output

Under Test

Test

Point

C = 18 pF

L

Figure 3. High-Drive RLC Network

11

SN74GTLPH1612

18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE

UNIVERSAL BUS TRANSCEIVER

www.ti.com

SCES287D–OCTOBER 1999–REVISED MAY 2005

Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature,

V_TT= 1.5 V and V_REF= 1 V for GTLP (see Figure 3)

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

EDGE RATE⁽¹⁾

TYP⁽²⁾UNIT

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_en

5.3

ns

A

B

Slow

5.3

4

A

Fast

Slow

Fast

Slow

Fast

Slow

Fast

ns

4

5.2

ns

LEAB

CLK

OEAB

5.2

3.9

ns

3.9

5.5

ns

5.5

4.3

ns

4.3

5.7

ns

t_dis

4.3

t_en

4.3

ns

t_dis

3.8

Slow

Fast

Slow

Fast

2

t_r

t_f

Rise time, B outputs (20% to 80%)

ns

1.2

2.5

ns

Fall time, B outputs (80% to 20%)

1.8

(1) Slow (ERC = GND) and Fast (ERC = V_CC

)

(2) All typical values are at V_CC= 3.3 V, T_A= 25°C. All values are derived from TI-SPICE models.

12

PACKAGE OPTION ADDENDUM

www.ti.com

27-Sep-2007

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

74GTLPH1612DGGRE4

74GTLPH1612DGGRG4

SN74GTLPH1612DGGR

TSSOP

DGG

64

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

DGG

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

SN74GTLPH1612DGGR TSSOP

DGG

64

2000

330.0

24.4

8.4

17.3

1.7

12.0

24.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP DGG 64

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 41.0

SN74GTLPH1612DGGR

2000

Pack Materials-Page 2

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27

0,17

M

0,08

0,50

48

25

6,20

6,00

8,30

7,90

0,15 NOM

Gage Plane

0,25

1

24

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

48

56

64

DIM

A MAX

12,60

12,40

14,10

13,90

17,10

16,90

A MIN

4040078/F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	74GTLPH1612DGGRG4
厂家：	TEXAS INSTRUMENTS
描述：	GTLP SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO64, GREEN, PLASTIC, TSSOP-64 光电二极管输出元件逻辑集成电路触发器
文件：	总17页 (文件大小：336K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74GTLPH1612DGGRG4 [TI]

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